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drm/amd/pm: correct the fan speed RPM retrieving
[linux-block.git] / drivers / gpu / drm / amd / pm / swsmu / smu11 / sienna_cichlid_ppt.c
CommitLineData
b455159c
LG		 1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
d8e0b16d
EQ		 24#define SWSMU_CODE_LAYER_L2
25
b455159c
LG		 26#include <linux/firmware.h>
27#include <linux/pci.h>
bc50ca29 28#include <linux/i2c.h>
b455159c
LG		 29#include "amdgpu.h"
30#include "amdgpu_smu.h"
b455159c
LG		 31#include "atomfirmware.h"
32#include "amdgpu_atomfirmware.h"
22f2447c 33#include "amdgpu_atombios.h"
b455159c
LG		 34#include "smu_v11_0.h"
35#include "smu11_driver_if_sienna_cichlid.h"
36#include "soc15_common.h"
37#include "atom.h"
38#include "sienna_cichlid_ppt.h"
e05acd78 39#include "smu_v11_0_7_pptable.h"
b455159c 40#include "smu_v11_0_7_ppsmc.h"
40d3b8db 41#include "nbio/nbio_2_3_offset.h"
b7d25b5f 42#include "nbio/nbio_2_3_sh_mask.h"
e05acd78
LG		 43#include "thm/thm_11_0_2_offset.h"
44#include "thm/thm_11_0_2_sh_mask.h"
ea8139d8
WS		 45#include "mp/mp_11_0_offset.h"
46#include "mp/mp_11_0_sh_mask.h"
b455159c 47
6c339f37
EQ		 48#include "asic_reg/mp/mp_11_0_sh_mask.h"
49#include "smu_cmn.h"
50
55084d7f
EQ		 51/*
52 * DO NOT use these for err/warn/info/debug messages.
53 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
54 * They are more MGPU friendly.
55 */
56#undef pr_err
57#undef pr_warn
58#undef pr_info
59#undef pr_debug
60
bc50ca29
AD		 61#define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
62
b455159c
LG		 63#define FEATURE_MASK(feature) (1ULL << feature)
64#define SMC_DPM_FEATURE ( \
65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
fea905d4 66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65297d50 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
5cb74353 68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
4cd4f45b 69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
5f338f70 70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
ce7e5a6e
JC		 71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \
72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
b455159c 73
d817f375
LG		 74#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
75
7077b19a
CG		 76#define GET_PPTABLE_MEMBER(field, member) do {\
77 if (smu->adev->asic_type == CHIP_BEIGE_GOBY)\
78 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
79 else\
80 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
81} while(0)
82
83static int get_table_size(struct smu_context *smu)
84{
85 if (smu->adev->asic_type == CHIP_BEIGE_GOBY)
86 return sizeof(PPTable_beige_goby_t);
87 else
88 return sizeof(PPTable_t);
89}
90
6c339f37
EQ		 91static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
92 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
93 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
94 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
91190db1
LG		 95 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
96 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
97 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
98 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
6c339f37
EQ		 99 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
100 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
101 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
102 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
103 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
104 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
105 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
91190db1 106 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
4215a119
HC		 107 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
108 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
91190db1
LG		 109 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
110 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
4215a119 111 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
91190db1
LG		 112 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
113 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
66b8a9c0 114 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
91190db1 115 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
4215a119
HC		 116 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
117 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
6c339f37 118 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
91190db1 119 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
6c339f37
EQ		 120 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
121 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
122 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
91190db1
LG		 123 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
124 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
125 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
126 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
127 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
128 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
129 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
130 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
6c339f37 131 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
91190db1
LG		 132 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
133 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
134 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
6c339f37 135 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
91190db1
LG		 136 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
137 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
138 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
139 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
140 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
141 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
142 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
143 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
05f39286 144 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
76c71f00 145 MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0),
ac7804bb 146 MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0),
88dfd5d5 147 MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0),
b455159c
LG		 148};
149
6c339f37 150static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
b455159c
LG		 151 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
152 CLK_MAP(SCLK, PPCLK_GFXCLK),
153 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
154 CLK_MAP(FCLK, PPCLK_FCLK),
155 CLK_MAP(UCLK, PPCLK_UCLK),
156 CLK_MAP(MCLK, PPCLK_UCLK),
157 CLK_MAP(DCLK, PPCLK_DCLK_0),
9c0551f2
JC		 158 CLK_MAP(DCLK1, PPCLK_DCLK_1),
159 CLK_MAP(VCLK, PPCLK_VCLK_0),
b455159c
LG		 160 CLK_MAP(VCLK1, PPCLK_VCLK_1),
161 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
162 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
163 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
164 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
165};
166
6c339f37 167static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
b455159c
LG		 168 FEA_MAP(DPM_PREFETCHER),
169 FEA_MAP(DPM_GFXCLK),
31cb0dd9 170 FEA_MAP(DPM_GFX_GPO),
b455159c 171 FEA_MAP(DPM_UCLK),
e9073b43 172 FEA_MAP(DPM_FCLK),
b455159c
LG		 173 FEA_MAP(DPM_SOCCLK),
174 FEA_MAP(DPM_MP0CLK),
175 FEA_MAP(DPM_LINK),
176 FEA_MAP(DPM_DCEFCLK),
e9073b43 177 FEA_MAP(DPM_XGMI),
b455159c
LG		 178 FEA_MAP(MEM_VDDCI_SCALING),
179 FEA_MAP(MEM_MVDD_SCALING),
180 FEA_MAP(DS_GFXCLK),
181 FEA_MAP(DS_SOCCLK),
e9073b43 182 FEA_MAP(DS_FCLK),
b455159c
LG		 183 FEA_MAP(DS_LCLK),
184 FEA_MAP(DS_DCEFCLK),
185 FEA_MAP(DS_UCLK),
186 FEA_MAP(GFX_ULV),
187 FEA_MAP(FW_DSTATE),
188 FEA_MAP(GFXOFF),
189 FEA_MAP(BACO),
6fb176a7 190 FEA_MAP(MM_DPM_PG),
b455159c
LG		 191 FEA_MAP(RSMU_SMN_CG),
192 FEA_MAP(PPT),
193 FEA_MAP(TDC),
194 FEA_MAP(APCC_PLUS),
195 FEA_MAP(GTHR),
196 FEA_MAP(ACDC),
197 FEA_MAP(VR0HOT),
198 FEA_MAP(VR1HOT),
199 FEA_MAP(FW_CTF),
200 FEA_MAP(FAN_CONTROL),
201 FEA_MAP(THERMAL),
202 FEA_MAP(GFX_DCS),
203 FEA_MAP(RM),
204 FEA_MAP(LED_DISPLAY),
205 FEA_MAP(GFX_SS),
206 FEA_MAP(OUT_OF_BAND_MONITOR),
207 FEA_MAP(TEMP_DEPENDENT_VMIN),
208 FEA_MAP(MMHUB_PG),
209 FEA_MAP(ATHUB_PG),
cf06331f 210 FEA_MAP(APCC_DFLL),
b455159c
LG		 211};
212
6c339f37 213static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
b455159c
LG		 214 TAB_MAP(PPTABLE),
215 TAB_MAP(WATERMARKS),
216 TAB_MAP(AVFS_PSM_DEBUG),
217 TAB_MAP(AVFS_FUSE_OVERRIDE),
218 TAB_MAP(PMSTATUSLOG),
219 TAB_MAP(SMU_METRICS),
220 TAB_MAP(DRIVER_SMU_CONFIG),
221 TAB_MAP(ACTIVITY_MONITOR_COEFF),
222 TAB_MAP(OVERDRIVE),
223 TAB_MAP(I2C_COMMANDS),
224 TAB_MAP(PACE),
225};
226
6c339f37 227static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
1d5ca713
LG		 228 PWR_MAP(AC),
229 PWR_MAP(DC),
230};
231
6c339f37 232static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
b455159c
LG		 233 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
234 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
235 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
236 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
237 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
4c4d5a49 238 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
b455159c
LG		 239 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
240};
241
f06d9511
GS		 242static const uint8_t sienna_cichlid_throttler_map[] = {
243 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
244 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
245 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
246 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
247 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
248 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
249 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
250 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
251 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
252 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
253 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
254 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
255 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
256 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
257 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
258 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
259 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
260 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
261};
262
b455159c
LG		 263static int
264sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
265 uint32_t *feature_mask, uint32_t num)
266{
fea905d4
LG		 267 struct amdgpu_device *adev = smu->adev;
268
b455159c
LG		 269 if (num > 2)
270 return -EINVAL;
271
272 memset(feature_mask, 0, sizeof(uint32_t) * num);
273
4cd4f45b 274 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
15dbe18f 275 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
ce7e5a6e 276 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
094cdf15 277 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
5f338f70 278 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
86a9eb3f 279 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
80c36f86 280 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
9aa60213
LG		 281 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
282 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
d28f4aa1 283 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
20d71dcc 284 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
d0d71970 285 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
886c8bc6
LG		 286 | FEATURE_MASK(FEATURE_PPT_BIT)
287 | FEATURE_MASK(FEATURE_TDC_BIT)
3fc006f5 288 | FEATURE_MASK(FEATURE_BACO_BIT)
cf06331f 289 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
35ed946c 290 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
1c58d429 291 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
b971df70
LG		 292 | FEATURE_MASK(FEATURE_THERMAL_BIT)
293 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
fea905d4 294
c96721eb 295 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
fea905d4 296 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
c96721eb
KF		 297 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
298 }
fea905d4 299
680602d6
KF		 300 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
301 (adev->asic_type > CHIP_SIENNA_CICHLID) &&
302 !(adev->flags & AMD_IS_APU))
303 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
304
65297d50 305 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
fc17cd3f
LG		 306 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
307 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
308 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
65297d50 309
5cb74353
LG		 310 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
312
5f338f70
LG		 313 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
315
fea905d4
LG		 316 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
b455159c 318
62c1ea6b
LG		 319 if (adev->pm.pp_feature & PP_ULV_MASK)
320 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
321
02bb391d
LG		 322 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
323 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
324
e0da123a
LG		 325 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
327
b794616d
KF		 328 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
329 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
330
846938c2
KF		 331 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
332 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
333
6fb176a7
LG		 334 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
335 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
336 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
337
62826b86
KF		 338 if (smu->dc_controlled_by_gpio)
339 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
340
0064b0ce 341 if (amdgpu_aspm)
6ef28889
KF		 342 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
343
b455159c
LG		 344 return 0;
345}
346
458020dd 347static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
b455159c 348{
4a13b4ce 349 struct smu_table_context *table_context = &smu->smu_table;
e05acd78 350 struct smu_11_0_7_powerplay_table *powerplay_table =
4a13b4ce
EQ		 351 table_context->power_play_table;
352 struct smu_baco_context *smu_baco = &smu->smu_baco;
458020dd
LL		 353 struct amdgpu_device *adev = smu->adev;
354 uint32_t val;
355
1b41d67e 356 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) {
458020dd
LL		 357 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
358 smu_baco->platform_support =
359 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
360 false;
361 }
362}
363
364static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
365{
366 struct smu_table_context *table_context = &smu->smu_table;
367 struct smu_11_0_7_powerplay_table *powerplay_table =
368 table_context->power_play_table;
4a13b4ce 369
18a4b3de
EQ		 370 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
371 smu->dc_controlled_by_gpio = true;
372
458020dd 373 sienna_cichlid_check_bxco_support(smu);
4a13b4ce
EQ		 374
375 table_context->thermal_controller_type =
376 powerplay_table->thermal_controller_type;
377
aa75fa34
EQ		 378 /*
379 * Instead of having its own buffer space and get overdrive_table copied,
380 * smu->od_settings just points to the actual overdrive_table
381 */
382 smu->od_settings = &powerplay_table->overdrive_table;
383
b455159c
LG		 384 return 0;
385}
386
387static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
388{
dccc7c21
LG		 389 struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
390 int index, ret;
7077b19a 391 I2cControllerConfig_t *table_member;
dccc7c21
LG		 392
393 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
394 smc_dpm_info);
395
22f2447c 396 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
dccc7c21
LG		 397 (uint8_t **)&smc_dpm_table);
398 if (ret)
399 return ret;
7077b19a
CG		 400 GET_PPTABLE_MEMBER(I2cControllers, &table_member);
401 memcpy(table_member, smc_dpm_table->I2cControllers,
402 sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
969c8d16 403
b455159c
LG		 404 return 0;
405}
406
407static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
408{
b455159c 409 struct smu_table_context *table_context = &smu->smu_table;
e05acd78 410 struct smu_11_0_7_powerplay_table *powerplay_table =
4a13b4ce 411 table_context->power_play_table;
7077b19a 412 int table_size;
b455159c 413
7077b19a 414 table_size = get_table_size(smu);
b455159c 415 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
7077b19a 416 table_size);
b455159c 417
4a13b4ce
EQ		 418 return 0;
419}
b455159c 420
4a13b4ce
EQ		 421static int sienna_cichlid_setup_pptable(struct smu_context *smu)
422{
423 int ret = 0;
b455159c 424
4a13b4ce
EQ		 425 ret = smu_v11_0_setup_pptable(smu);
426 if (ret)
427 return ret;
428
429 ret = sienna_cichlid_store_powerplay_table(smu);
430 if (ret)
431 return ret;
432
433 ret = sienna_cichlid_append_powerplay_table(smu);
434 if (ret)
435 return ret;
436
437 ret = sienna_cichlid_check_powerplay_table(smu);
438 if (ret)
439 return ret;
440
441 return ret;
b455159c
LG		 442}
443
c1b353b7 444static int sienna_cichlid_tables_init(struct smu_context *smu)
b455159c
LG		 445{
446 struct smu_table_context *smu_table = &smu->smu_table;
c1b353b7 447 struct smu_table *tables = smu_table->tables;
7077b19a 448 int table_size;
b455159c 449
7077b19a
CG		 450 table_size = get_table_size(smu);
451 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
452 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c
LG		 453 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
454 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b4b0b79d 455 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
b455159c 456 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
bc50ca29
AD		 457 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
458 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c
LG		 459 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
460 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
461 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
462 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
463 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
f9e3fe46 464 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
b455159c
LG		 465 AMDGPU_GEM_DOMAIN_VRAM);
466
b4b0b79d 467 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
b455159c 468 if (!smu_table->metrics_table)
8ca78a0a 469 goto err0_out;
b455159c
LG		 470 smu_table->metrics_time = 0;
471
f06d9511 472 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
8ca78a0a
EQ		 473 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
474 if (!smu_table->gpu_metrics_table)
475 goto err1_out;
476
40d3b8db
LG		 477 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
478 if (!smu_table->watermarks_table)
8ca78a0a 479 goto err2_out;
40d3b8db 480
b455159c 481 return 0;
8ca78a0a
EQ		 482
483err2_out:
484 kfree(smu_table->gpu_metrics_table);
485err1_out:
486 kfree(smu_table->metrics_table);
487err0_out:
488 return -ENOMEM;
b455159c
LG		 489}
490
be22e2b9
EQ		 491static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu)
492{
493 struct smu_table_context *smu_table= &smu->smu_table;
494 SmuMetricsExternal_t *metrics_ext =
495 (SmuMetricsExternal_t *)(smu_table->metrics_table);
496 uint32_t throttler_status = 0;
497 int i;
498
499 if ((smu->adev->asic_type == CHIP_SIENNA_CICHLID) &&
500 (smu->smc_fw_version >= 0x3A4300)) {
501 for (i = 0; i < THROTTLER_COUNT; i++)
502 throttler_status |=
503 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
504 } else {
505 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus;
506 }
507
508 return throttler_status;
509}
510
60ae4d67
EQ		 511static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
512 MetricsMember_t member,
513 uint32_t *value)
514{
515 struct smu_table_context *smu_table= &smu->smu_table;
b4b0b79d
EQ		 516 SmuMetrics_t *metrics =
517 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
be22e2b9
EQ		 518 SmuMetrics_V2_t *metrics_v2 =
519 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
520 bool use_metrics_v2 = ((smu->adev->asic_type == CHIP_SIENNA_CICHLID) &&
521 (smu->smc_fw_version >= 0x3A4300)) ? true : false;
522 uint16_t average_gfx_activity;
60ae4d67
EQ		 523 int ret = 0;
524
525 mutex_lock(&smu->metrics_lock);
526
fceafc9b
EQ		 527 ret = smu_cmn_get_metrics_table_locked(smu,
528 NULL,
529 false);
60ae4d67
EQ		 530 if (ret) {
531 mutex_unlock(&smu->metrics_lock);
532 return ret;
533 }
534
8c686254
EQ		 535 switch (member) {
536 case METRICS_CURR_GFXCLK:
be22e2b9
EQ		 537 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] :
538 metrics->CurrClock[PPCLK_GFXCLK];
8c686254
EQ		 539 break;
540 case METRICS_CURR_SOCCLK:
be22e2b9
EQ		 541 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] :
542 metrics->CurrClock[PPCLK_SOCCLK];
8c686254
EQ		 543 break;
544 case METRICS_CURR_UCLK:
be22e2b9
EQ		 545 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] :
546 metrics->CurrClock[PPCLK_UCLK];
8c686254
EQ		 547 break;
548 case METRICS_CURR_VCLK:
be22e2b9
EQ		 549 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] :
550 metrics->CurrClock[PPCLK_VCLK_0];
8c686254
EQ		 551 break;
552 case METRICS_CURR_VCLK1:
be22e2b9
EQ		 553 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] :
554 metrics->CurrClock[PPCLK_VCLK_1];
8c686254
EQ		 555 break;
556 case METRICS_CURR_DCLK:
be22e2b9
EQ		 557 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] :
558 metrics->CurrClock[PPCLK_DCLK_0];
8c686254
EQ		 559 break;
560 case METRICS_CURR_DCLK1:
be22e2b9
EQ		 561 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
562 metrics->CurrClock[PPCLK_DCLK_1];
8c686254 563 break;
9d09fa6f 564 case METRICS_CURR_DCEFCLK:
be22e2b9
EQ		 565 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] :
566 metrics->CurrClock[PPCLK_DCEFCLK];
9d09fa6f 567 break;
4e2b3e23 568 case METRICS_CURR_FCLK:
be22e2b9
EQ		 569 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] :
570 metrics->CurrClock[PPCLK_FCLK];
4e2b3e23 571 break;
8c686254 572 case METRICS_AVERAGE_GFXCLK:
be22e2b9
EQ		 573 average_gfx_activity = use_metrics_v2 ? metrics_v2->AverageGfxActivity :
574 metrics->AverageGfxActivity;
575 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
576 *value = use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
577 metrics->AverageGfxclkFrequencyPostDs;
d817f375 578 else
be22e2b9
EQ		 579 *value = use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
580 metrics->AverageGfxclkFrequencyPreDs;
8c686254
EQ		 581 break;
582 case METRICS_AVERAGE_FCLK:
be22e2b9
EQ		 583 *value = use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs :
584 metrics->AverageFclkFrequencyPostDs;
8c686254
EQ		 585 break;
586 case METRICS_AVERAGE_UCLK:
be22e2b9
EQ		 587 *value = use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
588 metrics->AverageUclkFrequencyPostDs;
8c686254
EQ		 589 break;
590 case METRICS_AVERAGE_GFXACTIVITY:
be22e2b9
EQ		 591 *value = use_metrics_v2 ? metrics_v2->AverageGfxActivity :
592 metrics->AverageGfxActivity;
8c686254
EQ		 593 break;
594 case METRICS_AVERAGE_MEMACTIVITY:
be22e2b9
EQ		 595 *value = use_metrics_v2 ? metrics_v2->AverageUclkActivity :
596 metrics->AverageUclkActivity;
8c686254
EQ		 597 break;
598 case METRICS_AVERAGE_SOCKETPOWER:
be22e2b9
EQ		 599 *value = use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 :
600 metrics->AverageSocketPower << 8;
8c686254
EQ		 601 break;
602 case METRICS_TEMPERATURE_EDGE:
be22e2b9 603 *value = (use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge) *
8c686254
EQ		 604 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
605 break;
606 case METRICS_TEMPERATURE_HOTSPOT:
be22e2b9 607 *value = (use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot) *
8c686254
EQ		 608 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
609 break;
610 case METRICS_TEMPERATURE_MEM:
be22e2b9 611 *value = (use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem) *
8c686254
EQ		 612 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
613 break;
614 case METRICS_TEMPERATURE_VRGFX:
be22e2b9 615 *value = (use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx) *
8c686254
EQ		 616 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
617 break;
618 case METRICS_TEMPERATURE_VRSOC:
be22e2b9 619 *value = (use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc) *
8c686254
EQ		 620 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
621 break;
622 case METRICS_THROTTLER_STATUS:
be22e2b9 623 *value = sienna_cichlid_get_throttler_status_locked(smu);
8c686254
EQ		 624 break;
625 case METRICS_CURR_FANSPEED:
be22e2b9 626 *value = use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
8c686254
EQ		 627 break;
628 default:
629 *value = UINT_MAX;
630 break;
631 }
632
b455159c
LG		 633 mutex_unlock(&smu->metrics_lock);
634
635 return ret;
8c686254 636
b455159c
LG		 637}
638
639static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
640{
641 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
642
b455159c
LG		 643 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
644 GFP_KERNEL);
645 if (!smu_dpm->dpm_context)
646 return -ENOMEM;
647
648 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
649
650 return 0;
651}
652
c1b353b7
EQ		 653static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
654{
655 int ret = 0;
656
657 ret = sienna_cichlid_tables_init(smu);
658 if (ret)
659 return ret;
660
661 ret = sienna_cichlid_allocate_dpm_context(smu);
662 if (ret)
663 return ret;
664
665 return smu_v11_0_init_smc_tables(smu);
666}
667
b455159c
LG		 668static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
669{
90a89c31 670 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
90a89c31 671 struct smu_11_0_dpm_table *dpm_table;
85dec717 672 struct amdgpu_device *adev = smu->adev;
90a89c31 673 int ret = 0;
7077b19a 674 DpmDescriptor_t *table_member;
b455159c 675
90a89c31
EQ		 676 /* socclk dpm table setup */
677 dpm_table = &dpm_context->dpm_tables.soc_table;
7077b19a 678 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
b4bb3aaf 679 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
90a89c31
EQ		 680 ret = smu_v11_0_set_single_dpm_table(smu,
681 SMU_SOCCLK,
682 dpm_table);
683 if (ret)
684 return ret;
685 dpm_table->is_fine_grained =
7077b19a 686 !table_member[PPCLK_SOCCLK].SnapToDiscrete;
90a89c31
EQ		 687 } else {
688 dpm_table->count = 1;
689 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
690 dpm_table->dpm_levels[0].enabled = true;
691 dpm_table->min = dpm_table->dpm_levels[0].value;
692 dpm_table->max = dpm_table->dpm_levels[0].value;
693 }
b455159c 694
90a89c31
EQ		 695 /* gfxclk dpm table setup */
696 dpm_table = &dpm_context->dpm_tables.gfx_table;
b4bb3aaf 697 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
90a89c31
EQ		 698 ret = smu_v11_0_set_single_dpm_table(smu,
699 SMU_GFXCLK,
700 dpm_table);
701 if (ret)
702 return ret;
703 dpm_table->is_fine_grained =
7077b19a 704 !table_member[PPCLK_GFXCLK].SnapToDiscrete;
90a89c31
EQ		 705 } else {
706 dpm_table->count = 1;
707 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
708 dpm_table->dpm_levels[0].enabled = true;
709 dpm_table->min = dpm_table->dpm_levels[0].value;
710 dpm_table->max = dpm_table->dpm_levels[0].value;
711 }
b455159c 712
90a89c31
EQ		 713 /* uclk dpm table setup */
714 dpm_table = &dpm_context->dpm_tables.uclk_table;
b4bb3aaf 715 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
90a89c31
EQ		 716 ret = smu_v11_0_set_single_dpm_table(smu,
717 SMU_UCLK,
718 dpm_table);
719 if (ret)
720 return ret;
721 dpm_table->is_fine_grained =
7077b19a 722 !table_member[PPCLK_UCLK].SnapToDiscrete;
90a89c31
EQ		 723 } else {
724 dpm_table->count = 1;
725 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
726 dpm_table->dpm_levels[0].enabled = true;
727 dpm_table->min = dpm_table->dpm_levels[0].value;
728 dpm_table->max = dpm_table->dpm_levels[0].value;
729 }
b455159c 730
90a89c31
EQ		 731 /* fclk dpm table setup */
732 dpm_table = &dpm_context->dpm_tables.fclk_table;
b4bb3aaf 733 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
90a89c31
EQ		 734 ret = smu_v11_0_set_single_dpm_table(smu,
735 SMU_FCLK,
736 dpm_table);
737 if (ret)
738 return ret;
739 dpm_table->is_fine_grained =
7077b19a 740 !table_member[PPCLK_FCLK].SnapToDiscrete;
90a89c31
EQ		 741 } else {
742 dpm_table->count = 1;
743 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
744 dpm_table->dpm_levels[0].enabled = true;
745 dpm_table->min = dpm_table->dpm_levels[0].value;
746 dpm_table->max = dpm_table->dpm_levels[0].value;
747 }
b455159c 748
90a89c31
EQ		 749 /* vclk0 dpm table setup */
750 dpm_table = &dpm_context->dpm_tables.vclk_table;
b4bb3aaf 751 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
90a89c31
EQ		 752 ret = smu_v11_0_set_single_dpm_table(smu,
753 SMU_VCLK,
754 dpm_table);
755 if (ret)
756 return ret;
757 dpm_table->is_fine_grained =
7077b19a 758 !table_member[PPCLK_VCLK_0].SnapToDiscrete;
90a89c31
EQ		 759 } else {
760 dpm_table->count = 1;
761 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
762 dpm_table->dpm_levels[0].enabled = true;
763 dpm_table->min = dpm_table->dpm_levels[0].value;
764 dpm_table->max = dpm_table->dpm_levels[0].value;
765 }
b455159c 766
90a89c31 767 /* vclk1 dpm table setup */
85dec717
JC		 768 if (adev->vcn.num_vcn_inst > 1) {
769 dpm_table = &dpm_context->dpm_tables.vclk1_table;
770 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
771 ret = smu_v11_0_set_single_dpm_table(smu,
772 SMU_VCLK1,
773 dpm_table);
774 if (ret)
775 return ret;
776 dpm_table->is_fine_grained =
7077b19a 777 !table_member[PPCLK_VCLK_1].SnapToDiscrete;
85dec717
JC		 778 } else {
779 dpm_table->count = 1;
780 dpm_table->dpm_levels[0].value =
781 smu->smu_table.boot_values.vclk / 100;
782 dpm_table->dpm_levels[0].enabled = true;
783 dpm_table->min = dpm_table->dpm_levels[0].value;
784 dpm_table->max = dpm_table->dpm_levels[0].value;
785 }
90a89c31 786 }
b455159c 787
90a89c31
EQ		 788 /* dclk0 dpm table setup */
789 dpm_table = &dpm_context->dpm_tables.dclk_table;
b4bb3aaf 790 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
90a89c31
EQ		 791 ret = smu_v11_0_set_single_dpm_table(smu,
792 SMU_DCLK,
793 dpm_table);
794 if (ret)
795 return ret;
796 dpm_table->is_fine_grained =
7077b19a 797 !table_member[PPCLK_DCLK_0].SnapToDiscrete;
90a89c31
EQ		 798 } else {
799 dpm_table->count = 1;
800 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
801 dpm_table->dpm_levels[0].enabled = true;
802 dpm_table->min = dpm_table->dpm_levels[0].value;
803 dpm_table->max = dpm_table->dpm_levels[0].value;
804 }
805
806 /* dclk1 dpm table setup */
85dec717
JC		 807 if (adev->vcn.num_vcn_inst > 1) {
808 dpm_table = &dpm_context->dpm_tables.dclk1_table;
809 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
810 ret = smu_v11_0_set_single_dpm_table(smu,
811 SMU_DCLK1,
812 dpm_table);
813 if (ret)
814 return ret;
815 dpm_table->is_fine_grained =
7077b19a 816 !table_member[PPCLK_DCLK_1].SnapToDiscrete;
85dec717
JC		 817 } else {
818 dpm_table->count = 1;
819 dpm_table->dpm_levels[0].value =
820 smu->smu_table.boot_values.dclk / 100;
821 dpm_table->dpm_levels[0].enabled = true;
822 dpm_table->min = dpm_table->dpm_levels[0].value;
823 dpm_table->max = dpm_table->dpm_levels[0].value;
824 }
90a89c31
EQ		 825 }
826
827 /* dcefclk dpm table setup */
828 dpm_table = &dpm_context->dpm_tables.dcef_table;
b4bb3aaf 829 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 830 ret = smu_v11_0_set_single_dpm_table(smu,
831 SMU_DCEFCLK,
832 dpm_table);
833 if (ret)
834 return ret;
835 dpm_table->is_fine_grained =
7077b19a 836 !table_member[PPCLK_DCEFCLK].SnapToDiscrete;
90a89c31
EQ		 837 } else {
838 dpm_table->count = 1;
839 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
840 dpm_table->dpm_levels[0].enabled = true;
841 dpm_table->min = dpm_table->dpm_levels[0].value;
842 dpm_table->max = dpm_table->dpm_levels[0].value;
843 }
b455159c 844
90a89c31
EQ		 845 /* pixelclk dpm table setup */
846 dpm_table = &dpm_context->dpm_tables.pixel_table;
b4bb3aaf 847 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 848 ret = smu_v11_0_set_single_dpm_table(smu,
849 SMU_PIXCLK,
850 dpm_table);
851 if (ret)
852 return ret;
853 dpm_table->is_fine_grained =
7077b19a 854 !table_member[PPCLK_PIXCLK].SnapToDiscrete;
90a89c31
EQ		 855 } else {
856 dpm_table->count = 1;
857 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
858 dpm_table->dpm_levels[0].enabled = true;
859 dpm_table->min = dpm_table->dpm_levels[0].value;
860 dpm_table->max = dpm_table->dpm_levels[0].value;
861 }
b455159c 862
90a89c31
EQ		 863 /* displayclk dpm table setup */
864 dpm_table = &dpm_context->dpm_tables.display_table;
b4bb3aaf 865 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 866 ret = smu_v11_0_set_single_dpm_table(smu,
867 SMU_DISPCLK,
868 dpm_table);
869 if (ret)
870 return ret;
871 dpm_table->is_fine_grained =
7077b19a 872 !table_member[PPCLK_DISPCLK].SnapToDiscrete;
90a89c31
EQ		 873 } else {
874 dpm_table->count = 1;
875 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
876 dpm_table->dpm_levels[0].enabled = true;
877 dpm_table->min = dpm_table->dpm_levels[0].value;
878 dpm_table->max = dpm_table->dpm_levels[0].value;
879 }
b455159c 880
90a89c31
EQ		 881 /* phyclk dpm table setup */
882 dpm_table = &dpm_context->dpm_tables.phy_table;
b4bb3aaf 883 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 884 ret = smu_v11_0_set_single_dpm_table(smu,
885 SMU_PHYCLK,
886 dpm_table);
887 if (ret)
888 return ret;
889 dpm_table->is_fine_grained =
7077b19a 890 !table_member[PPCLK_PHYCLK].SnapToDiscrete;
90a89c31
EQ		 891 } else {
892 dpm_table->count = 1;
893 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
894 dpm_table->dpm_levels[0].enabled = true;
895 dpm_table->min = dpm_table->dpm_levels[0].value;
896 dpm_table->max = dpm_table->dpm_levels[0].value;
897 }
b455159c
LG		 898
899 return 0;
900}
901
f6b4b4a1 902static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
b455159c 903{
d51dc613 904 struct amdgpu_device *adev = smu->adev;
b455159c
LG		 905 int ret = 0;
906
907 if (enable) {
908 /* vcn dpm on is a prerequisite for vcn power gate messages */
b4bb3aaf 909 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 910 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
6fb176a7
LG		 911 if (ret)
912 return ret;
6ec46653 913 if (adev->vcn.num_vcn_inst > 1) {
66c86828 914 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
d51dc613
JC		 915 0x10000, NULL);
916 if (ret)
917 return ret;
918 }
b455159c 919 }
b455159c 920 } else {
b4bb3aaf 921 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 922 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
6fb176a7
LG		 923 if (ret)
924 return ret;
6ec46653 925 if (adev->vcn.num_vcn_inst > 1) {
66c86828 926 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
d51dc613
JC		 927 0x10000, NULL);
928 if (ret)
929 return ret;
930 }
b455159c 931 }
b455159c
LG		 932 }
933
934 return ret;
935}
936
6fb176a7
LG		 937static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
938{
6fb176a7
LG		 939 int ret = 0;
940
941 if (enable) {
b4bb3aaf 942 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 943 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
6fb176a7
LG		 944 if (ret)
945 return ret;
6fb176a7 946 }
6fb176a7 947 } else {
b4bb3aaf 948 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 949 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
6fb176a7
LG		 950 if (ret)
951 return ret;
6fb176a7 952 }
6fb176a7
LG		 953 }
954
955 return ret;
956}
957
b455159c
LG		 958static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
959 enum smu_clk_type clk_type,
960 uint32_t *value)
961{
8c686254
EQ		 962 MetricsMember_t member_type;
963 int clk_id = 0;
b455159c 964
6c339f37
EQ		 965 clk_id = smu_cmn_to_asic_specific_index(smu,
966 CMN2ASIC_MAPPING_CLK,
967 clk_type);
b455159c
LG		 968 if (clk_id < 0)
969 return clk_id;
970
8c686254
EQ		 971 switch (clk_id) {
972 case PPCLK_GFXCLK:
973 member_type = METRICS_CURR_GFXCLK;
974 break;
975 case PPCLK_UCLK:
976 member_type = METRICS_CURR_UCLK;
977 break;
978 case PPCLK_SOCCLK:
979 member_type = METRICS_CURR_SOCCLK;
980 break;
981 case PPCLK_FCLK:
982 member_type = METRICS_CURR_FCLK;
983 break;
984 case PPCLK_VCLK_0:
985 member_type = METRICS_CURR_VCLK;
986 break;
987 case PPCLK_VCLK_1:
988 member_type = METRICS_CURR_VCLK1;
989 break;
990 case PPCLK_DCLK_0:
991 member_type = METRICS_CURR_DCLK;
992 break;
993 case PPCLK_DCLK_1:
994 member_type = METRICS_CURR_DCLK1;
995 break;
996 case PPCLK_DCEFCLK:
997 member_type = METRICS_CURR_DCEFCLK;
998 break;
999 default:
1000 return -EINVAL;
1001 }
1002
1003 return sienna_cichlid_get_smu_metrics_data(smu,
1004 member_type,
1005 value);
b455159c 1006
b455159c
LG		 1007}
1008
1009static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1010{
b455159c 1011 DpmDescriptor_t *dpm_desc = NULL;
7077b19a 1012 DpmDescriptor_t *table_member;
b455159c
LG		 1013 uint32_t clk_index = 0;
1014
7077b19a 1015 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
6c339f37
EQ		 1016 clk_index = smu_cmn_to_asic_specific_index(smu,
1017 CMN2ASIC_MAPPING_CLK,
1018 clk_type);
7077b19a 1019 dpm_desc = &table_member[clk_index];
b455159c
LG		 1020
1021 /* 0 - Fine grained DPM, 1 - Discrete DPM */
0ee56acc 1022 return dpm_desc->SnapToDiscrete == 0;
b455159c
LG		 1023}
1024
37a58f69
EQ		 1025static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
1026 enum SMU_11_0_7_ODFEATURE_CAP cap)
1027{
1028 return od_table->cap[cap];
1029}
1030
1031static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
1032 enum SMU_11_0_7_ODSETTING_ID setting,
1033 uint32_t *min, uint32_t *max)
1034{
1035 if (min)
1036 *min = od_table->min[setting];
1037 if (max)
1038 *max = od_table->max[setting];
1039}
1040
b455159c
LG		 1041static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
1042 enum smu_clk_type clk_type, char *buf)
1043{
b7d25b5f
LG		 1044 struct amdgpu_device *adev = smu->adev;
1045 struct smu_table_context *table_context = &smu->smu_table;
1046 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1047 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
7077b19a
CG		 1048 uint16_t *table_member;
1049
37a58f69
EQ		 1050 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
1051 OverDriveTable_t *od_table =
1052 (OverDriveTable_t *)table_context->overdrive_table;
b455159c
LG		 1053 int i, size = 0, ret = 0;
1054 uint32_t cur_value = 0, value = 0, count = 0;
1055 uint32_t freq_values[3] = {0};
1056 uint32_t mark_index = 0;
b7d25b5f 1057 uint32_t gen_speed, lane_width;
37a58f69 1058 uint32_t min_value, max_value;
a2b6df4f 1059 uint32_t smu_version;
b455159c
LG		 1060
1061 switch (clk_type) {
1062 case SMU_GFXCLK:
1063 case SMU_SCLK:
1064 case SMU_SOCCLK:
1065 case SMU_MCLK:
1066 case SMU_UCLK:
1067 case SMU_FCLK:
78842457
DN		 1068 case SMU_VCLK:
1069 case SMU_VCLK1:
1070 case SMU_DCLK:
1071 case SMU_DCLK1:
b455159c 1072 case SMU_DCEFCLK:
5e6dc8fe 1073 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
b455159c 1074 if (ret)
258d290c 1075 goto print_clk_out;
b455159c 1076
ba818620
KF		 1077 /* no need to disable gfxoff when retrieving the current gfxclk */
1078 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1079 amdgpu_gfx_off_ctrl(adev, false);
1080
d8d3493a 1081 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
b455159c 1082 if (ret)
258d290c 1083 goto print_clk_out;
b455159c
LG		 1084
1085 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1086 for (i = 0; i < count; i++) {
d8d3493a 1087 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
b455159c 1088 if (ret)
258d290c 1089 goto print_clk_out;
b455159c 1090
fe14c285 1091 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
b455159c
LG		 1092 cur_value == value ? "*" : "");
1093 }
1094 } else {
d8d3493a 1095 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
b455159c 1096 if (ret)
258d290c 1097 goto print_clk_out;
d8d3493a 1098 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
b455159c 1099 if (ret)
258d290c 1100 goto print_clk_out;
b455159c
LG		 1101
1102 freq_values[1] = cur_value;
1103 mark_index = cur_value == freq_values[0] ? 0 :
1104 cur_value == freq_values[2] ? 2 : 1;
b455159c 1105
891bacb8
KF		 1106 count = 3;
1107 if (mark_index != 1) {
1108 count = 2;
1109 freq_values[1] = freq_values[2];
1110 }
1111
1112 for (i = 0; i < count; i++) {
fe14c285 1113 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
891bacb8 1114 cur_value == freq_values[i] ? "*" : "");
b455159c
LG		 1115 }
1116
1117 }
1118 break;
b7d25b5f 1119 case SMU_PCIE:
f20c52f4
LG		 1120 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1121 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
7077b19a 1122 GET_PPTABLE_MEMBER(LclkFreq, &table_member);
b7d25b5f 1123 for (i = 0; i < NUM_LINK_LEVELS; i++)
fe14c285 1124 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
b7d25b5f
LG		 1125 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1126 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1127 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1128 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1129 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1130 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1131 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1132 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1133 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1134 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
7077b19a 1135 table_member[i],
b7d25b5f
LG		 1136 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1137 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1138 "*" : "");
1139 break;
37a58f69
EQ		 1140 case SMU_OD_SCLK:
1141 if (!smu->od_enabled || !od_table || !od_settings)
1142 break;
1143
1144 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1145 break;
1146
fe14c285
DP		 1147 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1148 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
37a58f69
EQ		 1149 break;
1150
1151 case SMU_OD_MCLK:
1152 if (!smu->od_enabled || !od_table || !od_settings)
1153 break;
1154
1155 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1156 break;
1157
fe14c285
DP		 1158 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1159 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
37a58f69
EQ		 1160 break;
1161
a2b6df4f
EQ		 1162 case SMU_OD_VDDGFX_OFFSET:
1163 if (!smu->od_enabled || !od_table || !od_settings)
1164 break;
1165
1166 /*
1167 * OD GFX Voltage Offset functionality is supported only by 58.41.0
1168 * and onwards SMU firmwares.
1169 */
1170 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1171 if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1172 (smu_version < 0x003a2900))
1173 break;
1174
fe14c285
DP		 1175 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1176 size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset);
a2b6df4f
EQ		 1177 break;
1178
37a58f69
EQ		 1179 case SMU_OD_RANGE:
1180 if (!smu->od_enabled || !od_table || !od_settings)
1181 break;
1182
fe14c285 1183 size = sysfs_emit(buf, "%s:\n", "OD_RANGE");
37a58f69
EQ		 1184
1185 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1186 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1187 &min_value, NULL);
1188 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1189 NULL, &max_value);
fe14c285 1190 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
37a58f69
EQ		 1191 min_value, max_value);
1192 }
1193
1194 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1195 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1196 &min_value, NULL);
1197 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1198 NULL, &max_value);
fe14c285 1199 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
37a58f69
EQ		 1200 min_value, max_value);
1201 }
1202 break;
1203
b455159c
LG		 1204 default:
1205 break;
1206 }
1207
258d290c
LG		 1208print_clk_out:
1209 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1210 amdgpu_gfx_off_ctrl(adev, true);
1211
b455159c
LG		 1212 return size;
1213}
1214
1215static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1216 enum smu_clk_type clk_type, uint32_t mask)
1217{
258d290c 1218 struct amdgpu_device *adev = smu->adev;
b455159c
LG		 1219 int ret = 0, size = 0;
1220 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1221
1222 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1223 soft_max_level = mask ? (fls(mask) - 1) : 0;
1224
258d290c
LG		 1225 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1226 amdgpu_gfx_off_ctrl(adev, false);
1227
b455159c
LG		 1228 switch (clk_type) {
1229 case SMU_GFXCLK:
1230 case SMU_SCLK:
1231 case SMU_SOCCLK:
1232 case SMU_MCLK:
1233 case SMU_UCLK:
b455159c 1234 case SMU_FCLK:
9ad9c8ac
LG		 1235 /* There is only 2 levels for fine grained DPM */
1236 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1237 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1238 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1239 }
1240
d8d3493a 1241 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
b455159c 1242 if (ret)
258d290c 1243 goto forec_level_out;
b455159c 1244
d8d3493a 1245 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
b455159c 1246 if (ret)
258d290c 1247 goto forec_level_out;
b455159c 1248
10e96d89 1249 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
b455159c 1250 if (ret)
258d290c 1251 goto forec_level_out;
b455159c 1252 break;
51ec6992
DP		 1253 case SMU_DCEFCLK:
1254 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1255 break;
b455159c
LG		 1256 default:
1257 break;
1258 }
1259
258d290c
LG		 1260forec_level_out:
1261 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1262 amdgpu_gfx_off_ctrl(adev, true);
1263
b455159c
LG		 1264 return size;
1265}
1266
1267static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1268{
62cc9dd1
EQ		 1269 struct smu_11_0_dpm_context *dpm_context =
1270 smu->smu_dpm.dpm_context;
1271 struct smu_11_0_dpm_table *gfx_table =
1272 &dpm_context->dpm_tables.gfx_table;
1273 struct smu_11_0_dpm_table *mem_table =
1274 &dpm_context->dpm_tables.uclk_table;
1275 struct smu_11_0_dpm_table *soc_table =
1276 &dpm_context->dpm_tables.soc_table;
1277 struct smu_umd_pstate_table *pstate_table =
1278 &smu->pstate_table;
1279
1280 pstate_table->gfxclk_pstate.min = gfx_table->min;
1281 pstate_table->gfxclk_pstate.peak = gfx_table->max;
0dc994fb
EQ		 1282 if (gfx_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK)
1283 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
62cc9dd1
EQ		 1284
1285 pstate_table->uclk_pstate.min = mem_table->min;
1286 pstate_table->uclk_pstate.peak = mem_table->max;
0dc994fb
EQ		 1287 if (mem_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK)
1288 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
62cc9dd1
EQ		 1289
1290 pstate_table->socclk_pstate.min = soc_table->min;
1291 pstate_table->socclk_pstate.peak = soc_table->max;
0dc994fb
EQ		 1292 if (soc_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK)
1293 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
b455159c 1294
62cc9dd1 1295 return 0;
b455159c
LG		 1296}
1297
b455159c
LG		 1298static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1299{
1300 int ret = 0;
1301 uint32_t max_freq = 0;
1302
1303 /* Sienna_Cichlid do not support to change display num currently */
1304 return 0;
1305#if 0
66c86828 1306 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
b455159c
LG		 1307 if (ret)
1308 return ret;
1309#endif
1310
b4bb3aaf 1311 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
e5ef784b 1312 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
b455159c
LG		 1313 if (ret)
1314 return ret;
661b94f5 1315 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
b455159c
LG		 1316 if (ret)
1317 return ret;
1318 }
1319
1320 return ret;
1321}
1322
1323static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1324{
1325 int ret = 0;
1326
b455159c 1327 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
4d942ae3
EQ		 1328 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1329 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
b455159c 1330#if 0
66c86828 1331 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
40d3b8db
LG		 1332 smu->display_config->num_display,
1333 NULL);
b455159c
LG		 1334#endif
1335 if (ret)
1336 return ret;
1337 }
1338
1339 return ret;
1340}
1341
b455159c
LG		 1342static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1343{
1344 int ret = 0;
1345 uint32_t feature_mask[2];
3d14a79b
KW		 1346 uint64_t feature_enabled;
1347
28251d72 1348 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
3d14a79b
KW		 1349 if (ret)
1350 return false;
1351
1352 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1353
b455159c
LG		 1354 return !!(feature_enabled & SMC_DPM_FEATURE);
1355}
1356
d9ca7567
EQ		 1357static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1358 uint32_t *speed)
1359{
1360 if (!speed)
1361 return -EINVAL;
1362
1363 /*
1364 * For Sienna_Cichlid and later, the fan speed(rpm) reported
1365 * by pmfw is always trustable(even when the fan control feature
1366 * disabled or 0 RPM kicked in).
1367 */
1368 return sienna_cichlid_get_smu_metrics_data(smu,
1369 METRICS_CURR_FANSPEED,
1370 speed);
1371}
1372
3204ff3e
AD		 1373static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1374{
7077b19a 1375 uint16_t *table_member;
3204ff3e 1376
7077b19a
CG		 1377 GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
1378 smu->fan_max_rpm = *table_member;
3204ff3e
AD		 1379
1380 return 0;
1381}
1382
b455159c
LG		 1383static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1384{
f9e3fe46
EQ		 1385 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1386 DpmActivityMonitorCoeffInt_t *activity_monitor =
1387 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
b455159c
LG		 1388 uint32_t i, size = 0;
1389 int16_t workload_type = 0;
1390 static const char *profile_name[] = {
1391 "BOOTUP_DEFAULT",
1392 "3D_FULL_SCREEN",
1393 "POWER_SAVING",
1394 "VIDEO",
1395 "VR",
1396 "COMPUTE",
1397 "CUSTOM"};
1398 static const char *title[] = {
1399 "PROFILE_INDEX(NAME)",
1400 "CLOCK_TYPE(NAME)",
1401 "FPS",
1402 "MinFreqType",
1403 "MinActiveFreqType",
1404 "MinActiveFreq",
1405 "BoosterFreqType",
1406 "BoosterFreq",
1407 "PD_Data_limit_c",
1408 "PD_Data_error_coeff",
1409 "PD_Data_error_rate_coeff"};
1410 int result = 0;
1411
1412 if (!buf)
1413 return -EINVAL;
1414
fe14c285 1415 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
b455159c
LG		 1416 title[0], title[1], title[2], title[3], title[4], title[5],
1417 title[6], title[7], title[8], title[9], title[10]);
1418
1419 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1420 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
6c339f37
EQ		 1421 workload_type = smu_cmn_to_asic_specific_index(smu,
1422 CMN2ASIC_MAPPING_WORKLOAD,
1423 i);
b455159c
LG		 1424 if (workload_type < 0)
1425 return -EINVAL;
1426
caad2613 1427 result = smu_cmn_update_table(smu,
b455159c 1428 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
f9e3fe46 1429 (void *)(&activity_monitor_external), false);
b455159c 1430 if (result) {
d9811cfc 1431 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
b455159c
LG		 1432 return result;
1433 }
1434
fe14c285 1435 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
b455159c
LG		 1436 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1437
fe14c285 1438 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
b455159c
LG		 1439 " ",
1440 0,
1441 "GFXCLK",
f9e3fe46
EQ		 1442 activity_monitor->Gfx_FPS,
1443 activity_monitor->Gfx_MinFreqStep,
1444 activity_monitor->Gfx_MinActiveFreqType,
1445 activity_monitor->Gfx_MinActiveFreq,
1446 activity_monitor->Gfx_BoosterFreqType,
1447 activity_monitor->Gfx_BoosterFreq,
1448 activity_monitor->Gfx_PD_Data_limit_c,
1449 activity_monitor->Gfx_PD_Data_error_coeff,
1450 activity_monitor->Gfx_PD_Data_error_rate_coeff);
b455159c 1451
fe14c285 1452 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
b455159c
LG		 1453 " ",
1454 1,
1455 "SOCCLK",
f9e3fe46
EQ		 1456 activity_monitor->Fclk_FPS,
1457 activity_monitor->Fclk_MinFreqStep,
1458 activity_monitor->Fclk_MinActiveFreqType,
1459 activity_monitor->Fclk_MinActiveFreq,
1460 activity_monitor->Fclk_BoosterFreqType,
1461 activity_monitor->Fclk_BoosterFreq,
1462 activity_monitor->Fclk_PD_Data_limit_c,
1463 activity_monitor->Fclk_PD_Data_error_coeff,
1464 activity_monitor->Fclk_PD_Data_error_rate_coeff);
b455159c 1465
fe14c285 1466 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
b455159c
LG		 1467 " ",
1468 2,
1469 "MEMLK",
f9e3fe46
EQ		 1470 activity_monitor->Mem_FPS,
1471 activity_monitor->Mem_MinFreqStep,
1472 activity_monitor->Mem_MinActiveFreqType,
1473 activity_monitor->Mem_MinActiveFreq,
1474 activity_monitor->Mem_BoosterFreqType,
1475 activity_monitor->Mem_BoosterFreq,
1476 activity_monitor->Mem_PD_Data_limit_c,
1477 activity_monitor->Mem_PD_Data_error_coeff,
1478 activity_monitor->Mem_PD_Data_error_rate_coeff);
b455159c
LG		 1479 }
1480
1481 return size;
1482}
1483
1484static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1485{
f9e3fe46
EQ		 1486
1487 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1488 DpmActivityMonitorCoeffInt_t *activity_monitor =
1489 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
b455159c
LG		 1490 int workload_type, ret = 0;
1491
1492 smu->power_profile_mode = input[size];
1493
1494 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
d9811cfc 1495 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
b455159c
LG		 1496 return -EINVAL;
1497 }
1498
1499 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
b455159c 1500
caad2613 1501 ret = smu_cmn_update_table(smu,
b455159c 1502 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
f9e3fe46 1503 (void *)(&activity_monitor_external), false);
b455159c 1504 if (ret) {
d9811cfc 1505 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
b455159c
LG		 1506 return ret;
1507 }
1508
1509 switch (input[0]) {
1510 case 0: /* Gfxclk */
f9e3fe46
EQ		 1511 activity_monitor->Gfx_FPS = input[1];
1512 activity_monitor->Gfx_MinFreqStep = input[2];
1513 activity_monitor->Gfx_MinActiveFreqType = input[3];
1514 activity_monitor->Gfx_MinActiveFreq = input[4];
1515 activity_monitor->Gfx_BoosterFreqType = input[5];
1516 activity_monitor->Gfx_BoosterFreq = input[6];
1517 activity_monitor->Gfx_PD_Data_limit_c = input[7];
1518 activity_monitor->Gfx_PD_Data_error_coeff = input[8];
1519 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1520 break;
1521 case 1: /* Socclk */
f9e3fe46
EQ		 1522 activity_monitor->Fclk_FPS = input[1];
1523 activity_monitor->Fclk_MinFreqStep = input[2];
1524 activity_monitor->Fclk_MinActiveFreqType = input[3];
1525 activity_monitor->Fclk_MinActiveFreq = input[4];
1526 activity_monitor->Fclk_BoosterFreqType = input[5];
1527 activity_monitor->Fclk_BoosterFreq = input[6];
1528 activity_monitor->Fclk_PD_Data_limit_c = input[7];
1529 activity_monitor->Fclk_PD_Data_error_coeff = input[8];
1530 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1531 break;
1532 case 2: /* Memlk */
f9e3fe46
EQ		 1533 activity_monitor->Mem_FPS = input[1];
1534 activity_monitor->Mem_MinFreqStep = input[2];
1535 activity_monitor->Mem_MinActiveFreqType = input[3];
1536 activity_monitor->Mem_MinActiveFreq = input[4];
1537 activity_monitor->Mem_BoosterFreqType = input[5];
1538 activity_monitor->Mem_BoosterFreq = input[6];
1539 activity_monitor->Mem_PD_Data_limit_c = input[7];
1540 activity_monitor->Mem_PD_Data_error_coeff = input[8];
1541 activity_monitor->Mem_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1542 break;
1543 }
1544
caad2613 1545 ret = smu_cmn_update_table(smu,
b455159c 1546 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
f9e3fe46 1547 (void *)(&activity_monitor_external), true);
b455159c 1548 if (ret) {
d9811cfc 1549 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
b455159c
LG		 1550 return ret;
1551 }
1552 }
1553
1554 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
6c339f37
EQ		 1555 workload_type = smu_cmn_to_asic_specific_index(smu,
1556 CMN2ASIC_MAPPING_WORKLOAD,
1557 smu->power_profile_mode);
b455159c
LG		 1558 if (workload_type < 0)
1559 return -EINVAL;
66c86828 1560 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
b455159c
LG		 1561 1 << workload_type, NULL);
1562
1563 return ret;
1564}
1565
b455159c
LG		 1566static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1567{
1568 struct smu_clocks min_clocks = {0};
1569 struct pp_display_clock_request clock_req;
1570 int ret = 0;
1571
1572 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1573 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1574 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1575
4d942ae3 1576 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
b455159c
LG		 1577 clock_req.clock_type = amd_pp_dcef_clock;
1578 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1579
1580 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1581 if (!ret) {
4d942ae3 1582 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
66c86828 1583 ret = smu_cmn_send_smc_msg_with_param(smu,
40d3b8db
LG		 1584 SMU_MSG_SetMinDeepSleepDcefclk,
1585 min_clocks.dcef_clock_in_sr/100,
1586 NULL);
1587 if (ret) {
d9811cfc 1588 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
40d3b8db
LG		 1589 return ret;
1590 }
b455159c
LG		 1591 }
1592 } else {
d9811cfc 1593 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
b455159c
LG		 1594 }
1595 }
1596
b4bb3aaf 1597 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
661b94f5 1598 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
b455159c 1599 if (ret) {
d9811cfc 1600 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
b455159c
LG		 1601 return ret;
1602 }
1603 }
1604
1605 return 0;
1606}
1607
1608static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
7b9c7e30 1609 struct pp_smu_wm_range_sets *clock_ranges)
b455159c 1610{
e7a95eea 1611 Watermarks_t *table = smu->smu_table.watermarks_table;
40d3b8db 1612 int ret = 0;
e7a95eea 1613 int i;
b455159c 1614
e7a95eea 1615 if (clock_ranges) {
7b9c7e30
EQ		 1616 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1617 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
e7a95eea
EQ		 1618 return -EINVAL;
1619
7b9c7e30
EQ		 1620 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1621 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1622 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1623 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1624 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1625 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1626 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1627 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1628 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1629
1630 table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1631 clock_ranges->reader_wm_sets[i].wm_inst;
e7a95eea 1632 }
b455159c 1633
7b9c7e30
EQ		 1634 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1635 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1636 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1637 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1638 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1639 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1640 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1641 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1642 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1643
1644 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1645 clock_ranges->writer_wm_sets[i].wm_inst;
e7a95eea
EQ		 1646 }
1647
1648 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1649 }
1650
1651 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1652 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
caad2613 1653 ret = smu_cmn_write_watermarks_table(smu);
40d3b8db 1654 if (ret) {
d9811cfc 1655 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
40d3b8db
LG		 1656 return ret;
1657 }
1658 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1659 }
1660
b455159c
LG		 1661 return 0;
1662}
1663
b455159c
LG		 1664static int sienna_cichlid_read_sensor(struct smu_context *smu,
1665 enum amd_pp_sensors sensor,
1666 void *data, uint32_t *size)
1667{
1668 int ret = 0;
7077b19a 1669 uint16_t *temp;
b455159c
LG		 1670
1671 if(!data || !size)
1672 return -EINVAL;
1673
1674 mutex_lock(&smu->sensor_lock);
1675 switch (sensor) {
1676 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
7077b19a
CG		 1677 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
1678 *(uint16_t *)data = *temp;
b455159c
LG		 1679 *size = 4;
1680 break;
1681 case AMDGPU_PP_SENSOR_MEM_LOAD:
60e317a2
AD		 1682 ret = sienna_cichlid_get_smu_metrics_data(smu,
1683 METRICS_AVERAGE_MEMACTIVITY,
1684 (uint32_t *)data);
1685 *size = 4;
1686 break;
b455159c 1687 case AMDGPU_PP_SENSOR_GPU_LOAD:
60e317a2
AD		 1688 ret = sienna_cichlid_get_smu_metrics_data(smu,
1689 METRICS_AVERAGE_GFXACTIVITY,
1690 (uint32_t *)data);
b455159c
LG		 1691 *size = 4;
1692 break;
1693 case AMDGPU_PP_SENSOR_GPU_POWER:
60e317a2
AD		 1694 ret = sienna_cichlid_get_smu_metrics_data(smu,
1695 METRICS_AVERAGE_SOCKETPOWER,
1696 (uint32_t *)data);
b455159c
LG		 1697 *size = 4;
1698 break;
1699 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
60e317a2
AD		 1700 ret = sienna_cichlid_get_smu_metrics_data(smu,
1701 METRICS_TEMPERATURE_HOTSPOT,
1702 (uint32_t *)data);
1703 *size = 4;
1704 break;
b455159c 1705 case AMDGPU_PP_SENSOR_EDGE_TEMP:
60e317a2
AD		 1706 ret = sienna_cichlid_get_smu_metrics_data(smu,
1707 METRICS_TEMPERATURE_EDGE,
1708 (uint32_t *)data);
1709 *size = 4;
1710 break;
b455159c 1711 case AMDGPU_PP_SENSOR_MEM_TEMP:
60e317a2
AD		 1712 ret = sienna_cichlid_get_smu_metrics_data(smu,
1713 METRICS_TEMPERATURE_MEM,
1714 (uint32_t *)data);
b455159c
LG		 1715 *size = 4;
1716 break;
e0f9e936
EQ		 1717 case AMDGPU_PP_SENSOR_GFX_MCLK:
1718 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1719 *(uint32_t *)data *= 100;
1720 *size = 4;
1721 break;
1722 case AMDGPU_PP_SENSOR_GFX_SCLK:
1723 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1724 *(uint32_t *)data *= 100;
1725 *size = 4;
1726 break;
b2febc99
EQ		 1727 case AMDGPU_PP_SENSOR_VDDGFX:
1728 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1729 *size = 4;
1730 break;
b455159c 1731 default:
b2febc99
EQ		 1732 ret = -EOPNOTSUPP;
1733 break;
b455159c
LG		 1734 }
1735 mutex_unlock(&smu->sensor_lock);
1736
1737 return ret;
1738}
1739
1740static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1741{
1742 uint32_t num_discrete_levels = 0;
1743 uint16_t *dpm_levels = NULL;
1744 uint16_t i = 0;
1745 struct smu_table_context *table_context = &smu->smu_table;
7077b19a
CG		 1746 DpmDescriptor_t *table_member1;
1747 uint16_t *table_member2;
b455159c
LG		 1748
1749 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1750 return -EINVAL;
1751
7077b19a
CG		 1752 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
1753 num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
1754 GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
1755 dpm_levels = table_member2;
b455159c
LG		 1756
1757 if (num_discrete_levels == 0 || dpm_levels == NULL)
1758 return -EINVAL;
1759
1760 *num_states = num_discrete_levels;
1761 for (i = 0; i < num_discrete_levels; i++) {
1762 /* convert to khz */
1763 *clocks_in_khz = (*dpm_levels) * 1000;
1764 clocks_in_khz++;
1765 dpm_levels++;
1766 }
1767
1768 return 0;
1769}
1770
1771static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1772 struct smu_temperature_range *range)
1773{
e02e4d51
EQ		 1774 struct smu_table_context *table_context = &smu->smu_table;
1775 struct smu_11_0_7_powerplay_table *powerplay_table =
1776 table_context->power_play_table;
7077b19a
CG		 1777 uint16_t *table_member;
1778 uint16_t temp_edge, temp_hotspot, temp_mem;
b455159c 1779
2b1f12a2 1780 if (!range)
b455159c
LG		 1781 return -EINVAL;
1782
0540eced
EQ		 1783 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1784
7077b19a
CG		 1785 GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
1786 temp_edge = table_member[TEMP_EDGE];
1787 temp_hotspot = table_member[TEMP_HOTSPOT];
1788 temp_mem = table_member[TEMP_MEM];
1789
1790 range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1791 range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
2b1f12a2 1792 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a
CG		 1793 range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1794 range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
2b1f12a2 1795 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a
CG		 1796 range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1797 range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
b455159c 1798 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a 1799
e02e4d51 1800 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
b455159c
LG		 1801
1802 return 0;
1803}
1804
1805static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1806 bool disable_memory_clock_switch)
1807{
1808 int ret = 0;
1809 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1810 (struct smu_11_0_max_sustainable_clocks *)
1811 smu->smu_table.max_sustainable_clocks;
1812 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1813 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1814
1815 if(smu->disable_uclk_switch == disable_memory_clock_switch)
1816 return 0;
1817
1818 if(disable_memory_clock_switch)
661b94f5 1819 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
b455159c 1820 else
661b94f5 1821 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
b455159c
LG		 1822
1823 if(!ret)
1824 smu->disable_uclk_switch = disable_memory_clock_switch;
1825
1826 return ret;
1827}
1828
488f211d
EQ		 1829static int sienna_cichlid_get_power_limit(struct smu_context *smu,
1830 uint32_t *current_power_limit,
1831 uint32_t *default_power_limit,
1832 uint32_t *max_power_limit)
b455159c 1833{
1e239fdd
EQ		 1834 struct smu_11_0_7_powerplay_table *powerplay_table =
1835 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
1e239fdd 1836 uint32_t power_limit, od_percent;
7077b19a
CG		 1837 uint16_t *table_member;
1838
1839 GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
1e239fdd
EQ		 1840
1841 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1e239fdd 1842 power_limit =
7077b19a 1843 table_member[PPT_THROTTLER_PPT0];
1e239fdd 1844 }
b455159c 1845
488f211d
EQ		 1846 if (current_power_limit)
1847 *current_power_limit = power_limit;
1848 if (default_power_limit)
1849 *default_power_limit = power_limit;
1e239fdd 1850
488f211d
EQ		 1851 if (max_power_limit) {
1852 if (smu->od_enabled) {
1853 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
1e239fdd 1854
488f211d
EQ		 1855 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1856
1857 power_limit *= (100 + od_percent);
1858 power_limit /= 100;
1859 }
1860 *max_power_limit = power_limit;
b455159c
LG		 1861 }
1862
b455159c
LG		 1863 return 0;
1864}
1865
08ccfe08
LG		 1866static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1867 uint32_t pcie_gen_cap,
1868 uint32_t pcie_width_cap)
1869{
0b590970 1870 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
7077b19a 1871
08ccfe08 1872 uint32_t smu_pcie_arg;
7077b19a 1873 uint8_t *table_member1, *table_member2;
0b590970 1874 int ret, i;
08ccfe08 1875
7077b19a
CG		 1876 GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
1877 GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
1878
0b590970
EQ		 1879 /* lclk dpm table setup */
1880 for (i = 0; i < MAX_PCIE_CONF; i++) {
7077b19a
CG		 1881 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = table_member1[i];
1882 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = table_member2[i];
0b590970 1883 }
08ccfe08
LG		 1884
1885 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1886 smu_pcie_arg = (i << 16) |
7077b19a
CG		 1887 ((table_member1[i] <= pcie_gen_cap) ?
1888 (table_member1[i] << 8) :
1889 (pcie_gen_cap << 8)) |
1890 ((table_member2[i] <= pcie_width_cap) ?
1891 table_member2[i] :
1892 pcie_width_cap);
08ccfe08 1893
66c86828 1894 ret = smu_cmn_send_smc_msg_with_param(smu,
7077b19a
CG		 1895 SMU_MSG_OverridePcieParameters,
1896 smu_pcie_arg,
1897 NULL);
08ccfe08
LG		 1898 if (ret)
1899 return ret;
1900
7077b19a 1901 if (table_member1[i] > pcie_gen_cap)
08ccfe08 1902 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
7077b19a 1903 if (table_member2[i] > pcie_width_cap)
08ccfe08
LG		 1904 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1905 }
1906
1907 return 0;
1908}
1909
38ed7b09 1910static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
258d290c
LG		 1911 enum smu_clk_type clk_type,
1912 uint32_t *min, uint32_t *max)
1913{
1914 struct amdgpu_device *adev = smu->adev;
1915 int ret;
1916
1917 if (clk_type == SMU_GFXCLK)
1918 amdgpu_gfx_off_ctrl(adev, false);
1919 ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
1920 if (clk_type == SMU_GFXCLK)
1921 amdgpu_gfx_off_ctrl(adev, true);
1922
1923 return ret;
1924}
1925
aa75fa34
EQ		 1926static void sienna_cichlid_dump_od_table(struct smu_context *smu,
1927 OverDriveTable_t *od_table)
1928{
a2b6df4f
EQ		 1929 struct amdgpu_device *adev = smu->adev;
1930 uint32_t smu_version;
1931
aa75fa34
EQ		 1932 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
1933 od_table->GfxclkFmax);
1934 dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
1935 od_table->UclkFmax);
a2b6df4f
EQ		 1936
1937 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1938 if (!((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1939 (smu_version < 0x003a2900)))
1940 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
aa75fa34
EQ		 1941}
1942
1943static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
1944{
1945 OverDriveTable_t *od_table =
1946 (OverDriveTable_t *)smu->smu_table.overdrive_table;
1947 OverDriveTable_t *boot_od_table =
1948 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
b521be9b
EQ		 1949 OverDriveTable_t *user_od_table =
1950 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
aa75fa34
EQ		 1951 int ret = 0;
1952
b521be9b
EQ		 1953 /*
1954 * For S3/S4/Runpm resume, no need to setup those overdrive tables again as
1955 * - either they already have the default OD settings got during cold bootup
1956 * - or they have some user customized OD settings which cannot be overwritten
1957 */
1958 if (smu->adev->in_suspend)
1959 return 0;
1960
aa75fa34 1961 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
b521be9b 1962 0, (void *)boot_od_table, false);
aa75fa34
EQ		 1963 if (ret) {
1964 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
1965 return ret;
1966 }
1967
b521be9b 1968 sienna_cichlid_dump_od_table(smu, boot_od_table);
aa75fa34 1969
b521be9b
EQ		 1970 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
1971 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
aa75fa34
EQ		 1972
1973 return 0;
1974}
1975
37a58f69
EQ		 1976static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
1977 struct smu_11_0_7_overdrive_table *od_table,
1978 enum SMU_11_0_7_ODSETTING_ID setting,
1979 uint32_t value)
1980{
1981 if (value < od_table->min[setting]) {
1982 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
1983 setting, value, od_table->min[setting]);
1984 return -EINVAL;
1985 }
1986 if (value > od_table->max[setting]) {
1987 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
1988 setting, value, od_table->max[setting]);
1989 return -EINVAL;
1990 }
1991
1992 return 0;
1993}
1994
1995static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
1996 enum PP_OD_DPM_TABLE_COMMAND type,
1997 long input[], uint32_t size)
1998{
1999 struct smu_table_context *table_context = &smu->smu_table;
2000 OverDriveTable_t *od_table =
2001 (OverDriveTable_t *)table_context->overdrive_table;
2002 struct smu_11_0_7_overdrive_table *od_settings =
2003 (struct smu_11_0_7_overdrive_table *)smu->od_settings;
a2b6df4f 2004 struct amdgpu_device *adev = smu->adev;
37a58f69
EQ		 2005 enum SMU_11_0_7_ODSETTING_ID freq_setting;
2006 uint16_t *freq_ptr;
2007 int i, ret = 0;
a2b6df4f 2008 uint32_t smu_version;
37a58f69
EQ		 2009
2010 if (!smu->od_enabled) {
2011 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2012 return -EINVAL;
2013 }
2014
2015 if (!smu->od_settings) {
2016 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2017 return -ENOENT;
2018 }
2019
2020 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2021 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2022 return -EINVAL;
2023 }
2024
2025 switch (type) {
2026 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2027 if (!sienna_cichlid_is_od_feature_supported(od_settings,
2028 SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
2029 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2030 return -ENOTSUPP;
2031 }
2032
2033 for (i = 0; i < size; i += 2) {
2034 if (i + 2 > size) {
2035 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2036 return -EINVAL;
2037 }
2038
2039 switch (input[i]) {
2040 case 0:
2041 if (input[i + 1] > od_table->GfxclkFmax) {
2042 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2043 input[i + 1], od_table->GfxclkFmax);
2044 return -EINVAL;
2045 }
2046
2047 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
2048 freq_ptr = &od_table->GfxclkFmin;
2049 break;
2050
2051 case 1:
2052 if (input[i + 1] < od_table->GfxclkFmin) {
2053 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2054 input[i + 1], od_table->GfxclkFmin);
2055 return -EINVAL;
2056 }
2057
2058 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
2059 freq_ptr = &od_table->GfxclkFmax;
2060 break;
2061
2062 default:
2063 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2064 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2065 return -EINVAL;
2066 }
2067
2068 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2069 freq_setting, input[i + 1]);
2070 if (ret)
2071 return ret;
2072
2073 *freq_ptr = (uint16_t)input[i + 1];
2074 }
2075 break;
2076
2077 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2078 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
2079 dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2080 return -ENOTSUPP;
2081 }
2082
2083 for (i = 0; i < size; i += 2) {
2084 if (i + 2 > size) {
2085 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2086 return -EINVAL;
2087 }
2088
2089 switch (input[i]) {
2090 case 0:
2091 if (input[i + 1] > od_table->UclkFmax) {
2092 dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2093 input[i + 1], od_table->UclkFmax);
2094 return -EINVAL;
2095 }
2096
2097 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
2098 freq_ptr = &od_table->UclkFmin;
2099 break;
2100
2101 case 1:
2102 if (input[i + 1] < od_table->UclkFmin) {
2103 dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2104 input[i + 1], od_table->UclkFmin);
2105 return -EINVAL;
2106 }
2107
2108 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
2109 freq_ptr = &od_table->UclkFmax;
2110 break;
2111
2112 default:
2113 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2114 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2115 return -EINVAL;
2116 }
2117
2118 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2119 freq_setting, input[i + 1]);
2120 if (ret)
2121 return ret;
2122
2123 *freq_ptr = (uint16_t)input[i + 1];
2124 }
2125 break;
2126
2127 case PP_OD_RESTORE_DEFAULT_TABLE:
2128 memcpy(table_context->overdrive_table,
2129 table_context->boot_overdrive_table,
2130 sizeof(OverDriveTable_t));
2131 fallthrough;
2132
2133 case PP_OD_COMMIT_DPM_TABLE:
b521be9b
EQ		 2134 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2135 sienna_cichlid_dump_od_table(smu, od_table);
2136 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2137 if (ret) {
2138 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2139 return ret;
2140 }
2141 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2142 smu->user_dpm_profile.user_od = true;
37a58f69 2143
b521be9b
EQ		 2144 if (!memcmp(table_context->user_overdrive_table,
2145 table_context->boot_overdrive_table,
2146 sizeof(OverDriveTable_t)))
2147 smu->user_dpm_profile.user_od = false;
37a58f69
EQ		 2148 }
2149 break;
2150
a2b6df4f
EQ		 2151 case PP_OD_EDIT_VDDGFX_OFFSET:
2152 if (size != 1) {
2153 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2154 return -EINVAL;
2155 }
2156
2157 /*
2158 * OD GFX Voltage Offset functionality is supported only by 58.41.0
2159 * and onwards SMU firmwares.
2160 */
2161 smu_cmn_get_smc_version(smu, NULL, &smu_version);
2162 if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
2163 (smu_version < 0x003a2900)) {
2164 dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2165 "only by 58.41.0 and onwards SMU firmwares!\n");
2166 return -EOPNOTSUPP;
2167 }
2168
2169 od_table->VddGfxOffset = (int16_t)input[0];
2170
2171 sienna_cichlid_dump_od_table(smu, od_table);
2172 break;
2173
37a58f69
EQ		 2174 default:
2175 return -ENOSYS;
2176 }
2177
2178 return ret;
2179}
2180
66b8a9c0
JC		 2181static int sienna_cichlid_run_btc(struct smu_context *smu)
2182{
2183 return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2184}
2185
13d75ead
EQ		 2186static int sienna_cichlid_baco_enter(struct smu_context *smu)
2187{
2188 struct amdgpu_device *adev = smu->adev;
2189
2190 if (adev->in_runpm)
2191 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2192 else
2193 return smu_v11_0_baco_enter(smu);
2194}
2195
2196static int sienna_cichlid_baco_exit(struct smu_context *smu)
2197{
2198 struct amdgpu_device *adev = smu->adev;
2199
2200 if (adev->in_runpm) {
2201 /* Wait for PMFW handling for the Dstate change */
2202 msleep(10);
2203 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2204 } else {
2205 return smu_v11_0_baco_exit(smu);
2206 }
2207}
2208
ea8139d8
WS		 2209static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2210{
2211 struct amdgpu_device *adev = smu->adev;
2212 uint32_t val;
2213 u32 smu_version;
2214
2215 /**
2216 * SRIOV env will not support SMU mode1 reset
2217 * PM FW support mode1 reset from 58.26
2218 */
a7bae061 2219 smu_cmn_get_smc_version(smu, NULL, &smu_version);
ea8139d8
WS		 2220 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
2221 return false;
2222
2223 /**
2224 * mode1 reset relies on PSP, so we should check if
2225 * PSP is alive.
2226 */
2227 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2228 return val != 0x0;
2229}
2230
7077b19a
CG		 2231static void beige_goby_dump_pptable(struct smu_context *smu)
2232{
2233 struct smu_table_context *table_context = &smu->smu_table;
2234 PPTable_beige_goby_t *pptable = table_context->driver_pptable;
2235 int i;
2236
2237 dev_info(smu->adev->dev, "Dumped PPTable:\n");
2238
2239 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2240 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2241 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2242
2243 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2244 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2245 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2246 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2247 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2248 }
2249
2250 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2251 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2252 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2253 }
2254
2255 for (i = 0; i < TEMP_COUNT; i++) {
2256 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2257 }
2258
2259 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2260 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2261 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2262 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2263 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2264
2265 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2266 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2267 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2268 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2269 }
2270 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2271
2272 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2273
2274 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2275 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2276 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2277 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2278
2279 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2280
2281 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2282
2283 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2284 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2285 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2286 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2287
2288 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2289 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2290
2291 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2292 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2293 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2294 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2295 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2296 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2297 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2298 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2299
2300 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2301 " .VoltageMode = 0x%02x\n"
2302 " .SnapToDiscrete = 0x%02x\n"
2303 " .NumDiscreteLevels = 0x%02x\n"
2304 " .padding = 0x%02x\n"
2305 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2306 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2307 " .SsFmin = 0x%04x\n"
2308 " .Padding_16 = 0x%04x\n",
2309 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2310 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2311 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2312 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2313 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2314 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2315 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2316 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2317 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2318 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2319 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2320
2321 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2322 " .VoltageMode = 0x%02x\n"
2323 " .SnapToDiscrete = 0x%02x\n"
2324 " .NumDiscreteLevels = 0x%02x\n"
2325 " .padding = 0x%02x\n"
2326 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2327 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2328 " .SsFmin = 0x%04x\n"
2329 " .Padding_16 = 0x%04x\n",
2330 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2331 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2332 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2333 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2334 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2335 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2336 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2337 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2338 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2339 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2340 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2341
2342 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2343 " .VoltageMode = 0x%02x\n"
2344 " .SnapToDiscrete = 0x%02x\n"
2345 " .NumDiscreteLevels = 0x%02x\n"
2346 " .padding = 0x%02x\n"
2347 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2348 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2349 " .SsFmin = 0x%04x\n"
2350 " .Padding_16 = 0x%04x\n",
2351 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2352 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2353 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2354 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2355 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2356 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2357 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2358 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2359 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2360 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2361 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2362
2363 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2364 " .VoltageMode = 0x%02x\n"
2365 " .SnapToDiscrete = 0x%02x\n"
2366 " .NumDiscreteLevels = 0x%02x\n"
2367 " .padding = 0x%02x\n"
2368 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2369 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2370 " .SsFmin = 0x%04x\n"
2371 " .Padding_16 = 0x%04x\n",
2372 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2373 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2374 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2375 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2376 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2377 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2378 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2379 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2380 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2381 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2382 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2383
2384 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2385 " .VoltageMode = 0x%02x\n"
2386 " .SnapToDiscrete = 0x%02x\n"
2387 " .NumDiscreteLevels = 0x%02x\n"
2388 " .padding = 0x%02x\n"
2389 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2390 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2391 " .SsFmin = 0x%04x\n"
2392 " .Padding_16 = 0x%04x\n",
2393 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2394 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2395 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2396 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2397 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2398 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2399 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2400 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2401 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2402 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2403 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2404
2405 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2406 " .VoltageMode = 0x%02x\n"
2407 " .SnapToDiscrete = 0x%02x\n"
2408 " .NumDiscreteLevels = 0x%02x\n"
2409 " .padding = 0x%02x\n"
2410 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2411 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2412 " .SsFmin = 0x%04x\n"
2413 " .Padding_16 = 0x%04x\n",
2414 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2415 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2416 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2417 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2418 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2419 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2420 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2421 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2422 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2423 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2424 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2425
2426 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2427 " .VoltageMode = 0x%02x\n"
2428 " .SnapToDiscrete = 0x%02x\n"
2429 " .NumDiscreteLevels = 0x%02x\n"
2430 " .padding = 0x%02x\n"
2431 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2432 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2433 " .SsFmin = 0x%04x\n"
2434 " .Padding_16 = 0x%04x\n",
2435 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2436 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2437 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2438 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2439 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2440 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2441 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2442 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2443 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2444 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2445 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2446
2447 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2448 " .VoltageMode = 0x%02x\n"
2449 " .SnapToDiscrete = 0x%02x\n"
2450 " .NumDiscreteLevels = 0x%02x\n"
2451 " .padding = 0x%02x\n"
2452 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2453 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2454 " .SsFmin = 0x%04x\n"
2455 " .Padding_16 = 0x%04x\n",
2456 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2457 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2458 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2459 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2460 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2461 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2462 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2463 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2464 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2465 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2466 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2467
2468 dev_info(smu->adev->dev, "FreqTableGfx\n");
2469 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2470 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2471
2472 dev_info(smu->adev->dev, "FreqTableVclk\n");
2473 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2474 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2475
2476 dev_info(smu->adev->dev, "FreqTableDclk\n");
2477 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2478 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2479
2480 dev_info(smu->adev->dev, "FreqTableSocclk\n");
2481 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2482 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2483
2484 dev_info(smu->adev->dev, "FreqTableUclk\n");
2485 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2486 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2487
2488 dev_info(smu->adev->dev, "FreqTableFclk\n");
2489 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2490 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2491
2492 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2493 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2494 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2495 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2496 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2497 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2498 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2499 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2500 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2501
2502 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2503 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2504 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2505
2506 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2507 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2508
2509 dev_info(smu->adev->dev, "Mp0clkFreq\n");
2510 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2511 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2512
2513 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2514 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2515 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2516
2517 dev_info(smu->adev->dev, "MemVddciVoltage\n");
2518 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2519 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2520
2521 dev_info(smu->adev->dev, "MemMvddVoltage\n");
2522 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2523 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2524
2525 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2526 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2527 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2528 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2529 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2530
2531 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2532
2533 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2534 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2535 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2536 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2537 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2538 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2539 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2540 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2541 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2542 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2543 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2544
2545 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2546 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2547 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2548 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2549 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2550 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2551
2552 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2553 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2554 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2555 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2556 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2557
2558 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2559 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2560 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2561
2562 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2563 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2564 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2565 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2566
2567 dev_info(smu->adev->dev, "UclkDpmPstates\n");
2568 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2569 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2570
2571 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2572 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2573 pptable->UclkDpmSrcFreqRange.Fmin);
2574 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2575 pptable->UclkDpmSrcFreqRange.Fmax);
2576 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2577 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2578 pptable->UclkDpmTargFreqRange.Fmin);
2579 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2580 pptable->UclkDpmTargFreqRange.Fmax);
2581 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2582 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2583
2584 dev_info(smu->adev->dev, "PcieGenSpeed\n");
2585 for (i = 0; i < NUM_LINK_LEVELS; i++)
2586 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2587
2588 dev_info(smu->adev->dev, "PcieLaneCount\n");
2589 for (i = 0; i < NUM_LINK_LEVELS; i++)
2590 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2591
2592 dev_info(smu->adev->dev, "LclkFreq\n");
2593 for (i = 0; i < NUM_LINK_LEVELS; i++)
2594 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2595
2596 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2597 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2598
2599 dev_info(smu->adev->dev, "FanGain\n");
2600 for (i = 0; i < TEMP_COUNT; i++)
2601 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2602
2603 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2604 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2605 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2606 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2607 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2608 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2609 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2610 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2611 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2612 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2613 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2614 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2615
2616 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2617 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2618 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2619 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2620
2621 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2622 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2623 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2624 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2625
2626 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2627 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2628 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2629 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2630 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2631 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2632 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2633 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2634 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2635 pptable->dBtcGbGfxPll.a,
2636 pptable->dBtcGbGfxPll.b,
2637 pptable->dBtcGbGfxPll.c);
2638 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2639 pptable->dBtcGbGfxDfll.a,
2640 pptable->dBtcGbGfxDfll.b,
2641 pptable->dBtcGbGfxDfll.c);
2642 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2643 pptable->dBtcGbSoc.a,
2644 pptable->dBtcGbSoc.b,
2645 pptable->dBtcGbSoc.c);
2646 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2647 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2648 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2649 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2650 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2651 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2652
2653 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2654 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2655 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
2656 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2657 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
2658 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2659 }
2660
2661 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2662 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2663 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2664 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2665 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2666 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2667 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2668 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2669
2670 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2671 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2672
2673 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2674 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2675 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2676 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2677
2678 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2679 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2680 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2681 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2682
2683 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2684 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2685
2686 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2687 for (i = 0; i < NUM_XGMI_LEVELS; i++)
2688 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2689 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2690 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2691
2692 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2693 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2694 pptable->ReservedEquation0.a,
2695 pptable->ReservedEquation0.b,
2696 pptable->ReservedEquation0.c);
2697 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2698 pptable->ReservedEquation1.a,
2699 pptable->ReservedEquation1.b,
2700 pptable->ReservedEquation1.c);
2701 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2702 pptable->ReservedEquation2.a,
2703 pptable->ReservedEquation2.b,
2704 pptable->ReservedEquation2.c);
2705 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2706 pptable->ReservedEquation3.a,
2707 pptable->ReservedEquation3.b,
2708 pptable->ReservedEquation3.c);
2709
2710 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2711 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2712 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2713 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2714 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2715 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2716 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2717 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2718
2719 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2720 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2721 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2722 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2723 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2724 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2725
2726 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2727 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2728 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
2729 pptable->I2cControllers[i].Enabled);
2730 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
2731 pptable->I2cControllers[i].Speed);
2732 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
2733 pptable->I2cControllers[i].SlaveAddress);
2734 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
2735 pptable->I2cControllers[i].ControllerPort);
2736 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
2737 pptable->I2cControllers[i].ControllerName);
2738 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
2739 pptable->I2cControllers[i].ThermalThrotter);
2740 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
2741 pptable->I2cControllers[i].I2cProtocol);
2742 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
2743 pptable->I2cControllers[i].PaddingConfig);
2744 }
2745
2746 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2747 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2748 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2749 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2750
2751 dev_info(smu->adev->dev, "Board Parameters:\n");
2752 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2753 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2754 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2755 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2756 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2757 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2758 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2759 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2760
2761 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2762 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2763 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2764
2765 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2766 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2767 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2768
2769 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2770 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2771 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2772
2773 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2774 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2775 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2776
2777 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2778
2779 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2780 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2781 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2782 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2783 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2784 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2785 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2786 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2787 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2788 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2789 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2790 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2791 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2792 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2793 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2794 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2795
2796 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2797 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2798 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
2799
2800 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2801 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2802 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
2803
2804 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
2805 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2806
2807 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2808 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2809 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2810
2811 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2812 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2813 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2814 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2815 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2816
2817 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2818 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2819
2820 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
2821 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2822 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2823 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
2824 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2825 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2826 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
2827 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2828 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2829 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
2830 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2831 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2832
2833 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2834 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2835 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2836 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2837
2838 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2839 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2840 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2841 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2842 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2843 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2844 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2845 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2846 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2847 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2848 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2849
2850 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2851 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2852 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2853 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2854 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2855 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2856 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2857 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2858}
2859
b455159c
LG		 2860static void sienna_cichlid_dump_pptable(struct smu_context *smu)
2861{
2862 struct smu_table_context *table_context = &smu->smu_table;
2863 PPTable_t *pptable = table_context->driver_pptable;
2864 int i;
2865
7077b19a
CG		 2866 if (smu->adev->asic_type == CHIP_BEIGE_GOBY) {
2867 beige_goby_dump_pptable(smu);
2868 return;
2869 }
2870
d9811cfc 2871 dev_info(smu->adev->dev, "Dumped PPTable:\n");
b455159c 2872
d9811cfc
EQ		 2873 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2874 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2875 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
b455159c
LG		 2876
2877 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
d9811cfc
EQ		 2878 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2879 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2880 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2881 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
b455159c
LG		 2882 }
2883
2884 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
d9811cfc
EQ		 2885 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2886 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
b455159c
LG		 2887 }
2888
2889 for (i = 0; i < TEMP_COUNT; i++) {
d9811cfc 2890 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
b455159c
LG		 2891 }
2892
d9811cfc
EQ		 2893 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2894 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2895 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2896 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2897 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
b455159c 2898
d9811cfc 2899 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
b455159c 2900 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
d9811cfc
EQ		 2901 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2902 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
b455159c 2903 }
d9811cfc
EQ		 2904 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2905
2906 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2907
2908 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2909 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2910 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2911 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2912
2913 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2914 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
2915
2916 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2917 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
2918 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
2919 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
2920
2921 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2922 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2923 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2924 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2925
2926 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2927 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2928
2929 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2930 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2931 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2932 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2933 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2934 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2935 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2936 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2937
2938 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
b455159c
LG		 2939 " .VoltageMode = 0x%02x\n"
2940 " .SnapToDiscrete = 0x%02x\n"
2941 " .NumDiscreteLevels = 0x%02x\n"
2942 " .padding = 0x%02x\n"
2943 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2944 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2945 " .SsFmin = 0x%04x\n"
2946 " .Padding_16 = 0x%04x\n",
2947 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2948 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2949 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2950 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2951 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2952 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2953 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2954 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2955 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2956 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2957 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2958
d9811cfc 2959 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
b455159c
LG		 2960 " .VoltageMode = 0x%02x\n"
2961 " .SnapToDiscrete = 0x%02x\n"
2962 " .NumDiscreteLevels = 0x%02x\n"
2963 " .padding = 0x%02x\n"
2964 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2965 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2966 " .SsFmin = 0x%04x\n"
2967 " .Padding_16 = 0x%04x\n",
2968 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2969 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2970 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2971 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2972 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2973 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2974 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2975 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2976 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2977 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2978 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2979
d9811cfc 2980 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
b455159c
LG		 2981 " .VoltageMode = 0x%02x\n"
2982 " .SnapToDiscrete = 0x%02x\n"
2983 " .NumDiscreteLevels = 0x%02x\n"
2984 " .padding = 0x%02x\n"
2985 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2986 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2987 " .SsFmin = 0x%04x\n"
2988 " .Padding_16 = 0x%04x\n",
2989 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2990 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2991 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2992 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2993 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2994 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2995 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2996 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2997 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2998 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2999 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
3000
d9811cfc 3001 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
b455159c
LG		 3002 " .VoltageMode = 0x%02x\n"
3003 " .SnapToDiscrete = 0x%02x\n"
3004 " .NumDiscreteLevels = 0x%02x\n"
3005 " .padding = 0x%02x\n"
3006 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3007 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3008 " .SsFmin = 0x%04x\n"
3009 " .Padding_16 = 0x%04x\n",
3010 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
3011 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
3012 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
3013 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
3014 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
3015 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
3016 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
3017 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
3018 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
3019 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
3020 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
3021
d9811cfc 3022 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
b455159c
LG		 3023 " .VoltageMode = 0x%02x\n"
3024 " .SnapToDiscrete = 0x%02x\n"
3025 " .NumDiscreteLevels = 0x%02x\n"
3026 " .padding = 0x%02x\n"
3027 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3028 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3029 " .SsFmin = 0x%04x\n"
3030 " .Padding_16 = 0x%04x\n",
3031 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
3032 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
3033 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
3034 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
3035 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
3036 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
3037 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
3038 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
3039 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
3040 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
3041 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
3042
d9811cfc 3043 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
b455159c
LG		 3044 " .VoltageMode = 0x%02x\n"
3045 " .SnapToDiscrete = 0x%02x\n"
3046 " .NumDiscreteLevels = 0x%02x\n"
3047 " .padding = 0x%02x\n"
3048 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3049 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3050 " .SsFmin = 0x%04x\n"
3051 " .Padding_16 = 0x%04x\n",
3052 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
3053 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
3054 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
3055 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
3056 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
3057 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
3058 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
3059 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
3060 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
3061 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
3062 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
3063
d9811cfc 3064 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
b455159c
LG		 3065 " .VoltageMode = 0x%02x\n"
3066 " .SnapToDiscrete = 0x%02x\n"
3067 " .NumDiscreteLevels = 0x%02x\n"
3068 " .padding = 0x%02x\n"
3069 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3070 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3071 " .SsFmin = 0x%04x\n"
3072 " .Padding_16 = 0x%04x\n",
3073 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
3074 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
3075 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
3076 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
3077 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
3078 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
3079 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
3080 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
3081 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
3082 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
3083 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
3084
d9811cfc 3085 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
b455159c
LG		 3086 " .VoltageMode = 0x%02x\n"
3087 " .SnapToDiscrete = 0x%02x\n"
3088 " .NumDiscreteLevels = 0x%02x\n"
3089 " .padding = 0x%02x\n"
3090 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3091 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3092 " .SsFmin = 0x%04x\n"
3093 " .Padding_16 = 0x%04x\n",
3094 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
3095 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
3096 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
3097 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
3098 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
3099 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
3100 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
3101 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
3102 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
3103 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
3104 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
3105
d9811cfc 3106 dev_info(smu->adev->dev, "FreqTableGfx\n");
b455159c 3107 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
d9811cfc 3108 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
b455159c 3109
d9811cfc 3110 dev_info(smu->adev->dev, "FreqTableVclk\n");
b455159c 3111 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
d9811cfc 3112 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
b455159c 3113
d9811cfc 3114 dev_info(smu->adev->dev, "FreqTableDclk\n");
b455159c 3115 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
d9811cfc 3116 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
b455159c 3117
d9811cfc 3118 dev_info(smu->adev->dev, "FreqTableSocclk\n");
b455159c 3119 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
d9811cfc 3120 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
b455159c 3121
d9811cfc 3122 dev_info(smu->adev->dev, "FreqTableUclk\n");
b455159c 3123 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3124 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
b455159c 3125
d9811cfc 3126 dev_info(smu->adev->dev, "FreqTableFclk\n");
b455159c 3127 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
d9811cfc
EQ		 3128 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
3129
d9811cfc
EQ		 3130 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
3131 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
3132 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
3133 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
3134 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
3135 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
3136 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
3137 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
3138 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
3139
3140 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
b455159c 3141 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3142 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
b455159c 3143
d9811cfc
EQ		 3144 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
3145 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
b455159c 3146
d9811cfc 3147 dev_info(smu->adev->dev, "Mp0clkFreq\n");
b455159c 3148 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc 3149 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
b455159c 3150
d9811cfc 3151 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
b455159c 3152 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc 3153 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
b455159c 3154
d9811cfc 3155 dev_info(smu->adev->dev, "MemVddciVoltage\n");
b455159c 3156 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3157 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
b455159c 3158
d9811cfc 3159 dev_info(smu->adev->dev, "MemMvddVoltage\n");
b455159c 3160 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc
EQ		 3161 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
3162
3163 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
3164 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
3165 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
3166 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
3167 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
3168
3169 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
3170
3171 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
3172 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
3173 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
3174 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
3175 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
3176 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
3177 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
3178 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
3179 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
3180 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
3181 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
3182
3183 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
3184 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
3185 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
3186 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
3187 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
3188 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
3189
3190 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
3191 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
3192 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
3193 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
3194 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
3195
3196 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
b455159c 3197 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
d9811cfc 3198 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
b455159c 3199
d9811cfc
EQ		 3200 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
3201 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
3202 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
3203 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
b455159c 3204
d9811cfc 3205 dev_info(smu->adev->dev, "UclkDpmPstates\n");
b455159c 3206 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3207 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
b455159c 3208
d9811cfc
EQ		 3209 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
3210 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
b455159c 3211 pptable->UclkDpmSrcFreqRange.Fmin);
d9811cfc 3212 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
b455159c 3213 pptable->UclkDpmSrcFreqRange.Fmax);
d9811cfc
EQ		 3214 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
3215 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
b455159c 3216 pptable->UclkDpmTargFreqRange.Fmin);
d9811cfc 3217 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
b455159c 3218 pptable->UclkDpmTargFreqRange.Fmax);
d9811cfc
EQ		 3219 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
3220 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
b455159c 3221
d9811cfc 3222 dev_info(smu->adev->dev, "PcieGenSpeed\n");
b455159c 3223 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3224 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
b455159c 3225
d9811cfc 3226 dev_info(smu->adev->dev, "PcieLaneCount\n");
b455159c 3227 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3228 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
b455159c 3229
d9811cfc 3230 dev_info(smu->adev->dev, "LclkFreq\n");
b455159c 3231 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3232 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
b455159c 3233
d9811cfc
EQ		 3234 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
3235 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
b455159c 3236
d9811cfc 3237 dev_info(smu->adev->dev, "FanGain\n");
b455159c 3238 for (i = 0; i < TEMP_COUNT; i++)
d9811cfc
EQ		 3239 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
3240
3241 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
3242 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
3243 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
3244 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
3245 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
3246 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
3247 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
3248 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
3249 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
3250 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
3251 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
3252 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
3253
3254 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
3255 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
3256 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
3257 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
3258
3259 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
3260 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
3261 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
3262 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
3263
3264 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3265 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
3266 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
3267 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
d9811cfc 3268 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3269 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
3270 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
3271 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
d9811cfc 3272 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3273 pptable->dBtcGbGfxPll.a,
3274 pptable->dBtcGbGfxPll.b,
3275 pptable->dBtcGbGfxPll.c);
d9811cfc 3276 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3277 pptable->dBtcGbGfxDfll.a,
3278 pptable->dBtcGbGfxDfll.b,
3279 pptable->dBtcGbGfxDfll.c);
d9811cfc 3280 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3281 pptable->dBtcGbSoc.a,
3282 pptable->dBtcGbSoc.b,
3283 pptable->dBtcGbSoc.c);
d9811cfc 3284 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
b455159c
LG		 3285 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
3286 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
d9811cfc 3287 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
b455159c
LG		 3288 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
3289 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
3290
d9811cfc 3291 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
b455159c 3292 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
d9811cfc 3293 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
b455159c 3294 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
d9811cfc 3295 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
b455159c
LG		 3296 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
3297 }
3298
d9811cfc 3299 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3300 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
3301 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
3302 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
d9811cfc 3303 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3304 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
3305 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
3306 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
3307
d9811cfc
EQ		 3308 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
3309 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
b455159c 3310
d9811cfc
EQ		 3311 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
3312 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
3313 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
3314 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
b455159c 3315
d9811cfc
EQ		 3316 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
3317 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
3318 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
3319 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
b455159c 3320
d9811cfc
EQ		 3321 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
3322 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
b455159c 3323
d9811cfc 3324 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
b455159c 3325 for (i = 0; i < NUM_XGMI_LEVELS; i++)
d9811cfc
EQ		 3326 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
3327 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
3328 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
b455159c 3329
d9811cfc
EQ		 3330 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
3331 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3332 pptable->ReservedEquation0.a,
3333 pptable->ReservedEquation0.b,
3334 pptable->ReservedEquation0.c);
d9811cfc 3335 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3336 pptable->ReservedEquation1.a,
3337 pptable->ReservedEquation1.b,
3338 pptable->ReservedEquation1.c);
d9811cfc 3339 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3340 pptable->ReservedEquation2.a,
3341 pptable->ReservedEquation2.b,
3342 pptable->ReservedEquation2.c);
d9811cfc 3343 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3344 pptable->ReservedEquation3.a,
3345 pptable->ReservedEquation3.b,
3346 pptable->ReservedEquation3.c);
3347
d9811cfc
EQ		 3348 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3349 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3350 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3351 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3352 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3353 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3354 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3355 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
d9811cfc
EQ		 3356
3357 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3358 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3359 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3360 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3361 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3362 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
b455159c
LG		 3363
3364 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
d9811cfc
EQ		 3365 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3366 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
b455159c 3367 pptable->I2cControllers[i].Enabled);
d9811cfc 3368 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
b455159c 3369 pptable->I2cControllers[i].Speed);
d9811cfc 3370 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
b455159c 3371 pptable->I2cControllers[i].SlaveAddress);
d9811cfc 3372 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
b455159c 3373 pptable->I2cControllers[i].ControllerPort);
d9811cfc 3374 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
b455159c 3375 pptable->I2cControllers[i].ControllerName);
d9811cfc 3376 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
b455159c 3377 pptable->I2cControllers[i].ThermalThrotter);
d9811cfc 3378 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
b455159c 3379 pptable->I2cControllers[i].I2cProtocol);
d9811cfc 3380 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
b455159c
LG		 3381 pptable->I2cControllers[i].PaddingConfig);
3382 }
3383
d9811cfc
EQ		 3384 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3385 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3386 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3387 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3388
3389 dev_info(smu->adev->dev, "Board Parameters:\n");
3390 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3391 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3392 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3393 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3394 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3395 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3396 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3397 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3398
3399 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3400 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3401 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3402
3403 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3404 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3405 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3406
3407 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3408 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3409 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3410
3411 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3412 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3413 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3414
3415 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3416
3417 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3418 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3419 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3420 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3421 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3422 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3423 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3424 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3425 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3426 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3427 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3428 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3429 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3430 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3431 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3432 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3433
3434 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3435 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3436 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3437
3438 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3439 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3440 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3441
f0f3d68e 3442 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
d9811cfc
EQ		 3443 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3444
3445 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3446 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3447 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3448
3449 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3450 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3451 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3452 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3453 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3454
3455 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3456 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3457
3458 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
b455159c 3459 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3460 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3461 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
b455159c 3462 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3463 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3464 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
b455159c 3465 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3466 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3467 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
b455159c 3468 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3469 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3470
3471 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3472 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3473 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3474 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3475
3476 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3477 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3478 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3479 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3480 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3481 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3482 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3483 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3484 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3485 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3486 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
d9811cfc
EQ		 3487
3488 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3489 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3490 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3491 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3492 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3493 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3494 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3495 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
b455159c
LG		 3496}
3497
5125c96a 3498static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
ebe57d0c 3499 struct i2c_msg *msg, int num_msgs)
bc50ca29 3500{
5125c96a 3501 struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
bc50ca29
AD		 3502 struct smu_table_context *smu_table = &adev->smu.smu_table;
3503 struct smu_table *table = &smu_table->driver_table;
5125c96a 3504 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
ebe57d0c
LT		 3505 int i, j, r, c;
3506 u16 dir;
d74a09c8 3507
5125c96a
AD		 3508 req = kzalloc(sizeof(*req), GFP_KERNEL);
3509 if (!req)
3510 return -ENOMEM;
bc50ca29 3511
5125c96a
AD		 3512 req->I2CcontrollerPort = 1;
3513 req->I2CSpeed = I2C_SPEED_FAST_400K;
ebe57d0c
LT		 3514 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
3515 dir = msg[0].flags & I2C_M_RD;
bc50ca29 3516
ebe57d0c
LT		 3517 for (c = i = 0; i < num_msgs; i++) {
3518 for (j = 0; j < msg[i].len; j++, c++) {
3519 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
bc50ca29 3520
5125c96a
AD		 3521 if (!(msg[i].flags & I2C_M_RD)) {
3522 /* write */
3523 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
ebe57d0c
LT		 3524 cmd->ReadWriteData = msg[i].buf[j];
3525 }
3526
3527 if ((dir ^ msg[i].flags) & I2C_M_RD) {
3528 /* The direction changes.
3529 */
3530 dir = msg[i].flags & I2C_M_RD;
3531 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
5125c96a 3532 }
14df5650 3533
ebe57d0c
LT		 3534 req->NumCmds++;
3535
14df5650
AG		 3536 /*
3537 * Insert STOP if we are at the last byte of either last
3538 * message for the transaction or the client explicitly
3539 * requires a STOP at this particular message.
3540 */
ebe57d0c
LT		 3541 if ((j == msg[i].len - 1) &&
3542 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
3543 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
5125c96a 3544 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
ebe57d0c 3545 }
5125c96a 3546 }
d74a09c8 3547 }
bc50ca29 3548 mutex_lock(&adev->smu.mutex);
5125c96a 3549 r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
bc50ca29 3550 mutex_unlock(&adev->smu.mutex);
5125c96a
AD		 3551 if (r)
3552 goto fail;
bc50ca29 3553
ebe57d0c
LT		 3554 for (c = i = 0; i < num_msgs; i++) {
3555 if (!(msg[i].flags & I2C_M_RD)) {
3556 c += msg[i].len;
3557 continue;
3558 }
3559 for (j = 0; j < msg[i].len; j++, c++) {
3560 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
bc50ca29 3561
ebe57d0c 3562 msg[i].buf[j] = cmd->ReadWriteData;
bc50ca29
AD		 3563 }
3564 }
ebe57d0c 3565 r = num_msgs;
bc50ca29 3566fail:
5125c96a 3567 kfree(req);
5125c96a 3568 return r;
bc50ca29
AD		 3569}
3570
3571static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
3572{
3573 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3574}
3575
3576
3577static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
3578 .master_xfer = sienna_cichlid_i2c_xfer,
3579 .functionality = sienna_cichlid_i2c_func,
3580};
3581
35ed2703 3582static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = {
c0838d3a 3583 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
16736627 3584 .max_read_len = MAX_SW_I2C_COMMANDS,
35ed2703 3585 .max_write_len = MAX_SW_I2C_COMMANDS,
16736627
LT		 3586 .max_comb_1st_msg_len = 2,
3587 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
35ed2703
AG		 3588};
3589
bc50ca29
AD		 3590static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
3591{
3592 struct amdgpu_device *adev = to_amdgpu_device(control);
3593 int res;
3594
bc50ca29 3595 control->owner = THIS_MODULE;
f4322d80 3596 control->class = I2C_CLASS_HWMON;
bc50ca29
AD		 3597 control->dev.parent = &adev->pdev->dev;
3598 control->algo = &sienna_cichlid_i2c_algo;
3599 snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
35ed2703 3600 control->quirks = &sienna_cichlid_i2c_control_quirks;
bc50ca29
AD		 3601
3602 res = i2c_add_adapter(control);
3603 if (res)
3604 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3605
3606 return res;
3607}
3608
3609static void sienna_cichlid_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
3610{
bc50ca29
AD		 3611 i2c_del_adapter(control);
3612}
3613
8ca78a0a
EQ		 3614static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
3615 void **table)
3616{
3617 struct smu_table_context *smu_table = &smu->smu_table;
f06d9511
GS		 3618 struct gpu_metrics_v1_3 *gpu_metrics =
3619 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
b4b0b79d
EQ		 3620 SmuMetricsExternal_t metrics_external;
3621 SmuMetrics_t *metrics =
3622 &(metrics_external.SmuMetrics);
be22e2b9
EQ		 3623 SmuMetrics_V2_t *metrics_v2 =
3624 &(metrics_external.SmuMetrics_V2);
c524c1c9 3625 struct amdgpu_device *adev = smu->adev;
be22e2b9
EQ		 3626 bool use_metrics_v2 = ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
3627 (smu->smc_fw_version >= 0x3A4300)) ? true : false;
3628 uint16_t average_gfx_activity;
8ca78a0a
EQ		 3629 int ret = 0;
3630
be22e2b9
EQ		 3631 mutex_lock(&smu->metrics_lock);
3632 ret = smu_cmn_get_metrics_table_locked(smu,
3633 &metrics_external,
3634 true);
3635 if (ret) {
3636 mutex_unlock(&smu->metrics_lock);
8ca78a0a 3637 return ret;
be22e2b9 3638 }
8ca78a0a 3639
f06d9511 3640 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
8ca78a0a 3641
be22e2b9
EQ		 3642 gpu_metrics->temperature_edge =
3643 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge;
3644 gpu_metrics->temperature_hotspot =
3645 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot;
3646 gpu_metrics->temperature_mem =
3647 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem;
3648 gpu_metrics->temperature_vrgfx =
3649 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx;
3650 gpu_metrics->temperature_vrsoc =
3651 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc;
3652 gpu_metrics->temperature_vrmem =
3653 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0;
3654
3655 gpu_metrics->average_gfx_activity =
3656 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3657 gpu_metrics->average_umc_activity =
3658 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity;
3659 gpu_metrics->average_mm_activity =
3660 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage;
3661
3662 gpu_metrics->average_socket_power =
3663 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower;
3664 gpu_metrics->energy_accumulator =
3665 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator;
3666
3667 average_gfx_activity = use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3668 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
3669 gpu_metrics->average_gfxclk_frequency =
3670 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs : metrics->AverageGfxclkFrequencyPostDs;
8ca78a0a 3671 else
be22e2b9
EQ		 3672 gpu_metrics->average_gfxclk_frequency =
3673 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs : metrics->AverageGfxclkFrequencyPreDs;
3674 gpu_metrics->average_uclk_frequency =
3675 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs : metrics->AverageUclkFrequencyPostDs;
3676 gpu_metrics->average_vclk0_frequency =
3677 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency;
3678 gpu_metrics->average_dclk0_frequency =
3679 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency;
3680 gpu_metrics->average_vclk1_frequency =
3681 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency;
3682 gpu_metrics->average_dclk1_frequency =
3683 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency;
3684
3685 gpu_metrics->current_gfxclk =
3686 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK];
3687 gpu_metrics->current_socclk =
3688 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK];
3689 gpu_metrics->current_uclk =
3690 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK];
3691 gpu_metrics->current_vclk0 =
3692 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0];
3693 gpu_metrics->current_dclk0 =
3694 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0];
3695 gpu_metrics->current_vclk1 =
3696 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1];
3697 gpu_metrics->current_dclk1 =
3698 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1];
3699
3700 gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu);
f06d9511 3701 gpu_metrics->indep_throttle_status =
be22e2b9 3702 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
f06d9511 3703 sienna_cichlid_throttler_map);
b4b0b79d 3704
be22e2b9 3705 gpu_metrics->current_fan_speed = use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
c524c1c9 3706
be22e2b9
EQ		 3707 if (((adev->asic_type == CHIP_SIENNA_CICHLID) && smu->smc_fw_version > 0x003A1E00) ||
3708 ((adev->asic_type == CHIP_NAVY_FLOUNDER) && smu->smc_fw_version > 0x00410400)) {
3709 gpu_metrics->pcie_link_width = use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
3710 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
c524c1c9
EQ		 3711 } else {
3712 gpu_metrics->pcie_link_width =
3713 smu_v11_0_get_current_pcie_link_width(smu);
3714 gpu_metrics->pcie_link_speed =
3715 smu_v11_0_get_current_pcie_link_speed(smu);
3716 }
8ca78a0a 3717
be22e2b9
EQ		 3718 mutex_unlock(&smu->metrics_lock);
3719
de4b7cd8
KW		 3720 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3721
8ca78a0a
EQ		 3722 *table = (void *)gpu_metrics;
3723
f06d9511 3724 return sizeof(struct gpu_metrics_v1_3);
8ca78a0a 3725}
bc50ca29 3726
05f39286
EQ		 3727static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
3728{
b804a75d
EQ		 3729 struct smu_table_context *table_context = &smu->smu_table;
3730 PPTable_t *smc_pptable = table_context->driver_pptable;
3731
3732 /*
3733 * Skip the MGpuFanBoost setting for those ASICs
3734 * which do not support it
3735 */
3736 if (!smc_pptable->MGpuFanBoostLimitRpm)
3737 return 0;
3738
05f39286
EQ		 3739 return smu_cmn_send_smc_msg_with_param(smu,
3740 SMU_MSG_SetMGpuFanBoostLimitRpm,
3741 0,
3742 NULL);
3743}
3744
76c71f00
EQ		 3745static int sienna_cichlid_gpo_control(struct smu_context *smu,
3746 bool enablement)
3747{
ac7804bb 3748 uint32_t smu_version;
76c71f00
EQ		 3749 int ret = 0;
3750
ac7804bb 3751
76c71f00 3752 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
ac7804bb
EQ		 3753 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
3754 if (ret)
3755 return ret;
3756
3757 if (enablement) {
3758 if (smu_version < 0x003a2500) {
3759 ret = smu_cmn_send_smc_msg_with_param(smu,
3760 SMU_MSG_SetGpoFeaturePMask,
3761 GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
3762 NULL);
3763 } else {
3764 ret = smu_cmn_send_smc_msg_with_param(smu,
3765 SMU_MSG_DisallowGpo,
3766 0,
3767 NULL);
3768 }
3769 } else {
3770 if (smu_version < 0x003a2500) {
3771 ret = smu_cmn_send_smc_msg_with_param(smu,
3772 SMU_MSG_SetGpoFeaturePMask,
3773 0,
3774 NULL);
3775 } else {
3776 ret = smu_cmn_send_smc_msg_with_param(smu,
3777 SMU_MSG_DisallowGpo,
3778 1,
3779 NULL);
3780 }
3781 }
76c71f00
EQ		 3782 }
3783
3784 return ret;
3785}
d7f52e29
EQ		 3786
3787static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
3788{
3789 uint32_t smu_version;
3790 int ret = 0;
3791
3792 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
3793 if (ret)
3794 return ret;
3795
3796 /*
3797 * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
3798 * onwards PMFWs.
3799 */
3800 if (smu_version < 0x003A2D00)
3801 return 0;
3802
3803 return smu_cmn_send_smc_msg_with_param(smu,
3804 SMU_MSG_Enable2ndUSB20Port,
3805 smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
3806 1 : 0,
3807 NULL);
3808}
3809
3810static int sienna_cichlid_system_features_control(struct smu_context *smu,
3811 bool en)
3812{
3813 int ret = 0;
3814
3815 if (en) {
3816 ret = sienna_cichlid_notify_2nd_usb20_port(smu);
3817 if (ret)
3818 return ret;
3819 }
3820
3821 return smu_v11_0_system_features_control(smu, en);
3822}
3823
1689fca0
EQ		 3824static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
3825 enum pp_mp1_state mp1_state)
3826{
9113a0fb
GC		 3827 int ret;
3828
1689fca0
EQ		 3829 switch (mp1_state) {
3830 case PP_MP1_STATE_UNLOAD:
9113a0fb
GC		 3831 ret = smu_cmn_set_mp1_state(smu, mp1_state);
3832 break;
1689fca0 3833 default:
9113a0fb
GC		 3834 /* Ignore others */
3835 ret = 0;
1689fca0
EQ		 3836 }
3837
9113a0fb 3838 return ret;
1689fca0
EQ		 3839}
3840
b455159c 3841static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
b455159c
LG		 3842 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
3843 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
f6b4b4a1 3844 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
6fb176a7 3845 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
bc50ca29
AD		 3846 .i2c_init = sienna_cichlid_i2c_control_init,
3847 .i2c_fini = sienna_cichlid_i2c_control_fini,
b455159c
LG		 3848 .print_clk_levels = sienna_cichlid_print_clk_levels,
3849 .force_clk_levels = sienna_cichlid_force_clk_levels,
3850 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
b455159c
LG		 3851 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
3852 .display_config_changed = sienna_cichlid_display_config_changed,
3853 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
b455159c 3854 .is_dpm_running = sienna_cichlid_is_dpm_running,
fb1f667e 3855 .get_fan_speed_percent = smu_v11_0_get_fan_speed_percent,
d9ca7567 3856 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
b455159c
LG		 3857 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
3858 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
b455159c
LG		 3859 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
3860 .read_sensor = sienna_cichlid_read_sensor,
3861 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
b2785e25 3862 .set_performance_level = smu_v11_0_set_performance_level,
b455159c
LG		 3863 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
3864 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
3865 .get_power_limit = sienna_cichlid_get_power_limit,
08ccfe08 3866 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
b455159c
LG		 3867 .dump_pptable = sienna_cichlid_dump_pptable,
3868 .init_microcode = smu_v11_0_init_microcode,
3869 .load_microcode = smu_v11_0_load_microcode,
c1b353b7 3870 .init_smc_tables = sienna_cichlid_init_smc_tables,
b455159c
LG		 3871 .fini_smc_tables = smu_v11_0_fini_smc_tables,
3872 .init_power = smu_v11_0_init_power,
3873 .fini_power = smu_v11_0_fini_power,
3874 .check_fw_status = smu_v11_0_check_fw_status,
4a13b4ce 3875 .setup_pptable = sienna_cichlid_setup_pptable,
b455159c 3876 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
b455159c 3877 .check_fw_version = smu_v11_0_check_fw_version,
caad2613 3878 .write_pptable = smu_cmn_write_pptable,
b455159c
LG		 3879 .set_driver_table_location = smu_v11_0_set_driver_table_location,
3880 .set_tool_table_location = smu_v11_0_set_tool_table_location,
3881 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
d7f52e29 3882 .system_features_control = sienna_cichlid_system_features_control,
66c86828
EQ		 3883 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
3884 .send_smc_msg = smu_cmn_send_smc_msg,
31157341 3885 .init_display_count = NULL,
b455159c 3886 .set_allowed_mask = smu_v11_0_set_allowed_mask,
28251d72 3887 .get_enabled_mask = smu_cmn_get_enabled_mask,
b4bb3aaf 3888 .feature_is_enabled = smu_cmn_feature_is_enabled,
af5ba6d2 3889 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
31157341 3890 .notify_display_change = NULL,
b455159c 3891 .set_power_limit = smu_v11_0_set_power_limit,
b455159c
LG		 3892 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
3893 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
3894 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
ce63d8f8 3895 .set_min_dcef_deep_sleep = NULL,
b455159c
LG		 3896 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
3897 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
3898 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
cd305137 3899 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
f3289d04 3900 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
b455159c
LG		 3901 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
3902 .gfx_off_control = smu_v11_0_gfx_off_control,
3903 .register_irq_handler = smu_v11_0_register_irq_handler,
3904 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
3905 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
9fd4781b 3906 .baco_is_support = smu_v11_0_baco_is_support,
b455159c
LG		 3907 .baco_get_state = smu_v11_0_baco_get_state,
3908 .baco_set_state = smu_v11_0_baco_set_state,
13d75ead
EQ		 3909 .baco_enter = sienna_cichlid_baco_enter,
3910 .baco_exit = sienna_cichlid_baco_exit,
ea8139d8
WS		 3911 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
3912 .mode1_reset = smu_v11_0_mode1_reset,
258d290c 3913 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
10e96d89 3914 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
aa75fa34 3915 .set_default_od_settings = sienna_cichlid_set_default_od_settings,
37a58f69 3916 .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
b521be9b 3917 .restore_user_od_settings = smu_v11_0_restore_user_od_settings,
66b8a9c0 3918 .run_btc = sienna_cichlid_run_btc,
18a4b3de 3919 .set_power_source = smu_v11_0_set_power_source,
7dbf7805
EQ		 3920 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3921 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
8ca78a0a 3922 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
05f39286 3923 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
e988026f 3924 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
5ce99853 3925 .deep_sleep_control = smu_v11_0_deep_sleep_control,
3204ff3e 3926 .get_fan_parameters = sienna_cichlid_get_fan_parameters,
234676d6 3927 .interrupt_work = smu_v11_0_interrupt_work,
76c71f00 3928 .gpo_control = sienna_cichlid_gpo_control,
1689fca0 3929 .set_mp1_state = sienna_cichlid_set_mp1_state,
b455159c
LG		 3930};
3931
3932void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
3933{
3934 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
6c339f37
EQ		 3935 smu->message_map = sienna_cichlid_message_map;
3936 smu->clock_map = sienna_cichlid_clk_map;
3937 smu->feature_map = sienna_cichlid_feature_mask_map;
3938 smu->table_map = sienna_cichlid_table_map;
3939 smu->pwr_src_map = sienna_cichlid_pwr_src_map;
3940 smu->workload_map = sienna_cichlid_workload_map;
b455159c 3941}
Linux 6.x block layer and io_uring tree(s)