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drm/amd/amdgpu: remove unnecessary RAS context field
[linux-2.6-block.git] / drivers / gpu / drm / amd / pm / swsmu / smu11 / sienna_cichlid_ppt.c
CommitLineData
b455159c
LG		 1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
d8e0b16d
EQ		 24#define SWSMU_CODE_LAYER_L2
25
b455159c
LG		 26#include <linux/firmware.h>
27#include <linux/pci.h>
bc50ca29 28#include <linux/i2c.h>
b455159c
LG		 29#include "amdgpu.h"
30#include "amdgpu_smu.h"
b455159c
LG		 31#include "atomfirmware.h"
32#include "amdgpu_atomfirmware.h"
22f2447c 33#include "amdgpu_atombios.h"
b455159c
LG		 34#include "smu_v11_0.h"
35#include "smu11_driver_if_sienna_cichlid.h"
36#include "soc15_common.h"
37#include "atom.h"
38#include "sienna_cichlid_ppt.h"
e05acd78 39#include "smu_v11_0_7_pptable.h"
b455159c 40#include "smu_v11_0_7_ppsmc.h"
40d3b8db 41#include "nbio/nbio_2_3_offset.h"
b7d25b5f 42#include "nbio/nbio_2_3_sh_mask.h"
e05acd78
LG		 43#include "thm/thm_11_0_2_offset.h"
44#include "thm/thm_11_0_2_sh_mask.h"
ea8139d8
WS		 45#include "mp/mp_11_0_offset.h"
46#include "mp/mp_11_0_sh_mask.h"
b455159c 47
6c339f37
EQ		 48#include "asic_reg/mp/mp_11_0_sh_mask.h"
49#include "smu_cmn.h"
50
55084d7f
EQ		 51/*
52 * DO NOT use these for err/warn/info/debug messages.
53 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
54 * They are more MGPU friendly.
55 */
56#undef pr_err
57#undef pr_warn
58#undef pr_info
59#undef pr_debug
60
bc50ca29
AD		 61#define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
62
b455159c
LG		 63#define FEATURE_MASK(feature) (1ULL << feature)
64#define SMC_DPM_FEATURE ( \
65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
fea905d4 66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65297d50 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
5cb74353 68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
4cd4f45b 69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
5f338f70 70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
ce7e5a6e
JC		 71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \
72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
b455159c 73
d817f375
LG		 74#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
75
7077b19a
CG		 76#define GET_PPTABLE_MEMBER(field, member) do {\
77 if (smu->adev->asic_type == CHIP_BEIGE_GOBY)\
78 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
79 else\
80 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
81} while(0)
82
83static int get_table_size(struct smu_context *smu)
84{
85 if (smu->adev->asic_type == CHIP_BEIGE_GOBY)
86 return sizeof(PPTable_beige_goby_t);
87 else
88 return sizeof(PPTable_t);
89}
90
6c339f37
EQ		 91static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
92 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
93 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
94 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
91190db1
LG		 95 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
96 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
97 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
98 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
6c339f37
EQ		 99 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
100 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
101 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
102 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
103 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
104 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
105 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
91190db1 106 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
4215a119
HC		 107 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
108 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
91190db1
LG		 109 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
110 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
4215a119 111 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
91190db1
LG		 112 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
113 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
66b8a9c0 114 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
91190db1 115 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
4215a119
HC		 116 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
117 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
6c339f37 118 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
91190db1 119 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
6c339f37
EQ		 120 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
121 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
122 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
91190db1
LG		 123 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
124 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
125 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
126 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
127 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
128 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
129 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
130 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
6c339f37 131 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
91190db1
LG		 132 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
133 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
134 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
6c339f37 135 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
91190db1
LG		 136 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
137 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
138 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
139 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
140 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
141 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
142 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
143 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
05f39286 144 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
76c71f00 145 MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0),
ac7804bb 146 MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0),
88dfd5d5 147 MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0),
b455159c
LG		 148};
149
6c339f37 150static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
b455159c
LG		 151 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
152 CLK_MAP(SCLK, PPCLK_GFXCLK),
153 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
154 CLK_MAP(FCLK, PPCLK_FCLK),
155 CLK_MAP(UCLK, PPCLK_UCLK),
156 CLK_MAP(MCLK, PPCLK_UCLK),
157 CLK_MAP(DCLK, PPCLK_DCLK_0),
9c0551f2
JC		 158 CLK_MAP(DCLK1, PPCLK_DCLK_1),
159 CLK_MAP(VCLK, PPCLK_VCLK_0),
b455159c
LG		 160 CLK_MAP(VCLK1, PPCLK_VCLK_1),
161 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
162 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
163 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
164 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
165};
166
6c339f37 167static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
b455159c
LG		 168 FEA_MAP(DPM_PREFETCHER),
169 FEA_MAP(DPM_GFXCLK),
31cb0dd9 170 FEA_MAP(DPM_GFX_GPO),
b455159c 171 FEA_MAP(DPM_UCLK),
e9073b43 172 FEA_MAP(DPM_FCLK),
b455159c
LG		 173 FEA_MAP(DPM_SOCCLK),
174 FEA_MAP(DPM_MP0CLK),
175 FEA_MAP(DPM_LINK),
176 FEA_MAP(DPM_DCEFCLK),
e9073b43 177 FEA_MAP(DPM_XGMI),
b455159c
LG		 178 FEA_MAP(MEM_VDDCI_SCALING),
179 FEA_MAP(MEM_MVDD_SCALING),
180 FEA_MAP(DS_GFXCLK),
181 FEA_MAP(DS_SOCCLK),
e9073b43 182 FEA_MAP(DS_FCLK),
b455159c
LG		 183 FEA_MAP(DS_LCLK),
184 FEA_MAP(DS_DCEFCLK),
185 FEA_MAP(DS_UCLK),
186 FEA_MAP(GFX_ULV),
187 FEA_MAP(FW_DSTATE),
188 FEA_MAP(GFXOFF),
189 FEA_MAP(BACO),
6fb176a7 190 FEA_MAP(MM_DPM_PG),
b455159c
LG		 191 FEA_MAP(RSMU_SMN_CG),
192 FEA_MAP(PPT),
193 FEA_MAP(TDC),
194 FEA_MAP(APCC_PLUS),
195 FEA_MAP(GTHR),
196 FEA_MAP(ACDC),
197 FEA_MAP(VR0HOT),
198 FEA_MAP(VR1HOT),
199 FEA_MAP(FW_CTF),
200 FEA_MAP(FAN_CONTROL),
201 FEA_MAP(THERMAL),
202 FEA_MAP(GFX_DCS),
203 FEA_MAP(RM),
204 FEA_MAP(LED_DISPLAY),
205 FEA_MAP(GFX_SS),
206 FEA_MAP(OUT_OF_BAND_MONITOR),
207 FEA_MAP(TEMP_DEPENDENT_VMIN),
208 FEA_MAP(MMHUB_PG),
209 FEA_MAP(ATHUB_PG),
cf06331f 210 FEA_MAP(APCC_DFLL),
b455159c
LG		 211};
212
6c339f37 213static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
b455159c
LG		 214 TAB_MAP(PPTABLE),
215 TAB_MAP(WATERMARKS),
216 TAB_MAP(AVFS_PSM_DEBUG),
217 TAB_MAP(AVFS_FUSE_OVERRIDE),
218 TAB_MAP(PMSTATUSLOG),
219 TAB_MAP(SMU_METRICS),
220 TAB_MAP(DRIVER_SMU_CONFIG),
221 TAB_MAP(ACTIVITY_MONITOR_COEFF),
222 TAB_MAP(OVERDRIVE),
223 TAB_MAP(I2C_COMMANDS),
224 TAB_MAP(PACE),
225};
226
6c339f37 227static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
1d5ca713
LG		 228 PWR_MAP(AC),
229 PWR_MAP(DC),
230};
231
6c339f37 232static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
b455159c
LG		 233 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
234 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
235 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
236 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
237 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
4c4d5a49 238 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
b455159c
LG		 239 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
240};
241
f06d9511
GS		 242static const uint8_t sienna_cichlid_throttler_map[] = {
243 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
244 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
245 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
246 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
247 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
248 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
249 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
250 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
251 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
252 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
253 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
254 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
255 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
256 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
257 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
258 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
259 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
260 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
261};
262
b455159c
LG		 263static int
264sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
265 uint32_t *feature_mask, uint32_t num)
266{
fea905d4
LG		 267 struct amdgpu_device *adev = smu->adev;
268
b455159c
LG		 269 if (num > 2)
270 return -EINVAL;
271
272 memset(feature_mask, 0, sizeof(uint32_t) * num);
273
4cd4f45b 274 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
15dbe18f 275 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
ce7e5a6e 276 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
094cdf15 277 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
5f338f70 278 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
86a9eb3f 279 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
80c36f86 280 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
9aa60213
LG		 281 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
282 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
d28f4aa1 283 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
20d71dcc 284 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
d0d71970 285 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
886c8bc6
LG		 286 | FEATURE_MASK(FEATURE_PPT_BIT)
287 | FEATURE_MASK(FEATURE_TDC_BIT)
3fc006f5 288 | FEATURE_MASK(FEATURE_BACO_BIT)
cf06331f 289 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
35ed946c 290 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
1c58d429 291 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
b971df70
LG		 292 | FEATURE_MASK(FEATURE_THERMAL_BIT)
293 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
fea905d4 294
c96721eb 295 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
fea905d4 296 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
c96721eb
KF		 297 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
298 }
fea905d4 299
680602d6
KF		 300 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
301 (adev->asic_type > CHIP_SIENNA_CICHLID) &&
302 !(adev->flags & AMD_IS_APU))
303 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
304
65297d50 305 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
fc17cd3f
LG		 306 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
307 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
308 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
65297d50 309
5cb74353
LG		 310 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
312
5f338f70
LG		 313 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
315
fea905d4
LG		 316 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
b455159c 318
62c1ea6b
LG		 319 if (adev->pm.pp_feature & PP_ULV_MASK)
320 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
321
02bb391d
LG		 322 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
323 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
324
e0da123a
LG		 325 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
327
b794616d
KF		 328 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
329 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
330
846938c2
KF		 331 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
332 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
333
6fb176a7
LG		 334 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
335 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
336 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
337
62826b86
KF		 338 if (smu->dc_controlled_by_gpio)
339 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
340
0064b0ce 341 if (amdgpu_aspm)
6ef28889
KF		 342 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
343
b455159c
LG		 344 return 0;
345}
346
458020dd 347static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
b455159c 348{
4a13b4ce 349 struct smu_table_context *table_context = &smu->smu_table;
e05acd78 350 struct smu_11_0_7_powerplay_table *powerplay_table =
4a13b4ce
EQ		 351 table_context->power_play_table;
352 struct smu_baco_context *smu_baco = &smu->smu_baco;
458020dd
LL		 353 struct amdgpu_device *adev = smu->adev;
354 uint32_t val;
355
1b41d67e 356 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) {
458020dd
LL		 357 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
358 smu_baco->platform_support =
359 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
360 false;
361 }
362}
363
364static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
365{
366 struct smu_table_context *table_context = &smu->smu_table;
367 struct smu_11_0_7_powerplay_table *powerplay_table =
368 table_context->power_play_table;
4a13b4ce 369
18a4b3de
EQ		 370 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
371 smu->dc_controlled_by_gpio = true;
372
458020dd 373 sienna_cichlid_check_bxco_support(smu);
4a13b4ce
EQ		 374
375 table_context->thermal_controller_type =
376 powerplay_table->thermal_controller_type;
377
aa75fa34
EQ		 378 /*
379 * Instead of having its own buffer space and get overdrive_table copied,
380 * smu->od_settings just points to the actual overdrive_table
381 */
382 smu->od_settings = &powerplay_table->overdrive_table;
383
b455159c
LG		 384 return 0;
385}
386
387static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
388{
dccc7c21
LG		 389 struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
390 int index, ret;
7077b19a 391 I2cControllerConfig_t *table_member;
dccc7c21
LG		 392
393 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
394 smc_dpm_info);
395
22f2447c 396 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
dccc7c21
LG		 397 (uint8_t **)&smc_dpm_table);
398 if (ret)
399 return ret;
7077b19a
CG		 400 GET_PPTABLE_MEMBER(I2cControllers, &table_member);
401 memcpy(table_member, smc_dpm_table->I2cControllers,
402 sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
969c8d16 403
b455159c
LG		 404 return 0;
405}
406
407static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
408{
b455159c 409 struct smu_table_context *table_context = &smu->smu_table;
e05acd78 410 struct smu_11_0_7_powerplay_table *powerplay_table =
4a13b4ce 411 table_context->power_play_table;
7077b19a 412 int table_size;
b455159c 413
7077b19a 414 table_size = get_table_size(smu);
b455159c 415 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
7077b19a 416 table_size);
b455159c 417
4a13b4ce
EQ		 418 return 0;
419}
b455159c 420
4a13b4ce
EQ		 421static int sienna_cichlid_setup_pptable(struct smu_context *smu)
422{
423 int ret = 0;
b455159c 424
4a13b4ce
EQ		 425 ret = smu_v11_0_setup_pptable(smu);
426 if (ret)
427 return ret;
428
429 ret = sienna_cichlid_store_powerplay_table(smu);
430 if (ret)
431 return ret;
432
433 ret = sienna_cichlid_append_powerplay_table(smu);
434 if (ret)
435 return ret;
436
437 ret = sienna_cichlid_check_powerplay_table(smu);
438 if (ret)
439 return ret;
440
441 return ret;
b455159c
LG		 442}
443
c1b353b7 444static int sienna_cichlid_tables_init(struct smu_context *smu)
b455159c
LG		 445{
446 struct smu_table_context *smu_table = &smu->smu_table;
c1b353b7 447 struct smu_table *tables = smu_table->tables;
7077b19a 448 int table_size;
b455159c 449
7077b19a
CG		 450 table_size = get_table_size(smu);
451 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
452 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c
LG		 453 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
454 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b4b0b79d 455 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
b455159c 456 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
bc50ca29
AD		 457 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
458 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c
LG		 459 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
460 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
461 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
462 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
463 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
f9e3fe46 464 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
b455159c
LG		 465 AMDGPU_GEM_DOMAIN_VRAM);
466
b4b0b79d 467 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
b455159c 468 if (!smu_table->metrics_table)
8ca78a0a 469 goto err0_out;
b455159c
LG		 470 smu_table->metrics_time = 0;
471
f06d9511 472 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
8ca78a0a
EQ		 473 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
474 if (!smu_table->gpu_metrics_table)
475 goto err1_out;
476
40d3b8db
LG		 477 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
478 if (!smu_table->watermarks_table)
8ca78a0a 479 goto err2_out;
40d3b8db 480
b455159c 481 return 0;
8ca78a0a
EQ		 482
483err2_out:
484 kfree(smu_table->gpu_metrics_table);
485err1_out:
486 kfree(smu_table->metrics_table);
487err0_out:
488 return -ENOMEM;
b455159c
LG		 489}
490
be22e2b9
EQ		 491static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu)
492{
493 struct smu_table_context *smu_table= &smu->smu_table;
494 SmuMetricsExternal_t *metrics_ext =
495 (SmuMetricsExternal_t *)(smu_table->metrics_table);
496 uint32_t throttler_status = 0;
497 int i;
498
499 if ((smu->adev->asic_type == CHIP_SIENNA_CICHLID) &&
500 (smu->smc_fw_version >= 0x3A4300)) {
501 for (i = 0; i < THROTTLER_COUNT; i++)
502 throttler_status |=
503 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
504 } else {
505 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus;
506 }
507
508 return throttler_status;
509}
510
60ae4d67
EQ		 511static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
512 MetricsMember_t member,
513 uint32_t *value)
514{
515 struct smu_table_context *smu_table= &smu->smu_table;
b4b0b79d
EQ		 516 SmuMetrics_t *metrics =
517 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
be22e2b9
EQ		 518 SmuMetrics_V2_t *metrics_v2 =
519 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
520 bool use_metrics_v2 = ((smu->adev->asic_type == CHIP_SIENNA_CICHLID) &&
521 (smu->smc_fw_version >= 0x3A4300)) ? true : false;
522 uint16_t average_gfx_activity;
60ae4d67
EQ		 523 int ret = 0;
524
525 mutex_lock(&smu->metrics_lock);
526
fceafc9b
EQ		 527 ret = smu_cmn_get_metrics_table_locked(smu,
528 NULL,
529 false);
60ae4d67
EQ		 530 if (ret) {
531 mutex_unlock(&smu->metrics_lock);
532 return ret;
533 }
534
8c686254
EQ		 535 switch (member) {
536 case METRICS_CURR_GFXCLK:
be22e2b9
EQ		 537 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] :
538 metrics->CurrClock[PPCLK_GFXCLK];
8c686254
EQ		 539 break;
540 case METRICS_CURR_SOCCLK:
be22e2b9
EQ		 541 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] :
542 metrics->CurrClock[PPCLK_SOCCLK];
8c686254
EQ		 543 break;
544 case METRICS_CURR_UCLK:
be22e2b9
EQ		 545 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] :
546 metrics->CurrClock[PPCLK_UCLK];
8c686254
EQ		 547 break;
548 case METRICS_CURR_VCLK:
be22e2b9
EQ		 549 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] :
550 metrics->CurrClock[PPCLK_VCLK_0];
8c686254
EQ		 551 break;
552 case METRICS_CURR_VCLK1:
be22e2b9
EQ		 553 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] :
554 metrics->CurrClock[PPCLK_VCLK_1];
8c686254
EQ		 555 break;
556 case METRICS_CURR_DCLK:
be22e2b9
EQ		 557 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] :
558 metrics->CurrClock[PPCLK_DCLK_0];
8c686254
EQ		 559 break;
560 case METRICS_CURR_DCLK1:
be22e2b9
EQ		 561 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
562 metrics->CurrClock[PPCLK_DCLK_1];
8c686254 563 break;
9d09fa6f 564 case METRICS_CURR_DCEFCLK:
be22e2b9
EQ		 565 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] :
566 metrics->CurrClock[PPCLK_DCEFCLK];
9d09fa6f 567 break;
4e2b3e23 568 case METRICS_CURR_FCLK:
be22e2b9
EQ		 569 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] :
570 metrics->CurrClock[PPCLK_FCLK];
4e2b3e23 571 break;
8c686254 572 case METRICS_AVERAGE_GFXCLK:
be22e2b9
EQ		 573 average_gfx_activity = use_metrics_v2 ? metrics_v2->AverageGfxActivity :
574 metrics->AverageGfxActivity;
575 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
576 *value = use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
577 metrics->AverageGfxclkFrequencyPostDs;
d817f375 578 else
be22e2b9
EQ		 579 *value = use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
580 metrics->AverageGfxclkFrequencyPreDs;
8c686254
EQ		 581 break;
582 case METRICS_AVERAGE_FCLK:
be22e2b9
EQ		 583 *value = use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs :
584 metrics->AverageFclkFrequencyPostDs;
8c686254
EQ		 585 break;
586 case METRICS_AVERAGE_UCLK:
be22e2b9
EQ		 587 *value = use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
588 metrics->AverageUclkFrequencyPostDs;
8c686254
EQ		 589 break;
590 case METRICS_AVERAGE_GFXACTIVITY:
be22e2b9
EQ		 591 *value = use_metrics_v2 ? metrics_v2->AverageGfxActivity :
592 metrics->AverageGfxActivity;
8c686254
EQ		 593 break;
594 case METRICS_AVERAGE_MEMACTIVITY:
be22e2b9
EQ		 595 *value = use_metrics_v2 ? metrics_v2->AverageUclkActivity :
596 metrics->AverageUclkActivity;
8c686254
EQ		 597 break;
598 case METRICS_AVERAGE_SOCKETPOWER:
be22e2b9
EQ		 599 *value = use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 :
600 metrics->AverageSocketPower << 8;
8c686254
EQ		 601 break;
602 case METRICS_TEMPERATURE_EDGE:
be22e2b9 603 *value = (use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge) *
8c686254
EQ		 604 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
605 break;
606 case METRICS_TEMPERATURE_HOTSPOT:
be22e2b9 607 *value = (use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot) *
8c686254
EQ		 608 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
609 break;
610 case METRICS_TEMPERATURE_MEM:
be22e2b9 611 *value = (use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem) *
8c686254
EQ		 612 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
613 break;
614 case METRICS_TEMPERATURE_VRGFX:
be22e2b9 615 *value = (use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx) *
8c686254
EQ		 616 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
617 break;
618 case METRICS_TEMPERATURE_VRSOC:
be22e2b9 619 *value = (use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc) *
8c686254
EQ		 620 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
621 break;
622 case METRICS_THROTTLER_STATUS:
be22e2b9 623 *value = sienna_cichlid_get_throttler_status_locked(smu);
8c686254
EQ		 624 break;
625 case METRICS_CURR_FANSPEED:
be22e2b9 626 *value = use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
8c686254
EQ		 627 break;
628 default:
629 *value = UINT_MAX;
630 break;
631 }
632
b455159c
LG		 633 mutex_unlock(&smu->metrics_lock);
634
635 return ret;
8c686254 636
b455159c
LG		 637}
638
639static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
640{
641 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
642
b455159c
LG		 643 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
644 GFP_KERNEL);
645 if (!smu_dpm->dpm_context)
646 return -ENOMEM;
647
648 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
649
650 return 0;
651}
652
c1b353b7
EQ		 653static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
654{
655 int ret = 0;
656
657 ret = sienna_cichlid_tables_init(smu);
658 if (ret)
659 return ret;
660
661 ret = sienna_cichlid_allocate_dpm_context(smu);
662 if (ret)
663 return ret;
664
665 return smu_v11_0_init_smc_tables(smu);
666}
667
b455159c
LG		 668static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
669{
90a89c31 670 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
90a89c31 671 struct smu_11_0_dpm_table *dpm_table;
85dec717 672 struct amdgpu_device *adev = smu->adev;
90a89c31 673 int ret = 0;
7077b19a 674 DpmDescriptor_t *table_member;
b455159c 675
90a89c31
EQ		 676 /* socclk dpm table setup */
677 dpm_table = &dpm_context->dpm_tables.soc_table;
7077b19a 678 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
b4bb3aaf 679 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
90a89c31
EQ		 680 ret = smu_v11_0_set_single_dpm_table(smu,
681 SMU_SOCCLK,
682 dpm_table);
683 if (ret)
684 return ret;
685 dpm_table->is_fine_grained =
7077b19a 686 !table_member[PPCLK_SOCCLK].SnapToDiscrete;
90a89c31
EQ		 687 } else {
688 dpm_table->count = 1;
689 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
690 dpm_table->dpm_levels[0].enabled = true;
691 dpm_table->min = dpm_table->dpm_levels[0].value;
692 dpm_table->max = dpm_table->dpm_levels[0].value;
693 }
b455159c 694
90a89c31
EQ		 695 /* gfxclk dpm table setup */
696 dpm_table = &dpm_context->dpm_tables.gfx_table;
b4bb3aaf 697 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
90a89c31
EQ		 698 ret = smu_v11_0_set_single_dpm_table(smu,
699 SMU_GFXCLK,
700 dpm_table);
701 if (ret)
702 return ret;
703 dpm_table->is_fine_grained =
7077b19a 704 !table_member[PPCLK_GFXCLK].SnapToDiscrete;
90a89c31
EQ		 705 } else {
706 dpm_table->count = 1;
707 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
708 dpm_table->dpm_levels[0].enabled = true;
709 dpm_table->min = dpm_table->dpm_levels[0].value;
710 dpm_table->max = dpm_table->dpm_levels[0].value;
711 }
b455159c 712
90a89c31
EQ		 713 /* uclk dpm table setup */
714 dpm_table = &dpm_context->dpm_tables.uclk_table;
b4bb3aaf 715 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
90a89c31
EQ		 716 ret = smu_v11_0_set_single_dpm_table(smu,
717 SMU_UCLK,
718 dpm_table);
719 if (ret)
720 return ret;
721 dpm_table->is_fine_grained =
7077b19a 722 !table_member[PPCLK_UCLK].SnapToDiscrete;
90a89c31
EQ		 723 } else {
724 dpm_table->count = 1;
725 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
726 dpm_table->dpm_levels[0].enabled = true;
727 dpm_table->min = dpm_table->dpm_levels[0].value;
728 dpm_table->max = dpm_table->dpm_levels[0].value;
729 }
b455159c 730
90a89c31
EQ		 731 /* fclk dpm table setup */
732 dpm_table = &dpm_context->dpm_tables.fclk_table;
b4bb3aaf 733 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
90a89c31
EQ		 734 ret = smu_v11_0_set_single_dpm_table(smu,
735 SMU_FCLK,
736 dpm_table);
737 if (ret)
738 return ret;
739 dpm_table->is_fine_grained =
7077b19a 740 !table_member[PPCLK_FCLK].SnapToDiscrete;
90a89c31
EQ		 741 } else {
742 dpm_table->count = 1;
743 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
744 dpm_table->dpm_levels[0].enabled = true;
745 dpm_table->min = dpm_table->dpm_levels[0].value;
746 dpm_table->max = dpm_table->dpm_levels[0].value;
747 }
b455159c 748
90a89c31
EQ		 749 /* vclk0 dpm table setup */
750 dpm_table = &dpm_context->dpm_tables.vclk_table;
b4bb3aaf 751 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
90a89c31
EQ		 752 ret = smu_v11_0_set_single_dpm_table(smu,
753 SMU_VCLK,
754 dpm_table);
755 if (ret)
756 return ret;
757 dpm_table->is_fine_grained =
7077b19a 758 !table_member[PPCLK_VCLK_0].SnapToDiscrete;
90a89c31
EQ		 759 } else {
760 dpm_table->count = 1;
761 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
762 dpm_table->dpm_levels[0].enabled = true;
763 dpm_table->min = dpm_table->dpm_levels[0].value;
764 dpm_table->max = dpm_table->dpm_levels[0].value;
765 }
b455159c 766
90a89c31 767 /* vclk1 dpm table setup */
85dec717
JC		 768 if (adev->vcn.num_vcn_inst > 1) {
769 dpm_table = &dpm_context->dpm_tables.vclk1_table;
770 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
771 ret = smu_v11_0_set_single_dpm_table(smu,
772 SMU_VCLK1,
773 dpm_table);
774 if (ret)
775 return ret;
776 dpm_table->is_fine_grained =
7077b19a 777 !table_member[PPCLK_VCLK_1].SnapToDiscrete;
85dec717
JC		 778 } else {
779 dpm_table->count = 1;
780 dpm_table->dpm_levels[0].value =
781 smu->smu_table.boot_values.vclk / 100;
782 dpm_table->dpm_levels[0].enabled = true;
783 dpm_table->min = dpm_table->dpm_levels[0].value;
784 dpm_table->max = dpm_table->dpm_levels[0].value;
785 }
90a89c31 786 }
b455159c 787
90a89c31
EQ		 788 /* dclk0 dpm table setup */
789 dpm_table = &dpm_context->dpm_tables.dclk_table;
b4bb3aaf 790 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
90a89c31
EQ		 791 ret = smu_v11_0_set_single_dpm_table(smu,
792 SMU_DCLK,
793 dpm_table);
794 if (ret)
795 return ret;
796 dpm_table->is_fine_grained =
7077b19a 797 !table_member[PPCLK_DCLK_0].SnapToDiscrete;
90a89c31
EQ		 798 } else {
799 dpm_table->count = 1;
800 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
801 dpm_table->dpm_levels[0].enabled = true;
802 dpm_table->min = dpm_table->dpm_levels[0].value;
803 dpm_table->max = dpm_table->dpm_levels[0].value;
804 }
805
806 /* dclk1 dpm table setup */
85dec717
JC		 807 if (adev->vcn.num_vcn_inst > 1) {
808 dpm_table = &dpm_context->dpm_tables.dclk1_table;
809 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
810 ret = smu_v11_0_set_single_dpm_table(smu,
811 SMU_DCLK1,
812 dpm_table);
813 if (ret)
814 return ret;
815 dpm_table->is_fine_grained =
7077b19a 816 !table_member[PPCLK_DCLK_1].SnapToDiscrete;
85dec717
JC		 817 } else {
818 dpm_table->count = 1;
819 dpm_table->dpm_levels[0].value =
820 smu->smu_table.boot_values.dclk / 100;
821 dpm_table->dpm_levels[0].enabled = true;
822 dpm_table->min = dpm_table->dpm_levels[0].value;
823 dpm_table->max = dpm_table->dpm_levels[0].value;
824 }
90a89c31
EQ		 825 }
826
827 /* dcefclk dpm table setup */
828 dpm_table = &dpm_context->dpm_tables.dcef_table;
b4bb3aaf 829 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 830 ret = smu_v11_0_set_single_dpm_table(smu,
831 SMU_DCEFCLK,
832 dpm_table);
833 if (ret)
834 return ret;
835 dpm_table->is_fine_grained =
7077b19a 836 !table_member[PPCLK_DCEFCLK].SnapToDiscrete;
90a89c31
EQ		 837 } else {
838 dpm_table->count = 1;
839 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
840 dpm_table->dpm_levels[0].enabled = true;
841 dpm_table->min = dpm_table->dpm_levels[0].value;
842 dpm_table->max = dpm_table->dpm_levels[0].value;
843 }
b455159c 844
90a89c31
EQ		 845 /* pixelclk dpm table setup */
846 dpm_table = &dpm_context->dpm_tables.pixel_table;
b4bb3aaf 847 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 848 ret = smu_v11_0_set_single_dpm_table(smu,
849 SMU_PIXCLK,
850 dpm_table);
851 if (ret)
852 return ret;
853 dpm_table->is_fine_grained =
7077b19a 854 !table_member[PPCLK_PIXCLK].SnapToDiscrete;
90a89c31
EQ		 855 } else {
856 dpm_table->count = 1;
857 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
858 dpm_table->dpm_levels[0].enabled = true;
859 dpm_table->min = dpm_table->dpm_levels[0].value;
860 dpm_table->max = dpm_table->dpm_levels[0].value;
861 }
b455159c 862
90a89c31
EQ		 863 /* displayclk dpm table setup */
864 dpm_table = &dpm_context->dpm_tables.display_table;
b4bb3aaf 865 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 866 ret = smu_v11_0_set_single_dpm_table(smu,
867 SMU_DISPCLK,
868 dpm_table);
869 if (ret)
870 return ret;
871 dpm_table->is_fine_grained =
7077b19a 872 !table_member[PPCLK_DISPCLK].SnapToDiscrete;
90a89c31
EQ		 873 } else {
874 dpm_table->count = 1;
875 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
876 dpm_table->dpm_levels[0].enabled = true;
877 dpm_table->min = dpm_table->dpm_levels[0].value;
878 dpm_table->max = dpm_table->dpm_levels[0].value;
879 }
b455159c 880
90a89c31
EQ		 881 /* phyclk dpm table setup */
882 dpm_table = &dpm_context->dpm_tables.phy_table;
b4bb3aaf 883 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 884 ret = smu_v11_0_set_single_dpm_table(smu,
885 SMU_PHYCLK,
886 dpm_table);
887 if (ret)
888 return ret;
889 dpm_table->is_fine_grained =
7077b19a 890 !table_member[PPCLK_PHYCLK].SnapToDiscrete;
90a89c31
EQ		 891 } else {
892 dpm_table->count = 1;
893 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
894 dpm_table->dpm_levels[0].enabled = true;
895 dpm_table->min = dpm_table->dpm_levels[0].value;
896 dpm_table->max = dpm_table->dpm_levels[0].value;
897 }
b455159c
LG		 898
899 return 0;
900}
901
f6b4b4a1 902static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
b455159c 903{
d51dc613 904 struct amdgpu_device *adev = smu->adev;
b455159c
LG		 905 int ret = 0;
906
907 if (enable) {
908 /* vcn dpm on is a prerequisite for vcn power gate messages */
b4bb3aaf 909 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 910 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
6fb176a7
LG		 911 if (ret)
912 return ret;
6ec46653 913 if (adev->vcn.num_vcn_inst > 1) {
66c86828 914 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
d51dc613
JC		 915 0x10000, NULL);
916 if (ret)
917 return ret;
918 }
b455159c 919 }
b455159c 920 } else {
b4bb3aaf 921 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 922 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
6fb176a7
LG		 923 if (ret)
924 return ret;
6ec46653 925 if (adev->vcn.num_vcn_inst > 1) {
66c86828 926 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
d51dc613
JC		 927 0x10000, NULL);
928 if (ret)
929 return ret;
930 }
b455159c 931 }
b455159c
LG		 932 }
933
934 return ret;
935}
936
6fb176a7
LG		 937static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
938{
6fb176a7
LG		 939 int ret = 0;
940
941 if (enable) {
b4bb3aaf 942 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 943 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
6fb176a7
LG		 944 if (ret)
945 return ret;
6fb176a7 946 }
6fb176a7 947 } else {
b4bb3aaf 948 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 949 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
6fb176a7
LG		 950 if (ret)
951 return ret;
6fb176a7 952 }
6fb176a7
LG		 953 }
954
955 return ret;
956}
957
b455159c
LG		 958static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
959 enum smu_clk_type clk_type,
960 uint32_t *value)
961{
8c686254
EQ		 962 MetricsMember_t member_type;
963 int clk_id = 0;
b455159c 964
6c339f37
EQ		 965 clk_id = smu_cmn_to_asic_specific_index(smu,
966 CMN2ASIC_MAPPING_CLK,
967 clk_type);
b455159c
LG		 968 if (clk_id < 0)
969 return clk_id;
970
8c686254
EQ		 971 switch (clk_id) {
972 case PPCLK_GFXCLK:
973 member_type = METRICS_CURR_GFXCLK;
974 break;
975 case PPCLK_UCLK:
976 member_type = METRICS_CURR_UCLK;
977 break;
978 case PPCLK_SOCCLK:
979 member_type = METRICS_CURR_SOCCLK;
980 break;
981 case PPCLK_FCLK:
982 member_type = METRICS_CURR_FCLK;
983 break;
984 case PPCLK_VCLK_0:
985 member_type = METRICS_CURR_VCLK;
986 break;
987 case PPCLK_VCLK_1:
988 member_type = METRICS_CURR_VCLK1;
989 break;
990 case PPCLK_DCLK_0:
991 member_type = METRICS_CURR_DCLK;
992 break;
993 case PPCLK_DCLK_1:
994 member_type = METRICS_CURR_DCLK1;
995 break;
996 case PPCLK_DCEFCLK:
997 member_type = METRICS_CURR_DCEFCLK;
998 break;
999 default:
1000 return -EINVAL;
1001 }
1002
1003 return sienna_cichlid_get_smu_metrics_data(smu,
1004 member_type,
1005 value);
b455159c 1006
b455159c
LG		 1007}
1008
1009static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1010{
b455159c 1011 DpmDescriptor_t *dpm_desc = NULL;
7077b19a 1012 DpmDescriptor_t *table_member;
b455159c
LG		 1013 uint32_t clk_index = 0;
1014
7077b19a 1015 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
6c339f37
EQ		 1016 clk_index = smu_cmn_to_asic_specific_index(smu,
1017 CMN2ASIC_MAPPING_CLK,
1018 clk_type);
7077b19a 1019 dpm_desc = &table_member[clk_index];
b455159c
LG		 1020
1021 /* 0 - Fine grained DPM, 1 - Discrete DPM */
0ee56acc 1022 return dpm_desc->SnapToDiscrete == 0;
b455159c
LG		 1023}
1024
37a58f69
EQ		 1025static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
1026 enum SMU_11_0_7_ODFEATURE_CAP cap)
1027{
1028 return od_table->cap[cap];
1029}
1030
1031static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
1032 enum SMU_11_0_7_ODSETTING_ID setting,
1033 uint32_t *min, uint32_t *max)
1034{
1035 if (min)
1036 *min = od_table->min[setting];
1037 if (max)
1038 *max = od_table->max[setting];
1039}
1040
b455159c
LG		 1041static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
1042 enum smu_clk_type clk_type, char *buf)
1043{
b7d25b5f
LG		 1044 struct amdgpu_device *adev = smu->adev;
1045 struct smu_table_context *table_context = &smu->smu_table;
1046 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1047 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
7077b19a
CG		 1048 uint16_t *table_member;
1049
37a58f69
EQ		 1050 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
1051 OverDriveTable_t *od_table =
1052 (OverDriveTable_t *)table_context->overdrive_table;
b455159c
LG		 1053 int i, size = 0, ret = 0;
1054 uint32_t cur_value = 0, value = 0, count = 0;
1055 uint32_t freq_values[3] = {0};
1056 uint32_t mark_index = 0;
b7d25b5f 1057 uint32_t gen_speed, lane_width;
37a58f69 1058 uint32_t min_value, max_value;
a2b6df4f 1059 uint32_t smu_version;
b455159c
LG		 1060
1061 switch (clk_type) {
1062 case SMU_GFXCLK:
1063 case SMU_SCLK:
1064 case SMU_SOCCLK:
1065 case SMU_MCLK:
1066 case SMU_UCLK:
1067 case SMU_FCLK:
78842457
DN		 1068 case SMU_VCLK:
1069 case SMU_VCLK1:
1070 case SMU_DCLK:
1071 case SMU_DCLK1:
b455159c 1072 case SMU_DCEFCLK:
5e6dc8fe 1073 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
b455159c 1074 if (ret)
258d290c 1075 goto print_clk_out;
b455159c 1076
ba818620
KF		 1077 /* no need to disable gfxoff when retrieving the current gfxclk */
1078 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1079 amdgpu_gfx_off_ctrl(adev, false);
1080
d8d3493a 1081 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
b455159c 1082 if (ret)
258d290c 1083 goto print_clk_out;
b455159c
LG		 1084
1085 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1086 for (i = 0; i < count; i++) {
d8d3493a 1087 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
b455159c 1088 if (ret)
258d290c 1089 goto print_clk_out;
b455159c 1090
fe14c285 1091 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
b455159c
LG		 1092 cur_value == value ? "*" : "");
1093 }
1094 } else {
d8d3493a 1095 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
b455159c 1096 if (ret)
258d290c 1097 goto print_clk_out;
d8d3493a 1098 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
b455159c 1099 if (ret)
258d290c 1100 goto print_clk_out;
b455159c
LG		 1101
1102 freq_values[1] = cur_value;
1103 mark_index = cur_value == freq_values[0] ? 0 :
1104 cur_value == freq_values[2] ? 2 : 1;
b455159c 1105
891bacb8
KF		 1106 count = 3;
1107 if (mark_index != 1) {
1108 count = 2;
1109 freq_values[1] = freq_values[2];
1110 }
1111
1112 for (i = 0; i < count; i++) {
fe14c285 1113 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
891bacb8 1114 cur_value == freq_values[i] ? "*" : "");
b455159c
LG		 1115 }
1116
1117 }
1118 break;
b7d25b5f 1119 case SMU_PCIE:
f20c52f4
LG		 1120 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1121 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
7077b19a 1122 GET_PPTABLE_MEMBER(LclkFreq, &table_member);
b7d25b5f 1123 for (i = 0; i < NUM_LINK_LEVELS; i++)
fe14c285 1124 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
b7d25b5f
LG		 1125 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1126 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1127 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1128 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1129 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1130 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1131 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1132 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1133 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1134 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
7077b19a 1135 table_member[i],
b7d25b5f
LG		 1136 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1137 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1138 "*" : "");
1139 break;
37a58f69
EQ		 1140 case SMU_OD_SCLK:
1141 if (!smu->od_enabled || !od_table || !od_settings)
1142 break;
1143
1144 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1145 break;
1146
fe14c285
DP		 1147 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1148 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
37a58f69
EQ		 1149 break;
1150
1151 case SMU_OD_MCLK:
1152 if (!smu->od_enabled || !od_table || !od_settings)
1153 break;
1154
1155 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1156 break;
1157
fe14c285
DP		 1158 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1159 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
37a58f69
EQ		 1160 break;
1161
a2b6df4f
EQ		 1162 case SMU_OD_VDDGFX_OFFSET:
1163 if (!smu->od_enabled || !od_table || !od_settings)
1164 break;
1165
1166 /*
1167 * OD GFX Voltage Offset functionality is supported only by 58.41.0
1168 * and onwards SMU firmwares.
1169 */
1170 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1171 if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1172 (smu_version < 0x003a2900))
1173 break;
1174
fe14c285
DP		 1175 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1176 size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset);
a2b6df4f
EQ		 1177 break;
1178
37a58f69
EQ		 1179 case SMU_OD_RANGE:
1180 if (!smu->od_enabled || !od_table || !od_settings)
1181 break;
1182
fe14c285 1183 size = sysfs_emit(buf, "%s:\n", "OD_RANGE");
37a58f69
EQ		 1184
1185 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1186 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1187 &min_value, NULL);
1188 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1189 NULL, &max_value);
fe14c285 1190 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
37a58f69
EQ		 1191 min_value, max_value);
1192 }
1193
1194 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1195 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1196 &min_value, NULL);
1197 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1198 NULL, &max_value);
fe14c285 1199 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
37a58f69
EQ		 1200 min_value, max_value);
1201 }
1202 break;
1203
b455159c
LG		 1204 default:
1205 break;
1206 }
1207
258d290c
LG		 1208print_clk_out:
1209 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1210 amdgpu_gfx_off_ctrl(adev, true);
1211
b455159c
LG		 1212 return size;
1213}
1214
1215static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1216 enum smu_clk_type clk_type, uint32_t mask)
1217{
258d290c 1218 struct amdgpu_device *adev = smu->adev;
b455159c
LG		 1219 int ret = 0, size = 0;
1220 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1221
1222 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1223 soft_max_level = mask ? (fls(mask) - 1) : 0;
1224
258d290c
LG		 1225 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1226 amdgpu_gfx_off_ctrl(adev, false);
1227
b455159c
LG		 1228 switch (clk_type) {
1229 case SMU_GFXCLK:
1230 case SMU_SCLK:
1231 case SMU_SOCCLK:
1232 case SMU_MCLK:
1233 case SMU_UCLK:
b455159c 1234 case SMU_FCLK:
9ad9c8ac
LG		 1235 /* There is only 2 levels for fine grained DPM */
1236 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1237 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1238 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1239 }
1240
d8d3493a 1241 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
b455159c 1242 if (ret)
258d290c 1243 goto forec_level_out;
b455159c 1244
d8d3493a 1245 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
b455159c 1246 if (ret)
258d290c 1247 goto forec_level_out;
b455159c 1248
10e96d89 1249 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
b455159c 1250 if (ret)
258d290c 1251 goto forec_level_out;
b455159c 1252 break;
51ec6992
DP		 1253 case SMU_DCEFCLK:
1254 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1255 break;
b455159c
LG		 1256 default:
1257 break;
1258 }
1259
258d290c
LG		 1260forec_level_out:
1261 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1262 amdgpu_gfx_off_ctrl(adev, true);
1263
b455159c
LG		 1264 return size;
1265}
1266
1267static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1268{
62cc9dd1
EQ		 1269 struct smu_11_0_dpm_context *dpm_context =
1270 smu->smu_dpm.dpm_context;
1271 struct smu_11_0_dpm_table *gfx_table =
1272 &dpm_context->dpm_tables.gfx_table;
1273 struct smu_11_0_dpm_table *mem_table =
1274 &dpm_context->dpm_tables.uclk_table;
1275 struct smu_11_0_dpm_table *soc_table =
1276 &dpm_context->dpm_tables.soc_table;
1277 struct smu_umd_pstate_table *pstate_table =
1278 &smu->pstate_table;
1279
1280 pstate_table->gfxclk_pstate.min = gfx_table->min;
1281 pstate_table->gfxclk_pstate.peak = gfx_table->max;
0dc994fb
EQ		 1282 if (gfx_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK)
1283 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
62cc9dd1
EQ		 1284
1285 pstate_table->uclk_pstate.min = mem_table->min;
1286 pstate_table->uclk_pstate.peak = mem_table->max;
0dc994fb
EQ		 1287 if (mem_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK)
1288 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
62cc9dd1
EQ		 1289
1290 pstate_table->socclk_pstate.min = soc_table->min;
1291 pstate_table->socclk_pstate.peak = soc_table->max;
0dc994fb
EQ		 1292 if (soc_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK)
1293 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
b455159c 1294
62cc9dd1 1295 return 0;
b455159c
LG		 1296}
1297
b455159c
LG		 1298static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1299{
1300 int ret = 0;
1301 uint32_t max_freq = 0;
1302
1303 /* Sienna_Cichlid do not support to change display num currently */
1304 return 0;
1305#if 0
66c86828 1306 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
b455159c
LG		 1307 if (ret)
1308 return ret;
1309#endif
1310
b4bb3aaf 1311 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
e5ef784b 1312 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
b455159c
LG		 1313 if (ret)
1314 return ret;
661b94f5 1315 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
b455159c
LG		 1316 if (ret)
1317 return ret;
1318 }
1319
1320 return ret;
1321}
1322
1323static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1324{
1325 int ret = 0;
1326
b455159c 1327 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
4d942ae3
EQ		 1328 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1329 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
b455159c 1330#if 0
66c86828 1331 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
40d3b8db
LG		 1332 smu->display_config->num_display,
1333 NULL);
b455159c
LG		 1334#endif
1335 if (ret)
1336 return ret;
1337 }
1338
1339 return ret;
1340}
1341
b455159c
LG		 1342static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1343{
1344 int ret = 0;
1345 uint32_t feature_mask[2];
3d14a79b
KW		 1346 uint64_t feature_enabled;
1347
28251d72 1348 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
3d14a79b
KW		 1349 if (ret)
1350 return false;
1351
1352 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1353
b455159c
LG		 1354 return !!(feature_enabled & SMC_DPM_FEATURE);
1355}
1356
4954a76a
AD		 1357static int sienna_cichlid_get_fan_speed_percent(struct smu_context *smu,
1358 uint32_t *speed)
b455159c 1359{
4954a76a
AD		 1360 int ret;
1361 u32 rpm;
1362
b455159c
LG		 1363 if (!speed)
1364 return -EINVAL;
1365
4954a76a
AD		 1366 switch (smu_v11_0_get_fan_control_mode(smu)) {
1367 case AMD_FAN_CTRL_AUTO:
1368 ret = sienna_cichlid_get_smu_metrics_data(smu,
1369 METRICS_CURR_FANSPEED,
1370 &rpm);
1371 if (!ret && smu->fan_max_rpm)
1372 *speed = rpm * 100 / smu->fan_max_rpm;
1373 return ret;
1374 default:
1375 *speed = smu->user_dpm_profile.fan_speed_percent;
1376 return 0;
1377 }
b455159c
LG		 1378}
1379
3204ff3e
AD		 1380static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1381{
7077b19a 1382 uint16_t *table_member;
3204ff3e 1383
7077b19a
CG		 1384 GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
1385 smu->fan_max_rpm = *table_member;
3204ff3e
AD		 1386
1387 return 0;
1388}
1389
b455159c
LG		 1390static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1391{
f9e3fe46
EQ		 1392 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1393 DpmActivityMonitorCoeffInt_t *activity_monitor =
1394 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
b455159c
LG		 1395 uint32_t i, size = 0;
1396 int16_t workload_type = 0;
1397 static const char *profile_name[] = {
1398 "BOOTUP_DEFAULT",
1399 "3D_FULL_SCREEN",
1400 "POWER_SAVING",
1401 "VIDEO",
1402 "VR",
1403 "COMPUTE",
1404 "CUSTOM"};
1405 static const char *title[] = {
1406 "PROFILE_INDEX(NAME)",
1407 "CLOCK_TYPE(NAME)",
1408 "FPS",
1409 "MinFreqType",
1410 "MinActiveFreqType",
1411 "MinActiveFreq",
1412 "BoosterFreqType",
1413 "BoosterFreq",
1414 "PD_Data_limit_c",
1415 "PD_Data_error_coeff",
1416 "PD_Data_error_rate_coeff"};
1417 int result = 0;
1418
1419 if (!buf)
1420 return -EINVAL;
1421
fe14c285 1422 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
b455159c
LG		 1423 title[0], title[1], title[2], title[3], title[4], title[5],
1424 title[6], title[7], title[8], title[9], title[10]);
1425
1426 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1427 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
6c339f37
EQ		 1428 workload_type = smu_cmn_to_asic_specific_index(smu,
1429 CMN2ASIC_MAPPING_WORKLOAD,
1430 i);
b455159c
LG		 1431 if (workload_type < 0)
1432 return -EINVAL;
1433
caad2613 1434 result = smu_cmn_update_table(smu,
b455159c 1435 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
f9e3fe46 1436 (void *)(&activity_monitor_external), false);
b455159c 1437 if (result) {
d9811cfc 1438 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
b455159c
LG		 1439 return result;
1440 }
1441
fe14c285 1442 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
b455159c
LG		 1443 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1444
fe14c285 1445 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
b455159c
LG		 1446 " ",
1447 0,
1448 "GFXCLK",
f9e3fe46
EQ		 1449 activity_monitor->Gfx_FPS,
1450 activity_monitor->Gfx_MinFreqStep,
1451 activity_monitor->Gfx_MinActiveFreqType,
1452 activity_monitor->Gfx_MinActiveFreq,
1453 activity_monitor->Gfx_BoosterFreqType,
1454 activity_monitor->Gfx_BoosterFreq,
1455 activity_monitor->Gfx_PD_Data_limit_c,
1456 activity_monitor->Gfx_PD_Data_error_coeff,
1457 activity_monitor->Gfx_PD_Data_error_rate_coeff);
b455159c 1458
fe14c285 1459 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
b455159c
LG		 1460 " ",
1461 1,
1462 "SOCCLK",
f9e3fe46
EQ		 1463 activity_monitor->Fclk_FPS,
1464 activity_monitor->Fclk_MinFreqStep,
1465 activity_monitor->Fclk_MinActiveFreqType,
1466 activity_monitor->Fclk_MinActiveFreq,
1467 activity_monitor->Fclk_BoosterFreqType,
1468 activity_monitor->Fclk_BoosterFreq,
1469 activity_monitor->Fclk_PD_Data_limit_c,
1470 activity_monitor->Fclk_PD_Data_error_coeff,
1471 activity_monitor->Fclk_PD_Data_error_rate_coeff);
b455159c 1472
fe14c285 1473 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
b455159c
LG		 1474 " ",
1475 2,
1476 "MEMLK",
f9e3fe46
EQ		 1477 activity_monitor->Mem_FPS,
1478 activity_monitor->Mem_MinFreqStep,
1479 activity_monitor->Mem_MinActiveFreqType,
1480 activity_monitor->Mem_MinActiveFreq,
1481 activity_monitor->Mem_BoosterFreqType,
1482 activity_monitor->Mem_BoosterFreq,
1483 activity_monitor->Mem_PD_Data_limit_c,
1484 activity_monitor->Mem_PD_Data_error_coeff,
1485 activity_monitor->Mem_PD_Data_error_rate_coeff);
b455159c
LG		 1486 }
1487
1488 return size;
1489}
1490
1491static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1492{
f9e3fe46
EQ		 1493
1494 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1495 DpmActivityMonitorCoeffInt_t *activity_monitor =
1496 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
b455159c
LG		 1497 int workload_type, ret = 0;
1498
1499 smu->power_profile_mode = input[size];
1500
1501 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
d9811cfc 1502 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
b455159c
LG		 1503 return -EINVAL;
1504 }
1505
1506 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
b455159c 1507
caad2613 1508 ret = smu_cmn_update_table(smu,
b455159c 1509 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
f9e3fe46 1510 (void *)(&activity_monitor_external), false);
b455159c 1511 if (ret) {
d9811cfc 1512 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
b455159c
LG		 1513 return ret;
1514 }
1515
1516 switch (input[0]) {
1517 case 0: /* Gfxclk */
f9e3fe46
EQ		 1518 activity_monitor->Gfx_FPS = input[1];
1519 activity_monitor->Gfx_MinFreqStep = input[2];
1520 activity_monitor->Gfx_MinActiveFreqType = input[3];
1521 activity_monitor->Gfx_MinActiveFreq = input[4];
1522 activity_monitor->Gfx_BoosterFreqType = input[5];
1523 activity_monitor->Gfx_BoosterFreq = input[6];
1524 activity_monitor->Gfx_PD_Data_limit_c = input[7];
1525 activity_monitor->Gfx_PD_Data_error_coeff = input[8];
1526 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1527 break;
1528 case 1: /* Socclk */
f9e3fe46
EQ		 1529 activity_monitor->Fclk_FPS = input[1];
1530 activity_monitor->Fclk_MinFreqStep = input[2];
1531 activity_monitor->Fclk_MinActiveFreqType = input[3];
1532 activity_monitor->Fclk_MinActiveFreq = input[4];
1533 activity_monitor->Fclk_BoosterFreqType = input[5];
1534 activity_monitor->Fclk_BoosterFreq = input[6];
1535 activity_monitor->Fclk_PD_Data_limit_c = input[7];
1536 activity_monitor->Fclk_PD_Data_error_coeff = input[8];
1537 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1538 break;
1539 case 2: /* Memlk */
f9e3fe46
EQ		 1540 activity_monitor->Mem_FPS = input[1];
1541 activity_monitor->Mem_MinFreqStep = input[2];
1542 activity_monitor->Mem_MinActiveFreqType = input[3];
1543 activity_monitor->Mem_MinActiveFreq = input[4];
1544 activity_monitor->Mem_BoosterFreqType = input[5];
1545 activity_monitor->Mem_BoosterFreq = input[6];
1546 activity_monitor->Mem_PD_Data_limit_c = input[7];
1547 activity_monitor->Mem_PD_Data_error_coeff = input[8];
1548 activity_monitor->Mem_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1549 break;
1550 }
1551
caad2613 1552 ret = smu_cmn_update_table(smu,
b455159c 1553 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
f9e3fe46 1554 (void *)(&activity_monitor_external), true);
b455159c 1555 if (ret) {
d9811cfc 1556 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
b455159c
LG		 1557 return ret;
1558 }
1559 }
1560
1561 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
6c339f37
EQ		 1562 workload_type = smu_cmn_to_asic_specific_index(smu,
1563 CMN2ASIC_MAPPING_WORKLOAD,
1564 smu->power_profile_mode);
b455159c
LG		 1565 if (workload_type < 0)
1566 return -EINVAL;
66c86828 1567 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
b455159c
LG		 1568 1 << workload_type, NULL);
1569
1570 return ret;
1571}
1572
b455159c
LG		 1573static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1574{
1575 struct smu_clocks min_clocks = {0};
1576 struct pp_display_clock_request clock_req;
1577 int ret = 0;
1578
1579 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1580 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1581 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1582
4d942ae3 1583 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
b455159c
LG		 1584 clock_req.clock_type = amd_pp_dcef_clock;
1585 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1586
1587 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1588 if (!ret) {
4d942ae3 1589 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
66c86828 1590 ret = smu_cmn_send_smc_msg_with_param(smu,
40d3b8db
LG		 1591 SMU_MSG_SetMinDeepSleepDcefclk,
1592 min_clocks.dcef_clock_in_sr/100,
1593 NULL);
1594 if (ret) {
d9811cfc 1595 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
40d3b8db
LG		 1596 return ret;
1597 }
b455159c
LG		 1598 }
1599 } else {
d9811cfc 1600 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
b455159c
LG		 1601 }
1602 }
1603
b4bb3aaf 1604 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
661b94f5 1605 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
b455159c 1606 if (ret) {
d9811cfc 1607 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
b455159c
LG		 1608 return ret;
1609 }
1610 }
1611
1612 return 0;
1613}
1614
1615static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
7b9c7e30 1616 struct pp_smu_wm_range_sets *clock_ranges)
b455159c 1617{
e7a95eea 1618 Watermarks_t *table = smu->smu_table.watermarks_table;
40d3b8db 1619 int ret = 0;
e7a95eea 1620 int i;
b455159c 1621
e7a95eea 1622 if (clock_ranges) {
7b9c7e30
EQ		 1623 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1624 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
e7a95eea
EQ		 1625 return -EINVAL;
1626
7b9c7e30
EQ		 1627 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1628 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1629 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1630 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1631 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1632 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1633 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1634 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1635 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1636
1637 table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1638 clock_ranges->reader_wm_sets[i].wm_inst;
e7a95eea 1639 }
b455159c 1640
7b9c7e30
EQ		 1641 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1642 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1643 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1644 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1645 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1646 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1647 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1648 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1649 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1650
1651 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1652 clock_ranges->writer_wm_sets[i].wm_inst;
e7a95eea
EQ		 1653 }
1654
1655 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1656 }
1657
1658 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1659 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
caad2613 1660 ret = smu_cmn_write_watermarks_table(smu);
40d3b8db 1661 if (ret) {
d9811cfc 1662 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
40d3b8db
LG		 1663 return ret;
1664 }
1665 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1666 }
1667
b455159c
LG		 1668 return 0;
1669}
1670
b455159c
LG		 1671static int sienna_cichlid_read_sensor(struct smu_context *smu,
1672 enum amd_pp_sensors sensor,
1673 void *data, uint32_t *size)
1674{
1675 int ret = 0;
7077b19a 1676 uint16_t *temp;
b455159c
LG		 1677
1678 if(!data || !size)
1679 return -EINVAL;
1680
1681 mutex_lock(&smu->sensor_lock);
1682 switch (sensor) {
1683 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
7077b19a
CG		 1684 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
1685 *(uint16_t *)data = *temp;
b455159c
LG		 1686 *size = 4;
1687 break;
1688 case AMDGPU_PP_SENSOR_MEM_LOAD:
60e317a2
AD		 1689 ret = sienna_cichlid_get_smu_metrics_data(smu,
1690 METRICS_AVERAGE_MEMACTIVITY,
1691 (uint32_t *)data);
1692 *size = 4;
1693 break;
b455159c 1694 case AMDGPU_PP_SENSOR_GPU_LOAD:
60e317a2
AD		 1695 ret = sienna_cichlid_get_smu_metrics_data(smu,
1696 METRICS_AVERAGE_GFXACTIVITY,
1697 (uint32_t *)data);
b455159c
LG		 1698 *size = 4;
1699 break;
1700 case AMDGPU_PP_SENSOR_GPU_POWER:
60e317a2
AD		 1701 ret = sienna_cichlid_get_smu_metrics_data(smu,
1702 METRICS_AVERAGE_SOCKETPOWER,
1703 (uint32_t *)data);
b455159c
LG		 1704 *size = 4;
1705 break;
1706 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
60e317a2
AD		 1707 ret = sienna_cichlid_get_smu_metrics_data(smu,
1708 METRICS_TEMPERATURE_HOTSPOT,
1709 (uint32_t *)data);
1710 *size = 4;
1711 break;
b455159c 1712 case AMDGPU_PP_SENSOR_EDGE_TEMP:
60e317a2
AD		 1713 ret = sienna_cichlid_get_smu_metrics_data(smu,
1714 METRICS_TEMPERATURE_EDGE,
1715 (uint32_t *)data);
1716 *size = 4;
1717 break;
b455159c 1718 case AMDGPU_PP_SENSOR_MEM_TEMP:
60e317a2
AD		 1719 ret = sienna_cichlid_get_smu_metrics_data(smu,
1720 METRICS_TEMPERATURE_MEM,
1721 (uint32_t *)data);
b455159c
LG		 1722 *size = 4;
1723 break;
e0f9e936
EQ		 1724 case AMDGPU_PP_SENSOR_GFX_MCLK:
1725 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1726 *(uint32_t *)data *= 100;
1727 *size = 4;
1728 break;
1729 case AMDGPU_PP_SENSOR_GFX_SCLK:
1730 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1731 *(uint32_t *)data *= 100;
1732 *size = 4;
1733 break;
b2febc99
EQ		 1734 case AMDGPU_PP_SENSOR_VDDGFX:
1735 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1736 *size = 4;
1737 break;
b455159c 1738 default:
b2febc99
EQ		 1739 ret = -EOPNOTSUPP;
1740 break;
b455159c
LG		 1741 }
1742 mutex_unlock(&smu->sensor_lock);
1743
1744 return ret;
1745}
1746
1747static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1748{
1749 uint32_t num_discrete_levels = 0;
1750 uint16_t *dpm_levels = NULL;
1751 uint16_t i = 0;
1752 struct smu_table_context *table_context = &smu->smu_table;
7077b19a
CG		 1753 DpmDescriptor_t *table_member1;
1754 uint16_t *table_member2;
b455159c
LG		 1755
1756 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1757 return -EINVAL;
1758
7077b19a
CG		 1759 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
1760 num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
1761 GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
1762 dpm_levels = table_member2;
b455159c
LG		 1763
1764 if (num_discrete_levels == 0 || dpm_levels == NULL)
1765 return -EINVAL;
1766
1767 *num_states = num_discrete_levels;
1768 for (i = 0; i < num_discrete_levels; i++) {
1769 /* convert to khz */
1770 *clocks_in_khz = (*dpm_levels) * 1000;
1771 clocks_in_khz++;
1772 dpm_levels++;
1773 }
1774
1775 return 0;
1776}
1777
1778static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1779 struct smu_temperature_range *range)
1780{
e02e4d51
EQ		 1781 struct smu_table_context *table_context = &smu->smu_table;
1782 struct smu_11_0_7_powerplay_table *powerplay_table =
1783 table_context->power_play_table;
7077b19a
CG		 1784 uint16_t *table_member;
1785 uint16_t temp_edge, temp_hotspot, temp_mem;
b455159c 1786
2b1f12a2 1787 if (!range)
b455159c
LG		 1788 return -EINVAL;
1789
0540eced
EQ		 1790 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1791
7077b19a
CG		 1792 GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
1793 temp_edge = table_member[TEMP_EDGE];
1794 temp_hotspot = table_member[TEMP_HOTSPOT];
1795 temp_mem = table_member[TEMP_MEM];
1796
1797 range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1798 range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
2b1f12a2 1799 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a
CG		 1800 range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1801 range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
2b1f12a2 1802 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a
CG		 1803 range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1804 range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
b455159c 1805 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a 1806
e02e4d51 1807 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
b455159c
LG		 1808
1809 return 0;
1810}
1811
1812static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1813 bool disable_memory_clock_switch)
1814{
1815 int ret = 0;
1816 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1817 (struct smu_11_0_max_sustainable_clocks *)
1818 smu->smu_table.max_sustainable_clocks;
1819 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1820 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1821
1822 if(smu->disable_uclk_switch == disable_memory_clock_switch)
1823 return 0;
1824
1825 if(disable_memory_clock_switch)
661b94f5 1826 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
b455159c 1827 else
661b94f5 1828 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
b455159c
LG		 1829
1830 if(!ret)
1831 smu->disable_uclk_switch = disable_memory_clock_switch;
1832
1833 return ret;
1834}
1835
488f211d
EQ		 1836static int sienna_cichlid_get_power_limit(struct smu_context *smu,
1837 uint32_t *current_power_limit,
1838 uint32_t *default_power_limit,
1839 uint32_t *max_power_limit)
b455159c 1840{
1e239fdd
EQ		 1841 struct smu_11_0_7_powerplay_table *powerplay_table =
1842 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
1e239fdd 1843 uint32_t power_limit, od_percent;
7077b19a
CG		 1844 uint16_t *table_member;
1845
1846 GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
1e239fdd
EQ		 1847
1848 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1e239fdd 1849 power_limit =
7077b19a 1850 table_member[PPT_THROTTLER_PPT0];
1e239fdd 1851 }
b455159c 1852
488f211d
EQ		 1853 if (current_power_limit)
1854 *current_power_limit = power_limit;
1855 if (default_power_limit)
1856 *default_power_limit = power_limit;
1e239fdd 1857
488f211d
EQ		 1858 if (max_power_limit) {
1859 if (smu->od_enabled) {
1860 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
1e239fdd 1861
488f211d
EQ		 1862 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1863
1864 power_limit *= (100 + od_percent);
1865 power_limit /= 100;
1866 }
1867 *max_power_limit = power_limit;
b455159c
LG		 1868 }
1869
b455159c
LG		 1870 return 0;
1871}
1872
08ccfe08
LG		 1873static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1874 uint32_t pcie_gen_cap,
1875 uint32_t pcie_width_cap)
1876{
0b590970 1877 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
7077b19a 1878
08ccfe08 1879 uint32_t smu_pcie_arg;
7077b19a 1880 uint8_t *table_member1, *table_member2;
0b590970 1881 int ret, i;
08ccfe08 1882
7077b19a
CG		 1883 GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
1884 GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
1885
0b590970
EQ		 1886 /* lclk dpm table setup */
1887 for (i = 0; i < MAX_PCIE_CONF; i++) {
7077b19a
CG		 1888 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = table_member1[i];
1889 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = table_member2[i];
0b590970 1890 }
08ccfe08
LG		 1891
1892 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1893 smu_pcie_arg = (i << 16) |
7077b19a
CG		 1894 ((table_member1[i] <= pcie_gen_cap) ?
1895 (table_member1[i] << 8) :
1896 (pcie_gen_cap << 8)) |
1897 ((table_member2[i] <= pcie_width_cap) ?
1898 table_member2[i] :
1899 pcie_width_cap);
08ccfe08 1900
66c86828 1901 ret = smu_cmn_send_smc_msg_with_param(smu,
7077b19a
CG		 1902 SMU_MSG_OverridePcieParameters,
1903 smu_pcie_arg,
1904 NULL);
08ccfe08
LG		 1905 if (ret)
1906 return ret;
1907
7077b19a 1908 if (table_member1[i] > pcie_gen_cap)
08ccfe08 1909 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
7077b19a 1910 if (table_member2[i] > pcie_width_cap)
08ccfe08
LG		 1911 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1912 }
1913
1914 return 0;
1915}
1916
38ed7b09 1917static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
258d290c
LG		 1918 enum smu_clk_type clk_type,
1919 uint32_t *min, uint32_t *max)
1920{
1921 struct amdgpu_device *adev = smu->adev;
1922 int ret;
1923
1924 if (clk_type == SMU_GFXCLK)
1925 amdgpu_gfx_off_ctrl(adev, false);
1926 ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
1927 if (clk_type == SMU_GFXCLK)
1928 amdgpu_gfx_off_ctrl(adev, true);
1929
1930 return ret;
1931}
1932
aa75fa34
EQ		 1933static void sienna_cichlid_dump_od_table(struct smu_context *smu,
1934 OverDriveTable_t *od_table)
1935{
a2b6df4f
EQ		 1936 struct amdgpu_device *adev = smu->adev;
1937 uint32_t smu_version;
1938
aa75fa34
EQ		 1939 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
1940 od_table->GfxclkFmax);
1941 dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
1942 od_table->UclkFmax);
a2b6df4f
EQ		 1943
1944 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1945 if (!((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1946 (smu_version < 0x003a2900)))
1947 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
aa75fa34
EQ		 1948}
1949
1950static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
1951{
1952 OverDriveTable_t *od_table =
1953 (OverDriveTable_t *)smu->smu_table.overdrive_table;
1954 OverDriveTable_t *boot_od_table =
1955 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
b521be9b
EQ		 1956 OverDriveTable_t *user_od_table =
1957 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
aa75fa34
EQ		 1958 int ret = 0;
1959
b521be9b
EQ		 1960 /*
1961 * For S3/S4/Runpm resume, no need to setup those overdrive tables again as
1962 * - either they already have the default OD settings got during cold bootup
1963 * - or they have some user customized OD settings which cannot be overwritten
1964 */
1965 if (smu->adev->in_suspend)
1966 return 0;
1967
aa75fa34 1968 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
b521be9b 1969 0, (void *)boot_od_table, false);
aa75fa34
EQ		 1970 if (ret) {
1971 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
1972 return ret;
1973 }
1974
b521be9b 1975 sienna_cichlid_dump_od_table(smu, boot_od_table);
aa75fa34 1976
b521be9b
EQ		 1977 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
1978 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
aa75fa34
EQ		 1979
1980 return 0;
1981}
1982
37a58f69
EQ		 1983static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
1984 struct smu_11_0_7_overdrive_table *od_table,
1985 enum SMU_11_0_7_ODSETTING_ID setting,
1986 uint32_t value)
1987{
1988 if (value < od_table->min[setting]) {
1989 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
1990 setting, value, od_table->min[setting]);
1991 return -EINVAL;
1992 }
1993 if (value > od_table->max[setting]) {
1994 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
1995 setting, value, od_table->max[setting]);
1996 return -EINVAL;
1997 }
1998
1999 return 0;
2000}
2001
2002static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
2003 enum PP_OD_DPM_TABLE_COMMAND type,
2004 long input[], uint32_t size)
2005{
2006 struct smu_table_context *table_context = &smu->smu_table;
2007 OverDriveTable_t *od_table =
2008 (OverDriveTable_t *)table_context->overdrive_table;
2009 struct smu_11_0_7_overdrive_table *od_settings =
2010 (struct smu_11_0_7_overdrive_table *)smu->od_settings;
a2b6df4f 2011 struct amdgpu_device *adev = smu->adev;
37a58f69
EQ		 2012 enum SMU_11_0_7_ODSETTING_ID freq_setting;
2013 uint16_t *freq_ptr;
2014 int i, ret = 0;
a2b6df4f 2015 uint32_t smu_version;
37a58f69
EQ		 2016
2017 if (!smu->od_enabled) {
2018 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2019 return -EINVAL;
2020 }
2021
2022 if (!smu->od_settings) {
2023 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2024 return -ENOENT;
2025 }
2026
2027 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2028 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2029 return -EINVAL;
2030 }
2031
2032 switch (type) {
2033 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2034 if (!sienna_cichlid_is_od_feature_supported(od_settings,
2035 SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
2036 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2037 return -ENOTSUPP;
2038 }
2039
2040 for (i = 0; i < size; i += 2) {
2041 if (i + 2 > size) {
2042 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2043 return -EINVAL;
2044 }
2045
2046 switch (input[i]) {
2047 case 0:
2048 if (input[i + 1] > od_table->GfxclkFmax) {
2049 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2050 input[i + 1], od_table->GfxclkFmax);
2051 return -EINVAL;
2052 }
2053
2054 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
2055 freq_ptr = &od_table->GfxclkFmin;
2056 break;
2057
2058 case 1:
2059 if (input[i + 1] < od_table->GfxclkFmin) {
2060 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2061 input[i + 1], od_table->GfxclkFmin);
2062 return -EINVAL;
2063 }
2064
2065 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
2066 freq_ptr = &od_table->GfxclkFmax;
2067 break;
2068
2069 default:
2070 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2071 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2072 return -EINVAL;
2073 }
2074
2075 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2076 freq_setting, input[i + 1]);
2077 if (ret)
2078 return ret;
2079
2080 *freq_ptr = (uint16_t)input[i + 1];
2081 }
2082 break;
2083
2084 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2085 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
2086 dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2087 return -ENOTSUPP;
2088 }
2089
2090 for (i = 0; i < size; i += 2) {
2091 if (i + 2 > size) {
2092 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2093 return -EINVAL;
2094 }
2095
2096 switch (input[i]) {
2097 case 0:
2098 if (input[i + 1] > od_table->UclkFmax) {
2099 dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2100 input[i + 1], od_table->UclkFmax);
2101 return -EINVAL;
2102 }
2103
2104 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
2105 freq_ptr = &od_table->UclkFmin;
2106 break;
2107
2108 case 1:
2109 if (input[i + 1] < od_table->UclkFmin) {
2110 dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2111 input[i + 1], od_table->UclkFmin);
2112 return -EINVAL;
2113 }
2114
2115 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
2116 freq_ptr = &od_table->UclkFmax;
2117 break;
2118
2119 default:
2120 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2121 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2122 return -EINVAL;
2123 }
2124
2125 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2126 freq_setting, input[i + 1]);
2127 if (ret)
2128 return ret;
2129
2130 *freq_ptr = (uint16_t)input[i + 1];
2131 }
2132 break;
2133
2134 case PP_OD_RESTORE_DEFAULT_TABLE:
2135 memcpy(table_context->overdrive_table,
2136 table_context->boot_overdrive_table,
2137 sizeof(OverDriveTable_t));
2138 fallthrough;
2139
2140 case PP_OD_COMMIT_DPM_TABLE:
b521be9b
EQ		 2141 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2142 sienna_cichlid_dump_od_table(smu, od_table);
2143 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2144 if (ret) {
2145 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2146 return ret;
2147 }
2148 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2149 smu->user_dpm_profile.user_od = true;
37a58f69 2150
b521be9b
EQ		 2151 if (!memcmp(table_context->user_overdrive_table,
2152 table_context->boot_overdrive_table,
2153 sizeof(OverDriveTable_t)))
2154 smu->user_dpm_profile.user_od = false;
37a58f69
EQ		 2155 }
2156 break;
2157
a2b6df4f
EQ		 2158 case PP_OD_EDIT_VDDGFX_OFFSET:
2159 if (size != 1) {
2160 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2161 return -EINVAL;
2162 }
2163
2164 /*
2165 * OD GFX Voltage Offset functionality is supported only by 58.41.0
2166 * and onwards SMU firmwares.
2167 */
2168 smu_cmn_get_smc_version(smu, NULL, &smu_version);
2169 if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
2170 (smu_version < 0x003a2900)) {
2171 dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2172 "only by 58.41.0 and onwards SMU firmwares!\n");
2173 return -EOPNOTSUPP;
2174 }
2175
2176 od_table->VddGfxOffset = (int16_t)input[0];
2177
2178 sienna_cichlid_dump_od_table(smu, od_table);
2179 break;
2180
37a58f69
EQ		 2181 default:
2182 return -ENOSYS;
2183 }
2184
2185 return ret;
2186}
2187
66b8a9c0
JC		 2188static int sienna_cichlid_run_btc(struct smu_context *smu)
2189{
2190 return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2191}
2192
13d75ead
EQ		 2193static int sienna_cichlid_baco_enter(struct smu_context *smu)
2194{
2195 struct amdgpu_device *adev = smu->adev;
2196
2197 if (adev->in_runpm)
2198 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2199 else
2200 return smu_v11_0_baco_enter(smu);
2201}
2202
2203static int sienna_cichlid_baco_exit(struct smu_context *smu)
2204{
2205 struct amdgpu_device *adev = smu->adev;
2206
2207 if (adev->in_runpm) {
2208 /* Wait for PMFW handling for the Dstate change */
2209 msleep(10);
2210 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2211 } else {
2212 return smu_v11_0_baco_exit(smu);
2213 }
2214}
2215
ea8139d8
WS		 2216static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2217{
2218 struct amdgpu_device *adev = smu->adev;
2219 uint32_t val;
2220 u32 smu_version;
2221
2222 /**
2223 * SRIOV env will not support SMU mode1 reset
2224 * PM FW support mode1 reset from 58.26
2225 */
a7bae061 2226 smu_cmn_get_smc_version(smu, NULL, &smu_version);
ea8139d8
WS		 2227 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
2228 return false;
2229
2230 /**
2231 * mode1 reset relies on PSP, so we should check if
2232 * PSP is alive.
2233 */
2234 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2235 return val != 0x0;
2236}
2237
7077b19a
CG		 2238static void beige_goby_dump_pptable(struct smu_context *smu)
2239{
2240 struct smu_table_context *table_context = &smu->smu_table;
2241 PPTable_beige_goby_t *pptable = table_context->driver_pptable;
2242 int i;
2243
2244 dev_info(smu->adev->dev, "Dumped PPTable:\n");
2245
2246 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2247 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2248 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2249
2250 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2251 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2252 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2253 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2254 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2255 }
2256
2257 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2258 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2259 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2260 }
2261
2262 for (i = 0; i < TEMP_COUNT; i++) {
2263 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2264 }
2265
2266 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2267 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2268 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2269 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2270 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2271
2272 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2273 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2274 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2275 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2276 }
2277 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2278
2279 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2280
2281 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2282 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2283 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2284 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2285
2286 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2287
2288 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2289
2290 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2291 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2292 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2293 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2294
2295 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2296 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2297
2298 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2299 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2300 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2301 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2302 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2303 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2304 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2305 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2306
2307 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2308 " .VoltageMode = 0x%02x\n"
2309 " .SnapToDiscrete = 0x%02x\n"
2310 " .NumDiscreteLevels = 0x%02x\n"
2311 " .padding = 0x%02x\n"
2312 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2313 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2314 " .SsFmin = 0x%04x\n"
2315 " .Padding_16 = 0x%04x\n",
2316 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2317 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2318 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2319 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2320 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2321 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2322 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2323 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2324 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2325 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2326 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2327
2328 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2329 " .VoltageMode = 0x%02x\n"
2330 " .SnapToDiscrete = 0x%02x\n"
2331 " .NumDiscreteLevels = 0x%02x\n"
2332 " .padding = 0x%02x\n"
2333 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2334 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2335 " .SsFmin = 0x%04x\n"
2336 " .Padding_16 = 0x%04x\n",
2337 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2338 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2339 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2340 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2341 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2342 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2343 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2344 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2345 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2346 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2347 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2348
2349 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2350 " .VoltageMode = 0x%02x\n"
2351 " .SnapToDiscrete = 0x%02x\n"
2352 " .NumDiscreteLevels = 0x%02x\n"
2353 " .padding = 0x%02x\n"
2354 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2355 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2356 " .SsFmin = 0x%04x\n"
2357 " .Padding_16 = 0x%04x\n",
2358 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2359 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2360 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2361 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2362 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2363 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2364 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2365 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2366 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2367 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2368 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2369
2370 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2371 " .VoltageMode = 0x%02x\n"
2372 " .SnapToDiscrete = 0x%02x\n"
2373 " .NumDiscreteLevels = 0x%02x\n"
2374 " .padding = 0x%02x\n"
2375 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2376 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2377 " .SsFmin = 0x%04x\n"
2378 " .Padding_16 = 0x%04x\n",
2379 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2380 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2381 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2382 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2383 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2384 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2385 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2386 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2387 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2388 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2389 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2390
2391 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2392 " .VoltageMode = 0x%02x\n"
2393 " .SnapToDiscrete = 0x%02x\n"
2394 " .NumDiscreteLevels = 0x%02x\n"
2395 " .padding = 0x%02x\n"
2396 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2397 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2398 " .SsFmin = 0x%04x\n"
2399 " .Padding_16 = 0x%04x\n",
2400 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2401 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2402 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2403 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2404 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2405 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2406 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2407 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2408 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2409 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2410 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2411
2412 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2413 " .VoltageMode = 0x%02x\n"
2414 " .SnapToDiscrete = 0x%02x\n"
2415 " .NumDiscreteLevels = 0x%02x\n"
2416 " .padding = 0x%02x\n"
2417 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2418 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2419 " .SsFmin = 0x%04x\n"
2420 " .Padding_16 = 0x%04x\n",
2421 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2422 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2423 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2424 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2425 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2426 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2427 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2428 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2429 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2430 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2431 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2432
2433 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2434 " .VoltageMode = 0x%02x\n"
2435 " .SnapToDiscrete = 0x%02x\n"
2436 " .NumDiscreteLevels = 0x%02x\n"
2437 " .padding = 0x%02x\n"
2438 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2439 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2440 " .SsFmin = 0x%04x\n"
2441 " .Padding_16 = 0x%04x\n",
2442 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2443 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2444 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2445 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2446 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2447 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2448 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2449 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2450 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2451 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2452 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2453
2454 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2455 " .VoltageMode = 0x%02x\n"
2456 " .SnapToDiscrete = 0x%02x\n"
2457 " .NumDiscreteLevels = 0x%02x\n"
2458 " .padding = 0x%02x\n"
2459 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2460 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2461 " .SsFmin = 0x%04x\n"
2462 " .Padding_16 = 0x%04x\n",
2463 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2464 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2465 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2466 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2467 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2468 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2469 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2470 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2471 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2472 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2473 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2474
2475 dev_info(smu->adev->dev, "FreqTableGfx\n");
2476 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2477 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2478
2479 dev_info(smu->adev->dev, "FreqTableVclk\n");
2480 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2481 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2482
2483 dev_info(smu->adev->dev, "FreqTableDclk\n");
2484 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2485 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2486
2487 dev_info(smu->adev->dev, "FreqTableSocclk\n");
2488 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2489 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2490
2491 dev_info(smu->adev->dev, "FreqTableUclk\n");
2492 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2493 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2494
2495 dev_info(smu->adev->dev, "FreqTableFclk\n");
2496 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2497 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2498
2499 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2500 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2501 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2502 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2503 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2504 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2505 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2506 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2507 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2508
2509 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2510 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2511 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2512
2513 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2514 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2515
2516 dev_info(smu->adev->dev, "Mp0clkFreq\n");
2517 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2518 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2519
2520 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2521 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2522 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2523
2524 dev_info(smu->adev->dev, "MemVddciVoltage\n");
2525 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2526 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2527
2528 dev_info(smu->adev->dev, "MemMvddVoltage\n");
2529 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2530 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2531
2532 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2533 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2534 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2535 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2536 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2537
2538 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2539
2540 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2541 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2542 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2543 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2544 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2545 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2546 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2547 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2548 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2549 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2550 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2551
2552 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2553 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2554 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2555 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2556 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2557 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2558
2559 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2560 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2561 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2562 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2563 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2564
2565 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2566 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2567 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2568
2569 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2570 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2571 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2572 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2573
2574 dev_info(smu->adev->dev, "UclkDpmPstates\n");
2575 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2576 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2577
2578 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2579 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2580 pptable->UclkDpmSrcFreqRange.Fmin);
2581 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2582 pptable->UclkDpmSrcFreqRange.Fmax);
2583 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2584 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2585 pptable->UclkDpmTargFreqRange.Fmin);
2586 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2587 pptable->UclkDpmTargFreqRange.Fmax);
2588 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2589 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2590
2591 dev_info(smu->adev->dev, "PcieGenSpeed\n");
2592 for (i = 0; i < NUM_LINK_LEVELS; i++)
2593 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2594
2595 dev_info(smu->adev->dev, "PcieLaneCount\n");
2596 for (i = 0; i < NUM_LINK_LEVELS; i++)
2597 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2598
2599 dev_info(smu->adev->dev, "LclkFreq\n");
2600 for (i = 0; i < NUM_LINK_LEVELS; i++)
2601 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2602
2603 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2604 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2605
2606 dev_info(smu->adev->dev, "FanGain\n");
2607 for (i = 0; i < TEMP_COUNT; i++)
2608 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2609
2610 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2611 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2612 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2613 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2614 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2615 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2616 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2617 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2618 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2619 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2620 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2621 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2622
2623 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2624 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2625 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2626 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2627
2628 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2629 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2630 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2631 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2632
2633 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2634 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2635 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2636 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2637 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2638 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2639 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2640 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2641 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2642 pptable->dBtcGbGfxPll.a,
2643 pptable->dBtcGbGfxPll.b,
2644 pptable->dBtcGbGfxPll.c);
2645 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2646 pptable->dBtcGbGfxDfll.a,
2647 pptable->dBtcGbGfxDfll.b,
2648 pptable->dBtcGbGfxDfll.c);
2649 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2650 pptable->dBtcGbSoc.a,
2651 pptable->dBtcGbSoc.b,
2652 pptable->dBtcGbSoc.c);
2653 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2654 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2655 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2656 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2657 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2658 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2659
2660 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2661 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2662 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
2663 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2664 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
2665 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2666 }
2667
2668 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2669 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2670 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2671 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2672 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2673 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2674 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2675 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2676
2677 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2678 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2679
2680 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2681 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2682 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2683 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2684
2685 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2686 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2687 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2688 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2689
2690 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2691 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2692
2693 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2694 for (i = 0; i < NUM_XGMI_LEVELS; i++)
2695 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2696 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2697 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2698
2699 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2700 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2701 pptable->ReservedEquation0.a,
2702 pptable->ReservedEquation0.b,
2703 pptable->ReservedEquation0.c);
2704 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2705 pptable->ReservedEquation1.a,
2706 pptable->ReservedEquation1.b,
2707 pptable->ReservedEquation1.c);
2708 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2709 pptable->ReservedEquation2.a,
2710 pptable->ReservedEquation2.b,
2711 pptable->ReservedEquation2.c);
2712 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2713 pptable->ReservedEquation3.a,
2714 pptable->ReservedEquation3.b,
2715 pptable->ReservedEquation3.c);
2716
2717 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2718 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2719 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2720 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2721 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2722 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2723 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2724 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2725
2726 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2727 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2728 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2729 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2730 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2731 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2732
2733 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2734 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2735 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
2736 pptable->I2cControllers[i].Enabled);
2737 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
2738 pptable->I2cControllers[i].Speed);
2739 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
2740 pptable->I2cControllers[i].SlaveAddress);
2741 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
2742 pptable->I2cControllers[i].ControllerPort);
2743 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
2744 pptable->I2cControllers[i].ControllerName);
2745 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
2746 pptable->I2cControllers[i].ThermalThrotter);
2747 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
2748 pptable->I2cControllers[i].I2cProtocol);
2749 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
2750 pptable->I2cControllers[i].PaddingConfig);
2751 }
2752
2753 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2754 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2755 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2756 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2757
2758 dev_info(smu->adev->dev, "Board Parameters:\n");
2759 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2760 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2761 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2762 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2763 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2764 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2765 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2766 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2767
2768 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2769 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2770 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2771
2772 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2773 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2774 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2775
2776 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2777 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2778 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2779
2780 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2781 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2782 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2783
2784 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2785
2786 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2787 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2788 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2789 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2790 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2791 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2792 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2793 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2794 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2795 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2796 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2797 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2798 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2799 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2800 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2801 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2802
2803 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2804 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2805 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
2806
2807 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2808 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2809 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
2810
2811 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
2812 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2813
2814 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2815 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2816 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2817
2818 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2819 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2820 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2821 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2822 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2823
2824 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2825 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2826
2827 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
2828 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2829 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2830 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
2831 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2832 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2833 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
2834 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2835 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2836 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
2837 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2838 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2839
2840 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2841 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2842 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2843 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2844
2845 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2846 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2847 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2848 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2849 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2850 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2851 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2852 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2853 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2854 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2855 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2856
2857 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2858 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2859 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2860 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2861 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2862 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2863 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2864 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2865}
2866
b455159c
LG		 2867static void sienna_cichlid_dump_pptable(struct smu_context *smu)
2868{
2869 struct smu_table_context *table_context = &smu->smu_table;
2870 PPTable_t *pptable = table_context->driver_pptable;
2871 int i;
2872
7077b19a
CG		 2873 if (smu->adev->asic_type == CHIP_BEIGE_GOBY) {
2874 beige_goby_dump_pptable(smu);
2875 return;
2876 }
2877
d9811cfc 2878 dev_info(smu->adev->dev, "Dumped PPTable:\n");
b455159c 2879
d9811cfc
EQ		 2880 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2881 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2882 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
b455159c
LG		 2883
2884 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
d9811cfc
EQ		 2885 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2886 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2887 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2888 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
b455159c
LG		 2889 }
2890
2891 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
d9811cfc
EQ		 2892 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2893 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
b455159c
LG		 2894 }
2895
2896 for (i = 0; i < TEMP_COUNT; i++) {
d9811cfc 2897 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
b455159c
LG		 2898 }
2899
d9811cfc
EQ		 2900 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2901 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2902 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2903 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2904 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
b455159c 2905
d9811cfc 2906 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
b455159c 2907 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
d9811cfc
EQ		 2908 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2909 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
b455159c 2910 }
d9811cfc
EQ		 2911 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2912
2913 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2914
2915 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2916 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2917 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2918 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2919
2920 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2921 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
2922
2923 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2924 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
2925 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
2926 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
2927
2928 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2929 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2930 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2931 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2932
2933 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2934 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2935
2936 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2937 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2938 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2939 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2940 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2941 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2942 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2943 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2944
2945 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
b455159c
LG		 2946 " .VoltageMode = 0x%02x\n"
2947 " .SnapToDiscrete = 0x%02x\n"
2948 " .NumDiscreteLevels = 0x%02x\n"
2949 " .padding = 0x%02x\n"
2950 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2951 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2952 " .SsFmin = 0x%04x\n"
2953 " .Padding_16 = 0x%04x\n",
2954 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2955 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2956 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2957 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2958 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2959 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2960 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2961 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2962 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2963 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2964 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2965
d9811cfc 2966 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
b455159c
LG		 2967 " .VoltageMode = 0x%02x\n"
2968 " .SnapToDiscrete = 0x%02x\n"
2969 " .NumDiscreteLevels = 0x%02x\n"
2970 " .padding = 0x%02x\n"
2971 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2972 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2973 " .SsFmin = 0x%04x\n"
2974 " .Padding_16 = 0x%04x\n",
2975 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2976 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2977 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2978 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2979 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2980 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2981 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2982 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2983 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2984 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2985 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2986
d9811cfc 2987 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
b455159c
LG		 2988 " .VoltageMode = 0x%02x\n"
2989 " .SnapToDiscrete = 0x%02x\n"
2990 " .NumDiscreteLevels = 0x%02x\n"
2991 " .padding = 0x%02x\n"
2992 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2993 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2994 " .SsFmin = 0x%04x\n"
2995 " .Padding_16 = 0x%04x\n",
2996 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2997 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2998 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2999 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
3000 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
3001 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
3002 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
3003 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
3004 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
3005 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
3006 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
3007
d9811cfc 3008 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
b455159c
LG		 3009 " .VoltageMode = 0x%02x\n"
3010 " .SnapToDiscrete = 0x%02x\n"
3011 " .NumDiscreteLevels = 0x%02x\n"
3012 " .padding = 0x%02x\n"
3013 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3014 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3015 " .SsFmin = 0x%04x\n"
3016 " .Padding_16 = 0x%04x\n",
3017 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
3018 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
3019 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
3020 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
3021 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
3022 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
3023 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
3024 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
3025 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
3026 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
3027 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
3028
d9811cfc 3029 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
b455159c
LG		 3030 " .VoltageMode = 0x%02x\n"
3031 " .SnapToDiscrete = 0x%02x\n"
3032 " .NumDiscreteLevels = 0x%02x\n"
3033 " .padding = 0x%02x\n"
3034 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3035 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3036 " .SsFmin = 0x%04x\n"
3037 " .Padding_16 = 0x%04x\n",
3038 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
3039 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
3040 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
3041 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
3042 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
3043 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
3044 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
3045 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
3046 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
3047 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
3048 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
3049
d9811cfc 3050 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
b455159c
LG		 3051 " .VoltageMode = 0x%02x\n"
3052 " .SnapToDiscrete = 0x%02x\n"
3053 " .NumDiscreteLevels = 0x%02x\n"
3054 " .padding = 0x%02x\n"
3055 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3056 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3057 " .SsFmin = 0x%04x\n"
3058 " .Padding_16 = 0x%04x\n",
3059 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
3060 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
3061 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
3062 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
3063 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
3064 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
3065 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
3066 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
3067 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
3068 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
3069 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
3070
d9811cfc 3071 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
b455159c
LG		 3072 " .VoltageMode = 0x%02x\n"
3073 " .SnapToDiscrete = 0x%02x\n"
3074 " .NumDiscreteLevels = 0x%02x\n"
3075 " .padding = 0x%02x\n"
3076 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3077 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3078 " .SsFmin = 0x%04x\n"
3079 " .Padding_16 = 0x%04x\n",
3080 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
3081 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
3082 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
3083 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
3084 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
3085 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
3086 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
3087 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
3088 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
3089 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
3090 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
3091
d9811cfc 3092 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
b455159c
LG		 3093 " .VoltageMode = 0x%02x\n"
3094 " .SnapToDiscrete = 0x%02x\n"
3095 " .NumDiscreteLevels = 0x%02x\n"
3096 " .padding = 0x%02x\n"
3097 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3098 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3099 " .SsFmin = 0x%04x\n"
3100 " .Padding_16 = 0x%04x\n",
3101 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
3102 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
3103 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
3104 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
3105 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
3106 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
3107 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
3108 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
3109 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
3110 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
3111 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
3112
d9811cfc 3113 dev_info(smu->adev->dev, "FreqTableGfx\n");
b455159c 3114 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
d9811cfc 3115 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
b455159c 3116
d9811cfc 3117 dev_info(smu->adev->dev, "FreqTableVclk\n");
b455159c 3118 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
d9811cfc 3119 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
b455159c 3120
d9811cfc 3121 dev_info(smu->adev->dev, "FreqTableDclk\n");
b455159c 3122 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
d9811cfc 3123 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
b455159c 3124
d9811cfc 3125 dev_info(smu->adev->dev, "FreqTableSocclk\n");
b455159c 3126 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
d9811cfc 3127 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
b455159c 3128
d9811cfc 3129 dev_info(smu->adev->dev, "FreqTableUclk\n");
b455159c 3130 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3131 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
b455159c 3132
d9811cfc 3133 dev_info(smu->adev->dev, "FreqTableFclk\n");
b455159c 3134 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
d9811cfc
EQ		 3135 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
3136
d9811cfc
EQ		 3137 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
3138 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
3139 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
3140 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
3141 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
3142 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
3143 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
3144 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
3145 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
3146
3147 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
b455159c 3148 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3149 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
b455159c 3150
d9811cfc
EQ		 3151 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
3152 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
b455159c 3153
d9811cfc 3154 dev_info(smu->adev->dev, "Mp0clkFreq\n");
b455159c 3155 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc 3156 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
b455159c 3157
d9811cfc 3158 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
b455159c 3159 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc 3160 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
b455159c 3161
d9811cfc 3162 dev_info(smu->adev->dev, "MemVddciVoltage\n");
b455159c 3163 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3164 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
b455159c 3165
d9811cfc 3166 dev_info(smu->adev->dev, "MemMvddVoltage\n");
b455159c 3167 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc
EQ		 3168 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
3169
3170 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
3171 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
3172 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
3173 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
3174 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
3175
3176 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
3177
3178 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
3179 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
3180 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
3181 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
3182 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
3183 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
3184 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
3185 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
3186 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
3187 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
3188 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
3189
3190 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
3191 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
3192 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
3193 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
3194 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
3195 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
3196
3197 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
3198 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
3199 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
3200 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
3201 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
3202
3203 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
b455159c 3204 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
d9811cfc 3205 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
b455159c 3206
d9811cfc
EQ		 3207 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
3208 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
3209 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
3210 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
b455159c 3211
d9811cfc 3212 dev_info(smu->adev->dev, "UclkDpmPstates\n");
b455159c 3213 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3214 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
b455159c 3215
d9811cfc
EQ		 3216 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
3217 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
b455159c 3218 pptable->UclkDpmSrcFreqRange.Fmin);
d9811cfc 3219 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
b455159c 3220 pptable->UclkDpmSrcFreqRange.Fmax);
d9811cfc
EQ		 3221 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
3222 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
b455159c 3223 pptable->UclkDpmTargFreqRange.Fmin);
d9811cfc 3224 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
b455159c 3225 pptable->UclkDpmTargFreqRange.Fmax);
d9811cfc
EQ		 3226 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
3227 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
b455159c 3228
d9811cfc 3229 dev_info(smu->adev->dev, "PcieGenSpeed\n");
b455159c 3230 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3231 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
b455159c 3232
d9811cfc 3233 dev_info(smu->adev->dev, "PcieLaneCount\n");
b455159c 3234 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3235 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
b455159c 3236
d9811cfc 3237 dev_info(smu->adev->dev, "LclkFreq\n");
b455159c 3238 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3239 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
b455159c 3240
d9811cfc
EQ		 3241 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
3242 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
b455159c 3243
d9811cfc 3244 dev_info(smu->adev->dev, "FanGain\n");
b455159c 3245 for (i = 0; i < TEMP_COUNT; i++)
d9811cfc
EQ		 3246 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
3247
3248 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
3249 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
3250 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
3251 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
3252 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
3253 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
3254 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
3255 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
3256 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
3257 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
3258 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
3259 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
3260
3261 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
3262 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
3263 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
3264 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
3265
3266 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
3267 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
3268 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
3269 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
3270
3271 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3272 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
3273 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
3274 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
d9811cfc 3275 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3276 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
3277 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
3278 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
d9811cfc 3279 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3280 pptable->dBtcGbGfxPll.a,
3281 pptable->dBtcGbGfxPll.b,
3282 pptable->dBtcGbGfxPll.c);
d9811cfc 3283 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3284 pptable->dBtcGbGfxDfll.a,
3285 pptable->dBtcGbGfxDfll.b,
3286 pptable->dBtcGbGfxDfll.c);
d9811cfc 3287 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3288 pptable->dBtcGbSoc.a,
3289 pptable->dBtcGbSoc.b,
3290 pptable->dBtcGbSoc.c);
d9811cfc 3291 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
b455159c
LG		 3292 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
3293 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
d9811cfc 3294 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
b455159c
LG		 3295 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
3296 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
3297
d9811cfc 3298 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
b455159c 3299 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
d9811cfc 3300 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
b455159c 3301 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
d9811cfc 3302 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
b455159c
LG		 3303 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
3304 }
3305
d9811cfc 3306 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3307 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
3308 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
3309 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
d9811cfc 3310 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3311 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
3312 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
3313 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
3314
d9811cfc
EQ		 3315 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
3316 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
b455159c 3317
d9811cfc
EQ		 3318 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
3319 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
3320 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
3321 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
b455159c 3322
d9811cfc
EQ		 3323 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
3324 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
3325 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
3326 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
b455159c 3327
d9811cfc
EQ		 3328 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
3329 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
b455159c 3330
d9811cfc 3331 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
b455159c 3332 for (i = 0; i < NUM_XGMI_LEVELS; i++)
d9811cfc
EQ		 3333 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
3334 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
3335 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
b455159c 3336
d9811cfc
EQ		 3337 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
3338 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3339 pptable->ReservedEquation0.a,
3340 pptable->ReservedEquation0.b,
3341 pptable->ReservedEquation0.c);
d9811cfc 3342 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3343 pptable->ReservedEquation1.a,
3344 pptable->ReservedEquation1.b,
3345 pptable->ReservedEquation1.c);
d9811cfc 3346 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3347 pptable->ReservedEquation2.a,
3348 pptable->ReservedEquation2.b,
3349 pptable->ReservedEquation2.c);
d9811cfc 3350 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3351 pptable->ReservedEquation3.a,
3352 pptable->ReservedEquation3.b,
3353 pptable->ReservedEquation3.c);
3354
d9811cfc
EQ		 3355 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3356 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3357 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3358 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3359 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3360 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3361 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3362 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
d9811cfc
EQ		 3363
3364 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3365 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3366 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3367 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3368 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3369 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
b455159c
LG		 3370
3371 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
d9811cfc
EQ		 3372 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3373 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
b455159c 3374 pptable->I2cControllers[i].Enabled);
d9811cfc 3375 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
b455159c 3376 pptable->I2cControllers[i].Speed);
d9811cfc 3377 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
b455159c 3378 pptable->I2cControllers[i].SlaveAddress);
d9811cfc 3379 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
b455159c 3380 pptable->I2cControllers[i].ControllerPort);
d9811cfc 3381 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
b455159c 3382 pptable->I2cControllers[i].ControllerName);
d9811cfc 3383 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
b455159c 3384 pptable->I2cControllers[i].ThermalThrotter);
d9811cfc 3385 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
b455159c 3386 pptable->I2cControllers[i].I2cProtocol);
d9811cfc 3387 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
b455159c
LG		 3388 pptable->I2cControllers[i].PaddingConfig);
3389 }
3390
d9811cfc
EQ		 3391 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3392 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3393 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3394 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3395
3396 dev_info(smu->adev->dev, "Board Parameters:\n");
3397 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3398 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3399 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3400 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3401 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3402 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3403 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3404 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3405
3406 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3407 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3408 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3409
3410 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3411 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3412 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3413
3414 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3415 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3416 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3417
3418 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3419 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3420 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3421
3422 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3423
3424 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3425 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3426 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3427 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3428 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3429 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3430 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3431 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3432 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3433 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3434 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3435 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3436 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3437 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3438 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3439 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3440
3441 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3442 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3443 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3444
3445 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3446 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3447 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3448
f0f3d68e 3449 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
d9811cfc
EQ		 3450 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3451
3452 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3453 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3454 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3455
3456 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3457 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3458 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3459 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3460 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3461
3462 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3463 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3464
3465 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
b455159c 3466 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3467 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3468 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
b455159c 3469 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3470 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3471 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
b455159c 3472 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3473 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3474 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
b455159c 3475 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3476 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3477
3478 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3479 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3480 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3481 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3482
3483 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3484 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3485 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3486 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3487 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3488 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3489 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3490 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3491 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3492 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3493 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
d9811cfc
EQ		 3494
3495 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3496 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3497 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3498 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3499 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3500 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3501 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3502 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
b455159c
LG		 3503}
3504
5125c96a 3505static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
ebe57d0c 3506 struct i2c_msg *msg, int num_msgs)
bc50ca29 3507{
5125c96a 3508 struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
bc50ca29
AD		 3509 struct smu_table_context *smu_table = &adev->smu.smu_table;
3510 struct smu_table *table = &smu_table->driver_table;
5125c96a 3511 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
ebe57d0c
LT		 3512 int i, j, r, c;
3513 u16 dir;
d74a09c8 3514
5125c96a
AD		 3515 req = kzalloc(sizeof(*req), GFP_KERNEL);
3516 if (!req)
3517 return -ENOMEM;
bc50ca29 3518
5125c96a
AD		 3519 req->I2CcontrollerPort = 1;
3520 req->I2CSpeed = I2C_SPEED_FAST_400K;
ebe57d0c
LT		 3521 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
3522 dir = msg[0].flags & I2C_M_RD;
bc50ca29 3523
ebe57d0c
LT		 3524 for (c = i = 0; i < num_msgs; i++) {
3525 for (j = 0; j < msg[i].len; j++, c++) {
3526 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
bc50ca29 3527
5125c96a
AD		 3528 if (!(msg[i].flags & I2C_M_RD)) {
3529 /* write */
3530 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
ebe57d0c
LT		 3531 cmd->ReadWriteData = msg[i].buf[j];
3532 }
3533
3534 if ((dir ^ msg[i].flags) & I2C_M_RD) {
3535 /* The direction changes.
3536 */
3537 dir = msg[i].flags & I2C_M_RD;
3538 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
5125c96a 3539 }
14df5650 3540
ebe57d0c
LT		 3541 req->NumCmds++;
3542
14df5650
AG		 3543 /*
3544 * Insert STOP if we are at the last byte of either last
3545 * message for the transaction or the client explicitly
3546 * requires a STOP at this particular message.
3547 */
ebe57d0c
LT		 3548 if ((j == msg[i].len - 1) &&
3549 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
3550 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
5125c96a 3551 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
ebe57d0c 3552 }
5125c96a 3553 }
d74a09c8 3554 }
bc50ca29 3555 mutex_lock(&adev->smu.mutex);
5125c96a 3556 r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
bc50ca29 3557 mutex_unlock(&adev->smu.mutex);
5125c96a
AD		 3558 if (r)
3559 goto fail;
bc50ca29 3560
ebe57d0c
LT		 3561 for (c = i = 0; i < num_msgs; i++) {
3562 if (!(msg[i].flags & I2C_M_RD)) {
3563 c += msg[i].len;
3564 continue;
3565 }
3566 for (j = 0; j < msg[i].len; j++, c++) {
3567 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
bc50ca29 3568
ebe57d0c 3569 msg[i].buf[j] = cmd->ReadWriteData;
bc50ca29
AD		 3570 }
3571 }
ebe57d0c 3572 r = num_msgs;
bc50ca29 3573fail:
5125c96a 3574 kfree(req);
5125c96a 3575 return r;
bc50ca29
AD		 3576}
3577
3578static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
3579{
3580 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3581}
3582
3583
3584static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
3585 .master_xfer = sienna_cichlid_i2c_xfer,
3586 .functionality = sienna_cichlid_i2c_func,
3587};
3588
35ed2703 3589static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = {
c0838d3a 3590 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
16736627 3591 .max_read_len = MAX_SW_I2C_COMMANDS,
35ed2703 3592 .max_write_len = MAX_SW_I2C_COMMANDS,
16736627
LT		 3593 .max_comb_1st_msg_len = 2,
3594 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
35ed2703
AG		 3595};
3596
bc50ca29
AD		 3597static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
3598{
3599 struct amdgpu_device *adev = to_amdgpu_device(control);
3600 int res;
3601
bc50ca29 3602 control->owner = THIS_MODULE;
f4322d80 3603 control->class = I2C_CLASS_HWMON;
bc50ca29
AD		 3604 control->dev.parent = &adev->pdev->dev;
3605 control->algo = &sienna_cichlid_i2c_algo;
3606 snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
35ed2703 3607 control->quirks = &sienna_cichlid_i2c_control_quirks;
bc50ca29
AD		 3608
3609 res = i2c_add_adapter(control);
3610 if (res)
3611 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3612
3613 return res;
3614}
3615
3616static void sienna_cichlid_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
3617{
bc50ca29
AD		 3618 i2c_del_adapter(control);
3619}
3620
8ca78a0a
EQ		 3621static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
3622 void **table)
3623{
3624 struct smu_table_context *smu_table = &smu->smu_table;
f06d9511
GS		 3625 struct gpu_metrics_v1_3 *gpu_metrics =
3626 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
b4b0b79d
EQ		 3627 SmuMetricsExternal_t metrics_external;
3628 SmuMetrics_t *metrics =
3629 &(metrics_external.SmuMetrics);
be22e2b9
EQ		 3630 SmuMetrics_V2_t *metrics_v2 =
3631 &(metrics_external.SmuMetrics_V2);
c524c1c9 3632 struct amdgpu_device *adev = smu->adev;
be22e2b9
EQ		 3633 bool use_metrics_v2 = ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
3634 (smu->smc_fw_version >= 0x3A4300)) ? true : false;
3635 uint16_t average_gfx_activity;
8ca78a0a
EQ		 3636 int ret = 0;
3637
be22e2b9
EQ		 3638 mutex_lock(&smu->metrics_lock);
3639 ret = smu_cmn_get_metrics_table_locked(smu,
3640 &metrics_external,
3641 true);
3642 if (ret) {
3643 mutex_unlock(&smu->metrics_lock);
8ca78a0a 3644 return ret;
be22e2b9 3645 }
8ca78a0a 3646
f06d9511 3647 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
8ca78a0a 3648
be22e2b9
EQ		 3649 gpu_metrics->temperature_edge =
3650 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge;
3651 gpu_metrics->temperature_hotspot =
3652 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot;
3653 gpu_metrics->temperature_mem =
3654 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem;
3655 gpu_metrics->temperature_vrgfx =
3656 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx;
3657 gpu_metrics->temperature_vrsoc =
3658 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc;
3659 gpu_metrics->temperature_vrmem =
3660 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0;
3661
3662 gpu_metrics->average_gfx_activity =
3663 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3664 gpu_metrics->average_umc_activity =
3665 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity;
3666 gpu_metrics->average_mm_activity =
3667 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage;
3668
3669 gpu_metrics->average_socket_power =
3670 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower;
3671 gpu_metrics->energy_accumulator =
3672 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator;
3673
3674 average_gfx_activity = use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3675 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
3676 gpu_metrics->average_gfxclk_frequency =
3677 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs : metrics->AverageGfxclkFrequencyPostDs;
8ca78a0a 3678 else
be22e2b9
EQ		 3679 gpu_metrics->average_gfxclk_frequency =
3680 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs : metrics->AverageGfxclkFrequencyPreDs;
3681 gpu_metrics->average_uclk_frequency =
3682 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs : metrics->AverageUclkFrequencyPostDs;
3683 gpu_metrics->average_vclk0_frequency =
3684 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency;
3685 gpu_metrics->average_dclk0_frequency =
3686 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency;
3687 gpu_metrics->average_vclk1_frequency =
3688 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency;
3689 gpu_metrics->average_dclk1_frequency =
3690 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency;
3691
3692 gpu_metrics->current_gfxclk =
3693 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK];
3694 gpu_metrics->current_socclk =
3695 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK];
3696 gpu_metrics->current_uclk =
3697 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK];
3698 gpu_metrics->current_vclk0 =
3699 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0];
3700 gpu_metrics->current_dclk0 =
3701 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0];
3702 gpu_metrics->current_vclk1 =
3703 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1];
3704 gpu_metrics->current_dclk1 =
3705 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1];
3706
3707 gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu);
f06d9511 3708 gpu_metrics->indep_throttle_status =
be22e2b9 3709 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
f06d9511 3710 sienna_cichlid_throttler_map);
b4b0b79d 3711
be22e2b9 3712 gpu_metrics->current_fan_speed = use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
c524c1c9 3713
be22e2b9
EQ		 3714 if (((adev->asic_type == CHIP_SIENNA_CICHLID) && smu->smc_fw_version > 0x003A1E00) ||
3715 ((adev->asic_type == CHIP_NAVY_FLOUNDER) && smu->smc_fw_version > 0x00410400)) {
3716 gpu_metrics->pcie_link_width = use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
3717 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
c524c1c9
EQ		 3718 } else {
3719 gpu_metrics->pcie_link_width =
3720 smu_v11_0_get_current_pcie_link_width(smu);
3721 gpu_metrics->pcie_link_speed =
3722 smu_v11_0_get_current_pcie_link_speed(smu);
3723 }
8ca78a0a 3724
be22e2b9
EQ		 3725 mutex_unlock(&smu->metrics_lock);
3726
de4b7cd8
KW		 3727 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3728
8ca78a0a
EQ		 3729 *table = (void *)gpu_metrics;
3730
f06d9511 3731 return sizeof(struct gpu_metrics_v1_3);
8ca78a0a 3732}
bc50ca29 3733
05f39286
EQ		 3734static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
3735{
b804a75d
EQ		 3736 struct smu_table_context *table_context = &smu->smu_table;
3737 PPTable_t *smc_pptable = table_context->driver_pptable;
3738
3739 /*
3740 * Skip the MGpuFanBoost setting for those ASICs
3741 * which do not support it
3742 */
3743 if (!smc_pptable->MGpuFanBoostLimitRpm)
3744 return 0;
3745
05f39286
EQ		 3746 return smu_cmn_send_smc_msg_with_param(smu,
3747 SMU_MSG_SetMGpuFanBoostLimitRpm,
3748 0,
3749 NULL);
3750}
3751
76c71f00
EQ		 3752static int sienna_cichlid_gpo_control(struct smu_context *smu,
3753 bool enablement)
3754{
ac7804bb 3755 uint32_t smu_version;
76c71f00
EQ		 3756 int ret = 0;
3757
ac7804bb 3758
76c71f00 3759 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
ac7804bb
EQ		 3760 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
3761 if (ret)
3762 return ret;
3763
3764 if (enablement) {
3765 if (smu_version < 0x003a2500) {
3766 ret = smu_cmn_send_smc_msg_with_param(smu,
3767 SMU_MSG_SetGpoFeaturePMask,
3768 GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
3769 NULL);
3770 } else {
3771 ret = smu_cmn_send_smc_msg_with_param(smu,
3772 SMU_MSG_DisallowGpo,
3773 0,
3774 NULL);
3775 }
3776 } else {
3777 if (smu_version < 0x003a2500) {
3778 ret = smu_cmn_send_smc_msg_with_param(smu,
3779 SMU_MSG_SetGpoFeaturePMask,
3780 0,
3781 NULL);
3782 } else {
3783 ret = smu_cmn_send_smc_msg_with_param(smu,
3784 SMU_MSG_DisallowGpo,
3785 1,
3786 NULL);
3787 }
3788 }
76c71f00
EQ		 3789 }
3790
3791 return ret;
3792}
d7f52e29
EQ		 3793
3794static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
3795{
3796 uint32_t smu_version;
3797 int ret = 0;
3798
3799 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
3800 if (ret)
3801 return ret;
3802
3803 /*
3804 * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
3805 * onwards PMFWs.
3806 */
3807 if (smu_version < 0x003A2D00)
3808 return 0;
3809
3810 return smu_cmn_send_smc_msg_with_param(smu,
3811 SMU_MSG_Enable2ndUSB20Port,
3812 smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
3813 1 : 0,
3814 NULL);
3815}
3816
3817static int sienna_cichlid_system_features_control(struct smu_context *smu,
3818 bool en)
3819{
3820 int ret = 0;
3821
3822 if (en) {
3823 ret = sienna_cichlid_notify_2nd_usb20_port(smu);
3824 if (ret)
3825 return ret;
3826 }
3827
3828 return smu_v11_0_system_features_control(smu, en);
3829}
3830
1689fca0
EQ		 3831static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
3832 enum pp_mp1_state mp1_state)
3833{
9113a0fb
GC		 3834 int ret;
3835
1689fca0
EQ		 3836 switch (mp1_state) {
3837 case PP_MP1_STATE_UNLOAD:
9113a0fb
GC		 3838 ret = smu_cmn_set_mp1_state(smu, mp1_state);
3839 break;
1689fca0 3840 default:
9113a0fb
GC		 3841 /* Ignore others */
3842 ret = 0;
1689fca0
EQ		 3843 }
3844
9113a0fb 3845 return ret;
1689fca0
EQ		 3846}
3847
b455159c 3848static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
b455159c
LG		 3849 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
3850 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
f6b4b4a1 3851 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
6fb176a7 3852 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
bc50ca29
AD		 3853 .i2c_init = sienna_cichlid_i2c_control_init,
3854 .i2c_fini = sienna_cichlid_i2c_control_fini,
b455159c
LG		 3855 .print_clk_levels = sienna_cichlid_print_clk_levels,
3856 .force_clk_levels = sienna_cichlid_force_clk_levels,
3857 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
b455159c
LG		 3858 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
3859 .display_config_changed = sienna_cichlid_display_config_changed,
3860 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
b455159c 3861 .is_dpm_running = sienna_cichlid_is_dpm_running,
4954a76a 3862 .get_fan_speed_percent = sienna_cichlid_get_fan_speed_percent,
b455159c
LG		 3863 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
3864 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
b455159c
LG		 3865 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
3866 .read_sensor = sienna_cichlid_read_sensor,
3867 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
b2785e25 3868 .set_performance_level = smu_v11_0_set_performance_level,
b455159c
LG		 3869 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
3870 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
3871 .get_power_limit = sienna_cichlid_get_power_limit,
08ccfe08 3872 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
b455159c
LG		 3873 .dump_pptable = sienna_cichlid_dump_pptable,
3874 .init_microcode = smu_v11_0_init_microcode,
3875 .load_microcode = smu_v11_0_load_microcode,
c1b353b7 3876 .init_smc_tables = sienna_cichlid_init_smc_tables,
b455159c
LG		 3877 .fini_smc_tables = smu_v11_0_fini_smc_tables,
3878 .init_power = smu_v11_0_init_power,
3879 .fini_power = smu_v11_0_fini_power,
3880 .check_fw_status = smu_v11_0_check_fw_status,
4a13b4ce 3881 .setup_pptable = sienna_cichlid_setup_pptable,
b455159c 3882 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
b455159c 3883 .check_fw_version = smu_v11_0_check_fw_version,
caad2613 3884 .write_pptable = smu_cmn_write_pptable,
b455159c
LG		 3885 .set_driver_table_location = smu_v11_0_set_driver_table_location,
3886 .set_tool_table_location = smu_v11_0_set_tool_table_location,
3887 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
d7f52e29 3888 .system_features_control = sienna_cichlid_system_features_control,
66c86828
EQ		 3889 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
3890 .send_smc_msg = smu_cmn_send_smc_msg,
31157341 3891 .init_display_count = NULL,
b455159c 3892 .set_allowed_mask = smu_v11_0_set_allowed_mask,
28251d72 3893 .get_enabled_mask = smu_cmn_get_enabled_mask,
b4bb3aaf 3894 .feature_is_enabled = smu_cmn_feature_is_enabled,
af5ba6d2 3895 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
31157341 3896 .notify_display_change = NULL,
b455159c 3897 .set_power_limit = smu_v11_0_set_power_limit,
b455159c
LG		 3898 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
3899 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
3900 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
ce63d8f8 3901 .set_min_dcef_deep_sleep = NULL,
b455159c
LG		 3902 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
3903 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
3904 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
cd305137 3905 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
b455159c
LG		 3906 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
3907 .gfx_off_control = smu_v11_0_gfx_off_control,
3908 .register_irq_handler = smu_v11_0_register_irq_handler,
3909 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
3910 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
9fd4781b 3911 .baco_is_support = smu_v11_0_baco_is_support,
b455159c
LG		 3912 .baco_get_state = smu_v11_0_baco_get_state,
3913 .baco_set_state = smu_v11_0_baco_set_state,
13d75ead
EQ		 3914 .baco_enter = sienna_cichlid_baco_enter,
3915 .baco_exit = sienna_cichlid_baco_exit,
ea8139d8
WS		 3916 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
3917 .mode1_reset = smu_v11_0_mode1_reset,
258d290c 3918 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
10e96d89 3919 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
aa75fa34 3920 .set_default_od_settings = sienna_cichlid_set_default_od_settings,
37a58f69 3921 .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
b521be9b 3922 .restore_user_od_settings = smu_v11_0_restore_user_od_settings,
66b8a9c0 3923 .run_btc = sienna_cichlid_run_btc,
18a4b3de 3924 .set_power_source = smu_v11_0_set_power_source,
7dbf7805
EQ		 3925 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3926 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
8ca78a0a 3927 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
05f39286 3928 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
e988026f 3929 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
5ce99853 3930 .deep_sleep_control = smu_v11_0_deep_sleep_control,
3204ff3e 3931 .get_fan_parameters = sienna_cichlid_get_fan_parameters,
234676d6 3932 .interrupt_work = smu_v11_0_interrupt_work,
76c71f00 3933 .gpo_control = sienna_cichlid_gpo_control,
1689fca0 3934 .set_mp1_state = sienna_cichlid_set_mp1_state,
b455159c
LG		 3935};
3936
3937void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
3938{
3939 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
6c339f37
EQ		 3940 smu->message_map = sienna_cichlid_message_map;
3941 smu->clock_map = sienna_cichlid_clk_map;
3942 smu->feature_map = sienna_cichlid_feature_mask_map;
3943 smu->table_map = sienna_cichlid_table_map;
3944 smu->pwr_src_map = sienna_cichlid_pwr_src_map;
3945 smu->workload_map = sienna_cichlid_workload_map;
b455159c 3946}
Linux 6.x block layer and io_uring tree(s)