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drm/amd/pm: Add navi1x throttler translation
[linux-block.git] / drivers / gpu / drm / amd / pm / swsmu / smu11 / sienna_cichlid_ppt.c
CommitLineData
b455159c
LG		 1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
d8e0b16d
EQ		 24#define SWSMU_CODE_LAYER_L2
25
b455159c
LG		 26#include <linux/firmware.h>
27#include <linux/pci.h>
bc50ca29 28#include <linux/i2c.h>
b455159c
LG		 29#include "amdgpu.h"
30#include "amdgpu_smu.h"
b455159c
LG		 31#include "atomfirmware.h"
32#include "amdgpu_atomfirmware.h"
22f2447c 33#include "amdgpu_atombios.h"
b455159c
LG		 34#include "smu_v11_0.h"
35#include "smu11_driver_if_sienna_cichlid.h"
36#include "soc15_common.h"
37#include "atom.h"
38#include "sienna_cichlid_ppt.h"
e05acd78 39#include "smu_v11_0_7_pptable.h"
b455159c 40#include "smu_v11_0_7_ppsmc.h"
40d3b8db 41#include "nbio/nbio_2_3_offset.h"
b7d25b5f 42#include "nbio/nbio_2_3_sh_mask.h"
e05acd78
LG		 43#include "thm/thm_11_0_2_offset.h"
44#include "thm/thm_11_0_2_sh_mask.h"
ea8139d8
WS		 45#include "mp/mp_11_0_offset.h"
46#include "mp/mp_11_0_sh_mask.h"
b455159c 47
6c339f37
EQ		 48#include "asic_reg/mp/mp_11_0_sh_mask.h"
49#include "smu_cmn.h"
50
55084d7f
EQ		 51/*
52 * DO NOT use these for err/warn/info/debug messages.
53 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
54 * They are more MGPU friendly.
55 */
56#undef pr_err
57#undef pr_warn
58#undef pr_info
59#undef pr_debug
60
bc50ca29
AD		 61#define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
62
b455159c
LG		 63#define FEATURE_MASK(feature) (1ULL << feature)
64#define SMC_DPM_FEATURE ( \
65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
fea905d4 66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65297d50 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
5cb74353 68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
4cd4f45b 69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
5f338f70 70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
ce7e5a6e
JC		 71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \
72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
b455159c 73
d817f375
LG		 74#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
75
7077b19a
CG		 76#define GET_PPTABLE_MEMBER(field, member) do {\
77 if (smu->adev->asic_type == CHIP_BEIGE_GOBY)\
78 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
79 else\
80 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
81} while(0)
82
83static int get_table_size(struct smu_context *smu)
84{
85 if (smu->adev->asic_type == CHIP_BEIGE_GOBY)
86 return sizeof(PPTable_beige_goby_t);
87 else
88 return sizeof(PPTable_t);
89}
90
6c339f37
EQ		 91static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
92 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
93 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
94 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
91190db1
LG		 95 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
96 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
97 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
98 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
6c339f37
EQ		 99 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
100 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
101 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
102 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
103 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
104 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
105 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
91190db1 106 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
4215a119
HC		 107 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
108 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
91190db1
LG		 109 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
110 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
4215a119 111 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
91190db1
LG		 112 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
113 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
66b8a9c0 114 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
91190db1 115 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
4215a119
HC		 116 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
117 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
6c339f37 118 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
91190db1 119 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
6c339f37
EQ		 120 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
121 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
122 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
91190db1
LG		 123 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
124 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
125 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
126 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
127 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
128 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
129 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
130 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
6c339f37 131 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
91190db1
LG		 132 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
133 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
134 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
6c339f37 135 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
91190db1
LG		 136 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
137 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
138 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
139 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
140 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
141 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
142 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
143 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
05f39286 144 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
76c71f00 145 MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0),
ac7804bb 146 MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0),
88dfd5d5 147 MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0),
b455159c
LG		 148};
149
6c339f37 150static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
b455159c
LG		 151 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
152 CLK_MAP(SCLK, PPCLK_GFXCLK),
153 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
154 CLK_MAP(FCLK, PPCLK_FCLK),
155 CLK_MAP(UCLK, PPCLK_UCLK),
156 CLK_MAP(MCLK, PPCLK_UCLK),
157 CLK_MAP(DCLK, PPCLK_DCLK_0),
9c0551f2
JC		 158 CLK_MAP(DCLK1, PPCLK_DCLK_1),
159 CLK_MAP(VCLK, PPCLK_VCLK_0),
b455159c
LG		 160 CLK_MAP(VCLK1, PPCLK_VCLK_1),
161 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
162 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
163 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
164 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
165};
166
6c339f37 167static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
b455159c
LG		 168 FEA_MAP(DPM_PREFETCHER),
169 FEA_MAP(DPM_GFXCLK),
31cb0dd9 170 FEA_MAP(DPM_GFX_GPO),
b455159c 171 FEA_MAP(DPM_UCLK),
e9073b43 172 FEA_MAP(DPM_FCLK),
b455159c
LG		 173 FEA_MAP(DPM_SOCCLK),
174 FEA_MAP(DPM_MP0CLK),
175 FEA_MAP(DPM_LINK),
176 FEA_MAP(DPM_DCEFCLK),
e9073b43 177 FEA_MAP(DPM_XGMI),
b455159c
LG		 178 FEA_MAP(MEM_VDDCI_SCALING),
179 FEA_MAP(MEM_MVDD_SCALING),
180 FEA_MAP(DS_GFXCLK),
181 FEA_MAP(DS_SOCCLK),
e9073b43 182 FEA_MAP(DS_FCLK),
b455159c
LG		 183 FEA_MAP(DS_LCLK),
184 FEA_MAP(DS_DCEFCLK),
185 FEA_MAP(DS_UCLK),
186 FEA_MAP(GFX_ULV),
187 FEA_MAP(FW_DSTATE),
188 FEA_MAP(GFXOFF),
189 FEA_MAP(BACO),
6fb176a7 190 FEA_MAP(MM_DPM_PG),
b455159c
LG		 191 FEA_MAP(RSMU_SMN_CG),
192 FEA_MAP(PPT),
193 FEA_MAP(TDC),
194 FEA_MAP(APCC_PLUS),
195 FEA_MAP(GTHR),
196 FEA_MAP(ACDC),
197 FEA_MAP(VR0HOT),
198 FEA_MAP(VR1HOT),
199 FEA_MAP(FW_CTF),
200 FEA_MAP(FAN_CONTROL),
201 FEA_MAP(THERMAL),
202 FEA_MAP(GFX_DCS),
203 FEA_MAP(RM),
204 FEA_MAP(LED_DISPLAY),
205 FEA_MAP(GFX_SS),
206 FEA_MAP(OUT_OF_BAND_MONITOR),
207 FEA_MAP(TEMP_DEPENDENT_VMIN),
208 FEA_MAP(MMHUB_PG),
209 FEA_MAP(ATHUB_PG),
cf06331f 210 FEA_MAP(APCC_DFLL),
b455159c
LG		 211};
212
6c339f37 213static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
b455159c
LG		 214 TAB_MAP(PPTABLE),
215 TAB_MAP(WATERMARKS),
216 TAB_MAP(AVFS_PSM_DEBUG),
217 TAB_MAP(AVFS_FUSE_OVERRIDE),
218 TAB_MAP(PMSTATUSLOG),
219 TAB_MAP(SMU_METRICS),
220 TAB_MAP(DRIVER_SMU_CONFIG),
221 TAB_MAP(ACTIVITY_MONITOR_COEFF),
222 TAB_MAP(OVERDRIVE),
223 TAB_MAP(I2C_COMMANDS),
224 TAB_MAP(PACE),
225};
226
6c339f37 227static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
1d5ca713
LG		 228 PWR_MAP(AC),
229 PWR_MAP(DC),
230};
231
6c339f37 232static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
b455159c
LG		 233 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
234 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
235 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
236 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
237 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
4c4d5a49 238 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
b455159c
LG		 239 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
240};
241
b455159c
LG		 242static int
243sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
244 uint32_t *feature_mask, uint32_t num)
245{
fea905d4
LG		 246 struct amdgpu_device *adev = smu->adev;
247
b455159c
LG		 248 if (num > 2)
249 return -EINVAL;
250
251 memset(feature_mask, 0, sizeof(uint32_t) * num);
252
4cd4f45b 253 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
15dbe18f 254 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
ce7e5a6e 255 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
094cdf15 256 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
5f338f70 257 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
86a9eb3f 258 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
80c36f86 259 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
9aa60213
LG		 260 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
261 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
d28f4aa1 262 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
20d71dcc 263 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
d0d71970 264 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
886c8bc6
LG		 265 | FEATURE_MASK(FEATURE_PPT_BIT)
266 | FEATURE_MASK(FEATURE_TDC_BIT)
3fc006f5 267 | FEATURE_MASK(FEATURE_BACO_BIT)
cf06331f 268 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
35ed946c 269 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
1c58d429 270 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
b971df70
LG		 271 | FEATURE_MASK(FEATURE_THERMAL_BIT)
272 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
fea905d4 273
c96721eb 274 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
fea905d4 275 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
c96721eb
KF		 276 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
277 }
fea905d4 278
680602d6
KF		 279 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
280 (adev->asic_type > CHIP_SIENNA_CICHLID) &&
281 !(adev->flags & AMD_IS_APU))
282 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
283
65297d50 284 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
fc17cd3f
LG		 285 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
286 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
287 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
65297d50 288
5cb74353
LG		 289 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
290 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
291
5f338f70
LG		 292 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
293 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
294
fea905d4
LG		 295 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
296 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
b455159c 297
62c1ea6b
LG		 298 if (adev->pm.pp_feature & PP_ULV_MASK)
299 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
300
02bb391d
LG		 301 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
302 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
303
e0da123a
LG		 304 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
305 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
306
b794616d
KF		 307 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
308 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
309
846938c2
KF		 310 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
312
6fb176a7
LG		 313 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
314 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
315 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
316
62826b86
KF		 317 if (smu->dc_controlled_by_gpio)
318 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
319
0064b0ce 320 if (amdgpu_aspm)
6ef28889
KF		 321 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
322
b455159c
LG		 323 return 0;
324}
325
458020dd 326static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
b455159c 327{
4a13b4ce 328 struct smu_table_context *table_context = &smu->smu_table;
e05acd78 329 struct smu_11_0_7_powerplay_table *powerplay_table =
4a13b4ce
EQ		 330 table_context->power_play_table;
331 struct smu_baco_context *smu_baco = &smu->smu_baco;
458020dd
LL		 332 struct amdgpu_device *adev = smu->adev;
333 uint32_t val;
334
335 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO ||
336 powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO) {
337 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
338 smu_baco->platform_support =
339 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
340 false;
341 }
342}
343
344static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
345{
346 struct smu_table_context *table_context = &smu->smu_table;
347 struct smu_11_0_7_powerplay_table *powerplay_table =
348 table_context->power_play_table;
4a13b4ce 349
18a4b3de
EQ		 350 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
351 smu->dc_controlled_by_gpio = true;
352
458020dd 353 sienna_cichlid_check_bxco_support(smu);
4a13b4ce
EQ		 354
355 table_context->thermal_controller_type =
356 powerplay_table->thermal_controller_type;
357
aa75fa34
EQ		 358 /*
359 * Instead of having its own buffer space and get overdrive_table copied,
360 * smu->od_settings just points to the actual overdrive_table
361 */
362 smu->od_settings = &powerplay_table->overdrive_table;
363
b455159c
LG		 364 return 0;
365}
366
367static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
368{
dccc7c21
LG		 369 struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
370 int index, ret;
7077b19a 371 I2cControllerConfig_t *table_member;
dccc7c21
LG		 372
373 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
374 smc_dpm_info);
375
22f2447c 376 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
dccc7c21
LG		 377 (uint8_t **)&smc_dpm_table);
378 if (ret)
379 return ret;
7077b19a
CG		 380 GET_PPTABLE_MEMBER(I2cControllers, &table_member);
381 memcpy(table_member, smc_dpm_table->I2cControllers,
382 sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
969c8d16 383
b455159c
LG		 384 return 0;
385}
386
387static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
388{
b455159c 389 struct smu_table_context *table_context = &smu->smu_table;
e05acd78 390 struct smu_11_0_7_powerplay_table *powerplay_table =
4a13b4ce 391 table_context->power_play_table;
7077b19a 392 int table_size;
b455159c 393
7077b19a 394 table_size = get_table_size(smu);
b455159c 395 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
7077b19a 396 table_size);
b455159c 397
4a13b4ce
EQ		 398 return 0;
399}
b455159c 400
4a13b4ce
EQ		 401static int sienna_cichlid_setup_pptable(struct smu_context *smu)
402{
403 int ret = 0;
b455159c 404
4a13b4ce
EQ		 405 ret = smu_v11_0_setup_pptable(smu);
406 if (ret)
407 return ret;
408
409 ret = sienna_cichlid_store_powerplay_table(smu);
410 if (ret)
411 return ret;
412
413 ret = sienna_cichlid_append_powerplay_table(smu);
414 if (ret)
415 return ret;
416
417 ret = sienna_cichlid_check_powerplay_table(smu);
418 if (ret)
419 return ret;
420
421 return ret;
b455159c
LG		 422}
423
c1b353b7 424static int sienna_cichlid_tables_init(struct smu_context *smu)
b455159c
LG		 425{
426 struct smu_table_context *smu_table = &smu->smu_table;
c1b353b7 427 struct smu_table *tables = smu_table->tables;
7077b19a 428 int table_size;
b455159c 429
7077b19a
CG		 430 table_size = get_table_size(smu);
431 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
432 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c
LG		 433 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
434 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b4b0b79d 435 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
b455159c 436 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
bc50ca29
AD		 437 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
438 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c
LG		 439 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
440 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
441 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
442 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
443 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
f9e3fe46 444 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
b455159c
LG		 445 AMDGPU_GEM_DOMAIN_VRAM);
446
b4b0b79d 447 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
b455159c 448 if (!smu_table->metrics_table)
8ca78a0a 449 goto err0_out;
b455159c
LG		 450 smu_table->metrics_time = 0;
451
152bb95c 452 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1);
8ca78a0a
EQ		 453 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
454 if (!smu_table->gpu_metrics_table)
455 goto err1_out;
456
40d3b8db
LG		 457 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
458 if (!smu_table->watermarks_table)
8ca78a0a 459 goto err2_out;
40d3b8db 460
b455159c 461 return 0;
8ca78a0a
EQ		 462
463err2_out:
464 kfree(smu_table->gpu_metrics_table);
465err1_out:
466 kfree(smu_table->metrics_table);
467err0_out:
468 return -ENOMEM;
b455159c
LG		 469}
470
60ae4d67
EQ		 471static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
472 MetricsMember_t member,
473 uint32_t *value)
474{
475 struct smu_table_context *smu_table= &smu->smu_table;
b4b0b79d
EQ		 476 SmuMetrics_t *metrics =
477 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
60ae4d67
EQ		 478 int ret = 0;
479
480 mutex_lock(&smu->metrics_lock);
481
fceafc9b
EQ		 482 ret = smu_cmn_get_metrics_table_locked(smu,
483 NULL,
484 false);
60ae4d67
EQ		 485 if (ret) {
486 mutex_unlock(&smu->metrics_lock);
487 return ret;
488 }
489
8c686254
EQ		 490 switch (member) {
491 case METRICS_CURR_GFXCLK:
492 *value = metrics->CurrClock[PPCLK_GFXCLK];
493 break;
494 case METRICS_CURR_SOCCLK:
495 *value = metrics->CurrClock[PPCLK_SOCCLK];
496 break;
497 case METRICS_CURR_UCLK:
498 *value = metrics->CurrClock[PPCLK_UCLK];
499 break;
500 case METRICS_CURR_VCLK:
501 *value = metrics->CurrClock[PPCLK_VCLK_0];
502 break;
503 case METRICS_CURR_VCLK1:
504 *value = metrics->CurrClock[PPCLK_VCLK_1];
505 break;
506 case METRICS_CURR_DCLK:
507 *value = metrics->CurrClock[PPCLK_DCLK_0];
508 break;
509 case METRICS_CURR_DCLK1:
510 *value = metrics->CurrClock[PPCLK_DCLK_1];
511 break;
9d09fa6f
ND		 512 case METRICS_CURR_DCEFCLK:
513 *value = metrics->CurrClock[PPCLK_DCEFCLK];
514 break;
4e2b3e23
KF		 515 case METRICS_CURR_FCLK:
516 *value = metrics->CurrClock[PPCLK_FCLK];
517 break;
8c686254 518 case METRICS_AVERAGE_GFXCLK:
d817f375
LG		 519 if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
520 *value = metrics->AverageGfxclkFrequencyPostDs;
521 else
522 *value = metrics->AverageGfxclkFrequencyPreDs;
8c686254
EQ		 523 break;
524 case METRICS_AVERAGE_FCLK:
d817f375 525 *value = metrics->AverageFclkFrequencyPostDs;
8c686254
EQ		 526 break;
527 case METRICS_AVERAGE_UCLK:
d817f375 528 *value = metrics->AverageUclkFrequencyPostDs;
8c686254
EQ		 529 break;
530 case METRICS_AVERAGE_GFXACTIVITY:
531 *value = metrics->AverageGfxActivity;
532 break;
533 case METRICS_AVERAGE_MEMACTIVITY:
534 *value = metrics->AverageUclkActivity;
535 break;
536 case METRICS_AVERAGE_SOCKETPOWER:
537 *value = metrics->AverageSocketPower << 8;
538 break;
539 case METRICS_TEMPERATURE_EDGE:
540 *value = metrics->TemperatureEdge *
541 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
542 break;
543 case METRICS_TEMPERATURE_HOTSPOT:
544 *value = metrics->TemperatureHotspot *
545 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
546 break;
547 case METRICS_TEMPERATURE_MEM:
548 *value = metrics->TemperatureMem *
549 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
550 break;
551 case METRICS_TEMPERATURE_VRGFX:
552 *value = metrics->TemperatureVrGfx *
553 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
554 break;
555 case METRICS_TEMPERATURE_VRSOC:
556 *value = metrics->TemperatureVrSoc *
557 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
558 break;
559 case METRICS_THROTTLER_STATUS:
560 *value = metrics->ThrottlerStatus;
561 break;
562 case METRICS_CURR_FANSPEED:
563 *value = metrics->CurrFanSpeed;
564 break;
565 default:
566 *value = UINT_MAX;
567 break;
568 }
569
b455159c
LG		 570 mutex_unlock(&smu->metrics_lock);
571
572 return ret;
8c686254 573
b455159c
LG		 574}
575
576static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
577{
578 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
579
b455159c
LG		 580 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
581 GFP_KERNEL);
582 if (!smu_dpm->dpm_context)
583 return -ENOMEM;
584
585 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
586
587 return 0;
588}
589
c1b353b7
EQ		 590static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
591{
592 int ret = 0;
593
594 ret = sienna_cichlid_tables_init(smu);
595 if (ret)
596 return ret;
597
598 ret = sienna_cichlid_allocate_dpm_context(smu);
599 if (ret)
600 return ret;
601
602 return smu_v11_0_init_smc_tables(smu);
603}
604
b455159c
LG		 605static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
606{
90a89c31 607 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
90a89c31 608 struct smu_11_0_dpm_table *dpm_table;
85dec717 609 struct amdgpu_device *adev = smu->adev;
90a89c31 610 int ret = 0;
7077b19a 611 DpmDescriptor_t *table_member;
b455159c 612
90a89c31
EQ		 613 /* socclk dpm table setup */
614 dpm_table = &dpm_context->dpm_tables.soc_table;
7077b19a 615 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
b4bb3aaf 616 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
90a89c31
EQ		 617 ret = smu_v11_0_set_single_dpm_table(smu,
618 SMU_SOCCLK,
619 dpm_table);
620 if (ret)
621 return ret;
622 dpm_table->is_fine_grained =
7077b19a 623 !table_member[PPCLK_SOCCLK].SnapToDiscrete;
90a89c31
EQ		 624 } else {
625 dpm_table->count = 1;
626 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
627 dpm_table->dpm_levels[0].enabled = true;
628 dpm_table->min = dpm_table->dpm_levels[0].value;
629 dpm_table->max = dpm_table->dpm_levels[0].value;
630 }
b455159c 631
90a89c31
EQ		 632 /* gfxclk dpm table setup */
633 dpm_table = &dpm_context->dpm_tables.gfx_table;
b4bb3aaf 634 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
90a89c31
EQ		 635 ret = smu_v11_0_set_single_dpm_table(smu,
636 SMU_GFXCLK,
637 dpm_table);
638 if (ret)
639 return ret;
640 dpm_table->is_fine_grained =
7077b19a 641 !table_member[PPCLK_GFXCLK].SnapToDiscrete;
90a89c31
EQ		 642 } else {
643 dpm_table->count = 1;
644 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
645 dpm_table->dpm_levels[0].enabled = true;
646 dpm_table->min = dpm_table->dpm_levels[0].value;
647 dpm_table->max = dpm_table->dpm_levels[0].value;
648 }
b455159c 649
90a89c31
EQ		 650 /* uclk dpm table setup */
651 dpm_table = &dpm_context->dpm_tables.uclk_table;
b4bb3aaf 652 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
90a89c31
EQ		 653 ret = smu_v11_0_set_single_dpm_table(smu,
654 SMU_UCLK,
655 dpm_table);
656 if (ret)
657 return ret;
658 dpm_table->is_fine_grained =
7077b19a 659 !table_member[PPCLK_UCLK].SnapToDiscrete;
90a89c31
EQ		 660 } else {
661 dpm_table->count = 1;
662 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
663 dpm_table->dpm_levels[0].enabled = true;
664 dpm_table->min = dpm_table->dpm_levels[0].value;
665 dpm_table->max = dpm_table->dpm_levels[0].value;
666 }
b455159c 667
90a89c31
EQ		 668 /* fclk dpm table setup */
669 dpm_table = &dpm_context->dpm_tables.fclk_table;
b4bb3aaf 670 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
90a89c31
EQ		 671 ret = smu_v11_0_set_single_dpm_table(smu,
672 SMU_FCLK,
673 dpm_table);
674 if (ret)
675 return ret;
676 dpm_table->is_fine_grained =
7077b19a 677 !table_member[PPCLK_FCLK].SnapToDiscrete;
90a89c31
EQ		 678 } else {
679 dpm_table->count = 1;
680 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
681 dpm_table->dpm_levels[0].enabled = true;
682 dpm_table->min = dpm_table->dpm_levels[0].value;
683 dpm_table->max = dpm_table->dpm_levels[0].value;
684 }
b455159c 685
90a89c31
EQ		 686 /* vclk0 dpm table setup */
687 dpm_table = &dpm_context->dpm_tables.vclk_table;
b4bb3aaf 688 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
90a89c31
EQ		 689 ret = smu_v11_0_set_single_dpm_table(smu,
690 SMU_VCLK,
691 dpm_table);
692 if (ret)
693 return ret;
694 dpm_table->is_fine_grained =
7077b19a 695 !table_member[PPCLK_VCLK_0].SnapToDiscrete;
90a89c31
EQ		 696 } else {
697 dpm_table->count = 1;
698 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
699 dpm_table->dpm_levels[0].enabled = true;
700 dpm_table->min = dpm_table->dpm_levels[0].value;
701 dpm_table->max = dpm_table->dpm_levels[0].value;
702 }
b455159c 703
90a89c31 704 /* vclk1 dpm table setup */
85dec717
JC		 705 if (adev->vcn.num_vcn_inst > 1) {
706 dpm_table = &dpm_context->dpm_tables.vclk1_table;
707 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
708 ret = smu_v11_0_set_single_dpm_table(smu,
709 SMU_VCLK1,
710 dpm_table);
711 if (ret)
712 return ret;
713 dpm_table->is_fine_grained =
7077b19a 714 !table_member[PPCLK_VCLK_1].SnapToDiscrete;
85dec717
JC		 715 } else {
716 dpm_table->count = 1;
717 dpm_table->dpm_levels[0].value =
718 smu->smu_table.boot_values.vclk / 100;
719 dpm_table->dpm_levels[0].enabled = true;
720 dpm_table->min = dpm_table->dpm_levels[0].value;
721 dpm_table->max = dpm_table->dpm_levels[0].value;
722 }
90a89c31 723 }
b455159c 724
90a89c31
EQ		 725 /* dclk0 dpm table setup */
726 dpm_table = &dpm_context->dpm_tables.dclk_table;
b4bb3aaf 727 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
90a89c31
EQ		 728 ret = smu_v11_0_set_single_dpm_table(smu,
729 SMU_DCLK,
730 dpm_table);
731 if (ret)
732 return ret;
733 dpm_table->is_fine_grained =
7077b19a 734 !table_member[PPCLK_DCLK_0].SnapToDiscrete;
90a89c31
EQ		 735 } else {
736 dpm_table->count = 1;
737 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
738 dpm_table->dpm_levels[0].enabled = true;
739 dpm_table->min = dpm_table->dpm_levels[0].value;
740 dpm_table->max = dpm_table->dpm_levels[0].value;
741 }
742
743 /* dclk1 dpm table setup */
85dec717
JC		 744 if (adev->vcn.num_vcn_inst > 1) {
745 dpm_table = &dpm_context->dpm_tables.dclk1_table;
746 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
747 ret = smu_v11_0_set_single_dpm_table(smu,
748 SMU_DCLK1,
749 dpm_table);
750 if (ret)
751 return ret;
752 dpm_table->is_fine_grained =
7077b19a 753 !table_member[PPCLK_DCLK_1].SnapToDiscrete;
85dec717
JC		 754 } else {
755 dpm_table->count = 1;
756 dpm_table->dpm_levels[0].value =
757 smu->smu_table.boot_values.dclk / 100;
758 dpm_table->dpm_levels[0].enabled = true;
759 dpm_table->min = dpm_table->dpm_levels[0].value;
760 dpm_table->max = dpm_table->dpm_levels[0].value;
761 }
90a89c31
EQ		 762 }
763
764 /* dcefclk dpm table setup */
765 dpm_table = &dpm_context->dpm_tables.dcef_table;
b4bb3aaf 766 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 767 ret = smu_v11_0_set_single_dpm_table(smu,
768 SMU_DCEFCLK,
769 dpm_table);
770 if (ret)
771 return ret;
772 dpm_table->is_fine_grained =
7077b19a 773 !table_member[PPCLK_DCEFCLK].SnapToDiscrete;
90a89c31
EQ		 774 } else {
775 dpm_table->count = 1;
776 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
777 dpm_table->dpm_levels[0].enabled = true;
778 dpm_table->min = dpm_table->dpm_levels[0].value;
779 dpm_table->max = dpm_table->dpm_levels[0].value;
780 }
b455159c 781
90a89c31
EQ		 782 /* pixelclk dpm table setup */
783 dpm_table = &dpm_context->dpm_tables.pixel_table;
b4bb3aaf 784 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 785 ret = smu_v11_0_set_single_dpm_table(smu,
786 SMU_PIXCLK,
787 dpm_table);
788 if (ret)
789 return ret;
790 dpm_table->is_fine_grained =
7077b19a 791 !table_member[PPCLK_PIXCLK].SnapToDiscrete;
90a89c31
EQ		 792 } else {
793 dpm_table->count = 1;
794 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
795 dpm_table->dpm_levels[0].enabled = true;
796 dpm_table->min = dpm_table->dpm_levels[0].value;
797 dpm_table->max = dpm_table->dpm_levels[0].value;
798 }
b455159c 799
90a89c31
EQ		 800 /* displayclk dpm table setup */
801 dpm_table = &dpm_context->dpm_tables.display_table;
b4bb3aaf 802 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 803 ret = smu_v11_0_set_single_dpm_table(smu,
804 SMU_DISPCLK,
805 dpm_table);
806 if (ret)
807 return ret;
808 dpm_table->is_fine_grained =
7077b19a 809 !table_member[PPCLK_DISPCLK].SnapToDiscrete;
90a89c31
EQ		 810 } else {
811 dpm_table->count = 1;
812 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
813 dpm_table->dpm_levels[0].enabled = true;
814 dpm_table->min = dpm_table->dpm_levels[0].value;
815 dpm_table->max = dpm_table->dpm_levels[0].value;
816 }
b455159c 817
90a89c31
EQ		 818 /* phyclk dpm table setup */
819 dpm_table = &dpm_context->dpm_tables.phy_table;
b4bb3aaf 820 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 821 ret = smu_v11_0_set_single_dpm_table(smu,
822 SMU_PHYCLK,
823 dpm_table);
824 if (ret)
825 return ret;
826 dpm_table->is_fine_grained =
7077b19a 827 !table_member[PPCLK_PHYCLK].SnapToDiscrete;
90a89c31
EQ		 828 } else {
829 dpm_table->count = 1;
830 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
831 dpm_table->dpm_levels[0].enabled = true;
832 dpm_table->min = dpm_table->dpm_levels[0].value;
833 dpm_table->max = dpm_table->dpm_levels[0].value;
834 }
b455159c
LG		 835
836 return 0;
837}
838
f6b4b4a1 839static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
b455159c 840{
d51dc613 841 struct amdgpu_device *adev = smu->adev;
b455159c
LG		 842 int ret = 0;
843
844 if (enable) {
845 /* vcn dpm on is a prerequisite for vcn power gate messages */
b4bb3aaf 846 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 847 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
6fb176a7
LG		 848 if (ret)
849 return ret;
6ec46653 850 if (adev->vcn.num_vcn_inst > 1) {
66c86828 851 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
d51dc613
JC		 852 0x10000, NULL);
853 if (ret)
854 return ret;
855 }
b455159c 856 }
b455159c 857 } else {
b4bb3aaf 858 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 859 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
6fb176a7
LG		 860 if (ret)
861 return ret;
6ec46653 862 if (adev->vcn.num_vcn_inst > 1) {
66c86828 863 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
d51dc613
JC		 864 0x10000, NULL);
865 if (ret)
866 return ret;
867 }
b455159c 868 }
b455159c
LG		 869 }
870
871 return ret;
872}
873
6fb176a7
LG		 874static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
875{
6fb176a7
LG		 876 int ret = 0;
877
878 if (enable) {
b4bb3aaf 879 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 880 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
6fb176a7
LG		 881 if (ret)
882 return ret;
6fb176a7 883 }
6fb176a7 884 } else {
b4bb3aaf 885 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 886 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
6fb176a7
LG		 887 if (ret)
888 return ret;
6fb176a7 889 }
6fb176a7
LG		 890 }
891
892 return ret;
893}
894
b455159c
LG		 895static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
896 enum smu_clk_type clk_type,
897 uint32_t *value)
898{
8c686254
EQ		 899 MetricsMember_t member_type;
900 int clk_id = 0;
b455159c 901
6c339f37
EQ		 902 clk_id = smu_cmn_to_asic_specific_index(smu,
903 CMN2ASIC_MAPPING_CLK,
904 clk_type);
b455159c
LG		 905 if (clk_id < 0)
906 return clk_id;
907
8c686254
EQ		 908 switch (clk_id) {
909 case PPCLK_GFXCLK:
910 member_type = METRICS_CURR_GFXCLK;
911 break;
912 case PPCLK_UCLK:
913 member_type = METRICS_CURR_UCLK;
914 break;
915 case PPCLK_SOCCLK:
916 member_type = METRICS_CURR_SOCCLK;
917 break;
918 case PPCLK_FCLK:
919 member_type = METRICS_CURR_FCLK;
920 break;
921 case PPCLK_VCLK_0:
922 member_type = METRICS_CURR_VCLK;
923 break;
924 case PPCLK_VCLK_1:
925 member_type = METRICS_CURR_VCLK1;
926 break;
927 case PPCLK_DCLK_0:
928 member_type = METRICS_CURR_DCLK;
929 break;
930 case PPCLK_DCLK_1:
931 member_type = METRICS_CURR_DCLK1;
932 break;
933 case PPCLK_DCEFCLK:
934 member_type = METRICS_CURR_DCEFCLK;
935 break;
936 default:
937 return -EINVAL;
938 }
939
940 return sienna_cichlid_get_smu_metrics_data(smu,
941 member_type,
942 value);
b455159c 943
b455159c
LG		 944}
945
946static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
947{
b455159c 948 DpmDescriptor_t *dpm_desc = NULL;
7077b19a 949 DpmDescriptor_t *table_member;
b455159c
LG		 950 uint32_t clk_index = 0;
951
7077b19a 952 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
6c339f37
EQ		 953 clk_index = smu_cmn_to_asic_specific_index(smu,
954 CMN2ASIC_MAPPING_CLK,
955 clk_type);
7077b19a 956 dpm_desc = &table_member[clk_index];
b455159c
LG		 957
958 /* 0 - Fine grained DPM, 1 - Discrete DPM */
0ee56acc 959 return dpm_desc->SnapToDiscrete == 0;
b455159c
LG		 960}
961
37a58f69
EQ		 962static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
963 enum SMU_11_0_7_ODFEATURE_CAP cap)
964{
965 return od_table->cap[cap];
966}
967
968static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
969 enum SMU_11_0_7_ODSETTING_ID setting,
970 uint32_t *min, uint32_t *max)
971{
972 if (min)
973 *min = od_table->min[setting];
974 if (max)
975 *max = od_table->max[setting];
976}
977
b455159c
LG		 978static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
979 enum smu_clk_type clk_type, char *buf)
980{
b7d25b5f
LG		 981 struct amdgpu_device *adev = smu->adev;
982 struct smu_table_context *table_context = &smu->smu_table;
983 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
984 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
7077b19a
CG		 985 uint16_t *table_member;
986
37a58f69
EQ		 987 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
988 OverDriveTable_t *od_table =
989 (OverDriveTable_t *)table_context->overdrive_table;
b455159c
LG		 990 int i, size = 0, ret = 0;
991 uint32_t cur_value = 0, value = 0, count = 0;
992 uint32_t freq_values[3] = {0};
993 uint32_t mark_index = 0;
b7d25b5f 994 uint32_t gen_speed, lane_width;
37a58f69 995 uint32_t min_value, max_value;
a2b6df4f 996 uint32_t smu_version;
b455159c
LG		 997
998 switch (clk_type) {
999 case SMU_GFXCLK:
1000 case SMU_SCLK:
1001 case SMU_SOCCLK:
1002 case SMU_MCLK:
1003 case SMU_UCLK:
1004 case SMU_FCLK:
78842457
DN		 1005 case SMU_VCLK:
1006 case SMU_VCLK1:
1007 case SMU_DCLK:
1008 case SMU_DCLK1:
b455159c 1009 case SMU_DCEFCLK:
5e6dc8fe 1010 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
b455159c 1011 if (ret)
258d290c 1012 goto print_clk_out;
b455159c 1013
ba818620
KF		 1014 /* no need to disable gfxoff when retrieving the current gfxclk */
1015 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1016 amdgpu_gfx_off_ctrl(adev, false);
1017
d8d3493a 1018 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
b455159c 1019 if (ret)
258d290c 1020 goto print_clk_out;
b455159c
LG		 1021
1022 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1023 for (i = 0; i < count; i++) {
d8d3493a 1024 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
b455159c 1025 if (ret)
258d290c 1026 goto print_clk_out;
b455159c
LG		 1027
1028 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
1029 cur_value == value ? "*" : "");
1030 }
1031 } else {
d8d3493a 1032 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
b455159c 1033 if (ret)
258d290c 1034 goto print_clk_out;
d8d3493a 1035 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
b455159c 1036 if (ret)
258d290c 1037 goto print_clk_out;
b455159c
LG		 1038
1039 freq_values[1] = cur_value;
1040 mark_index = cur_value == freq_values[0] ? 0 :
1041 cur_value == freq_values[2] ? 2 : 1;
b455159c 1042
891bacb8
KF		 1043 count = 3;
1044 if (mark_index != 1) {
1045 count = 2;
1046 freq_values[1] = freq_values[2];
1047 }
1048
1049 for (i = 0; i < count; i++) {
b455159c 1050 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
891bacb8 1051 cur_value == freq_values[i] ? "*" : "");
b455159c
LG		 1052 }
1053
1054 }
1055 break;
b7d25b5f 1056 case SMU_PCIE:
f20c52f4
LG		 1057 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1058 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
7077b19a 1059 GET_PPTABLE_MEMBER(LclkFreq, &table_member);
b7d25b5f
LG		 1060 for (i = 0; i < NUM_LINK_LEVELS; i++)
1061 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
1062 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1063 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1064 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1065 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1066 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1067 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1068 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1069 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1070 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1071 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
7077b19a 1072 table_member[i],
b7d25b5f
LG		 1073 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1074 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1075 "*" : "");
1076 break;
37a58f69
EQ		 1077 case SMU_OD_SCLK:
1078 if (!smu->od_enabled || !od_table || !od_settings)
1079 break;
1080
1081 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1082 break;
1083
1084 size += sprintf(buf + size, "OD_SCLK:\n");
1085 size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1086 break;
1087
1088 case SMU_OD_MCLK:
1089 if (!smu->od_enabled || !od_table || !od_settings)
1090 break;
1091
1092 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1093 break;
1094
1095 size += sprintf(buf + size, "OD_MCLK:\n");
1096 size += sprintf(buf + size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
1097 break;
1098
a2b6df4f
EQ		 1099 case SMU_OD_VDDGFX_OFFSET:
1100 if (!smu->od_enabled || !od_table || !od_settings)
1101 break;
1102
1103 /*
1104 * OD GFX Voltage Offset functionality is supported only by 58.41.0
1105 * and onwards SMU firmwares.
1106 */
1107 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1108 if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1109 (smu_version < 0x003a2900))
1110 break;
1111
1112 size += sprintf(buf + size, "OD_VDDGFX_OFFSET:\n");
1113 size += sprintf(buf + size, "%dmV\n", od_table->VddGfxOffset);
1114 break;
1115
37a58f69
EQ		 1116 case SMU_OD_RANGE:
1117 if (!smu->od_enabled || !od_table || !od_settings)
1118 break;
1119
1120 size = sprintf(buf, "%s:\n", "OD_RANGE");
1121
1122 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1123 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1124 &min_value, NULL);
1125 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1126 NULL, &max_value);
1127 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
1128 min_value, max_value);
1129 }
1130
1131 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1132 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1133 &min_value, NULL);
1134 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1135 NULL, &max_value);
1136 size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
1137 min_value, max_value);
1138 }
1139 break;
1140
b455159c
LG		 1141 default:
1142 break;
1143 }
1144
258d290c
LG		 1145print_clk_out:
1146 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1147 amdgpu_gfx_off_ctrl(adev, true);
1148
b455159c
LG		 1149 return size;
1150}
1151
1152static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1153 enum smu_clk_type clk_type, uint32_t mask)
1154{
258d290c 1155 struct amdgpu_device *adev = smu->adev;
b455159c
LG		 1156 int ret = 0, size = 0;
1157 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1158
1159 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1160 soft_max_level = mask ? (fls(mask) - 1) : 0;
1161
258d290c
LG		 1162 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1163 amdgpu_gfx_off_ctrl(adev, false);
1164
b455159c
LG		 1165 switch (clk_type) {
1166 case SMU_GFXCLK:
1167 case SMU_SCLK:
1168 case SMU_SOCCLK:
1169 case SMU_MCLK:
1170 case SMU_UCLK:
b455159c 1171 case SMU_FCLK:
9ad9c8ac
LG		 1172 /* There is only 2 levels for fine grained DPM */
1173 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1174 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1175 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1176 }
1177
d8d3493a 1178 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
b455159c 1179 if (ret)
258d290c 1180 goto forec_level_out;
b455159c 1181
d8d3493a 1182 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
b455159c 1183 if (ret)
258d290c 1184 goto forec_level_out;
b455159c 1185
10e96d89 1186 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
b455159c 1187 if (ret)
258d290c 1188 goto forec_level_out;
b455159c 1189 break;
51ec6992
DP		 1190 case SMU_DCEFCLK:
1191 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1192 break;
b455159c
LG		 1193 default:
1194 break;
1195 }
1196
258d290c
LG		 1197forec_level_out:
1198 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1199 amdgpu_gfx_off_ctrl(adev, true);
1200
b455159c
LG		 1201 return size;
1202}
1203
1204static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1205{
62cc9dd1
EQ		 1206 struct smu_11_0_dpm_context *dpm_context =
1207 smu->smu_dpm.dpm_context;
1208 struct smu_11_0_dpm_table *gfx_table =
1209 &dpm_context->dpm_tables.gfx_table;
1210 struct smu_11_0_dpm_table *mem_table =
1211 &dpm_context->dpm_tables.uclk_table;
1212 struct smu_11_0_dpm_table *soc_table =
1213 &dpm_context->dpm_tables.soc_table;
1214 struct smu_umd_pstate_table *pstate_table =
1215 &smu->pstate_table;
1216
1217 pstate_table->gfxclk_pstate.min = gfx_table->min;
1218 pstate_table->gfxclk_pstate.peak = gfx_table->max;
0dc994fb
EQ		 1219 if (gfx_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK)
1220 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
62cc9dd1
EQ		 1221
1222 pstate_table->uclk_pstate.min = mem_table->min;
1223 pstate_table->uclk_pstate.peak = mem_table->max;
0dc994fb
EQ		 1224 if (mem_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK)
1225 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
62cc9dd1
EQ		 1226
1227 pstate_table->socclk_pstate.min = soc_table->min;
1228 pstate_table->socclk_pstate.peak = soc_table->max;
0dc994fb
EQ		 1229 if (soc_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK)
1230 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
b455159c 1231
62cc9dd1 1232 return 0;
b455159c
LG		 1233}
1234
b455159c
LG		 1235static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1236{
1237 int ret = 0;
1238 uint32_t max_freq = 0;
1239
1240 /* Sienna_Cichlid do not support to change display num currently */
1241 return 0;
1242#if 0
66c86828 1243 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
b455159c
LG		 1244 if (ret)
1245 return ret;
1246#endif
1247
b4bb3aaf 1248 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
e5ef784b 1249 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
b455159c
LG		 1250 if (ret)
1251 return ret;
661b94f5 1252 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
b455159c
LG		 1253 if (ret)
1254 return ret;
1255 }
1256
1257 return ret;
1258}
1259
1260static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1261{
1262 int ret = 0;
1263
b455159c 1264 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
4d942ae3
EQ		 1265 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1266 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
b455159c 1267#if 0
66c86828 1268 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
40d3b8db
LG		 1269 smu->display_config->num_display,
1270 NULL);
b455159c
LG		 1271#endif
1272 if (ret)
1273 return ret;
1274 }
1275
1276 return ret;
1277}
1278
b455159c
LG		 1279static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1280{
1281 int ret = 0;
1282 uint32_t feature_mask[2];
3d14a79b
KW		 1283 uint64_t feature_enabled;
1284
28251d72 1285 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
3d14a79b
KW		 1286 if (ret)
1287 return false;
1288
1289 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1290
b455159c
LG		 1291 return !!(feature_enabled & SMC_DPM_FEATURE);
1292}
1293
4954a76a
AD		 1294static int sienna_cichlid_get_fan_speed_percent(struct smu_context *smu,
1295 uint32_t *speed)
b455159c 1296{
4954a76a
AD		 1297 int ret;
1298 u32 rpm;
1299
b455159c
LG		 1300 if (!speed)
1301 return -EINVAL;
1302
4954a76a
AD		 1303 switch (smu_v11_0_get_fan_control_mode(smu)) {
1304 case AMD_FAN_CTRL_AUTO:
1305 ret = sienna_cichlid_get_smu_metrics_data(smu,
1306 METRICS_CURR_FANSPEED,
1307 &rpm);
1308 if (!ret && smu->fan_max_rpm)
1309 *speed = rpm * 100 / smu->fan_max_rpm;
1310 return ret;
1311 default:
1312 *speed = smu->user_dpm_profile.fan_speed_percent;
1313 return 0;
1314 }
b455159c
LG		 1315}
1316
3204ff3e
AD		 1317static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1318{
7077b19a 1319 uint16_t *table_member;
3204ff3e 1320
7077b19a
CG		 1321 GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
1322 smu->fan_max_rpm = *table_member;
3204ff3e
AD		 1323
1324 return 0;
1325}
1326
b455159c
LG		 1327static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1328{
f9e3fe46
EQ		 1329 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1330 DpmActivityMonitorCoeffInt_t *activity_monitor =
1331 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
b455159c
LG		 1332 uint32_t i, size = 0;
1333 int16_t workload_type = 0;
1334 static const char *profile_name[] = {
1335 "BOOTUP_DEFAULT",
1336 "3D_FULL_SCREEN",
1337 "POWER_SAVING",
1338 "VIDEO",
1339 "VR",
1340 "COMPUTE",
1341 "CUSTOM"};
1342 static const char *title[] = {
1343 "PROFILE_INDEX(NAME)",
1344 "CLOCK_TYPE(NAME)",
1345 "FPS",
1346 "MinFreqType",
1347 "MinActiveFreqType",
1348 "MinActiveFreq",
1349 "BoosterFreqType",
1350 "BoosterFreq",
1351 "PD_Data_limit_c",
1352 "PD_Data_error_coeff",
1353 "PD_Data_error_rate_coeff"};
1354 int result = 0;
1355
1356 if (!buf)
1357 return -EINVAL;
1358
1359 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1360 title[0], title[1], title[2], title[3], title[4], title[5],
1361 title[6], title[7], title[8], title[9], title[10]);
1362
1363 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1364 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
6c339f37
EQ		 1365 workload_type = smu_cmn_to_asic_specific_index(smu,
1366 CMN2ASIC_MAPPING_WORKLOAD,
1367 i);
b455159c
LG		 1368 if (workload_type < 0)
1369 return -EINVAL;
1370
caad2613 1371 result = smu_cmn_update_table(smu,
b455159c 1372 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
f9e3fe46 1373 (void *)(&activity_monitor_external), false);
b455159c 1374 if (result) {
d9811cfc 1375 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
b455159c
LG		 1376 return result;
1377 }
1378
1379 size += sprintf(buf + size, "%2d %14s%s:\n",
1380 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1381
1382 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1383 " ",
1384 0,
1385 "GFXCLK",
f9e3fe46
EQ		 1386 activity_monitor->Gfx_FPS,
1387 activity_monitor->Gfx_MinFreqStep,
1388 activity_monitor->Gfx_MinActiveFreqType,
1389 activity_monitor->Gfx_MinActiveFreq,
1390 activity_monitor->Gfx_BoosterFreqType,
1391 activity_monitor->Gfx_BoosterFreq,
1392 activity_monitor->Gfx_PD_Data_limit_c,
1393 activity_monitor->Gfx_PD_Data_error_coeff,
1394 activity_monitor->Gfx_PD_Data_error_rate_coeff);
b455159c
LG		 1395
1396 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1397 " ",
1398 1,
1399 "SOCCLK",
f9e3fe46
EQ		 1400 activity_monitor->Fclk_FPS,
1401 activity_monitor->Fclk_MinFreqStep,
1402 activity_monitor->Fclk_MinActiveFreqType,
1403 activity_monitor->Fclk_MinActiveFreq,
1404 activity_monitor->Fclk_BoosterFreqType,
1405 activity_monitor->Fclk_BoosterFreq,
1406 activity_monitor->Fclk_PD_Data_limit_c,
1407 activity_monitor->Fclk_PD_Data_error_coeff,
1408 activity_monitor->Fclk_PD_Data_error_rate_coeff);
b455159c
LG		 1409
1410 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1411 " ",
1412 2,
1413 "MEMLK",
f9e3fe46
EQ		 1414 activity_monitor->Mem_FPS,
1415 activity_monitor->Mem_MinFreqStep,
1416 activity_monitor->Mem_MinActiveFreqType,
1417 activity_monitor->Mem_MinActiveFreq,
1418 activity_monitor->Mem_BoosterFreqType,
1419 activity_monitor->Mem_BoosterFreq,
1420 activity_monitor->Mem_PD_Data_limit_c,
1421 activity_monitor->Mem_PD_Data_error_coeff,
1422 activity_monitor->Mem_PD_Data_error_rate_coeff);
b455159c
LG		 1423 }
1424
1425 return size;
1426}
1427
1428static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1429{
f9e3fe46
EQ		 1430
1431 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1432 DpmActivityMonitorCoeffInt_t *activity_monitor =
1433 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
b455159c
LG		 1434 int workload_type, ret = 0;
1435
1436 smu->power_profile_mode = input[size];
1437
1438 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
d9811cfc 1439 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
b455159c
LG		 1440 return -EINVAL;
1441 }
1442
1443 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
b455159c 1444
caad2613 1445 ret = smu_cmn_update_table(smu,
b455159c 1446 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
f9e3fe46 1447 (void *)(&activity_monitor_external), false);
b455159c 1448 if (ret) {
d9811cfc 1449 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
b455159c
LG		 1450 return ret;
1451 }
1452
1453 switch (input[0]) {
1454 case 0: /* Gfxclk */
f9e3fe46
EQ		 1455 activity_monitor->Gfx_FPS = input[1];
1456 activity_monitor->Gfx_MinFreqStep = input[2];
1457 activity_monitor->Gfx_MinActiveFreqType = input[3];
1458 activity_monitor->Gfx_MinActiveFreq = input[4];
1459 activity_monitor->Gfx_BoosterFreqType = input[5];
1460 activity_monitor->Gfx_BoosterFreq = input[6];
1461 activity_monitor->Gfx_PD_Data_limit_c = input[7];
1462 activity_monitor->Gfx_PD_Data_error_coeff = input[8];
1463 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1464 break;
1465 case 1: /* Socclk */
f9e3fe46
EQ		 1466 activity_monitor->Fclk_FPS = input[1];
1467 activity_monitor->Fclk_MinFreqStep = input[2];
1468 activity_monitor->Fclk_MinActiveFreqType = input[3];
1469 activity_monitor->Fclk_MinActiveFreq = input[4];
1470 activity_monitor->Fclk_BoosterFreqType = input[5];
1471 activity_monitor->Fclk_BoosterFreq = input[6];
1472 activity_monitor->Fclk_PD_Data_limit_c = input[7];
1473 activity_monitor->Fclk_PD_Data_error_coeff = input[8];
1474 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1475 break;
1476 case 2: /* Memlk */
f9e3fe46
EQ		 1477 activity_monitor->Mem_FPS = input[1];
1478 activity_monitor->Mem_MinFreqStep = input[2];
1479 activity_monitor->Mem_MinActiveFreqType = input[3];
1480 activity_monitor->Mem_MinActiveFreq = input[4];
1481 activity_monitor->Mem_BoosterFreqType = input[5];
1482 activity_monitor->Mem_BoosterFreq = input[6];
1483 activity_monitor->Mem_PD_Data_limit_c = input[7];
1484 activity_monitor->Mem_PD_Data_error_coeff = input[8];
1485 activity_monitor->Mem_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1486 break;
1487 }
1488
caad2613 1489 ret = smu_cmn_update_table(smu,
b455159c 1490 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
f9e3fe46 1491 (void *)(&activity_monitor_external), true);
b455159c 1492 if (ret) {
d9811cfc 1493 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
b455159c
LG		 1494 return ret;
1495 }
1496 }
1497
1498 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
6c339f37
EQ		 1499 workload_type = smu_cmn_to_asic_specific_index(smu,
1500 CMN2ASIC_MAPPING_WORKLOAD,
1501 smu->power_profile_mode);
b455159c
LG		 1502 if (workload_type < 0)
1503 return -EINVAL;
66c86828 1504 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
b455159c
LG		 1505 1 << workload_type, NULL);
1506
1507 return ret;
1508}
1509
b455159c
LG		 1510static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1511{
1512 struct smu_clocks min_clocks = {0};
1513 struct pp_display_clock_request clock_req;
1514 int ret = 0;
1515
1516 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1517 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1518 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1519
4d942ae3 1520 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
b455159c
LG		 1521 clock_req.clock_type = amd_pp_dcef_clock;
1522 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1523
1524 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1525 if (!ret) {
4d942ae3 1526 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
66c86828 1527 ret = smu_cmn_send_smc_msg_with_param(smu,
40d3b8db
LG		 1528 SMU_MSG_SetMinDeepSleepDcefclk,
1529 min_clocks.dcef_clock_in_sr/100,
1530 NULL);
1531 if (ret) {
d9811cfc 1532 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
40d3b8db
LG		 1533 return ret;
1534 }
b455159c
LG		 1535 }
1536 } else {
d9811cfc 1537 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
b455159c
LG		 1538 }
1539 }
1540
b4bb3aaf 1541 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
661b94f5 1542 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
b455159c 1543 if (ret) {
d9811cfc 1544 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
b455159c
LG		 1545 return ret;
1546 }
1547 }
1548
1549 return 0;
1550}
1551
1552static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
7b9c7e30 1553 struct pp_smu_wm_range_sets *clock_ranges)
b455159c 1554{
e7a95eea 1555 Watermarks_t *table = smu->smu_table.watermarks_table;
40d3b8db 1556 int ret = 0;
e7a95eea 1557 int i;
b455159c 1558
e7a95eea 1559 if (clock_ranges) {
7b9c7e30
EQ		 1560 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1561 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
e7a95eea
EQ		 1562 return -EINVAL;
1563
7b9c7e30
EQ		 1564 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1565 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1566 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1567 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1568 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1569 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1570 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1571 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1572 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1573
1574 table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1575 clock_ranges->reader_wm_sets[i].wm_inst;
e7a95eea 1576 }
b455159c 1577
7b9c7e30
EQ		 1578 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1579 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1580 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1581 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1582 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1583 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1584 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1585 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1586 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1587
1588 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1589 clock_ranges->writer_wm_sets[i].wm_inst;
e7a95eea
EQ		 1590 }
1591
1592 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1593 }
1594
1595 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1596 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
caad2613 1597 ret = smu_cmn_write_watermarks_table(smu);
40d3b8db 1598 if (ret) {
d9811cfc 1599 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
40d3b8db
LG		 1600 return ret;
1601 }
1602 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1603 }
1604
b455159c
LG		 1605 return 0;
1606}
1607
b455159c
LG		 1608static int sienna_cichlid_read_sensor(struct smu_context *smu,
1609 enum amd_pp_sensors sensor,
1610 void *data, uint32_t *size)
1611{
1612 int ret = 0;
7077b19a 1613 uint16_t *temp;
b455159c
LG		 1614
1615 if(!data || !size)
1616 return -EINVAL;
1617
1618 mutex_lock(&smu->sensor_lock);
1619 switch (sensor) {
1620 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
7077b19a
CG		 1621 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
1622 *(uint16_t *)data = *temp;
b455159c
LG		 1623 *size = 4;
1624 break;
1625 case AMDGPU_PP_SENSOR_MEM_LOAD:
60e317a2
AD		 1626 ret = sienna_cichlid_get_smu_metrics_data(smu,
1627 METRICS_AVERAGE_MEMACTIVITY,
1628 (uint32_t *)data);
1629 *size = 4;
1630 break;
b455159c 1631 case AMDGPU_PP_SENSOR_GPU_LOAD:
60e317a2
AD		 1632 ret = sienna_cichlid_get_smu_metrics_data(smu,
1633 METRICS_AVERAGE_GFXACTIVITY,
1634 (uint32_t *)data);
b455159c
LG		 1635 *size = 4;
1636 break;
1637 case AMDGPU_PP_SENSOR_GPU_POWER:
60e317a2
AD		 1638 ret = sienna_cichlid_get_smu_metrics_data(smu,
1639 METRICS_AVERAGE_SOCKETPOWER,
1640 (uint32_t *)data);
b455159c
LG		 1641 *size = 4;
1642 break;
1643 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
60e317a2
AD		 1644 ret = sienna_cichlid_get_smu_metrics_data(smu,
1645 METRICS_TEMPERATURE_HOTSPOT,
1646 (uint32_t *)data);
1647 *size = 4;
1648 break;
b455159c 1649 case AMDGPU_PP_SENSOR_EDGE_TEMP:
60e317a2
AD		 1650 ret = sienna_cichlid_get_smu_metrics_data(smu,
1651 METRICS_TEMPERATURE_EDGE,
1652 (uint32_t *)data);
1653 *size = 4;
1654 break;
b455159c 1655 case AMDGPU_PP_SENSOR_MEM_TEMP:
60e317a2
AD		 1656 ret = sienna_cichlid_get_smu_metrics_data(smu,
1657 METRICS_TEMPERATURE_MEM,
1658 (uint32_t *)data);
b455159c
LG		 1659 *size = 4;
1660 break;
e0f9e936
EQ		 1661 case AMDGPU_PP_SENSOR_GFX_MCLK:
1662 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1663 *(uint32_t *)data *= 100;
1664 *size = 4;
1665 break;
1666 case AMDGPU_PP_SENSOR_GFX_SCLK:
1667 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1668 *(uint32_t *)data *= 100;
1669 *size = 4;
1670 break;
b2febc99
EQ		 1671 case AMDGPU_PP_SENSOR_VDDGFX:
1672 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1673 *size = 4;
1674 break;
b455159c 1675 default:
b2febc99
EQ		 1676 ret = -EOPNOTSUPP;
1677 break;
b455159c
LG		 1678 }
1679 mutex_unlock(&smu->sensor_lock);
1680
1681 return ret;
1682}
1683
1684static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1685{
1686 uint32_t num_discrete_levels = 0;
1687 uint16_t *dpm_levels = NULL;
1688 uint16_t i = 0;
1689 struct smu_table_context *table_context = &smu->smu_table;
7077b19a
CG		 1690 DpmDescriptor_t *table_member1;
1691 uint16_t *table_member2;
b455159c
LG		 1692
1693 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1694 return -EINVAL;
1695
7077b19a
CG		 1696 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
1697 num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
1698 GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
1699 dpm_levels = table_member2;
b455159c
LG		 1700
1701 if (num_discrete_levels == 0 || dpm_levels == NULL)
1702 return -EINVAL;
1703
1704 *num_states = num_discrete_levels;
1705 for (i = 0; i < num_discrete_levels; i++) {
1706 /* convert to khz */
1707 *clocks_in_khz = (*dpm_levels) * 1000;
1708 clocks_in_khz++;
1709 dpm_levels++;
1710 }
1711
1712 return 0;
1713}
1714
1715static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1716 struct smu_temperature_range *range)
1717{
e02e4d51
EQ		 1718 struct smu_table_context *table_context = &smu->smu_table;
1719 struct smu_11_0_7_powerplay_table *powerplay_table =
1720 table_context->power_play_table;
7077b19a
CG		 1721 uint16_t *table_member;
1722 uint16_t temp_edge, temp_hotspot, temp_mem;
b455159c 1723
2b1f12a2 1724 if (!range)
b455159c
LG		 1725 return -EINVAL;
1726
0540eced
EQ		 1727 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1728
7077b19a
CG		 1729 GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
1730 temp_edge = table_member[TEMP_EDGE];
1731 temp_hotspot = table_member[TEMP_HOTSPOT];
1732 temp_mem = table_member[TEMP_MEM];
1733
1734 range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1735 range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
2b1f12a2 1736 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a
CG		 1737 range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1738 range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
2b1f12a2 1739 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a
CG		 1740 range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1741 range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
b455159c 1742 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a 1743
e02e4d51 1744 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
b455159c
LG		 1745
1746 return 0;
1747}
1748
1749static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1750 bool disable_memory_clock_switch)
1751{
1752 int ret = 0;
1753 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1754 (struct smu_11_0_max_sustainable_clocks *)
1755 smu->smu_table.max_sustainable_clocks;
1756 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1757 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1758
1759 if(smu->disable_uclk_switch == disable_memory_clock_switch)
1760 return 0;
1761
1762 if(disable_memory_clock_switch)
661b94f5 1763 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
b455159c 1764 else
661b94f5 1765 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
b455159c
LG		 1766
1767 if(!ret)
1768 smu->disable_uclk_switch = disable_memory_clock_switch;
1769
1770 return ret;
1771}
1772
a141b4e3 1773static int sienna_cichlid_get_power_limit(struct smu_context *smu)
b455159c 1774{
1e239fdd
EQ		 1775 struct smu_11_0_7_powerplay_table *powerplay_table =
1776 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
1e239fdd 1777 uint32_t power_limit, od_percent;
7077b19a
CG		 1778 uint16_t *table_member;
1779
1780 GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
1e239fdd
EQ		 1781
1782 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1e239fdd 1783 power_limit =
7077b19a 1784 table_member[PPT_THROTTLER_PPT0];
1e239fdd 1785 }
6e58941c 1786 smu->current_power_limit = smu->default_power_limit = power_limit;
b455159c 1787
1e239fdd
EQ		 1788 if (smu->od_enabled) {
1789 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
1790
1791 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1792
1793 power_limit *= (100 + od_percent);
1794 power_limit /= 100;
b455159c 1795 }
1e239fdd 1796 smu->max_power_limit = power_limit;
b455159c 1797
b455159c
LG		 1798 return 0;
1799}
1800
08ccfe08
LG		 1801static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1802 uint32_t pcie_gen_cap,
1803 uint32_t pcie_width_cap)
1804{
0b590970 1805 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
7077b19a 1806
08ccfe08 1807 uint32_t smu_pcie_arg;
7077b19a 1808 uint8_t *table_member1, *table_member2;
0b590970 1809 int ret, i;
08ccfe08 1810
7077b19a
CG		 1811 GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
1812 GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
1813
0b590970
EQ		 1814 /* lclk dpm table setup */
1815 for (i = 0; i < MAX_PCIE_CONF; i++) {
7077b19a
CG		 1816 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = table_member1[i];
1817 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = table_member2[i];
0b590970 1818 }
08ccfe08
LG		 1819
1820 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1821 smu_pcie_arg = (i << 16) |
7077b19a
CG		 1822 ((table_member1[i] <= pcie_gen_cap) ?
1823 (table_member1[i] << 8) :
1824 (pcie_gen_cap << 8)) |
1825 ((table_member2[i] <= pcie_width_cap) ?
1826 table_member2[i] :
1827 pcie_width_cap);
08ccfe08 1828
66c86828 1829 ret = smu_cmn_send_smc_msg_with_param(smu,
7077b19a
CG		 1830 SMU_MSG_OverridePcieParameters,
1831 smu_pcie_arg,
1832 NULL);
08ccfe08
LG		 1833 if (ret)
1834 return ret;
1835
7077b19a 1836 if (table_member1[i] > pcie_gen_cap)
08ccfe08 1837 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
7077b19a 1838 if (table_member2[i] > pcie_width_cap)
08ccfe08
LG		 1839 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1840 }
1841
1842 return 0;
1843}
1844
38ed7b09 1845static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
258d290c
LG		 1846 enum smu_clk_type clk_type,
1847 uint32_t *min, uint32_t *max)
1848{
1849 struct amdgpu_device *adev = smu->adev;
1850 int ret;
1851
1852 if (clk_type == SMU_GFXCLK)
1853 amdgpu_gfx_off_ctrl(adev, false);
1854 ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
1855 if (clk_type == SMU_GFXCLK)
1856 amdgpu_gfx_off_ctrl(adev, true);
1857
1858 return ret;
1859}
1860
aa75fa34
EQ		 1861static void sienna_cichlid_dump_od_table(struct smu_context *smu,
1862 OverDriveTable_t *od_table)
1863{
a2b6df4f
EQ		 1864 struct amdgpu_device *adev = smu->adev;
1865 uint32_t smu_version;
1866
aa75fa34
EQ		 1867 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
1868 od_table->GfxclkFmax);
1869 dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
1870 od_table->UclkFmax);
a2b6df4f
EQ		 1871
1872 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1873 if (!((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1874 (smu_version < 0x003a2900)))
1875 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
aa75fa34
EQ		 1876}
1877
1878static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
1879{
1880 OverDriveTable_t *od_table =
1881 (OverDriveTable_t *)smu->smu_table.overdrive_table;
1882 OverDriveTable_t *boot_od_table =
1883 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
1884 int ret = 0;
1885
1886 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
1887 0, (void *)od_table, false);
1888 if (ret) {
1889 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
1890 return ret;
1891 }
1892
1893 memcpy(boot_od_table, od_table, sizeof(OverDriveTable_t));
1894
1895 sienna_cichlid_dump_od_table(smu, od_table);
1896
1897 return 0;
1898}
1899
37a58f69
EQ		 1900static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
1901 struct smu_11_0_7_overdrive_table *od_table,
1902 enum SMU_11_0_7_ODSETTING_ID setting,
1903 uint32_t value)
1904{
1905 if (value < od_table->min[setting]) {
1906 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
1907 setting, value, od_table->min[setting]);
1908 return -EINVAL;
1909 }
1910 if (value > od_table->max[setting]) {
1911 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
1912 setting, value, od_table->max[setting]);
1913 return -EINVAL;
1914 }
1915
1916 return 0;
1917}
1918
1919static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
1920 enum PP_OD_DPM_TABLE_COMMAND type,
1921 long input[], uint32_t size)
1922{
1923 struct smu_table_context *table_context = &smu->smu_table;
1924 OverDriveTable_t *od_table =
1925 (OverDriveTable_t *)table_context->overdrive_table;
1926 struct smu_11_0_7_overdrive_table *od_settings =
1927 (struct smu_11_0_7_overdrive_table *)smu->od_settings;
a2b6df4f 1928 struct amdgpu_device *adev = smu->adev;
37a58f69
EQ		 1929 enum SMU_11_0_7_ODSETTING_ID freq_setting;
1930 uint16_t *freq_ptr;
1931 int i, ret = 0;
a2b6df4f 1932 uint32_t smu_version;
37a58f69
EQ		 1933
1934 if (!smu->od_enabled) {
1935 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
1936 return -EINVAL;
1937 }
1938
1939 if (!smu->od_settings) {
1940 dev_err(smu->adev->dev, "OD board limits are not set!\n");
1941 return -ENOENT;
1942 }
1943
1944 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
1945 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
1946 return -EINVAL;
1947 }
1948
1949 switch (type) {
1950 case PP_OD_EDIT_SCLK_VDDC_TABLE:
1951 if (!sienna_cichlid_is_od_feature_supported(od_settings,
1952 SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1953 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
1954 return -ENOTSUPP;
1955 }
1956
1957 for (i = 0; i < size; i += 2) {
1958 if (i + 2 > size) {
1959 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
1960 return -EINVAL;
1961 }
1962
1963 switch (input[i]) {
1964 case 0:
1965 if (input[i + 1] > od_table->GfxclkFmax) {
1966 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
1967 input[i + 1], od_table->GfxclkFmax);
1968 return -EINVAL;
1969 }
1970
1971 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
1972 freq_ptr = &od_table->GfxclkFmin;
1973 break;
1974
1975 case 1:
1976 if (input[i + 1] < od_table->GfxclkFmin) {
1977 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
1978 input[i + 1], od_table->GfxclkFmin);
1979 return -EINVAL;
1980 }
1981
1982 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
1983 freq_ptr = &od_table->GfxclkFmax;
1984 break;
1985
1986 default:
1987 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
1988 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
1989 return -EINVAL;
1990 }
1991
1992 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
1993 freq_setting, input[i + 1]);
1994 if (ret)
1995 return ret;
1996
1997 *freq_ptr = (uint16_t)input[i + 1];
1998 }
1999 break;
2000
2001 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2002 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
2003 dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2004 return -ENOTSUPP;
2005 }
2006
2007 for (i = 0; i < size; i += 2) {
2008 if (i + 2 > size) {
2009 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2010 return -EINVAL;
2011 }
2012
2013 switch (input[i]) {
2014 case 0:
2015 if (input[i + 1] > od_table->UclkFmax) {
2016 dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2017 input[i + 1], od_table->UclkFmax);
2018 return -EINVAL;
2019 }
2020
2021 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
2022 freq_ptr = &od_table->UclkFmin;
2023 break;
2024
2025 case 1:
2026 if (input[i + 1] < od_table->UclkFmin) {
2027 dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2028 input[i + 1], od_table->UclkFmin);
2029 return -EINVAL;
2030 }
2031
2032 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
2033 freq_ptr = &od_table->UclkFmax;
2034 break;
2035
2036 default:
2037 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2038 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2039 return -EINVAL;
2040 }
2041
2042 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2043 freq_setting, input[i + 1]);
2044 if (ret)
2045 return ret;
2046
2047 *freq_ptr = (uint16_t)input[i + 1];
2048 }
2049 break;
2050
2051 case PP_OD_RESTORE_DEFAULT_TABLE:
2052 memcpy(table_context->overdrive_table,
2053 table_context->boot_overdrive_table,
2054 sizeof(OverDriveTable_t));
2055 fallthrough;
2056
2057 case PP_OD_COMMIT_DPM_TABLE:
2058 sienna_cichlid_dump_od_table(smu, od_table);
2059
2060 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
2061 0, (void *)od_table, true);
2062 if (ret) {
2063 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2064 return ret;
2065 }
2066 break;
2067
a2b6df4f
EQ		 2068 case PP_OD_EDIT_VDDGFX_OFFSET:
2069 if (size != 1) {
2070 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2071 return -EINVAL;
2072 }
2073
2074 /*
2075 * OD GFX Voltage Offset functionality is supported only by 58.41.0
2076 * and onwards SMU firmwares.
2077 */
2078 smu_cmn_get_smc_version(smu, NULL, &smu_version);
2079 if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
2080 (smu_version < 0x003a2900)) {
2081 dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2082 "only by 58.41.0 and onwards SMU firmwares!\n");
2083 return -EOPNOTSUPP;
2084 }
2085
2086 od_table->VddGfxOffset = (int16_t)input[0];
2087
2088 sienna_cichlid_dump_od_table(smu, od_table);
2089 break;
2090
37a58f69
EQ		 2091 default:
2092 return -ENOSYS;
2093 }
2094
2095 return ret;
2096}
2097
66b8a9c0
JC		 2098static int sienna_cichlid_run_btc(struct smu_context *smu)
2099{
2100 return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2101}
2102
ea8139d8
WS		 2103static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2104{
2105 struct amdgpu_device *adev = smu->adev;
2106 uint32_t val;
2107 u32 smu_version;
2108
2109 /**
2110 * SRIOV env will not support SMU mode1 reset
2111 * PM FW support mode1 reset from 58.26
2112 */
a7bae061 2113 smu_cmn_get_smc_version(smu, NULL, &smu_version);
ea8139d8
WS		 2114 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
2115 return false;
2116
2117 /**
2118 * mode1 reset relies on PSP, so we should check if
2119 * PSP is alive.
2120 */
2121 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2122 return val != 0x0;
2123}
2124
7077b19a
CG		 2125static void beige_goby_dump_pptable(struct smu_context *smu)
2126{
2127 struct smu_table_context *table_context = &smu->smu_table;
2128 PPTable_beige_goby_t *pptable = table_context->driver_pptable;
2129 int i;
2130
2131 dev_info(smu->adev->dev, "Dumped PPTable:\n");
2132
2133 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2134 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2135 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2136
2137 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2138 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2139 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2140 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2141 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2142 }
2143
2144 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2145 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2146 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2147 }
2148
2149 for (i = 0; i < TEMP_COUNT; i++) {
2150 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2151 }
2152
2153 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2154 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2155 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2156 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2157 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2158
2159 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2160 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2161 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2162 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2163 }
2164 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2165
2166 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2167
2168 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2169 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2170 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2171 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2172
2173 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2174
2175 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2176
2177 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2178 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2179 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2180 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2181
2182 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2183 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2184
2185 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2186 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2187 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2188 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2189 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2190 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2191 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2192 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2193
2194 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2195 " .VoltageMode = 0x%02x\n"
2196 " .SnapToDiscrete = 0x%02x\n"
2197 " .NumDiscreteLevels = 0x%02x\n"
2198 " .padding = 0x%02x\n"
2199 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2200 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2201 " .SsFmin = 0x%04x\n"
2202 " .Padding_16 = 0x%04x\n",
2203 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2204 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2205 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2206 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2207 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2208 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2209 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2210 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2211 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2212 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2213 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2214
2215 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2216 " .VoltageMode = 0x%02x\n"
2217 " .SnapToDiscrete = 0x%02x\n"
2218 " .NumDiscreteLevels = 0x%02x\n"
2219 " .padding = 0x%02x\n"
2220 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2221 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2222 " .SsFmin = 0x%04x\n"
2223 " .Padding_16 = 0x%04x\n",
2224 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2225 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2226 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2227 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2228 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2229 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2230 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2231 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2232 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2233 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2234 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2235
2236 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2237 " .VoltageMode = 0x%02x\n"
2238 " .SnapToDiscrete = 0x%02x\n"
2239 " .NumDiscreteLevels = 0x%02x\n"
2240 " .padding = 0x%02x\n"
2241 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2242 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2243 " .SsFmin = 0x%04x\n"
2244 " .Padding_16 = 0x%04x\n",
2245 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2246 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2247 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2248 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2249 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2250 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2251 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2252 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2253 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2254 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2255 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2256
2257 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2258 " .VoltageMode = 0x%02x\n"
2259 " .SnapToDiscrete = 0x%02x\n"
2260 " .NumDiscreteLevels = 0x%02x\n"
2261 " .padding = 0x%02x\n"
2262 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2263 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2264 " .SsFmin = 0x%04x\n"
2265 " .Padding_16 = 0x%04x\n",
2266 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2267 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2268 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2269 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2270 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2271 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2272 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2273 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2274 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2275 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2276 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2277
2278 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2279 " .VoltageMode = 0x%02x\n"
2280 " .SnapToDiscrete = 0x%02x\n"
2281 " .NumDiscreteLevels = 0x%02x\n"
2282 " .padding = 0x%02x\n"
2283 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2284 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2285 " .SsFmin = 0x%04x\n"
2286 " .Padding_16 = 0x%04x\n",
2287 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2288 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2289 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2290 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2291 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2292 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2293 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2294 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2295 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2296 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2297 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2298
2299 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2300 " .VoltageMode = 0x%02x\n"
2301 " .SnapToDiscrete = 0x%02x\n"
2302 " .NumDiscreteLevels = 0x%02x\n"
2303 " .padding = 0x%02x\n"
2304 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2305 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2306 " .SsFmin = 0x%04x\n"
2307 " .Padding_16 = 0x%04x\n",
2308 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2309 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2310 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2311 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2312 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2313 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2314 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2315 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2316 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2317 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2318 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2319
2320 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2321 " .VoltageMode = 0x%02x\n"
2322 " .SnapToDiscrete = 0x%02x\n"
2323 " .NumDiscreteLevels = 0x%02x\n"
2324 " .padding = 0x%02x\n"
2325 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2326 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2327 " .SsFmin = 0x%04x\n"
2328 " .Padding_16 = 0x%04x\n",
2329 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2330 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2331 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2332 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2333 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2334 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2335 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2336 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2337 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2338 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2339 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2340
2341 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2342 " .VoltageMode = 0x%02x\n"
2343 " .SnapToDiscrete = 0x%02x\n"
2344 " .NumDiscreteLevels = 0x%02x\n"
2345 " .padding = 0x%02x\n"
2346 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2347 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2348 " .SsFmin = 0x%04x\n"
2349 " .Padding_16 = 0x%04x\n",
2350 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2351 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2352 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2353 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2354 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2355 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2356 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2357 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2358 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2359 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2360 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2361
2362 dev_info(smu->adev->dev, "FreqTableGfx\n");
2363 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2364 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2365
2366 dev_info(smu->adev->dev, "FreqTableVclk\n");
2367 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2368 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2369
2370 dev_info(smu->adev->dev, "FreqTableDclk\n");
2371 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2372 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2373
2374 dev_info(smu->adev->dev, "FreqTableSocclk\n");
2375 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2376 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2377
2378 dev_info(smu->adev->dev, "FreqTableUclk\n");
2379 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2380 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2381
2382 dev_info(smu->adev->dev, "FreqTableFclk\n");
2383 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2384 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2385
2386 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2387 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2388 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2389 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2390 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2391 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2392 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2393 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2394 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2395
2396 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2397 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2398 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2399
2400 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2401 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2402
2403 dev_info(smu->adev->dev, "Mp0clkFreq\n");
2404 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2405 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2406
2407 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2408 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2409 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2410
2411 dev_info(smu->adev->dev, "MemVddciVoltage\n");
2412 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2413 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2414
2415 dev_info(smu->adev->dev, "MemMvddVoltage\n");
2416 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2417 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2418
2419 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2420 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2421 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2422 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2423 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2424
2425 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2426
2427 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2428 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2429 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2430 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2431 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2432 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2433 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2434 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2435 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2436 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2437 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2438
2439 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2440 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2441 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2442 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2443 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2444 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2445
2446 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2447 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2448 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2449 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2450 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2451
2452 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2453 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2454 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2455
2456 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2457 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2458 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2459 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2460
2461 dev_info(smu->adev->dev, "UclkDpmPstates\n");
2462 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2463 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2464
2465 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2466 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2467 pptable->UclkDpmSrcFreqRange.Fmin);
2468 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2469 pptable->UclkDpmSrcFreqRange.Fmax);
2470 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2471 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2472 pptable->UclkDpmTargFreqRange.Fmin);
2473 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2474 pptable->UclkDpmTargFreqRange.Fmax);
2475 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2476 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2477
2478 dev_info(smu->adev->dev, "PcieGenSpeed\n");
2479 for (i = 0; i < NUM_LINK_LEVELS; i++)
2480 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2481
2482 dev_info(smu->adev->dev, "PcieLaneCount\n");
2483 for (i = 0; i < NUM_LINK_LEVELS; i++)
2484 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2485
2486 dev_info(smu->adev->dev, "LclkFreq\n");
2487 for (i = 0; i < NUM_LINK_LEVELS; i++)
2488 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2489
2490 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2491 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2492
2493 dev_info(smu->adev->dev, "FanGain\n");
2494 for (i = 0; i < TEMP_COUNT; i++)
2495 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2496
2497 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2498 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2499 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2500 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2501 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2502 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2503 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2504 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2505 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2506 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2507 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2508 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2509
2510 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2511 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2512 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2513 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2514
2515 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2516 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2517 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2518 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2519
2520 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2521 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2522 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2523 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2524 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2525 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2526 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2527 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2528 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2529 pptable->dBtcGbGfxPll.a,
2530 pptable->dBtcGbGfxPll.b,
2531 pptable->dBtcGbGfxPll.c);
2532 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2533 pptable->dBtcGbGfxDfll.a,
2534 pptable->dBtcGbGfxDfll.b,
2535 pptable->dBtcGbGfxDfll.c);
2536 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2537 pptable->dBtcGbSoc.a,
2538 pptable->dBtcGbSoc.b,
2539 pptable->dBtcGbSoc.c);
2540 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2541 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2542 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2543 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2544 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2545 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2546
2547 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2548 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2549 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
2550 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2551 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
2552 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2553 }
2554
2555 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2556 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2557 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2558 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2559 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2560 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2561 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2562 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2563
2564 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2565 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2566
2567 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2568 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2569 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2570 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2571
2572 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2573 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2574 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2575 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2576
2577 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2578 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2579
2580 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2581 for (i = 0; i < NUM_XGMI_LEVELS; i++)
2582 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2583 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2584 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2585
2586 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2587 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2588 pptable->ReservedEquation0.a,
2589 pptable->ReservedEquation0.b,
2590 pptable->ReservedEquation0.c);
2591 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2592 pptable->ReservedEquation1.a,
2593 pptable->ReservedEquation1.b,
2594 pptable->ReservedEquation1.c);
2595 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2596 pptable->ReservedEquation2.a,
2597 pptable->ReservedEquation2.b,
2598 pptable->ReservedEquation2.c);
2599 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2600 pptable->ReservedEquation3.a,
2601 pptable->ReservedEquation3.b,
2602 pptable->ReservedEquation3.c);
2603
2604 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2605 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2606 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2607 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2608 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2609 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2610 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2611 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2612
2613 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2614 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2615 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2616 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2617 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2618 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2619
2620 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2621 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2622 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
2623 pptable->I2cControllers[i].Enabled);
2624 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
2625 pptable->I2cControllers[i].Speed);
2626 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
2627 pptable->I2cControllers[i].SlaveAddress);
2628 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
2629 pptable->I2cControllers[i].ControllerPort);
2630 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
2631 pptable->I2cControllers[i].ControllerName);
2632 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
2633 pptable->I2cControllers[i].ThermalThrotter);
2634 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
2635 pptable->I2cControllers[i].I2cProtocol);
2636 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
2637 pptable->I2cControllers[i].PaddingConfig);
2638 }
2639
2640 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2641 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2642 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2643 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2644
2645 dev_info(smu->adev->dev, "Board Parameters:\n");
2646 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2647 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2648 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2649 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2650 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2651 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2652 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2653 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2654
2655 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2656 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2657 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2658
2659 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2660 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2661 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2662
2663 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2664 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2665 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2666
2667 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2668 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2669 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2670
2671 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2672
2673 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2674 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2675 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2676 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2677 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2678 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2679 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2680 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2681 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2682 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2683 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2684 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2685 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2686 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2687 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2688 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2689
2690 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2691 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2692 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
2693
2694 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2695 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2696 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
2697
2698 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
2699 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2700
2701 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2702 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2703 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2704
2705 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2706 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2707 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2708 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2709 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2710
2711 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2712 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2713
2714 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
2715 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2716 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2717 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
2718 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2719 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2720 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
2721 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2722 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2723 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
2724 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2725 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2726
2727 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2728 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2729 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2730 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2731
2732 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2733 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2734 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2735 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2736 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2737 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2738 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2739 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2740 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2741 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2742 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2743
2744 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2745 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2746 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2747 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2748 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2749 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2750 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2751 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2752}
2753
b455159c
LG		 2754static void sienna_cichlid_dump_pptable(struct smu_context *smu)
2755{
2756 struct smu_table_context *table_context = &smu->smu_table;
2757 PPTable_t *pptable = table_context->driver_pptable;
2758 int i;
2759
7077b19a
CG		 2760 if (smu->adev->asic_type == CHIP_BEIGE_GOBY) {
2761 beige_goby_dump_pptable(smu);
2762 return;
2763 }
2764
d9811cfc 2765 dev_info(smu->adev->dev, "Dumped PPTable:\n");
b455159c 2766
d9811cfc
EQ		 2767 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2768 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2769 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
b455159c
LG		 2770
2771 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
d9811cfc
EQ		 2772 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2773 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2774 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2775 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
b455159c
LG		 2776 }
2777
2778 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
d9811cfc
EQ		 2779 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2780 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
b455159c
LG		 2781 }
2782
2783 for (i = 0; i < TEMP_COUNT; i++) {
d9811cfc 2784 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
b455159c
LG		 2785 }
2786
d9811cfc
EQ		 2787 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2788 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2789 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2790 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2791 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
b455159c 2792
d9811cfc 2793 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
b455159c 2794 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
d9811cfc
EQ		 2795 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2796 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
b455159c 2797 }
d9811cfc
EQ		 2798 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2799
2800 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2801
2802 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2803 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2804 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2805 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2806
2807 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2808 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
2809
2810 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2811 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
2812 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
2813 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
2814
2815 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2816 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2817 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2818 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2819
2820 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2821 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2822
2823 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2824 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2825 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2826 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2827 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2828 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2829 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2830 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2831
2832 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
b455159c
LG		 2833 " .VoltageMode = 0x%02x\n"
2834 " .SnapToDiscrete = 0x%02x\n"
2835 " .NumDiscreteLevels = 0x%02x\n"
2836 " .padding = 0x%02x\n"
2837 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2838 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2839 " .SsFmin = 0x%04x\n"
2840 " .Padding_16 = 0x%04x\n",
2841 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2842 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2843 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2844 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2845 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2846 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2847 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2848 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2849 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2850 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2851 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2852
d9811cfc 2853 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
b455159c
LG		 2854 " .VoltageMode = 0x%02x\n"
2855 " .SnapToDiscrete = 0x%02x\n"
2856 " .NumDiscreteLevels = 0x%02x\n"
2857 " .padding = 0x%02x\n"
2858 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2859 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2860 " .SsFmin = 0x%04x\n"
2861 " .Padding_16 = 0x%04x\n",
2862 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2863 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2864 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2865 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2866 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2867 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2868 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2869 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2870 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2871 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2872 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2873
d9811cfc 2874 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
b455159c
LG		 2875 " .VoltageMode = 0x%02x\n"
2876 " .SnapToDiscrete = 0x%02x\n"
2877 " .NumDiscreteLevels = 0x%02x\n"
2878 " .padding = 0x%02x\n"
2879 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2880 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2881 " .SsFmin = 0x%04x\n"
2882 " .Padding_16 = 0x%04x\n",
2883 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2884 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2885 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2886 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2887 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2888 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2889 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2890 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2891 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2892 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2893 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2894
d9811cfc 2895 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
b455159c
LG		 2896 " .VoltageMode = 0x%02x\n"
2897 " .SnapToDiscrete = 0x%02x\n"
2898 " .NumDiscreteLevels = 0x%02x\n"
2899 " .padding = 0x%02x\n"
2900 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2901 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2902 " .SsFmin = 0x%04x\n"
2903 " .Padding_16 = 0x%04x\n",
2904 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2905 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2906 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2907 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2908 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2909 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2910 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2911 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2912 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2913 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2914 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2915
d9811cfc 2916 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
b455159c
LG		 2917 " .VoltageMode = 0x%02x\n"
2918 " .SnapToDiscrete = 0x%02x\n"
2919 " .NumDiscreteLevels = 0x%02x\n"
2920 " .padding = 0x%02x\n"
2921 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2922 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2923 " .SsFmin = 0x%04x\n"
2924 " .Padding_16 = 0x%04x\n",
2925 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2926 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2927 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2928 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2929 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2930 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2931 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2932 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2933 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2934 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2935 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2936
d9811cfc 2937 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
b455159c
LG		 2938 " .VoltageMode = 0x%02x\n"
2939 " .SnapToDiscrete = 0x%02x\n"
2940 " .NumDiscreteLevels = 0x%02x\n"
2941 " .padding = 0x%02x\n"
2942 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2943 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2944 " .SsFmin = 0x%04x\n"
2945 " .Padding_16 = 0x%04x\n",
2946 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2947 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2948 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2949 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2950 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2951 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2952 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2953 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2954 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2955 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2956 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2957
d9811cfc 2958 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
b455159c
LG		 2959 " .VoltageMode = 0x%02x\n"
2960 " .SnapToDiscrete = 0x%02x\n"
2961 " .NumDiscreteLevels = 0x%02x\n"
2962 " .padding = 0x%02x\n"
2963 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2964 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2965 " .SsFmin = 0x%04x\n"
2966 " .Padding_16 = 0x%04x\n",
2967 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2968 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2969 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2970 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2971 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2972 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2973 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2974 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2975 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2976 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2977 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2978
d9811cfc 2979 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
b455159c
LG		 2980 " .VoltageMode = 0x%02x\n"
2981 " .SnapToDiscrete = 0x%02x\n"
2982 " .NumDiscreteLevels = 0x%02x\n"
2983 " .padding = 0x%02x\n"
2984 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2985 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2986 " .SsFmin = 0x%04x\n"
2987 " .Padding_16 = 0x%04x\n",
2988 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2989 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2990 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2991 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2992 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2993 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2994 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2995 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2996 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2997 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2998 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2999
d9811cfc 3000 dev_info(smu->adev->dev, "FreqTableGfx\n");
b455159c 3001 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
d9811cfc 3002 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
b455159c 3003
d9811cfc 3004 dev_info(smu->adev->dev, "FreqTableVclk\n");
b455159c 3005 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
d9811cfc 3006 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
b455159c 3007
d9811cfc 3008 dev_info(smu->adev->dev, "FreqTableDclk\n");
b455159c 3009 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
d9811cfc 3010 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
b455159c 3011
d9811cfc 3012 dev_info(smu->adev->dev, "FreqTableSocclk\n");
b455159c 3013 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
d9811cfc 3014 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
b455159c 3015
d9811cfc 3016 dev_info(smu->adev->dev, "FreqTableUclk\n");
b455159c 3017 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3018 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
b455159c 3019
d9811cfc 3020 dev_info(smu->adev->dev, "FreqTableFclk\n");
b455159c 3021 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
d9811cfc
EQ		 3022 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
3023
d9811cfc
EQ		 3024 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
3025 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
3026 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
3027 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
3028 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
3029 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
3030 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
3031 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
3032 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
3033
3034 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
b455159c 3035 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3036 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
b455159c 3037
d9811cfc
EQ		 3038 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
3039 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
b455159c 3040
d9811cfc 3041 dev_info(smu->adev->dev, "Mp0clkFreq\n");
b455159c 3042 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc 3043 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
b455159c 3044
d9811cfc 3045 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
b455159c 3046 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc 3047 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
b455159c 3048
d9811cfc 3049 dev_info(smu->adev->dev, "MemVddciVoltage\n");
b455159c 3050 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3051 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
b455159c 3052
d9811cfc 3053 dev_info(smu->adev->dev, "MemMvddVoltage\n");
b455159c 3054 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc
EQ		 3055 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
3056
3057 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
3058 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
3059 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
3060 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
3061 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
3062
3063 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
3064
3065 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
3066 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
3067 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
3068 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
3069 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
3070 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
3071 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
3072 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
3073 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
3074 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
3075 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
3076
3077 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
3078 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
3079 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
3080 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
3081 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
3082 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
3083
3084 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
3085 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
3086 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
3087 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
3088 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
3089
3090 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
b455159c 3091 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
d9811cfc 3092 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
b455159c 3093
d9811cfc
EQ		 3094 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
3095 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
3096 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
3097 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
b455159c 3098
d9811cfc 3099 dev_info(smu->adev->dev, "UclkDpmPstates\n");
b455159c 3100 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3101 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
b455159c 3102
d9811cfc
EQ		 3103 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
3104 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
b455159c 3105 pptable->UclkDpmSrcFreqRange.Fmin);
d9811cfc 3106 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
b455159c 3107 pptable->UclkDpmSrcFreqRange.Fmax);
d9811cfc
EQ		 3108 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
3109 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
b455159c 3110 pptable->UclkDpmTargFreqRange.Fmin);
d9811cfc 3111 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
b455159c 3112 pptable->UclkDpmTargFreqRange.Fmax);
d9811cfc
EQ		 3113 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
3114 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
b455159c 3115
d9811cfc 3116 dev_info(smu->adev->dev, "PcieGenSpeed\n");
b455159c 3117 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3118 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
b455159c 3119
d9811cfc 3120 dev_info(smu->adev->dev, "PcieLaneCount\n");
b455159c 3121 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3122 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
b455159c 3123
d9811cfc 3124 dev_info(smu->adev->dev, "LclkFreq\n");
b455159c 3125 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3126 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
b455159c 3127
d9811cfc
EQ		 3128 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
3129 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
b455159c 3130
d9811cfc 3131 dev_info(smu->adev->dev, "FanGain\n");
b455159c 3132 for (i = 0; i < TEMP_COUNT; i++)
d9811cfc
EQ		 3133 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
3134
3135 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
3136 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
3137 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
3138 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
3139 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
3140 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
3141 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
3142 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
3143 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
3144 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
3145 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
3146 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
3147
3148 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
3149 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
3150 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
3151 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
3152
3153 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
3154 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
3155 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
3156 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
3157
3158 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3159 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
3160 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
3161 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
d9811cfc 3162 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3163 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
3164 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
3165 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
d9811cfc 3166 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3167 pptable->dBtcGbGfxPll.a,
3168 pptable->dBtcGbGfxPll.b,
3169 pptable->dBtcGbGfxPll.c);
d9811cfc 3170 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3171 pptable->dBtcGbGfxDfll.a,
3172 pptable->dBtcGbGfxDfll.b,
3173 pptable->dBtcGbGfxDfll.c);
d9811cfc 3174 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3175 pptable->dBtcGbSoc.a,
3176 pptable->dBtcGbSoc.b,
3177 pptable->dBtcGbSoc.c);
d9811cfc 3178 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
b455159c
LG		 3179 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
3180 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
d9811cfc 3181 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
b455159c
LG		 3182 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
3183 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
3184
d9811cfc 3185 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
b455159c 3186 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
d9811cfc 3187 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
b455159c 3188 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
d9811cfc 3189 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
b455159c
LG		 3190 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
3191 }
3192
d9811cfc 3193 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3194 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
3195 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
3196 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
d9811cfc 3197 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3198 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
3199 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
3200 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
3201
d9811cfc
EQ		 3202 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
3203 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
b455159c 3204
d9811cfc
EQ		 3205 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
3206 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
3207 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
3208 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
b455159c 3209
d9811cfc
EQ		 3210 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
3211 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
3212 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
3213 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
b455159c 3214
d9811cfc
EQ		 3215 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
3216 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
b455159c 3217
d9811cfc 3218 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
b455159c 3219 for (i = 0; i < NUM_XGMI_LEVELS; i++)
d9811cfc
EQ		 3220 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
3221 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
3222 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
b455159c 3223
d9811cfc
EQ		 3224 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
3225 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3226 pptable->ReservedEquation0.a,
3227 pptable->ReservedEquation0.b,
3228 pptable->ReservedEquation0.c);
d9811cfc 3229 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3230 pptable->ReservedEquation1.a,
3231 pptable->ReservedEquation1.b,
3232 pptable->ReservedEquation1.c);
d9811cfc 3233 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3234 pptable->ReservedEquation2.a,
3235 pptable->ReservedEquation2.b,
3236 pptable->ReservedEquation2.c);
d9811cfc 3237 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3238 pptable->ReservedEquation3.a,
3239 pptable->ReservedEquation3.b,
3240 pptable->ReservedEquation3.c);
3241
d9811cfc
EQ		 3242 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3243 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3244 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3245 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3246 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3247 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3248 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3249 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
d9811cfc
EQ		 3250
3251 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3252 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3253 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3254 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3255 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3256 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
b455159c
LG		 3257
3258 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
d9811cfc
EQ		 3259 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3260 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
b455159c 3261 pptable->I2cControllers[i].Enabled);
d9811cfc 3262 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
b455159c 3263 pptable->I2cControllers[i].Speed);
d9811cfc 3264 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
b455159c 3265 pptable->I2cControllers[i].SlaveAddress);
d9811cfc 3266 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
b455159c 3267 pptable->I2cControllers[i].ControllerPort);
d9811cfc 3268 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
b455159c 3269 pptable->I2cControllers[i].ControllerName);
d9811cfc 3270 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
b455159c 3271 pptable->I2cControllers[i].ThermalThrotter);
d9811cfc 3272 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
b455159c 3273 pptable->I2cControllers[i].I2cProtocol);
d9811cfc 3274 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
b455159c
LG		 3275 pptable->I2cControllers[i].PaddingConfig);
3276 }
3277
d9811cfc
EQ		 3278 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3279 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3280 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3281 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3282
3283 dev_info(smu->adev->dev, "Board Parameters:\n");
3284 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3285 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3286 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3287 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3288 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3289 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3290 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3291 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3292
3293 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3294 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3295 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3296
3297 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3298 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3299 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3300
3301 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3302 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3303 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3304
3305 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3306 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3307 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3308
3309 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3310
3311 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3312 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3313 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3314 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3315 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3316 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3317 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3318 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3319 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3320 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3321 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3322 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3323 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3324 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3325 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3326 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3327
3328 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3329 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3330 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3331
3332 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3333 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3334 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3335
f0f3d68e 3336 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
d9811cfc
EQ		 3337 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3338
3339 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3340 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3341 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3342
3343 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3344 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3345 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3346 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3347 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3348
3349 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3350 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3351
3352 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
b455159c 3353 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3354 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3355 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
b455159c 3356 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3357 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3358 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
b455159c 3359 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3360 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3361 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
b455159c 3362 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3363 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3364
3365 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3366 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3367 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3368 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3369
3370 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3371 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3372 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3373 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3374 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3375 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3376 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3377 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3378 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3379 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3380 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
d9811cfc
EQ		 3381
3382 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3383 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3384 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3385 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3386 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3387 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3388 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3389 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
b455159c
LG		 3390}
3391
bc50ca29
AD		 3392static void sienna_cichlid_fill_i2c_req(SwI2cRequest_t *req, bool write,
3393 uint8_t address, uint32_t numbytes,
3394 uint8_t *data)
3395{
3396 int i;
3397
0d294931 3398 req->I2CcontrollerPort = 1;
bc50ca29
AD		 3399 req->I2CSpeed = 2;
3400 req->SlaveAddress = address;
3401 req->NumCmds = numbytes;
3402
3403 for (i = 0; i < numbytes; i++) {
3404 SwI2cCmd_t *cmd = &req->SwI2cCmds[i];
3405
3406 /* First 2 bytes are always write for lower 2b EEPROM address */
3407 if (i < 2)
3408 cmd->CmdConfig = CMDCONFIG_READWRITE_MASK;
3409 else
3410 cmd->CmdConfig = write ? CMDCONFIG_READWRITE_MASK : 0;
3411
3412
3413 /* Add RESTART for read after address filled */
3414 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
3415
3416 /* Add STOP in the end */
3417 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
3418
3419 /* Fill with data regardless if read or write to simplify code */
3420 cmd->ReadWriteData = data[i];
3421 }
3422}
3423
3424static int sienna_cichlid_i2c_read_data(struct i2c_adapter *control,
3425 uint8_t address,
3426 uint8_t *data,
3427 uint32_t numbytes)
3428{
3429 uint32_t i, ret = 0;
3430 SwI2cRequest_t req;
3431 struct amdgpu_device *adev = to_amdgpu_device(control);
3432 struct smu_table_context *smu_table = &adev->smu.smu_table;
3433 struct smu_table *table = &smu_table->driver_table;
3434
d74a09c8
AD		 3435 if (numbytes > MAX_SW_I2C_COMMANDS) {
3436 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
3437 numbytes, MAX_SW_I2C_COMMANDS);
3438 return -EINVAL;
3439 }
3440
bc50ca29
AD		 3441 memset(&req, 0, sizeof(req));
3442 sienna_cichlid_fill_i2c_req(&req, false, address, numbytes, data);
3443
3444 mutex_lock(&adev->smu.mutex);
3445 /* Now read data starting with that address */
3446 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
3447 true);
3448 mutex_unlock(&adev->smu.mutex);
3449
3450 if (!ret) {
3451 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
3452
3453 /* Assume SMU fills res.SwI2cCmds[i].Data with read bytes */
3454 for (i = 0; i < numbytes; i++)
3455 data[i] = res->SwI2cCmds[i].ReadWriteData;
3456
3457 dev_dbg(adev->dev, "sienna_cichlid_i2c_read_data, address = %x, bytes = %d, data :",
3458 (uint16_t)address, numbytes);
3459
3460 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
3461 8, 1, data, numbytes, false);
3462 } else
3463 dev_err(adev->dev, "sienna_cichlid_i2c_read_data - error occurred :%x", ret);
3464
3465 return ret;
3466}
3467
3468static int sienna_cichlid_i2c_write_data(struct i2c_adapter *control,
3469 uint8_t address,
3470 uint8_t *data,
3471 uint32_t numbytes)
3472{
3473 uint32_t ret;
3474 SwI2cRequest_t req;
3475 struct amdgpu_device *adev = to_amdgpu_device(control);
3476
d74a09c8
AD		 3477 if (numbytes > MAX_SW_I2C_COMMANDS) {
3478 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
3479 numbytes, MAX_SW_I2C_COMMANDS);
3480 return -EINVAL;
3481 }
3482
bc50ca29
AD		 3483 memset(&req, 0, sizeof(req));
3484 sienna_cichlid_fill_i2c_req(&req, true, address, numbytes, data);
3485
3486 mutex_lock(&adev->smu.mutex);
3487 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
3488 mutex_unlock(&adev->smu.mutex);
3489
3490 if (!ret) {
3491 dev_dbg(adev->dev, "sienna_cichlid_i2c_write(), address = %x, bytes = %d , data: ",
3492 (uint16_t)address, numbytes);
3493
3494 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
3495 8, 1, data, numbytes, false);
3496 /*
3497 * According to EEPROM spec there is a MAX of 10 ms required for
3498 * EEPROM to flush internal RX buffer after STOP was issued at the
3499 * end of write transaction. During this time the EEPROM will not be
3500 * responsive to any more commands - so wait a bit more.
3501 */
3502 msleep(10);
3503
3504 } else
3505 dev_err(adev->dev, "sienna_cichlid_i2c_write- error occurred :%x", ret);
3506
3507 return ret;
3508}
3509
3510static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
3511 struct i2c_msg *msgs, int num)
3512{
3513 uint32_t i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
3514 uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
3515
3516 for (i = 0; i < num; i++) {
3517 /*
3518 * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
3519 * once and hence the data needs to be spliced into chunks and sent each
3520 * chunk separately
3521 */
3522 data_size = msgs[i].len - 2;
3523 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
3524 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
3525 data_ptr = msgs[i].buf + 2;
3526
3527 for (j = 0; j < data_size / data_chunk_size; j++) {
3528 /* Insert the EEPROM dest addess, bits 0-15 */
3529 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
3530 data_chunk[1] = (next_eeprom_addr & 0xff);
3531
3532 if (msgs[i].flags & I2C_M_RD) {
3533 ret = sienna_cichlid_i2c_read_data(i2c_adap,
3534 (uint8_t)msgs[i].addr,
3535 data_chunk, MAX_SW_I2C_COMMANDS);
3536
3537 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
3538 } else {
3539
3540 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
3541
3542 ret = sienna_cichlid_i2c_write_data(i2c_adap,
3543 (uint8_t)msgs[i].addr,
3544 data_chunk, MAX_SW_I2C_COMMANDS);
3545 }
3546
3547 if (ret) {
3548 num = -EIO;
3549 goto fail;
3550 }
3551
3552 next_eeprom_addr += data_chunk_size;
3553 data_ptr += data_chunk_size;
3554 }
3555
3556 if (data_size % data_chunk_size) {
3557 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
3558 data_chunk[1] = (next_eeprom_addr & 0xff);
3559
3560 if (msgs[i].flags & I2C_M_RD) {
3561 ret = sienna_cichlid_i2c_read_data(i2c_adap,
3562 (uint8_t)msgs[i].addr,
3563 data_chunk, (data_size % data_chunk_size) + 2);
3564
3565 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
3566 } else {
3567 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
3568
3569 ret = sienna_cichlid_i2c_write_data(i2c_adap,
3570 (uint8_t)msgs[i].addr,
3571 data_chunk, (data_size % data_chunk_size) + 2);
3572 }
3573
3574 if (ret) {
3575 num = -EIO;
3576 goto fail;
3577 }
3578 }
3579 }
3580
3581fail:
3582 return num;
3583}
3584
3585static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
3586{
3587 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3588}
3589
3590
3591static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
3592 .master_xfer = sienna_cichlid_i2c_xfer,
3593 .functionality = sienna_cichlid_i2c_func,
3594};
3595
bc50ca29
AD		 3596static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
3597{
3598 struct amdgpu_device *adev = to_amdgpu_device(control);
3599 int res;
3600
bc50ca29
AD		 3601 control->owner = THIS_MODULE;
3602 control->class = I2C_CLASS_SPD;
3603 control->dev.parent = &adev->pdev->dev;
3604 control->algo = &sienna_cichlid_i2c_algo;
3605 snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
3606
3607 res = i2c_add_adapter(control);
3608 if (res)
3609 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3610
3611 return res;
3612}
3613
3614static void sienna_cichlid_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
3615{
bc50ca29
AD		 3616 i2c_del_adapter(control);
3617}
3618
8ca78a0a
EQ		 3619static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
3620 void **table)
3621{
3622 struct smu_table_context *smu_table = &smu->smu_table;
152bb95c
EQ		 3623 struct gpu_metrics_v1_1 *gpu_metrics =
3624 (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
b4b0b79d
EQ		 3625 SmuMetricsExternal_t metrics_external;
3626 SmuMetrics_t *metrics =
3627 &(metrics_external.SmuMetrics);
c524c1c9
EQ		 3628 struct amdgpu_device *adev = smu->adev;
3629 uint32_t smu_version;
8ca78a0a
EQ		 3630 int ret = 0;
3631
fceafc9b 3632 ret = smu_cmn_get_metrics_table(smu,
b4b0b79d 3633 &metrics_external,
fceafc9b 3634 true);
60ae4d67 3635 if (ret)
8ca78a0a 3636 return ret;
8ca78a0a 3637
152bb95c 3638 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1);
8ca78a0a 3639
b4b0b79d
EQ		 3640 gpu_metrics->temperature_edge = metrics->TemperatureEdge;
3641 gpu_metrics->temperature_hotspot = metrics->TemperatureHotspot;
3642 gpu_metrics->temperature_mem = metrics->TemperatureMem;
3643 gpu_metrics->temperature_vrgfx = metrics->TemperatureVrGfx;
3644 gpu_metrics->temperature_vrsoc = metrics->TemperatureVrSoc;
3645 gpu_metrics->temperature_vrmem = metrics->TemperatureVrMem0;
8ca78a0a 3646
b4b0b79d
EQ		 3647 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity;
3648 gpu_metrics->average_umc_activity = metrics->AverageUclkActivity;
3649 gpu_metrics->average_mm_activity = metrics->VcnActivityPercentage;
8ca78a0a 3650
b4b0b79d
EQ		 3651 gpu_metrics->average_socket_power = metrics->AverageSocketPower;
3652 gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
8ca78a0a 3653
b4b0b79d
EQ		 3654 if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
3655 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
8ca78a0a 3656 else
b4b0b79d
EQ		 3657 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs;
3658 gpu_metrics->average_uclk_frequency = metrics->AverageUclkFrequencyPostDs;
3659 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency;
3660 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency;
3661 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency;
3662 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency;
3663
3664 gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK];
3665 gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK];
3666 gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];
3667 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0];
3668 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0];
3669 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1];
3670 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1];
3671
3672 gpu_metrics->throttle_status = metrics->ThrottlerStatus;
3673
3674 gpu_metrics->current_fan_speed = metrics->CurrFanSpeed;
8ca78a0a 3675
c524c1c9
EQ		 3676 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
3677 if (ret)
3678 return ret;
3679
3680 if (((adev->asic_type == CHIP_SIENNA_CICHLID) && smu_version > 0x003A1E00) ||
3681 ((adev->asic_type == CHIP_NAVY_FLOUNDER) && smu_version > 0x00410400)) {
3682 gpu_metrics->pcie_link_width = metrics->PcieWidth;
3683 gpu_metrics->pcie_link_speed = link_speed[metrics->PcieRate];
3684 } else {
3685 gpu_metrics->pcie_link_width =
3686 smu_v11_0_get_current_pcie_link_width(smu);
3687 gpu_metrics->pcie_link_speed =
3688 smu_v11_0_get_current_pcie_link_speed(smu);
3689 }
8ca78a0a 3690
de4b7cd8
KW		 3691 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3692
8ca78a0a
EQ		 3693 *table = (void *)gpu_metrics;
3694
152bb95c 3695 return sizeof(struct gpu_metrics_v1_1);
8ca78a0a 3696}
bc50ca29 3697
05f39286
EQ		 3698static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
3699{
b804a75d
EQ		 3700 struct smu_table_context *table_context = &smu->smu_table;
3701 PPTable_t *smc_pptable = table_context->driver_pptable;
3702
3703 /*
3704 * Skip the MGpuFanBoost setting for those ASICs
3705 * which do not support it
3706 */
3707 if (!smc_pptable->MGpuFanBoostLimitRpm)
3708 return 0;
3709
05f39286
EQ		 3710 return smu_cmn_send_smc_msg_with_param(smu,
3711 SMU_MSG_SetMGpuFanBoostLimitRpm,
3712 0,
3713 NULL);
3714}
3715
76c71f00
EQ		 3716static int sienna_cichlid_gpo_control(struct smu_context *smu,
3717 bool enablement)
3718{
ac7804bb 3719 uint32_t smu_version;
76c71f00
EQ		 3720 int ret = 0;
3721
ac7804bb 3722
76c71f00 3723 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
ac7804bb
EQ		 3724 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
3725 if (ret)
3726 return ret;
3727
3728 if (enablement) {
3729 if (smu_version < 0x003a2500) {
3730 ret = smu_cmn_send_smc_msg_with_param(smu,
3731 SMU_MSG_SetGpoFeaturePMask,
3732 GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
3733 NULL);
3734 } else {
3735 ret = smu_cmn_send_smc_msg_with_param(smu,
3736 SMU_MSG_DisallowGpo,
3737 0,
3738 NULL);
3739 }
3740 } else {
3741 if (smu_version < 0x003a2500) {
3742 ret = smu_cmn_send_smc_msg_with_param(smu,
3743 SMU_MSG_SetGpoFeaturePMask,
3744 0,
3745 NULL);
3746 } else {
3747 ret = smu_cmn_send_smc_msg_with_param(smu,
3748 SMU_MSG_DisallowGpo,
3749 1,
3750 NULL);
3751 }
3752 }
76c71f00
EQ		 3753 }
3754
3755 return ret;
3756}
d7f52e29
EQ		 3757
3758static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
3759{
3760 uint32_t smu_version;
3761 int ret = 0;
3762
3763 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
3764 if (ret)
3765 return ret;
3766
3767 /*
3768 * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
3769 * onwards PMFWs.
3770 */
3771 if (smu_version < 0x003A2D00)
3772 return 0;
3773
3774 return smu_cmn_send_smc_msg_with_param(smu,
3775 SMU_MSG_Enable2ndUSB20Port,
3776 smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
3777 1 : 0,
3778 NULL);
3779}
3780
3781static int sienna_cichlid_system_features_control(struct smu_context *smu,
3782 bool en)
3783{
3784 int ret = 0;
3785
3786 if (en) {
3787 ret = sienna_cichlid_notify_2nd_usb20_port(smu);
3788 if (ret)
3789 return ret;
3790 }
3791
3792 return smu_v11_0_system_features_control(smu, en);
3793}
3794
1689fca0
EQ		 3795static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
3796 enum pp_mp1_state mp1_state)
3797{
9113a0fb
GC		 3798 int ret;
3799
1689fca0
EQ		 3800 switch (mp1_state) {
3801 case PP_MP1_STATE_UNLOAD:
9113a0fb
GC		 3802 ret = smu_cmn_set_mp1_state(smu, mp1_state);
3803 break;
1689fca0 3804 default:
9113a0fb
GC		 3805 /* Ignore others */
3806 ret = 0;
1689fca0
EQ		 3807 }
3808
9113a0fb 3809 return ret;
1689fca0
EQ		 3810}
3811
b455159c 3812static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
b455159c
LG		 3813 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
3814 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
f6b4b4a1 3815 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
6fb176a7 3816 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
bc50ca29
AD		 3817 .i2c_init = sienna_cichlid_i2c_control_init,
3818 .i2c_fini = sienna_cichlid_i2c_control_fini,
b455159c
LG		 3819 .print_clk_levels = sienna_cichlid_print_clk_levels,
3820 .force_clk_levels = sienna_cichlid_force_clk_levels,
3821 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
b455159c
LG		 3822 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
3823 .display_config_changed = sienna_cichlid_display_config_changed,
3824 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
b455159c 3825 .is_dpm_running = sienna_cichlid_is_dpm_running,
4954a76a 3826 .get_fan_speed_percent = sienna_cichlid_get_fan_speed_percent,
b455159c
LG		 3827 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
3828 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
b455159c
LG		 3829 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
3830 .read_sensor = sienna_cichlid_read_sensor,
3831 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
b2785e25 3832 .set_performance_level = smu_v11_0_set_performance_level,
b455159c
LG		 3833 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
3834 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
3835 .get_power_limit = sienna_cichlid_get_power_limit,
08ccfe08 3836 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
b455159c
LG		 3837 .dump_pptable = sienna_cichlid_dump_pptable,
3838 .init_microcode = smu_v11_0_init_microcode,
3839 .load_microcode = smu_v11_0_load_microcode,
c1b353b7 3840 .init_smc_tables = sienna_cichlid_init_smc_tables,
b455159c
LG		 3841 .fini_smc_tables = smu_v11_0_fini_smc_tables,
3842 .init_power = smu_v11_0_init_power,
3843 .fini_power = smu_v11_0_fini_power,
3844 .check_fw_status = smu_v11_0_check_fw_status,
4a13b4ce 3845 .setup_pptable = sienna_cichlid_setup_pptable,
b455159c 3846 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
b455159c 3847 .check_fw_version = smu_v11_0_check_fw_version,
caad2613 3848 .write_pptable = smu_cmn_write_pptable,
b455159c
LG		 3849 .set_driver_table_location = smu_v11_0_set_driver_table_location,
3850 .set_tool_table_location = smu_v11_0_set_tool_table_location,
3851 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
d7f52e29 3852 .system_features_control = sienna_cichlid_system_features_control,
66c86828
EQ		 3853 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
3854 .send_smc_msg = smu_cmn_send_smc_msg,
31157341 3855 .init_display_count = NULL,
b455159c 3856 .set_allowed_mask = smu_v11_0_set_allowed_mask,
28251d72 3857 .get_enabled_mask = smu_cmn_get_enabled_mask,
b4bb3aaf 3858 .feature_is_enabled = smu_cmn_feature_is_enabled,
af5ba6d2 3859 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
31157341 3860 .notify_display_change = NULL,
b455159c 3861 .set_power_limit = smu_v11_0_set_power_limit,
b455159c
LG		 3862 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
3863 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
3864 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
ce63d8f8 3865 .set_min_dcef_deep_sleep = NULL,
b455159c
LG		 3866 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
3867 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
3868 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
cd305137 3869 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
b455159c
LG		 3870 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
3871 .gfx_off_control = smu_v11_0_gfx_off_control,
3872 .register_irq_handler = smu_v11_0_register_irq_handler,
3873 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
3874 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
9fd4781b 3875 .baco_is_support = smu_v11_0_baco_is_support,
b455159c
LG		 3876 .baco_get_state = smu_v11_0_baco_get_state,
3877 .baco_set_state = smu_v11_0_baco_set_state,
3878 .baco_enter = smu_v11_0_baco_enter,
3879 .baco_exit = smu_v11_0_baco_exit,
ea8139d8
WS		 3880 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
3881 .mode1_reset = smu_v11_0_mode1_reset,
258d290c 3882 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
10e96d89 3883 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
aa75fa34 3884 .set_default_od_settings = sienna_cichlid_set_default_od_settings,
37a58f69 3885 .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
66b8a9c0 3886 .run_btc = sienna_cichlid_run_btc,
18a4b3de 3887 .set_power_source = smu_v11_0_set_power_source,
7dbf7805
EQ		 3888 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3889 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
8ca78a0a 3890 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
05f39286 3891 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
e988026f 3892 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
5ce99853 3893 .deep_sleep_control = smu_v11_0_deep_sleep_control,
3204ff3e 3894 .get_fan_parameters = sienna_cichlid_get_fan_parameters,
234676d6 3895 .interrupt_work = smu_v11_0_interrupt_work,
76c71f00 3896 .gpo_control = sienna_cichlid_gpo_control,
1689fca0 3897 .set_mp1_state = sienna_cichlid_set_mp1_state,
b455159c
LG		 3898};
3899
3900void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
3901{
3902 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
6c339f37
EQ		 3903 smu->message_map = sienna_cichlid_message_map;
3904 smu->clock_map = sienna_cichlid_clk_map;
3905 smu->feature_map = sienna_cichlid_feature_mask_map;
3906 smu->table_map = sienna_cichlid_table_map;
3907 smu->pwr_src_map = sienna_cichlid_pwr_src_map;
3908 smu->workload_map = sienna_cichlid_workload_map;
b455159c 3909}
Linux 6.x block layer and io_uring tree(s)