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drm/amd: Move helper for dynamic speed switch check out of smu13
[linux-block.git] / drivers / gpu / drm / amd / pm / swsmu / smu11 / sienna_cichlid_ppt.c
CommitLineData
b455159c
LG		 1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
d8e0b16d
EQ		 24#define SWSMU_CODE_LAYER_L2
25
b455159c
LG		 26#include <linux/firmware.h>
27#include <linux/pci.h>
bc50ca29 28#include <linux/i2c.h>
b455159c 29#include "amdgpu.h"
2f60dd50 30#include "amdgpu_dpm.h"
b455159c 31#include "amdgpu_smu.h"
b455159c
LG		 32#include "atomfirmware.h"
33#include "amdgpu_atomfirmware.h"
22f2447c 34#include "amdgpu_atombios.h"
b455159c
LG		 35#include "smu_v11_0.h"
36#include "smu11_driver_if_sienna_cichlid.h"
37#include "soc15_common.h"
38#include "atom.h"
39#include "sienna_cichlid_ppt.h"
e05acd78 40#include "smu_v11_0_7_pptable.h"
b455159c 41#include "smu_v11_0_7_ppsmc.h"
40d3b8db 42#include "nbio/nbio_2_3_offset.h"
b7d25b5f 43#include "nbio/nbio_2_3_sh_mask.h"
e05acd78
LG		 44#include "thm/thm_11_0_2_offset.h"
45#include "thm/thm_11_0_2_sh_mask.h"
ea8139d8
WS		 46#include "mp/mp_11_0_offset.h"
47#include "mp/mp_11_0_sh_mask.h"
b455159c 48
6c339f37 49#include "asic_reg/mp/mp_11_0_sh_mask.h"
3ddd0c90 50#include "amdgpu_ras.h"
6c339f37
EQ		 51#include "smu_cmn.h"
52
55084d7f
EQ		 53/*
54 * DO NOT use these for err/warn/info/debug messages.
55 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
56 * They are more MGPU friendly.
57 */
58#undef pr_err
59#undef pr_warn
60#undef pr_info
61#undef pr_debug
62
b455159c
LG		 63#define FEATURE_MASK(feature) (1ULL << feature)
64#define SMC_DPM_FEATURE ( \
65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
fea905d4 66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65297d50 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
5cb74353 68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
4cd4f45b 69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
5f338f70 70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
ce7e5a6e
JC		 71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \
72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
b455159c 73
d817f375
LG		 74#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
75
7077b19a 76#define GET_PPTABLE_MEMBER(field, member) do {\
1d789535 77 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))\
7077b19a
CG		 78 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
79 else\
80 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
81} while(0)
82
db5b5c67
AG		 83/* STB FIFO depth is in 64bit units */
84#define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES 8
85
3ddd0c90 86/*
87 * SMU support ECCTABLE since version 58.70.0,
88 * use this to check whether ECCTABLE feature is supported.
89 */
90#define SUPPORT_ECCTABLE_SMU_VERSION 0x003a4600
91
7077b19a
CG		 92static int get_table_size(struct smu_context *smu)
93{
1d789535 94 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
7077b19a
CG		 95 return sizeof(PPTable_beige_goby_t);
96 else
97 return sizeof(PPTable_t);
98}
99
6c339f37
EQ		 100static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
101 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
102 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
103 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
91190db1
LG		 104 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
105 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
106 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
107 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
6c339f37
EQ		 108 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
109 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
110 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
111 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
112 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
113 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
114 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
91190db1 115 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
4215a119
HC		 116 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
117 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
91190db1
LG		 118 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
119 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
4215a119 120 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
91190db1
LG		 121 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
122 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
66b8a9c0 123 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
91190db1 124 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
4215a119
HC		 125 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
126 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
6c339f37 127 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
91190db1 128 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
6c339f37
EQ		 129 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
130 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
131 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
91190db1
LG		 132 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
133 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
134 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
135 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
136 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
137 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
138 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
139 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
6c339f37 140 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
91190db1
LG		 141 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
142 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
40f1dc52 143 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
6c339f37 144 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
91190db1
LG		 145 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
146 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
147 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
148 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
149 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
150 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
151 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
152 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
05f39286 153 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
76c71f00 154 MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0),
ac7804bb 155 MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0),
88dfd5d5 156 MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0),
672c0218 157 MSG_MAP(DriverMode2Reset, PPSMC_MSG_DriverMode2Reset, 0),
b455159c
LG		 158};
159
6c339f37 160static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
b455159c
LG		 161 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
162 CLK_MAP(SCLK, PPCLK_GFXCLK),
163 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
164 CLK_MAP(FCLK, PPCLK_FCLK),
165 CLK_MAP(UCLK, PPCLK_UCLK),
166 CLK_MAP(MCLK, PPCLK_UCLK),
167 CLK_MAP(DCLK, PPCLK_DCLK_0),
9c0551f2
JC		 168 CLK_MAP(DCLK1, PPCLK_DCLK_1),
169 CLK_MAP(VCLK, PPCLK_VCLK_0),
b455159c
LG		 170 CLK_MAP(VCLK1, PPCLK_VCLK_1),
171 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
172 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
173 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
174 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
175};
176
6c339f37 177static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
b455159c
LG		 178 FEA_MAP(DPM_PREFETCHER),
179 FEA_MAP(DPM_GFXCLK),
31cb0dd9 180 FEA_MAP(DPM_GFX_GPO),
b455159c 181 FEA_MAP(DPM_UCLK),
e9073b43 182 FEA_MAP(DPM_FCLK),
b455159c
LG		 183 FEA_MAP(DPM_SOCCLK),
184 FEA_MAP(DPM_MP0CLK),
185 FEA_MAP(DPM_LINK),
186 FEA_MAP(DPM_DCEFCLK),
e9073b43 187 FEA_MAP(DPM_XGMI),
b455159c
LG		 188 FEA_MAP(MEM_VDDCI_SCALING),
189 FEA_MAP(MEM_MVDD_SCALING),
190 FEA_MAP(DS_GFXCLK),
191 FEA_MAP(DS_SOCCLK),
e9073b43 192 FEA_MAP(DS_FCLK),
b455159c
LG		 193 FEA_MAP(DS_LCLK),
194 FEA_MAP(DS_DCEFCLK),
195 FEA_MAP(DS_UCLK),
196 FEA_MAP(GFX_ULV),
197 FEA_MAP(FW_DSTATE),
198 FEA_MAP(GFXOFF),
199 FEA_MAP(BACO),
6fb176a7 200 FEA_MAP(MM_DPM_PG),
b455159c
LG		 201 FEA_MAP(RSMU_SMN_CG),
202 FEA_MAP(PPT),
203 FEA_MAP(TDC),
204 FEA_MAP(APCC_PLUS),
205 FEA_MAP(GTHR),
206 FEA_MAP(ACDC),
207 FEA_MAP(VR0HOT),
208 FEA_MAP(VR1HOT),
209 FEA_MAP(FW_CTF),
210 FEA_MAP(FAN_CONTROL),
211 FEA_MAP(THERMAL),
212 FEA_MAP(GFX_DCS),
213 FEA_MAP(RM),
214 FEA_MAP(LED_DISPLAY),
215 FEA_MAP(GFX_SS),
216 FEA_MAP(OUT_OF_BAND_MONITOR),
217 FEA_MAP(TEMP_DEPENDENT_VMIN),
218 FEA_MAP(MMHUB_PG),
219 FEA_MAP(ATHUB_PG),
cf06331f 220 FEA_MAP(APCC_DFLL),
b455159c
LG		 221};
222
6c339f37 223static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
b455159c
LG		 224 TAB_MAP(PPTABLE),
225 TAB_MAP(WATERMARKS),
226 TAB_MAP(AVFS_PSM_DEBUG),
227 TAB_MAP(AVFS_FUSE_OVERRIDE),
228 TAB_MAP(PMSTATUSLOG),
229 TAB_MAP(SMU_METRICS),
230 TAB_MAP(DRIVER_SMU_CONFIG),
231 TAB_MAP(ACTIVITY_MONITOR_COEFF),
232 TAB_MAP(OVERDRIVE),
233 TAB_MAP(I2C_COMMANDS),
234 TAB_MAP(PACE),
3ddd0c90 235 TAB_MAP(ECCINFO),
b455159c
LG		 236};
237
6c339f37 238static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
1d5ca713
LG		 239 PWR_MAP(AC),
240 PWR_MAP(DC),
241};
242
6c339f37 243static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
b455159c
LG		 244 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
245 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
246 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
247 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
248 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
4c4d5a49 249 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
b455159c
LG		 250 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
251};
252
f06d9511
GS		 253static const uint8_t sienna_cichlid_throttler_map[] = {
254 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
255 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
256 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
257 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
258 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
259 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
260 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
261 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
262 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
263 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
264 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
265 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
266 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
267 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
268 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
269 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
270 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
271 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
272};
273
b455159c
LG		 274static int
275sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
276 uint32_t *feature_mask, uint32_t num)
277{
fea905d4
LG		 278 struct amdgpu_device *adev = smu->adev;
279
b455159c
LG		 280 if (num > 2)
281 return -EINVAL;
282
283 memset(feature_mask, 0, sizeof(uint32_t) * num);
284
4cd4f45b 285 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
15dbe18f 286 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
ce7e5a6e 287 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
094cdf15 288 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
5f338f70 289 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
86a9eb3f 290 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
80c36f86 291 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
9aa60213
LG		 292 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
293 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
d28f4aa1 294 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
20d71dcc 295 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
d0d71970 296 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
886c8bc6
LG		 297 | FEATURE_MASK(FEATURE_PPT_BIT)
298 | FEATURE_MASK(FEATURE_TDC_BIT)
3fc006f5 299 | FEATURE_MASK(FEATURE_BACO_BIT)
cf06331f 300 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
35ed946c 301 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
1c58d429 302 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
b971df70
LG		 303 | FEATURE_MASK(FEATURE_THERMAL_BIT)
304 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
fea905d4 305
c96721eb 306 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
fea905d4 307 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
c96721eb
KF		 308 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
309 }
fea905d4 310
680602d6 311 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
1d789535 312 (adev->ip_versions[MP1_HWIP][0] > IP_VERSION(11, 0, 7)) &&
680602d6
KF		 313 !(adev->flags & AMD_IS_APU))
314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
315
65297d50 316 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
fc17cd3f
LG		 317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
318 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
319 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
65297d50 320
5cb74353
LG		 321 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
322 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
323
5f338f70
LG		 324 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
325 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
326
fea905d4
LG		 327 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
328 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
b455159c 329
62c1ea6b
LG		 330 if (adev->pm.pp_feature & PP_ULV_MASK)
331 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
332
02bb391d
LG		 333 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
334 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
335
e0da123a
LG		 336 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
337 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
338
b794616d
KF		 339 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
340 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
341
846938c2
KF		 342 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
343 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
344
6fb176a7
LG		 345 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
346 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
347 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
348
62826b86
KF		 349 if (smu->dc_controlled_by_gpio)
350 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
351
0ab5d711 352 if (amdgpu_device_should_use_aspm(adev))
6ef28889
KF		 353 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
354
b455159c
LG		 355 return 0;
356}
357
458020dd 358static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
b455159c 359{
4a13b4ce 360 struct smu_table_context *table_context = &smu->smu_table;
e05acd78 361 struct smu_11_0_7_powerplay_table *powerplay_table =
4a13b4ce
EQ		 362 table_context->power_play_table;
363 struct smu_baco_context *smu_baco = &smu->smu_baco;
458020dd
LL		 364 struct amdgpu_device *adev = smu->adev;
365 uint32_t val;
366
1b41d67e 367 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) {
458020dd
LL		 368 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
369 smu_baco->platform_support =
370 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
371 false;
7bb91228
GC		 372
373 /*
374 * Disable BACO entry/exit completely on below SKUs to
375 * avoid hardware intermittent failures.
376 */
377 if (((adev->pdev->device == 0x73A1) &&
378 (adev->pdev->revision == 0x00)) ||
379 ((adev->pdev->device == 0x73BF) &&
0c85c067
GC		 380 (adev->pdev->revision == 0xCF)) ||
381 ((adev->pdev->device == 0x7422) &&
192039f1
GC		 382 (adev->pdev->revision == 0x00)) ||
383 ((adev->pdev->device == 0x73A3) &&
384 (adev->pdev->revision == 0x00)) ||
385 ((adev->pdev->device == 0x73E3) &&
0c85c067 386 (adev->pdev->revision == 0x00)))
7bb91228
GC		 387 smu_baco->platform_support = false;
388
458020dd
LL		 389 }
390}
391
57301181
ES		 392static void sienna_cichlid_check_fan_support(struct smu_context *smu)
393{
394 struct smu_table_context *table_context = &smu->smu_table;
395 PPTable_t *pptable = table_context->driver_pptable;
396 uint64_t features = *(uint64_t *) pptable->FeaturesToRun;
397
398 /* Fan control is not possible if PPTable has it disabled */
399 smu->adev->pm.no_fan =
400 !(features & (1ULL << FEATURE_FAN_CONTROL_BIT));
401 if (smu->adev->pm.no_fan)
402 dev_info_once(smu->adev->dev,
403 "PMFW based fan control disabled");
404}
405
458020dd
LL		 406static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
407{
408 struct smu_table_context *table_context = &smu->smu_table;
409 struct smu_11_0_7_powerplay_table *powerplay_table =
410 table_context->power_play_table;
4a13b4ce 411
18a4b3de
EQ		 412 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
413 smu->dc_controlled_by_gpio = true;
414
458020dd 415 sienna_cichlid_check_bxco_support(smu);
57301181 416 sienna_cichlid_check_fan_support(smu);
4a13b4ce
EQ		 417
418 table_context->thermal_controller_type =
419 powerplay_table->thermal_controller_type;
420
aa75fa34
EQ		 421 /*
422 * Instead of having its own buffer space and get overdrive_table copied,
423 * smu->od_settings just points to the actual overdrive_table
424 */
425 smu->od_settings = &powerplay_table->overdrive_table;
426
b455159c
LG		 427 return 0;
428}
429
430static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
431{
dccc7c21
LG		 432 struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
433 int index, ret;
d50dc746
SS		 434 PPTable_beige_goby_t *ppt_beige_goby;
435 PPTable_t *ppt;
436
437 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
438 ppt_beige_goby = smu->smu_table.driver_pptable;
439 else
440 ppt = smu->smu_table.driver_pptable;
dccc7c21
LG		 441
442 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
443 smc_dpm_info);
444
22f2447c 445 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
dccc7c21
LG		 446 (uint8_t **)&smc_dpm_table);
447 if (ret)
448 return ret;
d50dc746
SS		 449
450 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
451 smu_memcpy_trailing(ppt_beige_goby, I2cControllers, BoardReserved,
452 smc_dpm_table, I2cControllers);
453 else
454 smu_memcpy_trailing(ppt, I2cControllers, BoardReserved,
455 smc_dpm_table, I2cControllers);
20f5e6cf 456
b455159c
LG		 457 return 0;
458}
459
460static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
461{
b455159c 462 struct smu_table_context *table_context = &smu->smu_table;
e05acd78 463 struct smu_11_0_7_powerplay_table *powerplay_table =
4a13b4ce 464 table_context->power_play_table;
7077b19a 465 int table_size;
b455159c 466
7077b19a 467 table_size = get_table_size(smu);
b455159c 468 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
7077b19a 469 table_size);
b455159c 470
4a13b4ce
EQ		 471 return 0;
472}
b455159c 473
951be8be
EQ		 474static int sienna_cichlid_patch_pptable_quirk(struct smu_context *smu)
475{
476 struct amdgpu_device *adev = smu->adev;
477 uint32_t *board_reserved;
478 uint16_t *freq_table_gfx;
479 uint32_t i;
480
481 /* Fix some OEM SKU specific stability issues */
482 GET_PPTABLE_MEMBER(BoardReserved, &board_reserved);
483 if ((adev->pdev->device == 0x73DF) &&
484 (adev->pdev->revision == 0XC3) &&
485 (adev->pdev->subsystem_device == 0x16C2) &&
486 (adev->pdev->subsystem_vendor == 0x1043))
487 board_reserved[0] = 1387;
488
489 GET_PPTABLE_MEMBER(FreqTableGfx, &freq_table_gfx);
490 if ((adev->pdev->device == 0x73DF) &&
491 (adev->pdev->revision == 0XC3) &&
492 ((adev->pdev->subsystem_device == 0x16C2) ||
493 (adev->pdev->subsystem_device == 0x133C)) &&
494 (adev->pdev->subsystem_vendor == 0x1043)) {
495 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) {
496 if (freq_table_gfx[i] > 2500)
497 freq_table_gfx[i] = 2500;
498 }
499 }
500
501 return 0;
502}
503
4a13b4ce
EQ		 504static int sienna_cichlid_setup_pptable(struct smu_context *smu)
505{
506 int ret = 0;
b455159c 507
4a13b4ce
EQ		 508 ret = smu_v11_0_setup_pptable(smu);
509 if (ret)
510 return ret;
511
512 ret = sienna_cichlid_store_powerplay_table(smu);
513 if (ret)
514 return ret;
515
516 ret = sienna_cichlid_append_powerplay_table(smu);
517 if (ret)
518 return ret;
519
520 ret = sienna_cichlid_check_powerplay_table(smu);
521 if (ret)
522 return ret;
523
951be8be 524 return sienna_cichlid_patch_pptable_quirk(smu);
b455159c
LG		 525}
526
c1b353b7 527static int sienna_cichlid_tables_init(struct smu_context *smu)
b455159c
LG		 528{
529 struct smu_table_context *smu_table = &smu->smu_table;
c1b353b7 530 struct smu_table *tables = smu_table->tables;
7077b19a 531 int table_size;
b455159c 532
7077b19a
CG		 533 table_size = get_table_size(smu);
534 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
535 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c
LG		 536 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
537 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b4b0b79d 538 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
b455159c 539 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
bc50ca29
AD		 540 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
541 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c
LG		 542 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
543 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
544 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
545 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
546 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
f9e3fe46 547 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
b455159c 548 AMDGPU_GEM_DOMAIN_VRAM);
3ddd0c90 549 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
550 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
816d61d5
EQ		 551 SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfigExternal_t),
552 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c 553
b4b0b79d 554 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
b455159c 555 if (!smu_table->metrics_table)
8ca78a0a 556 goto err0_out;
b455159c
LG		 557 smu_table->metrics_time = 0;
558
f06d9511 559 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
8ca78a0a
EQ		 560 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
561 if (!smu_table->gpu_metrics_table)
562 goto err1_out;
563
40d3b8db
LG		 564 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
565 if (!smu_table->watermarks_table)
8ca78a0a 566 goto err2_out;
40d3b8db 567
3ddd0c90 568 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
569 if (!smu_table->ecc_table)
816d61d5
EQ		 570 goto err3_out;
571
572 smu_table->driver_smu_config_table =
573 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL);
574 if (!smu_table->driver_smu_config_table)
575 goto err4_out;
3ddd0c90 576
b455159c 577 return 0;
8ca78a0a 578
816d61d5
EQ		 579err4_out:
580 kfree(smu_table->ecc_table);
581err3_out:
582 kfree(smu_table->watermarks_table);
8ca78a0a
EQ		 583err2_out:
584 kfree(smu_table->gpu_metrics_table);
585err1_out:
586 kfree(smu_table->metrics_table);
587err0_out:
588 return -ENOMEM;
b455159c
LG		 589}
590
be22e2b9
EQ		 591static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu)
592{
593 struct smu_table_context *smu_table= &smu->smu_table;
594 SmuMetricsExternal_t *metrics_ext =
595 (SmuMetricsExternal_t *)(smu_table->metrics_table);
596 uint32_t throttler_status = 0;
597 int i;
598
1d789535 599 if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
7952fa0d
DS		 600 (smu->smc_fw_version >= 0x3A4900)) {
601 for (i = 0; i < THROTTLER_COUNT; i++)
602 throttler_status |=
603 (metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0);
604 } else if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
be22e2b9
EQ		 605 (smu->smc_fw_version >= 0x3A4300)) {
606 for (i = 0; i < THROTTLER_COUNT; i++)
607 throttler_status |=
608 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
609 } else {
610 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus;
611 }
612
613 return throttler_status;
614}
615
d6810d7d
S		 616static int sienna_cichlid_get_power_limit(struct smu_context *smu,
617 uint32_t *current_power_limit,
618 uint32_t *default_power_limit,
619 uint32_t *max_power_limit)
620{
621 struct smu_11_0_7_powerplay_table *powerplay_table =
622 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
623 uint32_t power_limit, od_percent;
624 uint16_t *table_member;
625
626 GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
627
628 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
629 power_limit =
630 table_member[PPT_THROTTLER_PPT0];
631 }
632
633 if (current_power_limit)
634 *current_power_limit = power_limit;
635 if (default_power_limit)
636 *default_power_limit = power_limit;
637
638 if (max_power_limit) {
639 if (smu->od_enabled) {
640 od_percent =
641 le32_to_cpu(powerplay_table->overdrive_table.max[
642 SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
643
644 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n",
645 od_percent, power_limit);
646
647 power_limit *= (100 + od_percent);
648 power_limit /= 100;
649 }
650 *max_power_limit = power_limit;
651 }
652
653 return 0;
654}
655
656static void sienna_cichlid_get_smartshift_power_percentage(struct smu_context *smu,
657 uint32_t *apu_percent,
658 uint32_t *dgpu_percent)
659{
660 struct smu_table_context *smu_table = &smu->smu_table;
661 SmuMetrics_V4_t *metrics_v4 =
662 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V4);
663 uint16_t powerRatio = 0;
664 uint16_t apu_power_limit = 0;
665 uint16_t dgpu_power_limit = 0;
666 uint32_t apu_boost = 0;
667 uint32_t dgpu_boost = 0;
668 uint32_t cur_power_limit;
669
670 if (metrics_v4->ApuSTAPMSmartShiftLimit != 0) {
671 sienna_cichlid_get_power_limit(smu, &cur_power_limit, NULL, NULL);
672 apu_power_limit = metrics_v4->ApuSTAPMLimit;
673 dgpu_power_limit = cur_power_limit;
674 powerRatio = (((apu_power_limit +
675 dgpu_power_limit) * 100) /
676 metrics_v4->ApuSTAPMSmartShiftLimit);
677 if (powerRatio > 100) {
678 apu_power_limit = (apu_power_limit * 100) /
679 powerRatio;
680 dgpu_power_limit = (dgpu_power_limit * 100) /
681 powerRatio;
682 }
683 if (metrics_v4->AverageApuSocketPower > apu_power_limit &&
684 apu_power_limit != 0) {
685 apu_boost = ((metrics_v4->AverageApuSocketPower -
686 apu_power_limit) * 100) /
687 apu_power_limit;
688 if (apu_boost > 100)
689 apu_boost = 100;
690 }
691
692 if (metrics_v4->AverageSocketPower > dgpu_power_limit &&
693 dgpu_power_limit != 0) {
694 dgpu_boost = ((metrics_v4->AverageSocketPower -
695 dgpu_power_limit) * 100) /
696 dgpu_power_limit;
697 if (dgpu_boost > 100)
698 dgpu_boost = 100;
699 }
700
701 if (dgpu_boost >= apu_boost)
702 apu_boost = 0;
703 else
704 dgpu_boost = 0;
705 }
706 *apu_percent = apu_boost;
707 *dgpu_percent = dgpu_boost;
708}
709
60ae4d67
EQ		 710static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
711 MetricsMember_t member,
712 uint32_t *value)
713{
714 struct smu_table_context *smu_table= &smu->smu_table;
b4b0b79d
EQ		 715 SmuMetrics_t *metrics =
716 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
be22e2b9
EQ		 717 SmuMetrics_V2_t *metrics_v2 =
718 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
7952fa0d
DS		 719 SmuMetrics_V3_t *metrics_v3 =
720 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V3);
721 bool use_metrics_v2 = false;
722 bool use_metrics_v3 = false;
be22e2b9 723 uint16_t average_gfx_activity;
60ae4d67 724 int ret = 0;
d6810d7d
S		 725 uint32_t apu_percent = 0;
726 uint32_t dgpu_percent = 0;
60ae4d67 727
396beb91
EQ		 728 switch (smu->adev->ip_versions[MP1_HWIP][0]) {
729 case IP_VERSION(11, 0, 7):
730 if (smu->smc_fw_version >= 0x3A4900)
731 use_metrics_v3 = true;
732 else if (smu->smc_fw_version >= 0x3A4300)
733 use_metrics_v2 = true;
734 break;
735 case IP_VERSION(11, 0, 11):
736 if (smu->smc_fw_version >= 0x412D00)
737 use_metrics_v2 = true;
738 break;
739 case IP_VERSION(11, 0, 12):
740 if (smu->smc_fw_version >= 0x3B2300)
741 use_metrics_v2 = true;
742 break;
743 case IP_VERSION(11, 0, 13):
744 if (smu->smc_fw_version >= 0x491100)
745 use_metrics_v2 = true;
746 break;
747 default:
748 break;
749 }
7952fa0d 750
da11407f
EQ		 751 ret = smu_cmn_get_metrics_table(smu,
752 NULL,
753 false);
754 if (ret)
60ae4d67 755 return ret;
60ae4d67 756
8c686254
EQ		 757 switch (member) {
758 case METRICS_CURR_GFXCLK:
7952fa0d
DS		 759 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
760 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] :
be22e2b9 761 metrics->CurrClock[PPCLK_GFXCLK];
8c686254
EQ		 762 break;
763 case METRICS_CURR_SOCCLK:
7952fa0d
DS		 764 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
765 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] :
be22e2b9 766 metrics->CurrClock[PPCLK_SOCCLK];
8c686254
EQ		 767 break;
768 case METRICS_CURR_UCLK:
7952fa0d
DS		 769 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
770 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] :
be22e2b9 771 metrics->CurrClock[PPCLK_UCLK];
8c686254
EQ		 772 break;
773 case METRICS_CURR_VCLK:
7952fa0d
DS		 774 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
775 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] :
be22e2b9 776 metrics->CurrClock[PPCLK_VCLK_0];
8c686254
EQ		 777 break;
778 case METRICS_CURR_VCLK1:
7952fa0d
DS		 779 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
780 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] :
be22e2b9 781 metrics->CurrClock[PPCLK_VCLK_1];
8c686254
EQ		 782 break;
783 case METRICS_CURR_DCLK:
7952fa0d
DS		 784 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
785 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] :
be22e2b9 786 metrics->CurrClock[PPCLK_DCLK_0];
8c686254
EQ		 787 break;
788 case METRICS_CURR_DCLK1:
7952fa0d
DS		 789 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
790 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
be22e2b9 791 metrics->CurrClock[PPCLK_DCLK_1];
8c686254 792 break;
9d09fa6f 793 case METRICS_CURR_DCEFCLK:
7952fa0d
DS		 794 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCEFCLK] :
795 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] :
be22e2b9 796 metrics->CurrClock[PPCLK_DCEFCLK];
9d09fa6f 797 break;
4e2b3e23 798 case METRICS_CURR_FCLK:
7952fa0d
DS		 799 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_FCLK] :
800 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] :
be22e2b9 801 metrics->CurrClock[PPCLK_FCLK];
4e2b3e23 802 break;
8c686254 803 case METRICS_AVERAGE_GFXCLK:
7952fa0d
DS		 804 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
805 use_metrics_v2 ? metrics_v2->AverageGfxActivity :
be22e2b9
EQ		 806 metrics->AverageGfxActivity;
807 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
7952fa0d
DS		 808 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
809 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
be22e2b9 810 metrics->AverageGfxclkFrequencyPostDs;
d817f375 811 else
7952fa0d
DS		 812 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
813 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
be22e2b9 814 metrics->AverageGfxclkFrequencyPreDs;
8c686254
EQ		 815 break;
816 case METRICS_AVERAGE_FCLK:
7952fa0d
DS		 817 *value = use_metrics_v3 ? metrics_v3->AverageFclkFrequencyPostDs :
818 use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs :
be22e2b9 819 metrics->AverageFclkFrequencyPostDs;
8c686254
EQ		 820 break;
821 case METRICS_AVERAGE_UCLK:
7952fa0d
DS		 822 *value = use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
823 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
be22e2b9 824 metrics->AverageUclkFrequencyPostDs;
8c686254
EQ		 825 break;
826 case METRICS_AVERAGE_GFXACTIVITY:
7952fa0d
DS		 827 *value = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
828 use_metrics_v2 ? metrics_v2->AverageGfxActivity :
be22e2b9 829 metrics->AverageGfxActivity;
8c686254
EQ		 830 break;
831 case METRICS_AVERAGE_MEMACTIVITY:
7952fa0d
DS		 832 *value = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
833 use_metrics_v2 ? metrics_v2->AverageUclkActivity :
be22e2b9 834 metrics->AverageUclkActivity;
8c686254
EQ		 835 break;
836 case METRICS_AVERAGE_SOCKETPOWER:
7952fa0d
DS		 837 *value = use_metrics_v3 ? metrics_v3->AverageSocketPower << 8 :
838 use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 :
be22e2b9 839 metrics->AverageSocketPower << 8;
8c686254
EQ		 840 break;
841 case METRICS_TEMPERATURE_EDGE:
7952fa0d
DS		 842 *value = (use_metrics_v3 ? metrics_v3->TemperatureEdge :
843 use_metrics_v2 ? metrics_v2->TemperatureEdge :
844 metrics->TemperatureEdge) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
8c686254
EQ		 845 break;
846 case METRICS_TEMPERATURE_HOTSPOT:
7952fa0d
DS		 847 *value = (use_metrics_v3 ? metrics_v3->TemperatureHotspot :
848 use_metrics_v2 ? metrics_v2->TemperatureHotspot :
849 metrics->TemperatureHotspot) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
8c686254
EQ		 850 break;
851 case METRICS_TEMPERATURE_MEM:
7952fa0d
DS		 852 *value = (use_metrics_v3 ? metrics_v3->TemperatureMem :
853 use_metrics_v2 ? metrics_v2->TemperatureMem :
854 metrics->TemperatureMem) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
8c686254
EQ		 855 break;
856 case METRICS_TEMPERATURE_VRGFX:
7952fa0d
DS		 857 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
858 use_metrics_v2 ? metrics_v2->TemperatureVrGfx :
859 metrics->TemperatureVrGfx) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
8c686254
EQ		 860 break;
861 case METRICS_TEMPERATURE_VRSOC:
7952fa0d
DS		 862 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
863 use_metrics_v2 ? metrics_v2->TemperatureVrSoc :
864 metrics->TemperatureVrSoc) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
8c686254
EQ		 865 break;
866 case METRICS_THROTTLER_STATUS:
be22e2b9 867 *value = sienna_cichlid_get_throttler_status_locked(smu);
8c686254
EQ		 868 break;
869 case METRICS_CURR_FANSPEED:
7952fa0d
DS		 870 *value = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
871 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
8c686254 872 break;
ebd9c071 873 case METRICS_UNIQUE_ID_UPPER32:
5e9c4451
KR		 874 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
875 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumUpper32 : 0;
ebd9c071
KR		 876 break;
877 case METRICS_UNIQUE_ID_LOWER32:
5e9c4451
KR		 878 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
879 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumLower32 : 0;
ebd9c071 880 break;
d6810d7d
S		 881 case METRICS_SS_APU_SHARE:
882 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
883 *value = apu_percent;
884 break;
885 case METRICS_SS_DGPU_SHARE:
886 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
887 *value = dgpu_percent;
888 break;
889
8c686254
EQ		 890 default:
891 *value = UINT_MAX;
892 break;
893 }
894
b455159c 895 return ret;
8c686254 896
b455159c
LG		 897}
898
899static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
900{
901 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
902
b455159c
LG		 903 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
904 GFP_KERNEL);
905 if (!smu_dpm->dpm_context)
906 return -ENOMEM;
907
908 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
909
910 return 0;
911}
912
db5b5c67
AG		 913static void sienna_cichlid_stb_init(struct smu_context *smu);
914
c1b353b7
EQ		 915static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
916{
748262eb 917 struct amdgpu_device *adev = smu->adev;
c1b353b7
EQ		 918 int ret = 0;
919
920 ret = sienna_cichlid_tables_init(smu);
921 if (ret)
922 return ret;
923
924 ret = sienna_cichlid_allocate_dpm_context(smu);
925 if (ret)
926 return ret;
927
748262eb 928 if (!amdgpu_sriov_vf(adev))
929 sienna_cichlid_stb_init(smu);
db5b5c67 930
c1b353b7
EQ		 931 return smu_v11_0_init_smc_tables(smu);
932}
933
b455159c
LG		 934static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
935{
90a89c31 936 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
90a89c31 937 struct smu_11_0_dpm_table *dpm_table;
85dec717 938 struct amdgpu_device *adev = smu->adev;
0b54122c 939 int i, ret = 0;
7077b19a 940 DpmDescriptor_t *table_member;
b455159c 941
90a89c31
EQ		 942 /* socclk dpm table setup */
943 dpm_table = &dpm_context->dpm_tables.soc_table;
7077b19a 944 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
b4bb3aaf 945 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
90a89c31
EQ		 946 ret = smu_v11_0_set_single_dpm_table(smu,
947 SMU_SOCCLK,
948 dpm_table);
949 if (ret)
950 return ret;
951 dpm_table->is_fine_grained =
7077b19a 952 !table_member[PPCLK_SOCCLK].SnapToDiscrete;
90a89c31
EQ		 953 } else {
954 dpm_table->count = 1;
955 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
956 dpm_table->dpm_levels[0].enabled = true;
957 dpm_table->min = dpm_table->dpm_levels[0].value;
958 dpm_table->max = dpm_table->dpm_levels[0].value;
959 }
b455159c 960
90a89c31
EQ		 961 /* gfxclk dpm table setup */
962 dpm_table = &dpm_context->dpm_tables.gfx_table;
b4bb3aaf 963 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
90a89c31
EQ		 964 ret = smu_v11_0_set_single_dpm_table(smu,
965 SMU_GFXCLK,
966 dpm_table);
967 if (ret)
968 return ret;
969 dpm_table->is_fine_grained =
7077b19a 970 !table_member[PPCLK_GFXCLK].SnapToDiscrete;
90a89c31
EQ		 971 } else {
972 dpm_table->count = 1;
973 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
974 dpm_table->dpm_levels[0].enabled = true;
975 dpm_table->min = dpm_table->dpm_levels[0].value;
976 dpm_table->max = dpm_table->dpm_levels[0].value;
977 }
b455159c 978
90a89c31
EQ		 979 /* uclk dpm table setup */
980 dpm_table = &dpm_context->dpm_tables.uclk_table;
b4bb3aaf 981 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
90a89c31
EQ		 982 ret = smu_v11_0_set_single_dpm_table(smu,
983 SMU_UCLK,
984 dpm_table);
985 if (ret)
986 return ret;
987 dpm_table->is_fine_grained =
7077b19a 988 !table_member[PPCLK_UCLK].SnapToDiscrete;
90a89c31
EQ		 989 } else {
990 dpm_table->count = 1;
991 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
992 dpm_table->dpm_levels[0].enabled = true;
993 dpm_table->min = dpm_table->dpm_levels[0].value;
994 dpm_table->max = dpm_table->dpm_levels[0].value;
995 }
b455159c 996
90a89c31
EQ		 997 /* fclk dpm table setup */
998 dpm_table = &dpm_context->dpm_tables.fclk_table;
b4bb3aaf 999 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
90a89c31
EQ		 1000 ret = smu_v11_0_set_single_dpm_table(smu,
1001 SMU_FCLK,
1002 dpm_table);
1003 if (ret)
1004 return ret;
1005 dpm_table->is_fine_grained =
7077b19a 1006 !table_member[PPCLK_FCLK].SnapToDiscrete;
90a89c31
EQ		 1007 } else {
1008 dpm_table->count = 1;
1009 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
1010 dpm_table->dpm_levels[0].enabled = true;
1011 dpm_table->min = dpm_table->dpm_levels[0].value;
1012 dpm_table->max = dpm_table->dpm_levels[0].value;
1013 }
b455159c 1014
0b54122c
AD		 1015 /* vclk0/1 dpm table setup */
1016 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1017 if (adev->vcn.harvest_config & (1 << i))
1018 continue;
b455159c 1019
0b54122c 1020 dpm_table = &dpm_context->dpm_tables.vclk_table;
85dec717
JC		 1021 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1022 ret = smu_v11_0_set_single_dpm_table(smu,
0b54122c 1023 i ? SMU_VCLK1 : SMU_VCLK,
85dec717
JC		 1024 dpm_table);
1025 if (ret)
1026 return ret;
1027 dpm_table->is_fine_grained =
0b54122c 1028 !table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete;
85dec717
JC		 1029 } else {
1030 dpm_table->count = 1;
0b54122c 1031 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
85dec717
JC		 1032 dpm_table->dpm_levels[0].enabled = true;
1033 dpm_table->min = dpm_table->dpm_levels[0].value;
1034 dpm_table->max = dpm_table->dpm_levels[0].value;
1035 }
90a89c31 1036 }
b455159c 1037
0b54122c
AD		 1038 /* dclk0/1 dpm table setup */
1039 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1040 if (adev->vcn.harvest_config & (1 << i))
1041 continue;
1042 dpm_table = &dpm_context->dpm_tables.dclk_table;
85dec717
JC		 1043 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1044 ret = smu_v11_0_set_single_dpm_table(smu,
0b54122c 1045 i ? SMU_DCLK1 : SMU_DCLK,
85dec717
JC		 1046 dpm_table);
1047 if (ret)
1048 return ret;
1049 dpm_table->is_fine_grained =
0b54122c 1050 !table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0].SnapToDiscrete;
85dec717
JC		 1051 } else {
1052 dpm_table->count = 1;
0b54122c 1053 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
85dec717
JC		 1054 dpm_table->dpm_levels[0].enabled = true;
1055 dpm_table->min = dpm_table->dpm_levels[0].value;
1056 dpm_table->max = dpm_table->dpm_levels[0].value;
1057 }
90a89c31
EQ		 1058 }
1059
1060 /* dcefclk dpm table setup */
1061 dpm_table = &dpm_context->dpm_tables.dcef_table;
b4bb3aaf 1062 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 1063 ret = smu_v11_0_set_single_dpm_table(smu,
1064 SMU_DCEFCLK,
1065 dpm_table);
1066 if (ret)
1067 return ret;
1068 dpm_table->is_fine_grained =
7077b19a 1069 !table_member[PPCLK_DCEFCLK].SnapToDiscrete;
90a89c31
EQ		 1070 } else {
1071 dpm_table->count = 1;
1072 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1073 dpm_table->dpm_levels[0].enabled = true;
1074 dpm_table->min = dpm_table->dpm_levels[0].value;
1075 dpm_table->max = dpm_table->dpm_levels[0].value;
1076 }
b455159c 1077
90a89c31
EQ		 1078 /* pixelclk dpm table setup */
1079 dpm_table = &dpm_context->dpm_tables.pixel_table;
b4bb3aaf 1080 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 1081 ret = smu_v11_0_set_single_dpm_table(smu,
1082 SMU_PIXCLK,
1083 dpm_table);
1084 if (ret)
1085 return ret;
1086 dpm_table->is_fine_grained =
7077b19a 1087 !table_member[PPCLK_PIXCLK].SnapToDiscrete;
90a89c31
EQ		 1088 } else {
1089 dpm_table->count = 1;
1090 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1091 dpm_table->dpm_levels[0].enabled = true;
1092 dpm_table->min = dpm_table->dpm_levels[0].value;
1093 dpm_table->max = dpm_table->dpm_levels[0].value;
1094 }
b455159c 1095
90a89c31
EQ		 1096 /* displayclk dpm table setup */
1097 dpm_table = &dpm_context->dpm_tables.display_table;
b4bb3aaf 1098 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 1099 ret = smu_v11_0_set_single_dpm_table(smu,
1100 SMU_DISPCLK,
1101 dpm_table);
1102 if (ret)
1103 return ret;
1104 dpm_table->is_fine_grained =
7077b19a 1105 !table_member[PPCLK_DISPCLK].SnapToDiscrete;
90a89c31
EQ		 1106 } else {
1107 dpm_table->count = 1;
1108 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1109 dpm_table->dpm_levels[0].enabled = true;
1110 dpm_table->min = dpm_table->dpm_levels[0].value;
1111 dpm_table->max = dpm_table->dpm_levels[0].value;
1112 }
b455159c 1113
90a89c31
EQ		 1114 /* phyclk dpm table setup */
1115 dpm_table = &dpm_context->dpm_tables.phy_table;
b4bb3aaf 1116 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 1117 ret = smu_v11_0_set_single_dpm_table(smu,
1118 SMU_PHYCLK,
1119 dpm_table);
1120 if (ret)
1121 return ret;
1122 dpm_table->is_fine_grained =
7077b19a 1123 !table_member[PPCLK_PHYCLK].SnapToDiscrete;
90a89c31
EQ		 1124 } else {
1125 dpm_table->count = 1;
1126 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1127 dpm_table->dpm_levels[0].enabled = true;
1128 dpm_table->min = dpm_table->dpm_levels[0].value;
1129 dpm_table->max = dpm_table->dpm_levels[0].value;
1130 }
b455159c
LG		 1131
1132 return 0;
1133}
1134
f6b4b4a1 1135static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
b455159c 1136{
d51dc613 1137 struct amdgpu_device *adev = smu->adev;
0b54122c 1138 int i, ret = 0;
b455159c 1139
0b54122c
AD		 1140 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1141 if (adev->vcn.harvest_config & (1 << i))
1142 continue;
b455159c 1143 /* vcn dpm on is a prerequisite for vcn power gate messages */
b4bb3aaf 1144 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
0b54122c
AD		 1145 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1146 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
1147 0x10000 * i, NULL);
6fb176a7
LG		 1148 if (ret)
1149 return ret;
b455159c 1150 }
b455159c
LG		 1151 }
1152
1153 return ret;
1154}
1155
6fb176a7
LG		 1156static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
1157{
6fb176a7
LG		 1158 int ret = 0;
1159
1160 if (enable) {
b4bb3aaf 1161 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 1162 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
6fb176a7
LG		 1163 if (ret)
1164 return ret;
6fb176a7 1165 }
6fb176a7 1166 } else {
b4bb3aaf 1167 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 1168 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
6fb176a7
LG		 1169 if (ret)
1170 return ret;
6fb176a7 1171 }
6fb176a7
LG		 1172 }
1173
1174 return ret;
1175}
1176
b455159c
LG		 1177static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
1178 enum smu_clk_type clk_type,
1179 uint32_t *value)
1180{
8c686254
EQ		 1181 MetricsMember_t member_type;
1182 int clk_id = 0;
b455159c 1183
6c339f37
EQ		 1184 clk_id = smu_cmn_to_asic_specific_index(smu,
1185 CMN2ASIC_MAPPING_CLK,
1186 clk_type);
b455159c
LG		 1187 if (clk_id < 0)
1188 return clk_id;
1189
8c686254
EQ		 1190 switch (clk_id) {
1191 case PPCLK_GFXCLK:
1192 member_type = METRICS_CURR_GFXCLK;
1193 break;
1194 case PPCLK_UCLK:
1195 member_type = METRICS_CURR_UCLK;
1196 break;
1197 case PPCLK_SOCCLK:
1198 member_type = METRICS_CURR_SOCCLK;
1199 break;
1200 case PPCLK_FCLK:
1201 member_type = METRICS_CURR_FCLK;
1202 break;
1203 case PPCLK_VCLK_0:
1204 member_type = METRICS_CURR_VCLK;
1205 break;
1206 case PPCLK_VCLK_1:
1207 member_type = METRICS_CURR_VCLK1;
1208 break;
1209 case PPCLK_DCLK_0:
1210 member_type = METRICS_CURR_DCLK;
1211 break;
1212 case PPCLK_DCLK_1:
1213 member_type = METRICS_CURR_DCLK1;
1214 break;
1215 case PPCLK_DCEFCLK:
1216 member_type = METRICS_CURR_DCEFCLK;
1217 break;
1218 default:
1219 return -EINVAL;
1220 }
1221
1222 return sienna_cichlid_get_smu_metrics_data(smu,
1223 member_type,
1224 value);
b455159c 1225
b455159c
LG		 1226}
1227
1228static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1229{
b455159c 1230 DpmDescriptor_t *dpm_desc = NULL;
7077b19a 1231 DpmDescriptor_t *table_member;
b455159c
LG		 1232 uint32_t clk_index = 0;
1233
7077b19a 1234 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
6c339f37
EQ		 1235 clk_index = smu_cmn_to_asic_specific_index(smu,
1236 CMN2ASIC_MAPPING_CLK,
1237 clk_type);
7077b19a 1238 dpm_desc = &table_member[clk_index];
b455159c
LG		 1239
1240 /* 0 - Fine grained DPM, 1 - Discrete DPM */
0ee56acc 1241 return dpm_desc->SnapToDiscrete == 0;
b455159c
LG		 1242}
1243
37a58f69
EQ		 1244static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
1245 enum SMU_11_0_7_ODFEATURE_CAP cap)
1246{
1247 return od_table->cap[cap];
1248}
1249
1250static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
1251 enum SMU_11_0_7_ODSETTING_ID setting,
1252 uint32_t *min, uint32_t *max)
1253{
1254 if (min)
1255 *min = od_table->min[setting];
1256 if (max)
1257 *max = od_table->max[setting];
1258}
1259
b455159c
LG		 1260static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
1261 enum smu_clk_type clk_type, char *buf)
1262{
b7d25b5f
LG		 1263 struct amdgpu_device *adev = smu->adev;
1264 struct smu_table_context *table_context = &smu->smu_table;
1265 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1266 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
7077b19a
CG		 1267 uint16_t *table_member;
1268
37a58f69
EQ		 1269 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
1270 OverDriveTable_t *od_table =
1271 (OverDriveTable_t *)table_context->overdrive_table;
b455159c
LG		 1272 int i, size = 0, ret = 0;
1273 uint32_t cur_value = 0, value = 0, count = 0;
1274 uint32_t freq_values[3] = {0};
1275 uint32_t mark_index = 0;
b7d25b5f 1276 uint32_t gen_speed, lane_width;
37a58f69 1277 uint32_t min_value, max_value;
a2b6df4f 1278 uint32_t smu_version;
b455159c 1279
8f48ba30
LY		 1280 smu_cmn_get_sysfs_buf(&buf, &size);
1281
b455159c
LG		 1282 switch (clk_type) {
1283 case SMU_GFXCLK:
1284 case SMU_SCLK:
1285 case SMU_SOCCLK:
1286 case SMU_MCLK:
1287 case SMU_UCLK:
1288 case SMU_FCLK:
78842457
DN		 1289 case SMU_VCLK:
1290 case SMU_VCLK1:
1291 case SMU_DCLK:
1292 case SMU_DCLK1:
b455159c 1293 case SMU_DCEFCLK:
5e6dc8fe 1294 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
b455159c 1295 if (ret)
258d290c 1296 goto print_clk_out;
b455159c 1297
d8d3493a 1298 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
b455159c 1299 if (ret)
258d290c 1300 goto print_clk_out;
b455159c
LG		 1301
1302 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1303 for (i = 0; i < count; i++) {
d8d3493a 1304 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
b455159c 1305 if (ret)
258d290c 1306 goto print_clk_out;
b455159c 1307
fe14c285 1308 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
b455159c
LG		 1309 cur_value == value ? "*" : "");
1310 }
1311 } else {
d8d3493a 1312 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
b455159c 1313 if (ret)
258d290c 1314 goto print_clk_out;
d8d3493a 1315 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
b455159c 1316 if (ret)
258d290c 1317 goto print_clk_out;
b455159c
LG		 1318
1319 freq_values[1] = cur_value;
1320 mark_index = cur_value == freq_values[0] ? 0 :
1321 cur_value == freq_values[2] ? 2 : 1;
b455159c 1322
891bacb8
KF		 1323 count = 3;
1324 if (mark_index != 1) {
1325 count = 2;
1326 freq_values[1] = freq_values[2];
1327 }
1328
1329 for (i = 0; i < count; i++) {
fe14c285 1330 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
891bacb8 1331 cur_value == freq_values[i] ? "*" : "");
b455159c
LG		 1332 }
1333
1334 }
1335 break;
b7d25b5f 1336 case SMU_PCIE:
f20c52f4
LG		 1337 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1338 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
7077b19a 1339 GET_PPTABLE_MEMBER(LclkFreq, &table_member);
b7d25b5f 1340 for (i = 0; i < NUM_LINK_LEVELS; i++)
fe14c285 1341 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
b7d25b5f
LG		 1342 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1343 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1344 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1345 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1346 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1347 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1348 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1349 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1350 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1351 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
7077b19a 1352 table_member[i],
b7d25b5f
LG		 1353 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1354 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1355 "*" : "");
1356 break;
37a58f69
EQ		 1357 case SMU_OD_SCLK:
1358 if (!smu->od_enabled || !od_table || !od_settings)
1359 break;
1360
1361 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1362 break;
1363
fe14c285
DP		 1364 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1365 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
37a58f69
EQ		 1366 break;
1367
1368 case SMU_OD_MCLK:
1369 if (!smu->od_enabled || !od_table || !od_settings)
1370 break;
1371
1372 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1373 break;
1374
fe14c285
DP		 1375 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1376 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
37a58f69
EQ		 1377 break;
1378
a2b6df4f
EQ		 1379 case SMU_OD_VDDGFX_OFFSET:
1380 if (!smu->od_enabled || !od_table || !od_settings)
1381 break;
1382
1383 /*
1384 * OD GFX Voltage Offset functionality is supported only by 58.41.0
1385 * and onwards SMU firmwares.
1386 */
1387 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1d789535 1388 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
a2b6df4f
EQ		 1389 (smu_version < 0x003a2900))
1390 break;
1391
fe14c285
DP		 1392 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1393 size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset);
a2b6df4f
EQ		 1394 break;
1395
37a58f69
EQ		 1396 case SMU_OD_RANGE:
1397 if (!smu->od_enabled || !od_table || !od_settings)
1398 break;
1399
8f48ba30 1400 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
37a58f69
EQ		 1401
1402 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1403 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1404 &min_value, NULL);
1405 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1406 NULL, &max_value);
fe14c285 1407 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
37a58f69
EQ		 1408 min_value, max_value);
1409 }
1410
1411 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1412 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1413 &min_value, NULL);
1414 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1415 NULL, &max_value);
fe14c285 1416 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
37a58f69
EQ		 1417 min_value, max_value);
1418 }
1419 break;
1420
b455159c
LG		 1421 default:
1422 break;
1423 }
1424
258d290c 1425print_clk_out:
b455159c
LG		 1426 return size;
1427}
1428
1429static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1430 enum smu_clk_type clk_type, uint32_t mask)
1431{
d3c98301 1432 int ret = 0;
b455159c
LG		 1433 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1434
1435 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1436 soft_max_level = mask ? (fls(mask) - 1) : 0;
1437
1438 switch (clk_type) {
1439 case SMU_GFXCLK:
1440 case SMU_SCLK:
1441 case SMU_SOCCLK:
1442 case SMU_MCLK:
1443 case SMU_UCLK:
b455159c 1444 case SMU_FCLK:
9ad9c8ac
LG		 1445 /* There is only 2 levels for fine grained DPM */
1446 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1447 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1448 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1449 }
1450
d8d3493a 1451 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
b455159c 1452 if (ret)
258d290c 1453 goto forec_level_out;
b455159c 1454
d8d3493a 1455 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
b455159c 1456 if (ret)
258d290c 1457 goto forec_level_out;
b455159c 1458
10e96d89 1459 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
b455159c 1460 if (ret)
258d290c 1461 goto forec_level_out;
b455159c 1462 break;
51ec6992
DP		 1463 case SMU_DCEFCLK:
1464 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1465 break;
b455159c
LG		 1466 default:
1467 break;
1468 }
1469
258d290c 1470forec_level_out:
d3c98301 1471 return 0;
b455159c
LG		 1472}
1473
1474static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1475{
62cc9dd1
EQ		 1476 struct smu_11_0_dpm_context *dpm_context =
1477 smu->smu_dpm.dpm_context;
1478 struct smu_11_0_dpm_table *gfx_table =
1479 &dpm_context->dpm_tables.gfx_table;
1480 struct smu_11_0_dpm_table *mem_table =
1481 &dpm_context->dpm_tables.uclk_table;
1482 struct smu_11_0_dpm_table *soc_table =
1483 &dpm_context->dpm_tables.soc_table;
1484 struct smu_umd_pstate_table *pstate_table =
1485 &smu->pstate_table;
60aac460 1486 struct amdgpu_device *adev = smu->adev;
62cc9dd1
EQ		 1487
1488 pstate_table->gfxclk_pstate.min = gfx_table->min;
1489 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1490
1491 pstate_table->uclk_pstate.min = mem_table->min;
1492 pstate_table->uclk_pstate.peak = mem_table->max;
1493
1494 pstate_table->socclk_pstate.min = soc_table->min;
1495 pstate_table->socclk_pstate.peak = soc_table->max;
60aac460 1496
9d6b2041
AD		 1497 switch (adev->ip_versions[MP1_HWIP][0]) {
1498 case IP_VERSION(11, 0, 7):
1499 case IP_VERSION(11, 0, 11):
60aac460
EQ		 1500 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
1501 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
0dc994fb 1502 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
60aac460 1503 break;
9d6b2041 1504 case IP_VERSION(11, 0, 12):
60aac460
EQ		 1505 pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK;
1506 pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK;
1507 pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK;
1508 break;
9d6b2041 1509 case IP_VERSION(11, 0, 13):
60aac460
EQ		 1510 pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK;
1511 pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK;
1512 pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK;
1513 break;
1514 default:
1515 break;
1516 }
b455159c 1517
62cc9dd1 1518 return 0;
b455159c
LG		 1519}
1520
b455159c
LG		 1521static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1522{
1523 int ret = 0;
1524 uint32_t max_freq = 0;
1525
1526 /* Sienna_Cichlid do not support to change display num currently */
1527 return 0;
1528#if 0
66c86828 1529 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
b455159c
LG		 1530 if (ret)
1531 return ret;
1532#endif
1533
b4bb3aaf 1534 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
e5ef784b 1535 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
b455159c
LG		 1536 if (ret)
1537 return ret;
661b94f5 1538 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
b455159c
LG		 1539 if (ret)
1540 return ret;
1541 }
1542
1543 return ret;
1544}
1545
1546static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1547{
1548 int ret = 0;
1549
b455159c 1550 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
7ade3ca9
EQ		 1551 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1552 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
b455159c 1553#if 0
66c86828 1554 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
40d3b8db
LG		 1555 smu->display_config->num_display,
1556 NULL);
b455159c
LG		 1557#endif
1558 if (ret)
1559 return ret;
1560 }
1561
1562 return ret;
1563}
1564
b455159c
LG		 1565static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1566{
1567 int ret = 0;
3d14a79b
KW		 1568 uint64_t feature_enabled;
1569
2d282665 1570 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
3d14a79b
KW		 1571 if (ret)
1572 return false;
1573
b455159c
LG		 1574 return !!(feature_enabled & SMC_DPM_FEATURE);
1575}
1576
d9ca7567
EQ		 1577static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1578 uint32_t *speed)
1579{
1580 if (!speed)
1581 return -EINVAL;
1582
1583 /*
1584 * For Sienna_Cichlid and later, the fan speed(rpm) reported
1585 * by pmfw is always trustable(even when the fan control feature
1586 * disabled or 0 RPM kicked in).
1587 */
1588 return sienna_cichlid_get_smu_metrics_data(smu,
1589 METRICS_CURR_FANSPEED,
1590 speed);
1591}
1592
3204ff3e
AD		 1593static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1594{
7077b19a 1595 uint16_t *table_member;
3204ff3e 1596
7077b19a
CG		 1597 GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
1598 smu->fan_max_rpm = *table_member;
3204ff3e
AD		 1599
1600 return 0;
1601}
1602
b455159c
LG		 1603static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1604{
f9e3fe46
EQ		 1605 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1606 DpmActivityMonitorCoeffInt_t *activity_monitor =
1607 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
b455159c
LG		 1608 uint32_t i, size = 0;
1609 int16_t workload_type = 0;
b455159c
LG		 1610 static const char *title[] = {
1611 "PROFILE_INDEX(NAME)",
1612 "CLOCK_TYPE(NAME)",
1613 "FPS",
1614 "MinFreqType",
1615 "MinActiveFreqType",
1616 "MinActiveFreq",
1617 "BoosterFreqType",
1618 "BoosterFreq",
1619 "PD_Data_limit_c",
1620 "PD_Data_error_coeff",
1621 "PD_Data_error_rate_coeff"};
1622 int result = 0;
1623
1624 if (!buf)
1625 return -EINVAL;
1626
fe14c285 1627 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
b455159c
LG		 1628 title[0], title[1], title[2], title[3], title[4], title[5],
1629 title[6], title[7], title[8], title[9], title[10]);
1630
1631 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1632 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
6c339f37
EQ		 1633 workload_type = smu_cmn_to_asic_specific_index(smu,
1634 CMN2ASIC_MAPPING_WORKLOAD,
1635 i);
b455159c
LG		 1636 if (workload_type < 0)
1637 return -EINVAL;
1638
caad2613 1639 result = smu_cmn_update_table(smu,
b455159c 1640 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
f9e3fe46 1641 (void *)(&activity_monitor_external), false);
b455159c 1642 if (result) {
d9811cfc 1643 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
b455159c
LG		 1644 return result;
1645 }
1646
fe14c285 1647 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
94a80b5b 1648 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
b455159c 1649
fe14c285 1650 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
b455159c
LG		 1651 " ",
1652 0,
1653 "GFXCLK",
f9e3fe46
EQ		 1654 activity_monitor->Gfx_FPS,
1655 activity_monitor->Gfx_MinFreqStep,
1656 activity_monitor->Gfx_MinActiveFreqType,
1657 activity_monitor->Gfx_MinActiveFreq,
1658 activity_monitor->Gfx_BoosterFreqType,
1659 activity_monitor->Gfx_BoosterFreq,
1660 activity_monitor->Gfx_PD_Data_limit_c,
1661 activity_monitor->Gfx_PD_Data_error_coeff,
1662 activity_monitor->Gfx_PD_Data_error_rate_coeff);
b455159c 1663
fe14c285 1664 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
b455159c
LG		 1665 " ",
1666 1,
1667 "SOCCLK",
f9e3fe46
EQ		 1668 activity_monitor->Fclk_FPS,
1669 activity_monitor->Fclk_MinFreqStep,
1670 activity_monitor->Fclk_MinActiveFreqType,
1671 activity_monitor->Fclk_MinActiveFreq,
1672 activity_monitor->Fclk_BoosterFreqType,
1673 activity_monitor->Fclk_BoosterFreq,
1674 activity_monitor->Fclk_PD_Data_limit_c,
1675 activity_monitor->Fclk_PD_Data_error_coeff,
1676 activity_monitor->Fclk_PD_Data_error_rate_coeff);
b455159c 1677
fe14c285 1678 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
b455159c
LG		 1679 " ",
1680 2,
1681 "MEMLK",
f9e3fe46
EQ		 1682 activity_monitor->Mem_FPS,
1683 activity_monitor->Mem_MinFreqStep,
1684 activity_monitor->Mem_MinActiveFreqType,
1685 activity_monitor->Mem_MinActiveFreq,
1686 activity_monitor->Mem_BoosterFreqType,
1687 activity_monitor->Mem_BoosterFreq,
1688 activity_monitor->Mem_PD_Data_limit_c,
1689 activity_monitor->Mem_PD_Data_error_coeff,
1690 activity_monitor->Mem_PD_Data_error_rate_coeff);
b455159c
LG		 1691 }
1692
1693 return size;
1694}
1695
1696static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1697{
f9e3fe46
EQ		 1698
1699 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1700 DpmActivityMonitorCoeffInt_t *activity_monitor =
1701 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
b455159c
LG		 1702 int workload_type, ret = 0;
1703
1704 smu->power_profile_mode = input[size];
1705
1706 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
d9811cfc 1707 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
b455159c
LG		 1708 return -EINVAL;
1709 }
1710
1711 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
b455159c 1712
caad2613 1713 ret = smu_cmn_update_table(smu,
b455159c 1714 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
f9e3fe46 1715 (void *)(&activity_monitor_external), false);
b455159c 1716 if (ret) {
d9811cfc 1717 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
b455159c
LG		 1718 return ret;
1719 }
1720
1721 switch (input[0]) {
1722 case 0: /* Gfxclk */
f9e3fe46
EQ		 1723 activity_monitor->Gfx_FPS = input[1];
1724 activity_monitor->Gfx_MinFreqStep = input[2];
1725 activity_monitor->Gfx_MinActiveFreqType = input[3];
1726 activity_monitor->Gfx_MinActiveFreq = input[4];
1727 activity_monitor->Gfx_BoosterFreqType = input[5];
1728 activity_monitor->Gfx_BoosterFreq = input[6];
1729 activity_monitor->Gfx_PD_Data_limit_c = input[7];
1730 activity_monitor->Gfx_PD_Data_error_coeff = input[8];
1731 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1732 break;
1733 case 1: /* Socclk */
f9e3fe46
EQ		 1734 activity_monitor->Fclk_FPS = input[1];
1735 activity_monitor->Fclk_MinFreqStep = input[2];
1736 activity_monitor->Fclk_MinActiveFreqType = input[3];
1737 activity_monitor->Fclk_MinActiveFreq = input[4];
1738 activity_monitor->Fclk_BoosterFreqType = input[5];
1739 activity_monitor->Fclk_BoosterFreq = input[6];
1740 activity_monitor->Fclk_PD_Data_limit_c = input[7];
1741 activity_monitor->Fclk_PD_Data_error_coeff = input[8];
1742 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1743 break;
1744 case 2: /* Memlk */
f9e3fe46
EQ		 1745 activity_monitor->Mem_FPS = input[1];
1746 activity_monitor->Mem_MinFreqStep = input[2];
1747 activity_monitor->Mem_MinActiveFreqType = input[3];
1748 activity_monitor->Mem_MinActiveFreq = input[4];
1749 activity_monitor->Mem_BoosterFreqType = input[5];
1750 activity_monitor->Mem_BoosterFreq = input[6];
1751 activity_monitor->Mem_PD_Data_limit_c = input[7];
1752 activity_monitor->Mem_PD_Data_error_coeff = input[8];
1753 activity_monitor->Mem_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1754 break;
1755 }
1756
caad2613 1757 ret = smu_cmn_update_table(smu,
b455159c 1758 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
f9e3fe46 1759 (void *)(&activity_monitor_external), true);
b455159c 1760 if (ret) {
d9811cfc 1761 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
b455159c
LG		 1762 return ret;
1763 }
1764 }
1765
1766 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
6c339f37
EQ		 1767 workload_type = smu_cmn_to_asic_specific_index(smu,
1768 CMN2ASIC_MAPPING_WORKLOAD,
1769 smu->power_profile_mode);
b455159c
LG		 1770 if (workload_type < 0)
1771 return -EINVAL;
66c86828 1772 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
b455159c
LG		 1773 1 << workload_type, NULL);
1774
1775 return ret;
1776}
1777
b455159c
LG		 1778static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1779{
1780 struct smu_clocks min_clocks = {0};
1781 struct pp_display_clock_request clock_req;
1782 int ret = 0;
1783
1784 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1785 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1786 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1787
7ade3ca9 1788 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
b455159c
LG		 1789 clock_req.clock_type = amd_pp_dcef_clock;
1790 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1791
1792 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1793 if (!ret) {
7ade3ca9 1794 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
66c86828 1795 ret = smu_cmn_send_smc_msg_with_param(smu,
40d3b8db
LG		 1796 SMU_MSG_SetMinDeepSleepDcefclk,
1797 min_clocks.dcef_clock_in_sr/100,
1798 NULL);
1799 if (ret) {
d9811cfc 1800 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
40d3b8db
LG		 1801 return ret;
1802 }
b455159c
LG		 1803 }
1804 } else {
d9811cfc 1805 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
b455159c
LG		 1806 }
1807 }
1808
b4bb3aaf 1809 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
661b94f5 1810 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
b455159c 1811 if (ret) {
d9811cfc 1812 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
b455159c
LG		 1813 return ret;
1814 }
1815 }
1816
1817 return 0;
1818}
1819
1820static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
7b9c7e30 1821 struct pp_smu_wm_range_sets *clock_ranges)
b455159c 1822{
e7a95eea 1823 Watermarks_t *table = smu->smu_table.watermarks_table;
40d3b8db 1824 int ret = 0;
e7a95eea 1825 int i;
b455159c 1826
e7a95eea 1827 if (clock_ranges) {
7b9c7e30
EQ		 1828 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1829 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
e7a95eea
EQ		 1830 return -EINVAL;
1831
7b9c7e30
EQ		 1832 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1833 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1834 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1835 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1836 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1837 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1838 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1839 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1840 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1841
1842 table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1843 clock_ranges->reader_wm_sets[i].wm_inst;
e7a95eea 1844 }
b455159c 1845
7b9c7e30
EQ		 1846 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1847 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1848 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1849 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1850 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1851 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1852 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1853 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1854 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1855
1856 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1857 clock_ranges->writer_wm_sets[i].wm_inst;
e7a95eea
EQ		 1858 }
1859
1860 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1861 }
1862
1863 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1864 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
caad2613 1865 ret = smu_cmn_write_watermarks_table(smu);
40d3b8db 1866 if (ret) {
d9811cfc 1867 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
40d3b8db
LG		 1868 return ret;
1869 }
1870 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1871 }
1872
b455159c
LG		 1873 return 0;
1874}
1875
b455159c
LG		 1876static int sienna_cichlid_read_sensor(struct smu_context *smu,
1877 enum amd_pp_sensors sensor,
1878 void *data, uint32_t *size)
1879{
1880 int ret = 0;
7077b19a 1881 uint16_t *temp;
d6810d7d 1882 struct amdgpu_device *adev = smu->adev;
b455159c
LG		 1883
1884 if(!data || !size)
1885 return -EINVAL;
1886
b455159c
LG		 1887 switch (sensor) {
1888 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
7077b19a
CG		 1889 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
1890 *(uint16_t *)data = *temp;
b455159c
LG		 1891 *size = 4;
1892 break;
1893 case AMDGPU_PP_SENSOR_MEM_LOAD:
60e317a2
AD		 1894 ret = sienna_cichlid_get_smu_metrics_data(smu,
1895 METRICS_AVERAGE_MEMACTIVITY,
1896 (uint32_t *)data);
1897 *size = 4;
1898 break;
b455159c 1899 case AMDGPU_PP_SENSOR_GPU_LOAD:
60e317a2
AD		 1900 ret = sienna_cichlid_get_smu_metrics_data(smu,
1901 METRICS_AVERAGE_GFXACTIVITY,
1902 (uint32_t *)data);
b455159c
LG		 1903 *size = 4;
1904 break;
1905 case AMDGPU_PP_SENSOR_GPU_POWER:
60e317a2
AD		 1906 ret = sienna_cichlid_get_smu_metrics_data(smu,
1907 METRICS_AVERAGE_SOCKETPOWER,
1908 (uint32_t *)data);
b455159c
LG		 1909 *size = 4;
1910 break;
1911 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
60e317a2
AD		 1912 ret = sienna_cichlid_get_smu_metrics_data(smu,
1913 METRICS_TEMPERATURE_HOTSPOT,
1914 (uint32_t *)data);
1915 *size = 4;
1916 break;
b455159c 1917 case AMDGPU_PP_SENSOR_EDGE_TEMP:
60e317a2
AD		 1918 ret = sienna_cichlid_get_smu_metrics_data(smu,
1919 METRICS_TEMPERATURE_EDGE,
1920 (uint32_t *)data);
1921 *size = 4;
1922 break;
b455159c 1923 case AMDGPU_PP_SENSOR_MEM_TEMP:
60e317a2
AD		 1924 ret = sienna_cichlid_get_smu_metrics_data(smu,
1925 METRICS_TEMPERATURE_MEM,
1926 (uint32_t *)data);
b455159c
LG		 1927 *size = 4;
1928 break;
e0f9e936
EQ		 1929 case AMDGPU_PP_SENSOR_GFX_MCLK:
1930 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1931 *(uint32_t *)data *= 100;
1932 *size = 4;
1933 break;
1934 case AMDGPU_PP_SENSOR_GFX_SCLK:
1935 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1936 *(uint32_t *)data *= 100;
1937 *size = 4;
1938 break;
b2febc99
EQ		 1939 case AMDGPU_PP_SENSOR_VDDGFX:
1940 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1941 *size = 4;
1942 break;
d6810d7d
S		 1943 case AMDGPU_PP_SENSOR_SS_APU_SHARE:
1944 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) {
1945 ret = sienna_cichlid_get_smu_metrics_data(smu,
1946 METRICS_SS_APU_SHARE, (uint32_t *)data);
1947 *size = 4;
1948 } else {
1949 ret = -EOPNOTSUPP;
1950 }
1951 break;
1952 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
1953 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) {
1954 ret = sienna_cichlid_get_smu_metrics_data(smu,
1955 METRICS_SS_DGPU_SHARE, (uint32_t *)data);
1956 *size = 4;
1957 } else {
1958 ret = -EOPNOTSUPP;
1959 }
1960 break;
b455159c 1961 default:
b2febc99
EQ		 1962 ret = -EOPNOTSUPP;
1963 break;
b455159c 1964 }
b455159c
LG		 1965
1966 return ret;
1967}
1968
ebd9c071
KR		 1969static void sienna_cichlid_get_unique_id(struct smu_context *smu)
1970{
1971 struct amdgpu_device *adev = smu->adev;
1972 uint32_t upper32 = 0, lower32 = 0;
1973
1974 /* Only supported as of version 0.58.83.0 and only on Sienna Cichlid */
1975 if (smu->smc_fw_version < 0x3A5300 ||
1976 smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7))
1977 return;
1978
1979 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32))
1980 goto out;
1981 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32))
1982 goto out;
1983
1984out:
1985
1986 adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1987 if (adev->serial[0] == '\0')
1988 sprintf(adev->serial, "%016llx", adev->unique_id);
1989}
1990
b455159c
LG		 1991static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1992{
1993 uint32_t num_discrete_levels = 0;
1994 uint16_t *dpm_levels = NULL;
1995 uint16_t i = 0;
1996 struct smu_table_context *table_context = &smu->smu_table;
7077b19a
CG		 1997 DpmDescriptor_t *table_member1;
1998 uint16_t *table_member2;
b455159c
LG		 1999
2000 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
2001 return -EINVAL;
2002
7077b19a
CG		 2003 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
2004 num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
2005 GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
2006 dpm_levels = table_member2;
b455159c
LG		 2007
2008 if (num_discrete_levels == 0 || dpm_levels == NULL)
2009 return -EINVAL;
2010
2011 *num_states = num_discrete_levels;
2012 for (i = 0; i < num_discrete_levels; i++) {
2013 /* convert to khz */
2014 *clocks_in_khz = (*dpm_levels) * 1000;
2015 clocks_in_khz++;
2016 dpm_levels++;
2017 }
2018
2019 return 0;
2020}
2021
2022static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
2023 struct smu_temperature_range *range)
2024{
e02e4d51
EQ		 2025 struct smu_table_context *table_context = &smu->smu_table;
2026 struct smu_11_0_7_powerplay_table *powerplay_table =
2027 table_context->power_play_table;
7077b19a
CG		 2028 uint16_t *table_member;
2029 uint16_t temp_edge, temp_hotspot, temp_mem;
b455159c 2030
2b1f12a2 2031 if (!range)
b455159c
LG		 2032 return -EINVAL;
2033
0540eced
EQ		 2034 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
2035
7077b19a
CG		 2036 GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
2037 temp_edge = table_member[TEMP_EDGE];
2038 temp_hotspot = table_member[TEMP_HOTSPOT];
2039 temp_mem = table_member[TEMP_MEM];
2040
2041 range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2042 range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
2b1f12a2 2043 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a
CG		 2044 range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2045 range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
2b1f12a2 2046 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a
CG		 2047 range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2048 range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
b455159c 2049 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a 2050
e02e4d51 2051 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
b455159c
LG		 2052
2053 return 0;
2054}
2055
2056static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
2057 bool disable_memory_clock_switch)
2058{
2059 int ret = 0;
2060 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
2061 (struct smu_11_0_max_sustainable_clocks *)
2062 smu->smu_table.max_sustainable_clocks;
2063 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
2064 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
2065
2066 if(smu->disable_uclk_switch == disable_memory_clock_switch)
2067 return 0;
2068
2069 if(disable_memory_clock_switch)
661b94f5 2070 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
b455159c 2071 else
661b94f5 2072 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
b455159c
LG		 2073
2074 if(!ret)
2075 smu->disable_uclk_switch = disable_memory_clock_switch;
2076
2077 return ret;
2078}
2079
6ff5a1cf
EQ		 2080static void sienna_cichlid_get_override_pcie_settings(struct smu_context *smu,
2081 uint32_t *gen_speed_override,
2082 uint32_t *lane_width_override)
2083{
2084 struct amdgpu_device *adev = smu->adev;
2085
2086 *gen_speed_override = 0xff;
2087 *lane_width_override = 0xff;
2088
2089 switch (adev->pdev->device) {
2090 case 0x73A0:
2091 case 0x73A1:
2092 case 0x73A2:
2093 case 0x73A3:
2094 case 0x73AB:
2095 case 0x73AE:
2096 /* Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 */
2097 *lane_width_override = 6;
2098 break;
2099 case 0x73E0:
2100 case 0x73E1:
2101 case 0x73E3:
2102 *lane_width_override = 4;
2103 break;
2104 case 0x7420:
2105 case 0x7421:
2106 case 0x7422:
2107 case 0x7423:
2108 case 0x7424:
2109 *lane_width_override = 3;
2110 break;
2111 default:
2112 break;
2113 }
2114}
2115
2116#define MAX(a, b) ((a) > (b) ? (a) : (b))
2117
08ccfe08
LG		 2118static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
2119 uint32_t pcie_gen_cap,
2120 uint32_t pcie_width_cap)
2121{
0b590970 2122 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
6ff5a1cf
EQ		 2123 struct smu_11_0_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table;
2124 uint32_t gen_speed_override, lane_width_override;
7077b19a 2125 uint8_t *table_member1, *table_member2;
6ff5a1cf
EQ		 2126 uint32_t min_gen_speed, max_gen_speed;
2127 uint32_t min_lane_width, max_lane_width;
2128 uint32_t smu_pcie_arg;
0b590970 2129 int ret, i;
08ccfe08 2130
7077b19a
CG		 2131 GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
2132 GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
2133
6ff5a1cf
EQ		 2134 sienna_cichlid_get_override_pcie_settings(smu,
2135 &gen_speed_override,
2136 &lane_width_override);
2137
2138 /* PCIE gen speed override */
2139 if (gen_speed_override != 0xff) {
2140 min_gen_speed = MIN(pcie_gen_cap, gen_speed_override);
2141 max_gen_speed = MIN(pcie_gen_cap, gen_speed_override);
2142 } else {
2143 min_gen_speed = MAX(0, table_member1[0]);
2144 max_gen_speed = MIN(pcie_gen_cap, table_member1[1]);
2145 min_gen_speed = min_gen_speed > max_gen_speed ?
2146 max_gen_speed : min_gen_speed;
0b590970 2147 }
6ff5a1cf
EQ		 2148 pcie_table->pcie_gen[0] = min_gen_speed;
2149 pcie_table->pcie_gen[1] = max_gen_speed;
2150
2151 /* PCIE lane width override */
2152 if (lane_width_override != 0xff) {
2153 min_lane_width = MIN(pcie_width_cap, lane_width_override);
2154 max_lane_width = MIN(pcie_width_cap, lane_width_override);
2155 } else {
2156 min_lane_width = MAX(1, table_member2[0]);
2157 max_lane_width = MIN(pcie_width_cap, table_member2[1]);
2158 min_lane_width = min_lane_width > max_lane_width ?
2159 max_lane_width : min_lane_width;
2160 }
2161 pcie_table->pcie_lane[0] = min_lane_width;
2162 pcie_table->pcie_lane[1] = max_lane_width;
08ccfe08
LG		 2163
2164 for (i = 0; i < NUM_LINK_LEVELS; i++) {
6ff5a1cf
EQ		 2165 smu_pcie_arg = (i << 16 |
2166 pcie_table->pcie_gen[i] << 8 |
2167 pcie_table->pcie_lane[i]);
08ccfe08 2168
66c86828 2169 ret = smu_cmn_send_smc_msg_with_param(smu,
7077b19a
CG		 2170 SMU_MSG_OverridePcieParameters,
2171 smu_pcie_arg,
2172 NULL);
08ccfe08
LG		 2173 if (ret)
2174 return ret;
08ccfe08
LG		 2175 }
2176
2177 return 0;
2178}
2179
38ed7b09 2180static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
258d290c
LG		 2181 enum smu_clk_type clk_type,
2182 uint32_t *min, uint32_t *max)
2183{
3bce90bf 2184 return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
258d290c
LG		 2185}
2186
aa75fa34
EQ		 2187static void sienna_cichlid_dump_od_table(struct smu_context *smu,
2188 OverDriveTable_t *od_table)
2189{
a2b6df4f
EQ		 2190 struct amdgpu_device *adev = smu->adev;
2191 uint32_t smu_version;
2192
aa75fa34
EQ		 2193 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
2194 od_table->GfxclkFmax);
2195 dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
2196 od_table->UclkFmax);
a2b6df4f
EQ		 2197
2198 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1d789535 2199 if (!((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
a2b6df4f
EQ		 2200 (smu_version < 0x003a2900)))
2201 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
aa75fa34
EQ		 2202}
2203
2204static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
2205{
2206 OverDriveTable_t *od_table =
2207 (OverDriveTable_t *)smu->smu_table.overdrive_table;
2208 OverDriveTable_t *boot_od_table =
2209 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
b521be9b
EQ		 2210 OverDriveTable_t *user_od_table =
2211 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
49017304 2212 OverDriveTable_t user_od_table_bak;
aa75fa34
EQ		 2213 int ret = 0;
2214
2215 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
b521be9b 2216 0, (void *)boot_od_table, false);
aa75fa34
EQ		 2217 if (ret) {
2218 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2219 return ret;
2220 }
2221
b521be9b 2222 sienna_cichlid_dump_od_table(smu, boot_od_table);
aa75fa34 2223
b521be9b 2224 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
49017304
BS		 2225
2226 /*
2227 * For S3/S4/Runpm resume, we need to setup those overdrive tables again,
2228 * but we have to preserve user defined values in "user_od_table".
2229 */
2230 if (!smu->adev->in_suspend) {
2231 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2232 smu->user_dpm_profile.user_od = false;
2233 } else if (smu->user_dpm_profile.user_od) {
2234 memcpy(&user_od_table_bak, user_od_table, sizeof(OverDriveTable_t));
2235 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2236 user_od_table->GfxclkFmin = user_od_table_bak.GfxclkFmin;
2237 user_od_table->GfxclkFmax = user_od_table_bak.GfxclkFmax;
2238 user_od_table->UclkFmin = user_od_table_bak.UclkFmin;
2239 user_od_table->UclkFmax = user_od_table_bak.UclkFmax;
2240 user_od_table->VddGfxOffset = user_od_table_bak.VddGfxOffset;
2241 }
aa75fa34
EQ		 2242
2243 return 0;
2244}
2245
37a58f69
EQ		 2246static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
2247 struct smu_11_0_7_overdrive_table *od_table,
2248 enum SMU_11_0_7_ODSETTING_ID setting,
2249 uint32_t value)
2250{
2251 if (value < od_table->min[setting]) {
2252 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
2253 setting, value, od_table->min[setting]);
2254 return -EINVAL;
2255 }
2256 if (value > od_table->max[setting]) {
2257 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
2258 setting, value, od_table->max[setting]);
2259 return -EINVAL;
2260 }
2261
2262 return 0;
2263}
2264
2265static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
2266 enum PP_OD_DPM_TABLE_COMMAND type,
2267 long input[], uint32_t size)
2268{
2269 struct smu_table_context *table_context = &smu->smu_table;
2270 OverDriveTable_t *od_table =
2271 (OverDriveTable_t *)table_context->overdrive_table;
2272 struct smu_11_0_7_overdrive_table *od_settings =
2273 (struct smu_11_0_7_overdrive_table *)smu->od_settings;
a2b6df4f 2274 struct amdgpu_device *adev = smu->adev;
37a58f69
EQ		 2275 enum SMU_11_0_7_ODSETTING_ID freq_setting;
2276 uint16_t *freq_ptr;
2277 int i, ret = 0;
a2b6df4f 2278 uint32_t smu_version;
37a58f69
EQ		 2279
2280 if (!smu->od_enabled) {
2281 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2282 return -EINVAL;
2283 }
2284
2285 if (!smu->od_settings) {
2286 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2287 return -ENOENT;
2288 }
2289
2290 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2291 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2292 return -EINVAL;
2293 }
2294
2295 switch (type) {
2296 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2297 if (!sienna_cichlid_is_od_feature_supported(od_settings,
2298 SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
2299 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2300 return -ENOTSUPP;
2301 }
2302
2303 for (i = 0; i < size; i += 2) {
2304 if (i + 2 > size) {
2305 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2306 return -EINVAL;
2307 }
2308
2309 switch (input[i]) {
2310 case 0:
2311 if (input[i + 1] > od_table->GfxclkFmax) {
2312 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2313 input[i + 1], od_table->GfxclkFmax);
2314 return -EINVAL;
2315 }
2316
2317 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
2318 freq_ptr = &od_table->GfxclkFmin;
2319 break;
2320
2321 case 1:
2322 if (input[i + 1] < od_table->GfxclkFmin) {
2323 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2324 input[i + 1], od_table->GfxclkFmin);
2325 return -EINVAL;
2326 }
2327
2328 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
2329 freq_ptr = &od_table->GfxclkFmax;
2330 break;
2331
2332 default:
2333 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2334 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2335 return -EINVAL;
2336 }
2337
2338 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2339 freq_setting, input[i + 1]);
2340 if (ret)
2341 return ret;
2342
2343 *freq_ptr = (uint16_t)input[i + 1];
2344 }
2345 break;
2346
2347 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2348 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
2349 dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2350 return -ENOTSUPP;
2351 }
2352
2353 for (i = 0; i < size; i += 2) {
2354 if (i + 2 > size) {
2355 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2356 return -EINVAL;
2357 }
2358
2359 switch (input[i]) {
2360 case 0:
2361 if (input[i + 1] > od_table->UclkFmax) {
2362 dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2363 input[i + 1], od_table->UclkFmax);
2364 return -EINVAL;
2365 }
2366
2367 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
2368 freq_ptr = &od_table->UclkFmin;
2369 break;
2370
2371 case 1:
2372 if (input[i + 1] < od_table->UclkFmin) {
2373 dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2374 input[i + 1], od_table->UclkFmin);
2375 return -EINVAL;
2376 }
2377
2378 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
2379 freq_ptr = &od_table->UclkFmax;
2380 break;
2381
2382 default:
2383 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2384 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2385 return -EINVAL;
2386 }
2387
2388 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2389 freq_setting, input[i + 1]);
2390 if (ret)
2391 return ret;
2392
2393 *freq_ptr = (uint16_t)input[i + 1];
2394 }
2395 break;
2396
2397 case PP_OD_RESTORE_DEFAULT_TABLE:
2398 memcpy(table_context->overdrive_table,
2399 table_context->boot_overdrive_table,
2400 sizeof(OverDriveTable_t));
2401 fallthrough;
2402
2403 case PP_OD_COMMIT_DPM_TABLE:
b521be9b
EQ		 2404 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2405 sienna_cichlid_dump_od_table(smu, od_table);
2406 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2407 if (ret) {
2408 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2409 return ret;
2410 }
2411 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2412 smu->user_dpm_profile.user_od = true;
37a58f69 2413
b521be9b
EQ		 2414 if (!memcmp(table_context->user_overdrive_table,
2415 table_context->boot_overdrive_table,
2416 sizeof(OverDriveTable_t)))
2417 smu->user_dpm_profile.user_od = false;
37a58f69
EQ		 2418 }
2419 break;
2420
a2b6df4f
EQ		 2421 case PP_OD_EDIT_VDDGFX_OFFSET:
2422 if (size != 1) {
2423 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2424 return -EINVAL;
2425 }
2426
2427 /*
2428 * OD GFX Voltage Offset functionality is supported only by 58.41.0
2429 * and onwards SMU firmwares.
2430 */
2431 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1d789535 2432 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
a2b6df4f
EQ		 2433 (smu_version < 0x003a2900)) {
2434 dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2435 "only by 58.41.0 and onwards SMU firmwares!\n");
2436 return -EOPNOTSUPP;
2437 }
2438
2439 od_table->VddGfxOffset = (int16_t)input[0];
2440
2441 sienna_cichlid_dump_od_table(smu, od_table);
2442 break;
2443
37a58f69
EQ		 2444 default:
2445 return -ENOSYS;
2446 }
2447
2448 return ret;
2449}
2450
49017304
BS		 2451static int sienna_cichlid_restore_user_od_settings(struct smu_context *smu)
2452{
2453 struct smu_table_context *table_context = &smu->smu_table;
2454 OverDriveTable_t *od_table = table_context->overdrive_table;
2455 OverDriveTable_t *user_od_table = table_context->user_overdrive_table;
2456 int res;
2457
2458 res = smu_v11_0_restore_user_od_settings(smu);
2459 if (res == 0)
2460 memcpy(od_table, user_od_table, sizeof(OverDriveTable_t));
2461
2462 return res;
2463}
2464
66b8a9c0
JC		 2465static int sienna_cichlid_run_btc(struct smu_context *smu)
2466{
dc78fea1
LT		 2467 int res;
2468
2469 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2470 if (res)
2471 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2472
2473 return res;
66b8a9c0
JC		 2474}
2475
13d75ead
EQ		 2476static int sienna_cichlid_baco_enter(struct smu_context *smu)
2477{
2478 struct amdgpu_device *adev = smu->adev;
2479
8b514e89 2480 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
13d75ead
EQ		 2481 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2482 else
2483 return smu_v11_0_baco_enter(smu);
2484}
2485
2486static int sienna_cichlid_baco_exit(struct smu_context *smu)
2487{
2488 struct amdgpu_device *adev = smu->adev;
2489
8b514e89 2490 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
13d75ead
EQ		 2491 /* Wait for PMFW handling for the Dstate change */
2492 msleep(10);
2493 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2494 } else {
2495 return smu_v11_0_baco_exit(smu);
2496 }
2497}
2498
ea8139d8
WS		 2499static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2500{
2501 struct amdgpu_device *adev = smu->adev;
2502 uint32_t val;
2503 u32 smu_version;
2504
2505 /**
2506 * SRIOV env will not support SMU mode1 reset
2507 * PM FW support mode1 reset from 58.26
2508 */
a7bae061 2509 smu_cmn_get_smc_version(smu, NULL, &smu_version);
ea8139d8
WS		 2510 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
2511 return false;
2512
2513 /**
2514 * mode1 reset relies on PSP, so we should check if
2515 * PSP is alive.
2516 */
2517 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2518 return val != 0x0;
2519}
2520
7077b19a
CG		 2521static void beige_goby_dump_pptable(struct smu_context *smu)
2522{
2523 struct smu_table_context *table_context = &smu->smu_table;
2524 PPTable_beige_goby_t *pptable = table_context->driver_pptable;
2525 int i;
2526
2527 dev_info(smu->adev->dev, "Dumped PPTable:\n");
2528
2529 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2530 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2531 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2532
2533 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2534 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2535 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2536 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2537 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2538 }
2539
2540 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2541 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2542 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2543 }
2544
2545 for (i = 0; i < TEMP_COUNT; i++) {
2546 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2547 }
2548
2549 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2550 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2551 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2552 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2553 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2554
2555 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2556 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2557 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2558 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2559 }
2560 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2561
2562 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2563
2564 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2565 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2566 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2567 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2568
2569 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2570
2571 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2572
2573 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2574 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2575 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2576 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2577
2578 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2579 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2580
2581 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2582 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2583 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2584 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2585 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2586 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2587 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2588 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2589
2590 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2591 " .VoltageMode = 0x%02x\n"
2592 " .SnapToDiscrete = 0x%02x\n"
2593 " .NumDiscreteLevels = 0x%02x\n"
2594 " .padding = 0x%02x\n"
2595 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2596 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2597 " .SsFmin = 0x%04x\n"
2598 " .Padding_16 = 0x%04x\n",
2599 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2600 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2601 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2602 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2603 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2604 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2605 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2606 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2607 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2608 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2609 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2610
2611 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2612 " .VoltageMode = 0x%02x\n"
2613 " .SnapToDiscrete = 0x%02x\n"
2614 " .NumDiscreteLevels = 0x%02x\n"
2615 " .padding = 0x%02x\n"
2616 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2617 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2618 " .SsFmin = 0x%04x\n"
2619 " .Padding_16 = 0x%04x\n",
2620 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2621 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2622 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2623 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2624 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2625 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2626 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2627 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2628 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2629 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2630 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2631
2632 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2633 " .VoltageMode = 0x%02x\n"
2634 " .SnapToDiscrete = 0x%02x\n"
2635 " .NumDiscreteLevels = 0x%02x\n"
2636 " .padding = 0x%02x\n"
2637 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2638 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2639 " .SsFmin = 0x%04x\n"
2640 " .Padding_16 = 0x%04x\n",
2641 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2642 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2643 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2644 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2645 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2646 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2647 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2648 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2649 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2650 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2651 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2652
2653 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2654 " .VoltageMode = 0x%02x\n"
2655 " .SnapToDiscrete = 0x%02x\n"
2656 " .NumDiscreteLevels = 0x%02x\n"
2657 " .padding = 0x%02x\n"
2658 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2659 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2660 " .SsFmin = 0x%04x\n"
2661 " .Padding_16 = 0x%04x\n",
2662 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2663 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2664 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2665 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2666 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2667 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2668 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2669 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2670 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2671 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2672 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2673
2674 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2675 " .VoltageMode = 0x%02x\n"
2676 " .SnapToDiscrete = 0x%02x\n"
2677 " .NumDiscreteLevels = 0x%02x\n"
2678 " .padding = 0x%02x\n"
2679 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2680 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2681 " .SsFmin = 0x%04x\n"
2682 " .Padding_16 = 0x%04x\n",
2683 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2684 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2685 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2686 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2687 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2688 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2689 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2690 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2691 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2692 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2693 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2694
2695 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2696 " .VoltageMode = 0x%02x\n"
2697 " .SnapToDiscrete = 0x%02x\n"
2698 " .NumDiscreteLevels = 0x%02x\n"
2699 " .padding = 0x%02x\n"
2700 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2701 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2702 " .SsFmin = 0x%04x\n"
2703 " .Padding_16 = 0x%04x\n",
2704 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2705 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2706 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2707 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2708 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2709 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2710 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2711 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2712 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2713 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2714 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2715
2716 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2717 " .VoltageMode = 0x%02x\n"
2718 " .SnapToDiscrete = 0x%02x\n"
2719 " .NumDiscreteLevels = 0x%02x\n"
2720 " .padding = 0x%02x\n"
2721 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2722 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2723 " .SsFmin = 0x%04x\n"
2724 " .Padding_16 = 0x%04x\n",
2725 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2726 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2727 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2728 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2729 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2730 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2731 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2732 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2733 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2734 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2735 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2736
2737 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2738 " .VoltageMode = 0x%02x\n"
2739 " .SnapToDiscrete = 0x%02x\n"
2740 " .NumDiscreteLevels = 0x%02x\n"
2741 " .padding = 0x%02x\n"
2742 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2743 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2744 " .SsFmin = 0x%04x\n"
2745 " .Padding_16 = 0x%04x\n",
2746 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2747 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2748 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2749 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2750 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2751 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2752 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2753 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2754 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2755 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2756 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2757
2758 dev_info(smu->adev->dev, "FreqTableGfx\n");
2759 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2760 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2761
2762 dev_info(smu->adev->dev, "FreqTableVclk\n");
2763 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2764 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2765
2766 dev_info(smu->adev->dev, "FreqTableDclk\n");
2767 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2768 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2769
2770 dev_info(smu->adev->dev, "FreqTableSocclk\n");
2771 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2772 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2773
2774 dev_info(smu->adev->dev, "FreqTableUclk\n");
2775 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2776 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2777
2778 dev_info(smu->adev->dev, "FreqTableFclk\n");
2779 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2780 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2781
2782 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2783 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2784 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2785 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2786 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2787 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2788 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2789 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2790 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2791
2792 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2793 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2794 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2795
2796 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2797 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2798
2799 dev_info(smu->adev->dev, "Mp0clkFreq\n");
2800 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2801 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2802
2803 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2804 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2805 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2806
2807 dev_info(smu->adev->dev, "MemVddciVoltage\n");
2808 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2809 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2810
2811 dev_info(smu->adev->dev, "MemMvddVoltage\n");
2812 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2813 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2814
2815 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2816 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2817 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2818 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2819 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2820
2821 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2822
2823 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2824 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2825 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2826 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2827 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2828 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2829 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2830 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2831 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2832 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2833 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2834
2835 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2836 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2837 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2838 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2839 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2840 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2841
2842 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2843 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2844 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2845 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2846 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2847
2848 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2849 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2850 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2851
2852 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2853 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2854 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2855 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2856
2857 dev_info(smu->adev->dev, "UclkDpmPstates\n");
2858 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2859 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2860
2861 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2862 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2863 pptable->UclkDpmSrcFreqRange.Fmin);
2864 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2865 pptable->UclkDpmSrcFreqRange.Fmax);
2866 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2867 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2868 pptable->UclkDpmTargFreqRange.Fmin);
2869 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2870 pptable->UclkDpmTargFreqRange.Fmax);
2871 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2872 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2873
2874 dev_info(smu->adev->dev, "PcieGenSpeed\n");
2875 for (i = 0; i < NUM_LINK_LEVELS; i++)
2876 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2877
2878 dev_info(smu->adev->dev, "PcieLaneCount\n");
2879 for (i = 0; i < NUM_LINK_LEVELS; i++)
2880 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2881
2882 dev_info(smu->adev->dev, "LclkFreq\n");
2883 for (i = 0; i < NUM_LINK_LEVELS; i++)
2884 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2885
2886 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2887 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2888
2889 dev_info(smu->adev->dev, "FanGain\n");
2890 for (i = 0; i < TEMP_COUNT; i++)
2891 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2892
2893 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2894 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2895 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2896 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2897 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2898 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2899 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2900 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2901 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2902 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2903 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2904 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2905
2906 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2907 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2908 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2909 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2910
2911 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2912 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2913 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2914 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2915
2916 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2917 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2918 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2919 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2920 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2921 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2922 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2923 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2924 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2925 pptable->dBtcGbGfxPll.a,
2926 pptable->dBtcGbGfxPll.b,
2927 pptable->dBtcGbGfxPll.c);
2928 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2929 pptable->dBtcGbGfxDfll.a,
2930 pptable->dBtcGbGfxDfll.b,
2931 pptable->dBtcGbGfxDfll.c);
2932 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2933 pptable->dBtcGbSoc.a,
2934 pptable->dBtcGbSoc.b,
2935 pptable->dBtcGbSoc.c);
2936 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2937 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2938 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2939 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2940 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2941 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2942
2943 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2944 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2945 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
2946 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2947 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
2948 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2949 }
2950
2951 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2952 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2953 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2954 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2955 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2956 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2957 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2958 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2959
2960 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2961 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2962
2963 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2964 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2965 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2966 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2967
2968 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2969 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2970 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2971 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2972
2973 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2974 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2975
2976 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2977 for (i = 0; i < NUM_XGMI_LEVELS; i++)
2978 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2979 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2980 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2981
2982 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2983 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2984 pptable->ReservedEquation0.a,
2985 pptable->ReservedEquation0.b,
2986 pptable->ReservedEquation0.c);
2987 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2988 pptable->ReservedEquation1.a,
2989 pptable->ReservedEquation1.b,
2990 pptable->ReservedEquation1.c);
2991 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2992 pptable->ReservedEquation2.a,
2993 pptable->ReservedEquation2.b,
2994 pptable->ReservedEquation2.c);
2995 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2996 pptable->ReservedEquation3.a,
2997 pptable->ReservedEquation3.b,
2998 pptable->ReservedEquation3.c);
2999
3000 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3001 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3002 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3003 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3004 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3005 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3006 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3007 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
3008
3009 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3010 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3011 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3012 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3013 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3014 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
3015
3016 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
3017 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3018 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
3019 pptable->I2cControllers[i].Enabled);
3020 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
3021 pptable->I2cControllers[i].Speed);
3022 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
3023 pptable->I2cControllers[i].SlaveAddress);
3024 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
3025 pptable->I2cControllers[i].ControllerPort);
3026 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
3027 pptable->I2cControllers[i].ControllerName);
3028 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
3029 pptable->I2cControllers[i].ThermalThrotter);
3030 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
3031 pptable->I2cControllers[i].I2cProtocol);
3032 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
3033 pptable->I2cControllers[i].PaddingConfig);
3034 }
3035
3036 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3037 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3038 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3039 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3040
3041 dev_info(smu->adev->dev, "Board Parameters:\n");
3042 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3043 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3044 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3045 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3046 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3047 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3048 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3049 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3050
3051 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3052 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3053 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3054
3055 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3056 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3057 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3058
3059 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3060 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3061 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3062
3063 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3064 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3065 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3066
3067 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3068
3069 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3070 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3071 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3072 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3073 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3074 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3075 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3076 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3077 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3078 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3079 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3080 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3081 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3082 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3083 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3084 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3085
3086 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3087 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3088 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3089
3090 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3091 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3092 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3093
3094 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3095 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3096
3097 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3098 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3099 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3100
3101 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3102 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3103 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3104 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3105 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3106
3107 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3108 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3109
3110 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3111 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3112 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3113 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3114 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3115 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3116 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3117 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3118 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3119 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3120 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3121 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3122
3123 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3124 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3125 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3126 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3127
3128 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3129 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3130 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3131 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3132 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3133 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3134 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3135 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3136 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3137 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3138 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3139
3140 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3141 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3142 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3143 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3144 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3145 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3146 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3147 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3148}
3149
b455159c
LG		 3150static void sienna_cichlid_dump_pptable(struct smu_context *smu)
3151{
3152 struct smu_table_context *table_context = &smu->smu_table;
3153 PPTable_t *pptable = table_context->driver_pptable;
3154 int i;
3155
1d789535 3156 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) {
7077b19a
CG		 3157 beige_goby_dump_pptable(smu);
3158 return;
3159 }
3160
d9811cfc 3161 dev_info(smu->adev->dev, "Dumped PPTable:\n");
b455159c 3162
d9811cfc
EQ		 3163 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
3164 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
3165 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
b455159c
LG		 3166
3167 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
d9811cfc
EQ		 3168 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
3169 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
3170 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
3171 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
b455159c
LG		 3172 }
3173
3174 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
d9811cfc
EQ		 3175 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
3176 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
b455159c
LG		 3177 }
3178
3179 for (i = 0; i < TEMP_COUNT; i++) {
d9811cfc 3180 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
b455159c
LG		 3181 }
3182
d9811cfc
EQ		 3183 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
3184 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
3185 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
3186 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
3187 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
b455159c 3188
d9811cfc 3189 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
b455159c 3190 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
d9811cfc
EQ		 3191 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
3192 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
b455159c 3193 }
d9811cfc
EQ		 3194 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
3195
3196 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
3197
3198 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
3199 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
3200 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
3201 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
3202
3203 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
3204 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
3205
3206 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
3207 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
3208 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
3209 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
3210
3211 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
3212 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
3213 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
3214 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
3215
3216 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
3217 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
3218
3219 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
3220 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
3221 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
3222 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
3223 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
3224 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
3225 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
3226 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
3227
3228 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
b455159c
LG		 3229 " .VoltageMode = 0x%02x\n"
3230 " .SnapToDiscrete = 0x%02x\n"
3231 " .NumDiscreteLevels = 0x%02x\n"
3232 " .padding = 0x%02x\n"
3233 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3234 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3235 " .SsFmin = 0x%04x\n"
3236 " .Padding_16 = 0x%04x\n",
3237 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
3238 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
3239 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
3240 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
3241 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
3242 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
3243 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
3244 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
3245 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
3246 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
3247 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
3248
d9811cfc 3249 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
b455159c
LG		 3250 " .VoltageMode = 0x%02x\n"
3251 " .SnapToDiscrete = 0x%02x\n"
3252 " .NumDiscreteLevels = 0x%02x\n"
3253 " .padding = 0x%02x\n"
3254 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3255 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3256 " .SsFmin = 0x%04x\n"
3257 " .Padding_16 = 0x%04x\n",
3258 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
3259 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
3260 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
3261 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
3262 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
3263 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
3264 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
3265 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
3266 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
3267 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
3268 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
3269
d9811cfc 3270 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
b455159c
LG		 3271 " .VoltageMode = 0x%02x\n"
3272 " .SnapToDiscrete = 0x%02x\n"
3273 " .NumDiscreteLevels = 0x%02x\n"
3274 " .padding = 0x%02x\n"
3275 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3276 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3277 " .SsFmin = 0x%04x\n"
3278 " .Padding_16 = 0x%04x\n",
3279 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
3280 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
3281 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
3282 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
3283 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
3284 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
3285 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
3286 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
3287 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
3288 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
3289 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
3290
d9811cfc 3291 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
b455159c
LG		 3292 " .VoltageMode = 0x%02x\n"
3293 " .SnapToDiscrete = 0x%02x\n"
3294 " .NumDiscreteLevels = 0x%02x\n"
3295 " .padding = 0x%02x\n"
3296 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3297 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3298 " .SsFmin = 0x%04x\n"
3299 " .Padding_16 = 0x%04x\n",
3300 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
3301 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
3302 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
3303 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
3304 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
3305 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
3306 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
3307 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
3308 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
3309 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
3310 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
3311
d9811cfc 3312 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
b455159c
LG		 3313 " .VoltageMode = 0x%02x\n"
3314 " .SnapToDiscrete = 0x%02x\n"
3315 " .NumDiscreteLevels = 0x%02x\n"
3316 " .padding = 0x%02x\n"
3317 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3318 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3319 " .SsFmin = 0x%04x\n"
3320 " .Padding_16 = 0x%04x\n",
3321 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
3322 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
3323 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
3324 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
3325 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
3326 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
3327 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
3328 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
3329 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
3330 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
3331 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
3332
d9811cfc 3333 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
b455159c
LG		 3334 " .VoltageMode = 0x%02x\n"
3335 " .SnapToDiscrete = 0x%02x\n"
3336 " .NumDiscreteLevels = 0x%02x\n"
3337 " .padding = 0x%02x\n"
3338 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3339 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3340 " .SsFmin = 0x%04x\n"
3341 " .Padding_16 = 0x%04x\n",
3342 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
3343 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
3344 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
3345 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
3346 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
3347 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
3348 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
3349 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
3350 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
3351 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
3352 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
3353
d9811cfc 3354 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
b455159c
LG		 3355 " .VoltageMode = 0x%02x\n"
3356 " .SnapToDiscrete = 0x%02x\n"
3357 " .NumDiscreteLevels = 0x%02x\n"
3358 " .padding = 0x%02x\n"
3359 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3360 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3361 " .SsFmin = 0x%04x\n"
3362 " .Padding_16 = 0x%04x\n",
3363 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
3364 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
3365 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
3366 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
3367 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
3368 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
3369 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
3370 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
3371 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
3372 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
3373 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
3374
d9811cfc 3375 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
b455159c
LG		 3376 " .VoltageMode = 0x%02x\n"
3377 " .SnapToDiscrete = 0x%02x\n"
3378 " .NumDiscreteLevels = 0x%02x\n"
3379 " .padding = 0x%02x\n"
3380 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3381 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3382 " .SsFmin = 0x%04x\n"
3383 " .Padding_16 = 0x%04x\n",
3384 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
3385 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
3386 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
3387 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
3388 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
3389 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
3390 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
3391 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
3392 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
3393 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
3394 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
3395
d9811cfc 3396 dev_info(smu->adev->dev, "FreqTableGfx\n");
b455159c 3397 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
d9811cfc 3398 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
b455159c 3399
d9811cfc 3400 dev_info(smu->adev->dev, "FreqTableVclk\n");
b455159c 3401 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
d9811cfc 3402 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
b455159c 3403
d9811cfc 3404 dev_info(smu->adev->dev, "FreqTableDclk\n");
b455159c 3405 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
d9811cfc 3406 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
b455159c 3407
d9811cfc 3408 dev_info(smu->adev->dev, "FreqTableSocclk\n");
b455159c 3409 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
d9811cfc 3410 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
b455159c 3411
d9811cfc 3412 dev_info(smu->adev->dev, "FreqTableUclk\n");
b455159c 3413 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3414 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
b455159c 3415
d9811cfc 3416 dev_info(smu->adev->dev, "FreqTableFclk\n");
b455159c 3417 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
d9811cfc
EQ		 3418 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
3419
d9811cfc
EQ		 3420 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
3421 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
3422 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
3423 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
3424 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
3425 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
3426 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
3427 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
3428 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
3429
3430 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
b455159c 3431 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3432 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
b455159c 3433
d9811cfc
EQ		 3434 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
3435 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
b455159c 3436
d9811cfc 3437 dev_info(smu->adev->dev, "Mp0clkFreq\n");
b455159c 3438 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc 3439 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
b455159c 3440
d9811cfc 3441 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
b455159c 3442 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc 3443 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
b455159c 3444
d9811cfc 3445 dev_info(smu->adev->dev, "MemVddciVoltage\n");
b455159c 3446 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3447 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
b455159c 3448
d9811cfc 3449 dev_info(smu->adev->dev, "MemMvddVoltage\n");
b455159c 3450 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc
EQ		 3451 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
3452
3453 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
3454 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
3455 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
3456 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
3457 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
3458
3459 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
3460
3461 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
3462 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
3463 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
3464 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
3465 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
3466 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
3467 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
3468 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
3469 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
3470 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
3471 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
3472
3473 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
3474 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
3475 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
3476 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
3477 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
3478 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
3479
3480 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
3481 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
3482 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
3483 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
3484 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
3485
3486 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
b455159c 3487 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
d9811cfc 3488 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
b455159c 3489
d9811cfc
EQ		 3490 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
3491 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
3492 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
3493 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
b455159c 3494
d9811cfc 3495 dev_info(smu->adev->dev, "UclkDpmPstates\n");
b455159c 3496 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3497 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
b455159c 3498
d9811cfc
EQ		 3499 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
3500 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
b455159c 3501 pptable->UclkDpmSrcFreqRange.Fmin);
d9811cfc 3502 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
b455159c 3503 pptable->UclkDpmSrcFreqRange.Fmax);
d9811cfc
EQ		 3504 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
3505 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
b455159c 3506 pptable->UclkDpmTargFreqRange.Fmin);
d9811cfc 3507 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
b455159c 3508 pptable->UclkDpmTargFreqRange.Fmax);
d9811cfc
EQ		 3509 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
3510 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
b455159c 3511
d9811cfc 3512 dev_info(smu->adev->dev, "PcieGenSpeed\n");
b455159c 3513 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3514 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
b455159c 3515
d9811cfc 3516 dev_info(smu->adev->dev, "PcieLaneCount\n");
b455159c 3517 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3518 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
b455159c 3519
d9811cfc 3520 dev_info(smu->adev->dev, "LclkFreq\n");
b455159c 3521 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3522 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
b455159c 3523
d9811cfc
EQ		 3524 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
3525 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
b455159c 3526
d9811cfc 3527 dev_info(smu->adev->dev, "FanGain\n");
b455159c 3528 for (i = 0; i < TEMP_COUNT; i++)
d9811cfc
EQ		 3529 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
3530
3531 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
3532 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
3533 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
3534 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
3535 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
3536 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
3537 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
3538 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
3539 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
3540 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
3541 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
3542 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
3543
3544 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
3545 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
3546 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
3547 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
3548
3549 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
3550 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
3551 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
3552 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
3553
3554 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3555 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
3556 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
3557 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
d9811cfc 3558 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3559 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
3560 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
3561 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
d9811cfc 3562 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3563 pptable->dBtcGbGfxPll.a,
3564 pptable->dBtcGbGfxPll.b,
3565 pptable->dBtcGbGfxPll.c);
d9811cfc 3566 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3567 pptable->dBtcGbGfxDfll.a,
3568 pptable->dBtcGbGfxDfll.b,
3569 pptable->dBtcGbGfxDfll.c);
d9811cfc 3570 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3571 pptable->dBtcGbSoc.a,
3572 pptable->dBtcGbSoc.b,
3573 pptable->dBtcGbSoc.c);
d9811cfc 3574 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
b455159c
LG		 3575 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
3576 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
d9811cfc 3577 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
b455159c
LG		 3578 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
3579 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
3580
d9811cfc 3581 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
b455159c 3582 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
d9811cfc 3583 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
b455159c 3584 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
d9811cfc 3585 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
b455159c
LG		 3586 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
3587 }
3588
d9811cfc 3589 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3590 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
3591 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
3592 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
d9811cfc 3593 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3594 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
3595 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
3596 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
3597
d9811cfc
EQ		 3598 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
3599 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
b455159c 3600
d9811cfc
EQ		 3601 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
3602 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
3603 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
3604 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
b455159c 3605
d9811cfc
EQ		 3606 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
3607 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
3608 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
3609 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
b455159c 3610
d9811cfc
EQ		 3611 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
3612 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
b455159c 3613
d9811cfc 3614 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
b455159c 3615 for (i = 0; i < NUM_XGMI_LEVELS; i++)
d9811cfc
EQ		 3616 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
3617 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
3618 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
b455159c 3619
d9811cfc
EQ		 3620 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
3621 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3622 pptable->ReservedEquation0.a,
3623 pptable->ReservedEquation0.b,
3624 pptable->ReservedEquation0.c);
d9811cfc 3625 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3626 pptable->ReservedEquation1.a,
3627 pptable->ReservedEquation1.b,
3628 pptable->ReservedEquation1.c);
d9811cfc 3629 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3630 pptable->ReservedEquation2.a,
3631 pptable->ReservedEquation2.b,
3632 pptable->ReservedEquation2.c);
d9811cfc 3633 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3634 pptable->ReservedEquation3.a,
3635 pptable->ReservedEquation3.b,
3636 pptable->ReservedEquation3.c);
3637
d9811cfc
EQ		 3638 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3639 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3640 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3641 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3642 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3643 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3644 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3645 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
d9811cfc
EQ		 3646
3647 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3648 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3649 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3650 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3651 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3652 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
b455159c
LG		 3653
3654 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
d9811cfc
EQ		 3655 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3656 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
b455159c 3657 pptable->I2cControllers[i].Enabled);
d9811cfc 3658 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
b455159c 3659 pptable->I2cControllers[i].Speed);
d9811cfc 3660 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
b455159c 3661 pptable->I2cControllers[i].SlaveAddress);
d9811cfc 3662 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
b455159c 3663 pptable->I2cControllers[i].ControllerPort);
d9811cfc 3664 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
b455159c 3665 pptable->I2cControllers[i].ControllerName);
d9811cfc 3666 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
b455159c 3667 pptable->I2cControllers[i].ThermalThrotter);
d9811cfc 3668 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
b455159c 3669 pptable->I2cControllers[i].I2cProtocol);
d9811cfc 3670 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
b455159c
LG		 3671 pptable->I2cControllers[i].PaddingConfig);
3672 }
3673
d9811cfc
EQ		 3674 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3675 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3676 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3677 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3678
3679 dev_info(smu->adev->dev, "Board Parameters:\n");
3680 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3681 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3682 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3683 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3684 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3685 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3686 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3687 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3688
3689 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3690 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3691 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3692
3693 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3694 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3695 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3696
3697 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3698 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3699 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3700
3701 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3702 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3703 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3704
3705 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3706
3707 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3708 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3709 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3710 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3711 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3712 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3713 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3714 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3715 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3716 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3717 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3718 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3719 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3720 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3721 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3722 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3723
3724 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3725 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3726 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3727
3728 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3729 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3730 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3731
f0f3d68e 3732 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
d9811cfc
EQ		 3733 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3734
3735 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3736 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3737 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3738
3739 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3740 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3741 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3742 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3743 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3744
3745 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3746 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3747
3748 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
b455159c 3749 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3750 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3751 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
b455159c 3752 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3753 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3754 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
b455159c 3755 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3756 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3757 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
b455159c 3758 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3759 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3760
3761 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3762 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3763 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3764 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3765
3766 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3767 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3768 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3769 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3770 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3771 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3772 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3773 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3774 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3775 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3776 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
d9811cfc
EQ		 3777
3778 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3779 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3780 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3781 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3782 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3783 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3784 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3785 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
b455159c
LG		 3786}
3787
5125c96a 3788static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
ebe57d0c 3789 struct i2c_msg *msg, int num_msgs)
bc50ca29 3790{
2f60dd50
LT		 3791 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
3792 struct amdgpu_device *adev = smu_i2c->adev;
ebfc2533
EQ		 3793 struct smu_context *smu = adev->powerplay.pp_handle;
3794 struct smu_table_context *smu_table = &smu->smu_table;
bc50ca29 3795 struct smu_table *table = &smu_table->driver_table;
5125c96a 3796 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
ebe57d0c
LT		 3797 int i, j, r, c;
3798 u16 dir;
d74a09c8 3799
e281d594
AD		 3800 if (!adev->pm.dpm_enabled)
3801 return -EBUSY;
3802
5125c96a
AD		 3803 req = kzalloc(sizeof(*req), GFP_KERNEL);
3804 if (!req)
3805 return -ENOMEM;
bc50ca29 3806
2f60dd50 3807 req->I2CcontrollerPort = smu_i2c->port;
5125c96a 3808 req->I2CSpeed = I2C_SPEED_FAST_400K;
ebe57d0c
LT		 3809 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
3810 dir = msg[0].flags & I2C_M_RD;
bc50ca29 3811
ebe57d0c
LT		 3812 for (c = i = 0; i < num_msgs; i++) {
3813 for (j = 0; j < msg[i].len; j++, c++) {
3814 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
bc50ca29 3815
5125c96a
AD		 3816 if (!(msg[i].flags & I2C_M_RD)) {
3817 /* write */
3818 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
ebe57d0c
LT		 3819 cmd->ReadWriteData = msg[i].buf[j];
3820 }
3821
3822 if ((dir ^ msg[i].flags) & I2C_M_RD) {
3823 /* The direction changes.
3824 */
3825 dir = msg[i].flags & I2C_M_RD;
3826 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
5125c96a 3827 }
14df5650 3828
ebe57d0c
LT		 3829 req->NumCmds++;
3830
14df5650
AG		 3831 /*
3832 * Insert STOP if we are at the last byte of either last
3833 * message for the transaction or the client explicitly
3834 * requires a STOP at this particular message.
3835 */
ebe57d0c
LT		 3836 if ((j == msg[i].len - 1) &&
3837 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
3838 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
5125c96a 3839 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
ebe57d0c 3840 }
5125c96a 3841 }
d74a09c8 3842 }
e0638c7a 3843 mutex_lock(&adev->pm.mutex);
ebfc2533 3844 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
5125c96a
AD		 3845 if (r)
3846 goto fail;
bc50ca29 3847
ebe57d0c
LT		 3848 for (c = i = 0; i < num_msgs; i++) {
3849 if (!(msg[i].flags & I2C_M_RD)) {
3850 c += msg[i].len;
3851 continue;
3852 }
3853 for (j = 0; j < msg[i].len; j++, c++) {
3854 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
bc50ca29 3855
ebe57d0c 3856 msg[i].buf[j] = cmd->ReadWriteData;
bc50ca29
AD		 3857 }
3858 }
ebe57d0c 3859 r = num_msgs;
bc50ca29 3860fail:
62b73bd5 3861 mutex_unlock(&adev->pm.mutex);
5125c96a 3862 kfree(req);
5125c96a 3863 return r;
bc50ca29
AD		 3864}
3865
3866static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
3867{
3868 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3869}
3870
3871
3872static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
3873 .master_xfer = sienna_cichlid_i2c_xfer,
3874 .functionality = sienna_cichlid_i2c_func,
3875};
3876
35ed2703 3877static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = {
c0838d3a 3878 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
16736627 3879 .max_read_len = MAX_SW_I2C_COMMANDS,
35ed2703 3880 .max_write_len = MAX_SW_I2C_COMMANDS,
16736627
LT		 3881 .max_comb_1st_msg_len = 2,
3882 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
35ed2703
AG		 3883};
3884
2f60dd50 3885static int sienna_cichlid_i2c_control_init(struct smu_context *smu)
bc50ca29 3886{
2f60dd50
LT		 3887 struct amdgpu_device *adev = smu->adev;
3888 int res, i;
3889
3890 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3891 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3892 struct i2c_adapter *control = &smu_i2c->adapter;
3893
3894 smu_i2c->adev = adev;
3895 smu_i2c->port = i;
3896 mutex_init(&smu_i2c->mutex);
3897 control->owner = THIS_MODULE;
3898 control->class = I2C_CLASS_HWMON;
3899 control->dev.parent = &adev->pdev->dev;
3900 control->algo = &sienna_cichlid_i2c_algo;
3901 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
3902 control->quirks = &sienna_cichlid_i2c_control_quirks;
3903 i2c_set_adapdata(control, smu_i2c);
3904
3905 res = i2c_add_adapter(control);
3906 if (res) {
3907 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3908 goto Out_err;
3909 }
3910 }
3911 /* assign the buses used for the FRU EEPROM and RAS EEPROM */
3912 /* XXX ideally this would be something in a vbios data table */
3913 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
3914 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
bc50ca29 3915
2f60dd50
LT		 3916 return 0;
3917Out_err:
3918 for ( ; i >= 0; i--) {
3919 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3920 struct i2c_adapter *control = &smu_i2c->adapter;
bc50ca29 3921
2f60dd50
LT		 3922 i2c_del_adapter(control);
3923 }
bc50ca29
AD		 3924 return res;
3925}
3926
2f60dd50 3927static void sienna_cichlid_i2c_control_fini(struct smu_context *smu)
bc50ca29 3928{
2f60dd50
LT		 3929 struct amdgpu_device *adev = smu->adev;
3930 int i;
3931
3932 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3933 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3934 struct i2c_adapter *control = &smu_i2c->adapter;
3935
3936 i2c_del_adapter(control);
3937 }
3938 adev->pm.ras_eeprom_i2c_bus = NULL;
3939 adev->pm.fru_eeprom_i2c_bus = NULL;
bc50ca29
AD		 3940}
3941
8ca78a0a
EQ		 3942static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
3943 void **table)
3944{
3945 struct smu_table_context *smu_table = &smu->smu_table;
f06d9511
GS		 3946 struct gpu_metrics_v1_3 *gpu_metrics =
3947 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
b4b0b79d
EQ		 3948 SmuMetricsExternal_t metrics_external;
3949 SmuMetrics_t *metrics =
3950 &(metrics_external.SmuMetrics);
be22e2b9
EQ		 3951 SmuMetrics_V2_t *metrics_v2 =
3952 &(metrics_external.SmuMetrics_V2);
7952fa0d
DS		 3953 SmuMetrics_V3_t *metrics_v3 =
3954 &(metrics_external.SmuMetrics_V3);
c524c1c9 3955 struct amdgpu_device *adev = smu->adev;
7952fa0d
DS		 3956 bool use_metrics_v2 = false;
3957 bool use_metrics_v3 = false;
be22e2b9 3958 uint16_t average_gfx_activity;
8ca78a0a
EQ		 3959 int ret = 0;
3960
396beb91
EQ		 3961 switch (smu->adev->ip_versions[MP1_HWIP][0]) {
3962 case IP_VERSION(11, 0, 7):
3963 if (smu->smc_fw_version >= 0x3A4900)
3964 use_metrics_v3 = true;
3965 else if (smu->smc_fw_version >= 0x3A4300)
3966 use_metrics_v2 = true;
3967 break;
3968 case IP_VERSION(11, 0, 11):
3969 if (smu->smc_fw_version >= 0x412D00)
3970 use_metrics_v2 = true;
3971 break;
3972 case IP_VERSION(11, 0, 12):
3973 if (smu->smc_fw_version >= 0x3B2300)
3974 use_metrics_v2 = true;
3975 break;
3976 case IP_VERSION(11, 0, 13):
3977 if (smu->smc_fw_version >= 0x491100)
3978 use_metrics_v2 = true;
3979 break;
3980 default:
3981 break;
3982 }
7952fa0d 3983
da11407f
EQ		 3984 ret = smu_cmn_get_metrics_table(smu,
3985 &metrics_external,
3986 true);
3987 if (ret)
8ca78a0a 3988 return ret;
8ca78a0a 3989
f06d9511 3990 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
8ca78a0a 3991
7952fa0d 3992 gpu_metrics->temperature_edge = use_metrics_v3 ? metrics_v3->TemperatureEdge :
be22e2b9 3993 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge;
7952fa0d 3994 gpu_metrics->temperature_hotspot = use_metrics_v3 ? metrics_v3->TemperatureHotspot :
be22e2b9 3995 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot;
7952fa0d 3996 gpu_metrics->temperature_mem = use_metrics_v3 ? metrics_v3->TemperatureMem :
be22e2b9 3997 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem;
7952fa0d 3998 gpu_metrics->temperature_vrgfx = use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
be22e2b9 3999 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx;
7952fa0d 4000 gpu_metrics->temperature_vrsoc = use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
be22e2b9 4001 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc;
7952fa0d 4002 gpu_metrics->temperature_vrmem = use_metrics_v3 ? metrics_v3->TemperatureVrMem0 :
be22e2b9
EQ		 4003 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0;
4004
7952fa0d 4005 gpu_metrics->average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
be22e2b9 4006 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
7952fa0d 4007 gpu_metrics->average_umc_activity = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
be22e2b9 4008 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity;
7952fa0d
DS		 4009 gpu_metrics->average_mm_activity = use_metrics_v3 ?
4010 (metrics_v3->VcnUsagePercentage0 + metrics_v3->VcnUsagePercentage1) / 2 :
be22e2b9
EQ		 4011 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage;
4012
7952fa0d 4013 gpu_metrics->average_socket_power = use_metrics_v3 ? metrics_v3->AverageSocketPower :
be22e2b9 4014 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower;
7952fa0d 4015 gpu_metrics->energy_accumulator = use_metrics_v3 ? metrics_v3->EnergyAccumulator :
be22e2b9
EQ		 4016 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator;
4017
3a50403f
SK		 4018 if (metrics->CurrGfxVoltageOffset)
4019 gpu_metrics->voltage_gfx =
4020 (155000 - 625 * metrics->CurrGfxVoltageOffset) / 100;
4021 if (metrics->CurrMemVidOffset)
4022 gpu_metrics->voltage_mem =
4023 (155000 - 625 * metrics->CurrMemVidOffset) / 100;
4024 if (metrics->CurrSocVoltageOffset)
4025 gpu_metrics->voltage_soc =
4026 (155000 - 625 * metrics->CurrSocVoltageOffset) / 100;
4027
7952fa0d
DS		 4028 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
4029 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
be22e2b9
EQ		 4030 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
4031 gpu_metrics->average_gfxclk_frequency =
7952fa0d
DS		 4032 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
4033 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
4034 metrics->AverageGfxclkFrequencyPostDs;
8ca78a0a 4035 else
be22e2b9 4036 gpu_metrics->average_gfxclk_frequency =
7952fa0d
DS		 4037 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
4038 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
4039 metrics->AverageGfxclkFrequencyPreDs;
4040
be22e2b9 4041 gpu_metrics->average_uclk_frequency =
7952fa0d
DS		 4042 use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
4043 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
4044 metrics->AverageUclkFrequencyPostDs;
4045 gpu_metrics->average_vclk0_frequency = use_metrics_v3 ? metrics_v3->AverageVclk0Frequency :
be22e2b9 4046 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency;
7952fa0d 4047 gpu_metrics->average_dclk0_frequency = use_metrics_v3 ? metrics_v3->AverageDclk0Frequency :
be22e2b9 4048 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency;
7952fa0d 4049 gpu_metrics->average_vclk1_frequency = use_metrics_v3 ? metrics_v3->AverageVclk1Frequency :
be22e2b9 4050 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency;
7952fa0d 4051 gpu_metrics->average_dclk1_frequency = use_metrics_v3 ? metrics_v3->AverageDclk1Frequency :
be22e2b9
EQ		 4052 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency;
4053
7952fa0d 4054 gpu_metrics->current_gfxclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
be22e2b9 4055 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK];
7952fa0d 4056 gpu_metrics->current_socclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
be22e2b9 4057 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK];
7952fa0d 4058 gpu_metrics->current_uclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
be22e2b9 4059 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK];
7952fa0d 4060 gpu_metrics->current_vclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
be22e2b9 4061 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0];
7952fa0d 4062 gpu_metrics->current_dclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
be22e2b9 4063 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0];
7952fa0d 4064 gpu_metrics->current_vclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
be22e2b9 4065 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1];
7952fa0d 4066 gpu_metrics->current_dclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
be22e2b9
EQ		 4067 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1];
4068
4069 gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu);
f06d9511 4070 gpu_metrics->indep_throttle_status =
be22e2b9 4071 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
f06d9511 4072 sienna_cichlid_throttler_map);
b4b0b79d 4073
7952fa0d
DS		 4074 gpu_metrics->current_fan_speed = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
4075 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
c524c1c9 4076
1d789535
AD		 4077 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) ||
4078 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) {
7952fa0d
DS		 4079 gpu_metrics->pcie_link_width = use_metrics_v3 ? metrics_v3->PcieWidth :
4080 use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
4081 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v3 ? metrics_v3->PcieRate :
4082 use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
c524c1c9
EQ		 4083 } else {
4084 gpu_metrics->pcie_link_width =
4085 smu_v11_0_get_current_pcie_link_width(smu);
4086 gpu_metrics->pcie_link_speed =
4087 smu_v11_0_get_current_pcie_link_speed(smu);
4088 }
8ca78a0a 4089
de4b7cd8
KW		 4090 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
4091
8ca78a0a
EQ		 4092 *table = (void *)gpu_metrics;
4093
f06d9511 4094 return sizeof(struct gpu_metrics_v1_3);
8ca78a0a 4095}
bc50ca29 4096
3ddd0c90 4097static int sienna_cichlid_check_ecc_table_support(struct smu_context *smu)
4098{
4099 uint32_t if_version = 0xff, smu_version = 0xff;
4100 int ret = 0;
4101
4102 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
4103 if (ret)
4104 return -EOPNOTSUPP;
4105
4106 if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION)
4107 ret = -EOPNOTSUPP;
4108
4109 return ret;
4110}
4111
4112static ssize_t sienna_cichlid_get_ecc_info(struct smu_context *smu,
4113 void *table)
4114{
4115 struct smu_table_context *smu_table = &smu->smu_table;
4116 EccInfoTable_t *ecc_table = NULL;
4117 struct ecc_info_per_ch *ecc_info_per_channel = NULL;
4118 int i, ret = 0;
4119 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
4120
4121 ret = sienna_cichlid_check_ecc_table_support(smu);
4122 if (ret)
4123 return ret;
4124
4125 ret = smu_cmn_update_table(smu,
4126 SMU_TABLE_ECCINFO,
4127 0,
4128 smu_table->ecc_table,
4129 false);
4130 if (ret) {
4131 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n");
4132 return ret;
4133 }
4134
4135 ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
4136
4137 for (i = 0; i < SIENNA_CICHLID_UMC_CHANNEL_NUM; i++) {
4138 ecc_info_per_channel = &(eccinfo->ecc[i]);
4139 ecc_info_per_channel->ce_count_lo_chip =
4140 ecc_table->EccInfo[i].ce_count_lo_chip;
4141 ecc_info_per_channel->ce_count_hi_chip =
4142 ecc_table->EccInfo[i].ce_count_hi_chip;
4143 ecc_info_per_channel->mca_umc_status =
4144 ecc_table->EccInfo[i].mca_umc_status;
4145 ecc_info_per_channel->mca_umc_addr =
4146 ecc_table->EccInfo[i].mca_umc_addr;
4147 }
4148
4149 return ret;
4150}
05f39286
EQ		 4151static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
4152{
f4e2a66d 4153 uint16_t *mgpu_fan_boost_limit_rpm;
b804a75d 4154
f4e2a66d 4155 GET_PPTABLE_MEMBER(MGpuFanBoostLimitRpm, &mgpu_fan_boost_limit_rpm);
b804a75d
EQ		 4156 /*
4157 * Skip the MGpuFanBoost setting for those ASICs
4158 * which do not support it
4159 */
f4e2a66d 4160 if (*mgpu_fan_boost_limit_rpm == 0)
b804a75d
EQ		 4161 return 0;
4162
05f39286
EQ		 4163 return smu_cmn_send_smc_msg_with_param(smu,
4164 SMU_MSG_SetMGpuFanBoostLimitRpm,
4165 0,
4166 NULL);
4167}
4168
76c71f00
EQ		 4169static int sienna_cichlid_gpo_control(struct smu_context *smu,
4170 bool enablement)
4171{
ac7804bb 4172 uint32_t smu_version;
76c71f00
EQ		 4173 int ret = 0;
4174
ac7804bb 4175
7ade3ca9 4176 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
ac7804bb
EQ		 4177 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
4178 if (ret)
4179 return ret;
4180
4181 if (enablement) {
4182 if (smu_version < 0x003a2500) {
4183 ret = smu_cmn_send_smc_msg_with_param(smu,
4184 SMU_MSG_SetGpoFeaturePMask,
4185 GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
4186 NULL);
4187 } else {
4188 ret = smu_cmn_send_smc_msg_with_param(smu,
4189 SMU_MSG_DisallowGpo,
4190 0,
4191 NULL);
4192 }
4193 } else {
4194 if (smu_version < 0x003a2500) {
4195 ret = smu_cmn_send_smc_msg_with_param(smu,
4196 SMU_MSG_SetGpoFeaturePMask,
4197 0,
4198 NULL);
4199 } else {
4200 ret = smu_cmn_send_smc_msg_with_param(smu,
4201 SMU_MSG_DisallowGpo,
4202 1,
4203 NULL);
4204 }
4205 }
76c71f00
EQ		 4206 }
4207
4208 return ret;
4209}
d7f52e29
EQ		 4210
4211static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
4212{
4213 uint32_t smu_version;
4214 int ret = 0;
4215
4216 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
4217 if (ret)
4218 return ret;
4219
4220 /*
4221 * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
4222 * onwards PMFWs.
4223 */
4224 if (smu_version < 0x003A2D00)
4225 return 0;
4226
4227 return smu_cmn_send_smc_msg_with_param(smu,
4228 SMU_MSG_Enable2ndUSB20Port,
4229 smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
4230 1 : 0,
4231 NULL);
4232}
4233
4234static int sienna_cichlid_system_features_control(struct smu_context *smu,
4235 bool en)
4236{
4237 int ret = 0;
4238
4239 if (en) {
4240 ret = sienna_cichlid_notify_2nd_usb20_port(smu);
4241 if (ret)
4242 return ret;
4243 }
4244
4245 return smu_v11_0_system_features_control(smu, en);
4246}
4247
1689fca0
EQ		 4248static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
4249 enum pp_mp1_state mp1_state)
4250{
9113a0fb
GC		 4251 int ret;
4252
1689fca0
EQ		 4253 switch (mp1_state) {
4254 case PP_MP1_STATE_UNLOAD:
9113a0fb
GC		 4255 ret = smu_cmn_set_mp1_state(smu, mp1_state);
4256 break;
1689fca0 4257 default:
9113a0fb
GC		 4258 /* Ignore others */
4259 ret = 0;
1689fca0
EQ		 4260 }
4261
9113a0fb 4262 return ret;
1689fca0
EQ		 4263}
4264
db5b5c67
AG		 4265static void sienna_cichlid_stb_init(struct smu_context *smu)
4266{
4267 struct amdgpu_device *adev = smu->adev;
4268 uint32_t reg;
4269
4270 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START);
4271 smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE);
4272
4273 /* STB is disabled */
4274 if (!smu->stb_context.enabled)
4275 return;
4276
4277 spin_lock_init(&smu->stb_context.lock);
4278
4279 /* STB buffer size in bytes as function of FIFO depth */
4280 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO);
4281 smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH);
4282 smu->stb_context.stb_buf_size *= SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES;
4283
4284 dev_info(smu->adev->dev, "STB initialized to %d entries",
4285 smu->stb_context.stb_buf_size / SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES);
4286
4287}
4288
c85bf88b
EQ		 4289static int sienna_cichlid_get_default_config_table_settings(struct smu_context *smu,
4290 struct config_table_setting *table)
4291{
4292 struct amdgpu_device *adev = smu->adev;
4293
4294 if (!table)
4295 return -EINVAL;
4296
4297 table->gfxclk_average_tau = 10;
4298 table->socclk_average_tau = 10;
4299 table->fclk_average_tau = 10;
4300 table->uclk_average_tau = 10;
4301 table->gfx_activity_average_tau = 10;
4302 table->mem_activity_average_tau = 10;
4303 table->socket_power_average_tau = 100;
ab9d97d6 4304 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7))
c85bf88b
EQ		 4305 table->apu_socket_power_average_tau = 100;
4306
4307 return 0;
4308}
4309
4310static int sienna_cichlid_set_config_table(struct smu_context *smu,
4311 struct config_table_setting *table)
4312{
4313 DriverSmuConfigExternal_t driver_smu_config_table;
4314
4315 if (!table)
4316 return -EINVAL;
4317
4318 memset(&driver_smu_config_table,
4319 0,
4320 sizeof(driver_smu_config_table));
4321 driver_smu_config_table.DriverSmuConfig.GfxclkAverageLpfTau =
4322 table->gfxclk_average_tau;
4323 driver_smu_config_table.DriverSmuConfig.FclkAverageLpfTau =
4324 table->fclk_average_tau;
4325 driver_smu_config_table.DriverSmuConfig.UclkAverageLpfTau =
4326 table->uclk_average_tau;
4327 driver_smu_config_table.DriverSmuConfig.GfxActivityLpfTau =
4328 table->gfx_activity_average_tau;
4329 driver_smu_config_table.DriverSmuConfig.UclkActivityLpfTau =
4330 table->mem_activity_average_tau;
4331 driver_smu_config_table.DriverSmuConfig.SocketPowerLpfTau =
4332 table->socket_power_average_tau;
4333
4334 return smu_cmn_update_table(smu,
4335 SMU_TABLE_DRIVER_SMU_CONFIG,
4336 0,
4337 (void *)&driver_smu_config_table,
4338 true);
4339}
4340
6a8cf634
AD		 4341static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu,
4342 void *buf,
4343 uint32_t size)
db5b5c67
AG		 4344{
4345 uint32_t *p = buf;
4346 struct amdgpu_device *adev = smu->adev;
4347
4348 /* No need to disable interrupts for now as we don't lock it yet from ISR */
4349 spin_lock(&smu->stb_context.lock);
4350
4351 /*
4352 * Read the STB FIFO in units of 32bit since this is the accessor window
4353 * (register width) we have.
4354 */
4355 buf = ((char *) buf) + size;
4356 while ((void *)p < buf)
4357 *p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3));
4358
4359 spin_unlock(&smu->stb_context.lock);
4360
4361 return 0;
4362}
4363
672c0218
VZ		 4364static bool sienna_cichlid_is_mode2_reset_supported(struct smu_context *smu)
4365{
4366 return true;
4367}
4368
4369static int sienna_cichlid_mode2_reset(struct smu_context *smu)
4370{
4371 u32 smu_version;
4372 int ret = 0, index;
4373 struct amdgpu_device *adev = smu->adev;
4374 int timeout = 100;
4375
4376 smu_cmn_get_smc_version(smu, NULL, &smu_version);
4377
4378 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
4379 SMU_MSG_DriverMode2Reset);
4380
4381 mutex_lock(&smu->message_lock);
4382
4383 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index,
4384 SMU_RESET_MODE_2);
4385
4386 ret = smu_cmn_wait_for_response(smu);
4387 while (ret != 0 && timeout) {
4388 ret = smu_cmn_wait_for_response(smu);
4389 /* Wait a bit more time for getting ACK */
4390 if (ret != 0) {
4391 --timeout;
4392 usleep_range(500, 1000);
4393 continue;
4394 } else {
4395 break;
4396 }
4397 }
4398
4399 if (!timeout) {
4400 dev_err(adev->dev,
4401 "failed to send mode2 message \tparam: 0x%08x response %#x\n",
4402 SMU_RESET_MODE_2, ret);
4403 goto out;
4404 }
4405
4406 dev_info(smu->adev->dev, "restore config space...\n");
4407 /* Restore the config space saved during init */
4408 amdgpu_device_load_pci_state(adev->pdev);
4409out:
4410 mutex_unlock(&smu->message_lock);
4411
4412 return ret;
4413}
4414
b455159c 4415static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
b455159c
LG		 4416 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
4417 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
f6b4b4a1 4418 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
6fb176a7 4419 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
bc50ca29
AD		 4420 .i2c_init = sienna_cichlid_i2c_control_init,
4421 .i2c_fini = sienna_cichlid_i2c_control_fini,
b455159c
LG		 4422 .print_clk_levels = sienna_cichlid_print_clk_levels,
4423 .force_clk_levels = sienna_cichlid_force_clk_levels,
4424 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
b455159c
LG		 4425 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
4426 .display_config_changed = sienna_cichlid_display_config_changed,
4427 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
b455159c 4428 .is_dpm_running = sienna_cichlid_is_dpm_running,
0d8318e1 4429 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
d9ca7567 4430 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
b455159c
LG		 4431 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
4432 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
b455159c
LG		 4433 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
4434 .read_sensor = sienna_cichlid_read_sensor,
4435 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
b2785e25 4436 .set_performance_level = smu_v11_0_set_performance_level,
b455159c
LG		 4437 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
4438 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
4439 .get_power_limit = sienna_cichlid_get_power_limit,
08ccfe08 4440 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
b455159c
LG		 4441 .dump_pptable = sienna_cichlid_dump_pptable,
4442 .init_microcode = smu_v11_0_init_microcode,
4443 .load_microcode = smu_v11_0_load_microcode,
0a2d922a 4444 .fini_microcode = smu_v11_0_fini_microcode,
c1b353b7 4445 .init_smc_tables = sienna_cichlid_init_smc_tables,
b455159c
LG		 4446 .fini_smc_tables = smu_v11_0_fini_smc_tables,
4447 .init_power = smu_v11_0_init_power,
4448 .fini_power = smu_v11_0_fini_power,
4449 .check_fw_status = smu_v11_0_check_fw_status,
4a13b4ce 4450 .setup_pptable = sienna_cichlid_setup_pptable,
b455159c 4451 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
b455159c 4452 .check_fw_version = smu_v11_0_check_fw_version,
caad2613 4453 .write_pptable = smu_cmn_write_pptable,
b455159c
LG		 4454 .set_driver_table_location = smu_v11_0_set_driver_table_location,
4455 .set_tool_table_location = smu_v11_0_set_tool_table_location,
4456 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
d7f52e29 4457 .system_features_control = sienna_cichlid_system_features_control,
66c86828
EQ		 4458 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
4459 .send_smc_msg = smu_cmn_send_smc_msg,
31157341 4460 .init_display_count = NULL,
b455159c 4461 .set_allowed_mask = smu_v11_0_set_allowed_mask,
28251d72 4462 .get_enabled_mask = smu_cmn_get_enabled_mask,
b4bb3aaf 4463 .feature_is_enabled = smu_cmn_feature_is_enabled,
af5ba6d2 4464 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
31157341 4465 .notify_display_change = NULL,
b455159c 4466 .set_power_limit = smu_v11_0_set_power_limit,
b455159c
LG		 4467 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
4468 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
4469 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
ce63d8f8 4470 .set_min_dcef_deep_sleep = NULL,
b455159c
LG		 4471 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
4472 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
4473 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
0d8318e1 4474 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
f3289d04 4475 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
b455159c
LG		 4476 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
4477 .gfx_off_control = smu_v11_0_gfx_off_control,
4478 .register_irq_handler = smu_v11_0_register_irq_handler,
4479 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
4480 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
9fd4781b 4481 .baco_is_support = smu_v11_0_baco_is_support,
b455159c
LG		 4482 .baco_get_state = smu_v11_0_baco_get_state,
4483 .baco_set_state = smu_v11_0_baco_set_state,
13d75ead
EQ		 4484 .baco_enter = sienna_cichlid_baco_enter,
4485 .baco_exit = sienna_cichlid_baco_exit,
ea8139d8
WS		 4486 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
4487 .mode1_reset = smu_v11_0_mode1_reset,
258d290c 4488 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
10e96d89 4489 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
aa75fa34 4490 .set_default_od_settings = sienna_cichlid_set_default_od_settings,
37a58f69 4491 .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
49017304 4492 .restore_user_od_settings = sienna_cichlid_restore_user_od_settings,
66b8a9c0 4493 .run_btc = sienna_cichlid_run_btc,
18a4b3de 4494 .set_power_source = smu_v11_0_set_power_source,
7dbf7805
EQ		 4495 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
4496 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
8ca78a0a 4497 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
05f39286 4498 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
e988026f 4499 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
5ce99853 4500 .deep_sleep_control = smu_v11_0_deep_sleep_control,
3204ff3e 4501 .get_fan_parameters = sienna_cichlid_get_fan_parameters,
234676d6 4502 .interrupt_work = smu_v11_0_interrupt_work,
76c71f00 4503 .gpo_control = sienna_cichlid_gpo_control,
1689fca0 4504 .set_mp1_state = sienna_cichlid_set_mp1_state,
db5b5c67 4505 .stb_collect_info = sienna_cichlid_stb_get_data_direct,
3ddd0c90 4506 .get_ecc_info = sienna_cichlid_get_ecc_info,
c85bf88b
EQ		 4507 .get_default_config_table_settings = sienna_cichlid_get_default_config_table_settings,
4508 .set_config_table = sienna_cichlid_set_config_table,
ebd9c071 4509 .get_unique_id = sienna_cichlid_get_unique_id,
672c0218
VZ		 4510 .mode2_reset_is_support = sienna_cichlid_is_mode2_reset_supported,
4511 .mode2_reset = sienna_cichlid_mode2_reset,
b455159c
LG		 4512};
4513
4514void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
4515{
4516 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
6c339f37
EQ		 4517 smu->message_map = sienna_cichlid_message_map;
4518 smu->clock_map = sienna_cichlid_clk_map;
4519 smu->feature_map = sienna_cichlid_feature_mask_map;
4520 smu->table_map = sienna_cichlid_table_map;
4521 smu->pwr_src_map = sienna_cichlid_pwr_src_map;
4522 smu->workload_map = sienna_cichlid_workload_map;
da1db031 4523 smu_v11_0_set_smu_mailbox_registers(smu);
b455159c 4524}
Linux 6.x block layer and io_uring tree(s)