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drm/amdgpu/gmc10: remove dummy read workaround for newer chips
[linux-block.git] / drivers / gpu / drm / amd / pm / swsmu / smu11 / sienna_cichlid_ppt.c
CommitLineData
b455159c
LG		 1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
d8e0b16d
EQ		 24#define SWSMU_CODE_LAYER_L2
25
b455159c
LG		 26#include <linux/firmware.h>
27#include <linux/pci.h>
bc50ca29 28#include <linux/i2c.h>
b455159c
LG		 29#include "amdgpu.h"
30#include "amdgpu_smu.h"
b455159c
LG		 31#include "atomfirmware.h"
32#include "amdgpu_atomfirmware.h"
22f2447c 33#include "amdgpu_atombios.h"
b455159c
LG		 34#include "smu_v11_0.h"
35#include "smu11_driver_if_sienna_cichlid.h"
36#include "soc15_common.h"
37#include "atom.h"
38#include "sienna_cichlid_ppt.h"
e05acd78 39#include "smu_v11_0_7_pptable.h"
b455159c 40#include "smu_v11_0_7_ppsmc.h"
40d3b8db 41#include "nbio/nbio_2_3_offset.h"
b7d25b5f 42#include "nbio/nbio_2_3_sh_mask.h"
e05acd78
LG		 43#include "thm/thm_11_0_2_offset.h"
44#include "thm/thm_11_0_2_sh_mask.h"
ea8139d8
WS		 45#include "mp/mp_11_0_offset.h"
46#include "mp/mp_11_0_sh_mask.h"
b455159c 47
6c339f37
EQ		 48#include "asic_reg/mp/mp_11_0_sh_mask.h"
49#include "smu_cmn.h"
50
55084d7f
EQ		 51/*
52 * DO NOT use these for err/warn/info/debug messages.
53 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
54 * They are more MGPU friendly.
55 */
56#undef pr_err
57#undef pr_warn
58#undef pr_info
59#undef pr_debug
60
bc50ca29
AD		 61#define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
62
b455159c
LG		 63#define FEATURE_MASK(feature) (1ULL << feature)
64#define SMC_DPM_FEATURE ( \
65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
fea905d4 66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65297d50 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
5cb74353 68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
4cd4f45b 69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
5f338f70 70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
ce7e5a6e
JC		 71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \
72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
b455159c 73
d817f375
LG		 74#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
75
6c339f37
EQ		 76static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
77 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
78 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
79 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
91190db1
LG		 80 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
81 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
82 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
83 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
6c339f37
EQ		 84 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
85 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
86 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
87 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
88 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
89 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
90 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
91190db1
LG		 91 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
92 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0),
93 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0),
94 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
95 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
96 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0),
97 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
98 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
66b8a9c0 99 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
91190db1
LG		 100 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
101 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
102 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0),
6c339f37 103 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
91190db1 104 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
6c339f37
EQ		 105 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
106 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
107 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
91190db1
LG		 108 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
109 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
110 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
111 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
112 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
113 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
114 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
115 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
6c339f37 116 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
91190db1
LG		 117 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
118 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
119 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
6c339f37 120 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
91190db1
LG		 121 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
122 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
123 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
124 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
125 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
126 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
127 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
128 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
05f39286 129 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
76c71f00 130 MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0),
b455159c
LG		 131};
132
6c339f37 133static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
b455159c
LG		 134 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
135 CLK_MAP(SCLK, PPCLK_GFXCLK),
136 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
137 CLK_MAP(FCLK, PPCLK_FCLK),
138 CLK_MAP(UCLK, PPCLK_UCLK),
139 CLK_MAP(MCLK, PPCLK_UCLK),
140 CLK_MAP(DCLK, PPCLK_DCLK_0),
9c0551f2
JC		 141 CLK_MAP(DCLK1, PPCLK_DCLK_1),
142 CLK_MAP(VCLK, PPCLK_VCLK_0),
b455159c
LG		 143 CLK_MAP(VCLK1, PPCLK_VCLK_1),
144 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
145 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
146 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
147 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
148};
149
6c339f37 150static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
b455159c
LG		 151 FEA_MAP(DPM_PREFETCHER),
152 FEA_MAP(DPM_GFXCLK),
31cb0dd9 153 FEA_MAP(DPM_GFX_GPO),
b455159c 154 FEA_MAP(DPM_UCLK),
e9073b43 155 FEA_MAP(DPM_FCLK),
b455159c
LG		 156 FEA_MAP(DPM_SOCCLK),
157 FEA_MAP(DPM_MP0CLK),
158 FEA_MAP(DPM_LINK),
159 FEA_MAP(DPM_DCEFCLK),
e9073b43 160 FEA_MAP(DPM_XGMI),
b455159c
LG		 161 FEA_MAP(MEM_VDDCI_SCALING),
162 FEA_MAP(MEM_MVDD_SCALING),
163 FEA_MAP(DS_GFXCLK),
164 FEA_MAP(DS_SOCCLK),
e9073b43 165 FEA_MAP(DS_FCLK),
b455159c
LG		 166 FEA_MAP(DS_LCLK),
167 FEA_MAP(DS_DCEFCLK),
168 FEA_MAP(DS_UCLK),
169 FEA_MAP(GFX_ULV),
170 FEA_MAP(FW_DSTATE),
171 FEA_MAP(GFXOFF),
172 FEA_MAP(BACO),
6fb176a7 173 FEA_MAP(MM_DPM_PG),
b455159c
LG		 174 FEA_MAP(RSMU_SMN_CG),
175 FEA_MAP(PPT),
176 FEA_MAP(TDC),
177 FEA_MAP(APCC_PLUS),
178 FEA_MAP(GTHR),
179 FEA_MAP(ACDC),
180 FEA_MAP(VR0HOT),
181 FEA_MAP(VR1HOT),
182 FEA_MAP(FW_CTF),
183 FEA_MAP(FAN_CONTROL),
184 FEA_MAP(THERMAL),
185 FEA_MAP(GFX_DCS),
186 FEA_MAP(RM),
187 FEA_MAP(LED_DISPLAY),
188 FEA_MAP(GFX_SS),
189 FEA_MAP(OUT_OF_BAND_MONITOR),
190 FEA_MAP(TEMP_DEPENDENT_VMIN),
191 FEA_MAP(MMHUB_PG),
192 FEA_MAP(ATHUB_PG),
cf06331f 193 FEA_MAP(APCC_DFLL),
b455159c
LG		 194};
195
6c339f37 196static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
b455159c
LG		 197 TAB_MAP(PPTABLE),
198 TAB_MAP(WATERMARKS),
199 TAB_MAP(AVFS_PSM_DEBUG),
200 TAB_MAP(AVFS_FUSE_OVERRIDE),
201 TAB_MAP(PMSTATUSLOG),
202 TAB_MAP(SMU_METRICS),
203 TAB_MAP(DRIVER_SMU_CONFIG),
204 TAB_MAP(ACTIVITY_MONITOR_COEFF),
205 TAB_MAP(OVERDRIVE),
206 TAB_MAP(I2C_COMMANDS),
207 TAB_MAP(PACE),
208};
209
6c339f37 210static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
1d5ca713
LG		 211 PWR_MAP(AC),
212 PWR_MAP(DC),
213};
214
6c339f37 215static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
b455159c
LG		 216 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
217 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
218 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
219 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
220 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
221 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT),
222 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
223};
224
b455159c
LG		 225static int
226sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
227 uint32_t *feature_mask, uint32_t num)
228{
fea905d4
LG		 229 struct amdgpu_device *adev = smu->adev;
230
b455159c
LG		 231 if (num > 2)
232 return -EINVAL;
233
234 memset(feature_mask, 0, sizeof(uint32_t) * num);
235
4cd4f45b 236 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
15dbe18f 237 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
ce7e5a6e 238 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
094cdf15 239 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
5f338f70 240 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
86a9eb3f 241 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
80c36f86 242 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
9aa60213
LG		 243 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
244 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
d28f4aa1 245 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
20d71dcc 246 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
d0d71970 247 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
886c8bc6
LG		 248 | FEATURE_MASK(FEATURE_PPT_BIT)
249 | FEATURE_MASK(FEATURE_TDC_BIT)
3fc006f5 250 | FEATURE_MASK(FEATURE_BACO_BIT)
cf06331f 251 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
35ed946c 252 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
1c58d429 253 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
b971df70
LG		 254 | FEATURE_MASK(FEATURE_THERMAL_BIT)
255 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
fea905d4 256
c96721eb 257 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
fea905d4 258 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
c96721eb
KF		 259 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
260 }
fea905d4 261
65297d50 262 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
fc17cd3f
LG		 263 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
264 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
265 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
65297d50 266
5cb74353
LG		 267 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
268 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
269
5f338f70
LG		 270 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
271 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
272
fea905d4
LG		 273 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
274 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
b455159c 275
62c1ea6b
LG		 276 if (adev->pm.pp_feature & PP_ULV_MASK)
277 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
278
02bb391d
LG		 279 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
280 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
281
e0da123a
LG		 282 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
283 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
284
b794616d
KF		 285 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
286 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
287
846938c2
KF		 288 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
289 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
290
6fb176a7
LG		 291 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
292 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
293 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
294
b455159c
LG		 295 return 0;
296}
297
298static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
299{
4a13b4ce 300 struct smu_table_context *table_context = &smu->smu_table;
e05acd78 301 struct smu_11_0_7_powerplay_table *powerplay_table =
4a13b4ce
EQ		 302 table_context->power_play_table;
303 struct smu_baco_context *smu_baco = &smu->smu_baco;
304
e05acd78
LG		 305 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO ||
306 powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO)
4a13b4ce 307 smu_baco->platform_support = true;
4a13b4ce
EQ		 308
309 table_context->thermal_controller_type =
310 powerplay_table->thermal_controller_type;
311
b455159c
LG		 312 return 0;
313}
314
315static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
316{
dccc7c21
LG		 317 struct smu_table_context *table_context = &smu->smu_table;
318 PPTable_t *smc_pptable = table_context->driver_pptable;
319 struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
320 int index, ret;
dccc7c21
LG		 321
322 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
323 smc_dpm_info);
324
22f2447c 325 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
dccc7c21
LG		 326 (uint8_t **)&smc_dpm_table);
327 if (ret)
328 return ret;
329
330 memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
969c8d16
LG		 331 sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
332
b455159c
LG		 333 return 0;
334}
335
336static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
337{
b455159c 338 struct smu_table_context *table_context = &smu->smu_table;
e05acd78 339 struct smu_11_0_7_powerplay_table *powerplay_table =
4a13b4ce 340 table_context->power_play_table;
b455159c
LG		 341
342 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
343 sizeof(PPTable_t));
344
4a13b4ce
EQ		 345 return 0;
346}
b455159c 347
4a13b4ce
EQ		 348static int sienna_cichlid_setup_pptable(struct smu_context *smu)
349{
350 int ret = 0;
b455159c 351
4a13b4ce
EQ		 352 ret = smu_v11_0_setup_pptable(smu);
353 if (ret)
354 return ret;
355
356 ret = sienna_cichlid_store_powerplay_table(smu);
357 if (ret)
358 return ret;
359
360 ret = sienna_cichlid_append_powerplay_table(smu);
361 if (ret)
362 return ret;
363
364 ret = sienna_cichlid_check_powerplay_table(smu);
365 if (ret)
366 return ret;
367
368 return ret;
b455159c
LG		 369}
370
c1b353b7 371static int sienna_cichlid_tables_init(struct smu_context *smu)
b455159c
LG		 372{
373 struct smu_table_context *smu_table = &smu->smu_table;
c1b353b7 374 struct smu_table *tables = smu_table->tables;
b455159c
LG		 375
376 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
377 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
378 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
379 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
380 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
381 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
bc50ca29
AD		 382 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
383 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c
LG		 384 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
385 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
386 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
387 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
388 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
389 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
390 AMDGPU_GEM_DOMAIN_VRAM);
391
392 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
393 if (!smu_table->metrics_table)
8ca78a0a 394 goto err0_out;
b455159c
LG		 395 smu_table->metrics_time = 0;
396
8ca78a0a
EQ		 397 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_0);
398 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
399 if (!smu_table->gpu_metrics_table)
400 goto err1_out;
401
40d3b8db
LG		 402 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
403 if (!smu_table->watermarks_table)
8ca78a0a 404 goto err2_out;
40d3b8db 405
b455159c 406 return 0;
8ca78a0a
EQ		 407
408err2_out:
409 kfree(smu_table->gpu_metrics_table);
410err1_out:
411 kfree(smu_table->metrics_table);
412err0_out:
413 return -ENOMEM;
b455159c
LG		 414}
415
60ae4d67
EQ		 416static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
417 MetricsMember_t member,
418 uint32_t *value)
419{
420 struct smu_table_context *smu_table= &smu->smu_table;
421 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
422 int ret = 0;
423
424 mutex_lock(&smu->metrics_lock);
425
fceafc9b
EQ		 426 ret = smu_cmn_get_metrics_table_locked(smu,
427 NULL,
428 false);
60ae4d67
EQ		 429 if (ret) {
430 mutex_unlock(&smu->metrics_lock);
431 return ret;
432 }
433
8c686254
EQ		 434 switch (member) {
435 case METRICS_CURR_GFXCLK:
436 *value = metrics->CurrClock[PPCLK_GFXCLK];
437 break;
438 case METRICS_CURR_SOCCLK:
439 *value = metrics->CurrClock[PPCLK_SOCCLK];
440 break;
441 case METRICS_CURR_UCLK:
442 *value = metrics->CurrClock[PPCLK_UCLK];
443 break;
444 case METRICS_CURR_VCLK:
445 *value = metrics->CurrClock[PPCLK_VCLK_0];
446 break;
447 case METRICS_CURR_VCLK1:
448 *value = metrics->CurrClock[PPCLK_VCLK_1];
449 break;
450 case METRICS_CURR_DCLK:
451 *value = metrics->CurrClock[PPCLK_DCLK_0];
452 break;
453 case METRICS_CURR_DCLK1:
454 *value = metrics->CurrClock[PPCLK_DCLK_1];
455 break;
9d09fa6f
ND		 456 case METRICS_CURR_DCEFCLK:
457 *value = metrics->CurrClock[PPCLK_DCEFCLK];
458 break;
8c686254 459 case METRICS_AVERAGE_GFXCLK:
d817f375
LG		 460 if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
461 *value = metrics->AverageGfxclkFrequencyPostDs;
462 else
463 *value = metrics->AverageGfxclkFrequencyPreDs;
8c686254
EQ		 464 break;
465 case METRICS_AVERAGE_FCLK:
d817f375 466 *value = metrics->AverageFclkFrequencyPostDs;
8c686254
EQ		 467 break;
468 case METRICS_AVERAGE_UCLK:
d817f375 469 *value = metrics->AverageUclkFrequencyPostDs;
8c686254
EQ		 470 break;
471 case METRICS_AVERAGE_GFXACTIVITY:
472 *value = metrics->AverageGfxActivity;
473 break;
474 case METRICS_AVERAGE_MEMACTIVITY:
475 *value = metrics->AverageUclkActivity;
476 break;
477 case METRICS_AVERAGE_SOCKETPOWER:
478 *value = metrics->AverageSocketPower << 8;
479 break;
480 case METRICS_TEMPERATURE_EDGE:
481 *value = metrics->TemperatureEdge *
482 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
483 break;
484 case METRICS_TEMPERATURE_HOTSPOT:
485 *value = metrics->TemperatureHotspot *
486 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
487 break;
488 case METRICS_TEMPERATURE_MEM:
489 *value = metrics->TemperatureMem *
490 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
491 break;
492 case METRICS_TEMPERATURE_VRGFX:
493 *value = metrics->TemperatureVrGfx *
494 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
495 break;
496 case METRICS_TEMPERATURE_VRSOC:
497 *value = metrics->TemperatureVrSoc *
498 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
499 break;
500 case METRICS_THROTTLER_STATUS:
501 *value = metrics->ThrottlerStatus;
502 break;
503 case METRICS_CURR_FANSPEED:
504 *value = metrics->CurrFanSpeed;
505 break;
506 default:
507 *value = UINT_MAX;
508 break;
509 }
510
b455159c
LG		 511 mutex_unlock(&smu->metrics_lock);
512
513 return ret;
8c686254 514
b455159c
LG		 515}
516
517static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
518{
519 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
520
b455159c
LG		 521 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
522 GFP_KERNEL);
523 if (!smu_dpm->dpm_context)
524 return -ENOMEM;
525
526 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
527
528 return 0;
529}
530
c1b353b7
EQ		 531static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
532{
533 int ret = 0;
534
535 ret = sienna_cichlid_tables_init(smu);
536 if (ret)
537 return ret;
538
539 ret = sienna_cichlid_allocate_dpm_context(smu);
540 if (ret)
541 return ret;
542
543 return smu_v11_0_init_smc_tables(smu);
544}
545
b455159c
LG		 546static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
547{
90a89c31
EQ		 548 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
549 PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
550 struct smu_11_0_dpm_table *dpm_table;
85dec717 551 struct amdgpu_device *adev = smu->adev;
90a89c31 552 int ret = 0;
b455159c 553
90a89c31
EQ		 554 /* socclk dpm table setup */
555 dpm_table = &dpm_context->dpm_tables.soc_table;
b4bb3aaf 556 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
90a89c31
EQ		 557 ret = smu_v11_0_set_single_dpm_table(smu,
558 SMU_SOCCLK,
559 dpm_table);
560 if (ret)
561 return ret;
562 dpm_table->is_fine_grained =
563 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
564 } else {
565 dpm_table->count = 1;
566 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
567 dpm_table->dpm_levels[0].enabled = true;
568 dpm_table->min = dpm_table->dpm_levels[0].value;
569 dpm_table->max = dpm_table->dpm_levels[0].value;
570 }
b455159c 571
90a89c31
EQ		 572 /* gfxclk dpm table setup */
573 dpm_table = &dpm_context->dpm_tables.gfx_table;
b4bb3aaf 574 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
90a89c31
EQ		 575 ret = smu_v11_0_set_single_dpm_table(smu,
576 SMU_GFXCLK,
577 dpm_table);
578 if (ret)
579 return ret;
580 dpm_table->is_fine_grained =
581 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
582 } else {
583 dpm_table->count = 1;
584 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
585 dpm_table->dpm_levels[0].enabled = true;
586 dpm_table->min = dpm_table->dpm_levels[0].value;
587 dpm_table->max = dpm_table->dpm_levels[0].value;
588 }
b455159c 589
90a89c31
EQ		 590 /* uclk dpm table setup */
591 dpm_table = &dpm_context->dpm_tables.uclk_table;
b4bb3aaf 592 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
90a89c31
EQ		 593 ret = smu_v11_0_set_single_dpm_table(smu,
594 SMU_UCLK,
595 dpm_table);
596 if (ret)
597 return ret;
598 dpm_table->is_fine_grained =
599 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
600 } else {
601 dpm_table->count = 1;
602 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
603 dpm_table->dpm_levels[0].enabled = true;
604 dpm_table->min = dpm_table->dpm_levels[0].value;
605 dpm_table->max = dpm_table->dpm_levels[0].value;
606 }
b455159c 607
90a89c31
EQ		 608 /* fclk dpm table setup */
609 dpm_table = &dpm_context->dpm_tables.fclk_table;
b4bb3aaf 610 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
90a89c31
EQ		 611 ret = smu_v11_0_set_single_dpm_table(smu,
612 SMU_FCLK,
613 dpm_table);
614 if (ret)
615 return ret;
616 dpm_table->is_fine_grained =
617 !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
618 } else {
619 dpm_table->count = 1;
620 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
621 dpm_table->dpm_levels[0].enabled = true;
622 dpm_table->min = dpm_table->dpm_levels[0].value;
623 dpm_table->max = dpm_table->dpm_levels[0].value;
624 }
b455159c 625
90a89c31
EQ		 626 /* vclk0 dpm table setup */
627 dpm_table = &dpm_context->dpm_tables.vclk_table;
b4bb3aaf 628 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
90a89c31
EQ		 629 ret = smu_v11_0_set_single_dpm_table(smu,
630 SMU_VCLK,
631 dpm_table);
632 if (ret)
633 return ret;
634 dpm_table->is_fine_grained =
635 !driver_ppt->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete;
636 } else {
637 dpm_table->count = 1;
638 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
639 dpm_table->dpm_levels[0].enabled = true;
640 dpm_table->min = dpm_table->dpm_levels[0].value;
641 dpm_table->max = dpm_table->dpm_levels[0].value;
642 }
b455159c 643
90a89c31 644 /* vclk1 dpm table setup */
85dec717
JC		 645 if (adev->vcn.num_vcn_inst > 1) {
646 dpm_table = &dpm_context->dpm_tables.vclk1_table;
647 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
648 ret = smu_v11_0_set_single_dpm_table(smu,
649 SMU_VCLK1,
650 dpm_table);
651 if (ret)
652 return ret;
653 dpm_table->is_fine_grained =
654 !driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete;
655 } else {
656 dpm_table->count = 1;
657 dpm_table->dpm_levels[0].value =
658 smu->smu_table.boot_values.vclk / 100;
659 dpm_table->dpm_levels[0].enabled = true;
660 dpm_table->min = dpm_table->dpm_levels[0].value;
661 dpm_table->max = dpm_table->dpm_levels[0].value;
662 }
90a89c31 663 }
b455159c 664
90a89c31
EQ		 665 /* dclk0 dpm table setup */
666 dpm_table = &dpm_context->dpm_tables.dclk_table;
b4bb3aaf 667 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
90a89c31
EQ		 668 ret = smu_v11_0_set_single_dpm_table(smu,
669 SMU_DCLK,
670 dpm_table);
671 if (ret)
672 return ret;
673 dpm_table->is_fine_grained =
674 !driver_ppt->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete;
675 } else {
676 dpm_table->count = 1;
677 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
678 dpm_table->dpm_levels[0].enabled = true;
679 dpm_table->min = dpm_table->dpm_levels[0].value;
680 dpm_table->max = dpm_table->dpm_levels[0].value;
681 }
682
683 /* dclk1 dpm table setup */
85dec717
JC		 684 if (adev->vcn.num_vcn_inst > 1) {
685 dpm_table = &dpm_context->dpm_tables.dclk1_table;
686 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
687 ret = smu_v11_0_set_single_dpm_table(smu,
688 SMU_DCLK1,
689 dpm_table);
690 if (ret)
691 return ret;
692 dpm_table->is_fine_grained =
693 !driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete;
694 } else {
695 dpm_table->count = 1;
696 dpm_table->dpm_levels[0].value =
697 smu->smu_table.boot_values.dclk / 100;
698 dpm_table->dpm_levels[0].enabled = true;
699 dpm_table->min = dpm_table->dpm_levels[0].value;
700 dpm_table->max = dpm_table->dpm_levels[0].value;
701 }
90a89c31
EQ		 702 }
703
704 /* dcefclk dpm table setup */
705 dpm_table = &dpm_context->dpm_tables.dcef_table;
b4bb3aaf 706 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 707 ret = smu_v11_0_set_single_dpm_table(smu,
708 SMU_DCEFCLK,
709 dpm_table);
710 if (ret)
711 return ret;
712 dpm_table->is_fine_grained =
713 !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
714 } else {
715 dpm_table->count = 1;
716 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
717 dpm_table->dpm_levels[0].enabled = true;
718 dpm_table->min = dpm_table->dpm_levels[0].value;
719 dpm_table->max = dpm_table->dpm_levels[0].value;
720 }
b455159c 721
90a89c31
EQ		 722 /* pixelclk dpm table setup */
723 dpm_table = &dpm_context->dpm_tables.pixel_table;
b4bb3aaf 724 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 725 ret = smu_v11_0_set_single_dpm_table(smu,
726 SMU_PIXCLK,
727 dpm_table);
728 if (ret)
729 return ret;
730 dpm_table->is_fine_grained =
731 !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
732 } else {
733 dpm_table->count = 1;
734 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
735 dpm_table->dpm_levels[0].enabled = true;
736 dpm_table->min = dpm_table->dpm_levels[0].value;
737 dpm_table->max = dpm_table->dpm_levels[0].value;
738 }
b455159c 739
90a89c31
EQ		 740 /* displayclk dpm table setup */
741 dpm_table = &dpm_context->dpm_tables.display_table;
b4bb3aaf 742 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 743 ret = smu_v11_0_set_single_dpm_table(smu,
744 SMU_DISPCLK,
745 dpm_table);
746 if (ret)
747 return ret;
748 dpm_table->is_fine_grained =
749 !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
750 } else {
751 dpm_table->count = 1;
752 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
753 dpm_table->dpm_levels[0].enabled = true;
754 dpm_table->min = dpm_table->dpm_levels[0].value;
755 dpm_table->max = dpm_table->dpm_levels[0].value;
756 }
b455159c 757
90a89c31
EQ		 758 /* phyclk dpm table setup */
759 dpm_table = &dpm_context->dpm_tables.phy_table;
b4bb3aaf 760 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 761 ret = smu_v11_0_set_single_dpm_table(smu,
762 SMU_PHYCLK,
763 dpm_table);
764 if (ret)
765 return ret;
766 dpm_table->is_fine_grained =
767 !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
768 } else {
769 dpm_table->count = 1;
770 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
771 dpm_table->dpm_levels[0].enabled = true;
772 dpm_table->min = dpm_table->dpm_levels[0].value;
773 dpm_table->max = dpm_table->dpm_levels[0].value;
774 }
b455159c
LG		 775
776 return 0;
777}
778
f6b4b4a1 779static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
b455159c 780{
d51dc613 781 struct amdgpu_device *adev = smu->adev;
b455159c
LG		 782 int ret = 0;
783
784 if (enable) {
785 /* vcn dpm on is a prerequisite for vcn power gate messages */
b4bb3aaf 786 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 787 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
6fb176a7
LG		 788 if (ret)
789 return ret;
6ec46653 790 if (adev->vcn.num_vcn_inst > 1) {
66c86828 791 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
d51dc613
JC		 792 0x10000, NULL);
793 if (ret)
794 return ret;
795 }
b455159c 796 }
b455159c 797 } else {
b4bb3aaf 798 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 799 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
6fb176a7
LG		 800 if (ret)
801 return ret;
6ec46653 802 if (adev->vcn.num_vcn_inst > 1) {
66c86828 803 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
d51dc613
JC		 804 0x10000, NULL);
805 if (ret)
806 return ret;
807 }
b455159c 808 }
b455159c
LG		 809 }
810
811 return ret;
812}
813
6fb176a7
LG		 814static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
815{
6fb176a7
LG		 816 int ret = 0;
817
818 if (enable) {
b4bb3aaf 819 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 820 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
6fb176a7
LG		 821 if (ret)
822 return ret;
6fb176a7 823 }
6fb176a7 824 } else {
b4bb3aaf 825 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 826 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
6fb176a7
LG		 827 if (ret)
828 return ret;
6fb176a7 829 }
6fb176a7
LG		 830 }
831
832 return ret;
833}
834
b455159c
LG		 835static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
836 enum smu_clk_type clk_type,
837 uint32_t *value)
838{
8c686254
EQ		 839 MetricsMember_t member_type;
840 int clk_id = 0;
b455159c 841
6c339f37
EQ		 842 clk_id = smu_cmn_to_asic_specific_index(smu,
843 CMN2ASIC_MAPPING_CLK,
844 clk_type);
b455159c
LG		 845 if (clk_id < 0)
846 return clk_id;
847
8c686254
EQ		 848 switch (clk_id) {
849 case PPCLK_GFXCLK:
850 member_type = METRICS_CURR_GFXCLK;
851 break;
852 case PPCLK_UCLK:
853 member_type = METRICS_CURR_UCLK;
854 break;
855 case PPCLK_SOCCLK:
856 member_type = METRICS_CURR_SOCCLK;
857 break;
858 case PPCLK_FCLK:
859 member_type = METRICS_CURR_FCLK;
860 break;
861 case PPCLK_VCLK_0:
862 member_type = METRICS_CURR_VCLK;
863 break;
864 case PPCLK_VCLK_1:
865 member_type = METRICS_CURR_VCLK1;
866 break;
867 case PPCLK_DCLK_0:
868 member_type = METRICS_CURR_DCLK;
869 break;
870 case PPCLK_DCLK_1:
871 member_type = METRICS_CURR_DCLK1;
872 break;
873 case PPCLK_DCEFCLK:
874 member_type = METRICS_CURR_DCEFCLK;
875 break;
876 default:
877 return -EINVAL;
878 }
879
880 return sienna_cichlid_get_smu_metrics_data(smu,
881 member_type,
882 value);
b455159c 883
b455159c
LG		 884}
885
886static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
887{
888 PPTable_t *pptable = smu->smu_table.driver_pptable;
889 DpmDescriptor_t *dpm_desc = NULL;
890 uint32_t clk_index = 0;
891
6c339f37
EQ		 892 clk_index = smu_cmn_to_asic_specific_index(smu,
893 CMN2ASIC_MAPPING_CLK,
894 clk_type);
b455159c
LG		 895 dpm_desc = &pptable->DpmDescriptor[clk_index];
896
897 /* 0 - Fine grained DPM, 1 - Discrete DPM */
898 return dpm_desc->SnapToDiscrete == 0 ? true : false;
899}
900
901static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
902 enum smu_clk_type clk_type, char *buf)
903{
b7d25b5f
LG		 904 struct amdgpu_device *adev = smu->adev;
905 struct smu_table_context *table_context = &smu->smu_table;
906 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
907 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
908 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
b455159c
LG		 909 int i, size = 0, ret = 0;
910 uint32_t cur_value = 0, value = 0, count = 0;
911 uint32_t freq_values[3] = {0};
912 uint32_t mark_index = 0;
b7d25b5f 913 uint32_t gen_speed, lane_width;
b455159c
LG		 914
915 switch (clk_type) {
916 case SMU_GFXCLK:
917 case SMU_SCLK:
918 case SMU_SOCCLK:
919 case SMU_MCLK:
920 case SMU_UCLK:
921 case SMU_FCLK:
922 case SMU_DCEFCLK:
5e6dc8fe 923 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
b455159c 924 if (ret)
258d290c 925 goto print_clk_out;
b455159c 926
ba818620
KF		 927 /* no need to disable gfxoff when retrieving the current gfxclk */
928 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
929 amdgpu_gfx_off_ctrl(adev, false);
930
d8d3493a 931 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
b455159c 932 if (ret)
258d290c 933 goto print_clk_out;
b455159c
LG		 934
935 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
936 for (i = 0; i < count; i++) {
d8d3493a 937 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
b455159c 938 if (ret)
258d290c 939 goto print_clk_out;
b455159c
LG		 940
941 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
942 cur_value == value ? "*" : "");
943 }
944 } else {
d8d3493a 945 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
b455159c 946 if (ret)
258d290c 947 goto print_clk_out;
d8d3493a 948 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
b455159c 949 if (ret)
258d290c 950 goto print_clk_out;
b455159c
LG		 951
952 freq_values[1] = cur_value;
953 mark_index = cur_value == freq_values[0] ? 0 :
954 cur_value == freq_values[2] ? 2 : 1;
955 if (mark_index != 1)
956 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
957
958 for (i = 0; i < 3; i++) {
959 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
960 i == mark_index ? "*" : "");
961 }
962
963 }
964 break;
b7d25b5f 965 case SMU_PCIE:
e4c9200d
EQ		 966 gen_speed = smu_v11_0_get_current_pcie_link_speed(smu);
967 lane_width = smu_v11_0_get_current_pcie_link_width(smu);
b7d25b5f
LG		 968 for (i = 0; i < NUM_LINK_LEVELS; i++)
969 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
970 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
971 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
972 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
973 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
974 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
975 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
976 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
977 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
978 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
979 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
980 pptable->LclkFreq[i],
981 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
982 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
983 "*" : "");
984 break;
b455159c
LG		 985 default:
986 break;
987 }
988
258d290c
LG		 989print_clk_out:
990 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
991 amdgpu_gfx_off_ctrl(adev, true);
992
b455159c
LG		 993 return size;
994}
995
996static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
997 enum smu_clk_type clk_type, uint32_t mask)
998{
258d290c 999 struct amdgpu_device *adev = smu->adev;
b455159c
LG		 1000 int ret = 0, size = 0;
1001 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1002
1003 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1004 soft_max_level = mask ? (fls(mask) - 1) : 0;
1005
258d290c
LG		 1006 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1007 amdgpu_gfx_off_ctrl(adev, false);
1008
b455159c
LG		 1009 switch (clk_type) {
1010 case SMU_GFXCLK:
1011 case SMU_SCLK:
1012 case SMU_SOCCLK:
1013 case SMU_MCLK:
1014 case SMU_UCLK:
1015 case SMU_DCEFCLK:
1016 case SMU_FCLK:
9ad9c8ac
LG		 1017 /* There is only 2 levels for fine grained DPM */
1018 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1019 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1020 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1021 }
1022
d8d3493a 1023 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
b455159c 1024 if (ret)
258d290c 1025 goto forec_level_out;
b455159c 1026
d8d3493a 1027 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
b455159c 1028 if (ret)
258d290c 1029 goto forec_level_out;
b455159c 1030
10e96d89 1031 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
b455159c 1032 if (ret)
258d290c 1033 goto forec_level_out;
b455159c
LG		 1034 break;
1035 default:
1036 break;
1037 }
1038
258d290c
LG		 1039forec_level_out:
1040 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1041 amdgpu_gfx_off_ctrl(adev, true);
1042
b455159c
LG		 1043 return size;
1044}
1045
1046static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1047{
62cc9dd1
EQ		 1048 struct smu_11_0_dpm_context *dpm_context =
1049 smu->smu_dpm.dpm_context;
1050 struct smu_11_0_dpm_table *gfx_table =
1051 &dpm_context->dpm_tables.gfx_table;
1052 struct smu_11_0_dpm_table *mem_table =
1053 &dpm_context->dpm_tables.uclk_table;
1054 struct smu_11_0_dpm_table *soc_table =
1055 &dpm_context->dpm_tables.soc_table;
1056 struct smu_umd_pstate_table *pstate_table =
1057 &smu->pstate_table;
1058
1059 pstate_table->gfxclk_pstate.min = gfx_table->min;
1060 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1061
1062 pstate_table->uclk_pstate.min = mem_table->min;
1063 pstate_table->uclk_pstate.peak = mem_table->max;
1064
1065 pstate_table->socclk_pstate.min = soc_table->min;
1066 pstate_table->socclk_pstate.peak = soc_table->max;
b455159c 1067
62cc9dd1 1068 return 0;
b455159c
LG		 1069}
1070
b455159c
LG		 1071static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1072{
1073 int ret = 0;
1074 uint32_t max_freq = 0;
1075
1076 /* Sienna_Cichlid do not support to change display num currently */
1077 return 0;
1078#if 0
66c86828 1079 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
b455159c
LG		 1080 if (ret)
1081 return ret;
1082#endif
1083
b4bb3aaf 1084 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
e5ef784b 1085 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
b455159c
LG		 1086 if (ret)
1087 return ret;
661b94f5 1088 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
b455159c
LG		 1089 if (ret)
1090 return ret;
1091 }
1092
1093 return ret;
1094}
1095
1096static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1097{
1098 int ret = 0;
1099
b455159c 1100 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
4d942ae3
EQ		 1101 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1102 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
b455159c 1103#if 0
66c86828 1104 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
40d3b8db
LG		 1105 smu->display_config->num_display,
1106 NULL);
b455159c
LG		 1107#endif
1108 if (ret)
1109 return ret;
1110 }
1111
1112 return ret;
1113}
1114
b455159c
LG		 1115static int sienna_cichlid_get_gpu_power(struct smu_context *smu, uint32_t *value)
1116{
b455159c
LG		 1117 if (!value)
1118 return -EINVAL;
1119
8c686254
EQ		 1120 return sienna_cichlid_get_smu_metrics_data(smu,
1121 METRICS_AVERAGE_SOCKETPOWER,
1122 value);
b455159c
LG		 1123}
1124
1125static int sienna_cichlid_get_current_activity_percent(struct smu_context *smu,
1126 enum amd_pp_sensors sensor,
1127 uint32_t *value)
1128{
1129 int ret = 0;
b455159c
LG		 1130
1131 if (!value)
1132 return -EINVAL;
1133
b455159c
LG		 1134 switch (sensor) {
1135 case AMDGPU_PP_SENSOR_GPU_LOAD:
8c686254
EQ		 1136 ret = sienna_cichlid_get_smu_metrics_data(smu,
1137 METRICS_AVERAGE_GFXACTIVITY,
1138 value);
b455159c
LG		 1139 break;
1140 case AMDGPU_PP_SENSOR_MEM_LOAD:
8c686254
EQ		 1141 ret = sienna_cichlid_get_smu_metrics_data(smu,
1142 METRICS_AVERAGE_MEMACTIVITY,
1143 value);
b455159c
LG		 1144 break;
1145 default:
d9811cfc 1146 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
b455159c
LG		 1147 return -EINVAL;
1148 }
1149
8c686254 1150 return ret;
b455159c
LG		 1151}
1152
1153static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1154{
1155 int ret = 0;
1156 uint32_t feature_mask[2];
3d14a79b
KW		 1157 uint64_t feature_enabled;
1158
28251d72 1159 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
3d14a79b
KW		 1160 if (ret)
1161 return false;
1162
1163 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1164
b455159c
LG		 1165 return !!(feature_enabled & SMC_DPM_FEATURE);
1166}
1167
1168static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1169 uint32_t *speed)
1170{
b455159c
LG		 1171 if (!speed)
1172 return -EINVAL;
1173
f6eb4339
AD		 1174 switch (smu_v11_0_get_fan_control_mode(smu)) {
1175 case AMD_FAN_CTRL_AUTO:
1176 return sienna_cichlid_get_smu_metrics_data(smu,
1177 METRICS_CURR_FANSPEED,
1178 speed);
1179 default:
1180 return smu_v11_0_get_fan_speed_rpm(smu, speed);
1181 }
b455159c
LG		 1182}
1183
3204ff3e
AD		 1184static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1185{
1186 PPTable_t *pptable = smu->smu_table.driver_pptable;
1187
1188 smu->fan_max_rpm = pptable->FanMaximumRpm;
1189
1190 return 0;
1191}
1192
b455159c
LG		 1193static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1194{
1195 DpmActivityMonitorCoeffInt_t activity_monitor;
1196 uint32_t i, size = 0;
1197 int16_t workload_type = 0;
1198 static const char *profile_name[] = {
1199 "BOOTUP_DEFAULT",
1200 "3D_FULL_SCREEN",
1201 "POWER_SAVING",
1202 "VIDEO",
1203 "VR",
1204 "COMPUTE",
1205 "CUSTOM"};
1206 static const char *title[] = {
1207 "PROFILE_INDEX(NAME)",
1208 "CLOCK_TYPE(NAME)",
1209 "FPS",
1210 "MinFreqType",
1211 "MinActiveFreqType",
1212 "MinActiveFreq",
1213 "BoosterFreqType",
1214 "BoosterFreq",
1215 "PD_Data_limit_c",
1216 "PD_Data_error_coeff",
1217 "PD_Data_error_rate_coeff"};
1218 int result = 0;
1219
1220 if (!buf)
1221 return -EINVAL;
1222
1223 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1224 title[0], title[1], title[2], title[3], title[4], title[5],
1225 title[6], title[7], title[8], title[9], title[10]);
1226
1227 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1228 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
6c339f37
EQ		 1229 workload_type = smu_cmn_to_asic_specific_index(smu,
1230 CMN2ASIC_MAPPING_WORKLOAD,
1231 i);
b455159c
LG		 1232 if (workload_type < 0)
1233 return -EINVAL;
1234
caad2613 1235 result = smu_cmn_update_table(smu,
b455159c
LG		 1236 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1237 (void *)(&activity_monitor), false);
1238 if (result) {
d9811cfc 1239 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
b455159c
LG		 1240 return result;
1241 }
1242
1243 size += sprintf(buf + size, "%2d %14s%s:\n",
1244 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1245
1246 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1247 " ",
1248 0,
1249 "GFXCLK",
1250 activity_monitor.Gfx_FPS,
1251 activity_monitor.Gfx_MinFreqStep,
1252 activity_monitor.Gfx_MinActiveFreqType,
1253 activity_monitor.Gfx_MinActiveFreq,
1254 activity_monitor.Gfx_BoosterFreqType,
1255 activity_monitor.Gfx_BoosterFreq,
1256 activity_monitor.Gfx_PD_Data_limit_c,
1257 activity_monitor.Gfx_PD_Data_error_coeff,
1258 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1259
1260 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1261 " ",
1262 1,
1263 "SOCCLK",
1264 activity_monitor.Fclk_FPS,
1265 activity_monitor.Fclk_MinFreqStep,
1266 activity_monitor.Fclk_MinActiveFreqType,
1267 activity_monitor.Fclk_MinActiveFreq,
1268 activity_monitor.Fclk_BoosterFreqType,
1269 activity_monitor.Fclk_BoosterFreq,
1270 activity_monitor.Fclk_PD_Data_limit_c,
1271 activity_monitor.Fclk_PD_Data_error_coeff,
1272 activity_monitor.Fclk_PD_Data_error_rate_coeff);
1273
1274 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1275 " ",
1276 2,
1277 "MEMLK",
1278 activity_monitor.Mem_FPS,
1279 activity_monitor.Mem_MinFreqStep,
1280 activity_monitor.Mem_MinActiveFreqType,
1281 activity_monitor.Mem_MinActiveFreq,
1282 activity_monitor.Mem_BoosterFreqType,
1283 activity_monitor.Mem_BoosterFreq,
1284 activity_monitor.Mem_PD_Data_limit_c,
1285 activity_monitor.Mem_PD_Data_error_coeff,
1286 activity_monitor.Mem_PD_Data_error_rate_coeff);
1287 }
1288
1289 return size;
1290}
1291
1292static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1293{
1294 DpmActivityMonitorCoeffInt_t activity_monitor;
1295 int workload_type, ret = 0;
1296
1297 smu->power_profile_mode = input[size];
1298
1299 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
d9811cfc 1300 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
b455159c
LG		 1301 return -EINVAL;
1302 }
1303
1304 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
b455159c 1305
caad2613 1306 ret = smu_cmn_update_table(smu,
b455159c
LG		 1307 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1308 (void *)(&activity_monitor), false);
1309 if (ret) {
d9811cfc 1310 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
b455159c
LG		 1311 return ret;
1312 }
1313
1314 switch (input[0]) {
1315 case 0: /* Gfxclk */
1316 activity_monitor.Gfx_FPS = input[1];
1317 activity_monitor.Gfx_MinFreqStep = input[2];
1318 activity_monitor.Gfx_MinActiveFreqType = input[3];
1319 activity_monitor.Gfx_MinActiveFreq = input[4];
1320 activity_monitor.Gfx_BoosterFreqType = input[5];
1321 activity_monitor.Gfx_BoosterFreq = input[6];
1322 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1323 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1324 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1325 break;
1326 case 1: /* Socclk */
1327 activity_monitor.Fclk_FPS = input[1];
1328 activity_monitor.Fclk_MinFreqStep = input[2];
1329 activity_monitor.Fclk_MinActiveFreqType = input[3];
1330 activity_monitor.Fclk_MinActiveFreq = input[4];
1331 activity_monitor.Fclk_BoosterFreqType = input[5];
1332 activity_monitor.Fclk_BoosterFreq = input[6];
1333 activity_monitor.Fclk_PD_Data_limit_c = input[7];
1334 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1335 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1336 break;
1337 case 2: /* Memlk */
1338 activity_monitor.Mem_FPS = input[1];
1339 activity_monitor.Mem_MinFreqStep = input[2];
1340 activity_monitor.Mem_MinActiveFreqType = input[3];
1341 activity_monitor.Mem_MinActiveFreq = input[4];
1342 activity_monitor.Mem_BoosterFreqType = input[5];
1343 activity_monitor.Mem_BoosterFreq = input[6];
1344 activity_monitor.Mem_PD_Data_limit_c = input[7];
1345 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1346 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1347 break;
1348 }
1349
caad2613 1350 ret = smu_cmn_update_table(smu,
b455159c
LG		 1351 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1352 (void *)(&activity_monitor), true);
1353 if (ret) {
d9811cfc 1354 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
b455159c
LG		 1355 return ret;
1356 }
1357 }
1358
1359 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
6c339f37
EQ		 1360 workload_type = smu_cmn_to_asic_specific_index(smu,
1361 CMN2ASIC_MAPPING_WORKLOAD,
1362 smu->power_profile_mode);
b455159c
LG		 1363 if (workload_type < 0)
1364 return -EINVAL;
66c86828 1365 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
b455159c
LG		 1366 1 << workload_type, NULL);
1367
1368 return ret;
1369}
1370
b455159c
LG		 1371static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1372{
1373 struct smu_clocks min_clocks = {0};
1374 struct pp_display_clock_request clock_req;
1375 int ret = 0;
1376
1377 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1378 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1379 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1380
4d942ae3 1381 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
b455159c
LG		 1382 clock_req.clock_type = amd_pp_dcef_clock;
1383 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1384
1385 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1386 if (!ret) {
4d942ae3 1387 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
66c86828 1388 ret = smu_cmn_send_smc_msg_with_param(smu,
40d3b8db
LG		 1389 SMU_MSG_SetMinDeepSleepDcefclk,
1390 min_clocks.dcef_clock_in_sr/100,
1391 NULL);
1392 if (ret) {
d9811cfc 1393 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
40d3b8db
LG		 1394 return ret;
1395 }
b455159c
LG		 1396 }
1397 } else {
d9811cfc 1398 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
b455159c
LG		 1399 }
1400 }
1401
b4bb3aaf 1402 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
661b94f5 1403 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
b455159c 1404 if (ret) {
d9811cfc 1405 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
b455159c
LG		 1406 return ret;
1407 }
1408 }
1409
1410 return 0;
1411}
1412
1413static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
7b9c7e30 1414 struct pp_smu_wm_range_sets *clock_ranges)
b455159c 1415{
e7a95eea 1416 Watermarks_t *table = smu->smu_table.watermarks_table;
40d3b8db 1417 int ret = 0;
e7a95eea 1418 int i;
b455159c 1419
e7a95eea 1420 if (clock_ranges) {
7b9c7e30
EQ		 1421 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1422 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
e7a95eea
EQ		 1423 return -EINVAL;
1424
7b9c7e30
EQ		 1425 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1426 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1427 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1428 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1429 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1430 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1431 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1432 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1433 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1434
1435 table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1436 clock_ranges->reader_wm_sets[i].wm_inst;
e7a95eea 1437 }
b455159c 1438
7b9c7e30
EQ		 1439 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1440 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1441 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1442 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1443 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1444 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1445 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1446 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1447 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1448
1449 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1450 clock_ranges->writer_wm_sets[i].wm_inst;
e7a95eea
EQ		 1451 }
1452
1453 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1454 }
1455
1456 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1457 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
caad2613 1458 ret = smu_cmn_write_watermarks_table(smu);
40d3b8db 1459 if (ret) {
d9811cfc 1460 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
40d3b8db
LG		 1461 return ret;
1462 }
1463 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1464 }
1465
b455159c
LG		 1466 return 0;
1467}
1468
1469static int sienna_cichlid_thermal_get_temperature(struct smu_context *smu,
1470 enum amd_pp_sensors sensor,
1471 uint32_t *value)
1472{
b455159c
LG		 1473 int ret = 0;
1474
1475 if (!value)
1476 return -EINVAL;
1477
b455159c
LG		 1478 switch (sensor) {
1479 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
8c686254
EQ		 1480 ret = sienna_cichlid_get_smu_metrics_data(smu,
1481 METRICS_TEMPERATURE_HOTSPOT,
1482 value);
b455159c
LG		 1483 break;
1484 case AMDGPU_PP_SENSOR_EDGE_TEMP:
8c686254
EQ		 1485 ret = sienna_cichlid_get_smu_metrics_data(smu,
1486 METRICS_TEMPERATURE_EDGE,
1487 value);
b455159c
LG		 1488 break;
1489 case AMDGPU_PP_SENSOR_MEM_TEMP:
8c686254
EQ		 1490 ret = sienna_cichlid_get_smu_metrics_data(smu,
1491 METRICS_TEMPERATURE_MEM,
1492 value);
b455159c
LG		 1493 break;
1494 default:
d9811cfc 1495 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
b455159c
LG		 1496 return -EINVAL;
1497 }
1498
8c686254 1499 return ret;
b455159c
LG		 1500}
1501
1502static int sienna_cichlid_read_sensor(struct smu_context *smu,
1503 enum amd_pp_sensors sensor,
1504 void *data, uint32_t *size)
1505{
1506 int ret = 0;
1507 struct smu_table_context *table_context = &smu->smu_table;
1508 PPTable_t *pptable = table_context->driver_pptable;
1509
1510 if(!data || !size)
1511 return -EINVAL;
1512
1513 mutex_lock(&smu->sensor_lock);
1514 switch (sensor) {
1515 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1516 *(uint32_t *)data = pptable->FanMaximumRpm;
1517 *size = 4;
1518 break;
1519 case AMDGPU_PP_SENSOR_MEM_LOAD:
1520 case AMDGPU_PP_SENSOR_GPU_LOAD:
1521 ret = sienna_cichlid_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1522 *size = 4;
1523 break;
1524 case AMDGPU_PP_SENSOR_GPU_POWER:
1525 ret = sienna_cichlid_get_gpu_power(smu, (uint32_t *)data);
1526 *size = 4;
1527 break;
1528 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1529 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1530 case AMDGPU_PP_SENSOR_MEM_TEMP:
1531 ret = sienna_cichlid_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1532 *size = 4;
1533 break;
e0f9e936
EQ		 1534 case AMDGPU_PP_SENSOR_GFX_MCLK:
1535 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1536 *(uint32_t *)data *= 100;
1537 *size = 4;
1538 break;
1539 case AMDGPU_PP_SENSOR_GFX_SCLK:
1540 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1541 *(uint32_t *)data *= 100;
1542 *size = 4;
1543 break;
b2febc99
EQ		 1544 case AMDGPU_PP_SENSOR_VDDGFX:
1545 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1546 *size = 4;
1547 break;
b455159c 1548 default:
b2febc99
EQ		 1549 ret = -EOPNOTSUPP;
1550 break;
b455159c
LG		 1551 }
1552 mutex_unlock(&smu->sensor_lock);
1553
1554 return ret;
1555}
1556
1557static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1558{
1559 uint32_t num_discrete_levels = 0;
1560 uint16_t *dpm_levels = NULL;
1561 uint16_t i = 0;
1562 struct smu_table_context *table_context = &smu->smu_table;
1563 PPTable_t *driver_ppt = NULL;
1564
1565 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1566 return -EINVAL;
1567
1568 driver_ppt = table_context->driver_pptable;
1569 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1570 dpm_levels = driver_ppt->FreqTableUclk;
1571
1572 if (num_discrete_levels == 0 || dpm_levels == NULL)
1573 return -EINVAL;
1574
1575 *num_states = num_discrete_levels;
1576 for (i = 0; i < num_discrete_levels; i++) {
1577 /* convert to khz */
1578 *clocks_in_khz = (*dpm_levels) * 1000;
1579 clocks_in_khz++;
1580 dpm_levels++;
1581 }
1582
1583 return 0;
1584}
1585
1586static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1587 struct smu_temperature_range *range)
1588{
e02e4d51
EQ		 1589 struct smu_table_context *table_context = &smu->smu_table;
1590 struct smu_11_0_7_powerplay_table *powerplay_table =
1591 table_context->power_play_table;
2b1f12a2 1592 PPTable_t *pptable = smu->smu_table.driver_pptable;
b455159c 1593
2b1f12a2 1594 if (!range)
b455159c
LG		 1595 return -EINVAL;
1596
0540eced
EQ		 1597 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1598
2b1f12a2
EQ		 1599 range->max = pptable->TemperatureLimit[TEMP_EDGE] *
1600 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1601 range->edge_emergency_max = (pptable->TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
1602 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1603 range->hotspot_crit_max = pptable->TemperatureLimit[TEMP_HOTSPOT] *
1604 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1605 range->hotspot_emergency_max = (pptable->TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
1606 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1607 range->mem_crit_max = pptable->TemperatureLimit[TEMP_MEM] *
1608 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1609 range->mem_emergency_max = (pptable->TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
b455159c 1610 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
e02e4d51 1611 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
b455159c
LG		 1612
1613 return 0;
1614}
1615
1616static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1617 bool disable_memory_clock_switch)
1618{
1619 int ret = 0;
1620 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1621 (struct smu_11_0_max_sustainable_clocks *)
1622 smu->smu_table.max_sustainable_clocks;
1623 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1624 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1625
1626 if(smu->disable_uclk_switch == disable_memory_clock_switch)
1627 return 0;
1628
1629 if(disable_memory_clock_switch)
661b94f5 1630 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
b455159c 1631 else
661b94f5 1632 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
b455159c
LG		 1633
1634 if(!ret)
1635 smu->disable_uclk_switch = disable_memory_clock_switch;
1636
1637 return ret;
1638}
1639
a141b4e3 1640static int sienna_cichlid_get_power_limit(struct smu_context *smu)
b455159c 1641{
1e239fdd
EQ		 1642 struct smu_11_0_7_powerplay_table *powerplay_table =
1643 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
b455159c 1644 PPTable_t *pptable = smu->smu_table.driver_pptable;
1e239fdd
EQ		 1645 uint32_t power_limit, od_percent;
1646
1647 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1648 /* the last hope to figure out the ppt limit */
1649 if (!pptable) {
1650 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1651 return -EINVAL;
b455159c 1652 }
1e239fdd
EQ		 1653 power_limit =
1654 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1655 }
1656 smu->current_power_limit = power_limit;
b455159c 1657
1e239fdd
EQ		 1658 if (smu->od_enabled) {
1659 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
1660
1661 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1662
1663 power_limit *= (100 + od_percent);
1664 power_limit /= 100;
b455159c 1665 }
1e239fdd 1666 smu->max_power_limit = power_limit;
b455159c 1667
b455159c
LG		 1668 return 0;
1669}
1670
08ccfe08
LG		 1671static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1672 uint32_t pcie_gen_cap,
1673 uint32_t pcie_width_cap)
1674{
0b590970 1675 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
08ccfe08 1676 PPTable_t *pptable = smu->smu_table.driver_pptable;
08ccfe08 1677 uint32_t smu_pcie_arg;
0b590970 1678 int ret, i;
08ccfe08 1679
0b590970
EQ		 1680 /* lclk dpm table setup */
1681 for (i = 0; i < MAX_PCIE_CONF; i++) {
1682 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
1683 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
1684 }
08ccfe08
LG		 1685
1686 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1687 smu_pcie_arg = (i << 16) |
1688 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ?
1689 (pptable->PcieGenSpeed[i] << 8) :
1690 (pcie_gen_cap << 8)) |
1691 ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1692 pptable->PcieLaneCount[i] :
1693 pcie_width_cap);
1694
66c86828 1695 ret = smu_cmn_send_smc_msg_with_param(smu,
40d3b8db
LG		 1696 SMU_MSG_OverridePcieParameters,
1697 smu_pcie_arg,
1698 NULL);
1699
08ccfe08
LG		 1700 if (ret)
1701 return ret;
1702
1703 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1704 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1705 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1706 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1707 }
1708
1709 return 0;
1710}
1711
38ed7b09 1712static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
258d290c
LG		 1713 enum smu_clk_type clk_type,
1714 uint32_t *min, uint32_t *max)
1715{
1716 struct amdgpu_device *adev = smu->adev;
1717 int ret;
1718
1719 if (clk_type == SMU_GFXCLK)
1720 amdgpu_gfx_off_ctrl(adev, false);
1721 ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
1722 if (clk_type == SMU_GFXCLK)
1723 amdgpu_gfx_off_ctrl(adev, true);
1724
1725 return ret;
1726}
1727
66b8a9c0
JC		 1728static int sienna_cichlid_run_btc(struct smu_context *smu)
1729{
1730 return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
1731}
1732
40d3b8db
LG		 1733static bool sienna_cichlid_is_baco_supported(struct smu_context *smu)
1734{
1735 struct amdgpu_device *adev = smu->adev;
1736 uint32_t val;
1737
311531f0 1738 if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu)))
40d3b8db
LG		 1739 return false;
1740
1741 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
1742 return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
1743}
1744
ea8139d8
WS		 1745static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
1746{
1747 struct amdgpu_device *adev = smu->adev;
1748 uint32_t val;
1749 u32 smu_version;
1750
1751 /**
1752 * SRIOV env will not support SMU mode1 reset
1753 * PM FW support mode1 reset from 58.26
1754 */
a7bae061 1755 smu_cmn_get_smc_version(smu, NULL, &smu_version);
ea8139d8
WS		 1756 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
1757 return false;
1758
1759 /**
1760 * mode1 reset relies on PSP, so we should check if
1761 * PSP is alive.
1762 */
1763 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
1764 return val != 0x0;
1765}
1766
b455159c
LG		 1767static void sienna_cichlid_dump_pptable(struct smu_context *smu)
1768{
1769 struct smu_table_context *table_context = &smu->smu_table;
1770 PPTable_t *pptable = table_context->driver_pptable;
1771 int i;
1772
d9811cfc 1773 dev_info(smu->adev->dev, "Dumped PPTable:\n");
b455159c 1774
d9811cfc
EQ		 1775 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
1776 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1777 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
b455159c
LG		 1778
1779 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
d9811cfc
EQ		 1780 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
1781 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
1782 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
1783 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
b455159c
LG		 1784 }
1785
1786 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
d9811cfc
EQ		 1787 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
1788 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
b455159c
LG		 1789 }
1790
1791 for (i = 0; i < TEMP_COUNT; i++) {
d9811cfc 1792 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
b455159c
LG		 1793 }
1794
d9811cfc
EQ		 1795 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
1796 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
1797 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
1798 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
1799 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
b455159c 1800
d9811cfc 1801 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
b455159c 1802 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
d9811cfc
EQ		 1803 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
1804 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
b455159c 1805 }
d9811cfc
EQ		 1806 dev_info(smu->adev->dev, "PaddingAPCC[0] = 0x%x\n", pptable->PaddingAPCC[0]);
1807 dev_info(smu->adev->dev, "PaddingAPCC[1] = 0x%x\n", pptable->PaddingAPCC[1]);
1808 dev_info(smu->adev->dev, "PaddingAPCC[2] = 0x%x\n", pptable->PaddingAPCC[2]);
1809 dev_info(smu->adev->dev, "PaddingAPCC[3] = 0x%x\n", pptable->PaddingAPCC[3]);
1810
1811 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
1812
1813 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
1814
1815 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
1816 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
1817 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
1818 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
1819
1820 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
1821 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
1822
1823 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
1824 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
1825 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
1826 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
1827
1828 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
1829 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
1830 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
1831 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
1832
1833 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
1834 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
1835
1836 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
1837 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
1838 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
1839 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
1840 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
1841 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
1842 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
1843 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
1844
1845 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
b455159c
LG		 1846 " .VoltageMode = 0x%02x\n"
1847 " .SnapToDiscrete = 0x%02x\n"
1848 " .NumDiscreteLevels = 0x%02x\n"
1849 " .padding = 0x%02x\n"
1850 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1851 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1852 " .SsFmin = 0x%04x\n"
1853 " .Padding_16 = 0x%04x\n",
1854 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1855 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1856 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1857 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
1858 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1859 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1860 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1861 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1862 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1863 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1864 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1865
d9811cfc 1866 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
b455159c
LG		 1867 " .VoltageMode = 0x%02x\n"
1868 " .SnapToDiscrete = 0x%02x\n"
1869 " .NumDiscreteLevels = 0x%02x\n"
1870 " .padding = 0x%02x\n"
1871 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1872 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1873 " .SsFmin = 0x%04x\n"
1874 " .Padding_16 = 0x%04x\n",
1875 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1876 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1877 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1878 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
1879 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1880 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1881 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1882 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1883 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1884 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1885 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1886
d9811cfc 1887 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
b455159c
LG		 1888 " .VoltageMode = 0x%02x\n"
1889 " .SnapToDiscrete = 0x%02x\n"
1890 " .NumDiscreteLevels = 0x%02x\n"
1891 " .padding = 0x%02x\n"
1892 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1893 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1894 " .SsFmin = 0x%04x\n"
1895 " .Padding_16 = 0x%04x\n",
1896 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1897 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1898 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1899 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
1900 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1901 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1902 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1903 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1904 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1905 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1906 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1907
d9811cfc 1908 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
b455159c
LG		 1909 " .VoltageMode = 0x%02x\n"
1910 " .SnapToDiscrete = 0x%02x\n"
1911 " .NumDiscreteLevels = 0x%02x\n"
1912 " .padding = 0x%02x\n"
1913 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1914 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1915 " .SsFmin = 0x%04x\n"
1916 " .Padding_16 = 0x%04x\n",
1917 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1918 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1919 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1920 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
1921 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1922 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1923 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1924 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1925 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1926 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1927 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1928
d9811cfc 1929 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
b455159c
LG		 1930 " .VoltageMode = 0x%02x\n"
1931 " .SnapToDiscrete = 0x%02x\n"
1932 " .NumDiscreteLevels = 0x%02x\n"
1933 " .padding = 0x%02x\n"
1934 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1935 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1936 " .SsFmin = 0x%04x\n"
1937 " .Padding_16 = 0x%04x\n",
1938 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
1939 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
1940 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
1941 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
1942 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
1943 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
1944 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
1945 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
1946 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
1947 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
1948 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
1949
d9811cfc 1950 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
b455159c
LG		 1951 " .VoltageMode = 0x%02x\n"
1952 " .SnapToDiscrete = 0x%02x\n"
1953 " .NumDiscreteLevels = 0x%02x\n"
1954 " .padding = 0x%02x\n"
1955 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1956 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1957 " .SsFmin = 0x%04x\n"
1958 " .Padding_16 = 0x%04x\n",
1959 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
1960 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
1961 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
1962 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
1963 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
1964 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
1965 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
1966 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
1967 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
1968 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
1969 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
1970
d9811cfc 1971 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
b455159c
LG		 1972 " .VoltageMode = 0x%02x\n"
1973 " .SnapToDiscrete = 0x%02x\n"
1974 " .NumDiscreteLevels = 0x%02x\n"
1975 " .padding = 0x%02x\n"
1976 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1977 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1978 " .SsFmin = 0x%04x\n"
1979 " .Padding_16 = 0x%04x\n",
1980 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
1981 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
1982 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
1983 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
1984 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
1985 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
1986 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
1987 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
1988 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
1989 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
1990 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
1991
d9811cfc 1992 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
b455159c
LG		 1993 " .VoltageMode = 0x%02x\n"
1994 " .SnapToDiscrete = 0x%02x\n"
1995 " .NumDiscreteLevels = 0x%02x\n"
1996 " .padding = 0x%02x\n"
1997 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1998 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1999 " .SsFmin = 0x%04x\n"
2000 " .Padding_16 = 0x%04x\n",
2001 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2002 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2003 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2004 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2005 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2006 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2007 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2008 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2009 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2010 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2011 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2012
d9811cfc 2013 dev_info(smu->adev->dev, "FreqTableGfx\n");
b455159c 2014 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
d9811cfc 2015 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
b455159c 2016
d9811cfc 2017 dev_info(smu->adev->dev, "FreqTableVclk\n");
b455159c 2018 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
d9811cfc 2019 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
b455159c 2020
d9811cfc 2021 dev_info(smu->adev->dev, "FreqTableDclk\n");
b455159c 2022 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
d9811cfc 2023 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
b455159c 2024
d9811cfc 2025 dev_info(smu->adev->dev, "FreqTableSocclk\n");
b455159c 2026 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
d9811cfc 2027 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
b455159c 2028
d9811cfc 2029 dev_info(smu->adev->dev, "FreqTableUclk\n");
b455159c 2030 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 2031 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
b455159c 2032
d9811cfc 2033 dev_info(smu->adev->dev, "FreqTableFclk\n");
b455159c 2034 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
d9811cfc
EQ		 2035 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2036
2037 dev_info(smu->adev->dev, "Paddingclks[0] = 0x%x\n", pptable->Paddingclks[0]);
2038 dev_info(smu->adev->dev, "Paddingclks[1] = 0x%x\n", pptable->Paddingclks[1]);
2039 dev_info(smu->adev->dev, "Paddingclks[2] = 0x%x\n", pptable->Paddingclks[2]);
2040 dev_info(smu->adev->dev, "Paddingclks[3] = 0x%x\n", pptable->Paddingclks[3]);
2041 dev_info(smu->adev->dev, "Paddingclks[4] = 0x%x\n", pptable->Paddingclks[4]);
2042 dev_info(smu->adev->dev, "Paddingclks[5] = 0x%x\n", pptable->Paddingclks[5]);
2043 dev_info(smu->adev->dev, "Paddingclks[6] = 0x%x\n", pptable->Paddingclks[6]);
2044 dev_info(smu->adev->dev, "Paddingclks[7] = 0x%x\n", pptable->Paddingclks[7]);
2045 dev_info(smu->adev->dev, "Paddingclks[8] = 0x%x\n", pptable->Paddingclks[8]);
2046 dev_info(smu->adev->dev, "Paddingclks[9] = 0x%x\n", pptable->Paddingclks[9]);
2047 dev_info(smu->adev->dev, "Paddingclks[10] = 0x%x\n", pptable->Paddingclks[10]);
2048 dev_info(smu->adev->dev, "Paddingclks[11] = 0x%x\n", pptable->Paddingclks[11]);
2049 dev_info(smu->adev->dev, "Paddingclks[12] = 0x%x\n", pptable->Paddingclks[12]);
2050 dev_info(smu->adev->dev, "Paddingclks[13] = 0x%x\n", pptable->Paddingclks[13]);
2051 dev_info(smu->adev->dev, "Paddingclks[14] = 0x%x\n", pptable->Paddingclks[14]);
2052 dev_info(smu->adev->dev, "Paddingclks[15] = 0x%x\n", pptable->Paddingclks[15]);
2053
2054 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2055 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2056 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2057 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2058 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2059 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2060 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2061 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2062 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2063
2064 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
b455159c 2065 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 2066 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
b455159c 2067
d9811cfc
EQ		 2068 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2069 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
b455159c 2070
d9811cfc 2071 dev_info(smu->adev->dev, "Mp0clkFreq\n");
b455159c 2072 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc 2073 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
b455159c 2074
d9811cfc 2075 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
b455159c 2076 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc 2077 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
b455159c 2078
d9811cfc 2079 dev_info(smu->adev->dev, "MemVddciVoltage\n");
b455159c 2080 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 2081 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
b455159c 2082
d9811cfc 2083 dev_info(smu->adev->dev, "MemMvddVoltage\n");
b455159c 2084 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc
EQ		 2085 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2086
2087 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2088 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2089 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2090 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2091 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2092
2093 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2094
2095 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2096 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2097 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2098 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2099 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2100 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2101 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2102 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2103 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2104 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2105 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2106
2107 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2108 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2109 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2110 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2111 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2112 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2113
2114 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2115 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2116 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2117 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2118 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2119
2120 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
b455159c 2121 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
d9811cfc 2122 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
b455159c 2123
d9811cfc
EQ		 2124 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2125 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2126 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2127 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
b455159c 2128
d9811cfc 2129 dev_info(smu->adev->dev, "UclkDpmPstates\n");
b455159c 2130 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 2131 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
b455159c 2132
d9811cfc
EQ		 2133 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2134 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
b455159c 2135 pptable->UclkDpmSrcFreqRange.Fmin);
d9811cfc 2136 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
b455159c 2137 pptable->UclkDpmSrcFreqRange.Fmax);
d9811cfc
EQ		 2138 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2139 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
b455159c 2140 pptable->UclkDpmTargFreqRange.Fmin);
d9811cfc 2141 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
b455159c 2142 pptable->UclkDpmTargFreqRange.Fmax);
d9811cfc
EQ		 2143 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2144 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
b455159c 2145
d9811cfc 2146 dev_info(smu->adev->dev, "PcieGenSpeed\n");
b455159c 2147 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 2148 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
b455159c 2149
d9811cfc 2150 dev_info(smu->adev->dev, "PcieLaneCount\n");
b455159c 2151 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 2152 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
b455159c 2153
d9811cfc 2154 dev_info(smu->adev->dev, "LclkFreq\n");
b455159c 2155 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 2156 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
b455159c 2157
d9811cfc
EQ		 2158 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2159 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
b455159c 2160
d9811cfc 2161 dev_info(smu->adev->dev, "FanGain\n");
b455159c 2162 for (i = 0; i < TEMP_COUNT; i++)
d9811cfc
EQ		 2163 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2164
2165 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2166 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2167 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2168 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2169 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2170 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2171 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2172 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2173 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2174 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2175 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2176 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2177
2178 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2179 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2180 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2181 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2182
2183 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2184 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2185 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2186 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2187
2188 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2189 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2190 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2191 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
d9811cfc 2192 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2193 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2194 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2195 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
d9811cfc 2196 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2197 pptable->dBtcGbGfxPll.a,
2198 pptable->dBtcGbGfxPll.b,
2199 pptable->dBtcGbGfxPll.c);
d9811cfc 2200 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2201 pptable->dBtcGbGfxDfll.a,
2202 pptable->dBtcGbGfxDfll.b,
2203 pptable->dBtcGbGfxDfll.c);
d9811cfc 2204 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2205 pptable->dBtcGbSoc.a,
2206 pptable->dBtcGbSoc.b,
2207 pptable->dBtcGbSoc.c);
d9811cfc 2208 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
b455159c
LG		 2209 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2210 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
d9811cfc 2211 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
b455159c
LG		 2212 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2213 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2214
d9811cfc 2215 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
b455159c 2216 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
d9811cfc 2217 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
b455159c 2218 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
d9811cfc 2219 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
b455159c
LG		 2220 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2221 }
2222
d9811cfc 2223 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2224 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2225 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2226 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
d9811cfc 2227 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2228 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2229 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2230 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2231
d9811cfc
EQ		 2232 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2233 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
b455159c 2234
d9811cfc
EQ		 2235 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2236 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2237 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2238 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
b455159c 2239
d9811cfc
EQ		 2240 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2241 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2242 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2243 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
b455159c 2244
d9811cfc
EQ		 2245 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2246 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
b455159c 2247
d9811cfc 2248 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
b455159c 2249 for (i = 0; i < NUM_XGMI_LEVELS; i++)
d9811cfc
EQ		 2250 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2251 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2252 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
b455159c 2253
d9811cfc
EQ		 2254 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2255 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2256 pptable->ReservedEquation0.a,
2257 pptable->ReservedEquation0.b,
2258 pptable->ReservedEquation0.c);
d9811cfc 2259 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2260 pptable->ReservedEquation1.a,
2261 pptable->ReservedEquation1.b,
2262 pptable->ReservedEquation1.c);
d9811cfc 2263 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2264 pptable->ReservedEquation2.a,
2265 pptable->ReservedEquation2.b,
2266 pptable->ReservedEquation2.c);
d9811cfc 2267 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2268 pptable->ReservedEquation3.a,
2269 pptable->ReservedEquation3.b,
2270 pptable->ReservedEquation3.c);
2271
d9811cfc
EQ		 2272 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2273 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2274 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2275 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2276 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2277 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2278 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2279 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2280 dev_info(smu->adev->dev, "SkuReserved[8] = 0x%x\n", pptable->SkuReserved[8]);
d9811cfc
EQ		 2281
2282 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2283 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2284 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2285 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2286 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2287 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
b455159c
LG		 2288
2289 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
d9811cfc
EQ		 2290 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2291 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
b455159c 2292 pptable->I2cControllers[i].Enabled);
d9811cfc 2293 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
b455159c 2294 pptable->I2cControllers[i].Speed);
d9811cfc 2295 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
b455159c 2296 pptable->I2cControllers[i].SlaveAddress);
d9811cfc 2297 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
b455159c 2298 pptable->I2cControllers[i].ControllerPort);
d9811cfc 2299 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
b455159c 2300 pptable->I2cControllers[i].ControllerName);
d9811cfc 2301 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
b455159c 2302 pptable->I2cControllers[i].ThermalThrotter);
d9811cfc 2303 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
b455159c 2304 pptable->I2cControllers[i].I2cProtocol);
d9811cfc 2305 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
b455159c
LG		 2306 pptable->I2cControllers[i].PaddingConfig);
2307 }
2308
d9811cfc
EQ		 2309 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2310 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2311 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2312 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2313
2314 dev_info(smu->adev->dev, "Board Parameters:\n");
2315 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2316 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2317 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2318 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2319 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2320 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2321 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2322 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2323
2324 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2325 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2326 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2327
2328 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2329 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2330 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2331
2332 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2333 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2334 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2335
2336 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2337 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2338 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2339
2340 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2341
2342 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2343 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2344 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2345 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2346 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2347 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2348 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2349 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2350 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2351 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2352 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2353 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2354 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2355 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2356 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2357 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2358
2359 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2360 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2361 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
2362
2363 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2364 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2365 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
2366
f0f3d68e 2367 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
d9811cfc
EQ		 2368 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2369
2370 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2371 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2372 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2373
2374 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2375 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2376 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2377 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2378 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2379
2380 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2381 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2382
2383 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
b455159c 2384 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 2385 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2386 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
b455159c 2387 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 2388 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2389 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
b455159c 2390 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 2391 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2392 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
b455159c 2393 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 2394 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2395
2396 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2397 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2398 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2399 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2400
2401 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2402 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2403 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2404 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2405 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2406 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2407 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2408 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2409 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2410 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2411 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
d9811cfc
EQ		 2412
2413 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2414 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2415 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2416 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2417 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2418 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2419 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2420 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
b455159c
LG		 2421}
2422
bc50ca29
AD		 2423static void sienna_cichlid_fill_i2c_req(SwI2cRequest_t *req, bool write,
2424 uint8_t address, uint32_t numbytes,
2425 uint8_t *data)
2426{
2427 int i;
2428
bc50ca29
AD		 2429 req->I2CcontrollerPort = 0;
2430 req->I2CSpeed = 2;
2431 req->SlaveAddress = address;
2432 req->NumCmds = numbytes;
2433
2434 for (i = 0; i < numbytes; i++) {
2435 SwI2cCmd_t *cmd = &req->SwI2cCmds[i];
2436
2437 /* First 2 bytes are always write for lower 2b EEPROM address */
2438 if (i < 2)
2439 cmd->CmdConfig = CMDCONFIG_READWRITE_MASK;
2440 else
2441 cmd->CmdConfig = write ? CMDCONFIG_READWRITE_MASK : 0;
2442
2443
2444 /* Add RESTART for read after address filled */
2445 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
2446
2447 /* Add STOP in the end */
2448 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
2449
2450 /* Fill with data regardless if read or write to simplify code */
2451 cmd->ReadWriteData = data[i];
2452 }
2453}
2454
2455static int sienna_cichlid_i2c_read_data(struct i2c_adapter *control,
2456 uint8_t address,
2457 uint8_t *data,
2458 uint32_t numbytes)
2459{
2460 uint32_t i, ret = 0;
2461 SwI2cRequest_t req;
2462 struct amdgpu_device *adev = to_amdgpu_device(control);
2463 struct smu_table_context *smu_table = &adev->smu.smu_table;
2464 struct smu_table *table = &smu_table->driver_table;
2465
d74a09c8
AD		 2466 if (numbytes > MAX_SW_I2C_COMMANDS) {
2467 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
2468 numbytes, MAX_SW_I2C_COMMANDS);
2469 return -EINVAL;
2470 }
2471
bc50ca29
AD		 2472 memset(&req, 0, sizeof(req));
2473 sienna_cichlid_fill_i2c_req(&req, false, address, numbytes, data);
2474
2475 mutex_lock(&adev->smu.mutex);
2476 /* Now read data starting with that address */
2477 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
2478 true);
2479 mutex_unlock(&adev->smu.mutex);
2480
2481 if (!ret) {
2482 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
2483
2484 /* Assume SMU fills res.SwI2cCmds[i].Data with read bytes */
2485 for (i = 0; i < numbytes; i++)
2486 data[i] = res->SwI2cCmds[i].ReadWriteData;
2487
2488 dev_dbg(adev->dev, "sienna_cichlid_i2c_read_data, address = %x, bytes = %d, data :",
2489 (uint16_t)address, numbytes);
2490
2491 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2492 8, 1, data, numbytes, false);
2493 } else
2494 dev_err(adev->dev, "sienna_cichlid_i2c_read_data - error occurred :%x", ret);
2495
2496 return ret;
2497}
2498
2499static int sienna_cichlid_i2c_write_data(struct i2c_adapter *control,
2500 uint8_t address,
2501 uint8_t *data,
2502 uint32_t numbytes)
2503{
2504 uint32_t ret;
2505 SwI2cRequest_t req;
2506 struct amdgpu_device *adev = to_amdgpu_device(control);
2507
d74a09c8
AD		 2508 if (numbytes > MAX_SW_I2C_COMMANDS) {
2509 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
2510 numbytes, MAX_SW_I2C_COMMANDS);
2511 return -EINVAL;
2512 }
2513
bc50ca29
AD		 2514 memset(&req, 0, sizeof(req));
2515 sienna_cichlid_fill_i2c_req(&req, true, address, numbytes, data);
2516
2517 mutex_lock(&adev->smu.mutex);
2518 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
2519 mutex_unlock(&adev->smu.mutex);
2520
2521 if (!ret) {
2522 dev_dbg(adev->dev, "sienna_cichlid_i2c_write(), address = %x, bytes = %d , data: ",
2523 (uint16_t)address, numbytes);
2524
2525 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2526 8, 1, data, numbytes, false);
2527 /*
2528 * According to EEPROM spec there is a MAX of 10 ms required for
2529 * EEPROM to flush internal RX buffer after STOP was issued at the
2530 * end of write transaction. During this time the EEPROM will not be
2531 * responsive to any more commands - so wait a bit more.
2532 */
2533 msleep(10);
2534
2535 } else
2536 dev_err(adev->dev, "sienna_cichlid_i2c_write- error occurred :%x", ret);
2537
2538 return ret;
2539}
2540
2541static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
2542 struct i2c_msg *msgs, int num)
2543{
2544 uint32_t i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
2545 uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
2546
2547 for (i = 0; i < num; i++) {
2548 /*
2549 * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
2550 * once and hence the data needs to be spliced into chunks and sent each
2551 * chunk separately
2552 */
2553 data_size = msgs[i].len - 2;
2554 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
2555 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
2556 data_ptr = msgs[i].buf + 2;
2557
2558 for (j = 0; j < data_size / data_chunk_size; j++) {
2559 /* Insert the EEPROM dest addess, bits 0-15 */
2560 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2561 data_chunk[1] = (next_eeprom_addr & 0xff);
2562
2563 if (msgs[i].flags & I2C_M_RD) {
2564 ret = sienna_cichlid_i2c_read_data(i2c_adap,
2565 (uint8_t)msgs[i].addr,
2566 data_chunk, MAX_SW_I2C_COMMANDS);
2567
2568 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
2569 } else {
2570
2571 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
2572
2573 ret = sienna_cichlid_i2c_write_data(i2c_adap,
2574 (uint8_t)msgs[i].addr,
2575 data_chunk, MAX_SW_I2C_COMMANDS);
2576 }
2577
2578 if (ret) {
2579 num = -EIO;
2580 goto fail;
2581 }
2582
2583 next_eeprom_addr += data_chunk_size;
2584 data_ptr += data_chunk_size;
2585 }
2586
2587 if (data_size % data_chunk_size) {
2588 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2589 data_chunk[1] = (next_eeprom_addr & 0xff);
2590
2591 if (msgs[i].flags & I2C_M_RD) {
2592 ret = sienna_cichlid_i2c_read_data(i2c_adap,
2593 (uint8_t)msgs[i].addr,
2594 data_chunk, (data_size % data_chunk_size) + 2);
2595
2596 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2597 } else {
2598 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2599
2600 ret = sienna_cichlid_i2c_write_data(i2c_adap,
2601 (uint8_t)msgs[i].addr,
2602 data_chunk, (data_size % data_chunk_size) + 2);
2603 }
2604
2605 if (ret) {
2606 num = -EIO;
2607 goto fail;
2608 }
2609 }
2610 }
2611
2612fail:
2613 return num;
2614}
2615
2616static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
2617{
2618 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2619}
2620
2621
2622static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
2623 .master_xfer = sienna_cichlid_i2c_xfer,
2624 .functionality = sienna_cichlid_i2c_func,
2625};
2626
bc50ca29
AD		 2627static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2628{
2629 struct amdgpu_device *adev = to_amdgpu_device(control);
2630 int res;
2631
bc50ca29
AD		 2632 control->owner = THIS_MODULE;
2633 control->class = I2C_CLASS_SPD;
2634 control->dev.parent = &adev->pdev->dev;
2635 control->algo = &sienna_cichlid_i2c_algo;
2636 snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2637
2638 res = i2c_add_adapter(control);
2639 if (res)
2640 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2641
2642 return res;
2643}
2644
2645static void sienna_cichlid_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2646{
bc50ca29
AD		 2647 i2c_del_adapter(control);
2648}
2649
8ca78a0a
EQ		 2650static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
2651 void **table)
2652{
2653 struct smu_table_context *smu_table = &smu->smu_table;
2654 struct gpu_metrics_v1_0 *gpu_metrics =
2655 (struct gpu_metrics_v1_0 *)smu_table->gpu_metrics_table;
2656 SmuMetrics_t metrics;
2657 int ret = 0;
2658
fceafc9b
EQ		 2659 ret = smu_cmn_get_metrics_table(smu,
2660 &metrics,
2661 true);
60ae4d67 2662 if (ret)
8ca78a0a 2663 return ret;
8ca78a0a
EQ		 2664
2665 smu_v11_0_init_gpu_metrics_v1_0(gpu_metrics);
2666
2667 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2668 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2669 gpu_metrics->temperature_mem = metrics.TemperatureMem;
2670 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2671 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2672 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2673
2674 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2675 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2676 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2677
2678 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2679 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2680
2681 if (metrics.AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
2682 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
2683 else
2684 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
2685 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
2686 gpu_metrics->average_vclk0_frequency = metrics.AverageVclk0Frequency;
2687 gpu_metrics->average_dclk0_frequency = metrics.AverageDclk0Frequency;
2688 gpu_metrics->average_vclk1_frequency = metrics.AverageVclk1Frequency;
2689 gpu_metrics->average_dclk1_frequency = metrics.AverageDclk1Frequency;
2690
2691 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2692 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2693 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2694 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK_0];
2695 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK_0];
2696 gpu_metrics->current_vclk1 = metrics.CurrClock[PPCLK_VCLK_1];
2697 gpu_metrics->current_dclk1 = metrics.CurrClock[PPCLK_DCLK_1];
2698
2699 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2700
2701 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2702
2703 gpu_metrics->pcie_link_width =
2704 smu_v11_0_get_current_pcie_link_width(smu);
2705 gpu_metrics->pcie_link_speed =
2706 smu_v11_0_get_current_pcie_link_speed(smu);
2707
2708 *table = (void *)gpu_metrics;
2709
2710 return sizeof(struct gpu_metrics_v1_0);
2711}
bc50ca29 2712
05f39286
EQ		 2713static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
2714{
2715 return smu_cmn_send_smc_msg_with_param(smu,
2716 SMU_MSG_SetMGpuFanBoostLimitRpm,
2717 0,
2718 NULL);
2719}
2720
76c71f00
EQ		 2721static int sienna_cichlid_gpo_control(struct smu_context *smu,
2722 bool enablement)
2723{
2724 int ret = 0;
2725
2726 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
2727 if (enablement)
2728 ret = smu_cmn_send_smc_msg_with_param(smu,
2729 SMU_MSG_SetGpoFeaturePMask,
2730 GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
2731 NULL);
2732 else
2733 ret = smu_cmn_send_smc_msg_with_param(smu,
2734 SMU_MSG_SetGpoFeaturePMask,
2735 0,
2736 NULL);
2737 }
2738
2739 return ret;
2740}
b455159c 2741static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
b455159c
LG		 2742 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
2743 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
f6b4b4a1 2744 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
6fb176a7 2745 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
bc50ca29
AD		 2746 .i2c_init = sienna_cichlid_i2c_control_init,
2747 .i2c_fini = sienna_cichlid_i2c_control_fini,
b455159c
LG		 2748 .print_clk_levels = sienna_cichlid_print_clk_levels,
2749 .force_clk_levels = sienna_cichlid_force_clk_levels,
2750 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
b455159c
LG		 2751 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
2752 .display_config_changed = sienna_cichlid_display_config_changed,
2753 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
b455159c 2754 .is_dpm_running = sienna_cichlid_is_dpm_running,
b455159c
LG		 2755 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
2756 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
2757 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
b455159c
LG		 2758 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
2759 .read_sensor = sienna_cichlid_read_sensor,
2760 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
b2785e25 2761 .set_performance_level = smu_v11_0_set_performance_level,
b455159c
LG		 2762 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
2763 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
2764 .get_power_limit = sienna_cichlid_get_power_limit,
08ccfe08 2765 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
b455159c
LG		 2766 .dump_pptable = sienna_cichlid_dump_pptable,
2767 .init_microcode = smu_v11_0_init_microcode,
2768 .load_microcode = smu_v11_0_load_microcode,
c1b353b7 2769 .init_smc_tables = sienna_cichlid_init_smc_tables,
b455159c
LG		 2770 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2771 .init_power = smu_v11_0_init_power,
2772 .fini_power = smu_v11_0_fini_power,
2773 .check_fw_status = smu_v11_0_check_fw_status,
4a13b4ce 2774 .setup_pptable = sienna_cichlid_setup_pptable,
b455159c 2775 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
b455159c 2776 .check_fw_version = smu_v11_0_check_fw_version,
caad2613 2777 .write_pptable = smu_cmn_write_pptable,
b455159c
LG		 2778 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2779 .set_tool_table_location = smu_v11_0_set_tool_table_location,
2780 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2781 .system_features_control = smu_v11_0_system_features_control,
66c86828
EQ		 2782 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2783 .send_smc_msg = smu_cmn_send_smc_msg,
31157341 2784 .init_display_count = NULL,
b455159c 2785 .set_allowed_mask = smu_v11_0_set_allowed_mask,
28251d72 2786 .get_enabled_mask = smu_cmn_get_enabled_mask,
b4bb3aaf 2787 .feature_is_enabled = smu_cmn_feature_is_enabled,
af5ba6d2 2788 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
31157341 2789 .notify_display_change = NULL,
b455159c 2790 .set_power_limit = smu_v11_0_set_power_limit,
b455159c
LG		 2791 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2792 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2793 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
ce63d8f8 2794 .set_min_dcef_deep_sleep = NULL,
b455159c
LG		 2795 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2796 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2797 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
b455159c
LG		 2798 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2799 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2800 .gfx_off_control = smu_v11_0_gfx_off_control,
2801 .register_irq_handler = smu_v11_0_register_irq_handler,
2802 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2803 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
40d3b8db 2804 .baco_is_support= sienna_cichlid_is_baco_supported,
b455159c
LG		 2805 .baco_get_state = smu_v11_0_baco_get_state,
2806 .baco_set_state = smu_v11_0_baco_set_state,
2807 .baco_enter = smu_v11_0_baco_enter,
2808 .baco_exit = smu_v11_0_baco_exit,
ea8139d8
WS		 2809 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
2810 .mode1_reset = smu_v11_0_mode1_reset,
258d290c 2811 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
10e96d89 2812 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
66b8a9c0 2813 .run_btc = sienna_cichlid_run_btc,
7dbf7805
EQ		 2814 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2815 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
8ca78a0a 2816 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
05f39286 2817 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
e988026f 2818 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
5ce99853 2819 .deep_sleep_control = smu_v11_0_deep_sleep_control,
3204ff3e 2820 .get_fan_parameters = sienna_cichlid_get_fan_parameters,
234676d6 2821 .interrupt_work = smu_v11_0_interrupt_work,
76c71f00 2822 .gpo_control = sienna_cichlid_gpo_control,
b455159c
LG		 2823};
2824
2825void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
2826{
2827 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
6c339f37
EQ		 2828 smu->message_map = sienna_cichlid_message_map;
2829 smu->clock_map = sienna_cichlid_clk_map;
2830 smu->feature_map = sienna_cichlid_feature_mask_map;
2831 smu->table_map = sienna_cichlid_table_map;
2832 smu->pwr_src_map = sienna_cichlid_pwr_src_map;
2833 smu->workload_map = sienna_cichlid_workload_map;
b455159c 2834}
Linux 6.x block layer and io_uring tree(s)