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Merge tag 'amd-drm-next-6.1-2022-09-08' of https://gitlab.freedesktop.org/agd5f/linux...
[linux-2.6-block.git] / drivers / gpu / drm / amd / pm / swsmu / smu11 / sienna_cichlid_ppt.c
CommitLineData
b455159c
LG		 1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
d8e0b16d
EQ		 24#define SWSMU_CODE_LAYER_L2
25
b455159c
LG		 26#include <linux/firmware.h>
27#include <linux/pci.h>
bc50ca29 28#include <linux/i2c.h>
b455159c 29#include "amdgpu.h"
2f60dd50 30#include "amdgpu_dpm.h"
b455159c 31#include "amdgpu_smu.h"
b455159c
LG		 32#include "atomfirmware.h"
33#include "amdgpu_atomfirmware.h"
22f2447c 34#include "amdgpu_atombios.h"
b455159c
LG		 35#include "smu_v11_0.h"
36#include "smu11_driver_if_sienna_cichlid.h"
37#include "soc15_common.h"
38#include "atom.h"
39#include "sienna_cichlid_ppt.h"
e05acd78 40#include "smu_v11_0_7_pptable.h"
b455159c 41#include "smu_v11_0_7_ppsmc.h"
40d3b8db 42#include "nbio/nbio_2_3_offset.h"
b7d25b5f 43#include "nbio/nbio_2_3_sh_mask.h"
e05acd78
LG		 44#include "thm/thm_11_0_2_offset.h"
45#include "thm/thm_11_0_2_sh_mask.h"
ea8139d8
WS		 46#include "mp/mp_11_0_offset.h"
47#include "mp/mp_11_0_sh_mask.h"
b455159c 48
6c339f37 49#include "asic_reg/mp/mp_11_0_sh_mask.h"
3ddd0c90 50#include "amdgpu_ras.h"
6c339f37
EQ		 51#include "smu_cmn.h"
52
55084d7f
EQ		 53/*
54 * DO NOT use these for err/warn/info/debug messages.
55 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
56 * They are more MGPU friendly.
57 */
58#undef pr_err
59#undef pr_warn
60#undef pr_info
61#undef pr_debug
62
b455159c
LG		 63#define FEATURE_MASK(feature) (1ULL << feature)
64#define SMC_DPM_FEATURE ( \
65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
fea905d4 66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65297d50 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
5cb74353 68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
4cd4f45b 69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
5f338f70 70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
ce7e5a6e
JC		 71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \
72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
b455159c 73
d817f375
LG		 74#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
75
7077b19a 76#define GET_PPTABLE_MEMBER(field, member) do {\
1d789535 77 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))\
7077b19a
CG		 78 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
79 else\
80 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
81} while(0)
82
db5b5c67
AG		 83/* STB FIFO depth is in 64bit units */
84#define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES 8
85
3ddd0c90 86/*
87 * SMU support ECCTABLE since version 58.70.0,
88 * use this to check whether ECCTABLE feature is supported.
89 */
90#define SUPPORT_ECCTABLE_SMU_VERSION 0x003a4600
91
7077b19a
CG		 92static int get_table_size(struct smu_context *smu)
93{
1d789535 94 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
7077b19a
CG		 95 return sizeof(PPTable_beige_goby_t);
96 else
97 return sizeof(PPTable_t);
98}
99
6c339f37
EQ		 100static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
101 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
102 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
103 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
91190db1
LG		 104 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
105 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
106 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
107 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
6c339f37
EQ		 108 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
109 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
110 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
111 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
112 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
113 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
114 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
91190db1 115 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
4215a119
HC		 116 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
117 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
91190db1
LG		 118 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
119 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
4215a119 120 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
91190db1
LG		 121 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
122 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
66b8a9c0 123 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
91190db1 124 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
4215a119
HC		 125 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
126 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
6c339f37 127 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
91190db1 128 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
6c339f37
EQ		 129 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
130 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
131 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
91190db1
LG		 132 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
133 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
134 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
135 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
136 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
137 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
138 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
139 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
6c339f37 140 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
91190db1
LG		 141 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
142 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
40f1dc52 143 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
6c339f37 144 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
91190db1
LG		 145 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
146 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
147 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
148 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
149 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
150 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
151 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
152 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
05f39286 153 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
76c71f00 154 MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0),
ac7804bb 155 MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0),
88dfd5d5 156 MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0),
672c0218 157 MSG_MAP(DriverMode2Reset, PPSMC_MSG_DriverMode2Reset, 0),
b455159c
LG		 158};
159
6c339f37 160static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
b455159c
LG		 161 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
162 CLK_MAP(SCLK, PPCLK_GFXCLK),
163 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
164 CLK_MAP(FCLK, PPCLK_FCLK),
165 CLK_MAP(UCLK, PPCLK_UCLK),
166 CLK_MAP(MCLK, PPCLK_UCLK),
167 CLK_MAP(DCLK, PPCLK_DCLK_0),
9c0551f2
JC		 168 CLK_MAP(DCLK1, PPCLK_DCLK_1),
169 CLK_MAP(VCLK, PPCLK_VCLK_0),
b455159c
LG		 170 CLK_MAP(VCLK1, PPCLK_VCLK_1),
171 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
172 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
173 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
174 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
175};
176
6c339f37 177static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
b455159c
LG		 178 FEA_MAP(DPM_PREFETCHER),
179 FEA_MAP(DPM_GFXCLK),
31cb0dd9 180 FEA_MAP(DPM_GFX_GPO),
b455159c 181 FEA_MAP(DPM_UCLK),
e9073b43 182 FEA_MAP(DPM_FCLK),
b455159c
LG		 183 FEA_MAP(DPM_SOCCLK),
184 FEA_MAP(DPM_MP0CLK),
185 FEA_MAP(DPM_LINK),
186 FEA_MAP(DPM_DCEFCLK),
e9073b43 187 FEA_MAP(DPM_XGMI),
b455159c
LG		 188 FEA_MAP(MEM_VDDCI_SCALING),
189 FEA_MAP(MEM_MVDD_SCALING),
190 FEA_MAP(DS_GFXCLK),
191 FEA_MAP(DS_SOCCLK),
e9073b43 192 FEA_MAP(DS_FCLK),
b455159c
LG		 193 FEA_MAP(DS_LCLK),
194 FEA_MAP(DS_DCEFCLK),
195 FEA_MAP(DS_UCLK),
196 FEA_MAP(GFX_ULV),
197 FEA_MAP(FW_DSTATE),
198 FEA_MAP(GFXOFF),
199 FEA_MAP(BACO),
6fb176a7 200 FEA_MAP(MM_DPM_PG),
b455159c
LG		 201 FEA_MAP(RSMU_SMN_CG),
202 FEA_MAP(PPT),
203 FEA_MAP(TDC),
204 FEA_MAP(APCC_PLUS),
205 FEA_MAP(GTHR),
206 FEA_MAP(ACDC),
207 FEA_MAP(VR0HOT),
208 FEA_MAP(VR1HOT),
209 FEA_MAP(FW_CTF),
210 FEA_MAP(FAN_CONTROL),
211 FEA_MAP(THERMAL),
212 FEA_MAP(GFX_DCS),
213 FEA_MAP(RM),
214 FEA_MAP(LED_DISPLAY),
215 FEA_MAP(GFX_SS),
216 FEA_MAP(OUT_OF_BAND_MONITOR),
217 FEA_MAP(TEMP_DEPENDENT_VMIN),
218 FEA_MAP(MMHUB_PG),
219 FEA_MAP(ATHUB_PG),
cf06331f 220 FEA_MAP(APCC_DFLL),
b455159c
LG		 221};
222
6c339f37 223static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
b455159c
LG		 224 TAB_MAP(PPTABLE),
225 TAB_MAP(WATERMARKS),
226 TAB_MAP(AVFS_PSM_DEBUG),
227 TAB_MAP(AVFS_FUSE_OVERRIDE),
228 TAB_MAP(PMSTATUSLOG),
229 TAB_MAP(SMU_METRICS),
230 TAB_MAP(DRIVER_SMU_CONFIG),
231 TAB_MAP(ACTIVITY_MONITOR_COEFF),
232 TAB_MAP(OVERDRIVE),
233 TAB_MAP(I2C_COMMANDS),
234 TAB_MAP(PACE),
3ddd0c90 235 TAB_MAP(ECCINFO),
b455159c
LG		 236};
237
6c339f37 238static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
1d5ca713
LG		 239 PWR_MAP(AC),
240 PWR_MAP(DC),
241};
242
6c339f37 243static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
b455159c
LG		 244 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
245 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
246 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
247 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
248 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
4c4d5a49 249 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
b455159c
LG		 250 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
251};
252
f06d9511
GS		 253static const uint8_t sienna_cichlid_throttler_map[] = {
254 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
255 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
256 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
257 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
258 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
259 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
260 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
261 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
262 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
263 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
264 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
265 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
266 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
267 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
268 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
269 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
270 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
271 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
272};
273
b455159c
LG		 274static int
275sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
276 uint32_t *feature_mask, uint32_t num)
277{
fea905d4
LG		 278 struct amdgpu_device *adev = smu->adev;
279
b455159c
LG		 280 if (num > 2)
281 return -EINVAL;
282
283 memset(feature_mask, 0, sizeof(uint32_t) * num);
284
4cd4f45b 285 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
15dbe18f 286 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
ce7e5a6e 287 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
094cdf15 288 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
5f338f70 289 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
86a9eb3f 290 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
80c36f86 291 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
9aa60213
LG		 292 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
293 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
d28f4aa1 294 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
20d71dcc 295 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
d0d71970 296 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
886c8bc6
LG		 297 | FEATURE_MASK(FEATURE_PPT_BIT)
298 | FEATURE_MASK(FEATURE_TDC_BIT)
3fc006f5 299 | FEATURE_MASK(FEATURE_BACO_BIT)
cf06331f 300 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
35ed946c 301 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
1c58d429 302 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
b971df70
LG		 303 | FEATURE_MASK(FEATURE_THERMAL_BIT)
304 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
fea905d4 305
c96721eb 306 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
fea905d4 307 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
c96721eb
KF		 308 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
309 }
fea905d4 310
680602d6 311 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
1d789535 312 (adev->ip_versions[MP1_HWIP][0] > IP_VERSION(11, 0, 7)) &&
680602d6
KF		 313 !(adev->flags & AMD_IS_APU))
314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
315
65297d50 316 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
fc17cd3f
LG		 317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
318 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
319 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
65297d50 320
5cb74353
LG		 321 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
322 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
323
5f338f70
LG		 324 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
325 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
326
fea905d4
LG		 327 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
328 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
b455159c 329
62c1ea6b
LG		 330 if (adev->pm.pp_feature & PP_ULV_MASK)
331 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
332
02bb391d
LG		 333 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
334 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
335
e0da123a
LG		 336 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
337 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
338
b794616d
KF		 339 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
340 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
341
846938c2
KF		 342 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
343 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
344
6fb176a7
LG		 345 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
346 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
347 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
348
62826b86
KF		 349 if (smu->dc_controlled_by_gpio)
350 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
351
0ab5d711 352 if (amdgpu_device_should_use_aspm(adev))
6ef28889
KF		 353 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
354
b455159c
LG		 355 return 0;
356}
357
458020dd 358static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
b455159c 359{
4a13b4ce 360 struct smu_table_context *table_context = &smu->smu_table;
e05acd78 361 struct smu_11_0_7_powerplay_table *powerplay_table =
4a13b4ce
EQ		 362 table_context->power_play_table;
363 struct smu_baco_context *smu_baco = &smu->smu_baco;
458020dd
LL		 364 struct amdgpu_device *adev = smu->adev;
365 uint32_t val;
366
1b41d67e 367 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) {
458020dd
LL		 368 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
369 smu_baco->platform_support =
370 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
371 false;
372 }
373}
374
57301181
ES		 375static void sienna_cichlid_check_fan_support(struct smu_context *smu)
376{
377 struct smu_table_context *table_context = &smu->smu_table;
378 PPTable_t *pptable = table_context->driver_pptable;
379 uint64_t features = *(uint64_t *) pptable->FeaturesToRun;
380
381 /* Fan control is not possible if PPTable has it disabled */
382 smu->adev->pm.no_fan =
383 !(features & (1ULL << FEATURE_FAN_CONTROL_BIT));
384 if (smu->adev->pm.no_fan)
385 dev_info_once(smu->adev->dev,
386 "PMFW based fan control disabled");
387}
388
458020dd
LL		 389static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
390{
391 struct smu_table_context *table_context = &smu->smu_table;
392 struct smu_11_0_7_powerplay_table *powerplay_table =
393 table_context->power_play_table;
4a13b4ce 394
18a4b3de
EQ		 395 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
396 smu->dc_controlled_by_gpio = true;
397
458020dd 398 sienna_cichlid_check_bxco_support(smu);
57301181 399 sienna_cichlid_check_fan_support(smu);
4a13b4ce
EQ		 400
401 table_context->thermal_controller_type =
402 powerplay_table->thermal_controller_type;
403
aa75fa34
EQ		 404 /*
405 * Instead of having its own buffer space and get overdrive_table copied,
406 * smu->od_settings just points to the actual overdrive_table
407 */
408 smu->od_settings = &powerplay_table->overdrive_table;
409
b455159c
LG		 410 return 0;
411}
412
413static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
414{
dccc7c21
LG		 415 struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
416 int index, ret;
7077b19a 417 I2cControllerConfig_t *table_member;
dccc7c21
LG		 418
419 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
420 smc_dpm_info);
421
22f2447c 422 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
dccc7c21
LG		 423 (uint8_t **)&smc_dpm_table);
424 if (ret)
425 return ret;
7077b19a
CG		 426 GET_PPTABLE_MEMBER(I2cControllers, &table_member);
427 memcpy(table_member, smc_dpm_table->I2cControllers,
428 sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
20f5e6cf 429
b455159c
LG		 430 return 0;
431}
432
433static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
434{
b455159c 435 struct smu_table_context *table_context = &smu->smu_table;
e05acd78 436 struct smu_11_0_7_powerplay_table *powerplay_table =
4a13b4ce 437 table_context->power_play_table;
7077b19a 438 int table_size;
b455159c 439
7077b19a 440 table_size = get_table_size(smu);
b455159c 441 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
7077b19a 442 table_size);
b455159c 443
4a13b4ce
EQ		 444 return 0;
445}
b455159c 446
951be8be
EQ		 447static int sienna_cichlid_patch_pptable_quirk(struct smu_context *smu)
448{
449 struct amdgpu_device *adev = smu->adev;
450 uint32_t *board_reserved;
451 uint16_t *freq_table_gfx;
452 uint32_t i;
453
454 /* Fix some OEM SKU specific stability issues */
455 GET_PPTABLE_MEMBER(BoardReserved, &board_reserved);
456 if ((adev->pdev->device == 0x73DF) &&
457 (adev->pdev->revision == 0XC3) &&
458 (adev->pdev->subsystem_device == 0x16C2) &&
459 (adev->pdev->subsystem_vendor == 0x1043))
460 board_reserved[0] = 1387;
461
462 GET_PPTABLE_MEMBER(FreqTableGfx, &freq_table_gfx);
463 if ((adev->pdev->device == 0x73DF) &&
464 (adev->pdev->revision == 0XC3) &&
465 ((adev->pdev->subsystem_device == 0x16C2) ||
466 (adev->pdev->subsystem_device == 0x133C)) &&
467 (adev->pdev->subsystem_vendor == 0x1043)) {
468 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) {
469 if (freq_table_gfx[i] > 2500)
470 freq_table_gfx[i] = 2500;
471 }
472 }
473
474 return 0;
475}
476
4a13b4ce
EQ		 477static int sienna_cichlid_setup_pptable(struct smu_context *smu)
478{
479 int ret = 0;
b455159c 480
4a13b4ce
EQ		 481 ret = smu_v11_0_setup_pptable(smu);
482 if (ret)
483 return ret;
484
485 ret = sienna_cichlid_store_powerplay_table(smu);
486 if (ret)
487 return ret;
488
489 ret = sienna_cichlid_append_powerplay_table(smu);
490 if (ret)
491 return ret;
492
493 ret = sienna_cichlid_check_powerplay_table(smu);
494 if (ret)
495 return ret;
496
951be8be 497 return sienna_cichlid_patch_pptable_quirk(smu);
b455159c
LG		 498}
499
c1b353b7 500static int sienna_cichlid_tables_init(struct smu_context *smu)
b455159c
LG		 501{
502 struct smu_table_context *smu_table = &smu->smu_table;
c1b353b7 503 struct smu_table *tables = smu_table->tables;
7077b19a 504 int table_size;
b455159c 505
7077b19a
CG		 506 table_size = get_table_size(smu);
507 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
508 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c
LG		 509 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
510 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b4b0b79d 511 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
b455159c 512 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
bc50ca29
AD		 513 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
514 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c
LG		 515 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
516 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
517 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
518 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
519 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
f9e3fe46 520 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
b455159c 521 AMDGPU_GEM_DOMAIN_VRAM);
3ddd0c90 522 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
523 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
816d61d5
EQ		 524 SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfigExternal_t),
525 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c 526
b4b0b79d 527 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
b455159c 528 if (!smu_table->metrics_table)
8ca78a0a 529 goto err0_out;
b455159c
LG		 530 smu_table->metrics_time = 0;
531
f06d9511 532 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
8ca78a0a
EQ		 533 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
534 if (!smu_table->gpu_metrics_table)
535 goto err1_out;
536
40d3b8db
LG		 537 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
538 if (!smu_table->watermarks_table)
8ca78a0a 539 goto err2_out;
40d3b8db 540
3ddd0c90 541 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
542 if (!smu_table->ecc_table)
816d61d5
EQ		 543 goto err3_out;
544
545 smu_table->driver_smu_config_table =
546 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL);
547 if (!smu_table->driver_smu_config_table)
548 goto err4_out;
3ddd0c90 549
b455159c 550 return 0;
8ca78a0a 551
816d61d5
EQ		 552err4_out:
553 kfree(smu_table->ecc_table);
554err3_out:
555 kfree(smu_table->watermarks_table);
8ca78a0a
EQ		 556err2_out:
557 kfree(smu_table->gpu_metrics_table);
558err1_out:
559 kfree(smu_table->metrics_table);
560err0_out:
561 return -ENOMEM;
b455159c
LG		 562}
563
be22e2b9
EQ		 564static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu)
565{
566 struct smu_table_context *smu_table= &smu->smu_table;
567 SmuMetricsExternal_t *metrics_ext =
568 (SmuMetricsExternal_t *)(smu_table->metrics_table);
569 uint32_t throttler_status = 0;
570 int i;
571
1d789535 572 if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
7952fa0d
DS		 573 (smu->smc_fw_version >= 0x3A4900)) {
574 for (i = 0; i < THROTTLER_COUNT; i++)
575 throttler_status |=
576 (metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0);
577 } else if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
be22e2b9
EQ		 578 (smu->smc_fw_version >= 0x3A4300)) {
579 for (i = 0; i < THROTTLER_COUNT; i++)
580 throttler_status |=
581 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
582 } else {
583 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus;
584 }
585
586 return throttler_status;
587}
588
d6810d7d
S		 589static int sienna_cichlid_get_power_limit(struct smu_context *smu,
590 uint32_t *current_power_limit,
591 uint32_t *default_power_limit,
592 uint32_t *max_power_limit)
593{
594 struct smu_11_0_7_powerplay_table *powerplay_table =
595 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
596 uint32_t power_limit, od_percent;
597 uint16_t *table_member;
598
599 GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
600
601 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
602 power_limit =
603 table_member[PPT_THROTTLER_PPT0];
604 }
605
606 if (current_power_limit)
607 *current_power_limit = power_limit;
608 if (default_power_limit)
609 *default_power_limit = power_limit;
610
611 if (max_power_limit) {
612 if (smu->od_enabled) {
613 od_percent =
614 le32_to_cpu(powerplay_table->overdrive_table.max[
615 SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
616
617 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n",
618 od_percent, power_limit);
619
620 power_limit *= (100 + od_percent);
621 power_limit /= 100;
622 }
623 *max_power_limit = power_limit;
624 }
625
626 return 0;
627}
628
629static void sienna_cichlid_get_smartshift_power_percentage(struct smu_context *smu,
630 uint32_t *apu_percent,
631 uint32_t *dgpu_percent)
632{
633 struct smu_table_context *smu_table = &smu->smu_table;
634 SmuMetrics_V4_t *metrics_v4 =
635 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V4);
636 uint16_t powerRatio = 0;
637 uint16_t apu_power_limit = 0;
638 uint16_t dgpu_power_limit = 0;
639 uint32_t apu_boost = 0;
640 uint32_t dgpu_boost = 0;
641 uint32_t cur_power_limit;
642
643 if (metrics_v4->ApuSTAPMSmartShiftLimit != 0) {
644 sienna_cichlid_get_power_limit(smu, &cur_power_limit, NULL, NULL);
645 apu_power_limit = metrics_v4->ApuSTAPMLimit;
646 dgpu_power_limit = cur_power_limit;
647 powerRatio = (((apu_power_limit +
648 dgpu_power_limit) * 100) /
649 metrics_v4->ApuSTAPMSmartShiftLimit);
650 if (powerRatio > 100) {
651 apu_power_limit = (apu_power_limit * 100) /
652 powerRatio;
653 dgpu_power_limit = (dgpu_power_limit * 100) /
654 powerRatio;
655 }
656 if (metrics_v4->AverageApuSocketPower > apu_power_limit &&
657 apu_power_limit != 0) {
658 apu_boost = ((metrics_v4->AverageApuSocketPower -
659 apu_power_limit) * 100) /
660 apu_power_limit;
661 if (apu_boost > 100)
662 apu_boost = 100;
663 }
664
665 if (metrics_v4->AverageSocketPower > dgpu_power_limit &&
666 dgpu_power_limit != 0) {
667 dgpu_boost = ((metrics_v4->AverageSocketPower -
668 dgpu_power_limit) * 100) /
669 dgpu_power_limit;
670 if (dgpu_boost > 100)
671 dgpu_boost = 100;
672 }
673
674 if (dgpu_boost >= apu_boost)
675 apu_boost = 0;
676 else
677 dgpu_boost = 0;
678 }
679 *apu_percent = apu_boost;
680 *dgpu_percent = dgpu_boost;
681}
682
60ae4d67
EQ		 683static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
684 MetricsMember_t member,
685 uint32_t *value)
686{
687 struct smu_table_context *smu_table= &smu->smu_table;
b4b0b79d
EQ		 688 SmuMetrics_t *metrics =
689 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
be22e2b9
EQ		 690 SmuMetrics_V2_t *metrics_v2 =
691 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
7952fa0d
DS		 692 SmuMetrics_V3_t *metrics_v3 =
693 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V3);
694 bool use_metrics_v2 = false;
695 bool use_metrics_v3 = false;
be22e2b9 696 uint16_t average_gfx_activity;
60ae4d67 697 int ret = 0;
d6810d7d
S		 698 uint32_t apu_percent = 0;
699 uint32_t dgpu_percent = 0;
60ae4d67 700
396beb91
EQ		 701 switch (smu->adev->ip_versions[MP1_HWIP][0]) {
702 case IP_VERSION(11, 0, 7):
703 if (smu->smc_fw_version >= 0x3A4900)
704 use_metrics_v3 = true;
705 else if (smu->smc_fw_version >= 0x3A4300)
706 use_metrics_v2 = true;
707 break;
708 case IP_VERSION(11, 0, 11):
709 if (smu->smc_fw_version >= 0x412D00)
710 use_metrics_v2 = true;
711 break;
712 case IP_VERSION(11, 0, 12):
713 if (smu->smc_fw_version >= 0x3B2300)
714 use_metrics_v2 = true;
715 break;
716 case IP_VERSION(11, 0, 13):
717 if (smu->smc_fw_version >= 0x491100)
718 use_metrics_v2 = true;
719 break;
720 default:
721 break;
722 }
7952fa0d 723
da11407f
EQ		 724 ret = smu_cmn_get_metrics_table(smu,
725 NULL,
726 false);
727 if (ret)
60ae4d67 728 return ret;
60ae4d67 729
8c686254
EQ		 730 switch (member) {
731 case METRICS_CURR_GFXCLK:
7952fa0d
DS		 732 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
733 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] :
be22e2b9 734 metrics->CurrClock[PPCLK_GFXCLK];
8c686254
EQ		 735 break;
736 case METRICS_CURR_SOCCLK:
7952fa0d
DS		 737 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
738 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] :
be22e2b9 739 metrics->CurrClock[PPCLK_SOCCLK];
8c686254
EQ		 740 break;
741 case METRICS_CURR_UCLK:
7952fa0d
DS		 742 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
743 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] :
be22e2b9 744 metrics->CurrClock[PPCLK_UCLK];
8c686254
EQ		 745 break;
746 case METRICS_CURR_VCLK:
7952fa0d
DS		 747 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
748 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] :
be22e2b9 749 metrics->CurrClock[PPCLK_VCLK_0];
8c686254
EQ		 750 break;
751 case METRICS_CURR_VCLK1:
7952fa0d
DS		 752 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
753 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] :
be22e2b9 754 metrics->CurrClock[PPCLK_VCLK_1];
8c686254
EQ		 755 break;
756 case METRICS_CURR_DCLK:
7952fa0d
DS		 757 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
758 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] :
be22e2b9 759 metrics->CurrClock[PPCLK_DCLK_0];
8c686254
EQ		 760 break;
761 case METRICS_CURR_DCLK1:
7952fa0d
DS		 762 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
763 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
be22e2b9 764 metrics->CurrClock[PPCLK_DCLK_1];
8c686254 765 break;
9d09fa6f 766 case METRICS_CURR_DCEFCLK:
7952fa0d
DS		 767 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCEFCLK] :
768 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] :
be22e2b9 769 metrics->CurrClock[PPCLK_DCEFCLK];
9d09fa6f 770 break;
4e2b3e23 771 case METRICS_CURR_FCLK:
7952fa0d
DS		 772 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_FCLK] :
773 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] :
be22e2b9 774 metrics->CurrClock[PPCLK_FCLK];
4e2b3e23 775 break;
8c686254 776 case METRICS_AVERAGE_GFXCLK:
7952fa0d
DS		 777 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
778 use_metrics_v2 ? metrics_v2->AverageGfxActivity :
be22e2b9
EQ		 779 metrics->AverageGfxActivity;
780 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
7952fa0d
DS		 781 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
782 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
be22e2b9 783 metrics->AverageGfxclkFrequencyPostDs;
d817f375 784 else
7952fa0d
DS		 785 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
786 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
be22e2b9 787 metrics->AverageGfxclkFrequencyPreDs;
8c686254
EQ		 788 break;
789 case METRICS_AVERAGE_FCLK:
7952fa0d
DS		 790 *value = use_metrics_v3 ? metrics_v3->AverageFclkFrequencyPostDs :
791 use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs :
be22e2b9 792 metrics->AverageFclkFrequencyPostDs;
8c686254
EQ		 793 break;
794 case METRICS_AVERAGE_UCLK:
7952fa0d
DS		 795 *value = use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
796 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
be22e2b9 797 metrics->AverageUclkFrequencyPostDs;
8c686254
EQ		 798 break;
799 case METRICS_AVERAGE_GFXACTIVITY:
7952fa0d
DS		 800 *value = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
801 use_metrics_v2 ? metrics_v2->AverageGfxActivity :
be22e2b9 802 metrics->AverageGfxActivity;
8c686254
EQ		 803 break;
804 case METRICS_AVERAGE_MEMACTIVITY:
7952fa0d
DS		 805 *value = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
806 use_metrics_v2 ? metrics_v2->AverageUclkActivity :
be22e2b9 807 metrics->AverageUclkActivity;
8c686254
EQ		 808 break;
809 case METRICS_AVERAGE_SOCKETPOWER:
7952fa0d
DS		 810 *value = use_metrics_v3 ? metrics_v3->AverageSocketPower << 8 :
811 use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 :
be22e2b9 812 metrics->AverageSocketPower << 8;
8c686254
EQ		 813 break;
814 case METRICS_TEMPERATURE_EDGE:
7952fa0d
DS		 815 *value = (use_metrics_v3 ? metrics_v3->TemperatureEdge :
816 use_metrics_v2 ? metrics_v2->TemperatureEdge :
817 metrics->TemperatureEdge) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
8c686254
EQ		 818 break;
819 case METRICS_TEMPERATURE_HOTSPOT:
7952fa0d
DS		 820 *value = (use_metrics_v3 ? metrics_v3->TemperatureHotspot :
821 use_metrics_v2 ? metrics_v2->TemperatureHotspot :
822 metrics->TemperatureHotspot) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
8c686254
EQ		 823 break;
824 case METRICS_TEMPERATURE_MEM:
7952fa0d
DS		 825 *value = (use_metrics_v3 ? metrics_v3->TemperatureMem :
826 use_metrics_v2 ? metrics_v2->TemperatureMem :
827 metrics->TemperatureMem) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
8c686254
EQ		 828 break;
829 case METRICS_TEMPERATURE_VRGFX:
7952fa0d
DS		 830 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
831 use_metrics_v2 ? metrics_v2->TemperatureVrGfx :
832 metrics->TemperatureVrGfx) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
8c686254
EQ		 833 break;
834 case METRICS_TEMPERATURE_VRSOC:
7952fa0d
DS		 835 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
836 use_metrics_v2 ? metrics_v2->TemperatureVrSoc :
837 metrics->TemperatureVrSoc) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
8c686254
EQ		 838 break;
839 case METRICS_THROTTLER_STATUS:
be22e2b9 840 *value = sienna_cichlid_get_throttler_status_locked(smu);
8c686254
EQ		 841 break;
842 case METRICS_CURR_FANSPEED:
7952fa0d
DS		 843 *value = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
844 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
8c686254 845 break;
ebd9c071 846 case METRICS_UNIQUE_ID_UPPER32:
5e9c4451
KR		 847 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
848 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumUpper32 : 0;
ebd9c071
KR		 849 break;
850 case METRICS_UNIQUE_ID_LOWER32:
5e9c4451
KR		 851 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
852 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumLower32 : 0;
ebd9c071 853 break;
d6810d7d
S		 854 case METRICS_SS_APU_SHARE:
855 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
856 *value = apu_percent;
857 break;
858 case METRICS_SS_DGPU_SHARE:
859 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
860 *value = dgpu_percent;
861 break;
862
8c686254
EQ		 863 default:
864 *value = UINT_MAX;
865 break;
866 }
867
b455159c 868 return ret;
8c686254 869
b455159c
LG		 870}
871
872static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
873{
874 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
875
b455159c
LG		 876 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
877 GFP_KERNEL);
878 if (!smu_dpm->dpm_context)
879 return -ENOMEM;
880
881 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
882
883 return 0;
884}
885
db5b5c67
AG		 886static void sienna_cichlid_stb_init(struct smu_context *smu);
887
c1b353b7
EQ		 888static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
889{
748262eb 890 struct amdgpu_device *adev = smu->adev;
c1b353b7
EQ		 891 int ret = 0;
892
893 ret = sienna_cichlid_tables_init(smu);
894 if (ret)
895 return ret;
896
897 ret = sienna_cichlid_allocate_dpm_context(smu);
898 if (ret)
899 return ret;
900
748262eb 901 if (!amdgpu_sriov_vf(adev))
902 sienna_cichlid_stb_init(smu);
db5b5c67 903
c1b353b7
EQ		 904 return smu_v11_0_init_smc_tables(smu);
905}
906
b455159c
LG		 907static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
908{
90a89c31 909 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
90a89c31 910 struct smu_11_0_dpm_table *dpm_table;
85dec717 911 struct amdgpu_device *adev = smu->adev;
0b54122c 912 int i, ret = 0;
7077b19a 913 DpmDescriptor_t *table_member;
b455159c 914
90a89c31
EQ		 915 /* socclk dpm table setup */
916 dpm_table = &dpm_context->dpm_tables.soc_table;
7077b19a 917 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
b4bb3aaf 918 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
90a89c31
EQ		 919 ret = smu_v11_0_set_single_dpm_table(smu,
920 SMU_SOCCLK,
921 dpm_table);
922 if (ret)
923 return ret;
924 dpm_table->is_fine_grained =
7077b19a 925 !table_member[PPCLK_SOCCLK].SnapToDiscrete;
90a89c31
EQ		 926 } else {
927 dpm_table->count = 1;
928 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
929 dpm_table->dpm_levels[0].enabled = true;
930 dpm_table->min = dpm_table->dpm_levels[0].value;
931 dpm_table->max = dpm_table->dpm_levels[0].value;
932 }
b455159c 933
90a89c31
EQ		 934 /* gfxclk dpm table setup */
935 dpm_table = &dpm_context->dpm_tables.gfx_table;
b4bb3aaf 936 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
90a89c31
EQ		 937 ret = smu_v11_0_set_single_dpm_table(smu,
938 SMU_GFXCLK,
939 dpm_table);
940 if (ret)
941 return ret;
942 dpm_table->is_fine_grained =
7077b19a 943 !table_member[PPCLK_GFXCLK].SnapToDiscrete;
90a89c31
EQ		 944 } else {
945 dpm_table->count = 1;
946 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
947 dpm_table->dpm_levels[0].enabled = true;
948 dpm_table->min = dpm_table->dpm_levels[0].value;
949 dpm_table->max = dpm_table->dpm_levels[0].value;
950 }
b455159c 951
90a89c31
EQ		 952 /* uclk dpm table setup */
953 dpm_table = &dpm_context->dpm_tables.uclk_table;
b4bb3aaf 954 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
90a89c31
EQ		 955 ret = smu_v11_0_set_single_dpm_table(smu,
956 SMU_UCLK,
957 dpm_table);
958 if (ret)
959 return ret;
960 dpm_table->is_fine_grained =
7077b19a 961 !table_member[PPCLK_UCLK].SnapToDiscrete;
90a89c31
EQ		 962 } else {
963 dpm_table->count = 1;
964 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
965 dpm_table->dpm_levels[0].enabled = true;
966 dpm_table->min = dpm_table->dpm_levels[0].value;
967 dpm_table->max = dpm_table->dpm_levels[0].value;
968 }
b455159c 969
90a89c31
EQ		 970 /* fclk dpm table setup */
971 dpm_table = &dpm_context->dpm_tables.fclk_table;
b4bb3aaf 972 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
90a89c31
EQ		 973 ret = smu_v11_0_set_single_dpm_table(smu,
974 SMU_FCLK,
975 dpm_table);
976 if (ret)
977 return ret;
978 dpm_table->is_fine_grained =
7077b19a 979 !table_member[PPCLK_FCLK].SnapToDiscrete;
90a89c31
EQ		 980 } else {
981 dpm_table->count = 1;
982 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
983 dpm_table->dpm_levels[0].enabled = true;
984 dpm_table->min = dpm_table->dpm_levels[0].value;
985 dpm_table->max = dpm_table->dpm_levels[0].value;
986 }
b455159c 987
0b54122c
AD		 988 /* vclk0/1 dpm table setup */
989 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
990 if (adev->vcn.harvest_config & (1 << i))
991 continue;
b455159c 992
0b54122c 993 dpm_table = &dpm_context->dpm_tables.vclk_table;
85dec717
JC		 994 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
995 ret = smu_v11_0_set_single_dpm_table(smu,
0b54122c 996 i ? SMU_VCLK1 : SMU_VCLK,
85dec717
JC		 997 dpm_table);
998 if (ret)
999 return ret;
1000 dpm_table->is_fine_grained =
0b54122c 1001 !table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete;
85dec717
JC		 1002 } else {
1003 dpm_table->count = 1;
0b54122c 1004 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
85dec717
JC		 1005 dpm_table->dpm_levels[0].enabled = true;
1006 dpm_table->min = dpm_table->dpm_levels[0].value;
1007 dpm_table->max = dpm_table->dpm_levels[0].value;
1008 }
90a89c31 1009 }
b455159c 1010
0b54122c
AD		 1011 /* dclk0/1 dpm table setup */
1012 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1013 if (adev->vcn.harvest_config & (1 << i))
1014 continue;
1015 dpm_table = &dpm_context->dpm_tables.dclk_table;
85dec717
JC		 1016 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1017 ret = smu_v11_0_set_single_dpm_table(smu,
0b54122c 1018 i ? SMU_DCLK1 : SMU_DCLK,
85dec717
JC		 1019 dpm_table);
1020 if (ret)
1021 return ret;
1022 dpm_table->is_fine_grained =
0b54122c 1023 !table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0].SnapToDiscrete;
85dec717
JC		 1024 } else {
1025 dpm_table->count = 1;
0b54122c 1026 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
85dec717
JC		 1027 dpm_table->dpm_levels[0].enabled = true;
1028 dpm_table->min = dpm_table->dpm_levels[0].value;
1029 dpm_table->max = dpm_table->dpm_levels[0].value;
1030 }
90a89c31
EQ		 1031 }
1032
1033 /* dcefclk dpm table setup */
1034 dpm_table = &dpm_context->dpm_tables.dcef_table;
b4bb3aaf 1035 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 1036 ret = smu_v11_0_set_single_dpm_table(smu,
1037 SMU_DCEFCLK,
1038 dpm_table);
1039 if (ret)
1040 return ret;
1041 dpm_table->is_fine_grained =
7077b19a 1042 !table_member[PPCLK_DCEFCLK].SnapToDiscrete;
90a89c31
EQ		 1043 } else {
1044 dpm_table->count = 1;
1045 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1046 dpm_table->dpm_levels[0].enabled = true;
1047 dpm_table->min = dpm_table->dpm_levels[0].value;
1048 dpm_table->max = dpm_table->dpm_levels[0].value;
1049 }
b455159c 1050
90a89c31
EQ		 1051 /* pixelclk dpm table setup */
1052 dpm_table = &dpm_context->dpm_tables.pixel_table;
b4bb3aaf 1053 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 1054 ret = smu_v11_0_set_single_dpm_table(smu,
1055 SMU_PIXCLK,
1056 dpm_table);
1057 if (ret)
1058 return ret;
1059 dpm_table->is_fine_grained =
7077b19a 1060 !table_member[PPCLK_PIXCLK].SnapToDiscrete;
90a89c31
EQ		 1061 } else {
1062 dpm_table->count = 1;
1063 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1064 dpm_table->dpm_levels[0].enabled = true;
1065 dpm_table->min = dpm_table->dpm_levels[0].value;
1066 dpm_table->max = dpm_table->dpm_levels[0].value;
1067 }
b455159c 1068
90a89c31
EQ		 1069 /* displayclk dpm table setup */
1070 dpm_table = &dpm_context->dpm_tables.display_table;
b4bb3aaf 1071 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 1072 ret = smu_v11_0_set_single_dpm_table(smu,
1073 SMU_DISPCLK,
1074 dpm_table);
1075 if (ret)
1076 return ret;
1077 dpm_table->is_fine_grained =
7077b19a 1078 !table_member[PPCLK_DISPCLK].SnapToDiscrete;
90a89c31
EQ		 1079 } else {
1080 dpm_table->count = 1;
1081 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1082 dpm_table->dpm_levels[0].enabled = true;
1083 dpm_table->min = dpm_table->dpm_levels[0].value;
1084 dpm_table->max = dpm_table->dpm_levels[0].value;
1085 }
b455159c 1086
90a89c31
EQ		 1087 /* phyclk dpm table setup */
1088 dpm_table = &dpm_context->dpm_tables.phy_table;
b4bb3aaf 1089 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 1090 ret = smu_v11_0_set_single_dpm_table(smu,
1091 SMU_PHYCLK,
1092 dpm_table);
1093 if (ret)
1094 return ret;
1095 dpm_table->is_fine_grained =
7077b19a 1096 !table_member[PPCLK_PHYCLK].SnapToDiscrete;
90a89c31
EQ		 1097 } else {
1098 dpm_table->count = 1;
1099 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1100 dpm_table->dpm_levels[0].enabled = true;
1101 dpm_table->min = dpm_table->dpm_levels[0].value;
1102 dpm_table->max = dpm_table->dpm_levels[0].value;
1103 }
b455159c
LG		 1104
1105 return 0;
1106}
1107
f6b4b4a1 1108static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
b455159c 1109{
d51dc613 1110 struct amdgpu_device *adev = smu->adev;
0b54122c 1111 int i, ret = 0;
b455159c 1112
0b54122c
AD		 1113 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1114 if (adev->vcn.harvest_config & (1 << i))
1115 continue;
b455159c 1116 /* vcn dpm on is a prerequisite for vcn power gate messages */
b4bb3aaf 1117 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
0b54122c
AD		 1118 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1119 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
1120 0x10000 * i, NULL);
6fb176a7
LG		 1121 if (ret)
1122 return ret;
b455159c 1123 }
b455159c
LG		 1124 }
1125
1126 return ret;
1127}
1128
6fb176a7
LG		 1129static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
1130{
6fb176a7
LG		 1131 int ret = 0;
1132
1133 if (enable) {
b4bb3aaf 1134 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 1135 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
6fb176a7
LG		 1136 if (ret)
1137 return ret;
6fb176a7 1138 }
6fb176a7 1139 } else {
b4bb3aaf 1140 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 1141 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
6fb176a7
LG		 1142 if (ret)
1143 return ret;
6fb176a7 1144 }
6fb176a7
LG		 1145 }
1146
1147 return ret;
1148}
1149
b455159c
LG		 1150static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
1151 enum smu_clk_type clk_type,
1152 uint32_t *value)
1153{
8c686254
EQ		 1154 MetricsMember_t member_type;
1155 int clk_id = 0;
b455159c 1156
6c339f37
EQ		 1157 clk_id = smu_cmn_to_asic_specific_index(smu,
1158 CMN2ASIC_MAPPING_CLK,
1159 clk_type);
b455159c
LG		 1160 if (clk_id < 0)
1161 return clk_id;
1162
8c686254
EQ		 1163 switch (clk_id) {
1164 case PPCLK_GFXCLK:
1165 member_type = METRICS_CURR_GFXCLK;
1166 break;
1167 case PPCLK_UCLK:
1168 member_type = METRICS_CURR_UCLK;
1169 break;
1170 case PPCLK_SOCCLK:
1171 member_type = METRICS_CURR_SOCCLK;
1172 break;
1173 case PPCLK_FCLK:
1174 member_type = METRICS_CURR_FCLK;
1175 break;
1176 case PPCLK_VCLK_0:
1177 member_type = METRICS_CURR_VCLK;
1178 break;
1179 case PPCLK_VCLK_1:
1180 member_type = METRICS_CURR_VCLK1;
1181 break;
1182 case PPCLK_DCLK_0:
1183 member_type = METRICS_CURR_DCLK;
1184 break;
1185 case PPCLK_DCLK_1:
1186 member_type = METRICS_CURR_DCLK1;
1187 break;
1188 case PPCLK_DCEFCLK:
1189 member_type = METRICS_CURR_DCEFCLK;
1190 break;
1191 default:
1192 return -EINVAL;
1193 }
1194
1195 return sienna_cichlid_get_smu_metrics_data(smu,
1196 member_type,
1197 value);
b455159c 1198
b455159c
LG		 1199}
1200
1201static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1202{
b455159c 1203 DpmDescriptor_t *dpm_desc = NULL;
7077b19a 1204 DpmDescriptor_t *table_member;
b455159c
LG		 1205 uint32_t clk_index = 0;
1206
7077b19a 1207 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
6c339f37
EQ		 1208 clk_index = smu_cmn_to_asic_specific_index(smu,
1209 CMN2ASIC_MAPPING_CLK,
1210 clk_type);
7077b19a 1211 dpm_desc = &table_member[clk_index];
b455159c
LG		 1212
1213 /* 0 - Fine grained DPM, 1 - Discrete DPM */
0ee56acc 1214 return dpm_desc->SnapToDiscrete == 0;
b455159c
LG		 1215}
1216
37a58f69
EQ		 1217static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
1218 enum SMU_11_0_7_ODFEATURE_CAP cap)
1219{
1220 return od_table->cap[cap];
1221}
1222
1223static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
1224 enum SMU_11_0_7_ODSETTING_ID setting,
1225 uint32_t *min, uint32_t *max)
1226{
1227 if (min)
1228 *min = od_table->min[setting];
1229 if (max)
1230 *max = od_table->max[setting];
1231}
1232
b455159c
LG		 1233static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
1234 enum smu_clk_type clk_type, char *buf)
1235{
b7d25b5f
LG		 1236 struct amdgpu_device *adev = smu->adev;
1237 struct smu_table_context *table_context = &smu->smu_table;
1238 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1239 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
7077b19a
CG		 1240 uint16_t *table_member;
1241
37a58f69
EQ		 1242 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
1243 OverDriveTable_t *od_table =
1244 (OverDriveTable_t *)table_context->overdrive_table;
b455159c
LG		 1245 int i, size = 0, ret = 0;
1246 uint32_t cur_value = 0, value = 0, count = 0;
1247 uint32_t freq_values[3] = {0};
1248 uint32_t mark_index = 0;
b7d25b5f 1249 uint32_t gen_speed, lane_width;
37a58f69 1250 uint32_t min_value, max_value;
a2b6df4f 1251 uint32_t smu_version;
b455159c 1252
8f48ba30
LY		 1253 smu_cmn_get_sysfs_buf(&buf, &size);
1254
b455159c
LG		 1255 switch (clk_type) {
1256 case SMU_GFXCLK:
1257 case SMU_SCLK:
1258 case SMU_SOCCLK:
1259 case SMU_MCLK:
1260 case SMU_UCLK:
1261 case SMU_FCLK:
78842457
DN		 1262 case SMU_VCLK:
1263 case SMU_VCLK1:
1264 case SMU_DCLK:
1265 case SMU_DCLK1:
b455159c 1266 case SMU_DCEFCLK:
5e6dc8fe 1267 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
b455159c 1268 if (ret)
258d290c 1269 goto print_clk_out;
b455159c 1270
d8d3493a 1271 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
b455159c 1272 if (ret)
258d290c 1273 goto print_clk_out;
b455159c
LG		 1274
1275 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1276 for (i = 0; i < count; i++) {
d8d3493a 1277 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
b455159c 1278 if (ret)
258d290c 1279 goto print_clk_out;
b455159c 1280
fe14c285 1281 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
b455159c
LG		 1282 cur_value == value ? "*" : "");
1283 }
1284 } else {
d8d3493a 1285 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
b455159c 1286 if (ret)
258d290c 1287 goto print_clk_out;
d8d3493a 1288 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
b455159c 1289 if (ret)
258d290c 1290 goto print_clk_out;
b455159c
LG		 1291
1292 freq_values[1] = cur_value;
1293 mark_index = cur_value == freq_values[0] ? 0 :
1294 cur_value == freq_values[2] ? 2 : 1;
b455159c 1295
891bacb8
KF		 1296 count = 3;
1297 if (mark_index != 1) {
1298 count = 2;
1299 freq_values[1] = freq_values[2];
1300 }
1301
1302 for (i = 0; i < count; i++) {
fe14c285 1303 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
891bacb8 1304 cur_value == freq_values[i] ? "*" : "");
b455159c
LG		 1305 }
1306
1307 }
1308 break;
b7d25b5f 1309 case SMU_PCIE:
f20c52f4
LG		 1310 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1311 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
7077b19a 1312 GET_PPTABLE_MEMBER(LclkFreq, &table_member);
b7d25b5f 1313 for (i = 0; i < NUM_LINK_LEVELS; i++)
fe14c285 1314 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
b7d25b5f
LG		 1315 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1316 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1317 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1318 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1319 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1320 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1321 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1322 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1323 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1324 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
7077b19a 1325 table_member[i],
b7d25b5f
LG		 1326 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1327 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1328 "*" : "");
1329 break;
37a58f69
EQ		 1330 case SMU_OD_SCLK:
1331 if (!smu->od_enabled || !od_table || !od_settings)
1332 break;
1333
1334 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1335 break;
1336
fe14c285
DP		 1337 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1338 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
37a58f69
EQ		 1339 break;
1340
1341 case SMU_OD_MCLK:
1342 if (!smu->od_enabled || !od_table || !od_settings)
1343 break;
1344
1345 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1346 break;
1347
fe14c285
DP		 1348 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1349 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
37a58f69
EQ		 1350 break;
1351
a2b6df4f
EQ		 1352 case SMU_OD_VDDGFX_OFFSET:
1353 if (!smu->od_enabled || !od_table || !od_settings)
1354 break;
1355
1356 /*
1357 * OD GFX Voltage Offset functionality is supported only by 58.41.0
1358 * and onwards SMU firmwares.
1359 */
1360 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1d789535 1361 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
a2b6df4f
EQ		 1362 (smu_version < 0x003a2900))
1363 break;
1364
fe14c285
DP		 1365 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1366 size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset);
a2b6df4f
EQ		 1367 break;
1368
37a58f69
EQ		 1369 case SMU_OD_RANGE:
1370 if (!smu->od_enabled || !od_table || !od_settings)
1371 break;
1372
8f48ba30 1373 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
37a58f69
EQ		 1374
1375 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1376 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1377 &min_value, NULL);
1378 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1379 NULL, &max_value);
fe14c285 1380 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
37a58f69
EQ		 1381 min_value, max_value);
1382 }
1383
1384 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1385 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1386 &min_value, NULL);
1387 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1388 NULL, &max_value);
fe14c285 1389 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
37a58f69
EQ		 1390 min_value, max_value);
1391 }
1392 break;
1393
b455159c
LG		 1394 default:
1395 break;
1396 }
1397
258d290c 1398print_clk_out:
b455159c
LG		 1399 return size;
1400}
1401
1402static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1403 enum smu_clk_type clk_type, uint32_t mask)
1404{
d3c98301 1405 int ret = 0;
b455159c
LG		 1406 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1407
1408 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1409 soft_max_level = mask ? (fls(mask) - 1) : 0;
1410
1411 switch (clk_type) {
1412 case SMU_GFXCLK:
1413 case SMU_SCLK:
1414 case SMU_SOCCLK:
1415 case SMU_MCLK:
1416 case SMU_UCLK:
b455159c 1417 case SMU_FCLK:
9ad9c8ac
LG		 1418 /* There is only 2 levels for fine grained DPM */
1419 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1420 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1421 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1422 }
1423
d8d3493a 1424 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
b455159c 1425 if (ret)
258d290c 1426 goto forec_level_out;
b455159c 1427
d8d3493a 1428 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
b455159c 1429 if (ret)
258d290c 1430 goto forec_level_out;
b455159c 1431
10e96d89 1432 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
b455159c 1433 if (ret)
258d290c 1434 goto forec_level_out;
b455159c 1435 break;
51ec6992
DP		 1436 case SMU_DCEFCLK:
1437 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1438 break;
b455159c
LG		 1439 default:
1440 break;
1441 }
1442
258d290c 1443forec_level_out:
d3c98301 1444 return 0;
b455159c
LG		 1445}
1446
1447static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1448{
62cc9dd1
EQ		 1449 struct smu_11_0_dpm_context *dpm_context =
1450 smu->smu_dpm.dpm_context;
1451 struct smu_11_0_dpm_table *gfx_table =
1452 &dpm_context->dpm_tables.gfx_table;
1453 struct smu_11_0_dpm_table *mem_table =
1454 &dpm_context->dpm_tables.uclk_table;
1455 struct smu_11_0_dpm_table *soc_table =
1456 &dpm_context->dpm_tables.soc_table;
1457 struct smu_umd_pstate_table *pstate_table =
1458 &smu->pstate_table;
60aac460 1459 struct amdgpu_device *adev = smu->adev;
62cc9dd1
EQ		 1460
1461 pstate_table->gfxclk_pstate.min = gfx_table->min;
1462 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1463
1464 pstate_table->uclk_pstate.min = mem_table->min;
1465 pstate_table->uclk_pstate.peak = mem_table->max;
1466
1467 pstate_table->socclk_pstate.min = soc_table->min;
1468 pstate_table->socclk_pstate.peak = soc_table->max;
60aac460 1469
9d6b2041
AD		 1470 switch (adev->ip_versions[MP1_HWIP][0]) {
1471 case IP_VERSION(11, 0, 7):
1472 case IP_VERSION(11, 0, 11):
60aac460
EQ		 1473 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
1474 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
0dc994fb 1475 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
60aac460 1476 break;
9d6b2041 1477 case IP_VERSION(11, 0, 12):
60aac460
EQ		 1478 pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK;
1479 pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK;
1480 pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK;
1481 break;
9d6b2041 1482 case IP_VERSION(11, 0, 13):
60aac460
EQ		 1483 pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK;
1484 pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK;
1485 pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK;
1486 break;
1487 default:
1488 break;
1489 }
b455159c 1490
62cc9dd1 1491 return 0;
b455159c
LG		 1492}
1493
b455159c
LG		 1494static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1495{
1496 int ret = 0;
1497 uint32_t max_freq = 0;
1498
1499 /* Sienna_Cichlid do not support to change display num currently */
1500 return 0;
1501#if 0
66c86828 1502 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
b455159c
LG		 1503 if (ret)
1504 return ret;
1505#endif
1506
b4bb3aaf 1507 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
e5ef784b 1508 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
b455159c
LG		 1509 if (ret)
1510 return ret;
661b94f5 1511 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
b455159c
LG		 1512 if (ret)
1513 return ret;
1514 }
1515
1516 return ret;
1517}
1518
1519static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1520{
1521 int ret = 0;
1522
b455159c 1523 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
7ade3ca9
EQ		 1524 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1525 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
b455159c 1526#if 0
66c86828 1527 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
40d3b8db
LG		 1528 smu->display_config->num_display,
1529 NULL);
b455159c
LG		 1530#endif
1531 if (ret)
1532 return ret;
1533 }
1534
1535 return ret;
1536}
1537
b455159c
LG		 1538static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1539{
1540 int ret = 0;
3d14a79b
KW		 1541 uint64_t feature_enabled;
1542
2d282665 1543 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
3d14a79b
KW		 1544 if (ret)
1545 return false;
1546
b455159c
LG		 1547 return !!(feature_enabled & SMC_DPM_FEATURE);
1548}
1549
d9ca7567
EQ		 1550static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1551 uint32_t *speed)
1552{
1553 if (!speed)
1554 return -EINVAL;
1555
1556 /*
1557 * For Sienna_Cichlid and later, the fan speed(rpm) reported
1558 * by pmfw is always trustable(even when the fan control feature
1559 * disabled or 0 RPM kicked in).
1560 */
1561 return sienna_cichlid_get_smu_metrics_data(smu,
1562 METRICS_CURR_FANSPEED,
1563 speed);
1564}
1565
3204ff3e
AD		 1566static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1567{
7077b19a 1568 uint16_t *table_member;
3204ff3e 1569
7077b19a
CG		 1570 GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
1571 smu->fan_max_rpm = *table_member;
3204ff3e
AD		 1572
1573 return 0;
1574}
1575
b455159c
LG		 1576static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1577{
f9e3fe46
EQ		 1578 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1579 DpmActivityMonitorCoeffInt_t *activity_monitor =
1580 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
b455159c
LG		 1581 uint32_t i, size = 0;
1582 int16_t workload_type = 0;
b455159c
LG		 1583 static const char *title[] = {
1584 "PROFILE_INDEX(NAME)",
1585 "CLOCK_TYPE(NAME)",
1586 "FPS",
1587 "MinFreqType",
1588 "MinActiveFreqType",
1589 "MinActiveFreq",
1590 "BoosterFreqType",
1591 "BoosterFreq",
1592 "PD_Data_limit_c",
1593 "PD_Data_error_coeff",
1594 "PD_Data_error_rate_coeff"};
1595 int result = 0;
1596
1597 if (!buf)
1598 return -EINVAL;
1599
fe14c285 1600 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
b455159c
LG		 1601 title[0], title[1], title[2], title[3], title[4], title[5],
1602 title[6], title[7], title[8], title[9], title[10]);
1603
1604 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1605 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
6c339f37
EQ		 1606 workload_type = smu_cmn_to_asic_specific_index(smu,
1607 CMN2ASIC_MAPPING_WORKLOAD,
1608 i);
b455159c
LG		 1609 if (workload_type < 0)
1610 return -EINVAL;
1611
caad2613 1612 result = smu_cmn_update_table(smu,
b455159c 1613 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
f9e3fe46 1614 (void *)(&activity_monitor_external), false);
b455159c 1615 if (result) {
d9811cfc 1616 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
b455159c
LG		 1617 return result;
1618 }
1619
fe14c285 1620 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
94a80b5b 1621 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
b455159c 1622
fe14c285 1623 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
b455159c
LG		 1624 " ",
1625 0,
1626 "GFXCLK",
f9e3fe46
EQ		 1627 activity_monitor->Gfx_FPS,
1628 activity_monitor->Gfx_MinFreqStep,
1629 activity_monitor->Gfx_MinActiveFreqType,
1630 activity_monitor->Gfx_MinActiveFreq,
1631 activity_monitor->Gfx_BoosterFreqType,
1632 activity_monitor->Gfx_BoosterFreq,
1633 activity_monitor->Gfx_PD_Data_limit_c,
1634 activity_monitor->Gfx_PD_Data_error_coeff,
1635 activity_monitor->Gfx_PD_Data_error_rate_coeff);
b455159c 1636
fe14c285 1637 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
b455159c
LG		 1638 " ",
1639 1,
1640 "SOCCLK",
f9e3fe46
EQ		 1641 activity_monitor->Fclk_FPS,
1642 activity_monitor->Fclk_MinFreqStep,
1643 activity_monitor->Fclk_MinActiveFreqType,
1644 activity_monitor->Fclk_MinActiveFreq,
1645 activity_monitor->Fclk_BoosterFreqType,
1646 activity_monitor->Fclk_BoosterFreq,
1647 activity_monitor->Fclk_PD_Data_limit_c,
1648 activity_monitor->Fclk_PD_Data_error_coeff,
1649 activity_monitor->Fclk_PD_Data_error_rate_coeff);
b455159c 1650
fe14c285 1651 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
b455159c
LG		 1652 " ",
1653 2,
1654 "MEMLK",
f9e3fe46
EQ		 1655 activity_monitor->Mem_FPS,
1656 activity_monitor->Mem_MinFreqStep,
1657 activity_monitor->Mem_MinActiveFreqType,
1658 activity_monitor->Mem_MinActiveFreq,
1659 activity_monitor->Mem_BoosterFreqType,
1660 activity_monitor->Mem_BoosterFreq,
1661 activity_monitor->Mem_PD_Data_limit_c,
1662 activity_monitor->Mem_PD_Data_error_coeff,
1663 activity_monitor->Mem_PD_Data_error_rate_coeff);
b455159c
LG		 1664 }
1665
1666 return size;
1667}
1668
1669static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1670{
f9e3fe46
EQ		 1671
1672 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1673 DpmActivityMonitorCoeffInt_t *activity_monitor =
1674 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
b455159c
LG		 1675 int workload_type, ret = 0;
1676
1677 smu->power_profile_mode = input[size];
1678
1679 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
d9811cfc 1680 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
b455159c
LG		 1681 return -EINVAL;
1682 }
1683
1684 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
b455159c 1685
caad2613 1686 ret = smu_cmn_update_table(smu,
b455159c 1687 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
f9e3fe46 1688 (void *)(&activity_monitor_external), false);
b455159c 1689 if (ret) {
d9811cfc 1690 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
b455159c
LG		 1691 return ret;
1692 }
1693
1694 switch (input[0]) {
1695 case 0: /* Gfxclk */
f9e3fe46
EQ		 1696 activity_monitor->Gfx_FPS = input[1];
1697 activity_monitor->Gfx_MinFreqStep = input[2];
1698 activity_monitor->Gfx_MinActiveFreqType = input[3];
1699 activity_monitor->Gfx_MinActiveFreq = input[4];
1700 activity_monitor->Gfx_BoosterFreqType = input[5];
1701 activity_monitor->Gfx_BoosterFreq = input[6];
1702 activity_monitor->Gfx_PD_Data_limit_c = input[7];
1703 activity_monitor->Gfx_PD_Data_error_coeff = input[8];
1704 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1705 break;
1706 case 1: /* Socclk */
f9e3fe46
EQ		 1707 activity_monitor->Fclk_FPS = input[1];
1708 activity_monitor->Fclk_MinFreqStep = input[2];
1709 activity_monitor->Fclk_MinActiveFreqType = input[3];
1710 activity_monitor->Fclk_MinActiveFreq = input[4];
1711 activity_monitor->Fclk_BoosterFreqType = input[5];
1712 activity_monitor->Fclk_BoosterFreq = input[6];
1713 activity_monitor->Fclk_PD_Data_limit_c = input[7];
1714 activity_monitor->Fclk_PD_Data_error_coeff = input[8];
1715 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1716 break;
1717 case 2: /* Memlk */
f9e3fe46
EQ		 1718 activity_monitor->Mem_FPS = input[1];
1719 activity_monitor->Mem_MinFreqStep = input[2];
1720 activity_monitor->Mem_MinActiveFreqType = input[3];
1721 activity_monitor->Mem_MinActiveFreq = input[4];
1722 activity_monitor->Mem_BoosterFreqType = input[5];
1723 activity_monitor->Mem_BoosterFreq = input[6];
1724 activity_monitor->Mem_PD_Data_limit_c = input[7];
1725 activity_monitor->Mem_PD_Data_error_coeff = input[8];
1726 activity_monitor->Mem_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1727 break;
1728 }
1729
caad2613 1730 ret = smu_cmn_update_table(smu,
b455159c 1731 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
f9e3fe46 1732 (void *)(&activity_monitor_external), true);
b455159c 1733 if (ret) {
d9811cfc 1734 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
b455159c
LG		 1735 return ret;
1736 }
1737 }
1738
1739 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
6c339f37
EQ		 1740 workload_type = smu_cmn_to_asic_specific_index(smu,
1741 CMN2ASIC_MAPPING_WORKLOAD,
1742 smu->power_profile_mode);
b455159c
LG		 1743 if (workload_type < 0)
1744 return -EINVAL;
66c86828 1745 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
b455159c
LG		 1746 1 << workload_type, NULL);
1747
1748 return ret;
1749}
1750
b455159c
LG		 1751static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1752{
1753 struct smu_clocks min_clocks = {0};
1754 struct pp_display_clock_request clock_req;
1755 int ret = 0;
1756
1757 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1758 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1759 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1760
7ade3ca9 1761 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
b455159c
LG		 1762 clock_req.clock_type = amd_pp_dcef_clock;
1763 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1764
1765 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1766 if (!ret) {
7ade3ca9 1767 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
66c86828 1768 ret = smu_cmn_send_smc_msg_with_param(smu,
40d3b8db
LG		 1769 SMU_MSG_SetMinDeepSleepDcefclk,
1770 min_clocks.dcef_clock_in_sr/100,
1771 NULL);
1772 if (ret) {
d9811cfc 1773 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
40d3b8db
LG		 1774 return ret;
1775 }
b455159c
LG		 1776 }
1777 } else {
d9811cfc 1778 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
b455159c
LG		 1779 }
1780 }
1781
b4bb3aaf 1782 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
661b94f5 1783 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
b455159c 1784 if (ret) {
d9811cfc 1785 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
b455159c
LG		 1786 return ret;
1787 }
1788 }
1789
1790 return 0;
1791}
1792
1793static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
7b9c7e30 1794 struct pp_smu_wm_range_sets *clock_ranges)
b455159c 1795{
e7a95eea 1796 Watermarks_t *table = smu->smu_table.watermarks_table;
40d3b8db 1797 int ret = 0;
e7a95eea 1798 int i;
b455159c 1799
e7a95eea 1800 if (clock_ranges) {
7b9c7e30
EQ		 1801 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1802 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
e7a95eea
EQ		 1803 return -EINVAL;
1804
7b9c7e30
EQ		 1805 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1806 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1807 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1808 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1809 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1810 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1811 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1812 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1813 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1814
1815 table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1816 clock_ranges->reader_wm_sets[i].wm_inst;
e7a95eea 1817 }
b455159c 1818
7b9c7e30
EQ		 1819 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1820 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1821 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1822 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1823 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1824 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1825 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1826 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1827 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1828
1829 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1830 clock_ranges->writer_wm_sets[i].wm_inst;
e7a95eea
EQ		 1831 }
1832
1833 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1834 }
1835
1836 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1837 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
caad2613 1838 ret = smu_cmn_write_watermarks_table(smu);
40d3b8db 1839 if (ret) {
d9811cfc 1840 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
40d3b8db
LG		 1841 return ret;
1842 }
1843 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1844 }
1845
b455159c
LG		 1846 return 0;
1847}
1848
b455159c
LG		 1849static int sienna_cichlid_read_sensor(struct smu_context *smu,
1850 enum amd_pp_sensors sensor,
1851 void *data, uint32_t *size)
1852{
1853 int ret = 0;
7077b19a 1854 uint16_t *temp;
d6810d7d 1855 struct amdgpu_device *adev = smu->adev;
b455159c
LG		 1856
1857 if(!data || !size)
1858 return -EINVAL;
1859
b455159c
LG		 1860 switch (sensor) {
1861 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
7077b19a
CG		 1862 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
1863 *(uint16_t *)data = *temp;
b455159c
LG		 1864 *size = 4;
1865 break;
1866 case AMDGPU_PP_SENSOR_MEM_LOAD:
60e317a2
AD		 1867 ret = sienna_cichlid_get_smu_metrics_data(smu,
1868 METRICS_AVERAGE_MEMACTIVITY,
1869 (uint32_t *)data);
1870 *size = 4;
1871 break;
b455159c 1872 case AMDGPU_PP_SENSOR_GPU_LOAD:
60e317a2
AD		 1873 ret = sienna_cichlid_get_smu_metrics_data(smu,
1874 METRICS_AVERAGE_GFXACTIVITY,
1875 (uint32_t *)data);
b455159c
LG		 1876 *size = 4;
1877 break;
1878 case AMDGPU_PP_SENSOR_GPU_POWER:
60e317a2
AD		 1879 ret = sienna_cichlid_get_smu_metrics_data(smu,
1880 METRICS_AVERAGE_SOCKETPOWER,
1881 (uint32_t *)data);
b455159c
LG		 1882 *size = 4;
1883 break;
1884 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
60e317a2
AD		 1885 ret = sienna_cichlid_get_smu_metrics_data(smu,
1886 METRICS_TEMPERATURE_HOTSPOT,
1887 (uint32_t *)data);
1888 *size = 4;
1889 break;
b455159c 1890 case AMDGPU_PP_SENSOR_EDGE_TEMP:
60e317a2
AD		 1891 ret = sienna_cichlid_get_smu_metrics_data(smu,
1892 METRICS_TEMPERATURE_EDGE,
1893 (uint32_t *)data);
1894 *size = 4;
1895 break;
b455159c 1896 case AMDGPU_PP_SENSOR_MEM_TEMP:
60e317a2
AD		 1897 ret = sienna_cichlid_get_smu_metrics_data(smu,
1898 METRICS_TEMPERATURE_MEM,
1899 (uint32_t *)data);
b455159c
LG		 1900 *size = 4;
1901 break;
e0f9e936
EQ		 1902 case AMDGPU_PP_SENSOR_GFX_MCLK:
1903 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1904 *(uint32_t *)data *= 100;
1905 *size = 4;
1906 break;
1907 case AMDGPU_PP_SENSOR_GFX_SCLK:
1908 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1909 *(uint32_t *)data *= 100;
1910 *size = 4;
1911 break;
b2febc99
EQ		 1912 case AMDGPU_PP_SENSOR_VDDGFX:
1913 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1914 *size = 4;
1915 break;
d6810d7d
S		 1916 case AMDGPU_PP_SENSOR_SS_APU_SHARE:
1917 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) {
1918 ret = sienna_cichlid_get_smu_metrics_data(smu,
1919 METRICS_SS_APU_SHARE, (uint32_t *)data);
1920 *size = 4;
1921 } else {
1922 ret = -EOPNOTSUPP;
1923 }
1924 break;
1925 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
1926 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) {
1927 ret = sienna_cichlid_get_smu_metrics_data(smu,
1928 METRICS_SS_DGPU_SHARE, (uint32_t *)data);
1929 *size = 4;
1930 } else {
1931 ret = -EOPNOTSUPP;
1932 }
1933 break;
b455159c 1934 default:
b2febc99
EQ		 1935 ret = -EOPNOTSUPP;
1936 break;
b455159c 1937 }
b455159c
LG		 1938
1939 return ret;
1940}
1941
ebd9c071
KR		 1942static void sienna_cichlid_get_unique_id(struct smu_context *smu)
1943{
1944 struct amdgpu_device *adev = smu->adev;
1945 uint32_t upper32 = 0, lower32 = 0;
1946
1947 /* Only supported as of version 0.58.83.0 and only on Sienna Cichlid */
1948 if (smu->smc_fw_version < 0x3A5300 ||
1949 smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7))
1950 return;
1951
1952 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32))
1953 goto out;
1954 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32))
1955 goto out;
1956
1957out:
1958
1959 adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1960 if (adev->serial[0] == '\0')
1961 sprintf(adev->serial, "%016llx", adev->unique_id);
1962}
1963
b455159c
LG		 1964static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1965{
1966 uint32_t num_discrete_levels = 0;
1967 uint16_t *dpm_levels = NULL;
1968 uint16_t i = 0;
1969 struct smu_table_context *table_context = &smu->smu_table;
7077b19a
CG		 1970 DpmDescriptor_t *table_member1;
1971 uint16_t *table_member2;
b455159c
LG		 1972
1973 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1974 return -EINVAL;
1975
7077b19a
CG		 1976 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
1977 num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
1978 GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
1979 dpm_levels = table_member2;
b455159c
LG		 1980
1981 if (num_discrete_levels == 0 || dpm_levels == NULL)
1982 return -EINVAL;
1983
1984 *num_states = num_discrete_levels;
1985 for (i = 0; i < num_discrete_levels; i++) {
1986 /* convert to khz */
1987 *clocks_in_khz = (*dpm_levels) * 1000;
1988 clocks_in_khz++;
1989 dpm_levels++;
1990 }
1991
1992 return 0;
1993}
1994
1995static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1996 struct smu_temperature_range *range)
1997{
e02e4d51
EQ		 1998 struct smu_table_context *table_context = &smu->smu_table;
1999 struct smu_11_0_7_powerplay_table *powerplay_table =
2000 table_context->power_play_table;
7077b19a
CG		 2001 uint16_t *table_member;
2002 uint16_t temp_edge, temp_hotspot, temp_mem;
b455159c 2003
2b1f12a2 2004 if (!range)
b455159c
LG		 2005 return -EINVAL;
2006
0540eced
EQ		 2007 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
2008
7077b19a
CG		 2009 GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
2010 temp_edge = table_member[TEMP_EDGE];
2011 temp_hotspot = table_member[TEMP_HOTSPOT];
2012 temp_mem = table_member[TEMP_MEM];
2013
2014 range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2015 range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
2b1f12a2 2016 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a
CG		 2017 range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2018 range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
2b1f12a2 2019 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a
CG		 2020 range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2021 range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
b455159c 2022 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a 2023
e02e4d51 2024 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
b455159c
LG		 2025
2026 return 0;
2027}
2028
2029static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
2030 bool disable_memory_clock_switch)
2031{
2032 int ret = 0;
2033 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
2034 (struct smu_11_0_max_sustainable_clocks *)
2035 smu->smu_table.max_sustainable_clocks;
2036 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
2037 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
2038
2039 if(smu->disable_uclk_switch == disable_memory_clock_switch)
2040 return 0;
2041
2042 if(disable_memory_clock_switch)
661b94f5 2043 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
b455159c 2044 else
661b94f5 2045 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
b455159c
LG		 2046
2047 if(!ret)
2048 smu->disable_uclk_switch = disable_memory_clock_switch;
2049
2050 return ret;
2051}
2052
08ccfe08
LG		 2053static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
2054 uint32_t pcie_gen_cap,
2055 uint32_t pcie_width_cap)
2056{
0b590970 2057 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
7077b19a 2058
08ccfe08 2059 uint32_t smu_pcie_arg;
7077b19a 2060 uint8_t *table_member1, *table_member2;
0b590970 2061 int ret, i;
08ccfe08 2062
7077b19a
CG		 2063 GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
2064 GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
2065
0b590970
EQ		 2066 /* lclk dpm table setup */
2067 for (i = 0; i < MAX_PCIE_CONF; i++) {
7077b19a
CG		 2068 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = table_member1[i];
2069 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = table_member2[i];
0b590970 2070 }
08ccfe08
LG		 2071
2072 for (i = 0; i < NUM_LINK_LEVELS; i++) {
2073 smu_pcie_arg = (i << 16) |
7077b19a
CG		 2074 ((table_member1[i] <= pcie_gen_cap) ?
2075 (table_member1[i] << 8) :
2076 (pcie_gen_cap << 8)) |
2077 ((table_member2[i] <= pcie_width_cap) ?
2078 table_member2[i] :
2079 pcie_width_cap);
08ccfe08 2080
66c86828 2081 ret = smu_cmn_send_smc_msg_with_param(smu,
7077b19a
CG		 2082 SMU_MSG_OverridePcieParameters,
2083 smu_pcie_arg,
2084 NULL);
08ccfe08
LG		 2085 if (ret)
2086 return ret;
2087
7077b19a 2088 if (table_member1[i] > pcie_gen_cap)
08ccfe08 2089 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
7077b19a 2090 if (table_member2[i] > pcie_width_cap)
08ccfe08
LG		 2091 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
2092 }
2093
2094 return 0;
2095}
2096
38ed7b09 2097static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
258d290c
LG		 2098 enum smu_clk_type clk_type,
2099 uint32_t *min, uint32_t *max)
2100{
3bce90bf 2101 return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
258d290c
LG		 2102}
2103
aa75fa34
EQ		 2104static void sienna_cichlid_dump_od_table(struct smu_context *smu,
2105 OverDriveTable_t *od_table)
2106{
a2b6df4f
EQ		 2107 struct amdgpu_device *adev = smu->adev;
2108 uint32_t smu_version;
2109
aa75fa34
EQ		 2110 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
2111 od_table->GfxclkFmax);
2112 dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
2113 od_table->UclkFmax);
a2b6df4f
EQ		 2114
2115 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1d789535 2116 if (!((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
a2b6df4f
EQ		 2117 (smu_version < 0x003a2900)))
2118 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
aa75fa34
EQ		 2119}
2120
2121static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
2122{
2123 OverDriveTable_t *od_table =
2124 (OverDriveTable_t *)smu->smu_table.overdrive_table;
2125 OverDriveTable_t *boot_od_table =
2126 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
b521be9b
EQ		 2127 OverDriveTable_t *user_od_table =
2128 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
aa75fa34
EQ		 2129 int ret = 0;
2130
b521be9b
EQ		 2131 /*
2132 * For S3/S4/Runpm resume, no need to setup those overdrive tables again as
2133 * - either they already have the default OD settings got during cold bootup
2134 * - or they have some user customized OD settings which cannot be overwritten
2135 */
2136 if (smu->adev->in_suspend)
2137 return 0;
2138
aa75fa34 2139 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
b521be9b 2140 0, (void *)boot_od_table, false);
aa75fa34
EQ		 2141 if (ret) {
2142 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2143 return ret;
2144 }
2145
b521be9b 2146 sienna_cichlid_dump_od_table(smu, boot_od_table);
aa75fa34 2147
b521be9b
EQ		 2148 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
2149 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
aa75fa34
EQ		 2150
2151 return 0;
2152}
2153
37a58f69
EQ		 2154static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
2155 struct smu_11_0_7_overdrive_table *od_table,
2156 enum SMU_11_0_7_ODSETTING_ID setting,
2157 uint32_t value)
2158{
2159 if (value < od_table->min[setting]) {
2160 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
2161 setting, value, od_table->min[setting]);
2162 return -EINVAL;
2163 }
2164 if (value > od_table->max[setting]) {
2165 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
2166 setting, value, od_table->max[setting]);
2167 return -EINVAL;
2168 }
2169
2170 return 0;
2171}
2172
2173static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
2174 enum PP_OD_DPM_TABLE_COMMAND type,
2175 long input[], uint32_t size)
2176{
2177 struct smu_table_context *table_context = &smu->smu_table;
2178 OverDriveTable_t *od_table =
2179 (OverDriveTable_t *)table_context->overdrive_table;
2180 struct smu_11_0_7_overdrive_table *od_settings =
2181 (struct smu_11_0_7_overdrive_table *)smu->od_settings;
a2b6df4f 2182 struct amdgpu_device *adev = smu->adev;
37a58f69
EQ		 2183 enum SMU_11_0_7_ODSETTING_ID freq_setting;
2184 uint16_t *freq_ptr;
2185 int i, ret = 0;
a2b6df4f 2186 uint32_t smu_version;
37a58f69
EQ		 2187
2188 if (!smu->od_enabled) {
2189 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2190 return -EINVAL;
2191 }
2192
2193 if (!smu->od_settings) {
2194 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2195 return -ENOENT;
2196 }
2197
2198 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2199 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2200 return -EINVAL;
2201 }
2202
2203 switch (type) {
2204 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2205 if (!sienna_cichlid_is_od_feature_supported(od_settings,
2206 SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
2207 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2208 return -ENOTSUPP;
2209 }
2210
2211 for (i = 0; i < size; i += 2) {
2212 if (i + 2 > size) {
2213 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2214 return -EINVAL;
2215 }
2216
2217 switch (input[i]) {
2218 case 0:
2219 if (input[i + 1] > od_table->GfxclkFmax) {
2220 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2221 input[i + 1], od_table->GfxclkFmax);
2222 return -EINVAL;
2223 }
2224
2225 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
2226 freq_ptr = &od_table->GfxclkFmin;
2227 break;
2228
2229 case 1:
2230 if (input[i + 1] < od_table->GfxclkFmin) {
2231 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2232 input[i + 1], od_table->GfxclkFmin);
2233 return -EINVAL;
2234 }
2235
2236 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
2237 freq_ptr = &od_table->GfxclkFmax;
2238 break;
2239
2240 default:
2241 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2242 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2243 return -EINVAL;
2244 }
2245
2246 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2247 freq_setting, input[i + 1]);
2248 if (ret)
2249 return ret;
2250
2251 *freq_ptr = (uint16_t)input[i + 1];
2252 }
2253 break;
2254
2255 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2256 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
2257 dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2258 return -ENOTSUPP;
2259 }
2260
2261 for (i = 0; i < size; i += 2) {
2262 if (i + 2 > size) {
2263 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2264 return -EINVAL;
2265 }
2266
2267 switch (input[i]) {
2268 case 0:
2269 if (input[i + 1] > od_table->UclkFmax) {
2270 dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2271 input[i + 1], od_table->UclkFmax);
2272 return -EINVAL;
2273 }
2274
2275 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
2276 freq_ptr = &od_table->UclkFmin;
2277 break;
2278
2279 case 1:
2280 if (input[i + 1] < od_table->UclkFmin) {
2281 dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2282 input[i + 1], od_table->UclkFmin);
2283 return -EINVAL;
2284 }
2285
2286 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
2287 freq_ptr = &od_table->UclkFmax;
2288 break;
2289
2290 default:
2291 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2292 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2293 return -EINVAL;
2294 }
2295
2296 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2297 freq_setting, input[i + 1]);
2298 if (ret)
2299 return ret;
2300
2301 *freq_ptr = (uint16_t)input[i + 1];
2302 }
2303 break;
2304
2305 case PP_OD_RESTORE_DEFAULT_TABLE:
2306 memcpy(table_context->overdrive_table,
2307 table_context->boot_overdrive_table,
2308 sizeof(OverDriveTable_t));
2309 fallthrough;
2310
2311 case PP_OD_COMMIT_DPM_TABLE:
b521be9b
EQ		 2312 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2313 sienna_cichlid_dump_od_table(smu, od_table);
2314 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2315 if (ret) {
2316 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2317 return ret;
2318 }
2319 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2320 smu->user_dpm_profile.user_od = true;
37a58f69 2321
b521be9b
EQ		 2322 if (!memcmp(table_context->user_overdrive_table,
2323 table_context->boot_overdrive_table,
2324 sizeof(OverDriveTable_t)))
2325 smu->user_dpm_profile.user_od = false;
37a58f69
EQ		 2326 }
2327 break;
2328
a2b6df4f
EQ		 2329 case PP_OD_EDIT_VDDGFX_OFFSET:
2330 if (size != 1) {
2331 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2332 return -EINVAL;
2333 }
2334
2335 /*
2336 * OD GFX Voltage Offset functionality is supported only by 58.41.0
2337 * and onwards SMU firmwares.
2338 */
2339 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1d789535 2340 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
a2b6df4f
EQ		 2341 (smu_version < 0x003a2900)) {
2342 dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2343 "only by 58.41.0 and onwards SMU firmwares!\n");
2344 return -EOPNOTSUPP;
2345 }
2346
2347 od_table->VddGfxOffset = (int16_t)input[0];
2348
2349 sienna_cichlid_dump_od_table(smu, od_table);
2350 break;
2351
37a58f69
EQ		 2352 default:
2353 return -ENOSYS;
2354 }
2355
2356 return ret;
2357}
2358
66b8a9c0
JC		 2359static int sienna_cichlid_run_btc(struct smu_context *smu)
2360{
dc78fea1
LT		 2361 int res;
2362
2363 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2364 if (res)
2365 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2366
2367 return res;
66b8a9c0
JC		 2368}
2369
13d75ead
EQ		 2370static int sienna_cichlid_baco_enter(struct smu_context *smu)
2371{
2372 struct amdgpu_device *adev = smu->adev;
2373
8b514e89 2374 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
13d75ead
EQ		 2375 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2376 else
2377 return smu_v11_0_baco_enter(smu);
2378}
2379
2380static int sienna_cichlid_baco_exit(struct smu_context *smu)
2381{
2382 struct amdgpu_device *adev = smu->adev;
2383
8b514e89 2384 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
13d75ead
EQ		 2385 /* Wait for PMFW handling for the Dstate change */
2386 msleep(10);
2387 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2388 } else {
2389 return smu_v11_0_baco_exit(smu);
2390 }
2391}
2392
ea8139d8
WS		 2393static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2394{
2395 struct amdgpu_device *adev = smu->adev;
2396 uint32_t val;
2397 u32 smu_version;
2398
2399 /**
2400 * SRIOV env will not support SMU mode1 reset
2401 * PM FW support mode1 reset from 58.26
2402 */
a7bae061 2403 smu_cmn_get_smc_version(smu, NULL, &smu_version);
ea8139d8
WS		 2404 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
2405 return false;
2406
2407 /**
2408 * mode1 reset relies on PSP, so we should check if
2409 * PSP is alive.
2410 */
2411 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2412 return val != 0x0;
2413}
2414
7077b19a
CG		 2415static void beige_goby_dump_pptable(struct smu_context *smu)
2416{
2417 struct smu_table_context *table_context = &smu->smu_table;
2418 PPTable_beige_goby_t *pptable = table_context->driver_pptable;
2419 int i;
2420
2421 dev_info(smu->adev->dev, "Dumped PPTable:\n");
2422
2423 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2424 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2425 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2426
2427 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2428 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2429 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2430 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2431 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2432 }
2433
2434 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2435 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2436 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2437 }
2438
2439 for (i = 0; i < TEMP_COUNT; i++) {
2440 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2441 }
2442
2443 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2444 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2445 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2446 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2447 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2448
2449 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2450 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2451 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2452 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2453 }
2454 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2455
2456 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2457
2458 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2459 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2460 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2461 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2462
2463 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2464
2465 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2466
2467 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2468 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2469 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2470 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2471
2472 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2473 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2474
2475 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2476 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2477 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2478 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2479 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2480 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2481 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2482 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2483
2484 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2485 " .VoltageMode = 0x%02x\n"
2486 " .SnapToDiscrete = 0x%02x\n"
2487 " .NumDiscreteLevels = 0x%02x\n"
2488 " .padding = 0x%02x\n"
2489 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2490 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2491 " .SsFmin = 0x%04x\n"
2492 " .Padding_16 = 0x%04x\n",
2493 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2494 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2495 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2496 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2497 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2498 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2499 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2500 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2501 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2502 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2503 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2504
2505 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2506 " .VoltageMode = 0x%02x\n"
2507 " .SnapToDiscrete = 0x%02x\n"
2508 " .NumDiscreteLevels = 0x%02x\n"
2509 " .padding = 0x%02x\n"
2510 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2511 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2512 " .SsFmin = 0x%04x\n"
2513 " .Padding_16 = 0x%04x\n",
2514 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2515 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2516 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2517 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2518 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2519 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2520 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2521 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2522 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2523 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2524 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2525
2526 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2527 " .VoltageMode = 0x%02x\n"
2528 " .SnapToDiscrete = 0x%02x\n"
2529 " .NumDiscreteLevels = 0x%02x\n"
2530 " .padding = 0x%02x\n"
2531 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2532 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2533 " .SsFmin = 0x%04x\n"
2534 " .Padding_16 = 0x%04x\n",
2535 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2536 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2537 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2538 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2539 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2540 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2541 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2542 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2543 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2544 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2545 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2546
2547 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2548 " .VoltageMode = 0x%02x\n"
2549 " .SnapToDiscrete = 0x%02x\n"
2550 " .NumDiscreteLevels = 0x%02x\n"
2551 " .padding = 0x%02x\n"
2552 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2553 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2554 " .SsFmin = 0x%04x\n"
2555 " .Padding_16 = 0x%04x\n",
2556 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2557 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2558 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2559 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2560 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2561 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2562 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2563 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2564 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2565 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2566 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2567
2568 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2569 " .VoltageMode = 0x%02x\n"
2570 " .SnapToDiscrete = 0x%02x\n"
2571 " .NumDiscreteLevels = 0x%02x\n"
2572 " .padding = 0x%02x\n"
2573 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2574 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2575 " .SsFmin = 0x%04x\n"
2576 " .Padding_16 = 0x%04x\n",
2577 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2578 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2579 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2580 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2581 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2582 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2583 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2584 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2585 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2586 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2587 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2588
2589 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2590 " .VoltageMode = 0x%02x\n"
2591 " .SnapToDiscrete = 0x%02x\n"
2592 " .NumDiscreteLevels = 0x%02x\n"
2593 " .padding = 0x%02x\n"
2594 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2595 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2596 " .SsFmin = 0x%04x\n"
2597 " .Padding_16 = 0x%04x\n",
2598 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2599 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2600 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2601 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2602 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2603 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2604 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2605 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2606 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2607 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2608 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2609
2610 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2611 " .VoltageMode = 0x%02x\n"
2612 " .SnapToDiscrete = 0x%02x\n"
2613 " .NumDiscreteLevels = 0x%02x\n"
2614 " .padding = 0x%02x\n"
2615 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2616 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2617 " .SsFmin = 0x%04x\n"
2618 " .Padding_16 = 0x%04x\n",
2619 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2620 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2621 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2622 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2623 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2624 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2625 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2626 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2627 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2628 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2629 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2630
2631 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2632 " .VoltageMode = 0x%02x\n"
2633 " .SnapToDiscrete = 0x%02x\n"
2634 " .NumDiscreteLevels = 0x%02x\n"
2635 " .padding = 0x%02x\n"
2636 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2637 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2638 " .SsFmin = 0x%04x\n"
2639 " .Padding_16 = 0x%04x\n",
2640 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2641 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2642 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2643 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2644 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2645 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2646 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2647 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2648 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2649 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2650 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2651
2652 dev_info(smu->adev->dev, "FreqTableGfx\n");
2653 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2654 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2655
2656 dev_info(smu->adev->dev, "FreqTableVclk\n");
2657 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2658 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2659
2660 dev_info(smu->adev->dev, "FreqTableDclk\n");
2661 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2662 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2663
2664 dev_info(smu->adev->dev, "FreqTableSocclk\n");
2665 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2666 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2667
2668 dev_info(smu->adev->dev, "FreqTableUclk\n");
2669 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2670 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2671
2672 dev_info(smu->adev->dev, "FreqTableFclk\n");
2673 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2674 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2675
2676 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2677 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2678 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2679 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2680 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2681 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2682 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2683 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2684 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2685
2686 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2687 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2688 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2689
2690 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2691 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2692
2693 dev_info(smu->adev->dev, "Mp0clkFreq\n");
2694 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2695 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2696
2697 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2698 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2699 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2700
2701 dev_info(smu->adev->dev, "MemVddciVoltage\n");
2702 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2703 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2704
2705 dev_info(smu->adev->dev, "MemMvddVoltage\n");
2706 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2707 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2708
2709 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2710 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2711 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2712 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2713 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2714
2715 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2716
2717 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2718 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2719 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2720 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2721 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2722 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2723 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2724 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2725 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2726 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2727 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2728
2729 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2730 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2731 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2732 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2733 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2734 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2735
2736 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2737 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2738 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2739 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2740 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2741
2742 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2743 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2744 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2745
2746 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2747 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2748 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2749 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2750
2751 dev_info(smu->adev->dev, "UclkDpmPstates\n");
2752 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2753 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2754
2755 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2756 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2757 pptable->UclkDpmSrcFreqRange.Fmin);
2758 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2759 pptable->UclkDpmSrcFreqRange.Fmax);
2760 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2761 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2762 pptable->UclkDpmTargFreqRange.Fmin);
2763 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2764 pptable->UclkDpmTargFreqRange.Fmax);
2765 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2766 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2767
2768 dev_info(smu->adev->dev, "PcieGenSpeed\n");
2769 for (i = 0; i < NUM_LINK_LEVELS; i++)
2770 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2771
2772 dev_info(smu->adev->dev, "PcieLaneCount\n");
2773 for (i = 0; i < NUM_LINK_LEVELS; i++)
2774 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2775
2776 dev_info(smu->adev->dev, "LclkFreq\n");
2777 for (i = 0; i < NUM_LINK_LEVELS; i++)
2778 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2779
2780 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2781 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2782
2783 dev_info(smu->adev->dev, "FanGain\n");
2784 for (i = 0; i < TEMP_COUNT; i++)
2785 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2786
2787 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2788 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2789 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2790 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2791 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2792 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2793 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2794 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2795 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2796 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2797 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2798 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2799
2800 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2801 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2802 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2803 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2804
2805 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2806 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2807 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2808 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2809
2810 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2811 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2812 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2813 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2814 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2815 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2816 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2817 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2818 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2819 pptable->dBtcGbGfxPll.a,
2820 pptable->dBtcGbGfxPll.b,
2821 pptable->dBtcGbGfxPll.c);
2822 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2823 pptable->dBtcGbGfxDfll.a,
2824 pptable->dBtcGbGfxDfll.b,
2825 pptable->dBtcGbGfxDfll.c);
2826 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2827 pptable->dBtcGbSoc.a,
2828 pptable->dBtcGbSoc.b,
2829 pptable->dBtcGbSoc.c);
2830 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2831 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2832 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2833 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2834 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2835 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2836
2837 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2838 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2839 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
2840 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2841 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
2842 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2843 }
2844
2845 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2846 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2847 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2848 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2849 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2850 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2851 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2852 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2853
2854 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2855 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2856
2857 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2858 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2859 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2860 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2861
2862 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2863 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2864 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2865 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2866
2867 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2868 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2869
2870 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2871 for (i = 0; i < NUM_XGMI_LEVELS; i++)
2872 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2873 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2874 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2875
2876 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2877 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2878 pptable->ReservedEquation0.a,
2879 pptable->ReservedEquation0.b,
2880 pptable->ReservedEquation0.c);
2881 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2882 pptable->ReservedEquation1.a,
2883 pptable->ReservedEquation1.b,
2884 pptable->ReservedEquation1.c);
2885 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2886 pptable->ReservedEquation2.a,
2887 pptable->ReservedEquation2.b,
2888 pptable->ReservedEquation2.c);
2889 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2890 pptable->ReservedEquation3.a,
2891 pptable->ReservedEquation3.b,
2892 pptable->ReservedEquation3.c);
2893
2894 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2895 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2896 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2897 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2898 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2899 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2900 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2901 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2902
2903 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2904 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2905 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2906 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2907 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2908 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2909
2910 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2911 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2912 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
2913 pptable->I2cControllers[i].Enabled);
2914 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
2915 pptable->I2cControllers[i].Speed);
2916 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
2917 pptable->I2cControllers[i].SlaveAddress);
2918 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
2919 pptable->I2cControllers[i].ControllerPort);
2920 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
2921 pptable->I2cControllers[i].ControllerName);
2922 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
2923 pptable->I2cControllers[i].ThermalThrotter);
2924 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
2925 pptable->I2cControllers[i].I2cProtocol);
2926 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
2927 pptable->I2cControllers[i].PaddingConfig);
2928 }
2929
2930 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2931 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2932 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2933 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2934
2935 dev_info(smu->adev->dev, "Board Parameters:\n");
2936 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2937 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2938 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2939 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2940 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2941 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2942 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2943 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2944
2945 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2946 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2947 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2948
2949 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2950 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2951 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2952
2953 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2954 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2955 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2956
2957 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2958 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2959 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2960
2961 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2962
2963 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2964 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2965 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2966 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2967 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2968 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2969 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2970 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2971 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2972 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2973 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2974 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2975 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2976 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2977 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2978 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2979
2980 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2981 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2982 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
2983
2984 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2985 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2986 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
2987
2988 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
2989 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2990
2991 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2992 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2993 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2994
2995 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2996 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2997 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2998 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2999 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3000
3001 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3002 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3003
3004 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3005 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3006 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3007 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3008 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3009 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3010 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3011 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3012 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3013 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3014 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3015 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3016
3017 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3018 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3019 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3020 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3021
3022 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3023 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3024 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3025 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3026 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3027 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3028 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3029 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3030 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3031 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3032 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3033
3034 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3035 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3036 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3037 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3038 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3039 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3040 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3041 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3042}
3043
b455159c
LG		 3044static void sienna_cichlid_dump_pptable(struct smu_context *smu)
3045{
3046 struct smu_table_context *table_context = &smu->smu_table;
3047 PPTable_t *pptable = table_context->driver_pptable;
3048 int i;
3049
1d789535 3050 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) {
7077b19a
CG		 3051 beige_goby_dump_pptable(smu);
3052 return;
3053 }
3054
d9811cfc 3055 dev_info(smu->adev->dev, "Dumped PPTable:\n");
b455159c 3056
d9811cfc
EQ		 3057 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
3058 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
3059 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
b455159c
LG		 3060
3061 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
d9811cfc
EQ		 3062 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
3063 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
3064 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
3065 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
b455159c
LG		 3066 }
3067
3068 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
d9811cfc
EQ		 3069 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
3070 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
b455159c
LG		 3071 }
3072
3073 for (i = 0; i < TEMP_COUNT; i++) {
d9811cfc 3074 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
b455159c
LG		 3075 }
3076
d9811cfc
EQ		 3077 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
3078 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
3079 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
3080 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
3081 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
b455159c 3082
d9811cfc 3083 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
b455159c 3084 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
d9811cfc
EQ		 3085 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
3086 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
b455159c 3087 }
d9811cfc
EQ		 3088 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
3089
3090 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
3091
3092 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
3093 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
3094 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
3095 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
3096
3097 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
3098 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
3099
3100 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
3101 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
3102 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
3103 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
3104
3105 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
3106 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
3107 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
3108 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
3109
3110 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
3111 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
3112
3113 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
3114 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
3115 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
3116 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
3117 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
3118 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
3119 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
3120 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
3121
3122 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
b455159c
LG		 3123 " .VoltageMode = 0x%02x\n"
3124 " .SnapToDiscrete = 0x%02x\n"
3125 " .NumDiscreteLevels = 0x%02x\n"
3126 " .padding = 0x%02x\n"
3127 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3128 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3129 " .SsFmin = 0x%04x\n"
3130 " .Padding_16 = 0x%04x\n",
3131 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
3132 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
3133 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
3134 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
3135 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
3136 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
3137 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
3138 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
3139 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
3140 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
3141 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
3142
d9811cfc 3143 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
b455159c
LG		 3144 " .VoltageMode = 0x%02x\n"
3145 " .SnapToDiscrete = 0x%02x\n"
3146 " .NumDiscreteLevels = 0x%02x\n"
3147 " .padding = 0x%02x\n"
3148 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3149 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3150 " .SsFmin = 0x%04x\n"
3151 " .Padding_16 = 0x%04x\n",
3152 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
3153 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
3154 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
3155 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
3156 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
3157 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
3158 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
3159 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
3160 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
3161 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
3162 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
3163
d9811cfc 3164 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
b455159c
LG		 3165 " .VoltageMode = 0x%02x\n"
3166 " .SnapToDiscrete = 0x%02x\n"
3167 " .NumDiscreteLevels = 0x%02x\n"
3168 " .padding = 0x%02x\n"
3169 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3170 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3171 " .SsFmin = 0x%04x\n"
3172 " .Padding_16 = 0x%04x\n",
3173 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
3174 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
3175 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
3176 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
3177 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
3178 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
3179 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
3180 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
3181 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
3182 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
3183 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
3184
d9811cfc 3185 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
b455159c
LG		 3186 " .VoltageMode = 0x%02x\n"
3187 " .SnapToDiscrete = 0x%02x\n"
3188 " .NumDiscreteLevels = 0x%02x\n"
3189 " .padding = 0x%02x\n"
3190 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3191 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3192 " .SsFmin = 0x%04x\n"
3193 " .Padding_16 = 0x%04x\n",
3194 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
3195 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
3196 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
3197 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
3198 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
3199 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
3200 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
3201 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
3202 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
3203 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
3204 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
3205
d9811cfc 3206 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
b455159c
LG		 3207 " .VoltageMode = 0x%02x\n"
3208 " .SnapToDiscrete = 0x%02x\n"
3209 " .NumDiscreteLevels = 0x%02x\n"
3210 " .padding = 0x%02x\n"
3211 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3212 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3213 " .SsFmin = 0x%04x\n"
3214 " .Padding_16 = 0x%04x\n",
3215 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
3216 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
3217 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
3218 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
3219 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
3220 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
3221 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
3222 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
3223 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
3224 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
3225 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
3226
d9811cfc 3227 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
b455159c
LG		 3228 " .VoltageMode = 0x%02x\n"
3229 " .SnapToDiscrete = 0x%02x\n"
3230 " .NumDiscreteLevels = 0x%02x\n"
3231 " .padding = 0x%02x\n"
3232 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3233 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3234 " .SsFmin = 0x%04x\n"
3235 " .Padding_16 = 0x%04x\n",
3236 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
3237 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
3238 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
3239 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
3240 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
3241 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
3242 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
3243 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
3244 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
3245 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
3246 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
3247
d9811cfc 3248 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
b455159c
LG		 3249 " .VoltageMode = 0x%02x\n"
3250 " .SnapToDiscrete = 0x%02x\n"
3251 " .NumDiscreteLevels = 0x%02x\n"
3252 " .padding = 0x%02x\n"
3253 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3254 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3255 " .SsFmin = 0x%04x\n"
3256 " .Padding_16 = 0x%04x\n",
3257 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
3258 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
3259 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
3260 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
3261 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
3262 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
3263 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
3264 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
3265 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
3266 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
3267 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
3268
d9811cfc 3269 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
b455159c
LG		 3270 " .VoltageMode = 0x%02x\n"
3271 " .SnapToDiscrete = 0x%02x\n"
3272 " .NumDiscreteLevels = 0x%02x\n"
3273 " .padding = 0x%02x\n"
3274 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3275 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3276 " .SsFmin = 0x%04x\n"
3277 " .Padding_16 = 0x%04x\n",
3278 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
3279 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
3280 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
3281 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
3282 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
3283 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
3284 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
3285 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
3286 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
3287 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
3288 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
3289
d9811cfc 3290 dev_info(smu->adev->dev, "FreqTableGfx\n");
b455159c 3291 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
d9811cfc 3292 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
b455159c 3293
d9811cfc 3294 dev_info(smu->adev->dev, "FreqTableVclk\n");
b455159c 3295 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
d9811cfc 3296 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
b455159c 3297
d9811cfc 3298 dev_info(smu->adev->dev, "FreqTableDclk\n");
b455159c 3299 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
d9811cfc 3300 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
b455159c 3301
d9811cfc 3302 dev_info(smu->adev->dev, "FreqTableSocclk\n");
b455159c 3303 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
d9811cfc 3304 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
b455159c 3305
d9811cfc 3306 dev_info(smu->adev->dev, "FreqTableUclk\n");
b455159c 3307 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3308 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
b455159c 3309
d9811cfc 3310 dev_info(smu->adev->dev, "FreqTableFclk\n");
b455159c 3311 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
d9811cfc
EQ		 3312 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
3313
d9811cfc
EQ		 3314 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
3315 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
3316 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
3317 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
3318 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
3319 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
3320 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
3321 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
3322 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
3323
3324 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
b455159c 3325 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3326 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
b455159c 3327
d9811cfc
EQ		 3328 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
3329 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
b455159c 3330
d9811cfc 3331 dev_info(smu->adev->dev, "Mp0clkFreq\n");
b455159c 3332 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc 3333 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
b455159c 3334
d9811cfc 3335 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
b455159c 3336 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc 3337 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
b455159c 3338
d9811cfc 3339 dev_info(smu->adev->dev, "MemVddciVoltage\n");
b455159c 3340 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3341 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
b455159c 3342
d9811cfc 3343 dev_info(smu->adev->dev, "MemMvddVoltage\n");
b455159c 3344 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc
EQ		 3345 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
3346
3347 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
3348 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
3349 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
3350 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
3351 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
3352
3353 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
3354
3355 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
3356 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
3357 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
3358 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
3359 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
3360 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
3361 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
3362 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
3363 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
3364 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
3365 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
3366
3367 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
3368 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
3369 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
3370 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
3371 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
3372 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
3373
3374 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
3375 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
3376 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
3377 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
3378 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
3379
3380 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
b455159c 3381 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
d9811cfc 3382 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
b455159c 3383
d9811cfc
EQ		 3384 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
3385 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
3386 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
3387 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
b455159c 3388
d9811cfc 3389 dev_info(smu->adev->dev, "UclkDpmPstates\n");
b455159c 3390 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3391 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
b455159c 3392
d9811cfc
EQ		 3393 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
3394 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
b455159c 3395 pptable->UclkDpmSrcFreqRange.Fmin);
d9811cfc 3396 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
b455159c 3397 pptable->UclkDpmSrcFreqRange.Fmax);
d9811cfc
EQ		 3398 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
3399 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
b455159c 3400 pptable->UclkDpmTargFreqRange.Fmin);
d9811cfc 3401 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
b455159c 3402 pptable->UclkDpmTargFreqRange.Fmax);
d9811cfc
EQ		 3403 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
3404 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
b455159c 3405
d9811cfc 3406 dev_info(smu->adev->dev, "PcieGenSpeed\n");
b455159c 3407 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3408 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
b455159c 3409
d9811cfc 3410 dev_info(smu->adev->dev, "PcieLaneCount\n");
b455159c 3411 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3412 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
b455159c 3413
d9811cfc 3414 dev_info(smu->adev->dev, "LclkFreq\n");
b455159c 3415 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3416 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
b455159c 3417
d9811cfc
EQ		 3418 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
3419 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
b455159c 3420
d9811cfc 3421 dev_info(smu->adev->dev, "FanGain\n");
b455159c 3422 for (i = 0; i < TEMP_COUNT; i++)
d9811cfc
EQ		 3423 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
3424
3425 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
3426 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
3427 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
3428 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
3429 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
3430 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
3431 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
3432 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
3433 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
3434 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
3435 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
3436 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
3437
3438 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
3439 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
3440 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
3441 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
3442
3443 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
3444 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
3445 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
3446 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
3447
3448 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3449 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
3450 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
3451 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
d9811cfc 3452 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3453 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
3454 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
3455 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
d9811cfc 3456 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3457 pptable->dBtcGbGfxPll.a,
3458 pptable->dBtcGbGfxPll.b,
3459 pptable->dBtcGbGfxPll.c);
d9811cfc 3460 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3461 pptable->dBtcGbGfxDfll.a,
3462 pptable->dBtcGbGfxDfll.b,
3463 pptable->dBtcGbGfxDfll.c);
d9811cfc 3464 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3465 pptable->dBtcGbSoc.a,
3466 pptable->dBtcGbSoc.b,
3467 pptable->dBtcGbSoc.c);
d9811cfc 3468 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
b455159c
LG		 3469 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
3470 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
d9811cfc 3471 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
b455159c
LG		 3472 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
3473 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
3474
d9811cfc 3475 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
b455159c 3476 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
d9811cfc 3477 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
b455159c 3478 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
d9811cfc 3479 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
b455159c
LG		 3480 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
3481 }
3482
d9811cfc 3483 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3484 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
3485 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
3486 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
d9811cfc 3487 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3488 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
3489 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
3490 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
3491
d9811cfc
EQ		 3492 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
3493 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
b455159c 3494
d9811cfc
EQ		 3495 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
3496 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
3497 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
3498 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
b455159c 3499
d9811cfc
EQ		 3500 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
3501 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
3502 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
3503 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
b455159c 3504
d9811cfc
EQ		 3505 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
3506 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
b455159c 3507
d9811cfc 3508 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
b455159c 3509 for (i = 0; i < NUM_XGMI_LEVELS; i++)
d9811cfc
EQ		 3510 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
3511 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
3512 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
b455159c 3513
d9811cfc
EQ		 3514 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
3515 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3516 pptable->ReservedEquation0.a,
3517 pptable->ReservedEquation0.b,
3518 pptable->ReservedEquation0.c);
d9811cfc 3519 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3520 pptable->ReservedEquation1.a,
3521 pptable->ReservedEquation1.b,
3522 pptable->ReservedEquation1.c);
d9811cfc 3523 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3524 pptable->ReservedEquation2.a,
3525 pptable->ReservedEquation2.b,
3526 pptable->ReservedEquation2.c);
d9811cfc 3527 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3528 pptable->ReservedEquation3.a,
3529 pptable->ReservedEquation3.b,
3530 pptable->ReservedEquation3.c);
3531
d9811cfc
EQ		 3532 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3533 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3534 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3535 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3536 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3537 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3538 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3539 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
d9811cfc
EQ		 3540
3541 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3542 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3543 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3544 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3545 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3546 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
b455159c
LG		 3547
3548 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
d9811cfc
EQ		 3549 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3550 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
b455159c 3551 pptable->I2cControllers[i].Enabled);
d9811cfc 3552 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
b455159c 3553 pptable->I2cControllers[i].Speed);
d9811cfc 3554 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
b455159c 3555 pptable->I2cControllers[i].SlaveAddress);
d9811cfc 3556 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
b455159c 3557 pptable->I2cControllers[i].ControllerPort);
d9811cfc 3558 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
b455159c 3559 pptable->I2cControllers[i].ControllerName);
d9811cfc 3560 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
b455159c 3561 pptable->I2cControllers[i].ThermalThrotter);
d9811cfc 3562 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
b455159c 3563 pptable->I2cControllers[i].I2cProtocol);
d9811cfc 3564 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
b455159c
LG		 3565 pptable->I2cControllers[i].PaddingConfig);
3566 }
3567
d9811cfc
EQ		 3568 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3569 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3570 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3571 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3572
3573 dev_info(smu->adev->dev, "Board Parameters:\n");
3574 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3575 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3576 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3577 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3578 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3579 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3580 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3581 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3582
3583 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3584 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3585 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3586
3587 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3588 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3589 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3590
3591 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3592 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3593 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3594
3595 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3596 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3597 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3598
3599 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3600
3601 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3602 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3603 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3604 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3605 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3606 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3607 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3608 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3609 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3610 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3611 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3612 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3613 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3614 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3615 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3616 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3617
3618 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3619 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3620 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3621
3622 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3623 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3624 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3625
f0f3d68e 3626 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
d9811cfc
EQ		 3627 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3628
3629 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3630 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3631 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3632
3633 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3634 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3635 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3636 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3637 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3638
3639 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3640 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3641
3642 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
b455159c 3643 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3644 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3645 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
b455159c 3646 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3647 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3648 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
b455159c 3649 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3650 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3651 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
b455159c 3652 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3653 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3654
3655 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3656 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3657 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3658 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3659
3660 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3661 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3662 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3663 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3664 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3665 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3666 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3667 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3668 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3669 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3670 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
d9811cfc
EQ		 3671
3672 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3673 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3674 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3675 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3676 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3677 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3678 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3679 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
b455159c
LG		 3680}
3681
5125c96a 3682static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
ebe57d0c 3683 struct i2c_msg *msg, int num_msgs)
bc50ca29 3684{
2f60dd50
LT		 3685 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
3686 struct amdgpu_device *adev = smu_i2c->adev;
ebfc2533
EQ		 3687 struct smu_context *smu = adev->powerplay.pp_handle;
3688 struct smu_table_context *smu_table = &smu->smu_table;
bc50ca29 3689 struct smu_table *table = &smu_table->driver_table;
5125c96a 3690 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
ebe57d0c
LT		 3691 int i, j, r, c;
3692 u16 dir;
d74a09c8 3693
e281d594
AD		 3694 if (!adev->pm.dpm_enabled)
3695 return -EBUSY;
3696
5125c96a
AD		 3697 req = kzalloc(sizeof(*req), GFP_KERNEL);
3698 if (!req)
3699 return -ENOMEM;
bc50ca29 3700
2f60dd50 3701 req->I2CcontrollerPort = smu_i2c->port;
5125c96a 3702 req->I2CSpeed = I2C_SPEED_FAST_400K;
ebe57d0c
LT		 3703 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
3704 dir = msg[0].flags & I2C_M_RD;
bc50ca29 3705
ebe57d0c
LT		 3706 for (c = i = 0; i < num_msgs; i++) {
3707 for (j = 0; j < msg[i].len; j++, c++) {
3708 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
bc50ca29 3709
5125c96a
AD		 3710 if (!(msg[i].flags & I2C_M_RD)) {
3711 /* write */
3712 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
ebe57d0c
LT		 3713 cmd->ReadWriteData = msg[i].buf[j];
3714 }
3715
3716 if ((dir ^ msg[i].flags) & I2C_M_RD) {
3717 /* The direction changes.
3718 */
3719 dir = msg[i].flags & I2C_M_RD;
3720 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
5125c96a 3721 }
14df5650 3722
ebe57d0c
LT		 3723 req->NumCmds++;
3724
14df5650
AG		 3725 /*
3726 * Insert STOP if we are at the last byte of either last
3727 * message for the transaction or the client explicitly
3728 * requires a STOP at this particular message.
3729 */
ebe57d0c
LT		 3730 if ((j == msg[i].len - 1) &&
3731 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
3732 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
5125c96a 3733 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
ebe57d0c 3734 }
5125c96a 3735 }
d74a09c8 3736 }
e0638c7a 3737 mutex_lock(&adev->pm.mutex);
ebfc2533 3738 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
e0638c7a 3739 mutex_unlock(&adev->pm.mutex);
5125c96a
AD		 3740 if (r)
3741 goto fail;
bc50ca29 3742
ebe57d0c
LT		 3743 for (c = i = 0; i < num_msgs; i++) {
3744 if (!(msg[i].flags & I2C_M_RD)) {
3745 c += msg[i].len;
3746 continue;
3747 }
3748 for (j = 0; j < msg[i].len; j++, c++) {
3749 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
bc50ca29 3750
ebe57d0c 3751 msg[i].buf[j] = cmd->ReadWriteData;
bc50ca29
AD		 3752 }
3753 }
ebe57d0c 3754 r = num_msgs;
bc50ca29 3755fail:
5125c96a 3756 kfree(req);
5125c96a 3757 return r;
bc50ca29
AD		 3758}
3759
3760static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
3761{
3762 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3763}
3764
3765
3766static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
3767 .master_xfer = sienna_cichlid_i2c_xfer,
3768 .functionality = sienna_cichlid_i2c_func,
3769};
3770
35ed2703 3771static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = {
c0838d3a 3772 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
16736627 3773 .max_read_len = MAX_SW_I2C_COMMANDS,
35ed2703 3774 .max_write_len = MAX_SW_I2C_COMMANDS,
16736627
LT		 3775 .max_comb_1st_msg_len = 2,
3776 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
35ed2703
AG		 3777};
3778
2f60dd50 3779static int sienna_cichlid_i2c_control_init(struct smu_context *smu)
bc50ca29 3780{
2f60dd50
LT		 3781 struct amdgpu_device *adev = smu->adev;
3782 int res, i;
3783
3784 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3785 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3786 struct i2c_adapter *control = &smu_i2c->adapter;
3787
3788 smu_i2c->adev = adev;
3789 smu_i2c->port = i;
3790 mutex_init(&smu_i2c->mutex);
3791 control->owner = THIS_MODULE;
3792 control->class = I2C_CLASS_HWMON;
3793 control->dev.parent = &adev->pdev->dev;
3794 control->algo = &sienna_cichlid_i2c_algo;
3795 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
3796 control->quirks = &sienna_cichlid_i2c_control_quirks;
3797 i2c_set_adapdata(control, smu_i2c);
3798
3799 res = i2c_add_adapter(control);
3800 if (res) {
3801 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3802 goto Out_err;
3803 }
3804 }
3805 /* assign the buses used for the FRU EEPROM and RAS EEPROM */
3806 /* XXX ideally this would be something in a vbios data table */
3807 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
3808 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
bc50ca29 3809
2f60dd50
LT		 3810 return 0;
3811Out_err:
3812 for ( ; i >= 0; i--) {
3813 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3814 struct i2c_adapter *control = &smu_i2c->adapter;
bc50ca29 3815
2f60dd50
LT		 3816 i2c_del_adapter(control);
3817 }
bc50ca29
AD		 3818 return res;
3819}
3820
2f60dd50 3821static void sienna_cichlid_i2c_control_fini(struct smu_context *smu)
bc50ca29 3822{
2f60dd50
LT		 3823 struct amdgpu_device *adev = smu->adev;
3824 int i;
3825
3826 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3827 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3828 struct i2c_adapter *control = &smu_i2c->adapter;
3829
3830 i2c_del_adapter(control);
3831 }
3832 adev->pm.ras_eeprom_i2c_bus = NULL;
3833 adev->pm.fru_eeprom_i2c_bus = NULL;
bc50ca29
AD		 3834}
3835
8ca78a0a
EQ		 3836static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
3837 void **table)
3838{
3839 struct smu_table_context *smu_table = &smu->smu_table;
f06d9511
GS		 3840 struct gpu_metrics_v1_3 *gpu_metrics =
3841 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
b4b0b79d
EQ		 3842 SmuMetricsExternal_t metrics_external;
3843 SmuMetrics_t *metrics =
3844 &(metrics_external.SmuMetrics);
be22e2b9
EQ		 3845 SmuMetrics_V2_t *metrics_v2 =
3846 &(metrics_external.SmuMetrics_V2);
7952fa0d
DS		 3847 SmuMetrics_V3_t *metrics_v3 =
3848 &(metrics_external.SmuMetrics_V3);
c524c1c9 3849 struct amdgpu_device *adev = smu->adev;
7952fa0d
DS		 3850 bool use_metrics_v2 = false;
3851 bool use_metrics_v3 = false;
be22e2b9 3852 uint16_t average_gfx_activity;
8ca78a0a
EQ		 3853 int ret = 0;
3854
396beb91
EQ		 3855 switch (smu->adev->ip_versions[MP1_HWIP][0]) {
3856 case IP_VERSION(11, 0, 7):
3857 if (smu->smc_fw_version >= 0x3A4900)
3858 use_metrics_v3 = true;
3859 else if (smu->smc_fw_version >= 0x3A4300)
3860 use_metrics_v2 = true;
3861 break;
3862 case IP_VERSION(11, 0, 11):
3863 if (smu->smc_fw_version >= 0x412D00)
3864 use_metrics_v2 = true;
3865 break;
3866 case IP_VERSION(11, 0, 12):
3867 if (smu->smc_fw_version >= 0x3B2300)
3868 use_metrics_v2 = true;
3869 break;
3870 case IP_VERSION(11, 0, 13):
3871 if (smu->smc_fw_version >= 0x491100)
3872 use_metrics_v2 = true;
3873 break;
3874 default:
3875 break;
3876 }
7952fa0d 3877
da11407f
EQ		 3878 ret = smu_cmn_get_metrics_table(smu,
3879 &metrics_external,
3880 true);
3881 if (ret)
8ca78a0a 3882 return ret;
8ca78a0a 3883
f06d9511 3884 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
8ca78a0a 3885
7952fa0d 3886 gpu_metrics->temperature_edge = use_metrics_v3 ? metrics_v3->TemperatureEdge :
be22e2b9 3887 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge;
7952fa0d 3888 gpu_metrics->temperature_hotspot = use_metrics_v3 ? metrics_v3->TemperatureHotspot :
be22e2b9 3889 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot;
7952fa0d 3890 gpu_metrics->temperature_mem = use_metrics_v3 ? metrics_v3->TemperatureMem :
be22e2b9 3891 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem;
7952fa0d 3892 gpu_metrics->temperature_vrgfx = use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
be22e2b9 3893 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx;
7952fa0d 3894 gpu_metrics->temperature_vrsoc = use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
be22e2b9 3895 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc;
7952fa0d 3896 gpu_metrics->temperature_vrmem = use_metrics_v3 ? metrics_v3->TemperatureVrMem0 :
be22e2b9
EQ		 3897 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0;
3898
7952fa0d 3899 gpu_metrics->average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
be22e2b9 3900 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
7952fa0d 3901 gpu_metrics->average_umc_activity = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
be22e2b9 3902 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity;
7952fa0d
DS		 3903 gpu_metrics->average_mm_activity = use_metrics_v3 ?
3904 (metrics_v3->VcnUsagePercentage0 + metrics_v3->VcnUsagePercentage1) / 2 :
be22e2b9
EQ		 3905 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage;
3906
7952fa0d 3907 gpu_metrics->average_socket_power = use_metrics_v3 ? metrics_v3->AverageSocketPower :
be22e2b9 3908 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower;
7952fa0d 3909 gpu_metrics->energy_accumulator = use_metrics_v3 ? metrics_v3->EnergyAccumulator :
be22e2b9
EQ		 3910 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator;
3911
3a50403f
SK		 3912 if (metrics->CurrGfxVoltageOffset)
3913 gpu_metrics->voltage_gfx =
3914 (155000 - 625 * metrics->CurrGfxVoltageOffset) / 100;
3915 if (metrics->CurrMemVidOffset)
3916 gpu_metrics->voltage_mem =
3917 (155000 - 625 * metrics->CurrMemVidOffset) / 100;
3918 if (metrics->CurrSocVoltageOffset)
3919 gpu_metrics->voltage_soc =
3920 (155000 - 625 * metrics->CurrSocVoltageOffset) / 100;
3921
7952fa0d
DS		 3922 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
3923 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
be22e2b9
EQ		 3924 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
3925 gpu_metrics->average_gfxclk_frequency =
7952fa0d
DS		 3926 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
3927 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
3928 metrics->AverageGfxclkFrequencyPostDs;
8ca78a0a 3929 else
be22e2b9 3930 gpu_metrics->average_gfxclk_frequency =
7952fa0d
DS		 3931 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
3932 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
3933 metrics->AverageGfxclkFrequencyPreDs;
3934
be22e2b9 3935 gpu_metrics->average_uclk_frequency =
7952fa0d
DS		 3936 use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
3937 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
3938 metrics->AverageUclkFrequencyPostDs;
3939 gpu_metrics->average_vclk0_frequency = use_metrics_v3 ? metrics_v3->AverageVclk0Frequency :
be22e2b9 3940 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency;
7952fa0d 3941 gpu_metrics->average_dclk0_frequency = use_metrics_v3 ? metrics_v3->AverageDclk0Frequency :
be22e2b9 3942 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency;
7952fa0d 3943 gpu_metrics->average_vclk1_frequency = use_metrics_v3 ? metrics_v3->AverageVclk1Frequency :
be22e2b9 3944 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency;
7952fa0d 3945 gpu_metrics->average_dclk1_frequency = use_metrics_v3 ? metrics_v3->AverageDclk1Frequency :
be22e2b9
EQ		 3946 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency;
3947
7952fa0d 3948 gpu_metrics->current_gfxclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
be22e2b9 3949 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK];
7952fa0d 3950 gpu_metrics->current_socclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
be22e2b9 3951 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK];
7952fa0d 3952 gpu_metrics->current_uclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
be22e2b9 3953 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK];
7952fa0d 3954 gpu_metrics->current_vclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
be22e2b9 3955 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0];
7952fa0d 3956 gpu_metrics->current_dclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
be22e2b9 3957 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0];
7952fa0d 3958 gpu_metrics->current_vclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
be22e2b9 3959 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1];
7952fa0d 3960 gpu_metrics->current_dclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
be22e2b9
EQ		 3961 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1];
3962
3963 gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu);
f06d9511 3964 gpu_metrics->indep_throttle_status =
be22e2b9 3965 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
f06d9511 3966 sienna_cichlid_throttler_map);
b4b0b79d 3967
7952fa0d
DS		 3968 gpu_metrics->current_fan_speed = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
3969 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
c524c1c9 3970
1d789535
AD		 3971 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) ||
3972 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) {
7952fa0d
DS		 3973 gpu_metrics->pcie_link_width = use_metrics_v3 ? metrics_v3->PcieWidth :
3974 use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
3975 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v3 ? metrics_v3->PcieRate :
3976 use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
c524c1c9
EQ		 3977 } else {
3978 gpu_metrics->pcie_link_width =
3979 smu_v11_0_get_current_pcie_link_width(smu);
3980 gpu_metrics->pcie_link_speed =
3981 smu_v11_0_get_current_pcie_link_speed(smu);
3982 }
8ca78a0a 3983
de4b7cd8
KW		 3984 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3985
8ca78a0a
EQ		 3986 *table = (void *)gpu_metrics;
3987
f06d9511 3988 return sizeof(struct gpu_metrics_v1_3);
8ca78a0a 3989}
bc50ca29 3990
3ddd0c90 3991static int sienna_cichlid_check_ecc_table_support(struct smu_context *smu)
3992{
3993 uint32_t if_version = 0xff, smu_version = 0xff;
3994 int ret = 0;
3995
3996 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
3997 if (ret)
3998 return -EOPNOTSUPP;
3999
4000 if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION)
4001 ret = -EOPNOTSUPP;
4002
4003 return ret;
4004}
4005
4006static ssize_t sienna_cichlid_get_ecc_info(struct smu_context *smu,
4007 void *table)
4008{
4009 struct smu_table_context *smu_table = &smu->smu_table;
4010 EccInfoTable_t *ecc_table = NULL;
4011 struct ecc_info_per_ch *ecc_info_per_channel = NULL;
4012 int i, ret = 0;
4013 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
4014
4015 ret = sienna_cichlid_check_ecc_table_support(smu);
4016 if (ret)
4017 return ret;
4018
4019 ret = smu_cmn_update_table(smu,
4020 SMU_TABLE_ECCINFO,
4021 0,
4022 smu_table->ecc_table,
4023 false);
4024 if (ret) {
4025 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n");
4026 return ret;
4027 }
4028
4029 ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
4030
4031 for (i = 0; i < SIENNA_CICHLID_UMC_CHANNEL_NUM; i++) {
4032 ecc_info_per_channel = &(eccinfo->ecc[i]);
4033 ecc_info_per_channel->ce_count_lo_chip =
4034 ecc_table->EccInfo[i].ce_count_lo_chip;
4035 ecc_info_per_channel->ce_count_hi_chip =
4036 ecc_table->EccInfo[i].ce_count_hi_chip;
4037 ecc_info_per_channel->mca_umc_status =
4038 ecc_table->EccInfo[i].mca_umc_status;
4039 ecc_info_per_channel->mca_umc_addr =
4040 ecc_table->EccInfo[i].mca_umc_addr;
4041 }
4042
4043 return ret;
4044}
05f39286
EQ		 4045static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
4046{
f4e2a66d 4047 uint16_t *mgpu_fan_boost_limit_rpm;
b804a75d 4048
f4e2a66d 4049 GET_PPTABLE_MEMBER(MGpuFanBoostLimitRpm, &mgpu_fan_boost_limit_rpm);
b804a75d
EQ		 4050 /*
4051 * Skip the MGpuFanBoost setting for those ASICs
4052 * which do not support it
4053 */
f4e2a66d 4054 if (*mgpu_fan_boost_limit_rpm == 0)
b804a75d
EQ		 4055 return 0;
4056
05f39286
EQ		 4057 return smu_cmn_send_smc_msg_with_param(smu,
4058 SMU_MSG_SetMGpuFanBoostLimitRpm,
4059 0,
4060 NULL);
4061}
4062
76c71f00
EQ		 4063static int sienna_cichlid_gpo_control(struct smu_context *smu,
4064 bool enablement)
4065{
ac7804bb 4066 uint32_t smu_version;
76c71f00
EQ		 4067 int ret = 0;
4068
ac7804bb 4069
7ade3ca9 4070 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
ac7804bb
EQ		 4071 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
4072 if (ret)
4073 return ret;
4074
4075 if (enablement) {
4076 if (smu_version < 0x003a2500) {
4077 ret = smu_cmn_send_smc_msg_with_param(smu,
4078 SMU_MSG_SetGpoFeaturePMask,
4079 GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
4080 NULL);
4081 } else {
4082 ret = smu_cmn_send_smc_msg_with_param(smu,
4083 SMU_MSG_DisallowGpo,
4084 0,
4085 NULL);
4086 }
4087 } else {
4088 if (smu_version < 0x003a2500) {
4089 ret = smu_cmn_send_smc_msg_with_param(smu,
4090 SMU_MSG_SetGpoFeaturePMask,
4091 0,
4092 NULL);
4093 } else {
4094 ret = smu_cmn_send_smc_msg_with_param(smu,
4095 SMU_MSG_DisallowGpo,
4096 1,
4097 NULL);
4098 }
4099 }
76c71f00
EQ		 4100 }
4101
4102 return ret;
4103}
d7f52e29
EQ		 4104
4105static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
4106{
4107 uint32_t smu_version;
4108 int ret = 0;
4109
4110 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
4111 if (ret)
4112 return ret;
4113
4114 /*
4115 * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
4116 * onwards PMFWs.
4117 */
4118 if (smu_version < 0x003A2D00)
4119 return 0;
4120
4121 return smu_cmn_send_smc_msg_with_param(smu,
4122 SMU_MSG_Enable2ndUSB20Port,
4123 smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
4124 1 : 0,
4125 NULL);
4126}
4127
4128static int sienna_cichlid_system_features_control(struct smu_context *smu,
4129 bool en)
4130{
4131 int ret = 0;
4132
4133 if (en) {
4134 ret = sienna_cichlid_notify_2nd_usb20_port(smu);
4135 if (ret)
4136 return ret;
4137 }
4138
4139 return smu_v11_0_system_features_control(smu, en);
4140}
4141
1689fca0
EQ		 4142static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
4143 enum pp_mp1_state mp1_state)
4144{
9113a0fb
GC		 4145 int ret;
4146
1689fca0
EQ		 4147 switch (mp1_state) {
4148 case PP_MP1_STATE_UNLOAD:
9113a0fb
GC		 4149 ret = smu_cmn_set_mp1_state(smu, mp1_state);
4150 break;
1689fca0 4151 default:
9113a0fb
GC		 4152 /* Ignore others */
4153 ret = 0;
1689fca0
EQ		 4154 }
4155
9113a0fb 4156 return ret;
1689fca0
EQ		 4157}
4158
db5b5c67
AG		 4159static void sienna_cichlid_stb_init(struct smu_context *smu)
4160{
4161 struct amdgpu_device *adev = smu->adev;
4162 uint32_t reg;
4163
4164 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START);
4165 smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE);
4166
4167 /* STB is disabled */
4168 if (!smu->stb_context.enabled)
4169 return;
4170
4171 spin_lock_init(&smu->stb_context.lock);
4172
4173 /* STB buffer size in bytes as function of FIFO depth */
4174 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO);
4175 smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH);
4176 smu->stb_context.stb_buf_size *= SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES;
4177
4178 dev_info(smu->adev->dev, "STB initialized to %d entries",
4179 smu->stb_context.stb_buf_size / SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES);
4180
4181}
4182
c85bf88b
EQ		 4183static int sienna_cichlid_get_default_config_table_settings(struct smu_context *smu,
4184 struct config_table_setting *table)
4185{
4186 struct amdgpu_device *adev = smu->adev;
4187
4188 if (!table)
4189 return -EINVAL;
4190
4191 table->gfxclk_average_tau = 10;
4192 table->socclk_average_tau = 10;
4193 table->fclk_average_tau = 10;
4194 table->uclk_average_tau = 10;
4195 table->gfx_activity_average_tau = 10;
4196 table->mem_activity_average_tau = 10;
4197 table->socket_power_average_tau = 100;
ab9d97d6 4198 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7))
c85bf88b
EQ		 4199 table->apu_socket_power_average_tau = 100;
4200
4201 return 0;
4202}
4203
4204static int sienna_cichlid_set_config_table(struct smu_context *smu,
4205 struct config_table_setting *table)
4206{
4207 DriverSmuConfigExternal_t driver_smu_config_table;
4208
4209 if (!table)
4210 return -EINVAL;
4211
4212 memset(&driver_smu_config_table,
4213 0,
4214 sizeof(driver_smu_config_table));
4215 driver_smu_config_table.DriverSmuConfig.GfxclkAverageLpfTau =
4216 table->gfxclk_average_tau;
4217 driver_smu_config_table.DriverSmuConfig.FclkAverageLpfTau =
4218 table->fclk_average_tau;
4219 driver_smu_config_table.DriverSmuConfig.UclkAverageLpfTau =
4220 table->uclk_average_tau;
4221 driver_smu_config_table.DriverSmuConfig.GfxActivityLpfTau =
4222 table->gfx_activity_average_tau;
4223 driver_smu_config_table.DriverSmuConfig.UclkActivityLpfTau =
4224 table->mem_activity_average_tau;
4225 driver_smu_config_table.DriverSmuConfig.SocketPowerLpfTau =
4226 table->socket_power_average_tau;
4227
4228 return smu_cmn_update_table(smu,
4229 SMU_TABLE_DRIVER_SMU_CONFIG,
4230 0,
4231 (void *)&driver_smu_config_table,
4232 true);
4233}
4234
6a8cf634
AD		 4235static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu,
4236 void *buf,
4237 uint32_t size)
db5b5c67
AG		 4238{
4239 uint32_t *p = buf;
4240 struct amdgpu_device *adev = smu->adev;
4241
4242 /* No need to disable interrupts for now as we don't lock it yet from ISR */
4243 spin_lock(&smu->stb_context.lock);
4244
4245 /*
4246 * Read the STB FIFO in units of 32bit since this is the accessor window
4247 * (register width) we have.
4248 */
4249 buf = ((char *) buf) + size;
4250 while ((void *)p < buf)
4251 *p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3));
4252
4253 spin_unlock(&smu->stb_context.lock);
4254
4255 return 0;
4256}
4257
672c0218
VZ		 4258static bool sienna_cichlid_is_mode2_reset_supported(struct smu_context *smu)
4259{
4260 return true;
4261}
4262
4263static int sienna_cichlid_mode2_reset(struct smu_context *smu)
4264{
4265 u32 smu_version;
4266 int ret = 0, index;
4267 struct amdgpu_device *adev = smu->adev;
4268 int timeout = 100;
4269
4270 smu_cmn_get_smc_version(smu, NULL, &smu_version);
4271
4272 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
4273 SMU_MSG_DriverMode2Reset);
4274
4275 mutex_lock(&smu->message_lock);
4276
4277 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index,
4278 SMU_RESET_MODE_2);
4279
4280 ret = smu_cmn_wait_for_response(smu);
4281 while (ret != 0 && timeout) {
4282 ret = smu_cmn_wait_for_response(smu);
4283 /* Wait a bit more time for getting ACK */
4284 if (ret != 0) {
4285 --timeout;
4286 usleep_range(500, 1000);
4287 continue;
4288 } else {
4289 break;
4290 }
4291 }
4292
4293 if (!timeout) {
4294 dev_err(adev->dev,
4295 "failed to send mode2 message \tparam: 0x%08x response %#x\n",
4296 SMU_RESET_MODE_2, ret);
4297 goto out;
4298 }
4299
4300 dev_info(smu->adev->dev, "restore config space...\n");
4301 /* Restore the config space saved during init */
4302 amdgpu_device_load_pci_state(adev->pdev);
4303out:
4304 mutex_unlock(&smu->message_lock);
4305
4306 return ret;
4307}
4308
b455159c 4309static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
b455159c
LG		 4310 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
4311 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
f6b4b4a1 4312 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
6fb176a7 4313 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
bc50ca29
AD		 4314 .i2c_init = sienna_cichlid_i2c_control_init,
4315 .i2c_fini = sienna_cichlid_i2c_control_fini,
b455159c
LG		 4316 .print_clk_levels = sienna_cichlid_print_clk_levels,
4317 .force_clk_levels = sienna_cichlid_force_clk_levels,
4318 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
b455159c
LG		 4319 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
4320 .display_config_changed = sienna_cichlid_display_config_changed,
4321 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
b455159c 4322 .is_dpm_running = sienna_cichlid_is_dpm_running,
0d8318e1 4323 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
d9ca7567 4324 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
b455159c
LG		 4325 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
4326 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
b455159c
LG		 4327 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
4328 .read_sensor = sienna_cichlid_read_sensor,
4329 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
b2785e25 4330 .set_performance_level = smu_v11_0_set_performance_level,
b455159c
LG		 4331 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
4332 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
4333 .get_power_limit = sienna_cichlid_get_power_limit,
08ccfe08 4334 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
b455159c
LG		 4335 .dump_pptable = sienna_cichlid_dump_pptable,
4336 .init_microcode = smu_v11_0_init_microcode,
4337 .load_microcode = smu_v11_0_load_microcode,
0a2d922a 4338 .fini_microcode = smu_v11_0_fini_microcode,
c1b353b7 4339 .init_smc_tables = sienna_cichlid_init_smc_tables,
b455159c
LG		 4340 .fini_smc_tables = smu_v11_0_fini_smc_tables,
4341 .init_power = smu_v11_0_init_power,
4342 .fini_power = smu_v11_0_fini_power,
4343 .check_fw_status = smu_v11_0_check_fw_status,
4a13b4ce 4344 .setup_pptable = sienna_cichlid_setup_pptable,
b455159c 4345 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
b455159c 4346 .check_fw_version = smu_v11_0_check_fw_version,
caad2613 4347 .write_pptable = smu_cmn_write_pptable,
b455159c
LG		 4348 .set_driver_table_location = smu_v11_0_set_driver_table_location,
4349 .set_tool_table_location = smu_v11_0_set_tool_table_location,
4350 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
d7f52e29 4351 .system_features_control = sienna_cichlid_system_features_control,
66c86828
EQ		 4352 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
4353 .send_smc_msg = smu_cmn_send_smc_msg,
31157341 4354 .init_display_count = NULL,
b455159c 4355 .set_allowed_mask = smu_v11_0_set_allowed_mask,
28251d72 4356 .get_enabled_mask = smu_cmn_get_enabled_mask,
b4bb3aaf 4357 .feature_is_enabled = smu_cmn_feature_is_enabled,
af5ba6d2 4358 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
31157341 4359 .notify_display_change = NULL,
b455159c 4360 .set_power_limit = smu_v11_0_set_power_limit,
b455159c
LG		 4361 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
4362 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
4363 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
ce63d8f8 4364 .set_min_dcef_deep_sleep = NULL,
b455159c
LG		 4365 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
4366 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
4367 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
0d8318e1 4368 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
f3289d04 4369 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
b455159c
LG		 4370 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
4371 .gfx_off_control = smu_v11_0_gfx_off_control,
4372 .register_irq_handler = smu_v11_0_register_irq_handler,
4373 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
4374 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
9fd4781b 4375 .baco_is_support = smu_v11_0_baco_is_support,
b455159c
LG		 4376 .baco_get_state = smu_v11_0_baco_get_state,
4377 .baco_set_state = smu_v11_0_baco_set_state,
13d75ead
EQ		 4378 .baco_enter = sienna_cichlid_baco_enter,
4379 .baco_exit = sienna_cichlid_baco_exit,
ea8139d8
WS		 4380 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
4381 .mode1_reset = smu_v11_0_mode1_reset,
258d290c 4382 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
10e96d89 4383 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
aa75fa34 4384 .set_default_od_settings = sienna_cichlid_set_default_od_settings,
37a58f69 4385 .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
b521be9b 4386 .restore_user_od_settings = smu_v11_0_restore_user_od_settings,
66b8a9c0 4387 .run_btc = sienna_cichlid_run_btc,
18a4b3de 4388 .set_power_source = smu_v11_0_set_power_source,
7dbf7805
EQ		 4389 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
4390 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
8ca78a0a 4391 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
05f39286 4392 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
e988026f 4393 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
5ce99853 4394 .deep_sleep_control = smu_v11_0_deep_sleep_control,
3204ff3e 4395 .get_fan_parameters = sienna_cichlid_get_fan_parameters,
234676d6 4396 .interrupt_work = smu_v11_0_interrupt_work,
76c71f00 4397 .gpo_control = sienna_cichlid_gpo_control,
1689fca0 4398 .set_mp1_state = sienna_cichlid_set_mp1_state,
db5b5c67 4399 .stb_collect_info = sienna_cichlid_stb_get_data_direct,
3ddd0c90 4400 .get_ecc_info = sienna_cichlid_get_ecc_info,
c85bf88b
EQ		 4401 .get_default_config_table_settings = sienna_cichlid_get_default_config_table_settings,
4402 .set_config_table = sienna_cichlid_set_config_table,
ebd9c071 4403 .get_unique_id = sienna_cichlid_get_unique_id,
672c0218
VZ		 4404 .mode2_reset_is_support = sienna_cichlid_is_mode2_reset_supported,
4405 .mode2_reset = sienna_cichlid_mode2_reset,
b455159c
LG		 4406};
4407
4408void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
4409{
4410 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
6c339f37
EQ		 4411 smu->message_map = sienna_cichlid_message_map;
4412 smu->clock_map = sienna_cichlid_clk_map;
4413 smu->feature_map = sienna_cichlid_feature_mask_map;
4414 smu->table_map = sienna_cichlid_table_map;
4415 smu->pwr_src_map = sienna_cichlid_pwr_src_map;
4416 smu->workload_map = sienna_cichlid_workload_map;
da1db031 4417 smu_v11_0_set_smu_mailbox_registers(smu);
b455159c 4418}
Linux 6.x block layer and io_uring tree(s)