projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/amd/pm: Fix power context allocation in SMU13
[linux-block.git] / drivers / gpu / drm / amd / pm / swsmu / smu11 / sienna_cichlid_ppt.c
CommitLineData
b455159c
LG		 1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
d8e0b16d
EQ		 24#define SWSMU_CODE_LAYER_L2
25
b455159c
LG		 26#include <linux/firmware.h>
27#include <linux/pci.h>
bc50ca29 28#include <linux/i2c.h>
b455159c 29#include "amdgpu.h"
2f60dd50 30#include "amdgpu_dpm.h"
b455159c 31#include "amdgpu_smu.h"
b455159c
LG		 32#include "atomfirmware.h"
33#include "amdgpu_atomfirmware.h"
22f2447c 34#include "amdgpu_atombios.h"
b455159c
LG		 35#include "smu_v11_0.h"
36#include "smu11_driver_if_sienna_cichlid.h"
37#include "soc15_common.h"
38#include "atom.h"
39#include "sienna_cichlid_ppt.h"
e05acd78 40#include "smu_v11_0_7_pptable.h"
b455159c 41#include "smu_v11_0_7_ppsmc.h"
40d3b8db 42#include "nbio/nbio_2_3_offset.h"
b7d25b5f 43#include "nbio/nbio_2_3_sh_mask.h"
e05acd78
LG		 44#include "thm/thm_11_0_2_offset.h"
45#include "thm/thm_11_0_2_sh_mask.h"
ea8139d8
WS		 46#include "mp/mp_11_0_offset.h"
47#include "mp/mp_11_0_sh_mask.h"
b455159c 48
6c339f37 49#include "asic_reg/mp/mp_11_0_sh_mask.h"
3ddd0c90 50#include "amdgpu_ras.h"
6c339f37
EQ		 51#include "smu_cmn.h"
52
55084d7f
EQ		 53/*
54 * DO NOT use these for err/warn/info/debug messages.
55 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
56 * They are more MGPU friendly.
57 */
58#undef pr_err
59#undef pr_warn
60#undef pr_info
61#undef pr_debug
62
b455159c
LG		 63#define FEATURE_MASK(feature) (1ULL << feature)
64#define SMC_DPM_FEATURE ( \
65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
fea905d4 66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65297d50 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
5cb74353 68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
4cd4f45b 69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
5f338f70 70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
ce7e5a6e
JC		 71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \
72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
b455159c 73
d817f375
LG		 74#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
75
7077b19a 76#define GET_PPTABLE_MEMBER(field, member) do {\
1d789535 77 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))\
7077b19a
CG		 78 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
79 else\
80 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
81} while(0)
82
db5b5c67
AG		 83/* STB FIFO depth is in 64bit units */
84#define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES 8
85
3ddd0c90 86/*
87 * SMU support ECCTABLE since version 58.70.0,
88 * use this to check whether ECCTABLE feature is supported.
89 */
90#define SUPPORT_ECCTABLE_SMU_VERSION 0x003a4600
91
7077b19a
CG		 92static int get_table_size(struct smu_context *smu)
93{
1d789535 94 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
7077b19a
CG		 95 return sizeof(PPTable_beige_goby_t);
96 else
97 return sizeof(PPTable_t);
98}
99
6c339f37
EQ		 100static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
101 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
102 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
103 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
91190db1
LG		 104 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
105 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
106 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
107 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
6c339f37
EQ		 108 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
109 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
110 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
111 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
112 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
113 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
114 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
91190db1 115 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
4215a119
HC		 116 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
117 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
91190db1
LG		 118 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
119 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
4215a119 120 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
91190db1
LG		 121 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
122 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
66b8a9c0 123 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
91190db1 124 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
4215a119
HC		 125 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
126 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
6c339f37 127 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
91190db1 128 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
6c339f37
EQ		 129 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
130 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
131 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
91190db1
LG		 132 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
133 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
134 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
135 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
136 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
137 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
138 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
139 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
6c339f37 140 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
91190db1
LG		 141 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
142 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
40f1dc52 143 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
6c339f37 144 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
91190db1
LG		 145 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
146 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
147 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
148 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
149 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
150 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
151 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
152 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
05f39286 153 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
76c71f00 154 MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0),
ac7804bb 155 MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0),
88dfd5d5 156 MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0),
672c0218 157 MSG_MAP(DriverMode2Reset, PPSMC_MSG_DriverMode2Reset, 0),
b455159c
LG		 158};
159
6c339f37 160static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
b455159c
LG		 161 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
162 CLK_MAP(SCLK, PPCLK_GFXCLK),
163 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
164 CLK_MAP(FCLK, PPCLK_FCLK),
165 CLK_MAP(UCLK, PPCLK_UCLK),
166 CLK_MAP(MCLK, PPCLK_UCLK),
167 CLK_MAP(DCLK, PPCLK_DCLK_0),
9c0551f2
JC		 168 CLK_MAP(DCLK1, PPCLK_DCLK_1),
169 CLK_MAP(VCLK, PPCLK_VCLK_0),
b455159c
LG		 170 CLK_MAP(VCLK1, PPCLK_VCLK_1),
171 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
172 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
173 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
174 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
175};
176
6c339f37 177static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
b455159c
LG		 178 FEA_MAP(DPM_PREFETCHER),
179 FEA_MAP(DPM_GFXCLK),
31cb0dd9 180 FEA_MAP(DPM_GFX_GPO),
b455159c 181 FEA_MAP(DPM_UCLK),
e9073b43 182 FEA_MAP(DPM_FCLK),
b455159c
LG		 183 FEA_MAP(DPM_SOCCLK),
184 FEA_MAP(DPM_MP0CLK),
185 FEA_MAP(DPM_LINK),
186 FEA_MAP(DPM_DCEFCLK),
e9073b43 187 FEA_MAP(DPM_XGMI),
b455159c
LG		 188 FEA_MAP(MEM_VDDCI_SCALING),
189 FEA_MAP(MEM_MVDD_SCALING),
190 FEA_MAP(DS_GFXCLK),
191 FEA_MAP(DS_SOCCLK),
e9073b43 192 FEA_MAP(DS_FCLK),
b455159c
LG		 193 FEA_MAP(DS_LCLK),
194 FEA_MAP(DS_DCEFCLK),
195 FEA_MAP(DS_UCLK),
196 FEA_MAP(GFX_ULV),
197 FEA_MAP(FW_DSTATE),
198 FEA_MAP(GFXOFF),
199 FEA_MAP(BACO),
6fb176a7 200 FEA_MAP(MM_DPM_PG),
b455159c
LG		 201 FEA_MAP(RSMU_SMN_CG),
202 FEA_MAP(PPT),
203 FEA_MAP(TDC),
204 FEA_MAP(APCC_PLUS),
205 FEA_MAP(GTHR),
206 FEA_MAP(ACDC),
207 FEA_MAP(VR0HOT),
208 FEA_MAP(VR1HOT),
209 FEA_MAP(FW_CTF),
210 FEA_MAP(FAN_CONTROL),
211 FEA_MAP(THERMAL),
212 FEA_MAP(GFX_DCS),
213 FEA_MAP(RM),
214 FEA_MAP(LED_DISPLAY),
215 FEA_MAP(GFX_SS),
216 FEA_MAP(OUT_OF_BAND_MONITOR),
217 FEA_MAP(TEMP_DEPENDENT_VMIN),
218 FEA_MAP(MMHUB_PG),
219 FEA_MAP(ATHUB_PG),
cf06331f 220 FEA_MAP(APCC_DFLL),
b455159c
LG		 221};
222
6c339f37 223static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
b455159c
LG		 224 TAB_MAP(PPTABLE),
225 TAB_MAP(WATERMARKS),
226 TAB_MAP(AVFS_PSM_DEBUG),
227 TAB_MAP(AVFS_FUSE_OVERRIDE),
228 TAB_MAP(PMSTATUSLOG),
229 TAB_MAP(SMU_METRICS),
230 TAB_MAP(DRIVER_SMU_CONFIG),
231 TAB_MAP(ACTIVITY_MONITOR_COEFF),
232 TAB_MAP(OVERDRIVE),
233 TAB_MAP(I2C_COMMANDS),
234 TAB_MAP(PACE),
3ddd0c90 235 TAB_MAP(ECCINFO),
b455159c
LG		 236};
237
6c339f37 238static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
1d5ca713
LG		 239 PWR_MAP(AC),
240 PWR_MAP(DC),
241};
242
6c339f37 243static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
b455159c
LG		 244 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
245 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
246 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
247 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
248 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
4c4d5a49 249 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
b455159c
LG		 250 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
251};
252
f06d9511
GS		 253static const uint8_t sienna_cichlid_throttler_map[] = {
254 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
255 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
256 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
257 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
258 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
259 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
260 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
261 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
262 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
263 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
264 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
265 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
266 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
267 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
268 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
269 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
270 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
271 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
272};
273
b455159c
LG		 274static int
275sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
276 uint32_t *feature_mask, uint32_t num)
277{
fea905d4
LG		 278 struct amdgpu_device *adev = smu->adev;
279
b455159c
LG		 280 if (num > 2)
281 return -EINVAL;
282
283 memset(feature_mask, 0, sizeof(uint32_t) * num);
284
4cd4f45b 285 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
15dbe18f 286 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
ce7e5a6e 287 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
094cdf15 288 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
5f338f70 289 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
86a9eb3f 290 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
80c36f86 291 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
9aa60213
LG		 292 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
293 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
d28f4aa1 294 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
20d71dcc 295 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
d0d71970 296 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
886c8bc6
LG		 297 | FEATURE_MASK(FEATURE_PPT_BIT)
298 | FEATURE_MASK(FEATURE_TDC_BIT)
3fc006f5 299 | FEATURE_MASK(FEATURE_BACO_BIT)
cf06331f 300 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
35ed946c 301 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
1c58d429 302 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
b971df70
LG		 303 | FEATURE_MASK(FEATURE_THERMAL_BIT)
304 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
fea905d4 305
c96721eb 306 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
fea905d4 307 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
c96721eb
KF		 308 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
309 }
fea905d4 310
680602d6 311 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
1d789535 312 (adev->ip_versions[MP1_HWIP][0] > IP_VERSION(11, 0, 7)) &&
680602d6
KF		 313 !(adev->flags & AMD_IS_APU))
314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
315
65297d50 316 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
fc17cd3f
LG		 317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
318 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
319 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
65297d50 320
5cb74353
LG		 321 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
322 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
323
5f338f70
LG		 324 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
325 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
326
fea905d4
LG		 327 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
328 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
b455159c 329
62c1ea6b
LG		 330 if (adev->pm.pp_feature & PP_ULV_MASK)
331 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
332
02bb391d
LG		 333 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
334 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
335
e0da123a
LG		 336 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
337 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
338
b794616d
KF		 339 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
340 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
341
846938c2
KF		 342 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
343 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
344
6fb176a7
LG		 345 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
346 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
347 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
348
62826b86
KF		 349 if (smu->dc_controlled_by_gpio)
350 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
351
0ab5d711 352 if (amdgpu_device_should_use_aspm(adev))
6ef28889
KF		 353 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
354
b455159c
LG		 355 return 0;
356}
357
458020dd 358static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
b455159c 359{
4a13b4ce 360 struct smu_table_context *table_context = &smu->smu_table;
e05acd78 361 struct smu_11_0_7_powerplay_table *powerplay_table =
4a13b4ce
EQ		 362 table_context->power_play_table;
363 struct smu_baco_context *smu_baco = &smu->smu_baco;
458020dd
LL		 364 struct amdgpu_device *adev = smu->adev;
365 uint32_t val;
366
1b41d67e 367 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) {
458020dd
LL		 368 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
369 smu_baco->platform_support =
370 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
371 false;
7bb91228
GC		 372
373 /*
374 * Disable BACO entry/exit completely on below SKUs to
375 * avoid hardware intermittent failures.
376 */
377 if (((adev->pdev->device == 0x73A1) &&
378 (adev->pdev->revision == 0x00)) ||
379 ((adev->pdev->device == 0x73BF) &&
0c85c067
GC		 380 (adev->pdev->revision == 0xCF)) ||
381 ((adev->pdev->device == 0x7422) &&
192039f1
GC		 382 (adev->pdev->revision == 0x00)) ||
383 ((adev->pdev->device == 0x73A3) &&
384 (adev->pdev->revision == 0x00)) ||
385 ((adev->pdev->device == 0x73E3) &&
0c85c067 386 (adev->pdev->revision == 0x00)))
7bb91228
GC		 387 smu_baco->platform_support = false;
388
458020dd
LL		 389 }
390}
391
57301181
ES		 392static void sienna_cichlid_check_fan_support(struct smu_context *smu)
393{
394 struct smu_table_context *table_context = &smu->smu_table;
395 PPTable_t *pptable = table_context->driver_pptable;
396 uint64_t features = *(uint64_t *) pptable->FeaturesToRun;
397
398 /* Fan control is not possible if PPTable has it disabled */
399 smu->adev->pm.no_fan =
400 !(features & (1ULL << FEATURE_FAN_CONTROL_BIT));
401 if (smu->adev->pm.no_fan)
402 dev_info_once(smu->adev->dev,
403 "PMFW based fan control disabled");
404}
405
458020dd
LL		 406static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
407{
408 struct smu_table_context *table_context = &smu->smu_table;
409 struct smu_11_0_7_powerplay_table *powerplay_table =
410 table_context->power_play_table;
4a13b4ce 411
18a4b3de
EQ		 412 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
413 smu->dc_controlled_by_gpio = true;
414
458020dd 415 sienna_cichlid_check_bxco_support(smu);
57301181 416 sienna_cichlid_check_fan_support(smu);
4a13b4ce
EQ		 417
418 table_context->thermal_controller_type =
419 powerplay_table->thermal_controller_type;
420
aa75fa34
EQ		 421 /*
422 * Instead of having its own buffer space and get overdrive_table copied,
423 * smu->od_settings just points to the actual overdrive_table
424 */
425 smu->od_settings = &powerplay_table->overdrive_table;
426
b455159c
LG		 427 return 0;
428}
429
430static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
431{
dccc7c21
LG		 432 struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
433 int index, ret;
7077b19a 434 I2cControllerConfig_t *table_member;
dccc7c21
LG		 435
436 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
437 smc_dpm_info);
438
22f2447c 439 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
dccc7c21
LG		 440 (uint8_t **)&smc_dpm_table);
441 if (ret)
442 return ret;
7077b19a
CG		 443 GET_PPTABLE_MEMBER(I2cControllers, &table_member);
444 memcpy(table_member, smc_dpm_table->I2cControllers,
445 sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
20f5e6cf 446
b455159c
LG		 447 return 0;
448}
449
450static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
451{
b455159c 452 struct smu_table_context *table_context = &smu->smu_table;
e05acd78 453 struct smu_11_0_7_powerplay_table *powerplay_table =
4a13b4ce 454 table_context->power_play_table;
7077b19a 455 int table_size;
b455159c 456
7077b19a 457 table_size = get_table_size(smu);
b455159c 458 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
7077b19a 459 table_size);
b455159c 460
4a13b4ce
EQ		 461 return 0;
462}
b455159c 463
951be8be
EQ		 464static int sienna_cichlid_patch_pptable_quirk(struct smu_context *smu)
465{
466 struct amdgpu_device *adev = smu->adev;
467 uint32_t *board_reserved;
468 uint16_t *freq_table_gfx;
469 uint32_t i;
470
471 /* Fix some OEM SKU specific stability issues */
472 GET_PPTABLE_MEMBER(BoardReserved, &board_reserved);
473 if ((adev->pdev->device == 0x73DF) &&
474 (adev->pdev->revision == 0XC3) &&
475 (adev->pdev->subsystem_device == 0x16C2) &&
476 (adev->pdev->subsystem_vendor == 0x1043))
477 board_reserved[0] = 1387;
478
479 GET_PPTABLE_MEMBER(FreqTableGfx, &freq_table_gfx);
480 if ((adev->pdev->device == 0x73DF) &&
481 (adev->pdev->revision == 0XC3) &&
482 ((adev->pdev->subsystem_device == 0x16C2) ||
483 (adev->pdev->subsystem_device == 0x133C)) &&
484 (adev->pdev->subsystem_vendor == 0x1043)) {
485 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) {
486 if (freq_table_gfx[i] > 2500)
487 freq_table_gfx[i] = 2500;
488 }
489 }
490
491 return 0;
492}
493
4a13b4ce
EQ		 494static int sienna_cichlid_setup_pptable(struct smu_context *smu)
495{
496 int ret = 0;
b455159c 497
4a13b4ce
EQ		 498 ret = smu_v11_0_setup_pptable(smu);
499 if (ret)
500 return ret;
501
502 ret = sienna_cichlid_store_powerplay_table(smu);
503 if (ret)
504 return ret;
505
506 ret = sienna_cichlid_append_powerplay_table(smu);
507 if (ret)
508 return ret;
509
510 ret = sienna_cichlid_check_powerplay_table(smu);
511 if (ret)
512 return ret;
513
951be8be 514 return sienna_cichlid_patch_pptable_quirk(smu);
b455159c
LG		 515}
516
c1b353b7 517static int sienna_cichlid_tables_init(struct smu_context *smu)
b455159c
LG		 518{
519 struct smu_table_context *smu_table = &smu->smu_table;
c1b353b7 520 struct smu_table *tables = smu_table->tables;
7077b19a 521 int table_size;
b455159c 522
7077b19a
CG		 523 table_size = get_table_size(smu);
524 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
525 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c
LG		 526 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
527 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b4b0b79d 528 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
b455159c 529 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
bc50ca29
AD		 530 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
531 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c
LG		 532 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
533 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
534 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
535 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
536 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
f9e3fe46 537 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
b455159c 538 AMDGPU_GEM_DOMAIN_VRAM);
3ddd0c90 539 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
540 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
816d61d5
EQ		 541 SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfigExternal_t),
542 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c 543
b4b0b79d 544 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
b455159c 545 if (!smu_table->metrics_table)
8ca78a0a 546 goto err0_out;
b455159c
LG		 547 smu_table->metrics_time = 0;
548
f06d9511 549 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
8ca78a0a
EQ		 550 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
551 if (!smu_table->gpu_metrics_table)
552 goto err1_out;
553
40d3b8db
LG		 554 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
555 if (!smu_table->watermarks_table)
8ca78a0a 556 goto err2_out;
40d3b8db 557
3ddd0c90 558 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
559 if (!smu_table->ecc_table)
816d61d5
EQ		 560 goto err3_out;
561
562 smu_table->driver_smu_config_table =
563 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL);
564 if (!smu_table->driver_smu_config_table)
565 goto err4_out;
3ddd0c90 566
b455159c 567 return 0;
8ca78a0a 568
816d61d5
EQ		 569err4_out:
570 kfree(smu_table->ecc_table);
571err3_out:
572 kfree(smu_table->watermarks_table);
8ca78a0a
EQ		 573err2_out:
574 kfree(smu_table->gpu_metrics_table);
575err1_out:
576 kfree(smu_table->metrics_table);
577err0_out:
578 return -ENOMEM;
b455159c
LG		 579}
580
be22e2b9
EQ		 581static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu)
582{
583 struct smu_table_context *smu_table= &smu->smu_table;
584 SmuMetricsExternal_t *metrics_ext =
585 (SmuMetricsExternal_t *)(smu_table->metrics_table);
586 uint32_t throttler_status = 0;
587 int i;
588
1d789535 589 if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
7952fa0d
DS		 590 (smu->smc_fw_version >= 0x3A4900)) {
591 for (i = 0; i < THROTTLER_COUNT; i++)
592 throttler_status |=
593 (metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0);
594 } else if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
be22e2b9
EQ		 595 (smu->smc_fw_version >= 0x3A4300)) {
596 for (i = 0; i < THROTTLER_COUNT; i++)
597 throttler_status |=
598 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
599 } else {
600 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus;
601 }
602
603 return throttler_status;
604}
605
d6810d7d
S		 606static int sienna_cichlid_get_power_limit(struct smu_context *smu,
607 uint32_t *current_power_limit,
608 uint32_t *default_power_limit,
609 uint32_t *max_power_limit)
610{
611 struct smu_11_0_7_powerplay_table *powerplay_table =
612 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
613 uint32_t power_limit, od_percent;
614 uint16_t *table_member;
615
616 GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
617
618 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
619 power_limit =
620 table_member[PPT_THROTTLER_PPT0];
621 }
622
623 if (current_power_limit)
624 *current_power_limit = power_limit;
625 if (default_power_limit)
626 *default_power_limit = power_limit;
627
628 if (max_power_limit) {
629 if (smu->od_enabled) {
630 od_percent =
631 le32_to_cpu(powerplay_table->overdrive_table.max[
632 SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
633
634 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n",
635 od_percent, power_limit);
636
637 power_limit *= (100 + od_percent);
638 power_limit /= 100;
639 }
640 *max_power_limit = power_limit;
641 }
642
643 return 0;
644}
645
646static void sienna_cichlid_get_smartshift_power_percentage(struct smu_context *smu,
647 uint32_t *apu_percent,
648 uint32_t *dgpu_percent)
649{
650 struct smu_table_context *smu_table = &smu->smu_table;
651 SmuMetrics_V4_t *metrics_v4 =
652 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V4);
653 uint16_t powerRatio = 0;
654 uint16_t apu_power_limit = 0;
655 uint16_t dgpu_power_limit = 0;
656 uint32_t apu_boost = 0;
657 uint32_t dgpu_boost = 0;
658 uint32_t cur_power_limit;
659
660 if (metrics_v4->ApuSTAPMSmartShiftLimit != 0) {
661 sienna_cichlid_get_power_limit(smu, &cur_power_limit, NULL, NULL);
662 apu_power_limit = metrics_v4->ApuSTAPMLimit;
663 dgpu_power_limit = cur_power_limit;
664 powerRatio = (((apu_power_limit +
665 dgpu_power_limit) * 100) /
666 metrics_v4->ApuSTAPMSmartShiftLimit);
667 if (powerRatio > 100) {
668 apu_power_limit = (apu_power_limit * 100) /
669 powerRatio;
670 dgpu_power_limit = (dgpu_power_limit * 100) /
671 powerRatio;
672 }
673 if (metrics_v4->AverageApuSocketPower > apu_power_limit &&
674 apu_power_limit != 0) {
675 apu_boost = ((metrics_v4->AverageApuSocketPower -
676 apu_power_limit) * 100) /
677 apu_power_limit;
678 if (apu_boost > 100)
679 apu_boost = 100;
680 }
681
682 if (metrics_v4->AverageSocketPower > dgpu_power_limit &&
683 dgpu_power_limit != 0) {
684 dgpu_boost = ((metrics_v4->AverageSocketPower -
685 dgpu_power_limit) * 100) /
686 dgpu_power_limit;
687 if (dgpu_boost > 100)
688 dgpu_boost = 100;
689 }
690
691 if (dgpu_boost >= apu_boost)
692 apu_boost = 0;
693 else
694 dgpu_boost = 0;
695 }
696 *apu_percent = apu_boost;
697 *dgpu_percent = dgpu_boost;
698}
699
60ae4d67
EQ		 700static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
701 MetricsMember_t member,
702 uint32_t *value)
703{
704 struct smu_table_context *smu_table= &smu->smu_table;
b4b0b79d
EQ		 705 SmuMetrics_t *metrics =
706 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
be22e2b9
EQ		 707 SmuMetrics_V2_t *metrics_v2 =
708 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
7952fa0d
DS		 709 SmuMetrics_V3_t *metrics_v3 =
710 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V3);
711 bool use_metrics_v2 = false;
712 bool use_metrics_v3 = false;
be22e2b9 713 uint16_t average_gfx_activity;
60ae4d67 714 int ret = 0;
d6810d7d
S		 715 uint32_t apu_percent = 0;
716 uint32_t dgpu_percent = 0;
60ae4d67 717
396beb91
EQ		 718 switch (smu->adev->ip_versions[MP1_HWIP][0]) {
719 case IP_VERSION(11, 0, 7):
720 if (smu->smc_fw_version >= 0x3A4900)
721 use_metrics_v3 = true;
722 else if (smu->smc_fw_version >= 0x3A4300)
723 use_metrics_v2 = true;
724 break;
725 case IP_VERSION(11, 0, 11):
726 if (smu->smc_fw_version >= 0x412D00)
727 use_metrics_v2 = true;
728 break;
729 case IP_VERSION(11, 0, 12):
730 if (smu->smc_fw_version >= 0x3B2300)
731 use_metrics_v2 = true;
732 break;
733 case IP_VERSION(11, 0, 13):
734 if (smu->smc_fw_version >= 0x491100)
735 use_metrics_v2 = true;
736 break;
737 default:
738 break;
739 }
7952fa0d 740
da11407f
EQ		 741 ret = smu_cmn_get_metrics_table(smu,
742 NULL,
743 false);
744 if (ret)
60ae4d67 745 return ret;
60ae4d67 746
8c686254
EQ		 747 switch (member) {
748 case METRICS_CURR_GFXCLK:
7952fa0d
DS		 749 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
750 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] :
be22e2b9 751 metrics->CurrClock[PPCLK_GFXCLK];
8c686254
EQ		 752 break;
753 case METRICS_CURR_SOCCLK:
7952fa0d
DS		 754 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
755 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] :
be22e2b9 756 metrics->CurrClock[PPCLK_SOCCLK];
8c686254
EQ		 757 break;
758 case METRICS_CURR_UCLK:
7952fa0d
DS		 759 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
760 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] :
be22e2b9 761 metrics->CurrClock[PPCLK_UCLK];
8c686254
EQ		 762 break;
763 case METRICS_CURR_VCLK:
7952fa0d
DS		 764 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
765 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] :
be22e2b9 766 metrics->CurrClock[PPCLK_VCLK_0];
8c686254
EQ		 767 break;
768 case METRICS_CURR_VCLK1:
7952fa0d
DS		 769 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
770 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] :
be22e2b9 771 metrics->CurrClock[PPCLK_VCLK_1];
8c686254
EQ		 772 break;
773 case METRICS_CURR_DCLK:
7952fa0d
DS		 774 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
775 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] :
be22e2b9 776 metrics->CurrClock[PPCLK_DCLK_0];
8c686254
EQ		 777 break;
778 case METRICS_CURR_DCLK1:
7952fa0d
DS		 779 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
780 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
be22e2b9 781 metrics->CurrClock[PPCLK_DCLK_1];
8c686254 782 break;
9d09fa6f 783 case METRICS_CURR_DCEFCLK:
7952fa0d
DS		 784 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCEFCLK] :
785 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] :
be22e2b9 786 metrics->CurrClock[PPCLK_DCEFCLK];
9d09fa6f 787 break;
4e2b3e23 788 case METRICS_CURR_FCLK:
7952fa0d
DS		 789 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_FCLK] :
790 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] :
be22e2b9 791 metrics->CurrClock[PPCLK_FCLK];
4e2b3e23 792 break;
8c686254 793 case METRICS_AVERAGE_GFXCLK:
7952fa0d
DS		 794 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
795 use_metrics_v2 ? metrics_v2->AverageGfxActivity :
be22e2b9
EQ		 796 metrics->AverageGfxActivity;
797 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
7952fa0d
DS		 798 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
799 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
be22e2b9 800 metrics->AverageGfxclkFrequencyPostDs;
d817f375 801 else
7952fa0d
DS		 802 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
803 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
be22e2b9 804 metrics->AverageGfxclkFrequencyPreDs;
8c686254
EQ		 805 break;
806 case METRICS_AVERAGE_FCLK:
7952fa0d
DS		 807 *value = use_metrics_v3 ? metrics_v3->AverageFclkFrequencyPostDs :
808 use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs :
be22e2b9 809 metrics->AverageFclkFrequencyPostDs;
8c686254
EQ		 810 break;
811 case METRICS_AVERAGE_UCLK:
7952fa0d
DS		 812 *value = use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
813 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
be22e2b9 814 metrics->AverageUclkFrequencyPostDs;
8c686254
EQ		 815 break;
816 case METRICS_AVERAGE_GFXACTIVITY:
7952fa0d
DS		 817 *value = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
818 use_metrics_v2 ? metrics_v2->AverageGfxActivity :
be22e2b9 819 metrics->AverageGfxActivity;
8c686254
EQ		 820 break;
821 case METRICS_AVERAGE_MEMACTIVITY:
7952fa0d
DS		 822 *value = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
823 use_metrics_v2 ? metrics_v2->AverageUclkActivity :
be22e2b9 824 metrics->AverageUclkActivity;
8c686254
EQ		 825 break;
826 case METRICS_AVERAGE_SOCKETPOWER:
7952fa0d
DS		 827 *value = use_metrics_v3 ? metrics_v3->AverageSocketPower << 8 :
828 use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 :
be22e2b9 829 metrics->AverageSocketPower << 8;
8c686254
EQ		 830 break;
831 case METRICS_TEMPERATURE_EDGE:
7952fa0d
DS		 832 *value = (use_metrics_v3 ? metrics_v3->TemperatureEdge :
833 use_metrics_v2 ? metrics_v2->TemperatureEdge :
834 metrics->TemperatureEdge) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
8c686254
EQ		 835 break;
836 case METRICS_TEMPERATURE_HOTSPOT:
7952fa0d
DS		 837 *value = (use_metrics_v3 ? metrics_v3->TemperatureHotspot :
838 use_metrics_v2 ? metrics_v2->TemperatureHotspot :
839 metrics->TemperatureHotspot) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
8c686254
EQ		 840 break;
841 case METRICS_TEMPERATURE_MEM:
7952fa0d
DS		 842 *value = (use_metrics_v3 ? metrics_v3->TemperatureMem :
843 use_metrics_v2 ? metrics_v2->TemperatureMem :
844 metrics->TemperatureMem) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
8c686254
EQ		 845 break;
846 case METRICS_TEMPERATURE_VRGFX:
7952fa0d
DS		 847 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
848 use_metrics_v2 ? metrics_v2->TemperatureVrGfx :
849 metrics->TemperatureVrGfx) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
8c686254
EQ		 850 break;
851 case METRICS_TEMPERATURE_VRSOC:
7952fa0d
DS		 852 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
853 use_metrics_v2 ? metrics_v2->TemperatureVrSoc :
854 metrics->TemperatureVrSoc) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
8c686254
EQ		 855 break;
856 case METRICS_THROTTLER_STATUS:
be22e2b9 857 *value = sienna_cichlid_get_throttler_status_locked(smu);
8c686254
EQ		 858 break;
859 case METRICS_CURR_FANSPEED:
7952fa0d
DS		 860 *value = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
861 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
8c686254 862 break;
ebd9c071 863 case METRICS_UNIQUE_ID_UPPER32:
5e9c4451
KR		 864 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
865 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumUpper32 : 0;
ebd9c071
KR		 866 break;
867 case METRICS_UNIQUE_ID_LOWER32:
5e9c4451
KR		 868 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
869 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumLower32 : 0;
ebd9c071 870 break;
d6810d7d
S		 871 case METRICS_SS_APU_SHARE:
872 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
873 *value = apu_percent;
874 break;
875 case METRICS_SS_DGPU_SHARE:
876 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
877 *value = dgpu_percent;
878 break;
879
8c686254
EQ		 880 default:
881 *value = UINT_MAX;
882 break;
883 }
884
b455159c 885 return ret;
8c686254 886
b455159c
LG		 887}
888
889static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
890{
891 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
892
b455159c
LG		 893 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
894 GFP_KERNEL);
895 if (!smu_dpm->dpm_context)
896 return -ENOMEM;
897
898 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
899
900 return 0;
901}
902
db5b5c67
AG		 903static void sienna_cichlid_stb_init(struct smu_context *smu);
904
c1b353b7
EQ		 905static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
906{
748262eb 907 struct amdgpu_device *adev = smu->adev;
c1b353b7
EQ		 908 int ret = 0;
909
910 ret = sienna_cichlid_tables_init(smu);
911 if (ret)
912 return ret;
913
914 ret = sienna_cichlid_allocate_dpm_context(smu);
915 if (ret)
916 return ret;
917
748262eb 918 if (!amdgpu_sriov_vf(adev))
919 sienna_cichlid_stb_init(smu);
db5b5c67 920
c1b353b7
EQ		 921 return smu_v11_0_init_smc_tables(smu);
922}
923
b455159c
LG		 924static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
925{
90a89c31 926 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
90a89c31 927 struct smu_11_0_dpm_table *dpm_table;
85dec717 928 struct amdgpu_device *adev = smu->adev;
0b54122c 929 int i, ret = 0;
7077b19a 930 DpmDescriptor_t *table_member;
b455159c 931
90a89c31
EQ		 932 /* socclk dpm table setup */
933 dpm_table = &dpm_context->dpm_tables.soc_table;
7077b19a 934 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
b4bb3aaf 935 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
90a89c31
EQ		 936 ret = smu_v11_0_set_single_dpm_table(smu,
937 SMU_SOCCLK,
938 dpm_table);
939 if (ret)
940 return ret;
941 dpm_table->is_fine_grained =
7077b19a 942 !table_member[PPCLK_SOCCLK].SnapToDiscrete;
90a89c31
EQ		 943 } else {
944 dpm_table->count = 1;
945 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
946 dpm_table->dpm_levels[0].enabled = true;
947 dpm_table->min = dpm_table->dpm_levels[0].value;
948 dpm_table->max = dpm_table->dpm_levels[0].value;
949 }
b455159c 950
90a89c31
EQ		 951 /* gfxclk dpm table setup */
952 dpm_table = &dpm_context->dpm_tables.gfx_table;
b4bb3aaf 953 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
90a89c31
EQ		 954 ret = smu_v11_0_set_single_dpm_table(smu,
955 SMU_GFXCLK,
956 dpm_table);
957 if (ret)
958 return ret;
959 dpm_table->is_fine_grained =
7077b19a 960 !table_member[PPCLK_GFXCLK].SnapToDiscrete;
90a89c31
EQ		 961 } else {
962 dpm_table->count = 1;
963 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
964 dpm_table->dpm_levels[0].enabled = true;
965 dpm_table->min = dpm_table->dpm_levels[0].value;
966 dpm_table->max = dpm_table->dpm_levels[0].value;
967 }
b455159c 968
90a89c31
EQ		 969 /* uclk dpm table setup */
970 dpm_table = &dpm_context->dpm_tables.uclk_table;
b4bb3aaf 971 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
90a89c31
EQ		 972 ret = smu_v11_0_set_single_dpm_table(smu,
973 SMU_UCLK,
974 dpm_table);
975 if (ret)
976 return ret;
977 dpm_table->is_fine_grained =
7077b19a 978 !table_member[PPCLK_UCLK].SnapToDiscrete;
90a89c31
EQ		 979 } else {
980 dpm_table->count = 1;
981 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
982 dpm_table->dpm_levels[0].enabled = true;
983 dpm_table->min = dpm_table->dpm_levels[0].value;
984 dpm_table->max = dpm_table->dpm_levels[0].value;
985 }
b455159c 986
90a89c31
EQ		 987 /* fclk dpm table setup */
988 dpm_table = &dpm_context->dpm_tables.fclk_table;
b4bb3aaf 989 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
90a89c31
EQ		 990 ret = smu_v11_0_set_single_dpm_table(smu,
991 SMU_FCLK,
992 dpm_table);
993 if (ret)
994 return ret;
995 dpm_table->is_fine_grained =
7077b19a 996 !table_member[PPCLK_FCLK].SnapToDiscrete;
90a89c31
EQ		 997 } else {
998 dpm_table->count = 1;
999 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
1000 dpm_table->dpm_levels[0].enabled = true;
1001 dpm_table->min = dpm_table->dpm_levels[0].value;
1002 dpm_table->max = dpm_table->dpm_levels[0].value;
1003 }
b455159c 1004
0b54122c
AD		 1005 /* vclk0/1 dpm table setup */
1006 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1007 if (adev->vcn.harvest_config & (1 << i))
1008 continue;
b455159c 1009
0b54122c 1010 dpm_table = &dpm_context->dpm_tables.vclk_table;
85dec717
JC		 1011 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1012 ret = smu_v11_0_set_single_dpm_table(smu,
0b54122c 1013 i ? SMU_VCLK1 : SMU_VCLK,
85dec717
JC		 1014 dpm_table);
1015 if (ret)
1016 return ret;
1017 dpm_table->is_fine_grained =
0b54122c 1018 !table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete;
85dec717
JC		 1019 } else {
1020 dpm_table->count = 1;
0b54122c 1021 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
85dec717
JC		 1022 dpm_table->dpm_levels[0].enabled = true;
1023 dpm_table->min = dpm_table->dpm_levels[0].value;
1024 dpm_table->max = dpm_table->dpm_levels[0].value;
1025 }
90a89c31 1026 }
b455159c 1027
0b54122c
AD		 1028 /* dclk0/1 dpm table setup */
1029 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1030 if (adev->vcn.harvest_config & (1 << i))
1031 continue;
1032 dpm_table = &dpm_context->dpm_tables.dclk_table;
85dec717
JC		 1033 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1034 ret = smu_v11_0_set_single_dpm_table(smu,
0b54122c 1035 i ? SMU_DCLK1 : SMU_DCLK,
85dec717
JC		 1036 dpm_table);
1037 if (ret)
1038 return ret;
1039 dpm_table->is_fine_grained =
0b54122c 1040 !table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0].SnapToDiscrete;
85dec717
JC		 1041 } else {
1042 dpm_table->count = 1;
0b54122c 1043 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
85dec717
JC		 1044 dpm_table->dpm_levels[0].enabled = true;
1045 dpm_table->min = dpm_table->dpm_levels[0].value;
1046 dpm_table->max = dpm_table->dpm_levels[0].value;
1047 }
90a89c31
EQ		 1048 }
1049
1050 /* dcefclk dpm table setup */
1051 dpm_table = &dpm_context->dpm_tables.dcef_table;
b4bb3aaf 1052 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 1053 ret = smu_v11_0_set_single_dpm_table(smu,
1054 SMU_DCEFCLK,
1055 dpm_table);
1056 if (ret)
1057 return ret;
1058 dpm_table->is_fine_grained =
7077b19a 1059 !table_member[PPCLK_DCEFCLK].SnapToDiscrete;
90a89c31
EQ		 1060 } else {
1061 dpm_table->count = 1;
1062 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1063 dpm_table->dpm_levels[0].enabled = true;
1064 dpm_table->min = dpm_table->dpm_levels[0].value;
1065 dpm_table->max = dpm_table->dpm_levels[0].value;
1066 }
b455159c 1067
90a89c31
EQ		 1068 /* pixelclk dpm table setup */
1069 dpm_table = &dpm_context->dpm_tables.pixel_table;
b4bb3aaf 1070 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 1071 ret = smu_v11_0_set_single_dpm_table(smu,
1072 SMU_PIXCLK,
1073 dpm_table);
1074 if (ret)
1075 return ret;
1076 dpm_table->is_fine_grained =
7077b19a 1077 !table_member[PPCLK_PIXCLK].SnapToDiscrete;
90a89c31
EQ		 1078 } else {
1079 dpm_table->count = 1;
1080 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1081 dpm_table->dpm_levels[0].enabled = true;
1082 dpm_table->min = dpm_table->dpm_levels[0].value;
1083 dpm_table->max = dpm_table->dpm_levels[0].value;
1084 }
b455159c 1085
90a89c31
EQ		 1086 /* displayclk dpm table setup */
1087 dpm_table = &dpm_context->dpm_tables.display_table;
b4bb3aaf 1088 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 1089 ret = smu_v11_0_set_single_dpm_table(smu,
1090 SMU_DISPCLK,
1091 dpm_table);
1092 if (ret)
1093 return ret;
1094 dpm_table->is_fine_grained =
7077b19a 1095 !table_member[PPCLK_DISPCLK].SnapToDiscrete;
90a89c31
EQ		 1096 } else {
1097 dpm_table->count = 1;
1098 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1099 dpm_table->dpm_levels[0].enabled = true;
1100 dpm_table->min = dpm_table->dpm_levels[0].value;
1101 dpm_table->max = dpm_table->dpm_levels[0].value;
1102 }
b455159c 1103
90a89c31
EQ		 1104 /* phyclk dpm table setup */
1105 dpm_table = &dpm_context->dpm_tables.phy_table;
b4bb3aaf 1106 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 1107 ret = smu_v11_0_set_single_dpm_table(smu,
1108 SMU_PHYCLK,
1109 dpm_table);
1110 if (ret)
1111 return ret;
1112 dpm_table->is_fine_grained =
7077b19a 1113 !table_member[PPCLK_PHYCLK].SnapToDiscrete;
90a89c31
EQ		 1114 } else {
1115 dpm_table->count = 1;
1116 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1117 dpm_table->dpm_levels[0].enabled = true;
1118 dpm_table->min = dpm_table->dpm_levels[0].value;
1119 dpm_table->max = dpm_table->dpm_levels[0].value;
1120 }
b455159c
LG		 1121
1122 return 0;
1123}
1124
f6b4b4a1 1125static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
b455159c 1126{
d51dc613 1127 struct amdgpu_device *adev = smu->adev;
0b54122c 1128 int i, ret = 0;
b455159c 1129
0b54122c
AD		 1130 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1131 if (adev->vcn.harvest_config & (1 << i))
1132 continue;
b455159c 1133 /* vcn dpm on is a prerequisite for vcn power gate messages */
b4bb3aaf 1134 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
0b54122c
AD		 1135 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1136 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
1137 0x10000 * i, NULL);
6fb176a7
LG		 1138 if (ret)
1139 return ret;
b455159c 1140 }
b455159c
LG		 1141 }
1142
1143 return ret;
1144}
1145
6fb176a7
LG		 1146static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
1147{
6fb176a7
LG		 1148 int ret = 0;
1149
1150 if (enable) {
b4bb3aaf 1151 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 1152 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
6fb176a7
LG		 1153 if (ret)
1154 return ret;
6fb176a7 1155 }
6fb176a7 1156 } else {
b4bb3aaf 1157 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 1158 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
6fb176a7
LG		 1159 if (ret)
1160 return ret;
6fb176a7 1161 }
6fb176a7
LG		 1162 }
1163
1164 return ret;
1165}
1166
b455159c
LG		 1167static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
1168 enum smu_clk_type clk_type,
1169 uint32_t *value)
1170{
8c686254
EQ		 1171 MetricsMember_t member_type;
1172 int clk_id = 0;
b455159c 1173
6c339f37
EQ		 1174 clk_id = smu_cmn_to_asic_specific_index(smu,
1175 CMN2ASIC_MAPPING_CLK,
1176 clk_type);
b455159c
LG		 1177 if (clk_id < 0)
1178 return clk_id;
1179
8c686254
EQ		 1180 switch (clk_id) {
1181 case PPCLK_GFXCLK:
1182 member_type = METRICS_CURR_GFXCLK;
1183 break;
1184 case PPCLK_UCLK:
1185 member_type = METRICS_CURR_UCLK;
1186 break;
1187 case PPCLK_SOCCLK:
1188 member_type = METRICS_CURR_SOCCLK;
1189 break;
1190 case PPCLK_FCLK:
1191 member_type = METRICS_CURR_FCLK;
1192 break;
1193 case PPCLK_VCLK_0:
1194 member_type = METRICS_CURR_VCLK;
1195 break;
1196 case PPCLK_VCLK_1:
1197 member_type = METRICS_CURR_VCLK1;
1198 break;
1199 case PPCLK_DCLK_0:
1200 member_type = METRICS_CURR_DCLK;
1201 break;
1202 case PPCLK_DCLK_1:
1203 member_type = METRICS_CURR_DCLK1;
1204 break;
1205 case PPCLK_DCEFCLK:
1206 member_type = METRICS_CURR_DCEFCLK;
1207 break;
1208 default:
1209 return -EINVAL;
1210 }
1211
1212 return sienna_cichlid_get_smu_metrics_data(smu,
1213 member_type,
1214 value);
b455159c 1215
b455159c
LG		 1216}
1217
1218static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1219{
b455159c 1220 DpmDescriptor_t *dpm_desc = NULL;
7077b19a 1221 DpmDescriptor_t *table_member;
b455159c
LG		 1222 uint32_t clk_index = 0;
1223
7077b19a 1224 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
6c339f37
EQ		 1225 clk_index = smu_cmn_to_asic_specific_index(smu,
1226 CMN2ASIC_MAPPING_CLK,
1227 clk_type);
7077b19a 1228 dpm_desc = &table_member[clk_index];
b455159c
LG		 1229
1230 /* 0 - Fine grained DPM, 1 - Discrete DPM */
0ee56acc 1231 return dpm_desc->SnapToDiscrete == 0;
b455159c
LG		 1232}
1233
37a58f69
EQ		 1234static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
1235 enum SMU_11_0_7_ODFEATURE_CAP cap)
1236{
1237 return od_table->cap[cap];
1238}
1239
1240static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
1241 enum SMU_11_0_7_ODSETTING_ID setting,
1242 uint32_t *min, uint32_t *max)
1243{
1244 if (min)
1245 *min = od_table->min[setting];
1246 if (max)
1247 *max = od_table->max[setting];
1248}
1249
b455159c
LG		 1250static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
1251 enum smu_clk_type clk_type, char *buf)
1252{
b7d25b5f
LG		 1253 struct amdgpu_device *adev = smu->adev;
1254 struct smu_table_context *table_context = &smu->smu_table;
1255 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1256 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
7077b19a
CG		 1257 uint16_t *table_member;
1258
37a58f69
EQ		 1259 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
1260 OverDriveTable_t *od_table =
1261 (OverDriveTable_t *)table_context->overdrive_table;
b455159c
LG		 1262 int i, size = 0, ret = 0;
1263 uint32_t cur_value = 0, value = 0, count = 0;
1264 uint32_t freq_values[3] = {0};
1265 uint32_t mark_index = 0;
b7d25b5f 1266 uint32_t gen_speed, lane_width;
37a58f69 1267 uint32_t min_value, max_value;
a2b6df4f 1268 uint32_t smu_version;
b455159c 1269
8f48ba30
LY		 1270 smu_cmn_get_sysfs_buf(&buf, &size);
1271
b455159c
LG		 1272 switch (clk_type) {
1273 case SMU_GFXCLK:
1274 case SMU_SCLK:
1275 case SMU_SOCCLK:
1276 case SMU_MCLK:
1277 case SMU_UCLK:
1278 case SMU_FCLK:
78842457
DN		 1279 case SMU_VCLK:
1280 case SMU_VCLK1:
1281 case SMU_DCLK:
1282 case SMU_DCLK1:
b455159c 1283 case SMU_DCEFCLK:
5e6dc8fe 1284 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
b455159c 1285 if (ret)
258d290c 1286 goto print_clk_out;
b455159c 1287
d8d3493a 1288 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
b455159c 1289 if (ret)
258d290c 1290 goto print_clk_out;
b455159c
LG		 1291
1292 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1293 for (i = 0; i < count; i++) {
d8d3493a 1294 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
b455159c 1295 if (ret)
258d290c 1296 goto print_clk_out;
b455159c 1297
fe14c285 1298 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
b455159c
LG		 1299 cur_value == value ? "*" : "");
1300 }
1301 } else {
d8d3493a 1302 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
b455159c 1303 if (ret)
258d290c 1304 goto print_clk_out;
d8d3493a 1305 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
b455159c 1306 if (ret)
258d290c 1307 goto print_clk_out;
b455159c
LG		 1308
1309 freq_values[1] = cur_value;
1310 mark_index = cur_value == freq_values[0] ? 0 :
1311 cur_value == freq_values[2] ? 2 : 1;
b455159c 1312
891bacb8
KF		 1313 count = 3;
1314 if (mark_index != 1) {
1315 count = 2;
1316 freq_values[1] = freq_values[2];
1317 }
1318
1319 for (i = 0; i < count; i++) {
fe14c285 1320 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
891bacb8 1321 cur_value == freq_values[i] ? "*" : "");
b455159c
LG		 1322 }
1323
1324 }
1325 break;
b7d25b5f 1326 case SMU_PCIE:
f20c52f4
LG		 1327 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1328 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
7077b19a 1329 GET_PPTABLE_MEMBER(LclkFreq, &table_member);
b7d25b5f 1330 for (i = 0; i < NUM_LINK_LEVELS; i++)
fe14c285 1331 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
b7d25b5f
LG		 1332 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1333 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1334 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1335 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1336 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1337 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1338 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1339 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1340 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1341 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
7077b19a 1342 table_member[i],
b7d25b5f
LG		 1343 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1344 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1345 "*" : "");
1346 break;
37a58f69
EQ		 1347 case SMU_OD_SCLK:
1348 if (!smu->od_enabled || !od_table || !od_settings)
1349 break;
1350
1351 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1352 break;
1353
fe14c285
DP		 1354 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1355 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
37a58f69
EQ		 1356 break;
1357
1358 case SMU_OD_MCLK:
1359 if (!smu->od_enabled || !od_table || !od_settings)
1360 break;
1361
1362 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1363 break;
1364
fe14c285
DP		 1365 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1366 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
37a58f69
EQ		 1367 break;
1368
a2b6df4f
EQ		 1369 case SMU_OD_VDDGFX_OFFSET:
1370 if (!smu->od_enabled || !od_table || !od_settings)
1371 break;
1372
1373 /*
1374 * OD GFX Voltage Offset functionality is supported only by 58.41.0
1375 * and onwards SMU firmwares.
1376 */
1377 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1d789535 1378 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
a2b6df4f
EQ		 1379 (smu_version < 0x003a2900))
1380 break;
1381
fe14c285
DP		 1382 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1383 size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset);
a2b6df4f
EQ		 1384 break;
1385
37a58f69
EQ		 1386 case SMU_OD_RANGE:
1387 if (!smu->od_enabled || !od_table || !od_settings)
1388 break;
1389
8f48ba30 1390 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
37a58f69
EQ		 1391
1392 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1393 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1394 &min_value, NULL);
1395 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1396 NULL, &max_value);
fe14c285 1397 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
37a58f69
EQ		 1398 min_value, max_value);
1399 }
1400
1401 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1402 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1403 &min_value, NULL);
1404 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1405 NULL, &max_value);
fe14c285 1406 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
37a58f69
EQ		 1407 min_value, max_value);
1408 }
1409 break;
1410
b455159c
LG		 1411 default:
1412 break;
1413 }
1414
258d290c 1415print_clk_out:
b455159c
LG		 1416 return size;
1417}
1418
1419static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1420 enum smu_clk_type clk_type, uint32_t mask)
1421{
d3c98301 1422 int ret = 0;
b455159c
LG		 1423 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1424
1425 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1426 soft_max_level = mask ? (fls(mask) - 1) : 0;
1427
1428 switch (clk_type) {
1429 case SMU_GFXCLK:
1430 case SMU_SCLK:
1431 case SMU_SOCCLK:
1432 case SMU_MCLK:
1433 case SMU_UCLK:
b455159c 1434 case SMU_FCLK:
9ad9c8ac
LG		 1435 /* There is only 2 levels for fine grained DPM */
1436 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1437 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1438 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1439 }
1440
d8d3493a 1441 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
b455159c 1442 if (ret)
258d290c 1443 goto forec_level_out;
b455159c 1444
d8d3493a 1445 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
b455159c 1446 if (ret)
258d290c 1447 goto forec_level_out;
b455159c 1448
10e96d89 1449 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
b455159c 1450 if (ret)
258d290c 1451 goto forec_level_out;
b455159c 1452 break;
51ec6992
DP		 1453 case SMU_DCEFCLK:
1454 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1455 break;
b455159c
LG		 1456 default:
1457 break;
1458 }
1459
258d290c 1460forec_level_out:
d3c98301 1461 return 0;
b455159c
LG		 1462}
1463
1464static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1465{
62cc9dd1
EQ		 1466 struct smu_11_0_dpm_context *dpm_context =
1467 smu->smu_dpm.dpm_context;
1468 struct smu_11_0_dpm_table *gfx_table =
1469 &dpm_context->dpm_tables.gfx_table;
1470 struct smu_11_0_dpm_table *mem_table =
1471 &dpm_context->dpm_tables.uclk_table;
1472 struct smu_11_0_dpm_table *soc_table =
1473 &dpm_context->dpm_tables.soc_table;
1474 struct smu_umd_pstate_table *pstate_table =
1475 &smu->pstate_table;
60aac460 1476 struct amdgpu_device *adev = smu->adev;
62cc9dd1
EQ		 1477
1478 pstate_table->gfxclk_pstate.min = gfx_table->min;
1479 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1480
1481 pstate_table->uclk_pstate.min = mem_table->min;
1482 pstate_table->uclk_pstate.peak = mem_table->max;
1483
1484 pstate_table->socclk_pstate.min = soc_table->min;
1485 pstate_table->socclk_pstate.peak = soc_table->max;
60aac460 1486
9d6b2041
AD		 1487 switch (adev->ip_versions[MP1_HWIP][0]) {
1488 case IP_VERSION(11, 0, 7):
1489 case IP_VERSION(11, 0, 11):
60aac460
EQ		 1490 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
1491 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
0dc994fb 1492 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
60aac460 1493 break;
9d6b2041 1494 case IP_VERSION(11, 0, 12):
60aac460
EQ		 1495 pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK;
1496 pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK;
1497 pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK;
1498 break;
9d6b2041 1499 case IP_VERSION(11, 0, 13):
60aac460
EQ		 1500 pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK;
1501 pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK;
1502 pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK;
1503 break;
1504 default:
1505 break;
1506 }
b455159c 1507
62cc9dd1 1508 return 0;
b455159c
LG		 1509}
1510
b455159c
LG		 1511static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1512{
1513 int ret = 0;
1514 uint32_t max_freq = 0;
1515
1516 /* Sienna_Cichlid do not support to change display num currently */
1517 return 0;
1518#if 0
66c86828 1519 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
b455159c
LG		 1520 if (ret)
1521 return ret;
1522#endif
1523
b4bb3aaf 1524 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
e5ef784b 1525 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
b455159c
LG		 1526 if (ret)
1527 return ret;
661b94f5 1528 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
b455159c
LG		 1529 if (ret)
1530 return ret;
1531 }
1532
1533 return ret;
1534}
1535
1536static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1537{
1538 int ret = 0;
1539
b455159c 1540 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
7ade3ca9
EQ		 1541 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1542 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
b455159c 1543#if 0
66c86828 1544 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
40d3b8db
LG		 1545 smu->display_config->num_display,
1546 NULL);
b455159c
LG		 1547#endif
1548 if (ret)
1549 return ret;
1550 }
1551
1552 return ret;
1553}
1554
b455159c
LG		 1555static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1556{
1557 int ret = 0;
3d14a79b
KW		 1558 uint64_t feature_enabled;
1559
2d282665 1560 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
3d14a79b
KW		 1561 if (ret)
1562 return false;
1563
b455159c
LG		 1564 return !!(feature_enabled & SMC_DPM_FEATURE);
1565}
1566
d9ca7567
EQ		 1567static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1568 uint32_t *speed)
1569{
1570 if (!speed)
1571 return -EINVAL;
1572
1573 /*
1574 * For Sienna_Cichlid and later, the fan speed(rpm) reported
1575 * by pmfw is always trustable(even when the fan control feature
1576 * disabled or 0 RPM kicked in).
1577 */
1578 return sienna_cichlid_get_smu_metrics_data(smu,
1579 METRICS_CURR_FANSPEED,
1580 speed);
1581}
1582
3204ff3e
AD		 1583static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1584{
7077b19a 1585 uint16_t *table_member;
3204ff3e 1586
7077b19a
CG		 1587 GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
1588 smu->fan_max_rpm = *table_member;
3204ff3e
AD		 1589
1590 return 0;
1591}
1592
b455159c
LG		 1593static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1594{
f9e3fe46
EQ		 1595 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1596 DpmActivityMonitorCoeffInt_t *activity_monitor =
1597 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
b455159c
LG		 1598 uint32_t i, size = 0;
1599 int16_t workload_type = 0;
b455159c
LG		 1600 static const char *title[] = {
1601 "PROFILE_INDEX(NAME)",
1602 "CLOCK_TYPE(NAME)",
1603 "FPS",
1604 "MinFreqType",
1605 "MinActiveFreqType",
1606 "MinActiveFreq",
1607 "BoosterFreqType",
1608 "BoosterFreq",
1609 "PD_Data_limit_c",
1610 "PD_Data_error_coeff",
1611 "PD_Data_error_rate_coeff"};
1612 int result = 0;
1613
1614 if (!buf)
1615 return -EINVAL;
1616
fe14c285 1617 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
b455159c
LG		 1618 title[0], title[1], title[2], title[3], title[4], title[5],
1619 title[6], title[7], title[8], title[9], title[10]);
1620
1621 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1622 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
6c339f37
EQ		 1623 workload_type = smu_cmn_to_asic_specific_index(smu,
1624 CMN2ASIC_MAPPING_WORKLOAD,
1625 i);
b455159c
LG		 1626 if (workload_type < 0)
1627 return -EINVAL;
1628
caad2613 1629 result = smu_cmn_update_table(smu,
b455159c 1630 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
f9e3fe46 1631 (void *)(&activity_monitor_external), false);
b455159c 1632 if (result) {
d9811cfc 1633 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
b455159c
LG		 1634 return result;
1635 }
1636
fe14c285 1637 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
94a80b5b 1638 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
b455159c 1639
fe14c285 1640 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
b455159c
LG		 1641 " ",
1642 0,
1643 "GFXCLK",
f9e3fe46
EQ		 1644 activity_monitor->Gfx_FPS,
1645 activity_monitor->Gfx_MinFreqStep,
1646 activity_monitor->Gfx_MinActiveFreqType,
1647 activity_monitor->Gfx_MinActiveFreq,
1648 activity_monitor->Gfx_BoosterFreqType,
1649 activity_monitor->Gfx_BoosterFreq,
1650 activity_monitor->Gfx_PD_Data_limit_c,
1651 activity_monitor->Gfx_PD_Data_error_coeff,
1652 activity_monitor->Gfx_PD_Data_error_rate_coeff);
b455159c 1653
fe14c285 1654 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
b455159c
LG		 1655 " ",
1656 1,
1657 "SOCCLK",
f9e3fe46
EQ		 1658 activity_monitor->Fclk_FPS,
1659 activity_monitor->Fclk_MinFreqStep,
1660 activity_monitor->Fclk_MinActiveFreqType,
1661 activity_monitor->Fclk_MinActiveFreq,
1662 activity_monitor->Fclk_BoosterFreqType,
1663 activity_monitor->Fclk_BoosterFreq,
1664 activity_monitor->Fclk_PD_Data_limit_c,
1665 activity_monitor->Fclk_PD_Data_error_coeff,
1666 activity_monitor->Fclk_PD_Data_error_rate_coeff);
b455159c 1667
fe14c285 1668 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
b455159c
LG		 1669 " ",
1670 2,
1671 "MEMLK",
f9e3fe46
EQ		 1672 activity_monitor->Mem_FPS,
1673 activity_monitor->Mem_MinFreqStep,
1674 activity_monitor->Mem_MinActiveFreqType,
1675 activity_monitor->Mem_MinActiveFreq,
1676 activity_monitor->Mem_BoosterFreqType,
1677 activity_monitor->Mem_BoosterFreq,
1678 activity_monitor->Mem_PD_Data_limit_c,
1679 activity_monitor->Mem_PD_Data_error_coeff,
1680 activity_monitor->Mem_PD_Data_error_rate_coeff);
b455159c
LG		 1681 }
1682
1683 return size;
1684}
1685
1686static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1687{
f9e3fe46
EQ		 1688
1689 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1690 DpmActivityMonitorCoeffInt_t *activity_monitor =
1691 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
b455159c
LG		 1692 int workload_type, ret = 0;
1693
1694 smu->power_profile_mode = input[size];
1695
1696 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
d9811cfc 1697 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
b455159c
LG		 1698 return -EINVAL;
1699 }
1700
1701 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
b455159c 1702
caad2613 1703 ret = smu_cmn_update_table(smu,
b455159c 1704 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
f9e3fe46 1705 (void *)(&activity_monitor_external), false);
b455159c 1706 if (ret) {
d9811cfc 1707 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
b455159c
LG		 1708 return ret;
1709 }
1710
1711 switch (input[0]) {
1712 case 0: /* Gfxclk */
f9e3fe46
EQ		 1713 activity_monitor->Gfx_FPS = input[1];
1714 activity_monitor->Gfx_MinFreqStep = input[2];
1715 activity_monitor->Gfx_MinActiveFreqType = input[3];
1716 activity_monitor->Gfx_MinActiveFreq = input[4];
1717 activity_monitor->Gfx_BoosterFreqType = input[5];
1718 activity_monitor->Gfx_BoosterFreq = input[6];
1719 activity_monitor->Gfx_PD_Data_limit_c = input[7];
1720 activity_monitor->Gfx_PD_Data_error_coeff = input[8];
1721 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1722 break;
1723 case 1: /* Socclk */
f9e3fe46
EQ		 1724 activity_monitor->Fclk_FPS = input[1];
1725 activity_monitor->Fclk_MinFreqStep = input[2];
1726 activity_monitor->Fclk_MinActiveFreqType = input[3];
1727 activity_monitor->Fclk_MinActiveFreq = input[4];
1728 activity_monitor->Fclk_BoosterFreqType = input[5];
1729 activity_monitor->Fclk_BoosterFreq = input[6];
1730 activity_monitor->Fclk_PD_Data_limit_c = input[7];
1731 activity_monitor->Fclk_PD_Data_error_coeff = input[8];
1732 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1733 break;
1734 case 2: /* Memlk */
f9e3fe46
EQ		 1735 activity_monitor->Mem_FPS = input[1];
1736 activity_monitor->Mem_MinFreqStep = input[2];
1737 activity_monitor->Mem_MinActiveFreqType = input[3];
1738 activity_monitor->Mem_MinActiveFreq = input[4];
1739 activity_monitor->Mem_BoosterFreqType = input[5];
1740 activity_monitor->Mem_BoosterFreq = input[6];
1741 activity_monitor->Mem_PD_Data_limit_c = input[7];
1742 activity_monitor->Mem_PD_Data_error_coeff = input[8];
1743 activity_monitor->Mem_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1744 break;
1745 }
1746
caad2613 1747 ret = smu_cmn_update_table(smu,
b455159c 1748 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
f9e3fe46 1749 (void *)(&activity_monitor_external), true);
b455159c 1750 if (ret) {
d9811cfc 1751 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
b455159c
LG		 1752 return ret;
1753 }
1754 }
1755
1756 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
6c339f37
EQ		 1757 workload_type = smu_cmn_to_asic_specific_index(smu,
1758 CMN2ASIC_MAPPING_WORKLOAD,
1759 smu->power_profile_mode);
b455159c
LG		 1760 if (workload_type < 0)
1761 return -EINVAL;
66c86828 1762 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
b455159c
LG		 1763 1 << workload_type, NULL);
1764
1765 return ret;
1766}
1767
b455159c
LG		 1768static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1769{
1770 struct smu_clocks min_clocks = {0};
1771 struct pp_display_clock_request clock_req;
1772 int ret = 0;
1773
1774 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1775 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1776 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1777
7ade3ca9 1778 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
b455159c
LG		 1779 clock_req.clock_type = amd_pp_dcef_clock;
1780 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1781
1782 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1783 if (!ret) {
7ade3ca9 1784 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
66c86828 1785 ret = smu_cmn_send_smc_msg_with_param(smu,
40d3b8db
LG		 1786 SMU_MSG_SetMinDeepSleepDcefclk,
1787 min_clocks.dcef_clock_in_sr/100,
1788 NULL);
1789 if (ret) {
d9811cfc 1790 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
40d3b8db
LG		 1791 return ret;
1792 }
b455159c
LG		 1793 }
1794 } else {
d9811cfc 1795 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
b455159c
LG		 1796 }
1797 }
1798
b4bb3aaf 1799 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
661b94f5 1800 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
b455159c 1801 if (ret) {
d9811cfc 1802 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
b455159c
LG		 1803 return ret;
1804 }
1805 }
1806
1807 return 0;
1808}
1809
1810static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
7b9c7e30 1811 struct pp_smu_wm_range_sets *clock_ranges)
b455159c 1812{
e7a95eea 1813 Watermarks_t *table = smu->smu_table.watermarks_table;
40d3b8db 1814 int ret = 0;
e7a95eea 1815 int i;
b455159c 1816
e7a95eea 1817 if (clock_ranges) {
7b9c7e30
EQ		 1818 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1819 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
e7a95eea
EQ		 1820 return -EINVAL;
1821
7b9c7e30
EQ		 1822 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1823 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1824 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1825 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1826 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1827 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1828 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1829 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1830 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1831
1832 table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1833 clock_ranges->reader_wm_sets[i].wm_inst;
e7a95eea 1834 }
b455159c 1835
7b9c7e30
EQ		 1836 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1837 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1838 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1839 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1840 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1841 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1842 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1843 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1844 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1845
1846 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1847 clock_ranges->writer_wm_sets[i].wm_inst;
e7a95eea
EQ		 1848 }
1849
1850 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1851 }
1852
1853 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1854 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
caad2613 1855 ret = smu_cmn_write_watermarks_table(smu);
40d3b8db 1856 if (ret) {
d9811cfc 1857 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
40d3b8db
LG		 1858 return ret;
1859 }
1860 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1861 }
1862
b455159c
LG		 1863 return 0;
1864}
1865
b455159c
LG		 1866static int sienna_cichlid_read_sensor(struct smu_context *smu,
1867 enum amd_pp_sensors sensor,
1868 void *data, uint32_t *size)
1869{
1870 int ret = 0;
7077b19a 1871 uint16_t *temp;
d6810d7d 1872 struct amdgpu_device *adev = smu->adev;
b455159c
LG		 1873
1874 if(!data || !size)
1875 return -EINVAL;
1876
b455159c
LG		 1877 switch (sensor) {
1878 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
7077b19a
CG		 1879 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
1880 *(uint16_t *)data = *temp;
b455159c
LG		 1881 *size = 4;
1882 break;
1883 case AMDGPU_PP_SENSOR_MEM_LOAD:
60e317a2
AD		 1884 ret = sienna_cichlid_get_smu_metrics_data(smu,
1885 METRICS_AVERAGE_MEMACTIVITY,
1886 (uint32_t *)data);
1887 *size = 4;
1888 break;
b455159c 1889 case AMDGPU_PP_SENSOR_GPU_LOAD:
60e317a2
AD		 1890 ret = sienna_cichlid_get_smu_metrics_data(smu,
1891 METRICS_AVERAGE_GFXACTIVITY,
1892 (uint32_t *)data);
b455159c
LG		 1893 *size = 4;
1894 break;
1895 case AMDGPU_PP_SENSOR_GPU_POWER:
60e317a2
AD		 1896 ret = sienna_cichlid_get_smu_metrics_data(smu,
1897 METRICS_AVERAGE_SOCKETPOWER,
1898 (uint32_t *)data);
b455159c
LG		 1899 *size = 4;
1900 break;
1901 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
60e317a2
AD		 1902 ret = sienna_cichlid_get_smu_metrics_data(smu,
1903 METRICS_TEMPERATURE_HOTSPOT,
1904 (uint32_t *)data);
1905 *size = 4;
1906 break;
b455159c 1907 case AMDGPU_PP_SENSOR_EDGE_TEMP:
60e317a2
AD		 1908 ret = sienna_cichlid_get_smu_metrics_data(smu,
1909 METRICS_TEMPERATURE_EDGE,
1910 (uint32_t *)data);
1911 *size = 4;
1912 break;
b455159c 1913 case AMDGPU_PP_SENSOR_MEM_TEMP:
60e317a2
AD		 1914 ret = sienna_cichlid_get_smu_metrics_data(smu,
1915 METRICS_TEMPERATURE_MEM,
1916 (uint32_t *)data);
b455159c
LG		 1917 *size = 4;
1918 break;
e0f9e936
EQ		 1919 case AMDGPU_PP_SENSOR_GFX_MCLK:
1920 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1921 *(uint32_t *)data *= 100;
1922 *size = 4;
1923 break;
1924 case AMDGPU_PP_SENSOR_GFX_SCLK:
1925 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1926 *(uint32_t *)data *= 100;
1927 *size = 4;
1928 break;
b2febc99
EQ		 1929 case AMDGPU_PP_SENSOR_VDDGFX:
1930 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1931 *size = 4;
1932 break;
d6810d7d
S		 1933 case AMDGPU_PP_SENSOR_SS_APU_SHARE:
1934 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) {
1935 ret = sienna_cichlid_get_smu_metrics_data(smu,
1936 METRICS_SS_APU_SHARE, (uint32_t *)data);
1937 *size = 4;
1938 } else {
1939 ret = -EOPNOTSUPP;
1940 }
1941 break;
1942 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
1943 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) {
1944 ret = sienna_cichlid_get_smu_metrics_data(smu,
1945 METRICS_SS_DGPU_SHARE, (uint32_t *)data);
1946 *size = 4;
1947 } else {
1948 ret = -EOPNOTSUPP;
1949 }
1950 break;
b455159c 1951 default:
b2febc99
EQ		 1952 ret = -EOPNOTSUPP;
1953 break;
b455159c 1954 }
b455159c
LG		 1955
1956 return ret;
1957}
1958
ebd9c071
KR		 1959static void sienna_cichlid_get_unique_id(struct smu_context *smu)
1960{
1961 struct amdgpu_device *adev = smu->adev;
1962 uint32_t upper32 = 0, lower32 = 0;
1963
1964 /* Only supported as of version 0.58.83.0 and only on Sienna Cichlid */
1965 if (smu->smc_fw_version < 0x3A5300 ||
1966 smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7))
1967 return;
1968
1969 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32))
1970 goto out;
1971 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32))
1972 goto out;
1973
1974out:
1975
1976 adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1977 if (adev->serial[0] == '\0')
1978 sprintf(adev->serial, "%016llx", adev->unique_id);
1979}
1980
b455159c
LG		 1981static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1982{
1983 uint32_t num_discrete_levels = 0;
1984 uint16_t *dpm_levels = NULL;
1985 uint16_t i = 0;
1986 struct smu_table_context *table_context = &smu->smu_table;
7077b19a
CG		 1987 DpmDescriptor_t *table_member1;
1988 uint16_t *table_member2;
b455159c
LG		 1989
1990 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1991 return -EINVAL;
1992
7077b19a
CG		 1993 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
1994 num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
1995 GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
1996 dpm_levels = table_member2;
b455159c
LG		 1997
1998 if (num_discrete_levels == 0 || dpm_levels == NULL)
1999 return -EINVAL;
2000
2001 *num_states = num_discrete_levels;
2002 for (i = 0; i < num_discrete_levels; i++) {
2003 /* convert to khz */
2004 *clocks_in_khz = (*dpm_levels) * 1000;
2005 clocks_in_khz++;
2006 dpm_levels++;
2007 }
2008
2009 return 0;
2010}
2011
2012static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
2013 struct smu_temperature_range *range)
2014{
e02e4d51
EQ		 2015 struct smu_table_context *table_context = &smu->smu_table;
2016 struct smu_11_0_7_powerplay_table *powerplay_table =
2017 table_context->power_play_table;
7077b19a
CG		 2018 uint16_t *table_member;
2019 uint16_t temp_edge, temp_hotspot, temp_mem;
b455159c 2020
2b1f12a2 2021 if (!range)
b455159c
LG		 2022 return -EINVAL;
2023
0540eced
EQ		 2024 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
2025
7077b19a
CG		 2026 GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
2027 temp_edge = table_member[TEMP_EDGE];
2028 temp_hotspot = table_member[TEMP_HOTSPOT];
2029 temp_mem = table_member[TEMP_MEM];
2030
2031 range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2032 range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
2b1f12a2 2033 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a
CG		 2034 range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2035 range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
2b1f12a2 2036 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a
CG		 2037 range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2038 range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
b455159c 2039 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a 2040
e02e4d51 2041 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
b455159c
LG		 2042
2043 return 0;
2044}
2045
2046static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
2047 bool disable_memory_clock_switch)
2048{
2049 int ret = 0;
2050 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
2051 (struct smu_11_0_max_sustainable_clocks *)
2052 smu->smu_table.max_sustainable_clocks;
2053 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
2054 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
2055
2056 if(smu->disable_uclk_switch == disable_memory_clock_switch)
2057 return 0;
2058
2059 if(disable_memory_clock_switch)
661b94f5 2060 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
b455159c 2061 else
661b94f5 2062 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
b455159c
LG		 2063
2064 if(!ret)
2065 smu->disable_uclk_switch = disable_memory_clock_switch;
2066
2067 return ret;
2068}
2069
08ccfe08
LG		 2070static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
2071 uint32_t pcie_gen_cap,
2072 uint32_t pcie_width_cap)
2073{
0b590970 2074 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
7077b19a 2075
08ccfe08 2076 uint32_t smu_pcie_arg;
7077b19a 2077 uint8_t *table_member1, *table_member2;
0b590970 2078 int ret, i;
08ccfe08 2079
7077b19a
CG		 2080 GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
2081 GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
2082
0b590970
EQ		 2083 /* lclk dpm table setup */
2084 for (i = 0; i < MAX_PCIE_CONF; i++) {
7077b19a
CG		 2085 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = table_member1[i];
2086 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = table_member2[i];
0b590970 2087 }
08ccfe08
LG		 2088
2089 for (i = 0; i < NUM_LINK_LEVELS; i++) {
2090 smu_pcie_arg = (i << 16) |
7077b19a
CG		 2091 ((table_member1[i] <= pcie_gen_cap) ?
2092 (table_member1[i] << 8) :
2093 (pcie_gen_cap << 8)) |
2094 ((table_member2[i] <= pcie_width_cap) ?
2095 table_member2[i] :
2096 pcie_width_cap);
08ccfe08 2097
66c86828 2098 ret = smu_cmn_send_smc_msg_with_param(smu,
7077b19a
CG		 2099 SMU_MSG_OverridePcieParameters,
2100 smu_pcie_arg,
2101 NULL);
08ccfe08
LG		 2102 if (ret)
2103 return ret;
2104
7077b19a 2105 if (table_member1[i] > pcie_gen_cap)
08ccfe08 2106 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
7077b19a 2107 if (table_member2[i] > pcie_width_cap)
08ccfe08
LG		 2108 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
2109 }
2110
2111 return 0;
2112}
2113
38ed7b09 2114static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
258d290c
LG		 2115 enum smu_clk_type clk_type,
2116 uint32_t *min, uint32_t *max)
2117{
3bce90bf 2118 return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
258d290c
LG		 2119}
2120
aa75fa34
EQ		 2121static void sienna_cichlid_dump_od_table(struct smu_context *smu,
2122 OverDriveTable_t *od_table)
2123{
a2b6df4f
EQ		 2124 struct amdgpu_device *adev = smu->adev;
2125 uint32_t smu_version;
2126
aa75fa34
EQ		 2127 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
2128 od_table->GfxclkFmax);
2129 dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
2130 od_table->UclkFmax);
a2b6df4f
EQ		 2131
2132 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1d789535 2133 if (!((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
a2b6df4f
EQ		 2134 (smu_version < 0x003a2900)))
2135 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
aa75fa34
EQ		 2136}
2137
2138static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
2139{
2140 OverDriveTable_t *od_table =
2141 (OverDriveTable_t *)smu->smu_table.overdrive_table;
2142 OverDriveTable_t *boot_od_table =
2143 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
b521be9b
EQ		 2144 OverDriveTable_t *user_od_table =
2145 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
49017304 2146 OverDriveTable_t user_od_table_bak;
aa75fa34
EQ		 2147 int ret = 0;
2148
2149 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
b521be9b 2150 0, (void *)boot_od_table, false);
aa75fa34
EQ		 2151 if (ret) {
2152 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2153 return ret;
2154 }
2155
b521be9b 2156 sienna_cichlid_dump_od_table(smu, boot_od_table);
aa75fa34 2157
b521be9b 2158 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
49017304
BS		 2159
2160 /*
2161 * For S3/S4/Runpm resume, we need to setup those overdrive tables again,
2162 * but we have to preserve user defined values in "user_od_table".
2163 */
2164 if (!smu->adev->in_suspend) {
2165 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2166 smu->user_dpm_profile.user_od = false;
2167 } else if (smu->user_dpm_profile.user_od) {
2168 memcpy(&user_od_table_bak, user_od_table, sizeof(OverDriveTable_t));
2169 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2170 user_od_table->GfxclkFmin = user_od_table_bak.GfxclkFmin;
2171 user_od_table->GfxclkFmax = user_od_table_bak.GfxclkFmax;
2172 user_od_table->UclkFmin = user_od_table_bak.UclkFmin;
2173 user_od_table->UclkFmax = user_od_table_bak.UclkFmax;
2174 user_od_table->VddGfxOffset = user_od_table_bak.VddGfxOffset;
2175 }
aa75fa34
EQ		 2176
2177 return 0;
2178}
2179
37a58f69
EQ		 2180static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
2181 struct smu_11_0_7_overdrive_table *od_table,
2182 enum SMU_11_0_7_ODSETTING_ID setting,
2183 uint32_t value)
2184{
2185 if (value < od_table->min[setting]) {
2186 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
2187 setting, value, od_table->min[setting]);
2188 return -EINVAL;
2189 }
2190 if (value > od_table->max[setting]) {
2191 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
2192 setting, value, od_table->max[setting]);
2193 return -EINVAL;
2194 }
2195
2196 return 0;
2197}
2198
2199static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
2200 enum PP_OD_DPM_TABLE_COMMAND type,
2201 long input[], uint32_t size)
2202{
2203 struct smu_table_context *table_context = &smu->smu_table;
2204 OverDriveTable_t *od_table =
2205 (OverDriveTable_t *)table_context->overdrive_table;
2206 struct smu_11_0_7_overdrive_table *od_settings =
2207 (struct smu_11_0_7_overdrive_table *)smu->od_settings;
a2b6df4f 2208 struct amdgpu_device *adev = smu->adev;
37a58f69
EQ		 2209 enum SMU_11_0_7_ODSETTING_ID freq_setting;
2210 uint16_t *freq_ptr;
2211 int i, ret = 0;
a2b6df4f 2212 uint32_t smu_version;
37a58f69
EQ		 2213
2214 if (!smu->od_enabled) {
2215 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2216 return -EINVAL;
2217 }
2218
2219 if (!smu->od_settings) {
2220 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2221 return -ENOENT;
2222 }
2223
2224 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2225 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2226 return -EINVAL;
2227 }
2228
2229 switch (type) {
2230 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2231 if (!sienna_cichlid_is_od_feature_supported(od_settings,
2232 SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
2233 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2234 return -ENOTSUPP;
2235 }
2236
2237 for (i = 0; i < size; i += 2) {
2238 if (i + 2 > size) {
2239 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2240 return -EINVAL;
2241 }
2242
2243 switch (input[i]) {
2244 case 0:
2245 if (input[i + 1] > od_table->GfxclkFmax) {
2246 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2247 input[i + 1], od_table->GfxclkFmax);
2248 return -EINVAL;
2249 }
2250
2251 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
2252 freq_ptr = &od_table->GfxclkFmin;
2253 break;
2254
2255 case 1:
2256 if (input[i + 1] < od_table->GfxclkFmin) {
2257 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2258 input[i + 1], od_table->GfxclkFmin);
2259 return -EINVAL;
2260 }
2261
2262 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
2263 freq_ptr = &od_table->GfxclkFmax;
2264 break;
2265
2266 default:
2267 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2268 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2269 return -EINVAL;
2270 }
2271
2272 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2273 freq_setting, input[i + 1]);
2274 if (ret)
2275 return ret;
2276
2277 *freq_ptr = (uint16_t)input[i + 1];
2278 }
2279 break;
2280
2281 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2282 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
2283 dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2284 return -ENOTSUPP;
2285 }
2286
2287 for (i = 0; i < size; i += 2) {
2288 if (i + 2 > size) {
2289 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2290 return -EINVAL;
2291 }
2292
2293 switch (input[i]) {
2294 case 0:
2295 if (input[i + 1] > od_table->UclkFmax) {
2296 dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2297 input[i + 1], od_table->UclkFmax);
2298 return -EINVAL;
2299 }
2300
2301 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
2302 freq_ptr = &od_table->UclkFmin;
2303 break;
2304
2305 case 1:
2306 if (input[i + 1] < od_table->UclkFmin) {
2307 dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2308 input[i + 1], od_table->UclkFmin);
2309 return -EINVAL;
2310 }
2311
2312 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
2313 freq_ptr = &od_table->UclkFmax;
2314 break;
2315
2316 default:
2317 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2318 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2319 return -EINVAL;
2320 }
2321
2322 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2323 freq_setting, input[i + 1]);
2324 if (ret)
2325 return ret;
2326
2327 *freq_ptr = (uint16_t)input[i + 1];
2328 }
2329 break;
2330
2331 case PP_OD_RESTORE_DEFAULT_TABLE:
2332 memcpy(table_context->overdrive_table,
2333 table_context->boot_overdrive_table,
2334 sizeof(OverDriveTable_t));
2335 fallthrough;
2336
2337 case PP_OD_COMMIT_DPM_TABLE:
b521be9b
EQ		 2338 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2339 sienna_cichlid_dump_od_table(smu, od_table);
2340 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2341 if (ret) {
2342 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2343 return ret;
2344 }
2345 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2346 smu->user_dpm_profile.user_od = true;
37a58f69 2347
b521be9b
EQ		 2348 if (!memcmp(table_context->user_overdrive_table,
2349 table_context->boot_overdrive_table,
2350 sizeof(OverDriveTable_t)))
2351 smu->user_dpm_profile.user_od = false;
37a58f69
EQ		 2352 }
2353 break;
2354
a2b6df4f
EQ		 2355 case PP_OD_EDIT_VDDGFX_OFFSET:
2356 if (size != 1) {
2357 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2358 return -EINVAL;
2359 }
2360
2361 /*
2362 * OD GFX Voltage Offset functionality is supported only by 58.41.0
2363 * and onwards SMU firmwares.
2364 */
2365 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1d789535 2366 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
a2b6df4f
EQ		 2367 (smu_version < 0x003a2900)) {
2368 dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2369 "only by 58.41.0 and onwards SMU firmwares!\n");
2370 return -EOPNOTSUPP;
2371 }
2372
2373 od_table->VddGfxOffset = (int16_t)input[0];
2374
2375 sienna_cichlid_dump_od_table(smu, od_table);
2376 break;
2377
37a58f69
EQ		 2378 default:
2379 return -ENOSYS;
2380 }
2381
2382 return ret;
2383}
2384
49017304
BS		 2385static int sienna_cichlid_restore_user_od_settings(struct smu_context *smu)
2386{
2387 struct smu_table_context *table_context = &smu->smu_table;
2388 OverDriveTable_t *od_table = table_context->overdrive_table;
2389 OverDriveTable_t *user_od_table = table_context->user_overdrive_table;
2390 int res;
2391
2392 res = smu_v11_0_restore_user_od_settings(smu);
2393 if (res == 0)
2394 memcpy(od_table, user_od_table, sizeof(OverDriveTable_t));
2395
2396 return res;
2397}
2398
66b8a9c0
JC		 2399static int sienna_cichlid_run_btc(struct smu_context *smu)
2400{
dc78fea1
LT		 2401 int res;
2402
2403 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2404 if (res)
2405 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2406
2407 return res;
66b8a9c0
JC		 2408}
2409
13d75ead
EQ		 2410static int sienna_cichlid_baco_enter(struct smu_context *smu)
2411{
2412 struct amdgpu_device *adev = smu->adev;
2413
8b514e89 2414 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
13d75ead
EQ		 2415 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2416 else
2417 return smu_v11_0_baco_enter(smu);
2418}
2419
2420static int sienna_cichlid_baco_exit(struct smu_context *smu)
2421{
2422 struct amdgpu_device *adev = smu->adev;
2423
8b514e89 2424 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
13d75ead
EQ		 2425 /* Wait for PMFW handling for the Dstate change */
2426 msleep(10);
2427 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2428 } else {
2429 return smu_v11_0_baco_exit(smu);
2430 }
2431}
2432
ea8139d8
WS		 2433static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2434{
2435 struct amdgpu_device *adev = smu->adev;
2436 uint32_t val;
2437 u32 smu_version;
2438
2439 /**
2440 * SRIOV env will not support SMU mode1 reset
2441 * PM FW support mode1 reset from 58.26
2442 */
a7bae061 2443 smu_cmn_get_smc_version(smu, NULL, &smu_version);
ea8139d8
WS		 2444 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
2445 return false;
2446
2447 /**
2448 * mode1 reset relies on PSP, so we should check if
2449 * PSP is alive.
2450 */
2451 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2452 return val != 0x0;
2453}
2454
7077b19a
CG		 2455static void beige_goby_dump_pptable(struct smu_context *smu)
2456{
2457 struct smu_table_context *table_context = &smu->smu_table;
2458 PPTable_beige_goby_t *pptable = table_context->driver_pptable;
2459 int i;
2460
2461 dev_info(smu->adev->dev, "Dumped PPTable:\n");
2462
2463 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2464 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2465 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2466
2467 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2468 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2469 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2470 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2471 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2472 }
2473
2474 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2475 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2476 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2477 }
2478
2479 for (i = 0; i < TEMP_COUNT; i++) {
2480 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2481 }
2482
2483 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2484 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2485 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2486 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2487 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2488
2489 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2490 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2491 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2492 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2493 }
2494 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2495
2496 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2497
2498 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2499 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2500 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2501 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2502
2503 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2504
2505 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2506
2507 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2508 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2509 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2510 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2511
2512 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2513 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2514
2515 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2516 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2517 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2518 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2519 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2520 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2521 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2522 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2523
2524 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2525 " .VoltageMode = 0x%02x\n"
2526 " .SnapToDiscrete = 0x%02x\n"
2527 " .NumDiscreteLevels = 0x%02x\n"
2528 " .padding = 0x%02x\n"
2529 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2530 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2531 " .SsFmin = 0x%04x\n"
2532 " .Padding_16 = 0x%04x\n",
2533 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2534 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2535 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2536 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2537 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2538 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2539 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2540 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2541 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2542 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2543 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2544
2545 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2546 " .VoltageMode = 0x%02x\n"
2547 " .SnapToDiscrete = 0x%02x\n"
2548 " .NumDiscreteLevels = 0x%02x\n"
2549 " .padding = 0x%02x\n"
2550 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2551 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2552 " .SsFmin = 0x%04x\n"
2553 " .Padding_16 = 0x%04x\n",
2554 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2555 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2556 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2557 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2558 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2559 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2560 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2561 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2562 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2563 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2564 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2565
2566 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2567 " .VoltageMode = 0x%02x\n"
2568 " .SnapToDiscrete = 0x%02x\n"
2569 " .NumDiscreteLevels = 0x%02x\n"
2570 " .padding = 0x%02x\n"
2571 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2572 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2573 " .SsFmin = 0x%04x\n"
2574 " .Padding_16 = 0x%04x\n",
2575 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2576 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2577 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2578 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2579 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2580 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2581 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2582 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2583 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2584 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2585 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2586
2587 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2588 " .VoltageMode = 0x%02x\n"
2589 " .SnapToDiscrete = 0x%02x\n"
2590 " .NumDiscreteLevels = 0x%02x\n"
2591 " .padding = 0x%02x\n"
2592 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2593 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2594 " .SsFmin = 0x%04x\n"
2595 " .Padding_16 = 0x%04x\n",
2596 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2597 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2598 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2599 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2600 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2601 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2602 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2603 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2604 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2605 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2606 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2607
2608 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2609 " .VoltageMode = 0x%02x\n"
2610 " .SnapToDiscrete = 0x%02x\n"
2611 " .NumDiscreteLevels = 0x%02x\n"
2612 " .padding = 0x%02x\n"
2613 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2614 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2615 " .SsFmin = 0x%04x\n"
2616 " .Padding_16 = 0x%04x\n",
2617 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2618 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2619 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2620 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2621 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2622 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2623 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2624 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2625 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2626 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2627 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2628
2629 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2630 " .VoltageMode = 0x%02x\n"
2631 " .SnapToDiscrete = 0x%02x\n"
2632 " .NumDiscreteLevels = 0x%02x\n"
2633 " .padding = 0x%02x\n"
2634 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2635 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2636 " .SsFmin = 0x%04x\n"
2637 " .Padding_16 = 0x%04x\n",
2638 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2639 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2640 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2641 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2642 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2643 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2644 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2645 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2646 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2647 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2648 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2649
2650 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2651 " .VoltageMode = 0x%02x\n"
2652 " .SnapToDiscrete = 0x%02x\n"
2653 " .NumDiscreteLevels = 0x%02x\n"
2654 " .padding = 0x%02x\n"
2655 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2656 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2657 " .SsFmin = 0x%04x\n"
2658 " .Padding_16 = 0x%04x\n",
2659 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2660 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2661 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2662 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2663 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2664 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2665 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2666 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2667 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2668 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2669 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2670
2671 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2672 " .VoltageMode = 0x%02x\n"
2673 " .SnapToDiscrete = 0x%02x\n"
2674 " .NumDiscreteLevels = 0x%02x\n"
2675 " .padding = 0x%02x\n"
2676 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2677 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2678 " .SsFmin = 0x%04x\n"
2679 " .Padding_16 = 0x%04x\n",
2680 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2681 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2682 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2683 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2684 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2685 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2686 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2687 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2688 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2689 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2690 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2691
2692 dev_info(smu->adev->dev, "FreqTableGfx\n");
2693 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2694 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2695
2696 dev_info(smu->adev->dev, "FreqTableVclk\n");
2697 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2698 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2699
2700 dev_info(smu->adev->dev, "FreqTableDclk\n");
2701 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2702 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2703
2704 dev_info(smu->adev->dev, "FreqTableSocclk\n");
2705 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2706 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2707
2708 dev_info(smu->adev->dev, "FreqTableUclk\n");
2709 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2710 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2711
2712 dev_info(smu->adev->dev, "FreqTableFclk\n");
2713 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2714 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2715
2716 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2717 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2718 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2719 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2720 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2721 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2722 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2723 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2724 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2725
2726 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2727 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2728 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2729
2730 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2731 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2732
2733 dev_info(smu->adev->dev, "Mp0clkFreq\n");
2734 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2735 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2736
2737 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2738 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2739 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2740
2741 dev_info(smu->adev->dev, "MemVddciVoltage\n");
2742 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2743 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2744
2745 dev_info(smu->adev->dev, "MemMvddVoltage\n");
2746 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2747 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2748
2749 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2750 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2751 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2752 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2753 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2754
2755 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2756
2757 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2758 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2759 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2760 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2761 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2762 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2763 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2764 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2765 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2766 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2767 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2768
2769 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2770 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2771 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2772 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2773 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2774 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2775
2776 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2777 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2778 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2779 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2780 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2781
2782 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2783 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2784 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2785
2786 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2787 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2788 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2789 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2790
2791 dev_info(smu->adev->dev, "UclkDpmPstates\n");
2792 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2793 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2794
2795 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2796 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2797 pptable->UclkDpmSrcFreqRange.Fmin);
2798 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2799 pptable->UclkDpmSrcFreqRange.Fmax);
2800 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2801 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2802 pptable->UclkDpmTargFreqRange.Fmin);
2803 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2804 pptable->UclkDpmTargFreqRange.Fmax);
2805 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2806 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2807
2808 dev_info(smu->adev->dev, "PcieGenSpeed\n");
2809 for (i = 0; i < NUM_LINK_LEVELS; i++)
2810 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2811
2812 dev_info(smu->adev->dev, "PcieLaneCount\n");
2813 for (i = 0; i < NUM_LINK_LEVELS; i++)
2814 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2815
2816 dev_info(smu->adev->dev, "LclkFreq\n");
2817 for (i = 0; i < NUM_LINK_LEVELS; i++)
2818 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2819
2820 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2821 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2822
2823 dev_info(smu->adev->dev, "FanGain\n");
2824 for (i = 0; i < TEMP_COUNT; i++)
2825 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2826
2827 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2828 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2829 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2830 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2831 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2832 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2833 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2834 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2835 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2836 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2837 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2838 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2839
2840 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2841 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2842 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2843 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2844
2845 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2846 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2847 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2848 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2849
2850 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2851 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2852 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2853 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2854 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2855 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2856 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2857 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2858 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2859 pptable->dBtcGbGfxPll.a,
2860 pptable->dBtcGbGfxPll.b,
2861 pptable->dBtcGbGfxPll.c);
2862 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2863 pptable->dBtcGbGfxDfll.a,
2864 pptable->dBtcGbGfxDfll.b,
2865 pptable->dBtcGbGfxDfll.c);
2866 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2867 pptable->dBtcGbSoc.a,
2868 pptable->dBtcGbSoc.b,
2869 pptable->dBtcGbSoc.c);
2870 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2871 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2872 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2873 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2874 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2875 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2876
2877 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2878 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2879 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
2880 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2881 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
2882 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2883 }
2884
2885 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2886 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2887 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2888 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2889 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2890 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2891 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2892 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2893
2894 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2895 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2896
2897 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2898 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2899 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2900 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2901
2902 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2903 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2904 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2905 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2906
2907 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2908 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2909
2910 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2911 for (i = 0; i < NUM_XGMI_LEVELS; i++)
2912 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2913 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2914 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2915
2916 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2917 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2918 pptable->ReservedEquation0.a,
2919 pptable->ReservedEquation0.b,
2920 pptable->ReservedEquation0.c);
2921 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2922 pptable->ReservedEquation1.a,
2923 pptable->ReservedEquation1.b,
2924 pptable->ReservedEquation1.c);
2925 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2926 pptable->ReservedEquation2.a,
2927 pptable->ReservedEquation2.b,
2928 pptable->ReservedEquation2.c);
2929 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2930 pptable->ReservedEquation3.a,
2931 pptable->ReservedEquation3.b,
2932 pptable->ReservedEquation3.c);
2933
2934 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2935 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2936 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2937 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2938 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2939 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2940 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2941 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2942
2943 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2944 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2945 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2946 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2947 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2948 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2949
2950 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2951 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2952 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
2953 pptable->I2cControllers[i].Enabled);
2954 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
2955 pptable->I2cControllers[i].Speed);
2956 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
2957 pptable->I2cControllers[i].SlaveAddress);
2958 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
2959 pptable->I2cControllers[i].ControllerPort);
2960 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
2961 pptable->I2cControllers[i].ControllerName);
2962 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
2963 pptable->I2cControllers[i].ThermalThrotter);
2964 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
2965 pptable->I2cControllers[i].I2cProtocol);
2966 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
2967 pptable->I2cControllers[i].PaddingConfig);
2968 }
2969
2970 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2971 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2972 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2973 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2974
2975 dev_info(smu->adev->dev, "Board Parameters:\n");
2976 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2977 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2978 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2979 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2980 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2981 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2982 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2983 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2984
2985 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2986 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2987 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2988
2989 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2990 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2991 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2992
2993 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2994 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2995 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2996
2997 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2998 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2999 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3000
3001 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3002
3003 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3004 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3005 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3006 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3007 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3008 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3009 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3010 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3011 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3012 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3013 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3014 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3015 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3016 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3017 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3018 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3019
3020 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3021 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3022 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3023
3024 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3025 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3026 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3027
3028 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3029 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3030
3031 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3032 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3033 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3034
3035 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3036 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3037 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3038 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3039 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3040
3041 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3042 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3043
3044 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3045 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3046 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3047 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3048 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3049 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3050 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3051 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3052 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3053 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3054 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3055 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3056
3057 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3058 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3059 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3060 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3061
3062 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3063 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3064 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3065 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3066 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3067 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3068 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3069 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3070 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3071 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3072 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3073
3074 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3075 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3076 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3077 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3078 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3079 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3080 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3081 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3082}
3083
b455159c
LG		 3084static void sienna_cichlid_dump_pptable(struct smu_context *smu)
3085{
3086 struct smu_table_context *table_context = &smu->smu_table;
3087 PPTable_t *pptable = table_context->driver_pptable;
3088 int i;
3089
1d789535 3090 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) {
7077b19a
CG		 3091 beige_goby_dump_pptable(smu);
3092 return;
3093 }
3094
d9811cfc 3095 dev_info(smu->adev->dev, "Dumped PPTable:\n");
b455159c 3096
d9811cfc
EQ		 3097 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
3098 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
3099 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
b455159c
LG		 3100
3101 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
d9811cfc
EQ		 3102 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
3103 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
3104 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
3105 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
b455159c
LG		 3106 }
3107
3108 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
d9811cfc
EQ		 3109 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
3110 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
b455159c
LG		 3111 }
3112
3113 for (i = 0; i < TEMP_COUNT; i++) {
d9811cfc 3114 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
b455159c
LG		 3115 }
3116
d9811cfc
EQ		 3117 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
3118 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
3119 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
3120 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
3121 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
b455159c 3122
d9811cfc 3123 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
b455159c 3124 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
d9811cfc
EQ		 3125 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
3126 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
b455159c 3127 }
d9811cfc
EQ		 3128 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
3129
3130 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
3131
3132 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
3133 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
3134 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
3135 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
3136
3137 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
3138 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
3139
3140 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
3141 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
3142 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
3143 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
3144
3145 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
3146 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
3147 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
3148 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
3149
3150 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
3151 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
3152
3153 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
3154 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
3155 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
3156 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
3157 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
3158 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
3159 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
3160 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
3161
3162 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
b455159c
LG		 3163 " .VoltageMode = 0x%02x\n"
3164 " .SnapToDiscrete = 0x%02x\n"
3165 " .NumDiscreteLevels = 0x%02x\n"
3166 " .padding = 0x%02x\n"
3167 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3168 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3169 " .SsFmin = 0x%04x\n"
3170 " .Padding_16 = 0x%04x\n",
3171 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
3172 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
3173 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
3174 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
3175 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
3176 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
3177 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
3178 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
3179 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
3180 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
3181 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
3182
d9811cfc 3183 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
b455159c
LG		 3184 " .VoltageMode = 0x%02x\n"
3185 " .SnapToDiscrete = 0x%02x\n"
3186 " .NumDiscreteLevels = 0x%02x\n"
3187 " .padding = 0x%02x\n"
3188 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3189 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3190 " .SsFmin = 0x%04x\n"
3191 " .Padding_16 = 0x%04x\n",
3192 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
3193 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
3194 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
3195 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
3196 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
3197 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
3198 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
3199 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
3200 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
3201 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
3202 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
3203
d9811cfc 3204 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
b455159c
LG		 3205 " .VoltageMode = 0x%02x\n"
3206 " .SnapToDiscrete = 0x%02x\n"
3207 " .NumDiscreteLevels = 0x%02x\n"
3208 " .padding = 0x%02x\n"
3209 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3210 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3211 " .SsFmin = 0x%04x\n"
3212 " .Padding_16 = 0x%04x\n",
3213 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
3214 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
3215 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
3216 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
3217 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
3218 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
3219 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
3220 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
3221 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
3222 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
3223 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
3224
d9811cfc 3225 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
b455159c
LG		 3226 " .VoltageMode = 0x%02x\n"
3227 " .SnapToDiscrete = 0x%02x\n"
3228 " .NumDiscreteLevels = 0x%02x\n"
3229 " .padding = 0x%02x\n"
3230 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3231 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3232 " .SsFmin = 0x%04x\n"
3233 " .Padding_16 = 0x%04x\n",
3234 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
3235 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
3236 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
3237 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
3238 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
3239 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
3240 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
3241 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
3242 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
3243 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
3244 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
3245
d9811cfc 3246 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
b455159c
LG		 3247 " .VoltageMode = 0x%02x\n"
3248 " .SnapToDiscrete = 0x%02x\n"
3249 " .NumDiscreteLevels = 0x%02x\n"
3250 " .padding = 0x%02x\n"
3251 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3252 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3253 " .SsFmin = 0x%04x\n"
3254 " .Padding_16 = 0x%04x\n",
3255 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
3256 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
3257 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
3258 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
3259 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
3260 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
3261 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
3262 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
3263 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
3264 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
3265 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
3266
d9811cfc 3267 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
b455159c
LG		 3268 " .VoltageMode = 0x%02x\n"
3269 " .SnapToDiscrete = 0x%02x\n"
3270 " .NumDiscreteLevels = 0x%02x\n"
3271 " .padding = 0x%02x\n"
3272 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3273 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3274 " .SsFmin = 0x%04x\n"
3275 " .Padding_16 = 0x%04x\n",
3276 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
3277 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
3278 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
3279 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
3280 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
3281 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
3282 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
3283 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
3284 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
3285 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
3286 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
3287
d9811cfc 3288 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
b455159c
LG		 3289 " .VoltageMode = 0x%02x\n"
3290 " .SnapToDiscrete = 0x%02x\n"
3291 " .NumDiscreteLevels = 0x%02x\n"
3292 " .padding = 0x%02x\n"
3293 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3294 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3295 " .SsFmin = 0x%04x\n"
3296 " .Padding_16 = 0x%04x\n",
3297 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
3298 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
3299 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
3300 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
3301 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
3302 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
3303 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
3304 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
3305 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
3306 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
3307 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
3308
d9811cfc 3309 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
b455159c
LG		 3310 " .VoltageMode = 0x%02x\n"
3311 " .SnapToDiscrete = 0x%02x\n"
3312 " .NumDiscreteLevels = 0x%02x\n"
3313 " .padding = 0x%02x\n"
3314 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3315 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3316 " .SsFmin = 0x%04x\n"
3317 " .Padding_16 = 0x%04x\n",
3318 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
3319 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
3320 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
3321 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
3322 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
3323 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
3324 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
3325 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
3326 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
3327 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
3328 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
3329
d9811cfc 3330 dev_info(smu->adev->dev, "FreqTableGfx\n");
b455159c 3331 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
d9811cfc 3332 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
b455159c 3333
d9811cfc 3334 dev_info(smu->adev->dev, "FreqTableVclk\n");
b455159c 3335 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
d9811cfc 3336 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
b455159c 3337
d9811cfc 3338 dev_info(smu->adev->dev, "FreqTableDclk\n");
b455159c 3339 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
d9811cfc 3340 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
b455159c 3341
d9811cfc 3342 dev_info(smu->adev->dev, "FreqTableSocclk\n");
b455159c 3343 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
d9811cfc 3344 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
b455159c 3345
d9811cfc 3346 dev_info(smu->adev->dev, "FreqTableUclk\n");
b455159c 3347 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3348 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
b455159c 3349
d9811cfc 3350 dev_info(smu->adev->dev, "FreqTableFclk\n");
b455159c 3351 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
d9811cfc
EQ		 3352 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
3353
d9811cfc
EQ		 3354 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
3355 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
3356 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
3357 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
3358 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
3359 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
3360 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
3361 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
3362 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
3363
3364 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
b455159c 3365 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3366 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
b455159c 3367
d9811cfc
EQ		 3368 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
3369 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
b455159c 3370
d9811cfc 3371 dev_info(smu->adev->dev, "Mp0clkFreq\n");
b455159c 3372 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc 3373 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
b455159c 3374
d9811cfc 3375 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
b455159c 3376 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc 3377 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
b455159c 3378
d9811cfc 3379 dev_info(smu->adev->dev, "MemVddciVoltage\n");
b455159c 3380 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3381 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
b455159c 3382
d9811cfc 3383 dev_info(smu->adev->dev, "MemMvddVoltage\n");
b455159c 3384 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc
EQ		 3385 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
3386
3387 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
3388 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
3389 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
3390 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
3391 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
3392
3393 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
3394
3395 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
3396 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
3397 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
3398 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
3399 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
3400 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
3401 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
3402 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
3403 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
3404 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
3405 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
3406
3407 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
3408 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
3409 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
3410 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
3411 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
3412 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
3413
3414 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
3415 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
3416 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
3417 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
3418 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
3419
3420 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
b455159c 3421 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
d9811cfc 3422 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
b455159c 3423
d9811cfc
EQ		 3424 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
3425 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
3426 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
3427 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
b455159c 3428
d9811cfc 3429 dev_info(smu->adev->dev, "UclkDpmPstates\n");
b455159c 3430 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3431 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
b455159c 3432
d9811cfc
EQ		 3433 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
3434 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
b455159c 3435 pptable->UclkDpmSrcFreqRange.Fmin);
d9811cfc 3436 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
b455159c 3437 pptable->UclkDpmSrcFreqRange.Fmax);
d9811cfc
EQ		 3438 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
3439 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
b455159c 3440 pptable->UclkDpmTargFreqRange.Fmin);
d9811cfc 3441 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
b455159c 3442 pptable->UclkDpmTargFreqRange.Fmax);
d9811cfc
EQ		 3443 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
3444 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
b455159c 3445
d9811cfc 3446 dev_info(smu->adev->dev, "PcieGenSpeed\n");
b455159c 3447 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3448 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
b455159c 3449
d9811cfc 3450 dev_info(smu->adev->dev, "PcieLaneCount\n");
b455159c 3451 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3452 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
b455159c 3453
d9811cfc 3454 dev_info(smu->adev->dev, "LclkFreq\n");
b455159c 3455 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3456 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
b455159c 3457
d9811cfc
EQ		 3458 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
3459 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
b455159c 3460
d9811cfc 3461 dev_info(smu->adev->dev, "FanGain\n");
b455159c 3462 for (i = 0; i < TEMP_COUNT; i++)
d9811cfc
EQ		 3463 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
3464
3465 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
3466 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
3467 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
3468 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
3469 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
3470 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
3471 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
3472 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
3473 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
3474 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
3475 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
3476 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
3477
3478 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
3479 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
3480 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
3481 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
3482
3483 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
3484 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
3485 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
3486 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
3487
3488 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3489 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
3490 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
3491 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
d9811cfc 3492 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3493 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
3494 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
3495 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
d9811cfc 3496 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3497 pptable->dBtcGbGfxPll.a,
3498 pptable->dBtcGbGfxPll.b,
3499 pptable->dBtcGbGfxPll.c);
d9811cfc 3500 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3501 pptable->dBtcGbGfxDfll.a,
3502 pptable->dBtcGbGfxDfll.b,
3503 pptable->dBtcGbGfxDfll.c);
d9811cfc 3504 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3505 pptable->dBtcGbSoc.a,
3506 pptable->dBtcGbSoc.b,
3507 pptable->dBtcGbSoc.c);
d9811cfc 3508 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
b455159c
LG		 3509 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
3510 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
d9811cfc 3511 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
b455159c
LG		 3512 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
3513 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
3514
d9811cfc 3515 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
b455159c 3516 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
d9811cfc 3517 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
b455159c 3518 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
d9811cfc 3519 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
b455159c
LG		 3520 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
3521 }
3522
d9811cfc 3523 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3524 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
3525 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
3526 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
d9811cfc 3527 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3528 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
3529 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
3530 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
3531
d9811cfc
EQ		 3532 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
3533 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
b455159c 3534
d9811cfc
EQ		 3535 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
3536 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
3537 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
3538 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
b455159c 3539
d9811cfc
EQ		 3540 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
3541 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
3542 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
3543 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
b455159c 3544
d9811cfc
EQ		 3545 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
3546 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
b455159c 3547
d9811cfc 3548 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
b455159c 3549 for (i = 0; i < NUM_XGMI_LEVELS; i++)
d9811cfc
EQ		 3550 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
3551 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
3552 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
b455159c 3553
d9811cfc
EQ		 3554 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
3555 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3556 pptable->ReservedEquation0.a,
3557 pptable->ReservedEquation0.b,
3558 pptable->ReservedEquation0.c);
d9811cfc 3559 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3560 pptable->ReservedEquation1.a,
3561 pptable->ReservedEquation1.b,
3562 pptable->ReservedEquation1.c);
d9811cfc 3563 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3564 pptable->ReservedEquation2.a,
3565 pptable->ReservedEquation2.b,
3566 pptable->ReservedEquation2.c);
d9811cfc 3567 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3568 pptable->ReservedEquation3.a,
3569 pptable->ReservedEquation3.b,
3570 pptable->ReservedEquation3.c);
3571
d9811cfc
EQ		 3572 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3573 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3574 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3575 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3576 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3577 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3578 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3579 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
d9811cfc
EQ		 3580
3581 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3582 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3583 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3584 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3585 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3586 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
b455159c
LG		 3587
3588 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
d9811cfc
EQ		 3589 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3590 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
b455159c 3591 pptable->I2cControllers[i].Enabled);
d9811cfc 3592 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
b455159c 3593 pptable->I2cControllers[i].Speed);
d9811cfc 3594 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
b455159c 3595 pptable->I2cControllers[i].SlaveAddress);
d9811cfc 3596 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
b455159c 3597 pptable->I2cControllers[i].ControllerPort);
d9811cfc 3598 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
b455159c 3599 pptable->I2cControllers[i].ControllerName);
d9811cfc 3600 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
b455159c 3601 pptable->I2cControllers[i].ThermalThrotter);
d9811cfc 3602 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
b455159c 3603 pptable->I2cControllers[i].I2cProtocol);
d9811cfc 3604 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
b455159c
LG		 3605 pptable->I2cControllers[i].PaddingConfig);
3606 }
3607
d9811cfc
EQ		 3608 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3609 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3610 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3611 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3612
3613 dev_info(smu->adev->dev, "Board Parameters:\n");
3614 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3615 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3616 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3617 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3618 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3619 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3620 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3621 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3622
3623 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3624 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3625 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3626
3627 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3628 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3629 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3630
3631 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3632 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3633 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3634
3635 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3636 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3637 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3638
3639 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3640
3641 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3642 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3643 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3644 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3645 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3646 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3647 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3648 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3649 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3650 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3651 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3652 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3653 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3654 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3655 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3656 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3657
3658 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3659 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3660 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3661
3662 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3663 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3664 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3665
f0f3d68e 3666 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
d9811cfc
EQ		 3667 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3668
3669 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3670 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3671 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3672
3673 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3674 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3675 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3676 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3677 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3678
3679 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3680 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3681
3682 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
b455159c 3683 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3684 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3685 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
b455159c 3686 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3687 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3688 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
b455159c 3689 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3690 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3691 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
b455159c 3692 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3693 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3694
3695 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3696 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3697 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3698 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3699
3700 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3701 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3702 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3703 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3704 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3705 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3706 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3707 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3708 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3709 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3710 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
d9811cfc
EQ		 3711
3712 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3713 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3714 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3715 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3716 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3717 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3718 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3719 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
b455159c
LG		 3720}
3721
5125c96a 3722static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
ebe57d0c 3723 struct i2c_msg *msg, int num_msgs)
bc50ca29 3724{
2f60dd50
LT		 3725 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
3726 struct amdgpu_device *adev = smu_i2c->adev;
ebfc2533
EQ		 3727 struct smu_context *smu = adev->powerplay.pp_handle;
3728 struct smu_table_context *smu_table = &smu->smu_table;
bc50ca29 3729 struct smu_table *table = &smu_table->driver_table;
5125c96a 3730 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
ebe57d0c
LT		 3731 int i, j, r, c;
3732 u16 dir;
d74a09c8 3733
e281d594
AD		 3734 if (!adev->pm.dpm_enabled)
3735 return -EBUSY;
3736
5125c96a
AD		 3737 req = kzalloc(sizeof(*req), GFP_KERNEL);
3738 if (!req)
3739 return -ENOMEM;
bc50ca29 3740
2f60dd50 3741 req->I2CcontrollerPort = smu_i2c->port;
5125c96a 3742 req->I2CSpeed = I2C_SPEED_FAST_400K;
ebe57d0c
LT		 3743 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
3744 dir = msg[0].flags & I2C_M_RD;
bc50ca29 3745
ebe57d0c
LT		 3746 for (c = i = 0; i < num_msgs; i++) {
3747 for (j = 0; j < msg[i].len; j++, c++) {
3748 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
bc50ca29 3749
5125c96a
AD		 3750 if (!(msg[i].flags & I2C_M_RD)) {
3751 /* write */
3752 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
ebe57d0c
LT		 3753 cmd->ReadWriteData = msg[i].buf[j];
3754 }
3755
3756 if ((dir ^ msg[i].flags) & I2C_M_RD) {
3757 /* The direction changes.
3758 */
3759 dir = msg[i].flags & I2C_M_RD;
3760 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
5125c96a 3761 }
14df5650 3762
ebe57d0c
LT		 3763 req->NumCmds++;
3764
14df5650
AG		 3765 /*
3766 * Insert STOP if we are at the last byte of either last
3767 * message for the transaction or the client explicitly
3768 * requires a STOP at this particular message.
3769 */
ebe57d0c
LT		 3770 if ((j == msg[i].len - 1) &&
3771 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
3772 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
5125c96a 3773 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
ebe57d0c 3774 }
5125c96a 3775 }
d74a09c8 3776 }
e0638c7a 3777 mutex_lock(&adev->pm.mutex);
ebfc2533 3778 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
e0638c7a 3779 mutex_unlock(&adev->pm.mutex);
5125c96a
AD		 3780 if (r)
3781 goto fail;
bc50ca29 3782
ebe57d0c
LT		 3783 for (c = i = 0; i < num_msgs; i++) {
3784 if (!(msg[i].flags & I2C_M_RD)) {
3785 c += msg[i].len;
3786 continue;
3787 }
3788 for (j = 0; j < msg[i].len; j++, c++) {
3789 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
bc50ca29 3790
ebe57d0c 3791 msg[i].buf[j] = cmd->ReadWriteData;
bc50ca29
AD		 3792 }
3793 }
ebe57d0c 3794 r = num_msgs;
bc50ca29 3795fail:
5125c96a 3796 kfree(req);
5125c96a 3797 return r;
bc50ca29
AD		 3798}
3799
3800static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
3801{
3802 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3803}
3804
3805
3806static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
3807 .master_xfer = sienna_cichlid_i2c_xfer,
3808 .functionality = sienna_cichlid_i2c_func,
3809};
3810
35ed2703 3811static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = {
c0838d3a 3812 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
16736627 3813 .max_read_len = MAX_SW_I2C_COMMANDS,
35ed2703 3814 .max_write_len = MAX_SW_I2C_COMMANDS,
16736627
LT		 3815 .max_comb_1st_msg_len = 2,
3816 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
35ed2703
AG		 3817};
3818
2f60dd50 3819static int sienna_cichlid_i2c_control_init(struct smu_context *smu)
bc50ca29 3820{
2f60dd50
LT		 3821 struct amdgpu_device *adev = smu->adev;
3822 int res, i;
3823
3824 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3825 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3826 struct i2c_adapter *control = &smu_i2c->adapter;
3827
3828 smu_i2c->adev = adev;
3829 smu_i2c->port = i;
3830 mutex_init(&smu_i2c->mutex);
3831 control->owner = THIS_MODULE;
3832 control->class = I2C_CLASS_HWMON;
3833 control->dev.parent = &adev->pdev->dev;
3834 control->algo = &sienna_cichlid_i2c_algo;
3835 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
3836 control->quirks = &sienna_cichlid_i2c_control_quirks;
3837 i2c_set_adapdata(control, smu_i2c);
3838
3839 res = i2c_add_adapter(control);
3840 if (res) {
3841 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3842 goto Out_err;
3843 }
3844 }
3845 /* assign the buses used for the FRU EEPROM and RAS EEPROM */
3846 /* XXX ideally this would be something in a vbios data table */
3847 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
3848 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
bc50ca29 3849
2f60dd50
LT		 3850 return 0;
3851Out_err:
3852 for ( ; i >= 0; i--) {
3853 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3854 struct i2c_adapter *control = &smu_i2c->adapter;
bc50ca29 3855
2f60dd50
LT		 3856 i2c_del_adapter(control);
3857 }
bc50ca29
AD		 3858 return res;
3859}
3860
2f60dd50 3861static void sienna_cichlid_i2c_control_fini(struct smu_context *smu)
bc50ca29 3862{
2f60dd50
LT		 3863 struct amdgpu_device *adev = smu->adev;
3864 int i;
3865
3866 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3867 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3868 struct i2c_adapter *control = &smu_i2c->adapter;
3869
3870 i2c_del_adapter(control);
3871 }
3872 adev->pm.ras_eeprom_i2c_bus = NULL;
3873 adev->pm.fru_eeprom_i2c_bus = NULL;
bc50ca29
AD		 3874}
3875
8ca78a0a
EQ		 3876static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
3877 void **table)
3878{
3879 struct smu_table_context *smu_table = &smu->smu_table;
f06d9511
GS		 3880 struct gpu_metrics_v1_3 *gpu_metrics =
3881 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
b4b0b79d
EQ		 3882 SmuMetricsExternal_t metrics_external;
3883 SmuMetrics_t *metrics =
3884 &(metrics_external.SmuMetrics);
be22e2b9
EQ		 3885 SmuMetrics_V2_t *metrics_v2 =
3886 &(metrics_external.SmuMetrics_V2);
7952fa0d
DS		 3887 SmuMetrics_V3_t *metrics_v3 =
3888 &(metrics_external.SmuMetrics_V3);
c524c1c9 3889 struct amdgpu_device *adev = smu->adev;
7952fa0d
DS		 3890 bool use_metrics_v2 = false;
3891 bool use_metrics_v3 = false;
be22e2b9 3892 uint16_t average_gfx_activity;
8ca78a0a
EQ		 3893 int ret = 0;
3894
396beb91
EQ		 3895 switch (smu->adev->ip_versions[MP1_HWIP][0]) {
3896 case IP_VERSION(11, 0, 7):
3897 if (smu->smc_fw_version >= 0x3A4900)
3898 use_metrics_v3 = true;
3899 else if (smu->smc_fw_version >= 0x3A4300)
3900 use_metrics_v2 = true;
3901 break;
3902 case IP_VERSION(11, 0, 11):
3903 if (smu->smc_fw_version >= 0x412D00)
3904 use_metrics_v2 = true;
3905 break;
3906 case IP_VERSION(11, 0, 12):
3907 if (smu->smc_fw_version >= 0x3B2300)
3908 use_metrics_v2 = true;
3909 break;
3910 case IP_VERSION(11, 0, 13):
3911 if (smu->smc_fw_version >= 0x491100)
3912 use_metrics_v2 = true;
3913 break;
3914 default:
3915 break;
3916 }
7952fa0d 3917
da11407f
EQ		 3918 ret = smu_cmn_get_metrics_table(smu,
3919 &metrics_external,
3920 true);
3921 if (ret)
8ca78a0a 3922 return ret;
8ca78a0a 3923
f06d9511 3924 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
8ca78a0a 3925
7952fa0d 3926 gpu_metrics->temperature_edge = use_metrics_v3 ? metrics_v3->TemperatureEdge :
be22e2b9 3927 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge;
7952fa0d 3928 gpu_metrics->temperature_hotspot = use_metrics_v3 ? metrics_v3->TemperatureHotspot :
be22e2b9 3929 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot;
7952fa0d 3930 gpu_metrics->temperature_mem = use_metrics_v3 ? metrics_v3->TemperatureMem :
be22e2b9 3931 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem;
7952fa0d 3932 gpu_metrics->temperature_vrgfx = use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
be22e2b9 3933 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx;
7952fa0d 3934 gpu_metrics->temperature_vrsoc = use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
be22e2b9 3935 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc;
7952fa0d 3936 gpu_metrics->temperature_vrmem = use_metrics_v3 ? metrics_v3->TemperatureVrMem0 :
be22e2b9
EQ		 3937 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0;
3938
7952fa0d 3939 gpu_metrics->average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
be22e2b9 3940 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
7952fa0d 3941 gpu_metrics->average_umc_activity = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
be22e2b9 3942 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity;
7952fa0d
DS		 3943 gpu_metrics->average_mm_activity = use_metrics_v3 ?
3944 (metrics_v3->VcnUsagePercentage0 + metrics_v3->VcnUsagePercentage1) / 2 :
be22e2b9
EQ		 3945 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage;
3946
7952fa0d 3947 gpu_metrics->average_socket_power = use_metrics_v3 ? metrics_v3->AverageSocketPower :
be22e2b9 3948 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower;
7952fa0d 3949 gpu_metrics->energy_accumulator = use_metrics_v3 ? metrics_v3->EnergyAccumulator :
be22e2b9
EQ		 3950 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator;
3951
3a50403f
SK		 3952 if (metrics->CurrGfxVoltageOffset)
3953 gpu_metrics->voltage_gfx =
3954 (155000 - 625 * metrics->CurrGfxVoltageOffset) / 100;
3955 if (metrics->CurrMemVidOffset)
3956 gpu_metrics->voltage_mem =
3957 (155000 - 625 * metrics->CurrMemVidOffset) / 100;
3958 if (metrics->CurrSocVoltageOffset)
3959 gpu_metrics->voltage_soc =
3960 (155000 - 625 * metrics->CurrSocVoltageOffset) / 100;
3961
7952fa0d
DS		 3962 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
3963 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
be22e2b9
EQ		 3964 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
3965 gpu_metrics->average_gfxclk_frequency =
7952fa0d
DS		 3966 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
3967 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
3968 metrics->AverageGfxclkFrequencyPostDs;
8ca78a0a 3969 else
be22e2b9 3970 gpu_metrics->average_gfxclk_frequency =
7952fa0d
DS		 3971 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
3972 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
3973 metrics->AverageGfxclkFrequencyPreDs;
3974
be22e2b9 3975 gpu_metrics->average_uclk_frequency =
7952fa0d
DS		 3976 use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
3977 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
3978 metrics->AverageUclkFrequencyPostDs;
3979 gpu_metrics->average_vclk0_frequency = use_metrics_v3 ? metrics_v3->AverageVclk0Frequency :
be22e2b9 3980 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency;
7952fa0d 3981 gpu_metrics->average_dclk0_frequency = use_metrics_v3 ? metrics_v3->AverageDclk0Frequency :
be22e2b9 3982 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency;
7952fa0d 3983 gpu_metrics->average_vclk1_frequency = use_metrics_v3 ? metrics_v3->AverageVclk1Frequency :
be22e2b9 3984 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency;
7952fa0d 3985 gpu_metrics->average_dclk1_frequency = use_metrics_v3 ? metrics_v3->AverageDclk1Frequency :
be22e2b9
EQ		 3986 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency;
3987
7952fa0d 3988 gpu_metrics->current_gfxclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
be22e2b9 3989 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK];
7952fa0d 3990 gpu_metrics->current_socclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
be22e2b9 3991 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK];
7952fa0d 3992 gpu_metrics->current_uclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
be22e2b9 3993 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK];
7952fa0d 3994 gpu_metrics->current_vclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
be22e2b9 3995 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0];
7952fa0d 3996 gpu_metrics->current_dclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
be22e2b9 3997 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0];
7952fa0d 3998 gpu_metrics->current_vclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
be22e2b9 3999 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1];
7952fa0d 4000 gpu_metrics->current_dclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
be22e2b9
EQ		 4001 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1];
4002
4003 gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu);
f06d9511 4004 gpu_metrics->indep_throttle_status =
be22e2b9 4005 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
f06d9511 4006 sienna_cichlid_throttler_map);
b4b0b79d 4007
7952fa0d
DS		 4008 gpu_metrics->current_fan_speed = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
4009 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
c524c1c9 4010
1d789535
AD		 4011 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) ||
4012 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) {
7952fa0d
DS		 4013 gpu_metrics->pcie_link_width = use_metrics_v3 ? metrics_v3->PcieWidth :
4014 use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
4015 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v3 ? metrics_v3->PcieRate :
4016 use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
c524c1c9
EQ		 4017 } else {
4018 gpu_metrics->pcie_link_width =
4019 smu_v11_0_get_current_pcie_link_width(smu);
4020 gpu_metrics->pcie_link_speed =
4021 smu_v11_0_get_current_pcie_link_speed(smu);
4022 }
8ca78a0a 4023
de4b7cd8
KW		 4024 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
4025
8ca78a0a
EQ		 4026 *table = (void *)gpu_metrics;
4027
f06d9511 4028 return sizeof(struct gpu_metrics_v1_3);
8ca78a0a 4029}
bc50ca29 4030
3ddd0c90 4031static int sienna_cichlid_check_ecc_table_support(struct smu_context *smu)
4032{
4033 uint32_t if_version = 0xff, smu_version = 0xff;
4034 int ret = 0;
4035
4036 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
4037 if (ret)
4038 return -EOPNOTSUPP;
4039
4040 if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION)
4041 ret = -EOPNOTSUPP;
4042
4043 return ret;
4044}
4045
4046static ssize_t sienna_cichlid_get_ecc_info(struct smu_context *smu,
4047 void *table)
4048{
4049 struct smu_table_context *smu_table = &smu->smu_table;
4050 EccInfoTable_t *ecc_table = NULL;
4051 struct ecc_info_per_ch *ecc_info_per_channel = NULL;
4052 int i, ret = 0;
4053 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
4054
4055 ret = sienna_cichlid_check_ecc_table_support(smu);
4056 if (ret)
4057 return ret;
4058
4059 ret = smu_cmn_update_table(smu,
4060 SMU_TABLE_ECCINFO,
4061 0,
4062 smu_table->ecc_table,
4063 false);
4064 if (ret) {
4065 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n");
4066 return ret;
4067 }
4068
4069 ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
4070
4071 for (i = 0; i < SIENNA_CICHLID_UMC_CHANNEL_NUM; i++) {
4072 ecc_info_per_channel = &(eccinfo->ecc[i]);
4073 ecc_info_per_channel->ce_count_lo_chip =
4074 ecc_table->EccInfo[i].ce_count_lo_chip;
4075 ecc_info_per_channel->ce_count_hi_chip =
4076 ecc_table->EccInfo[i].ce_count_hi_chip;
4077 ecc_info_per_channel->mca_umc_status =
4078 ecc_table->EccInfo[i].mca_umc_status;
4079 ecc_info_per_channel->mca_umc_addr =
4080 ecc_table->EccInfo[i].mca_umc_addr;
4081 }
4082
4083 return ret;
4084}
05f39286
EQ		 4085static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
4086{
f4e2a66d 4087 uint16_t *mgpu_fan_boost_limit_rpm;
b804a75d 4088
f4e2a66d 4089 GET_PPTABLE_MEMBER(MGpuFanBoostLimitRpm, &mgpu_fan_boost_limit_rpm);
b804a75d
EQ		 4090 /*
4091 * Skip the MGpuFanBoost setting for those ASICs
4092 * which do not support it
4093 */
f4e2a66d 4094 if (*mgpu_fan_boost_limit_rpm == 0)
b804a75d
EQ		 4095 return 0;
4096
05f39286
EQ		 4097 return smu_cmn_send_smc_msg_with_param(smu,
4098 SMU_MSG_SetMGpuFanBoostLimitRpm,
4099 0,
4100 NULL);
4101}
4102
76c71f00
EQ		 4103static int sienna_cichlid_gpo_control(struct smu_context *smu,
4104 bool enablement)
4105{
ac7804bb 4106 uint32_t smu_version;
76c71f00
EQ		 4107 int ret = 0;
4108
ac7804bb 4109
7ade3ca9 4110 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
ac7804bb
EQ		 4111 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
4112 if (ret)
4113 return ret;
4114
4115 if (enablement) {
4116 if (smu_version < 0x003a2500) {
4117 ret = smu_cmn_send_smc_msg_with_param(smu,
4118 SMU_MSG_SetGpoFeaturePMask,
4119 GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
4120 NULL);
4121 } else {
4122 ret = smu_cmn_send_smc_msg_with_param(smu,
4123 SMU_MSG_DisallowGpo,
4124 0,
4125 NULL);
4126 }
4127 } else {
4128 if (smu_version < 0x003a2500) {
4129 ret = smu_cmn_send_smc_msg_with_param(smu,
4130 SMU_MSG_SetGpoFeaturePMask,
4131 0,
4132 NULL);
4133 } else {
4134 ret = smu_cmn_send_smc_msg_with_param(smu,
4135 SMU_MSG_DisallowGpo,
4136 1,
4137 NULL);
4138 }
4139 }
76c71f00
EQ		 4140 }
4141
4142 return ret;
4143}
d7f52e29
EQ		 4144
4145static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
4146{
4147 uint32_t smu_version;
4148 int ret = 0;
4149
4150 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
4151 if (ret)
4152 return ret;
4153
4154 /*
4155 * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
4156 * onwards PMFWs.
4157 */
4158 if (smu_version < 0x003A2D00)
4159 return 0;
4160
4161 return smu_cmn_send_smc_msg_with_param(smu,
4162 SMU_MSG_Enable2ndUSB20Port,
4163 smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
4164 1 : 0,
4165 NULL);
4166}
4167
4168static int sienna_cichlid_system_features_control(struct smu_context *smu,
4169 bool en)
4170{
4171 int ret = 0;
4172
4173 if (en) {
4174 ret = sienna_cichlid_notify_2nd_usb20_port(smu);
4175 if (ret)
4176 return ret;
4177 }
4178
4179 return smu_v11_0_system_features_control(smu, en);
4180}
4181
1689fca0
EQ		 4182static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
4183 enum pp_mp1_state mp1_state)
4184{
9113a0fb
GC		 4185 int ret;
4186
1689fca0
EQ		 4187 switch (mp1_state) {
4188 case PP_MP1_STATE_UNLOAD:
9113a0fb
GC		 4189 ret = smu_cmn_set_mp1_state(smu, mp1_state);
4190 break;
1689fca0 4191 default:
9113a0fb
GC		 4192 /* Ignore others */
4193 ret = 0;
1689fca0
EQ		 4194 }
4195
9113a0fb 4196 return ret;
1689fca0
EQ		 4197}
4198
db5b5c67
AG		 4199static void sienna_cichlid_stb_init(struct smu_context *smu)
4200{
4201 struct amdgpu_device *adev = smu->adev;
4202 uint32_t reg;
4203
4204 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START);
4205 smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE);
4206
4207 /* STB is disabled */
4208 if (!smu->stb_context.enabled)
4209 return;
4210
4211 spin_lock_init(&smu->stb_context.lock);
4212
4213 /* STB buffer size in bytes as function of FIFO depth */
4214 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO);
4215 smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH);
4216 smu->stb_context.stb_buf_size *= SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES;
4217
4218 dev_info(smu->adev->dev, "STB initialized to %d entries",
4219 smu->stb_context.stb_buf_size / SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES);
4220
4221}
4222
c85bf88b
EQ		 4223static int sienna_cichlid_get_default_config_table_settings(struct smu_context *smu,
4224 struct config_table_setting *table)
4225{
4226 struct amdgpu_device *adev = smu->adev;
4227
4228 if (!table)
4229 return -EINVAL;
4230
4231 table->gfxclk_average_tau = 10;
4232 table->socclk_average_tau = 10;
4233 table->fclk_average_tau = 10;
4234 table->uclk_average_tau = 10;
4235 table->gfx_activity_average_tau = 10;
4236 table->mem_activity_average_tau = 10;
4237 table->socket_power_average_tau = 100;
ab9d97d6 4238 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7))
c85bf88b
EQ		 4239 table->apu_socket_power_average_tau = 100;
4240
4241 return 0;
4242}
4243
4244static int sienna_cichlid_set_config_table(struct smu_context *smu,
4245 struct config_table_setting *table)
4246{
4247 DriverSmuConfigExternal_t driver_smu_config_table;
4248
4249 if (!table)
4250 return -EINVAL;
4251
4252 memset(&driver_smu_config_table,
4253 0,
4254 sizeof(driver_smu_config_table));
4255 driver_smu_config_table.DriverSmuConfig.GfxclkAverageLpfTau =
4256 table->gfxclk_average_tau;
4257 driver_smu_config_table.DriverSmuConfig.FclkAverageLpfTau =
4258 table->fclk_average_tau;
4259 driver_smu_config_table.DriverSmuConfig.UclkAverageLpfTau =
4260 table->uclk_average_tau;
4261 driver_smu_config_table.DriverSmuConfig.GfxActivityLpfTau =
4262 table->gfx_activity_average_tau;
4263 driver_smu_config_table.DriverSmuConfig.UclkActivityLpfTau =
4264 table->mem_activity_average_tau;
4265 driver_smu_config_table.DriverSmuConfig.SocketPowerLpfTau =
4266 table->socket_power_average_tau;
4267
4268 return smu_cmn_update_table(smu,
4269 SMU_TABLE_DRIVER_SMU_CONFIG,
4270 0,
4271 (void *)&driver_smu_config_table,
4272 true);
4273}
4274
6a8cf634
AD		 4275static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu,
4276 void *buf,
4277 uint32_t size)
db5b5c67
AG		 4278{
4279 uint32_t *p = buf;
4280 struct amdgpu_device *adev = smu->adev;
4281
4282 /* No need to disable interrupts for now as we don't lock it yet from ISR */
4283 spin_lock(&smu->stb_context.lock);
4284
4285 /*
4286 * Read the STB FIFO in units of 32bit since this is the accessor window
4287 * (register width) we have.
4288 */
4289 buf = ((char *) buf) + size;
4290 while ((void *)p < buf)
4291 *p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3));
4292
4293 spin_unlock(&smu->stb_context.lock);
4294
4295 return 0;
4296}
4297
672c0218
VZ		 4298static bool sienna_cichlid_is_mode2_reset_supported(struct smu_context *smu)
4299{
4300 return true;
4301}
4302
4303static int sienna_cichlid_mode2_reset(struct smu_context *smu)
4304{
4305 u32 smu_version;
4306 int ret = 0, index;
4307 struct amdgpu_device *adev = smu->adev;
4308 int timeout = 100;
4309
4310 smu_cmn_get_smc_version(smu, NULL, &smu_version);
4311
4312 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
4313 SMU_MSG_DriverMode2Reset);
4314
4315 mutex_lock(&smu->message_lock);
4316
4317 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index,
4318 SMU_RESET_MODE_2);
4319
4320 ret = smu_cmn_wait_for_response(smu);
4321 while (ret != 0 && timeout) {
4322 ret = smu_cmn_wait_for_response(smu);
4323 /* Wait a bit more time for getting ACK */
4324 if (ret != 0) {
4325 --timeout;
4326 usleep_range(500, 1000);
4327 continue;
4328 } else {
4329 break;
4330 }
4331 }
4332
4333 if (!timeout) {
4334 dev_err(adev->dev,
4335 "failed to send mode2 message \tparam: 0x%08x response %#x\n",
4336 SMU_RESET_MODE_2, ret);
4337 goto out;
4338 }
4339
4340 dev_info(smu->adev->dev, "restore config space...\n");
4341 /* Restore the config space saved during init */
4342 amdgpu_device_load_pci_state(adev->pdev);
4343out:
4344 mutex_unlock(&smu->message_lock);
4345
4346 return ret;
4347}
4348
b455159c 4349static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
b455159c
LG		 4350 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
4351 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
f6b4b4a1 4352 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
6fb176a7 4353 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
bc50ca29
AD		 4354 .i2c_init = sienna_cichlid_i2c_control_init,
4355 .i2c_fini = sienna_cichlid_i2c_control_fini,
b455159c
LG		 4356 .print_clk_levels = sienna_cichlid_print_clk_levels,
4357 .force_clk_levels = sienna_cichlid_force_clk_levels,
4358 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
b455159c
LG		 4359 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
4360 .display_config_changed = sienna_cichlid_display_config_changed,
4361 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
b455159c 4362 .is_dpm_running = sienna_cichlid_is_dpm_running,
0d8318e1 4363 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
d9ca7567 4364 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
b455159c
LG		 4365 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
4366 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
b455159c
LG		 4367 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
4368 .read_sensor = sienna_cichlid_read_sensor,
4369 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
b2785e25 4370 .set_performance_level = smu_v11_0_set_performance_level,
b455159c
LG		 4371 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
4372 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
4373 .get_power_limit = sienna_cichlid_get_power_limit,
08ccfe08 4374 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
b455159c
LG		 4375 .dump_pptable = sienna_cichlid_dump_pptable,
4376 .init_microcode = smu_v11_0_init_microcode,
4377 .load_microcode = smu_v11_0_load_microcode,
0a2d922a 4378 .fini_microcode = smu_v11_0_fini_microcode,
c1b353b7 4379 .init_smc_tables = sienna_cichlid_init_smc_tables,
b455159c
LG		 4380 .fini_smc_tables = smu_v11_0_fini_smc_tables,
4381 .init_power = smu_v11_0_init_power,
4382 .fini_power = smu_v11_0_fini_power,
4383 .check_fw_status = smu_v11_0_check_fw_status,
4a13b4ce 4384 .setup_pptable = sienna_cichlid_setup_pptable,
b455159c 4385 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
b455159c 4386 .check_fw_version = smu_v11_0_check_fw_version,
caad2613 4387 .write_pptable = smu_cmn_write_pptable,
b455159c
LG		 4388 .set_driver_table_location = smu_v11_0_set_driver_table_location,
4389 .set_tool_table_location = smu_v11_0_set_tool_table_location,
4390 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
d7f52e29 4391 .system_features_control = sienna_cichlid_system_features_control,
66c86828
EQ		 4392 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
4393 .send_smc_msg = smu_cmn_send_smc_msg,
31157341 4394 .init_display_count = NULL,
b455159c 4395 .set_allowed_mask = smu_v11_0_set_allowed_mask,
28251d72 4396 .get_enabled_mask = smu_cmn_get_enabled_mask,
b4bb3aaf 4397 .feature_is_enabled = smu_cmn_feature_is_enabled,
af5ba6d2 4398 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
31157341 4399 .notify_display_change = NULL,
b455159c 4400 .set_power_limit = smu_v11_0_set_power_limit,
b455159c
LG		 4401 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
4402 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
4403 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
ce63d8f8 4404 .set_min_dcef_deep_sleep = NULL,
b455159c
LG		 4405 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
4406 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
4407 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
0d8318e1 4408 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
f3289d04 4409 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
b455159c
LG		 4410 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
4411 .gfx_off_control = smu_v11_0_gfx_off_control,
4412 .register_irq_handler = smu_v11_0_register_irq_handler,
4413 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
4414 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
9fd4781b 4415 .baco_is_support = smu_v11_0_baco_is_support,
b455159c
LG		 4416 .baco_get_state = smu_v11_0_baco_get_state,
4417 .baco_set_state = smu_v11_0_baco_set_state,
13d75ead
EQ		 4418 .baco_enter = sienna_cichlid_baco_enter,
4419 .baco_exit = sienna_cichlid_baco_exit,
ea8139d8
WS		 4420 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
4421 .mode1_reset = smu_v11_0_mode1_reset,
258d290c 4422 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
10e96d89 4423 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
aa75fa34 4424 .set_default_od_settings = sienna_cichlid_set_default_od_settings,
37a58f69 4425 .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
49017304 4426 .restore_user_od_settings = sienna_cichlid_restore_user_od_settings,
66b8a9c0 4427 .run_btc = sienna_cichlid_run_btc,
18a4b3de 4428 .set_power_source = smu_v11_0_set_power_source,
7dbf7805
EQ		 4429 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
4430 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
8ca78a0a 4431 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
05f39286 4432 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
e988026f 4433 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
5ce99853 4434 .deep_sleep_control = smu_v11_0_deep_sleep_control,
3204ff3e 4435 .get_fan_parameters = sienna_cichlid_get_fan_parameters,
234676d6 4436 .interrupt_work = smu_v11_0_interrupt_work,
76c71f00 4437 .gpo_control = sienna_cichlid_gpo_control,
1689fca0 4438 .set_mp1_state = sienna_cichlid_set_mp1_state,
db5b5c67 4439 .stb_collect_info = sienna_cichlid_stb_get_data_direct,
3ddd0c90 4440 .get_ecc_info = sienna_cichlid_get_ecc_info,
c85bf88b
EQ		 4441 .get_default_config_table_settings = sienna_cichlid_get_default_config_table_settings,
4442 .set_config_table = sienna_cichlid_set_config_table,
ebd9c071 4443 .get_unique_id = sienna_cichlid_get_unique_id,
672c0218
VZ		 4444 .mode2_reset_is_support = sienna_cichlid_is_mode2_reset_supported,
4445 .mode2_reset = sienna_cichlid_mode2_reset,
b455159c
LG		 4446};
4447
4448void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
4449{
4450 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
6c339f37
EQ		 4451 smu->message_map = sienna_cichlid_message_map;
4452 smu->clock_map = sienna_cichlid_clk_map;
4453 smu->feature_map = sienna_cichlid_feature_mask_map;
4454 smu->table_map = sienna_cichlid_table_map;
4455 smu->pwr_src_map = sienna_cichlid_pwr_src_map;
4456 smu->workload_map = sienna_cichlid_workload_map;
da1db031 4457 smu_v11_0_set_smu_mailbox_registers(smu);
b455159c 4458}
Linux 6.x block layer and io_uring tree(s)