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drm/amdgpu/swsmu/arcturus: simplify sensor handling
[linux-block.git] / drivers / gpu / drm / amd / pm / swsmu / smu11 / sienna_cichlid_ppt.c
CommitLineData
b455159c
LG		 1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
d8e0b16d
EQ		 24#define SWSMU_CODE_LAYER_L2
25
b455159c
LG		 26#include <linux/firmware.h>
27#include <linux/pci.h>
bc50ca29 28#include <linux/i2c.h>
b455159c
LG		 29#include "amdgpu.h"
30#include "amdgpu_smu.h"
b455159c
LG		 31#include "atomfirmware.h"
32#include "amdgpu_atomfirmware.h"
22f2447c 33#include "amdgpu_atombios.h"
b455159c
LG		 34#include "smu_v11_0.h"
35#include "smu11_driver_if_sienna_cichlid.h"
36#include "soc15_common.h"
37#include "atom.h"
38#include "sienna_cichlid_ppt.h"
e05acd78 39#include "smu_v11_0_7_pptable.h"
b455159c 40#include "smu_v11_0_7_ppsmc.h"
40d3b8db 41#include "nbio/nbio_2_3_offset.h"
b7d25b5f 42#include "nbio/nbio_2_3_sh_mask.h"
e05acd78
LG		 43#include "thm/thm_11_0_2_offset.h"
44#include "thm/thm_11_0_2_sh_mask.h"
ea8139d8
WS		 45#include "mp/mp_11_0_offset.h"
46#include "mp/mp_11_0_sh_mask.h"
b455159c 47
6c339f37
EQ		 48#include "asic_reg/mp/mp_11_0_sh_mask.h"
49#include "smu_cmn.h"
50
55084d7f
EQ		 51/*
52 * DO NOT use these for err/warn/info/debug messages.
53 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
54 * They are more MGPU friendly.
55 */
56#undef pr_err
57#undef pr_warn
58#undef pr_info
59#undef pr_debug
60
bc50ca29
AD		 61#define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
62
b455159c
LG		 63#define FEATURE_MASK(feature) (1ULL << feature)
64#define SMC_DPM_FEATURE ( \
65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
fea905d4 66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65297d50 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
5cb74353 68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
4cd4f45b 69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
5f338f70 70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
ce7e5a6e
JC		 71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \
72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
b455159c 73
d817f375
LG		 74#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
75
6c339f37
EQ		 76static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
77 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
78 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
79 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
91190db1
LG		 80 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
81 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
82 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
83 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
6c339f37
EQ		 84 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
85 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
86 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
87 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
88 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
89 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
90 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
91190db1
LG		 91 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
92 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0),
93 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0),
94 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
95 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
96 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0),
97 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
98 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
66b8a9c0 99 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
91190db1
LG		 100 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
101 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
102 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0),
6c339f37 103 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
91190db1 104 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
6c339f37
EQ		 105 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
106 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
107 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
91190db1
LG		 108 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
109 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
110 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
111 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
112 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
113 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
114 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
115 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
6c339f37 116 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
91190db1
LG		 117 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
118 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
119 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
6c339f37 120 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
91190db1
LG		 121 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
122 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
123 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
124 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
125 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
126 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
127 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
128 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
05f39286 129 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
76c71f00 130 MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0),
b455159c
LG		 131};
132
6c339f37 133static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
b455159c
LG		 134 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
135 CLK_MAP(SCLK, PPCLK_GFXCLK),
136 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
137 CLK_MAP(FCLK, PPCLK_FCLK),
138 CLK_MAP(UCLK, PPCLK_UCLK),
139 CLK_MAP(MCLK, PPCLK_UCLK),
140 CLK_MAP(DCLK, PPCLK_DCLK_0),
9c0551f2
JC		 141 CLK_MAP(DCLK1, PPCLK_DCLK_1),
142 CLK_MAP(VCLK, PPCLK_VCLK_0),
b455159c
LG		 143 CLK_MAP(VCLK1, PPCLK_VCLK_1),
144 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
145 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
146 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
147 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
148};
149
6c339f37 150static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
b455159c
LG		 151 FEA_MAP(DPM_PREFETCHER),
152 FEA_MAP(DPM_GFXCLK),
31cb0dd9 153 FEA_MAP(DPM_GFX_GPO),
b455159c 154 FEA_MAP(DPM_UCLK),
e9073b43 155 FEA_MAP(DPM_FCLK),
b455159c
LG		 156 FEA_MAP(DPM_SOCCLK),
157 FEA_MAP(DPM_MP0CLK),
158 FEA_MAP(DPM_LINK),
159 FEA_MAP(DPM_DCEFCLK),
e9073b43 160 FEA_MAP(DPM_XGMI),
b455159c
LG		 161 FEA_MAP(MEM_VDDCI_SCALING),
162 FEA_MAP(MEM_MVDD_SCALING),
163 FEA_MAP(DS_GFXCLK),
164 FEA_MAP(DS_SOCCLK),
e9073b43 165 FEA_MAP(DS_FCLK),
b455159c
LG		 166 FEA_MAP(DS_LCLK),
167 FEA_MAP(DS_DCEFCLK),
168 FEA_MAP(DS_UCLK),
169 FEA_MAP(GFX_ULV),
170 FEA_MAP(FW_DSTATE),
171 FEA_MAP(GFXOFF),
172 FEA_MAP(BACO),
6fb176a7 173 FEA_MAP(MM_DPM_PG),
b455159c
LG		 174 FEA_MAP(RSMU_SMN_CG),
175 FEA_MAP(PPT),
176 FEA_MAP(TDC),
177 FEA_MAP(APCC_PLUS),
178 FEA_MAP(GTHR),
179 FEA_MAP(ACDC),
180 FEA_MAP(VR0HOT),
181 FEA_MAP(VR1HOT),
182 FEA_MAP(FW_CTF),
183 FEA_MAP(FAN_CONTROL),
184 FEA_MAP(THERMAL),
185 FEA_MAP(GFX_DCS),
186 FEA_MAP(RM),
187 FEA_MAP(LED_DISPLAY),
188 FEA_MAP(GFX_SS),
189 FEA_MAP(OUT_OF_BAND_MONITOR),
190 FEA_MAP(TEMP_DEPENDENT_VMIN),
191 FEA_MAP(MMHUB_PG),
192 FEA_MAP(ATHUB_PG),
cf06331f 193 FEA_MAP(APCC_DFLL),
b455159c
LG		 194};
195
6c339f37 196static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
b455159c
LG		 197 TAB_MAP(PPTABLE),
198 TAB_MAP(WATERMARKS),
199 TAB_MAP(AVFS_PSM_DEBUG),
200 TAB_MAP(AVFS_FUSE_OVERRIDE),
201 TAB_MAP(PMSTATUSLOG),
202 TAB_MAP(SMU_METRICS),
203 TAB_MAP(DRIVER_SMU_CONFIG),
204 TAB_MAP(ACTIVITY_MONITOR_COEFF),
205 TAB_MAP(OVERDRIVE),
206 TAB_MAP(I2C_COMMANDS),
207 TAB_MAP(PACE),
208};
209
6c339f37 210static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
1d5ca713
LG		 211 PWR_MAP(AC),
212 PWR_MAP(DC),
213};
214
6c339f37 215static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
b455159c
LG		 216 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
217 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
218 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
219 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
220 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
221 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT),
222 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
223};
224
b455159c
LG		 225static int
226sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
227 uint32_t *feature_mask, uint32_t num)
228{
fea905d4
LG		 229 struct amdgpu_device *adev = smu->adev;
230
b455159c
LG		 231 if (num > 2)
232 return -EINVAL;
233
234 memset(feature_mask, 0, sizeof(uint32_t) * num);
235
4cd4f45b 236 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
15dbe18f 237 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
ce7e5a6e 238 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
094cdf15 239 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
5f338f70 240 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
86a9eb3f 241 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
80c36f86 242 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
9aa60213
LG		 243 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
244 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
d28f4aa1 245 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
20d71dcc 246 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
d0d71970 247 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
886c8bc6
LG		 248 | FEATURE_MASK(FEATURE_PPT_BIT)
249 | FEATURE_MASK(FEATURE_TDC_BIT)
3fc006f5 250 | FEATURE_MASK(FEATURE_BACO_BIT)
cf06331f 251 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
35ed946c 252 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
1c58d429 253 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
b971df70
LG		 254 | FEATURE_MASK(FEATURE_THERMAL_BIT)
255 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
fea905d4 256
c96721eb 257 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
fea905d4 258 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
c96721eb
KF		 259 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
260 }
fea905d4 261
65297d50 262 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
fc17cd3f
LG		 263 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
264 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
265 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
65297d50 266
5cb74353
LG		 267 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
268 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
269
5f338f70
LG		 270 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
271 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
272
fea905d4
LG		 273 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
274 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
b455159c 275
62c1ea6b
LG		 276 if (adev->pm.pp_feature & PP_ULV_MASK)
277 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
278
02bb391d
LG		 279 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
280 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
281
e0da123a
LG		 282 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
283 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
284
b794616d
KF		 285 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
286 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
287
846938c2
KF		 288 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
289 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
290
6fb176a7
LG		 291 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
292 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
293 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
294
b455159c
LG		 295 return 0;
296}
297
298static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
299{
4a13b4ce 300 struct smu_table_context *table_context = &smu->smu_table;
e05acd78 301 struct smu_11_0_7_powerplay_table *powerplay_table =
4a13b4ce
EQ		 302 table_context->power_play_table;
303 struct smu_baco_context *smu_baco = &smu->smu_baco;
304
e05acd78
LG		 305 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO ||
306 powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO)
4a13b4ce 307 smu_baco->platform_support = true;
4a13b4ce
EQ		 308
309 table_context->thermal_controller_type =
310 powerplay_table->thermal_controller_type;
311
b455159c
LG		 312 return 0;
313}
314
315static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
316{
dccc7c21
LG		 317 struct smu_table_context *table_context = &smu->smu_table;
318 PPTable_t *smc_pptable = table_context->driver_pptable;
319 struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
320 int index, ret;
dccc7c21
LG		 321
322 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
323 smc_dpm_info);
324
22f2447c 325 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
dccc7c21
LG		 326 (uint8_t **)&smc_dpm_table);
327 if (ret)
328 return ret;
329
330 memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
969c8d16
LG		 331 sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
332
b455159c
LG		 333 return 0;
334}
335
336static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
337{
b455159c 338 struct smu_table_context *table_context = &smu->smu_table;
e05acd78 339 struct smu_11_0_7_powerplay_table *powerplay_table =
4a13b4ce 340 table_context->power_play_table;
b455159c
LG		 341
342 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
343 sizeof(PPTable_t));
344
4a13b4ce
EQ		 345 return 0;
346}
b455159c 347
4a13b4ce
EQ		 348static int sienna_cichlid_setup_pptable(struct smu_context *smu)
349{
350 int ret = 0;
b455159c 351
4a13b4ce
EQ		 352 ret = smu_v11_0_setup_pptable(smu);
353 if (ret)
354 return ret;
355
356 ret = sienna_cichlid_store_powerplay_table(smu);
357 if (ret)
358 return ret;
359
360 ret = sienna_cichlid_append_powerplay_table(smu);
361 if (ret)
362 return ret;
363
364 ret = sienna_cichlid_check_powerplay_table(smu);
365 if (ret)
366 return ret;
367
368 return ret;
b455159c
LG		 369}
370
c1b353b7 371static int sienna_cichlid_tables_init(struct smu_context *smu)
b455159c
LG		 372{
373 struct smu_table_context *smu_table = &smu->smu_table;
c1b353b7 374 struct smu_table *tables = smu_table->tables;
b455159c
LG		 375
376 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
377 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
378 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
379 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
380 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
381 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
bc50ca29
AD		 382 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
383 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c
LG		 384 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
385 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
386 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
387 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
388 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
389 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
390 AMDGPU_GEM_DOMAIN_VRAM);
391
392 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
393 if (!smu_table->metrics_table)
8ca78a0a 394 goto err0_out;
b455159c
LG		 395 smu_table->metrics_time = 0;
396
8ca78a0a
EQ		 397 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_0);
398 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
399 if (!smu_table->gpu_metrics_table)
400 goto err1_out;
401
40d3b8db
LG		 402 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
403 if (!smu_table->watermarks_table)
8ca78a0a 404 goto err2_out;
40d3b8db 405
b455159c 406 return 0;
8ca78a0a
EQ		 407
408err2_out:
409 kfree(smu_table->gpu_metrics_table);
410err1_out:
411 kfree(smu_table->metrics_table);
412err0_out:
413 return -ENOMEM;
b455159c
LG		 414}
415
60ae4d67
EQ		 416static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
417 MetricsMember_t member,
418 uint32_t *value)
419{
420 struct smu_table_context *smu_table= &smu->smu_table;
421 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
422 int ret = 0;
423
424 mutex_lock(&smu->metrics_lock);
425
fceafc9b
EQ		 426 ret = smu_cmn_get_metrics_table_locked(smu,
427 NULL,
428 false);
60ae4d67
EQ		 429 if (ret) {
430 mutex_unlock(&smu->metrics_lock);
431 return ret;
432 }
433
8c686254
EQ		 434 switch (member) {
435 case METRICS_CURR_GFXCLK:
436 *value = metrics->CurrClock[PPCLK_GFXCLK];
437 break;
438 case METRICS_CURR_SOCCLK:
439 *value = metrics->CurrClock[PPCLK_SOCCLK];
440 break;
441 case METRICS_CURR_UCLK:
442 *value = metrics->CurrClock[PPCLK_UCLK];
443 break;
444 case METRICS_CURR_VCLK:
445 *value = metrics->CurrClock[PPCLK_VCLK_0];
446 break;
447 case METRICS_CURR_VCLK1:
448 *value = metrics->CurrClock[PPCLK_VCLK_1];
449 break;
450 case METRICS_CURR_DCLK:
451 *value = metrics->CurrClock[PPCLK_DCLK_0];
452 break;
453 case METRICS_CURR_DCLK1:
454 *value = metrics->CurrClock[PPCLK_DCLK_1];
455 break;
9d09fa6f
ND		 456 case METRICS_CURR_DCEFCLK:
457 *value = metrics->CurrClock[PPCLK_DCEFCLK];
458 break;
4e2b3e23
KF		 459 case METRICS_CURR_FCLK:
460 *value = metrics->CurrClock[PPCLK_FCLK];
461 break;
8c686254 462 case METRICS_AVERAGE_GFXCLK:
d817f375
LG		 463 if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
464 *value = metrics->AverageGfxclkFrequencyPostDs;
465 else
466 *value = metrics->AverageGfxclkFrequencyPreDs;
8c686254
EQ		 467 break;
468 case METRICS_AVERAGE_FCLK:
d817f375 469 *value = metrics->AverageFclkFrequencyPostDs;
8c686254
EQ		 470 break;
471 case METRICS_AVERAGE_UCLK:
d817f375 472 *value = metrics->AverageUclkFrequencyPostDs;
8c686254
EQ		 473 break;
474 case METRICS_AVERAGE_GFXACTIVITY:
475 *value = metrics->AverageGfxActivity;
476 break;
477 case METRICS_AVERAGE_MEMACTIVITY:
478 *value = metrics->AverageUclkActivity;
479 break;
480 case METRICS_AVERAGE_SOCKETPOWER:
481 *value = metrics->AverageSocketPower << 8;
482 break;
483 case METRICS_TEMPERATURE_EDGE:
484 *value = metrics->TemperatureEdge *
485 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
486 break;
487 case METRICS_TEMPERATURE_HOTSPOT:
488 *value = metrics->TemperatureHotspot *
489 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
490 break;
491 case METRICS_TEMPERATURE_MEM:
492 *value = metrics->TemperatureMem *
493 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
494 break;
495 case METRICS_TEMPERATURE_VRGFX:
496 *value = metrics->TemperatureVrGfx *
497 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
498 break;
499 case METRICS_TEMPERATURE_VRSOC:
500 *value = metrics->TemperatureVrSoc *
501 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
502 break;
503 case METRICS_THROTTLER_STATUS:
504 *value = metrics->ThrottlerStatus;
505 break;
506 case METRICS_CURR_FANSPEED:
507 *value = metrics->CurrFanSpeed;
508 break;
509 default:
510 *value = UINT_MAX;
511 break;
512 }
513
b455159c
LG		 514 mutex_unlock(&smu->metrics_lock);
515
516 return ret;
8c686254 517
b455159c
LG		 518}
519
520static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
521{
522 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
523
b455159c
LG		 524 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
525 GFP_KERNEL);
526 if (!smu_dpm->dpm_context)
527 return -ENOMEM;
528
529 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
530
531 return 0;
532}
533
c1b353b7
EQ		 534static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
535{
536 int ret = 0;
537
538 ret = sienna_cichlid_tables_init(smu);
539 if (ret)
540 return ret;
541
542 ret = sienna_cichlid_allocate_dpm_context(smu);
543 if (ret)
544 return ret;
545
546 return smu_v11_0_init_smc_tables(smu);
547}
548
b455159c
LG		 549static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
550{
90a89c31
EQ		 551 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
552 PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
553 struct smu_11_0_dpm_table *dpm_table;
85dec717 554 struct amdgpu_device *adev = smu->adev;
90a89c31 555 int ret = 0;
b455159c 556
90a89c31
EQ		 557 /* socclk dpm table setup */
558 dpm_table = &dpm_context->dpm_tables.soc_table;
b4bb3aaf 559 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
90a89c31
EQ		 560 ret = smu_v11_0_set_single_dpm_table(smu,
561 SMU_SOCCLK,
562 dpm_table);
563 if (ret)
564 return ret;
565 dpm_table->is_fine_grained =
566 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
567 } else {
568 dpm_table->count = 1;
569 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
570 dpm_table->dpm_levels[0].enabled = true;
571 dpm_table->min = dpm_table->dpm_levels[0].value;
572 dpm_table->max = dpm_table->dpm_levels[0].value;
573 }
b455159c 574
90a89c31
EQ		 575 /* gfxclk dpm table setup */
576 dpm_table = &dpm_context->dpm_tables.gfx_table;
b4bb3aaf 577 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
90a89c31
EQ		 578 ret = smu_v11_0_set_single_dpm_table(smu,
579 SMU_GFXCLK,
580 dpm_table);
581 if (ret)
582 return ret;
583 dpm_table->is_fine_grained =
584 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
585 } else {
586 dpm_table->count = 1;
587 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
588 dpm_table->dpm_levels[0].enabled = true;
589 dpm_table->min = dpm_table->dpm_levels[0].value;
590 dpm_table->max = dpm_table->dpm_levels[0].value;
591 }
b455159c 592
90a89c31
EQ		 593 /* uclk dpm table setup */
594 dpm_table = &dpm_context->dpm_tables.uclk_table;
b4bb3aaf 595 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
90a89c31
EQ		 596 ret = smu_v11_0_set_single_dpm_table(smu,
597 SMU_UCLK,
598 dpm_table);
599 if (ret)
600 return ret;
601 dpm_table->is_fine_grained =
602 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
603 } else {
604 dpm_table->count = 1;
605 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
606 dpm_table->dpm_levels[0].enabled = true;
607 dpm_table->min = dpm_table->dpm_levels[0].value;
608 dpm_table->max = dpm_table->dpm_levels[0].value;
609 }
b455159c 610
90a89c31
EQ		 611 /* fclk dpm table setup */
612 dpm_table = &dpm_context->dpm_tables.fclk_table;
b4bb3aaf 613 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
90a89c31
EQ		 614 ret = smu_v11_0_set_single_dpm_table(smu,
615 SMU_FCLK,
616 dpm_table);
617 if (ret)
618 return ret;
619 dpm_table->is_fine_grained =
620 !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
621 } else {
622 dpm_table->count = 1;
623 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
624 dpm_table->dpm_levels[0].enabled = true;
625 dpm_table->min = dpm_table->dpm_levels[0].value;
626 dpm_table->max = dpm_table->dpm_levels[0].value;
627 }
b455159c 628
90a89c31
EQ		 629 /* vclk0 dpm table setup */
630 dpm_table = &dpm_context->dpm_tables.vclk_table;
b4bb3aaf 631 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
90a89c31
EQ		 632 ret = smu_v11_0_set_single_dpm_table(smu,
633 SMU_VCLK,
634 dpm_table);
635 if (ret)
636 return ret;
637 dpm_table->is_fine_grained =
638 !driver_ppt->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete;
639 } else {
640 dpm_table->count = 1;
641 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
642 dpm_table->dpm_levels[0].enabled = true;
643 dpm_table->min = dpm_table->dpm_levels[0].value;
644 dpm_table->max = dpm_table->dpm_levels[0].value;
645 }
b455159c 646
90a89c31 647 /* vclk1 dpm table setup */
85dec717
JC		 648 if (adev->vcn.num_vcn_inst > 1) {
649 dpm_table = &dpm_context->dpm_tables.vclk1_table;
650 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
651 ret = smu_v11_0_set_single_dpm_table(smu,
652 SMU_VCLK1,
653 dpm_table);
654 if (ret)
655 return ret;
656 dpm_table->is_fine_grained =
657 !driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete;
658 } else {
659 dpm_table->count = 1;
660 dpm_table->dpm_levels[0].value =
661 smu->smu_table.boot_values.vclk / 100;
662 dpm_table->dpm_levels[0].enabled = true;
663 dpm_table->min = dpm_table->dpm_levels[0].value;
664 dpm_table->max = dpm_table->dpm_levels[0].value;
665 }
90a89c31 666 }
b455159c 667
90a89c31
EQ		 668 /* dclk0 dpm table setup */
669 dpm_table = &dpm_context->dpm_tables.dclk_table;
b4bb3aaf 670 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
90a89c31
EQ		 671 ret = smu_v11_0_set_single_dpm_table(smu,
672 SMU_DCLK,
673 dpm_table);
674 if (ret)
675 return ret;
676 dpm_table->is_fine_grained =
677 !driver_ppt->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete;
678 } else {
679 dpm_table->count = 1;
680 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
681 dpm_table->dpm_levels[0].enabled = true;
682 dpm_table->min = dpm_table->dpm_levels[0].value;
683 dpm_table->max = dpm_table->dpm_levels[0].value;
684 }
685
686 /* dclk1 dpm table setup */
85dec717
JC		 687 if (adev->vcn.num_vcn_inst > 1) {
688 dpm_table = &dpm_context->dpm_tables.dclk1_table;
689 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
690 ret = smu_v11_0_set_single_dpm_table(smu,
691 SMU_DCLK1,
692 dpm_table);
693 if (ret)
694 return ret;
695 dpm_table->is_fine_grained =
696 !driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete;
697 } else {
698 dpm_table->count = 1;
699 dpm_table->dpm_levels[0].value =
700 smu->smu_table.boot_values.dclk / 100;
701 dpm_table->dpm_levels[0].enabled = true;
702 dpm_table->min = dpm_table->dpm_levels[0].value;
703 dpm_table->max = dpm_table->dpm_levels[0].value;
704 }
90a89c31
EQ		 705 }
706
707 /* dcefclk dpm table setup */
708 dpm_table = &dpm_context->dpm_tables.dcef_table;
b4bb3aaf 709 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 710 ret = smu_v11_0_set_single_dpm_table(smu,
711 SMU_DCEFCLK,
712 dpm_table);
713 if (ret)
714 return ret;
715 dpm_table->is_fine_grained =
716 !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
717 } else {
718 dpm_table->count = 1;
719 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
720 dpm_table->dpm_levels[0].enabled = true;
721 dpm_table->min = dpm_table->dpm_levels[0].value;
722 dpm_table->max = dpm_table->dpm_levels[0].value;
723 }
b455159c 724
90a89c31
EQ		 725 /* pixelclk dpm table setup */
726 dpm_table = &dpm_context->dpm_tables.pixel_table;
b4bb3aaf 727 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 728 ret = smu_v11_0_set_single_dpm_table(smu,
729 SMU_PIXCLK,
730 dpm_table);
731 if (ret)
732 return ret;
733 dpm_table->is_fine_grained =
734 !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
735 } else {
736 dpm_table->count = 1;
737 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
738 dpm_table->dpm_levels[0].enabled = true;
739 dpm_table->min = dpm_table->dpm_levels[0].value;
740 dpm_table->max = dpm_table->dpm_levels[0].value;
741 }
b455159c 742
90a89c31
EQ		 743 /* displayclk dpm table setup */
744 dpm_table = &dpm_context->dpm_tables.display_table;
b4bb3aaf 745 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 746 ret = smu_v11_0_set_single_dpm_table(smu,
747 SMU_DISPCLK,
748 dpm_table);
749 if (ret)
750 return ret;
751 dpm_table->is_fine_grained =
752 !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
753 } else {
754 dpm_table->count = 1;
755 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
756 dpm_table->dpm_levels[0].enabled = true;
757 dpm_table->min = dpm_table->dpm_levels[0].value;
758 dpm_table->max = dpm_table->dpm_levels[0].value;
759 }
b455159c 760
90a89c31
EQ		 761 /* phyclk dpm table setup */
762 dpm_table = &dpm_context->dpm_tables.phy_table;
b4bb3aaf 763 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 764 ret = smu_v11_0_set_single_dpm_table(smu,
765 SMU_PHYCLK,
766 dpm_table);
767 if (ret)
768 return ret;
769 dpm_table->is_fine_grained =
770 !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
771 } else {
772 dpm_table->count = 1;
773 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
774 dpm_table->dpm_levels[0].enabled = true;
775 dpm_table->min = dpm_table->dpm_levels[0].value;
776 dpm_table->max = dpm_table->dpm_levels[0].value;
777 }
b455159c
LG		 778
779 return 0;
780}
781
f6b4b4a1 782static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
b455159c 783{
d51dc613 784 struct amdgpu_device *adev = smu->adev;
b455159c
LG		 785 int ret = 0;
786
787 if (enable) {
788 /* vcn dpm on is a prerequisite for vcn power gate messages */
b4bb3aaf 789 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 790 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
6fb176a7
LG		 791 if (ret)
792 return ret;
6ec46653 793 if (adev->vcn.num_vcn_inst > 1) {
66c86828 794 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
d51dc613
JC		 795 0x10000, NULL);
796 if (ret)
797 return ret;
798 }
b455159c 799 }
b455159c 800 } else {
b4bb3aaf 801 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 802 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
6fb176a7
LG		 803 if (ret)
804 return ret;
6ec46653 805 if (adev->vcn.num_vcn_inst > 1) {
66c86828 806 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
d51dc613
JC		 807 0x10000, NULL);
808 if (ret)
809 return ret;
810 }
b455159c 811 }
b455159c
LG		 812 }
813
814 return ret;
815}
816
6fb176a7
LG		 817static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
818{
6fb176a7
LG		 819 int ret = 0;
820
821 if (enable) {
b4bb3aaf 822 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 823 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
6fb176a7
LG		 824 if (ret)
825 return ret;
6fb176a7 826 }
6fb176a7 827 } else {
b4bb3aaf 828 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 829 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
6fb176a7
LG		 830 if (ret)
831 return ret;
6fb176a7 832 }
6fb176a7
LG		 833 }
834
835 return ret;
836}
837
b455159c
LG		 838static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
839 enum smu_clk_type clk_type,
840 uint32_t *value)
841{
8c686254
EQ		 842 MetricsMember_t member_type;
843 int clk_id = 0;
b455159c 844
6c339f37
EQ		 845 clk_id = smu_cmn_to_asic_specific_index(smu,
846 CMN2ASIC_MAPPING_CLK,
847 clk_type);
b455159c
LG		 848 if (clk_id < 0)
849 return clk_id;
850
8c686254
EQ		 851 switch (clk_id) {
852 case PPCLK_GFXCLK:
853 member_type = METRICS_CURR_GFXCLK;
854 break;
855 case PPCLK_UCLK:
856 member_type = METRICS_CURR_UCLK;
857 break;
858 case PPCLK_SOCCLK:
859 member_type = METRICS_CURR_SOCCLK;
860 break;
861 case PPCLK_FCLK:
862 member_type = METRICS_CURR_FCLK;
863 break;
864 case PPCLK_VCLK_0:
865 member_type = METRICS_CURR_VCLK;
866 break;
867 case PPCLK_VCLK_1:
868 member_type = METRICS_CURR_VCLK1;
869 break;
870 case PPCLK_DCLK_0:
871 member_type = METRICS_CURR_DCLK;
872 break;
873 case PPCLK_DCLK_1:
874 member_type = METRICS_CURR_DCLK1;
875 break;
876 case PPCLK_DCEFCLK:
877 member_type = METRICS_CURR_DCEFCLK;
878 break;
879 default:
880 return -EINVAL;
881 }
882
883 return sienna_cichlid_get_smu_metrics_data(smu,
884 member_type,
885 value);
b455159c 886
b455159c
LG		 887}
888
889static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
890{
891 PPTable_t *pptable = smu->smu_table.driver_pptable;
892 DpmDescriptor_t *dpm_desc = NULL;
893 uint32_t clk_index = 0;
894
6c339f37
EQ		 895 clk_index = smu_cmn_to_asic_specific_index(smu,
896 CMN2ASIC_MAPPING_CLK,
897 clk_type);
b455159c
LG		 898 dpm_desc = &pptable->DpmDescriptor[clk_index];
899
900 /* 0 - Fine grained DPM, 1 - Discrete DPM */
901 return dpm_desc->SnapToDiscrete == 0 ? true : false;
902}
903
904static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
905 enum smu_clk_type clk_type, char *buf)
906{
b7d25b5f
LG		 907 struct amdgpu_device *adev = smu->adev;
908 struct smu_table_context *table_context = &smu->smu_table;
909 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
910 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
911 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
b455159c
LG		 912 int i, size = 0, ret = 0;
913 uint32_t cur_value = 0, value = 0, count = 0;
914 uint32_t freq_values[3] = {0};
915 uint32_t mark_index = 0;
b7d25b5f 916 uint32_t gen_speed, lane_width;
b455159c
LG		 917
918 switch (clk_type) {
919 case SMU_GFXCLK:
920 case SMU_SCLK:
921 case SMU_SOCCLK:
922 case SMU_MCLK:
923 case SMU_UCLK:
924 case SMU_FCLK:
925 case SMU_DCEFCLK:
5e6dc8fe 926 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
b455159c 927 if (ret)
258d290c 928 goto print_clk_out;
b455159c 929
ba818620
KF		 930 /* no need to disable gfxoff when retrieving the current gfxclk */
931 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
932 amdgpu_gfx_off_ctrl(adev, false);
933
d8d3493a 934 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
b455159c 935 if (ret)
258d290c 936 goto print_clk_out;
b455159c
LG		 937
938 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
939 for (i = 0; i < count; i++) {
d8d3493a 940 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
b455159c 941 if (ret)
258d290c 942 goto print_clk_out;
b455159c
LG		 943
944 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
945 cur_value == value ? "*" : "");
946 }
947 } else {
d8d3493a 948 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
b455159c 949 if (ret)
258d290c 950 goto print_clk_out;
d8d3493a 951 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
b455159c 952 if (ret)
258d290c 953 goto print_clk_out;
b455159c
LG		 954
955 freq_values[1] = cur_value;
956 mark_index = cur_value == freq_values[0] ? 0 :
957 cur_value == freq_values[2] ? 2 : 1;
b455159c 958
891bacb8
KF		 959 count = 3;
960 if (mark_index != 1) {
961 count = 2;
962 freq_values[1] = freq_values[2];
963 }
964
965 for (i = 0; i < count; i++) {
b455159c 966 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
891bacb8 967 cur_value == freq_values[i] ? "*" : "");
b455159c
LG		 968 }
969
970 }
971 break;
b7d25b5f 972 case SMU_PCIE:
f20c52f4
LG		 973 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
974 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
b7d25b5f
LG		 975 for (i = 0; i < NUM_LINK_LEVELS; i++)
976 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
977 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
978 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
979 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
980 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
981 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
982 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
983 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
984 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
985 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
986 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
987 pptable->LclkFreq[i],
988 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
989 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
990 "*" : "");
991 break;
b455159c
LG		 992 default:
993 break;
994 }
995
258d290c
LG		 996print_clk_out:
997 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
998 amdgpu_gfx_off_ctrl(adev, true);
999
b455159c
LG		 1000 return size;
1001}
1002
1003static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1004 enum smu_clk_type clk_type, uint32_t mask)
1005{
258d290c 1006 struct amdgpu_device *adev = smu->adev;
b455159c
LG		 1007 int ret = 0, size = 0;
1008 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1009
1010 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1011 soft_max_level = mask ? (fls(mask) - 1) : 0;
1012
258d290c
LG		 1013 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1014 amdgpu_gfx_off_ctrl(adev, false);
1015
b455159c
LG		 1016 switch (clk_type) {
1017 case SMU_GFXCLK:
1018 case SMU_SCLK:
1019 case SMU_SOCCLK:
1020 case SMU_MCLK:
1021 case SMU_UCLK:
1022 case SMU_DCEFCLK:
1023 case SMU_FCLK:
9ad9c8ac
LG		 1024 /* There is only 2 levels for fine grained DPM */
1025 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1026 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1027 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1028 }
1029
d8d3493a 1030 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
b455159c 1031 if (ret)
258d290c 1032 goto forec_level_out;
b455159c 1033
d8d3493a 1034 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
b455159c 1035 if (ret)
258d290c 1036 goto forec_level_out;
b455159c 1037
10e96d89 1038 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
b455159c 1039 if (ret)
258d290c 1040 goto forec_level_out;
b455159c
LG		 1041 break;
1042 default:
1043 break;
1044 }
1045
258d290c
LG		 1046forec_level_out:
1047 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1048 amdgpu_gfx_off_ctrl(adev, true);
1049
b455159c
LG		 1050 return size;
1051}
1052
1053static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1054{
62cc9dd1
EQ		 1055 struct smu_11_0_dpm_context *dpm_context =
1056 smu->smu_dpm.dpm_context;
1057 struct smu_11_0_dpm_table *gfx_table =
1058 &dpm_context->dpm_tables.gfx_table;
1059 struct smu_11_0_dpm_table *mem_table =
1060 &dpm_context->dpm_tables.uclk_table;
1061 struct smu_11_0_dpm_table *soc_table =
1062 &dpm_context->dpm_tables.soc_table;
1063 struct smu_umd_pstate_table *pstate_table =
1064 &smu->pstate_table;
1065
1066 pstate_table->gfxclk_pstate.min = gfx_table->min;
1067 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1068
1069 pstate_table->uclk_pstate.min = mem_table->min;
1070 pstate_table->uclk_pstate.peak = mem_table->max;
1071
1072 pstate_table->socclk_pstate.min = soc_table->min;
1073 pstate_table->socclk_pstate.peak = soc_table->max;
b455159c 1074
62cc9dd1 1075 return 0;
b455159c
LG		 1076}
1077
b455159c
LG		 1078static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1079{
1080 int ret = 0;
1081 uint32_t max_freq = 0;
1082
1083 /* Sienna_Cichlid do not support to change display num currently */
1084 return 0;
1085#if 0
66c86828 1086 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
b455159c
LG		 1087 if (ret)
1088 return ret;
1089#endif
1090
b4bb3aaf 1091 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
e5ef784b 1092 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
b455159c
LG		 1093 if (ret)
1094 return ret;
661b94f5 1095 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
b455159c
LG		 1096 if (ret)
1097 return ret;
1098 }
1099
1100 return ret;
1101}
1102
1103static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1104{
1105 int ret = 0;
1106
b455159c 1107 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
4d942ae3
EQ		 1108 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1109 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
b455159c 1110#if 0
66c86828 1111 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
40d3b8db
LG		 1112 smu->display_config->num_display,
1113 NULL);
b455159c
LG		 1114#endif
1115 if (ret)
1116 return ret;
1117 }
1118
1119 return ret;
1120}
1121
b455159c
LG		 1122static int sienna_cichlid_get_gpu_power(struct smu_context *smu, uint32_t *value)
1123{
b455159c
LG		 1124 if (!value)
1125 return -EINVAL;
1126
8c686254
EQ		 1127 return sienna_cichlid_get_smu_metrics_data(smu,
1128 METRICS_AVERAGE_SOCKETPOWER,
1129 value);
b455159c
LG		 1130}
1131
1132static int sienna_cichlid_get_current_activity_percent(struct smu_context *smu,
1133 enum amd_pp_sensors sensor,
1134 uint32_t *value)
1135{
1136 int ret = 0;
b455159c
LG		 1137
1138 if (!value)
1139 return -EINVAL;
1140
b455159c
LG		 1141 switch (sensor) {
1142 case AMDGPU_PP_SENSOR_GPU_LOAD:
8c686254
EQ		 1143 ret = sienna_cichlid_get_smu_metrics_data(smu,
1144 METRICS_AVERAGE_GFXACTIVITY,
1145 value);
b455159c
LG		 1146 break;
1147 case AMDGPU_PP_SENSOR_MEM_LOAD:
8c686254
EQ		 1148 ret = sienna_cichlid_get_smu_metrics_data(smu,
1149 METRICS_AVERAGE_MEMACTIVITY,
1150 value);
b455159c
LG		 1151 break;
1152 default:
d9811cfc 1153 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
b455159c
LG		 1154 return -EINVAL;
1155 }
1156
8c686254 1157 return ret;
b455159c
LG		 1158}
1159
1160static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1161{
1162 int ret = 0;
1163 uint32_t feature_mask[2];
3d14a79b
KW		 1164 uint64_t feature_enabled;
1165
28251d72 1166 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
3d14a79b
KW		 1167 if (ret)
1168 return false;
1169
1170 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1171
b455159c
LG		 1172 return !!(feature_enabled & SMC_DPM_FEATURE);
1173}
1174
1175static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1176 uint32_t *speed)
1177{
b455159c
LG		 1178 if (!speed)
1179 return -EINVAL;
1180
1eeb03c8
KF		 1181 return sienna_cichlid_get_smu_metrics_data(smu,
1182 METRICS_CURR_FANSPEED,
1183 speed);
b455159c
LG		 1184}
1185
3204ff3e
AD		 1186static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1187{
1188 PPTable_t *pptable = smu->smu_table.driver_pptable;
1189
1190 smu->fan_max_rpm = pptable->FanMaximumRpm;
1191
1192 return 0;
1193}
1194
b455159c
LG		 1195static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1196{
1197 DpmActivityMonitorCoeffInt_t activity_monitor;
1198 uint32_t i, size = 0;
1199 int16_t workload_type = 0;
1200 static const char *profile_name[] = {
1201 "BOOTUP_DEFAULT",
1202 "3D_FULL_SCREEN",
1203 "POWER_SAVING",
1204 "VIDEO",
1205 "VR",
1206 "COMPUTE",
1207 "CUSTOM"};
1208 static const char *title[] = {
1209 "PROFILE_INDEX(NAME)",
1210 "CLOCK_TYPE(NAME)",
1211 "FPS",
1212 "MinFreqType",
1213 "MinActiveFreqType",
1214 "MinActiveFreq",
1215 "BoosterFreqType",
1216 "BoosterFreq",
1217 "PD_Data_limit_c",
1218 "PD_Data_error_coeff",
1219 "PD_Data_error_rate_coeff"};
1220 int result = 0;
1221
1222 if (!buf)
1223 return -EINVAL;
1224
1225 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1226 title[0], title[1], title[2], title[3], title[4], title[5],
1227 title[6], title[7], title[8], title[9], title[10]);
1228
1229 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1230 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
6c339f37
EQ		 1231 workload_type = smu_cmn_to_asic_specific_index(smu,
1232 CMN2ASIC_MAPPING_WORKLOAD,
1233 i);
b455159c
LG		 1234 if (workload_type < 0)
1235 return -EINVAL;
1236
caad2613 1237 result = smu_cmn_update_table(smu,
b455159c
LG		 1238 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1239 (void *)(&activity_monitor), false);
1240 if (result) {
d9811cfc 1241 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
b455159c
LG		 1242 return result;
1243 }
1244
1245 size += sprintf(buf + size, "%2d %14s%s:\n",
1246 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1247
1248 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1249 " ",
1250 0,
1251 "GFXCLK",
1252 activity_monitor.Gfx_FPS,
1253 activity_monitor.Gfx_MinFreqStep,
1254 activity_monitor.Gfx_MinActiveFreqType,
1255 activity_monitor.Gfx_MinActiveFreq,
1256 activity_monitor.Gfx_BoosterFreqType,
1257 activity_monitor.Gfx_BoosterFreq,
1258 activity_monitor.Gfx_PD_Data_limit_c,
1259 activity_monitor.Gfx_PD_Data_error_coeff,
1260 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1261
1262 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1263 " ",
1264 1,
1265 "SOCCLK",
1266 activity_monitor.Fclk_FPS,
1267 activity_monitor.Fclk_MinFreqStep,
1268 activity_monitor.Fclk_MinActiveFreqType,
1269 activity_monitor.Fclk_MinActiveFreq,
1270 activity_monitor.Fclk_BoosterFreqType,
1271 activity_monitor.Fclk_BoosterFreq,
1272 activity_monitor.Fclk_PD_Data_limit_c,
1273 activity_monitor.Fclk_PD_Data_error_coeff,
1274 activity_monitor.Fclk_PD_Data_error_rate_coeff);
1275
1276 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1277 " ",
1278 2,
1279 "MEMLK",
1280 activity_monitor.Mem_FPS,
1281 activity_monitor.Mem_MinFreqStep,
1282 activity_monitor.Mem_MinActiveFreqType,
1283 activity_monitor.Mem_MinActiveFreq,
1284 activity_monitor.Mem_BoosterFreqType,
1285 activity_monitor.Mem_BoosterFreq,
1286 activity_monitor.Mem_PD_Data_limit_c,
1287 activity_monitor.Mem_PD_Data_error_coeff,
1288 activity_monitor.Mem_PD_Data_error_rate_coeff);
1289 }
1290
1291 return size;
1292}
1293
1294static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1295{
1296 DpmActivityMonitorCoeffInt_t activity_monitor;
1297 int workload_type, ret = 0;
1298
1299 smu->power_profile_mode = input[size];
1300
1301 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
d9811cfc 1302 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
b455159c
LG		 1303 return -EINVAL;
1304 }
1305
1306 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
b455159c 1307
caad2613 1308 ret = smu_cmn_update_table(smu,
b455159c
LG		 1309 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1310 (void *)(&activity_monitor), false);
1311 if (ret) {
d9811cfc 1312 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
b455159c
LG		 1313 return ret;
1314 }
1315
1316 switch (input[0]) {
1317 case 0: /* Gfxclk */
1318 activity_monitor.Gfx_FPS = input[1];
1319 activity_monitor.Gfx_MinFreqStep = input[2];
1320 activity_monitor.Gfx_MinActiveFreqType = input[3];
1321 activity_monitor.Gfx_MinActiveFreq = input[4];
1322 activity_monitor.Gfx_BoosterFreqType = input[5];
1323 activity_monitor.Gfx_BoosterFreq = input[6];
1324 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1325 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1326 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1327 break;
1328 case 1: /* Socclk */
1329 activity_monitor.Fclk_FPS = input[1];
1330 activity_monitor.Fclk_MinFreqStep = input[2];
1331 activity_monitor.Fclk_MinActiveFreqType = input[3];
1332 activity_monitor.Fclk_MinActiveFreq = input[4];
1333 activity_monitor.Fclk_BoosterFreqType = input[5];
1334 activity_monitor.Fclk_BoosterFreq = input[6];
1335 activity_monitor.Fclk_PD_Data_limit_c = input[7];
1336 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1337 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1338 break;
1339 case 2: /* Memlk */
1340 activity_monitor.Mem_FPS = input[1];
1341 activity_monitor.Mem_MinFreqStep = input[2];
1342 activity_monitor.Mem_MinActiveFreqType = input[3];
1343 activity_monitor.Mem_MinActiveFreq = input[4];
1344 activity_monitor.Mem_BoosterFreqType = input[5];
1345 activity_monitor.Mem_BoosterFreq = input[6];
1346 activity_monitor.Mem_PD_Data_limit_c = input[7];
1347 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1348 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1349 break;
1350 }
1351
caad2613 1352 ret = smu_cmn_update_table(smu,
b455159c
LG		 1353 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1354 (void *)(&activity_monitor), true);
1355 if (ret) {
d9811cfc 1356 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
b455159c
LG		 1357 return ret;
1358 }
1359 }
1360
1361 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
6c339f37
EQ		 1362 workload_type = smu_cmn_to_asic_specific_index(smu,
1363 CMN2ASIC_MAPPING_WORKLOAD,
1364 smu->power_profile_mode);
b455159c
LG		 1365 if (workload_type < 0)
1366 return -EINVAL;
66c86828 1367 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
b455159c
LG		 1368 1 << workload_type, NULL);
1369
1370 return ret;
1371}
1372
b455159c
LG		 1373static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1374{
1375 struct smu_clocks min_clocks = {0};
1376 struct pp_display_clock_request clock_req;
1377 int ret = 0;
1378
1379 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1380 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1381 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1382
4d942ae3 1383 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
b455159c
LG		 1384 clock_req.clock_type = amd_pp_dcef_clock;
1385 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1386
1387 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1388 if (!ret) {
4d942ae3 1389 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
66c86828 1390 ret = smu_cmn_send_smc_msg_with_param(smu,
40d3b8db
LG		 1391 SMU_MSG_SetMinDeepSleepDcefclk,
1392 min_clocks.dcef_clock_in_sr/100,
1393 NULL);
1394 if (ret) {
d9811cfc 1395 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
40d3b8db
LG		 1396 return ret;
1397 }
b455159c
LG		 1398 }
1399 } else {
d9811cfc 1400 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
b455159c
LG		 1401 }
1402 }
1403
b4bb3aaf 1404 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
661b94f5 1405 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
b455159c 1406 if (ret) {
d9811cfc 1407 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
b455159c
LG		 1408 return ret;
1409 }
1410 }
1411
1412 return 0;
1413}
1414
1415static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
7b9c7e30 1416 struct pp_smu_wm_range_sets *clock_ranges)
b455159c 1417{
e7a95eea 1418 Watermarks_t *table = smu->smu_table.watermarks_table;
40d3b8db 1419 int ret = 0;
e7a95eea 1420 int i;
b455159c 1421
e7a95eea 1422 if (clock_ranges) {
7b9c7e30
EQ		 1423 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1424 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
e7a95eea
EQ		 1425 return -EINVAL;
1426
7b9c7e30
EQ		 1427 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1428 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1429 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1430 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1431 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1432 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1433 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1434 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1435 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1436
1437 table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1438 clock_ranges->reader_wm_sets[i].wm_inst;
e7a95eea 1439 }
b455159c 1440
7b9c7e30
EQ		 1441 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1442 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1443 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1444 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1445 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1446 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1447 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1448 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1449 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1450
1451 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1452 clock_ranges->writer_wm_sets[i].wm_inst;
e7a95eea
EQ		 1453 }
1454
1455 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1456 }
1457
1458 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1459 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
caad2613 1460 ret = smu_cmn_write_watermarks_table(smu);
40d3b8db 1461 if (ret) {
d9811cfc 1462 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
40d3b8db
LG		 1463 return ret;
1464 }
1465 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1466 }
1467
b455159c
LG		 1468 return 0;
1469}
1470
1471static int sienna_cichlid_thermal_get_temperature(struct smu_context *smu,
1472 enum amd_pp_sensors sensor,
1473 uint32_t *value)
1474{
b455159c
LG		 1475 int ret = 0;
1476
1477 if (!value)
1478 return -EINVAL;
1479
b455159c
LG		 1480 switch (sensor) {
1481 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
8c686254
EQ		 1482 ret = sienna_cichlid_get_smu_metrics_data(smu,
1483 METRICS_TEMPERATURE_HOTSPOT,
1484 value);
b455159c
LG		 1485 break;
1486 case AMDGPU_PP_SENSOR_EDGE_TEMP:
8c686254
EQ		 1487 ret = sienna_cichlid_get_smu_metrics_data(smu,
1488 METRICS_TEMPERATURE_EDGE,
1489 value);
b455159c
LG		 1490 break;
1491 case AMDGPU_PP_SENSOR_MEM_TEMP:
8c686254
EQ		 1492 ret = sienna_cichlid_get_smu_metrics_data(smu,
1493 METRICS_TEMPERATURE_MEM,
1494 value);
b455159c
LG		 1495 break;
1496 default:
d9811cfc 1497 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
b455159c
LG		 1498 return -EINVAL;
1499 }
1500
8c686254 1501 return ret;
b455159c
LG		 1502}
1503
1504static int sienna_cichlid_read_sensor(struct smu_context *smu,
1505 enum amd_pp_sensors sensor,
1506 void *data, uint32_t *size)
1507{
1508 int ret = 0;
1509 struct smu_table_context *table_context = &smu->smu_table;
1510 PPTable_t *pptable = table_context->driver_pptable;
1511
1512 if(!data || !size)
1513 return -EINVAL;
1514
1515 mutex_lock(&smu->sensor_lock);
1516 switch (sensor) {
1517 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1518 *(uint32_t *)data = pptable->FanMaximumRpm;
1519 *size = 4;
1520 break;
1521 case AMDGPU_PP_SENSOR_MEM_LOAD:
1522 case AMDGPU_PP_SENSOR_GPU_LOAD:
1523 ret = sienna_cichlid_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1524 *size = 4;
1525 break;
1526 case AMDGPU_PP_SENSOR_GPU_POWER:
1527 ret = sienna_cichlid_get_gpu_power(smu, (uint32_t *)data);
1528 *size = 4;
1529 break;
1530 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1531 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1532 case AMDGPU_PP_SENSOR_MEM_TEMP:
1533 ret = sienna_cichlid_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1534 *size = 4;
1535 break;
e0f9e936
EQ		 1536 case AMDGPU_PP_SENSOR_GFX_MCLK:
1537 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1538 *(uint32_t *)data *= 100;
1539 *size = 4;
1540 break;
1541 case AMDGPU_PP_SENSOR_GFX_SCLK:
1542 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1543 *(uint32_t *)data *= 100;
1544 *size = 4;
1545 break;
b2febc99
EQ		 1546 case AMDGPU_PP_SENSOR_VDDGFX:
1547 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1548 *size = 4;
1549 break;
b455159c 1550 default:
b2febc99
EQ		 1551 ret = -EOPNOTSUPP;
1552 break;
b455159c
LG		 1553 }
1554 mutex_unlock(&smu->sensor_lock);
1555
1556 return ret;
1557}
1558
1559static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1560{
1561 uint32_t num_discrete_levels = 0;
1562 uint16_t *dpm_levels = NULL;
1563 uint16_t i = 0;
1564 struct smu_table_context *table_context = &smu->smu_table;
1565 PPTable_t *driver_ppt = NULL;
1566
1567 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1568 return -EINVAL;
1569
1570 driver_ppt = table_context->driver_pptable;
1571 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1572 dpm_levels = driver_ppt->FreqTableUclk;
1573
1574 if (num_discrete_levels == 0 || dpm_levels == NULL)
1575 return -EINVAL;
1576
1577 *num_states = num_discrete_levels;
1578 for (i = 0; i < num_discrete_levels; i++) {
1579 /* convert to khz */
1580 *clocks_in_khz = (*dpm_levels) * 1000;
1581 clocks_in_khz++;
1582 dpm_levels++;
1583 }
1584
1585 return 0;
1586}
1587
1588static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1589 struct smu_temperature_range *range)
1590{
e02e4d51
EQ		 1591 struct smu_table_context *table_context = &smu->smu_table;
1592 struct smu_11_0_7_powerplay_table *powerplay_table =
1593 table_context->power_play_table;
2b1f12a2 1594 PPTable_t *pptable = smu->smu_table.driver_pptable;
b455159c 1595
2b1f12a2 1596 if (!range)
b455159c
LG		 1597 return -EINVAL;
1598
0540eced
EQ		 1599 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1600
2b1f12a2
EQ		 1601 range->max = pptable->TemperatureLimit[TEMP_EDGE] *
1602 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1603 range->edge_emergency_max = (pptable->TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
1604 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1605 range->hotspot_crit_max = pptable->TemperatureLimit[TEMP_HOTSPOT] *
1606 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1607 range->hotspot_emergency_max = (pptable->TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
1608 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1609 range->mem_crit_max = pptable->TemperatureLimit[TEMP_MEM] *
1610 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1611 range->mem_emergency_max = (pptable->TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
b455159c 1612 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
e02e4d51 1613 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
b455159c
LG		 1614
1615 return 0;
1616}
1617
1618static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1619 bool disable_memory_clock_switch)
1620{
1621 int ret = 0;
1622 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1623 (struct smu_11_0_max_sustainable_clocks *)
1624 smu->smu_table.max_sustainable_clocks;
1625 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1626 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1627
1628 if(smu->disable_uclk_switch == disable_memory_clock_switch)
1629 return 0;
1630
1631 if(disable_memory_clock_switch)
661b94f5 1632 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
b455159c 1633 else
661b94f5 1634 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
b455159c
LG		 1635
1636 if(!ret)
1637 smu->disable_uclk_switch = disable_memory_clock_switch;
1638
1639 return ret;
1640}
1641
a141b4e3 1642static int sienna_cichlid_get_power_limit(struct smu_context *smu)
b455159c 1643{
1e239fdd
EQ		 1644 struct smu_11_0_7_powerplay_table *powerplay_table =
1645 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
b455159c 1646 PPTable_t *pptable = smu->smu_table.driver_pptable;
1e239fdd
EQ		 1647 uint32_t power_limit, od_percent;
1648
1649 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1650 /* the last hope to figure out the ppt limit */
1651 if (!pptable) {
1652 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1653 return -EINVAL;
b455159c 1654 }
1e239fdd
EQ		 1655 power_limit =
1656 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1657 }
1658 smu->current_power_limit = power_limit;
b455159c 1659
1e239fdd
EQ		 1660 if (smu->od_enabled) {
1661 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
1662
1663 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1664
1665 power_limit *= (100 + od_percent);
1666 power_limit /= 100;
b455159c 1667 }
1e239fdd 1668 smu->max_power_limit = power_limit;
b455159c 1669
b455159c
LG		 1670 return 0;
1671}
1672
08ccfe08
LG		 1673static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1674 uint32_t pcie_gen_cap,
1675 uint32_t pcie_width_cap)
1676{
0b590970 1677 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
08ccfe08 1678 PPTable_t *pptable = smu->smu_table.driver_pptable;
08ccfe08 1679 uint32_t smu_pcie_arg;
0b590970 1680 int ret, i;
08ccfe08 1681
0b590970
EQ		 1682 /* lclk dpm table setup */
1683 for (i = 0; i < MAX_PCIE_CONF; i++) {
1684 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
1685 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
1686 }
08ccfe08
LG		 1687
1688 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1689 smu_pcie_arg = (i << 16) |
1690 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ?
1691 (pptable->PcieGenSpeed[i] << 8) :
1692 (pcie_gen_cap << 8)) |
1693 ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1694 pptable->PcieLaneCount[i] :
1695 pcie_width_cap);
1696
66c86828 1697 ret = smu_cmn_send_smc_msg_with_param(smu,
40d3b8db
LG		 1698 SMU_MSG_OverridePcieParameters,
1699 smu_pcie_arg,
1700 NULL);
1701
08ccfe08
LG		 1702 if (ret)
1703 return ret;
1704
1705 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1706 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1707 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1708 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1709 }
1710
1711 return 0;
1712}
1713
38ed7b09 1714static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
258d290c
LG		 1715 enum smu_clk_type clk_type,
1716 uint32_t *min, uint32_t *max)
1717{
1718 struct amdgpu_device *adev = smu->adev;
1719 int ret;
1720
1721 if (clk_type == SMU_GFXCLK)
1722 amdgpu_gfx_off_ctrl(adev, false);
1723 ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
1724 if (clk_type == SMU_GFXCLK)
1725 amdgpu_gfx_off_ctrl(adev, true);
1726
1727 return ret;
1728}
1729
66b8a9c0
JC		 1730static int sienna_cichlid_run_btc(struct smu_context *smu)
1731{
1732 return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
1733}
1734
40d3b8db
LG		 1735static bool sienna_cichlid_is_baco_supported(struct smu_context *smu)
1736{
1737 struct amdgpu_device *adev = smu->adev;
1738 uint32_t val;
1739
311531f0 1740 if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu)))
40d3b8db
LG		 1741 return false;
1742
1743 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
1744 return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
1745}
1746
ea8139d8
WS		 1747static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
1748{
1749 struct amdgpu_device *adev = smu->adev;
1750 uint32_t val;
1751 u32 smu_version;
1752
1753 /**
1754 * SRIOV env will not support SMU mode1 reset
1755 * PM FW support mode1 reset from 58.26
1756 */
a7bae061 1757 smu_cmn_get_smc_version(smu, NULL, &smu_version);
ea8139d8
WS		 1758 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
1759 return false;
1760
1761 /**
1762 * mode1 reset relies on PSP, so we should check if
1763 * PSP is alive.
1764 */
1765 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
1766 return val != 0x0;
1767}
1768
b455159c
LG		 1769static void sienna_cichlid_dump_pptable(struct smu_context *smu)
1770{
1771 struct smu_table_context *table_context = &smu->smu_table;
1772 PPTable_t *pptable = table_context->driver_pptable;
1773 int i;
1774
d9811cfc 1775 dev_info(smu->adev->dev, "Dumped PPTable:\n");
b455159c 1776
d9811cfc
EQ		 1777 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
1778 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1779 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
b455159c
LG		 1780
1781 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
d9811cfc
EQ		 1782 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
1783 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
1784 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
1785 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
b455159c
LG		 1786 }
1787
1788 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
d9811cfc
EQ		 1789 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
1790 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
b455159c
LG		 1791 }
1792
1793 for (i = 0; i < TEMP_COUNT; i++) {
d9811cfc 1794 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
b455159c
LG		 1795 }
1796
d9811cfc
EQ		 1797 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
1798 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
1799 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
1800 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
1801 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
b455159c 1802
d9811cfc 1803 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
b455159c 1804 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
d9811cfc
EQ		 1805 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
1806 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
b455159c 1807 }
d9811cfc
EQ		 1808 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
1809
1810 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
1811
1812 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
1813 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
1814 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
1815 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
1816
1817 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
1818 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
1819
1820 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
1821 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
1822 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
1823 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
1824
1825 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
1826 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
1827 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
1828 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
1829
1830 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
1831 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
1832
1833 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
1834 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
1835 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
1836 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
1837 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
1838 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
1839 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
1840 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
1841
1842 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
b455159c
LG		 1843 " .VoltageMode = 0x%02x\n"
1844 " .SnapToDiscrete = 0x%02x\n"
1845 " .NumDiscreteLevels = 0x%02x\n"
1846 " .padding = 0x%02x\n"
1847 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1848 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1849 " .SsFmin = 0x%04x\n"
1850 " .Padding_16 = 0x%04x\n",
1851 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1852 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1853 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1854 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
1855 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1856 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1857 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1858 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1859 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1860 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1861 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1862
d9811cfc 1863 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
b455159c
LG		 1864 " .VoltageMode = 0x%02x\n"
1865 " .SnapToDiscrete = 0x%02x\n"
1866 " .NumDiscreteLevels = 0x%02x\n"
1867 " .padding = 0x%02x\n"
1868 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1869 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1870 " .SsFmin = 0x%04x\n"
1871 " .Padding_16 = 0x%04x\n",
1872 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1873 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1874 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1875 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
1876 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1877 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1878 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1879 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1880 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1881 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1882 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1883
d9811cfc 1884 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
b455159c
LG		 1885 " .VoltageMode = 0x%02x\n"
1886 " .SnapToDiscrete = 0x%02x\n"
1887 " .NumDiscreteLevels = 0x%02x\n"
1888 " .padding = 0x%02x\n"
1889 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1890 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1891 " .SsFmin = 0x%04x\n"
1892 " .Padding_16 = 0x%04x\n",
1893 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1894 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1895 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1896 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
1897 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1898 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1899 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1900 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1901 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1902 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1903 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1904
d9811cfc 1905 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
b455159c
LG		 1906 " .VoltageMode = 0x%02x\n"
1907 " .SnapToDiscrete = 0x%02x\n"
1908 " .NumDiscreteLevels = 0x%02x\n"
1909 " .padding = 0x%02x\n"
1910 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1911 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1912 " .SsFmin = 0x%04x\n"
1913 " .Padding_16 = 0x%04x\n",
1914 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1915 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1916 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1917 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
1918 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1919 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1920 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1921 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1922 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1923 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1924 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1925
d9811cfc 1926 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
b455159c
LG		 1927 " .VoltageMode = 0x%02x\n"
1928 " .SnapToDiscrete = 0x%02x\n"
1929 " .NumDiscreteLevels = 0x%02x\n"
1930 " .padding = 0x%02x\n"
1931 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1932 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1933 " .SsFmin = 0x%04x\n"
1934 " .Padding_16 = 0x%04x\n",
1935 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
1936 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
1937 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
1938 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
1939 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
1940 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
1941 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
1942 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
1943 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
1944 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
1945 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
1946
d9811cfc 1947 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
b455159c
LG		 1948 " .VoltageMode = 0x%02x\n"
1949 " .SnapToDiscrete = 0x%02x\n"
1950 " .NumDiscreteLevels = 0x%02x\n"
1951 " .padding = 0x%02x\n"
1952 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1953 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1954 " .SsFmin = 0x%04x\n"
1955 " .Padding_16 = 0x%04x\n",
1956 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
1957 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
1958 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
1959 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
1960 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
1961 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
1962 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
1963 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
1964 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
1965 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
1966 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
1967
d9811cfc 1968 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
b455159c
LG		 1969 " .VoltageMode = 0x%02x\n"
1970 " .SnapToDiscrete = 0x%02x\n"
1971 " .NumDiscreteLevels = 0x%02x\n"
1972 " .padding = 0x%02x\n"
1973 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1974 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1975 " .SsFmin = 0x%04x\n"
1976 " .Padding_16 = 0x%04x\n",
1977 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
1978 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
1979 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
1980 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
1981 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
1982 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
1983 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
1984 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
1985 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
1986 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
1987 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
1988
d9811cfc 1989 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
b455159c
LG		 1990 " .VoltageMode = 0x%02x\n"
1991 " .SnapToDiscrete = 0x%02x\n"
1992 " .NumDiscreteLevels = 0x%02x\n"
1993 " .padding = 0x%02x\n"
1994 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1995 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1996 " .SsFmin = 0x%04x\n"
1997 " .Padding_16 = 0x%04x\n",
1998 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
1999 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2000 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2001 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2002 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2003 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2004 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2005 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2006 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2007 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2008 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2009
d9811cfc 2010 dev_info(smu->adev->dev, "FreqTableGfx\n");
b455159c 2011 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
d9811cfc 2012 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
b455159c 2013
d9811cfc 2014 dev_info(smu->adev->dev, "FreqTableVclk\n");
b455159c 2015 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
d9811cfc 2016 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
b455159c 2017
d9811cfc 2018 dev_info(smu->adev->dev, "FreqTableDclk\n");
b455159c 2019 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
d9811cfc 2020 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
b455159c 2021
d9811cfc 2022 dev_info(smu->adev->dev, "FreqTableSocclk\n");
b455159c 2023 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
d9811cfc 2024 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
b455159c 2025
d9811cfc 2026 dev_info(smu->adev->dev, "FreqTableUclk\n");
b455159c 2027 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 2028 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
b455159c 2029
d9811cfc 2030 dev_info(smu->adev->dev, "FreqTableFclk\n");
b455159c 2031 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
d9811cfc
EQ		 2032 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2033
d9811cfc
EQ		 2034 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2035 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2036 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2037 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2038 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2039 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2040 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2041 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2042 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2043
2044 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
b455159c 2045 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 2046 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
b455159c 2047
d9811cfc
EQ		 2048 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2049 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
b455159c 2050
d9811cfc 2051 dev_info(smu->adev->dev, "Mp0clkFreq\n");
b455159c 2052 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc 2053 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
b455159c 2054
d9811cfc 2055 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
b455159c 2056 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc 2057 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
b455159c 2058
d9811cfc 2059 dev_info(smu->adev->dev, "MemVddciVoltage\n");
b455159c 2060 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 2061 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
b455159c 2062
d9811cfc 2063 dev_info(smu->adev->dev, "MemMvddVoltage\n");
b455159c 2064 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc
EQ		 2065 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2066
2067 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2068 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2069 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2070 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2071 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2072
2073 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2074
2075 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2076 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2077 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2078 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2079 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2080 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2081 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2082 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2083 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2084 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2085 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2086
2087 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2088 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2089 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2090 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2091 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2092 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2093
2094 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2095 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2096 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2097 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2098 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2099
2100 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
b455159c 2101 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
d9811cfc 2102 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
b455159c 2103
d9811cfc
EQ		 2104 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2105 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2106 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2107 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
b455159c 2108
d9811cfc 2109 dev_info(smu->adev->dev, "UclkDpmPstates\n");
b455159c 2110 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 2111 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
b455159c 2112
d9811cfc
EQ		 2113 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2114 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
b455159c 2115 pptable->UclkDpmSrcFreqRange.Fmin);
d9811cfc 2116 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
b455159c 2117 pptable->UclkDpmSrcFreqRange.Fmax);
d9811cfc
EQ		 2118 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2119 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
b455159c 2120 pptable->UclkDpmTargFreqRange.Fmin);
d9811cfc 2121 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
b455159c 2122 pptable->UclkDpmTargFreqRange.Fmax);
d9811cfc
EQ		 2123 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2124 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
b455159c 2125
d9811cfc 2126 dev_info(smu->adev->dev, "PcieGenSpeed\n");
b455159c 2127 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 2128 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
b455159c 2129
d9811cfc 2130 dev_info(smu->adev->dev, "PcieLaneCount\n");
b455159c 2131 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 2132 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
b455159c 2133
d9811cfc 2134 dev_info(smu->adev->dev, "LclkFreq\n");
b455159c 2135 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 2136 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
b455159c 2137
d9811cfc
EQ		 2138 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2139 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
b455159c 2140
d9811cfc 2141 dev_info(smu->adev->dev, "FanGain\n");
b455159c 2142 for (i = 0; i < TEMP_COUNT; i++)
d9811cfc
EQ		 2143 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2144
2145 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2146 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2147 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2148 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2149 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2150 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2151 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2152 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2153 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2154 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2155 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2156 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2157
2158 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2159 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2160 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2161 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2162
2163 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2164 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2165 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2166 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2167
2168 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2169 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2170 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2171 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
d9811cfc 2172 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2173 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2174 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2175 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
d9811cfc 2176 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2177 pptable->dBtcGbGfxPll.a,
2178 pptable->dBtcGbGfxPll.b,
2179 pptable->dBtcGbGfxPll.c);
d9811cfc 2180 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2181 pptable->dBtcGbGfxDfll.a,
2182 pptable->dBtcGbGfxDfll.b,
2183 pptable->dBtcGbGfxDfll.c);
d9811cfc 2184 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2185 pptable->dBtcGbSoc.a,
2186 pptable->dBtcGbSoc.b,
2187 pptable->dBtcGbSoc.c);
d9811cfc 2188 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
b455159c
LG		 2189 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2190 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
d9811cfc 2191 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
b455159c
LG		 2192 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2193 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2194
d9811cfc 2195 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
b455159c 2196 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
d9811cfc 2197 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
b455159c 2198 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
d9811cfc 2199 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
b455159c
LG		 2200 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2201 }
2202
d9811cfc 2203 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2204 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2205 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2206 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
d9811cfc 2207 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2208 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2209 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2210 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2211
d9811cfc
EQ		 2212 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2213 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
b455159c 2214
d9811cfc
EQ		 2215 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2216 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2217 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2218 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
b455159c 2219
d9811cfc
EQ		 2220 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2221 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2222 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2223 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
b455159c 2224
d9811cfc
EQ		 2225 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2226 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
b455159c 2227
d9811cfc 2228 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
b455159c 2229 for (i = 0; i < NUM_XGMI_LEVELS; i++)
d9811cfc
EQ		 2230 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2231 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2232 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
b455159c 2233
d9811cfc
EQ		 2234 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2235 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2236 pptable->ReservedEquation0.a,
2237 pptable->ReservedEquation0.b,
2238 pptable->ReservedEquation0.c);
d9811cfc 2239 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2240 pptable->ReservedEquation1.a,
2241 pptable->ReservedEquation1.b,
2242 pptable->ReservedEquation1.c);
d9811cfc 2243 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2244 pptable->ReservedEquation2.a,
2245 pptable->ReservedEquation2.b,
2246 pptable->ReservedEquation2.c);
d9811cfc 2247 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 2248 pptable->ReservedEquation3.a,
2249 pptable->ReservedEquation3.b,
2250 pptable->ReservedEquation3.c);
2251
d9811cfc
EQ		 2252 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2253 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2254 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2255 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2256 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2257 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2258 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2259 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
d9811cfc
EQ		 2260
2261 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2262 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2263 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2264 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2265 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2266 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
b455159c
LG		 2267
2268 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
d9811cfc
EQ		 2269 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2270 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
b455159c 2271 pptable->I2cControllers[i].Enabled);
d9811cfc 2272 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
b455159c 2273 pptable->I2cControllers[i].Speed);
d9811cfc 2274 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
b455159c 2275 pptable->I2cControllers[i].SlaveAddress);
d9811cfc 2276 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
b455159c 2277 pptable->I2cControllers[i].ControllerPort);
d9811cfc 2278 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
b455159c 2279 pptable->I2cControllers[i].ControllerName);
d9811cfc 2280 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
b455159c 2281 pptable->I2cControllers[i].ThermalThrotter);
d9811cfc 2282 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
b455159c 2283 pptable->I2cControllers[i].I2cProtocol);
d9811cfc 2284 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
b455159c
LG		 2285 pptable->I2cControllers[i].PaddingConfig);
2286 }
2287
d9811cfc
EQ		 2288 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2289 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2290 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2291 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2292
2293 dev_info(smu->adev->dev, "Board Parameters:\n");
2294 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2295 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2296 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2297 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2298 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2299 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2300 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2301 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2302
2303 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2304 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2305 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2306
2307 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2308 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2309 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2310
2311 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2312 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2313 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2314
2315 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2316 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2317 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2318
2319 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2320
2321 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2322 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2323 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2324 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2325 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2326 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2327 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2328 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2329 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2330 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2331 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2332 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2333 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2334 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2335 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2336 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2337
2338 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2339 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2340 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
2341
2342 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2343 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2344 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
2345
f0f3d68e 2346 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
d9811cfc
EQ		 2347 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2348
2349 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2350 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2351 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2352
2353 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2354 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2355 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2356 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2357 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2358
2359 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2360 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2361
2362 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
b455159c 2363 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 2364 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2365 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
b455159c 2366 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 2367 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2368 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
b455159c 2369 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 2370 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2371 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
b455159c 2372 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 2373 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2374
2375 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2376 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2377 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2378 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2379
2380 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2381 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2382 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2383 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2384 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2385 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2386 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2387 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2388 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2389 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2390 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
d9811cfc
EQ		 2391
2392 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2393 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2394 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2395 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2396 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2397 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2398 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2399 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
b455159c
LG		 2400}
2401
bc50ca29
AD		 2402static void sienna_cichlid_fill_i2c_req(SwI2cRequest_t *req, bool write,
2403 uint8_t address, uint32_t numbytes,
2404 uint8_t *data)
2405{
2406 int i;
2407
bc50ca29
AD		 2408 req->I2CcontrollerPort = 0;
2409 req->I2CSpeed = 2;
2410 req->SlaveAddress = address;
2411 req->NumCmds = numbytes;
2412
2413 for (i = 0; i < numbytes; i++) {
2414 SwI2cCmd_t *cmd = &req->SwI2cCmds[i];
2415
2416 /* First 2 bytes are always write for lower 2b EEPROM address */
2417 if (i < 2)
2418 cmd->CmdConfig = CMDCONFIG_READWRITE_MASK;
2419 else
2420 cmd->CmdConfig = write ? CMDCONFIG_READWRITE_MASK : 0;
2421
2422
2423 /* Add RESTART for read after address filled */
2424 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
2425
2426 /* Add STOP in the end */
2427 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
2428
2429 /* Fill with data regardless if read or write to simplify code */
2430 cmd->ReadWriteData = data[i];
2431 }
2432}
2433
2434static int sienna_cichlid_i2c_read_data(struct i2c_adapter *control,
2435 uint8_t address,
2436 uint8_t *data,
2437 uint32_t numbytes)
2438{
2439 uint32_t i, ret = 0;
2440 SwI2cRequest_t req;
2441 struct amdgpu_device *adev = to_amdgpu_device(control);
2442 struct smu_table_context *smu_table = &adev->smu.smu_table;
2443 struct smu_table *table = &smu_table->driver_table;
2444
d74a09c8
AD		 2445 if (numbytes > MAX_SW_I2C_COMMANDS) {
2446 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
2447 numbytes, MAX_SW_I2C_COMMANDS);
2448 return -EINVAL;
2449 }
2450
bc50ca29
AD		 2451 memset(&req, 0, sizeof(req));
2452 sienna_cichlid_fill_i2c_req(&req, false, address, numbytes, data);
2453
2454 mutex_lock(&adev->smu.mutex);
2455 /* Now read data starting with that address */
2456 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
2457 true);
2458 mutex_unlock(&adev->smu.mutex);
2459
2460 if (!ret) {
2461 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
2462
2463 /* Assume SMU fills res.SwI2cCmds[i].Data with read bytes */
2464 for (i = 0; i < numbytes; i++)
2465 data[i] = res->SwI2cCmds[i].ReadWriteData;
2466
2467 dev_dbg(adev->dev, "sienna_cichlid_i2c_read_data, address = %x, bytes = %d, data :",
2468 (uint16_t)address, numbytes);
2469
2470 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2471 8, 1, data, numbytes, false);
2472 } else
2473 dev_err(adev->dev, "sienna_cichlid_i2c_read_data - error occurred :%x", ret);
2474
2475 return ret;
2476}
2477
2478static int sienna_cichlid_i2c_write_data(struct i2c_adapter *control,
2479 uint8_t address,
2480 uint8_t *data,
2481 uint32_t numbytes)
2482{
2483 uint32_t ret;
2484 SwI2cRequest_t req;
2485 struct amdgpu_device *adev = to_amdgpu_device(control);
2486
d74a09c8
AD		 2487 if (numbytes > MAX_SW_I2C_COMMANDS) {
2488 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
2489 numbytes, MAX_SW_I2C_COMMANDS);
2490 return -EINVAL;
2491 }
2492
bc50ca29
AD		 2493 memset(&req, 0, sizeof(req));
2494 sienna_cichlid_fill_i2c_req(&req, true, address, numbytes, data);
2495
2496 mutex_lock(&adev->smu.mutex);
2497 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
2498 mutex_unlock(&adev->smu.mutex);
2499
2500 if (!ret) {
2501 dev_dbg(adev->dev, "sienna_cichlid_i2c_write(), address = %x, bytes = %d , data: ",
2502 (uint16_t)address, numbytes);
2503
2504 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2505 8, 1, data, numbytes, false);
2506 /*
2507 * According to EEPROM spec there is a MAX of 10 ms required for
2508 * EEPROM to flush internal RX buffer after STOP was issued at the
2509 * end of write transaction. During this time the EEPROM will not be
2510 * responsive to any more commands - so wait a bit more.
2511 */
2512 msleep(10);
2513
2514 } else
2515 dev_err(adev->dev, "sienna_cichlid_i2c_write- error occurred :%x", ret);
2516
2517 return ret;
2518}
2519
2520static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
2521 struct i2c_msg *msgs, int num)
2522{
2523 uint32_t i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
2524 uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
2525
2526 for (i = 0; i < num; i++) {
2527 /*
2528 * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
2529 * once and hence the data needs to be spliced into chunks and sent each
2530 * chunk separately
2531 */
2532 data_size = msgs[i].len - 2;
2533 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
2534 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
2535 data_ptr = msgs[i].buf + 2;
2536
2537 for (j = 0; j < data_size / data_chunk_size; j++) {
2538 /* Insert the EEPROM dest addess, bits 0-15 */
2539 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2540 data_chunk[1] = (next_eeprom_addr & 0xff);
2541
2542 if (msgs[i].flags & I2C_M_RD) {
2543 ret = sienna_cichlid_i2c_read_data(i2c_adap,
2544 (uint8_t)msgs[i].addr,
2545 data_chunk, MAX_SW_I2C_COMMANDS);
2546
2547 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
2548 } else {
2549
2550 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
2551
2552 ret = sienna_cichlid_i2c_write_data(i2c_adap,
2553 (uint8_t)msgs[i].addr,
2554 data_chunk, MAX_SW_I2C_COMMANDS);
2555 }
2556
2557 if (ret) {
2558 num = -EIO;
2559 goto fail;
2560 }
2561
2562 next_eeprom_addr += data_chunk_size;
2563 data_ptr += data_chunk_size;
2564 }
2565
2566 if (data_size % data_chunk_size) {
2567 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2568 data_chunk[1] = (next_eeprom_addr & 0xff);
2569
2570 if (msgs[i].flags & I2C_M_RD) {
2571 ret = sienna_cichlid_i2c_read_data(i2c_adap,
2572 (uint8_t)msgs[i].addr,
2573 data_chunk, (data_size % data_chunk_size) + 2);
2574
2575 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2576 } else {
2577 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2578
2579 ret = sienna_cichlid_i2c_write_data(i2c_adap,
2580 (uint8_t)msgs[i].addr,
2581 data_chunk, (data_size % data_chunk_size) + 2);
2582 }
2583
2584 if (ret) {
2585 num = -EIO;
2586 goto fail;
2587 }
2588 }
2589 }
2590
2591fail:
2592 return num;
2593}
2594
2595static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
2596{
2597 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2598}
2599
2600
2601static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
2602 .master_xfer = sienna_cichlid_i2c_xfer,
2603 .functionality = sienna_cichlid_i2c_func,
2604};
2605
bc50ca29
AD		 2606static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2607{
2608 struct amdgpu_device *adev = to_amdgpu_device(control);
2609 int res;
2610
bc50ca29
AD		 2611 control->owner = THIS_MODULE;
2612 control->class = I2C_CLASS_SPD;
2613 control->dev.parent = &adev->pdev->dev;
2614 control->algo = &sienna_cichlid_i2c_algo;
2615 snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2616
2617 res = i2c_add_adapter(control);
2618 if (res)
2619 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2620
2621 return res;
2622}
2623
2624static void sienna_cichlid_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2625{
bc50ca29
AD		 2626 i2c_del_adapter(control);
2627}
2628
8ca78a0a
EQ		 2629static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
2630 void **table)
2631{
2632 struct smu_table_context *smu_table = &smu->smu_table;
2633 struct gpu_metrics_v1_0 *gpu_metrics =
2634 (struct gpu_metrics_v1_0 *)smu_table->gpu_metrics_table;
2635 SmuMetrics_t metrics;
2636 int ret = 0;
2637
fceafc9b
EQ		 2638 ret = smu_cmn_get_metrics_table(smu,
2639 &metrics,
2640 true);
60ae4d67 2641 if (ret)
8ca78a0a 2642 return ret;
8ca78a0a
EQ		 2643
2644 smu_v11_0_init_gpu_metrics_v1_0(gpu_metrics);
2645
2646 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2647 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2648 gpu_metrics->temperature_mem = metrics.TemperatureMem;
2649 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2650 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2651 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2652
2653 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2654 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2655 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2656
2657 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2658 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2659
2660 if (metrics.AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
2661 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
2662 else
2663 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
2664 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
2665 gpu_metrics->average_vclk0_frequency = metrics.AverageVclk0Frequency;
2666 gpu_metrics->average_dclk0_frequency = metrics.AverageDclk0Frequency;
2667 gpu_metrics->average_vclk1_frequency = metrics.AverageVclk1Frequency;
2668 gpu_metrics->average_dclk1_frequency = metrics.AverageDclk1Frequency;
2669
2670 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2671 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2672 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2673 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK_0];
2674 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK_0];
2675 gpu_metrics->current_vclk1 = metrics.CurrClock[PPCLK_VCLK_1];
2676 gpu_metrics->current_dclk1 = metrics.CurrClock[PPCLK_DCLK_1];
2677
2678 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2679
2680 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2681
2682 gpu_metrics->pcie_link_width =
2683 smu_v11_0_get_current_pcie_link_width(smu);
2684 gpu_metrics->pcie_link_speed =
2685 smu_v11_0_get_current_pcie_link_speed(smu);
2686
2687 *table = (void *)gpu_metrics;
2688
2689 return sizeof(struct gpu_metrics_v1_0);
2690}
bc50ca29 2691
05f39286
EQ		 2692static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
2693{
2694 return smu_cmn_send_smc_msg_with_param(smu,
2695 SMU_MSG_SetMGpuFanBoostLimitRpm,
2696 0,
2697 NULL);
2698}
2699
76c71f00
EQ		 2700static int sienna_cichlid_gpo_control(struct smu_context *smu,
2701 bool enablement)
2702{
2703 int ret = 0;
2704
2705 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
2706 if (enablement)
2707 ret = smu_cmn_send_smc_msg_with_param(smu,
2708 SMU_MSG_SetGpoFeaturePMask,
2709 GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
2710 NULL);
2711 else
2712 ret = smu_cmn_send_smc_msg_with_param(smu,
2713 SMU_MSG_SetGpoFeaturePMask,
2714 0,
2715 NULL);
2716 }
2717
2718 return ret;
2719}
b455159c 2720static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
b455159c
LG		 2721 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
2722 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
f6b4b4a1 2723 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
6fb176a7 2724 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
bc50ca29
AD		 2725 .i2c_init = sienna_cichlid_i2c_control_init,
2726 .i2c_fini = sienna_cichlid_i2c_control_fini,
b455159c
LG		 2727 .print_clk_levels = sienna_cichlid_print_clk_levels,
2728 .force_clk_levels = sienna_cichlid_force_clk_levels,
2729 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
b455159c
LG		 2730 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
2731 .display_config_changed = sienna_cichlid_display_config_changed,
2732 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
b455159c 2733 .is_dpm_running = sienna_cichlid_is_dpm_running,
b455159c
LG		 2734 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
2735 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
2736 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
b455159c
LG		 2737 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
2738 .read_sensor = sienna_cichlid_read_sensor,
2739 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
b2785e25 2740 .set_performance_level = smu_v11_0_set_performance_level,
b455159c
LG		 2741 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
2742 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
2743 .get_power_limit = sienna_cichlid_get_power_limit,
08ccfe08 2744 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
b455159c
LG		 2745 .dump_pptable = sienna_cichlid_dump_pptable,
2746 .init_microcode = smu_v11_0_init_microcode,
2747 .load_microcode = smu_v11_0_load_microcode,
c1b353b7 2748 .init_smc_tables = sienna_cichlid_init_smc_tables,
b455159c
LG		 2749 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2750 .init_power = smu_v11_0_init_power,
2751 .fini_power = smu_v11_0_fini_power,
2752 .check_fw_status = smu_v11_0_check_fw_status,
4a13b4ce 2753 .setup_pptable = sienna_cichlid_setup_pptable,
b455159c 2754 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
b455159c 2755 .check_fw_version = smu_v11_0_check_fw_version,
caad2613 2756 .write_pptable = smu_cmn_write_pptable,
b455159c
LG		 2757 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2758 .set_tool_table_location = smu_v11_0_set_tool_table_location,
2759 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2760 .system_features_control = smu_v11_0_system_features_control,
66c86828
EQ		 2761 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2762 .send_smc_msg = smu_cmn_send_smc_msg,
31157341 2763 .init_display_count = NULL,
b455159c 2764 .set_allowed_mask = smu_v11_0_set_allowed_mask,
28251d72 2765 .get_enabled_mask = smu_cmn_get_enabled_mask,
b4bb3aaf 2766 .feature_is_enabled = smu_cmn_feature_is_enabled,
af5ba6d2 2767 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
31157341 2768 .notify_display_change = NULL,
b455159c 2769 .set_power_limit = smu_v11_0_set_power_limit,
b455159c
LG		 2770 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2771 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2772 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
ce63d8f8 2773 .set_min_dcef_deep_sleep = NULL,
b455159c
LG		 2774 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2775 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2776 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
b455159c
LG		 2777 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2778 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2779 .gfx_off_control = smu_v11_0_gfx_off_control,
2780 .register_irq_handler = smu_v11_0_register_irq_handler,
2781 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2782 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
40d3b8db 2783 .baco_is_support= sienna_cichlid_is_baco_supported,
b455159c
LG		 2784 .baco_get_state = smu_v11_0_baco_get_state,
2785 .baco_set_state = smu_v11_0_baco_set_state,
2786 .baco_enter = smu_v11_0_baco_enter,
2787 .baco_exit = smu_v11_0_baco_exit,
ea8139d8
WS		 2788 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
2789 .mode1_reset = smu_v11_0_mode1_reset,
258d290c 2790 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
10e96d89 2791 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
66b8a9c0 2792 .run_btc = sienna_cichlid_run_btc,
7dbf7805
EQ		 2793 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2794 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
8ca78a0a 2795 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
05f39286 2796 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
e988026f 2797 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
5ce99853 2798 .deep_sleep_control = smu_v11_0_deep_sleep_control,
3204ff3e 2799 .get_fan_parameters = sienna_cichlid_get_fan_parameters,
234676d6 2800 .interrupt_work = smu_v11_0_interrupt_work,
76c71f00 2801 .gpo_control = sienna_cichlid_gpo_control,
b455159c
LG		 2802};
2803
2804void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
2805{
2806 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
6c339f37
EQ		 2807 smu->message_map = sienna_cichlid_message_map;
2808 smu->clock_map = sienna_cichlid_clk_map;
2809 smu->feature_map = sienna_cichlid_feature_mask_map;
2810 smu->table_map = sienna_cichlid_table_map;
2811 smu->pwr_src_map = sienna_cichlid_pwr_src_map;
2812 smu->workload_map = sienna_cichlid_workload_map;
b455159c 2813}
Linux 6.x block layer and io_uring tree(s)