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drm/amdgpu: suppress the warning about enum value 'AMD_IP_BLOCK_TYPE_NUM'
[linux-block.git] / drivers / gpu / drm / amd / pm / swsmu / smu11 / sienna_cichlid_ppt.c
CommitLineData
b455159c
LG		 1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
d8e0b16d
EQ		 24#define SWSMU_CODE_LAYER_L2
25
b455159c
LG		 26#include <linux/firmware.h>
27#include <linux/pci.h>
bc50ca29 28#include <linux/i2c.h>
b455159c
LG		 29#include "amdgpu.h"
30#include "amdgpu_smu.h"
b455159c
LG		 31#include "atomfirmware.h"
32#include "amdgpu_atomfirmware.h"
22f2447c 33#include "amdgpu_atombios.h"
b455159c
LG		 34#include "smu_v11_0.h"
35#include "smu11_driver_if_sienna_cichlid.h"
36#include "soc15_common.h"
37#include "atom.h"
38#include "sienna_cichlid_ppt.h"
e05acd78 39#include "smu_v11_0_7_pptable.h"
b455159c 40#include "smu_v11_0_7_ppsmc.h"
40d3b8db 41#include "nbio/nbio_2_3_offset.h"
b7d25b5f 42#include "nbio/nbio_2_3_sh_mask.h"
e05acd78
LG		 43#include "thm/thm_11_0_2_offset.h"
44#include "thm/thm_11_0_2_sh_mask.h"
ea8139d8
WS		 45#include "mp/mp_11_0_offset.h"
46#include "mp/mp_11_0_sh_mask.h"
b455159c 47
6c339f37 48#include "asic_reg/mp/mp_11_0_sh_mask.h"
3ddd0c90 49#include "amdgpu_ras.h"
6c339f37
EQ		 50#include "smu_cmn.h"
51
55084d7f
EQ		 52/*
53 * DO NOT use these for err/warn/info/debug messages.
54 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
55 * They are more MGPU friendly.
56 */
57#undef pr_err
58#undef pr_warn
59#undef pr_info
60#undef pr_debug
61
bc50ca29
AD		 62#define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
63
b455159c
LG		 64#define FEATURE_MASK(feature) (1ULL << feature)
65#define SMC_DPM_FEATURE ( \
66 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
fea905d4 67 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65297d50 68 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
5cb74353 69 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
4cd4f45b 70 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
5f338f70 71 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
ce7e5a6e
JC		 72 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \
73 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
b455159c 74
d817f375
LG		 75#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
76
7077b19a 77#define GET_PPTABLE_MEMBER(field, member) do {\
1d789535 78 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))\
7077b19a
CG		 79 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
80 else\
81 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
82} while(0)
83
db5b5c67
AG		 84/* STB FIFO depth is in 64bit units */
85#define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES 8
86
3ddd0c90 87/*
88 * SMU support ECCTABLE since version 58.70.0,
89 * use this to check whether ECCTABLE feature is supported.
90 */
91#define SUPPORT_ECCTABLE_SMU_VERSION 0x003a4600
92
7077b19a
CG		 93static int get_table_size(struct smu_context *smu)
94{
1d789535 95 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
7077b19a
CG		 96 return sizeof(PPTable_beige_goby_t);
97 else
98 return sizeof(PPTable_t);
99}
100
6c339f37
EQ		 101static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
102 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
103 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
104 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
91190db1
LG		 105 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
106 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
107 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
108 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
6c339f37
EQ		 109 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
110 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
111 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
112 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
113 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
114 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
115 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
91190db1 116 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
4215a119
HC		 117 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
118 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
91190db1
LG		 119 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
120 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
4215a119 121 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
91190db1
LG		 122 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
123 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
66b8a9c0 124 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
91190db1 125 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
4215a119
HC		 126 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
127 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
6c339f37 128 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
91190db1 129 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
6c339f37
EQ		 130 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
131 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
132 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
91190db1
LG		 133 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
134 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
135 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
136 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
137 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
138 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
139 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
140 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
6c339f37 141 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
91190db1
LG		 142 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
143 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
f3527a64 144 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1),
6c339f37 145 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
91190db1
LG		 146 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
147 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
148 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
149 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
150 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
151 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
152 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
153 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
05f39286 154 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
76c71f00 155 MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0),
ac7804bb 156 MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0),
88dfd5d5 157 MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0),
b455159c
LG		 158};
159
6c339f37 160static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
b455159c
LG		 161 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
162 CLK_MAP(SCLK, PPCLK_GFXCLK),
163 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
164 CLK_MAP(FCLK, PPCLK_FCLK),
165 CLK_MAP(UCLK, PPCLK_UCLK),
166 CLK_MAP(MCLK, PPCLK_UCLK),
167 CLK_MAP(DCLK, PPCLK_DCLK_0),
9c0551f2
JC		 168 CLK_MAP(DCLK1, PPCLK_DCLK_1),
169 CLK_MAP(VCLK, PPCLK_VCLK_0),
b455159c
LG		 170 CLK_MAP(VCLK1, PPCLK_VCLK_1),
171 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
172 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
173 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
174 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
175};
176
6c339f37 177static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
b455159c
LG		 178 FEA_MAP(DPM_PREFETCHER),
179 FEA_MAP(DPM_GFXCLK),
31cb0dd9 180 FEA_MAP(DPM_GFX_GPO),
b455159c 181 FEA_MAP(DPM_UCLK),
e9073b43 182 FEA_MAP(DPM_FCLK),
b455159c
LG		 183 FEA_MAP(DPM_SOCCLK),
184 FEA_MAP(DPM_MP0CLK),
185 FEA_MAP(DPM_LINK),
186 FEA_MAP(DPM_DCEFCLK),
e9073b43 187 FEA_MAP(DPM_XGMI),
b455159c
LG		 188 FEA_MAP(MEM_VDDCI_SCALING),
189 FEA_MAP(MEM_MVDD_SCALING),
190 FEA_MAP(DS_GFXCLK),
191 FEA_MAP(DS_SOCCLK),
e9073b43 192 FEA_MAP(DS_FCLK),
b455159c
LG		 193 FEA_MAP(DS_LCLK),
194 FEA_MAP(DS_DCEFCLK),
195 FEA_MAP(DS_UCLK),
196 FEA_MAP(GFX_ULV),
197 FEA_MAP(FW_DSTATE),
198 FEA_MAP(GFXOFF),
199 FEA_MAP(BACO),
6fb176a7 200 FEA_MAP(MM_DPM_PG),
b455159c
LG		 201 FEA_MAP(RSMU_SMN_CG),
202 FEA_MAP(PPT),
203 FEA_MAP(TDC),
204 FEA_MAP(APCC_PLUS),
205 FEA_MAP(GTHR),
206 FEA_MAP(ACDC),
207 FEA_MAP(VR0HOT),
208 FEA_MAP(VR1HOT),
209 FEA_MAP(FW_CTF),
210 FEA_MAP(FAN_CONTROL),
211 FEA_MAP(THERMAL),
212 FEA_MAP(GFX_DCS),
213 FEA_MAP(RM),
214 FEA_MAP(LED_DISPLAY),
215 FEA_MAP(GFX_SS),
216 FEA_MAP(OUT_OF_BAND_MONITOR),
217 FEA_MAP(TEMP_DEPENDENT_VMIN),
218 FEA_MAP(MMHUB_PG),
219 FEA_MAP(ATHUB_PG),
cf06331f 220 FEA_MAP(APCC_DFLL),
b455159c
LG		 221};
222
6c339f37 223static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
b455159c
LG		 224 TAB_MAP(PPTABLE),
225 TAB_MAP(WATERMARKS),
226 TAB_MAP(AVFS_PSM_DEBUG),
227 TAB_MAP(AVFS_FUSE_OVERRIDE),
228 TAB_MAP(PMSTATUSLOG),
229 TAB_MAP(SMU_METRICS),
230 TAB_MAP(DRIVER_SMU_CONFIG),
231 TAB_MAP(ACTIVITY_MONITOR_COEFF),
232 TAB_MAP(OVERDRIVE),
233 TAB_MAP(I2C_COMMANDS),
234 TAB_MAP(PACE),
3ddd0c90 235 TAB_MAP(ECCINFO),
b455159c
LG		 236};
237
6c339f37 238static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
1d5ca713
LG		 239 PWR_MAP(AC),
240 PWR_MAP(DC),
241};
242
6c339f37 243static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
b455159c
LG		 244 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
245 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
246 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
247 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
248 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
4c4d5a49 249 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
b455159c
LG		 250 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
251};
252
f06d9511
GS		 253static const uint8_t sienna_cichlid_throttler_map[] = {
254 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
255 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
256 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
257 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
258 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
259 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
260 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
261 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
262 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
263 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
264 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
265 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
266 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
267 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
268 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
269 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
270 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
271 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
272};
273
b455159c
LG		 274static int
275sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
276 uint32_t *feature_mask, uint32_t num)
277{
fea905d4
LG		 278 struct amdgpu_device *adev = smu->adev;
279
b455159c
LG		 280 if (num > 2)
281 return -EINVAL;
282
283 memset(feature_mask, 0, sizeof(uint32_t) * num);
284
4cd4f45b 285 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
15dbe18f 286 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
ce7e5a6e 287 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
094cdf15 288 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
5f338f70 289 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
86a9eb3f 290 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
80c36f86 291 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
9aa60213
LG		 292 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
293 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
d28f4aa1 294 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
20d71dcc 295 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
d0d71970 296 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
886c8bc6
LG		 297 | FEATURE_MASK(FEATURE_PPT_BIT)
298 | FEATURE_MASK(FEATURE_TDC_BIT)
3fc006f5 299 | FEATURE_MASK(FEATURE_BACO_BIT)
cf06331f 300 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
35ed946c 301 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
1c58d429 302 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
b971df70
LG		 303 | FEATURE_MASK(FEATURE_THERMAL_BIT)
304 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
fea905d4 305
c96721eb 306 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
fea905d4 307 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
c96721eb
KF		 308 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
309 }
fea905d4 310
680602d6 311 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
1d789535 312 (adev->ip_versions[MP1_HWIP][0] > IP_VERSION(11, 0, 7)) &&
680602d6
KF		 313 !(adev->flags & AMD_IS_APU))
314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
315
65297d50 316 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
fc17cd3f
LG		 317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
318 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
319 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
65297d50 320
5cb74353
LG		 321 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
322 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
323
5f338f70
LG		 324 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
325 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
326
fea905d4
LG		 327 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
328 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
b455159c 329
62c1ea6b
LG		 330 if (adev->pm.pp_feature & PP_ULV_MASK)
331 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
332
02bb391d
LG		 333 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
334 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
335
e0da123a
LG		 336 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
337 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
338
b794616d
KF		 339 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
340 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
341
846938c2
KF		 342 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
343 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
344
6fb176a7
LG		 345 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
346 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
347 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
348
62826b86
KF		 349 if (smu->dc_controlled_by_gpio)
350 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
351
0064b0ce 352 if (amdgpu_aspm)
6ef28889
KF		 353 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
354
b455159c
LG		 355 return 0;
356}
357
458020dd 358static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
b455159c 359{
4a13b4ce 360 struct smu_table_context *table_context = &smu->smu_table;
e05acd78 361 struct smu_11_0_7_powerplay_table *powerplay_table =
4a13b4ce
EQ		 362 table_context->power_play_table;
363 struct smu_baco_context *smu_baco = &smu->smu_baco;
458020dd
LL		 364 struct amdgpu_device *adev = smu->adev;
365 uint32_t val;
366
1b41d67e 367 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) {
458020dd
LL		 368 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
369 smu_baco->platform_support =
370 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
371 false;
372 }
373}
374
375static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
376{
377 struct smu_table_context *table_context = &smu->smu_table;
378 struct smu_11_0_7_powerplay_table *powerplay_table =
379 table_context->power_play_table;
4a13b4ce 380
18a4b3de
EQ		 381 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
382 smu->dc_controlled_by_gpio = true;
383
458020dd 384 sienna_cichlid_check_bxco_support(smu);
4a13b4ce
EQ		 385
386 table_context->thermal_controller_type =
387 powerplay_table->thermal_controller_type;
388
aa75fa34
EQ		 389 /*
390 * Instead of having its own buffer space and get overdrive_table copied,
391 * smu->od_settings just points to the actual overdrive_table
392 */
393 smu->od_settings = &powerplay_table->overdrive_table;
394
b455159c
LG		 395 return 0;
396}
397
398static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
399{
dccc7c21
LG		 400 struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
401 int index, ret;
7077b19a 402 I2cControllerConfig_t *table_member;
dccc7c21
LG		 403
404 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
405 smc_dpm_info);
406
22f2447c 407 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
dccc7c21
LG		 408 (uint8_t **)&smc_dpm_table);
409 if (ret)
410 return ret;
7077b19a
CG		 411 GET_PPTABLE_MEMBER(I2cControllers, &table_member);
412 memcpy(table_member, smc_dpm_table->I2cControllers,
413 sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
969c8d16 414
b455159c
LG		 415 return 0;
416}
417
418static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
419{
b455159c 420 struct smu_table_context *table_context = &smu->smu_table;
e05acd78 421 struct smu_11_0_7_powerplay_table *powerplay_table =
4a13b4ce 422 table_context->power_play_table;
7077b19a 423 int table_size;
b455159c 424
7077b19a 425 table_size = get_table_size(smu);
b455159c 426 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
7077b19a 427 table_size);
b455159c 428
4a13b4ce
EQ		 429 return 0;
430}
b455159c 431
4a13b4ce
EQ		 432static int sienna_cichlid_setup_pptable(struct smu_context *smu)
433{
434 int ret = 0;
b455159c 435
4a13b4ce
EQ		 436 ret = smu_v11_0_setup_pptable(smu);
437 if (ret)
438 return ret;
439
440 ret = sienna_cichlid_store_powerplay_table(smu);
441 if (ret)
442 return ret;
443
444 ret = sienna_cichlid_append_powerplay_table(smu);
445 if (ret)
446 return ret;
447
448 ret = sienna_cichlid_check_powerplay_table(smu);
449 if (ret)
450 return ret;
451
452 return ret;
b455159c
LG		 453}
454
c1b353b7 455static int sienna_cichlid_tables_init(struct smu_context *smu)
b455159c
LG		 456{
457 struct smu_table_context *smu_table = &smu->smu_table;
c1b353b7 458 struct smu_table *tables = smu_table->tables;
7077b19a 459 int table_size;
b455159c 460
7077b19a
CG		 461 table_size = get_table_size(smu);
462 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
463 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c
LG		 464 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
465 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b4b0b79d 466 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
b455159c 467 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
bc50ca29
AD		 468 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
469 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c
LG		 470 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
471 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
472 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
473 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
474 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
f9e3fe46 475 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
b455159c 476 AMDGPU_GEM_DOMAIN_VRAM);
3ddd0c90 477 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
478 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c 479
b4b0b79d 480 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
b455159c 481 if (!smu_table->metrics_table)
8ca78a0a 482 goto err0_out;
b455159c
LG		 483 smu_table->metrics_time = 0;
484
f06d9511 485 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
8ca78a0a
EQ		 486 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
487 if (!smu_table->gpu_metrics_table)
488 goto err1_out;
489
40d3b8db
LG		 490 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
491 if (!smu_table->watermarks_table)
8ca78a0a 492 goto err2_out;
40d3b8db 493
3ddd0c90 494 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
495 if (!smu_table->ecc_table)
496 return -ENOMEM;
497
b455159c 498 return 0;
8ca78a0a
EQ		 499
500err2_out:
501 kfree(smu_table->gpu_metrics_table);
502err1_out:
503 kfree(smu_table->metrics_table);
504err0_out:
505 return -ENOMEM;
b455159c
LG		 506}
507
be22e2b9
EQ		 508static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu)
509{
510 struct smu_table_context *smu_table= &smu->smu_table;
511 SmuMetricsExternal_t *metrics_ext =
512 (SmuMetricsExternal_t *)(smu_table->metrics_table);
513 uint32_t throttler_status = 0;
514 int i;
515
1d789535 516 if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
be22e2b9
EQ		 517 (smu->smc_fw_version >= 0x3A4300)) {
518 for (i = 0; i < THROTTLER_COUNT; i++)
519 throttler_status |=
520 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
521 } else {
522 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus;
523 }
524
525 return throttler_status;
526}
527
60ae4d67
EQ		 528static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
529 MetricsMember_t member,
530 uint32_t *value)
531{
532 struct smu_table_context *smu_table= &smu->smu_table;
b4b0b79d
EQ		 533 SmuMetrics_t *metrics =
534 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
be22e2b9
EQ		 535 SmuMetrics_V2_t *metrics_v2 =
536 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
1d789535 537 bool use_metrics_v2 = ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
be22e2b9
EQ		 538 (smu->smc_fw_version >= 0x3A4300)) ? true : false;
539 uint16_t average_gfx_activity;
60ae4d67
EQ		 540 int ret = 0;
541
542 mutex_lock(&smu->metrics_lock);
543
fceafc9b
EQ		 544 ret = smu_cmn_get_metrics_table_locked(smu,
545 NULL,
546 false);
60ae4d67
EQ		 547 if (ret) {
548 mutex_unlock(&smu->metrics_lock);
549 return ret;
550 }
551
8c686254
EQ		 552 switch (member) {
553 case METRICS_CURR_GFXCLK:
be22e2b9
EQ		 554 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] :
555 metrics->CurrClock[PPCLK_GFXCLK];
8c686254
EQ		 556 break;
557 case METRICS_CURR_SOCCLK:
be22e2b9
EQ		 558 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] :
559 metrics->CurrClock[PPCLK_SOCCLK];
8c686254
EQ		 560 break;
561 case METRICS_CURR_UCLK:
be22e2b9
EQ		 562 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] :
563 metrics->CurrClock[PPCLK_UCLK];
8c686254
EQ		 564 break;
565 case METRICS_CURR_VCLK:
be22e2b9
EQ		 566 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] :
567 metrics->CurrClock[PPCLK_VCLK_0];
8c686254
EQ		 568 break;
569 case METRICS_CURR_VCLK1:
be22e2b9
EQ		 570 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] :
571 metrics->CurrClock[PPCLK_VCLK_1];
8c686254
EQ		 572 break;
573 case METRICS_CURR_DCLK:
be22e2b9
EQ		 574 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] :
575 metrics->CurrClock[PPCLK_DCLK_0];
8c686254
EQ		 576 break;
577 case METRICS_CURR_DCLK1:
be22e2b9
EQ		 578 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
579 metrics->CurrClock[PPCLK_DCLK_1];
8c686254 580 break;
9d09fa6f 581 case METRICS_CURR_DCEFCLK:
be22e2b9
EQ		 582 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] :
583 metrics->CurrClock[PPCLK_DCEFCLK];
9d09fa6f 584 break;
4e2b3e23 585 case METRICS_CURR_FCLK:
be22e2b9
EQ		 586 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] :
587 metrics->CurrClock[PPCLK_FCLK];
4e2b3e23 588 break;
8c686254 589 case METRICS_AVERAGE_GFXCLK:
be22e2b9
EQ		 590 average_gfx_activity = use_metrics_v2 ? metrics_v2->AverageGfxActivity :
591 metrics->AverageGfxActivity;
592 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
593 *value = use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
594 metrics->AverageGfxclkFrequencyPostDs;
d817f375 595 else
be22e2b9
EQ		 596 *value = use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
597 metrics->AverageGfxclkFrequencyPreDs;
8c686254
EQ		 598 break;
599 case METRICS_AVERAGE_FCLK:
be22e2b9
EQ		 600 *value = use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs :
601 metrics->AverageFclkFrequencyPostDs;
8c686254
EQ		 602 break;
603 case METRICS_AVERAGE_UCLK:
be22e2b9
EQ		 604 *value = use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
605 metrics->AverageUclkFrequencyPostDs;
8c686254
EQ		 606 break;
607 case METRICS_AVERAGE_GFXACTIVITY:
be22e2b9
EQ		 608 *value = use_metrics_v2 ? metrics_v2->AverageGfxActivity :
609 metrics->AverageGfxActivity;
8c686254
EQ		 610 break;
611 case METRICS_AVERAGE_MEMACTIVITY:
be22e2b9
EQ		 612 *value = use_metrics_v2 ? metrics_v2->AverageUclkActivity :
613 metrics->AverageUclkActivity;
8c686254
EQ		 614 break;
615 case METRICS_AVERAGE_SOCKETPOWER:
be22e2b9
EQ		 616 *value = use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 :
617 metrics->AverageSocketPower << 8;
8c686254
EQ		 618 break;
619 case METRICS_TEMPERATURE_EDGE:
be22e2b9 620 *value = (use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge) *
8c686254
EQ		 621 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
622 break;
623 case METRICS_TEMPERATURE_HOTSPOT:
be22e2b9 624 *value = (use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot) *
8c686254
EQ		 625 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
626 break;
627 case METRICS_TEMPERATURE_MEM:
be22e2b9 628 *value = (use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem) *
8c686254
EQ		 629 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
630 break;
631 case METRICS_TEMPERATURE_VRGFX:
be22e2b9 632 *value = (use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx) *
8c686254
EQ		 633 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
634 break;
635 case METRICS_TEMPERATURE_VRSOC:
be22e2b9 636 *value = (use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc) *
8c686254
EQ		 637 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
638 break;
639 case METRICS_THROTTLER_STATUS:
be22e2b9 640 *value = sienna_cichlid_get_throttler_status_locked(smu);
8c686254
EQ		 641 break;
642 case METRICS_CURR_FANSPEED:
be22e2b9 643 *value = use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
8c686254
EQ		 644 break;
645 default:
646 *value = UINT_MAX;
647 break;
648 }
649
b455159c
LG		 650 mutex_unlock(&smu->metrics_lock);
651
652 return ret;
8c686254 653
b455159c
LG		 654}
655
656static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
657{
658 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
659
b455159c
LG		 660 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
661 GFP_KERNEL);
662 if (!smu_dpm->dpm_context)
663 return -ENOMEM;
664
665 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
666
667 return 0;
668}
669
db5b5c67
AG		 670static void sienna_cichlid_stb_init(struct smu_context *smu);
671
c1b353b7
EQ		 672static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
673{
674 int ret = 0;
675
676 ret = sienna_cichlid_tables_init(smu);
677 if (ret)
678 return ret;
679
680 ret = sienna_cichlid_allocate_dpm_context(smu);
681 if (ret)
682 return ret;
683
db5b5c67
AG		 684 sienna_cichlid_stb_init(smu);
685
c1b353b7
EQ		 686 return smu_v11_0_init_smc_tables(smu);
687}
688
b455159c
LG		 689static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
690{
90a89c31 691 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
90a89c31 692 struct smu_11_0_dpm_table *dpm_table;
85dec717 693 struct amdgpu_device *adev = smu->adev;
0b54122c 694 int i, ret = 0;
7077b19a 695 DpmDescriptor_t *table_member;
b455159c 696
90a89c31
EQ		 697 /* socclk dpm table setup */
698 dpm_table = &dpm_context->dpm_tables.soc_table;
7077b19a 699 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
b4bb3aaf 700 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
90a89c31
EQ		 701 ret = smu_v11_0_set_single_dpm_table(smu,
702 SMU_SOCCLK,
703 dpm_table);
704 if (ret)
705 return ret;
706 dpm_table->is_fine_grained =
7077b19a 707 !table_member[PPCLK_SOCCLK].SnapToDiscrete;
90a89c31
EQ		 708 } else {
709 dpm_table->count = 1;
710 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
711 dpm_table->dpm_levels[0].enabled = true;
712 dpm_table->min = dpm_table->dpm_levels[0].value;
713 dpm_table->max = dpm_table->dpm_levels[0].value;
714 }
b455159c 715
90a89c31
EQ		 716 /* gfxclk dpm table setup */
717 dpm_table = &dpm_context->dpm_tables.gfx_table;
b4bb3aaf 718 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
90a89c31
EQ		 719 ret = smu_v11_0_set_single_dpm_table(smu,
720 SMU_GFXCLK,
721 dpm_table);
722 if (ret)
723 return ret;
724 dpm_table->is_fine_grained =
7077b19a 725 !table_member[PPCLK_GFXCLK].SnapToDiscrete;
90a89c31
EQ		 726 } else {
727 dpm_table->count = 1;
728 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
729 dpm_table->dpm_levels[0].enabled = true;
730 dpm_table->min = dpm_table->dpm_levels[0].value;
731 dpm_table->max = dpm_table->dpm_levels[0].value;
732 }
b455159c 733
90a89c31
EQ		 734 /* uclk dpm table setup */
735 dpm_table = &dpm_context->dpm_tables.uclk_table;
b4bb3aaf 736 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
90a89c31
EQ		 737 ret = smu_v11_0_set_single_dpm_table(smu,
738 SMU_UCLK,
739 dpm_table);
740 if (ret)
741 return ret;
742 dpm_table->is_fine_grained =
7077b19a 743 !table_member[PPCLK_UCLK].SnapToDiscrete;
90a89c31
EQ		 744 } else {
745 dpm_table->count = 1;
746 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
747 dpm_table->dpm_levels[0].enabled = true;
748 dpm_table->min = dpm_table->dpm_levels[0].value;
749 dpm_table->max = dpm_table->dpm_levels[0].value;
750 }
b455159c 751
90a89c31
EQ		 752 /* fclk dpm table setup */
753 dpm_table = &dpm_context->dpm_tables.fclk_table;
b4bb3aaf 754 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
90a89c31
EQ		 755 ret = smu_v11_0_set_single_dpm_table(smu,
756 SMU_FCLK,
757 dpm_table);
758 if (ret)
759 return ret;
760 dpm_table->is_fine_grained =
7077b19a 761 !table_member[PPCLK_FCLK].SnapToDiscrete;
90a89c31
EQ		 762 } else {
763 dpm_table->count = 1;
764 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
765 dpm_table->dpm_levels[0].enabled = true;
766 dpm_table->min = dpm_table->dpm_levels[0].value;
767 dpm_table->max = dpm_table->dpm_levels[0].value;
768 }
b455159c 769
0b54122c
AD		 770 /* vclk0/1 dpm table setup */
771 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
772 if (adev->vcn.harvest_config & (1 << i))
773 continue;
b455159c 774
0b54122c 775 dpm_table = &dpm_context->dpm_tables.vclk_table;
85dec717
JC		 776 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
777 ret = smu_v11_0_set_single_dpm_table(smu,
0b54122c 778 i ? SMU_VCLK1 : SMU_VCLK,
85dec717
JC		 779 dpm_table);
780 if (ret)
781 return ret;
782 dpm_table->is_fine_grained =
0b54122c 783 !table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete;
85dec717
JC		 784 } else {
785 dpm_table->count = 1;
0b54122c 786 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
85dec717
JC		 787 dpm_table->dpm_levels[0].enabled = true;
788 dpm_table->min = dpm_table->dpm_levels[0].value;
789 dpm_table->max = dpm_table->dpm_levels[0].value;
790 }
90a89c31 791 }
b455159c 792
0b54122c
AD		 793 /* dclk0/1 dpm table setup */
794 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
795 if (adev->vcn.harvest_config & (1 << i))
796 continue;
797 dpm_table = &dpm_context->dpm_tables.dclk_table;
85dec717
JC		 798 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
799 ret = smu_v11_0_set_single_dpm_table(smu,
0b54122c 800 i ? SMU_DCLK1 : SMU_DCLK,
85dec717
JC		 801 dpm_table);
802 if (ret)
803 return ret;
804 dpm_table->is_fine_grained =
0b54122c 805 !table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0].SnapToDiscrete;
85dec717
JC		 806 } else {
807 dpm_table->count = 1;
0b54122c 808 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
85dec717
JC		 809 dpm_table->dpm_levels[0].enabled = true;
810 dpm_table->min = dpm_table->dpm_levels[0].value;
811 dpm_table->max = dpm_table->dpm_levels[0].value;
812 }
90a89c31
EQ		 813 }
814
815 /* dcefclk dpm table setup */
816 dpm_table = &dpm_context->dpm_tables.dcef_table;
b4bb3aaf 817 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 818 ret = smu_v11_0_set_single_dpm_table(smu,
819 SMU_DCEFCLK,
820 dpm_table);
821 if (ret)
822 return ret;
823 dpm_table->is_fine_grained =
7077b19a 824 !table_member[PPCLK_DCEFCLK].SnapToDiscrete;
90a89c31
EQ		 825 } else {
826 dpm_table->count = 1;
827 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
828 dpm_table->dpm_levels[0].enabled = true;
829 dpm_table->min = dpm_table->dpm_levels[0].value;
830 dpm_table->max = dpm_table->dpm_levels[0].value;
831 }
b455159c 832
90a89c31
EQ		 833 /* pixelclk dpm table setup */
834 dpm_table = &dpm_context->dpm_tables.pixel_table;
b4bb3aaf 835 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 836 ret = smu_v11_0_set_single_dpm_table(smu,
837 SMU_PIXCLK,
838 dpm_table);
839 if (ret)
840 return ret;
841 dpm_table->is_fine_grained =
7077b19a 842 !table_member[PPCLK_PIXCLK].SnapToDiscrete;
90a89c31
EQ		 843 } else {
844 dpm_table->count = 1;
845 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
846 dpm_table->dpm_levels[0].enabled = true;
847 dpm_table->min = dpm_table->dpm_levels[0].value;
848 dpm_table->max = dpm_table->dpm_levels[0].value;
849 }
b455159c 850
90a89c31
EQ		 851 /* displayclk dpm table setup */
852 dpm_table = &dpm_context->dpm_tables.display_table;
b4bb3aaf 853 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 854 ret = smu_v11_0_set_single_dpm_table(smu,
855 SMU_DISPCLK,
856 dpm_table);
857 if (ret)
858 return ret;
859 dpm_table->is_fine_grained =
7077b19a 860 !table_member[PPCLK_DISPCLK].SnapToDiscrete;
90a89c31
EQ		 861 } else {
862 dpm_table->count = 1;
863 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
864 dpm_table->dpm_levels[0].enabled = true;
865 dpm_table->min = dpm_table->dpm_levels[0].value;
866 dpm_table->max = dpm_table->dpm_levels[0].value;
867 }
b455159c 868
90a89c31
EQ		 869 /* phyclk dpm table setup */
870 dpm_table = &dpm_context->dpm_tables.phy_table;
b4bb3aaf 871 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 872 ret = smu_v11_0_set_single_dpm_table(smu,
873 SMU_PHYCLK,
874 dpm_table);
875 if (ret)
876 return ret;
877 dpm_table->is_fine_grained =
7077b19a 878 !table_member[PPCLK_PHYCLK].SnapToDiscrete;
90a89c31
EQ		 879 } else {
880 dpm_table->count = 1;
881 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
882 dpm_table->dpm_levels[0].enabled = true;
883 dpm_table->min = dpm_table->dpm_levels[0].value;
884 dpm_table->max = dpm_table->dpm_levels[0].value;
885 }
b455159c
LG		 886
887 return 0;
888}
889
f6b4b4a1 890static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
b455159c 891{
d51dc613 892 struct amdgpu_device *adev = smu->adev;
0b54122c 893 int i, ret = 0;
b455159c 894
0b54122c
AD		 895 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
896 if (adev->vcn.harvest_config & (1 << i))
897 continue;
b455159c 898 /* vcn dpm on is a prerequisite for vcn power gate messages */
b4bb3aaf 899 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
0b54122c
AD		 900 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
901 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
902 0x10000 * i, NULL);
6fb176a7
LG		 903 if (ret)
904 return ret;
b455159c 905 }
b455159c
LG		 906 }
907
908 return ret;
909}
910
6fb176a7
LG		 911static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
912{
6fb176a7
LG		 913 int ret = 0;
914
915 if (enable) {
b4bb3aaf 916 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 917 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
6fb176a7
LG		 918 if (ret)
919 return ret;
6fb176a7 920 }
6fb176a7 921 } else {
b4bb3aaf 922 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 923 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
6fb176a7
LG		 924 if (ret)
925 return ret;
6fb176a7 926 }
6fb176a7
LG		 927 }
928
929 return ret;
930}
931
b455159c
LG		 932static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
933 enum smu_clk_type clk_type,
934 uint32_t *value)
935{
8c686254
EQ		 936 MetricsMember_t member_type;
937 int clk_id = 0;
b455159c 938
6c339f37
EQ		 939 clk_id = smu_cmn_to_asic_specific_index(smu,
940 CMN2ASIC_MAPPING_CLK,
941 clk_type);
b455159c
LG		 942 if (clk_id < 0)
943 return clk_id;
944
8c686254
EQ		 945 switch (clk_id) {
946 case PPCLK_GFXCLK:
947 member_type = METRICS_CURR_GFXCLK;
948 break;
949 case PPCLK_UCLK:
950 member_type = METRICS_CURR_UCLK;
951 break;
952 case PPCLK_SOCCLK:
953 member_type = METRICS_CURR_SOCCLK;
954 break;
955 case PPCLK_FCLK:
956 member_type = METRICS_CURR_FCLK;
957 break;
958 case PPCLK_VCLK_0:
959 member_type = METRICS_CURR_VCLK;
960 break;
961 case PPCLK_VCLK_1:
962 member_type = METRICS_CURR_VCLK1;
963 break;
964 case PPCLK_DCLK_0:
965 member_type = METRICS_CURR_DCLK;
966 break;
967 case PPCLK_DCLK_1:
968 member_type = METRICS_CURR_DCLK1;
969 break;
970 case PPCLK_DCEFCLK:
971 member_type = METRICS_CURR_DCEFCLK;
972 break;
973 default:
974 return -EINVAL;
975 }
976
977 return sienna_cichlid_get_smu_metrics_data(smu,
978 member_type,
979 value);
b455159c 980
b455159c
LG		 981}
982
983static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
984{
b455159c 985 DpmDescriptor_t *dpm_desc = NULL;
7077b19a 986 DpmDescriptor_t *table_member;
b455159c
LG		 987 uint32_t clk_index = 0;
988
7077b19a 989 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
6c339f37
EQ		 990 clk_index = smu_cmn_to_asic_specific_index(smu,
991 CMN2ASIC_MAPPING_CLK,
992 clk_type);
7077b19a 993 dpm_desc = &table_member[clk_index];
b455159c
LG		 994
995 /* 0 - Fine grained DPM, 1 - Discrete DPM */
0ee56acc 996 return dpm_desc->SnapToDiscrete == 0;
b455159c
LG		 997}
998
37a58f69
EQ		 999static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
1000 enum SMU_11_0_7_ODFEATURE_CAP cap)
1001{
1002 return od_table->cap[cap];
1003}
1004
1005static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
1006 enum SMU_11_0_7_ODSETTING_ID setting,
1007 uint32_t *min, uint32_t *max)
1008{
1009 if (min)
1010 *min = od_table->min[setting];
1011 if (max)
1012 *max = od_table->max[setting];
1013}
1014
b455159c
LG		 1015static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
1016 enum smu_clk_type clk_type, char *buf)
1017{
b7d25b5f
LG		 1018 struct amdgpu_device *adev = smu->adev;
1019 struct smu_table_context *table_context = &smu->smu_table;
1020 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1021 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
7077b19a
CG		 1022 uint16_t *table_member;
1023
37a58f69
EQ		 1024 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
1025 OverDriveTable_t *od_table =
1026 (OverDriveTable_t *)table_context->overdrive_table;
b455159c
LG		 1027 int i, size = 0, ret = 0;
1028 uint32_t cur_value = 0, value = 0, count = 0;
1029 uint32_t freq_values[3] = {0};
1030 uint32_t mark_index = 0;
b7d25b5f 1031 uint32_t gen_speed, lane_width;
37a58f69 1032 uint32_t min_value, max_value;
a2b6df4f 1033 uint32_t smu_version;
b455159c 1034
8f48ba30
LY		 1035 smu_cmn_get_sysfs_buf(&buf, &size);
1036
b455159c
LG		 1037 switch (clk_type) {
1038 case SMU_GFXCLK:
1039 case SMU_SCLK:
1040 case SMU_SOCCLK:
1041 case SMU_MCLK:
1042 case SMU_UCLK:
1043 case SMU_FCLK:
78842457
DN		 1044 case SMU_VCLK:
1045 case SMU_VCLK1:
1046 case SMU_DCLK:
1047 case SMU_DCLK1:
b455159c 1048 case SMU_DCEFCLK:
5e6dc8fe 1049 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
b455159c 1050 if (ret)
258d290c 1051 goto print_clk_out;
b455159c 1052
d8d3493a 1053 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
b455159c 1054 if (ret)
258d290c 1055 goto print_clk_out;
b455159c
LG		 1056
1057 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1058 for (i = 0; i < count; i++) {
d8d3493a 1059 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
b455159c 1060 if (ret)
258d290c 1061 goto print_clk_out;
b455159c 1062
fe14c285 1063 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
b455159c
LG		 1064 cur_value == value ? "*" : "");
1065 }
1066 } else {
d8d3493a 1067 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
b455159c 1068 if (ret)
258d290c 1069 goto print_clk_out;
d8d3493a 1070 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
b455159c 1071 if (ret)
258d290c 1072 goto print_clk_out;
b455159c
LG		 1073
1074 freq_values[1] = cur_value;
1075 mark_index = cur_value == freq_values[0] ? 0 :
1076 cur_value == freq_values[2] ? 2 : 1;
b455159c 1077
891bacb8
KF		 1078 count = 3;
1079 if (mark_index != 1) {
1080 count = 2;
1081 freq_values[1] = freq_values[2];
1082 }
1083
1084 for (i = 0; i < count; i++) {
fe14c285 1085 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
891bacb8 1086 cur_value == freq_values[i] ? "*" : "");
b455159c
LG		 1087 }
1088
1089 }
1090 break;
b7d25b5f 1091 case SMU_PCIE:
f20c52f4
LG		 1092 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1093 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
7077b19a 1094 GET_PPTABLE_MEMBER(LclkFreq, &table_member);
b7d25b5f 1095 for (i = 0; i < NUM_LINK_LEVELS; i++)
fe14c285 1096 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
b7d25b5f
LG		 1097 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1098 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1099 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1100 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1101 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1102 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1103 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1104 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1105 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1106 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
7077b19a 1107 table_member[i],
b7d25b5f
LG		 1108 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1109 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1110 "*" : "");
1111 break;
37a58f69
EQ		 1112 case SMU_OD_SCLK:
1113 if (!smu->od_enabled || !od_table || !od_settings)
1114 break;
1115
1116 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1117 break;
1118
fe14c285
DP		 1119 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1120 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
37a58f69
EQ		 1121 break;
1122
1123 case SMU_OD_MCLK:
1124 if (!smu->od_enabled || !od_table || !od_settings)
1125 break;
1126
1127 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1128 break;
1129
fe14c285
DP		 1130 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1131 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
37a58f69
EQ		 1132 break;
1133
a2b6df4f
EQ		 1134 case SMU_OD_VDDGFX_OFFSET:
1135 if (!smu->od_enabled || !od_table || !od_settings)
1136 break;
1137
1138 /*
1139 * OD GFX Voltage Offset functionality is supported only by 58.41.0
1140 * and onwards SMU firmwares.
1141 */
1142 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1d789535 1143 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
a2b6df4f
EQ		 1144 (smu_version < 0x003a2900))
1145 break;
1146
fe14c285
DP		 1147 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1148 size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset);
a2b6df4f
EQ		 1149 break;
1150
37a58f69
EQ		 1151 case SMU_OD_RANGE:
1152 if (!smu->od_enabled || !od_table || !od_settings)
1153 break;
1154
8f48ba30 1155 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
37a58f69
EQ		 1156
1157 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1158 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1159 &min_value, NULL);
1160 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1161 NULL, &max_value);
fe14c285 1162 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
37a58f69
EQ		 1163 min_value, max_value);
1164 }
1165
1166 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1167 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1168 &min_value, NULL);
1169 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1170 NULL, &max_value);
fe14c285 1171 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
37a58f69
EQ		 1172 min_value, max_value);
1173 }
1174 break;
1175
b455159c
LG		 1176 default:
1177 break;
1178 }
1179
258d290c 1180print_clk_out:
b455159c
LG		 1181 return size;
1182}
1183
1184static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1185 enum smu_clk_type clk_type, uint32_t mask)
1186{
d3c98301 1187 int ret = 0;
b455159c
LG		 1188 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1189
1190 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1191 soft_max_level = mask ? (fls(mask) - 1) : 0;
1192
1193 switch (clk_type) {
1194 case SMU_GFXCLK:
1195 case SMU_SCLK:
1196 case SMU_SOCCLK:
1197 case SMU_MCLK:
1198 case SMU_UCLK:
b455159c 1199 case SMU_FCLK:
9ad9c8ac
LG		 1200 /* There is only 2 levels for fine grained DPM */
1201 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1202 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1203 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1204 }
1205
d8d3493a 1206 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
b455159c 1207 if (ret)
258d290c 1208 goto forec_level_out;
b455159c 1209
d8d3493a 1210 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
b455159c 1211 if (ret)
258d290c 1212 goto forec_level_out;
b455159c 1213
10e96d89 1214 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
b455159c 1215 if (ret)
258d290c 1216 goto forec_level_out;
b455159c 1217 break;
51ec6992
DP		 1218 case SMU_DCEFCLK:
1219 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1220 break;
b455159c
LG		 1221 default:
1222 break;
1223 }
1224
258d290c 1225forec_level_out:
d3c98301 1226 return 0;
b455159c
LG		 1227}
1228
1229static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1230{
62cc9dd1
EQ		 1231 struct smu_11_0_dpm_context *dpm_context =
1232 smu->smu_dpm.dpm_context;
1233 struct smu_11_0_dpm_table *gfx_table =
1234 &dpm_context->dpm_tables.gfx_table;
1235 struct smu_11_0_dpm_table *mem_table =
1236 &dpm_context->dpm_tables.uclk_table;
1237 struct smu_11_0_dpm_table *soc_table =
1238 &dpm_context->dpm_tables.soc_table;
1239 struct smu_umd_pstate_table *pstate_table =
1240 &smu->pstate_table;
1241
1242 pstate_table->gfxclk_pstate.min = gfx_table->min;
1243 pstate_table->gfxclk_pstate.peak = gfx_table->max;
0dc994fb
EQ		 1244 if (gfx_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK)
1245 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
62cc9dd1
EQ		 1246
1247 pstate_table->uclk_pstate.min = mem_table->min;
1248 pstate_table->uclk_pstate.peak = mem_table->max;
0dc994fb
EQ		 1249 if (mem_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK)
1250 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
62cc9dd1
EQ		 1251
1252 pstate_table->socclk_pstate.min = soc_table->min;
1253 pstate_table->socclk_pstate.peak = soc_table->max;
0dc994fb
EQ		 1254 if (soc_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK)
1255 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
b455159c 1256
62cc9dd1 1257 return 0;
b455159c
LG		 1258}
1259
b455159c
LG		 1260static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1261{
1262 int ret = 0;
1263 uint32_t max_freq = 0;
1264
1265 /* Sienna_Cichlid do not support to change display num currently */
1266 return 0;
1267#if 0
66c86828 1268 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
b455159c
LG		 1269 if (ret)
1270 return ret;
1271#endif
1272
b4bb3aaf 1273 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
e5ef784b 1274 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
b455159c
LG		 1275 if (ret)
1276 return ret;
661b94f5 1277 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
b455159c
LG		 1278 if (ret)
1279 return ret;
1280 }
1281
1282 return ret;
1283}
1284
1285static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1286{
1287 int ret = 0;
1288
b455159c 1289 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
4d942ae3
EQ		 1290 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1291 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
b455159c 1292#if 0
66c86828 1293 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
40d3b8db
LG		 1294 smu->display_config->num_display,
1295 NULL);
b455159c
LG		 1296#endif
1297 if (ret)
1298 return ret;
1299 }
1300
1301 return ret;
1302}
1303
b455159c
LG		 1304static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1305{
1306 int ret = 0;
1307 uint32_t feature_mask[2];
3d14a79b
KW		 1308 uint64_t feature_enabled;
1309
28251d72 1310 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
3d14a79b
KW		 1311 if (ret)
1312 return false;
1313
1314 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1315
b455159c
LG		 1316 return !!(feature_enabled & SMC_DPM_FEATURE);
1317}
1318
d9ca7567
EQ		 1319static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1320 uint32_t *speed)
1321{
1322 if (!speed)
1323 return -EINVAL;
1324
1325 /*
1326 * For Sienna_Cichlid and later, the fan speed(rpm) reported
1327 * by pmfw is always trustable(even when the fan control feature
1328 * disabled or 0 RPM kicked in).
1329 */
1330 return sienna_cichlid_get_smu_metrics_data(smu,
1331 METRICS_CURR_FANSPEED,
1332 speed);
1333}
1334
3204ff3e
AD		 1335static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1336{
7077b19a 1337 uint16_t *table_member;
3204ff3e 1338
7077b19a
CG		 1339 GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
1340 smu->fan_max_rpm = *table_member;
3204ff3e
AD		 1341
1342 return 0;
1343}
1344
b455159c
LG		 1345static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1346{
f9e3fe46
EQ		 1347 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1348 DpmActivityMonitorCoeffInt_t *activity_monitor =
1349 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
b455159c
LG		 1350 uint32_t i, size = 0;
1351 int16_t workload_type = 0;
b455159c
LG		 1352 static const char *title[] = {
1353 "PROFILE_INDEX(NAME)",
1354 "CLOCK_TYPE(NAME)",
1355 "FPS",
1356 "MinFreqType",
1357 "MinActiveFreqType",
1358 "MinActiveFreq",
1359 "BoosterFreqType",
1360 "BoosterFreq",
1361 "PD_Data_limit_c",
1362 "PD_Data_error_coeff",
1363 "PD_Data_error_rate_coeff"};
1364 int result = 0;
1365
1366 if (!buf)
1367 return -EINVAL;
1368
fe14c285 1369 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
b455159c
LG		 1370 title[0], title[1], title[2], title[3], title[4], title[5],
1371 title[6], title[7], title[8], title[9], title[10]);
1372
1373 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1374 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
6c339f37
EQ		 1375 workload_type = smu_cmn_to_asic_specific_index(smu,
1376 CMN2ASIC_MAPPING_WORKLOAD,
1377 i);
b455159c
LG		 1378 if (workload_type < 0)
1379 return -EINVAL;
1380
caad2613 1381 result = smu_cmn_update_table(smu,
b455159c 1382 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
f9e3fe46 1383 (void *)(&activity_monitor_external), false);
b455159c 1384 if (result) {
d9811cfc 1385 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
b455159c
LG		 1386 return result;
1387 }
1388
fe14c285 1389 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
94a80b5b 1390 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
b455159c 1391
fe14c285 1392 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
b455159c
LG		 1393 " ",
1394 0,
1395 "GFXCLK",
f9e3fe46
EQ		 1396 activity_monitor->Gfx_FPS,
1397 activity_monitor->Gfx_MinFreqStep,
1398 activity_monitor->Gfx_MinActiveFreqType,
1399 activity_monitor->Gfx_MinActiveFreq,
1400 activity_monitor->Gfx_BoosterFreqType,
1401 activity_monitor->Gfx_BoosterFreq,
1402 activity_monitor->Gfx_PD_Data_limit_c,
1403 activity_monitor->Gfx_PD_Data_error_coeff,
1404 activity_monitor->Gfx_PD_Data_error_rate_coeff);
b455159c 1405
fe14c285 1406 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
b455159c
LG		 1407 " ",
1408 1,
1409 "SOCCLK",
f9e3fe46
EQ		 1410 activity_monitor->Fclk_FPS,
1411 activity_monitor->Fclk_MinFreqStep,
1412 activity_monitor->Fclk_MinActiveFreqType,
1413 activity_monitor->Fclk_MinActiveFreq,
1414 activity_monitor->Fclk_BoosterFreqType,
1415 activity_monitor->Fclk_BoosterFreq,
1416 activity_monitor->Fclk_PD_Data_limit_c,
1417 activity_monitor->Fclk_PD_Data_error_coeff,
1418 activity_monitor->Fclk_PD_Data_error_rate_coeff);
b455159c 1419
fe14c285 1420 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
b455159c
LG		 1421 " ",
1422 2,
1423 "MEMLK",
f9e3fe46
EQ		 1424 activity_monitor->Mem_FPS,
1425 activity_monitor->Mem_MinFreqStep,
1426 activity_monitor->Mem_MinActiveFreqType,
1427 activity_monitor->Mem_MinActiveFreq,
1428 activity_monitor->Mem_BoosterFreqType,
1429 activity_monitor->Mem_BoosterFreq,
1430 activity_monitor->Mem_PD_Data_limit_c,
1431 activity_monitor->Mem_PD_Data_error_coeff,
1432 activity_monitor->Mem_PD_Data_error_rate_coeff);
b455159c
LG		 1433 }
1434
1435 return size;
1436}
1437
1438static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1439{
f9e3fe46
EQ		 1440
1441 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1442 DpmActivityMonitorCoeffInt_t *activity_monitor =
1443 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
b455159c
LG		 1444 int workload_type, ret = 0;
1445
1446 smu->power_profile_mode = input[size];
1447
1448 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
d9811cfc 1449 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
b455159c
LG		 1450 return -EINVAL;
1451 }
1452
1453 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
b455159c 1454
caad2613 1455 ret = smu_cmn_update_table(smu,
b455159c 1456 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
f9e3fe46 1457 (void *)(&activity_monitor_external), false);
b455159c 1458 if (ret) {
d9811cfc 1459 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
b455159c
LG		 1460 return ret;
1461 }
1462
1463 switch (input[0]) {
1464 case 0: /* Gfxclk */
f9e3fe46
EQ		 1465 activity_monitor->Gfx_FPS = input[1];
1466 activity_monitor->Gfx_MinFreqStep = input[2];
1467 activity_monitor->Gfx_MinActiveFreqType = input[3];
1468 activity_monitor->Gfx_MinActiveFreq = input[4];
1469 activity_monitor->Gfx_BoosterFreqType = input[5];
1470 activity_monitor->Gfx_BoosterFreq = input[6];
1471 activity_monitor->Gfx_PD_Data_limit_c = input[7];
1472 activity_monitor->Gfx_PD_Data_error_coeff = input[8];
1473 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1474 break;
1475 case 1: /* Socclk */
f9e3fe46
EQ		 1476 activity_monitor->Fclk_FPS = input[1];
1477 activity_monitor->Fclk_MinFreqStep = input[2];
1478 activity_monitor->Fclk_MinActiveFreqType = input[3];
1479 activity_monitor->Fclk_MinActiveFreq = input[4];
1480 activity_monitor->Fclk_BoosterFreqType = input[5];
1481 activity_monitor->Fclk_BoosterFreq = input[6];
1482 activity_monitor->Fclk_PD_Data_limit_c = input[7];
1483 activity_monitor->Fclk_PD_Data_error_coeff = input[8];
1484 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1485 break;
1486 case 2: /* Memlk */
f9e3fe46
EQ		 1487 activity_monitor->Mem_FPS = input[1];
1488 activity_monitor->Mem_MinFreqStep = input[2];
1489 activity_monitor->Mem_MinActiveFreqType = input[3];
1490 activity_monitor->Mem_MinActiveFreq = input[4];
1491 activity_monitor->Mem_BoosterFreqType = input[5];
1492 activity_monitor->Mem_BoosterFreq = input[6];
1493 activity_monitor->Mem_PD_Data_limit_c = input[7];
1494 activity_monitor->Mem_PD_Data_error_coeff = input[8];
1495 activity_monitor->Mem_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1496 break;
1497 }
1498
caad2613 1499 ret = smu_cmn_update_table(smu,
b455159c 1500 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
f9e3fe46 1501 (void *)(&activity_monitor_external), true);
b455159c 1502 if (ret) {
d9811cfc 1503 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
b455159c
LG		 1504 return ret;
1505 }
1506 }
1507
1508 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
6c339f37
EQ		 1509 workload_type = smu_cmn_to_asic_specific_index(smu,
1510 CMN2ASIC_MAPPING_WORKLOAD,
1511 smu->power_profile_mode);
b455159c
LG		 1512 if (workload_type < 0)
1513 return -EINVAL;
66c86828 1514 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
b455159c
LG		 1515 1 << workload_type, NULL);
1516
1517 return ret;
1518}
1519
b455159c
LG		 1520static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1521{
1522 struct smu_clocks min_clocks = {0};
1523 struct pp_display_clock_request clock_req;
1524 int ret = 0;
1525
1526 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1527 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1528 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1529
4d942ae3 1530 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
b455159c
LG		 1531 clock_req.clock_type = amd_pp_dcef_clock;
1532 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1533
1534 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1535 if (!ret) {
4d942ae3 1536 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
66c86828 1537 ret = smu_cmn_send_smc_msg_with_param(smu,
40d3b8db
LG		 1538 SMU_MSG_SetMinDeepSleepDcefclk,
1539 min_clocks.dcef_clock_in_sr/100,
1540 NULL);
1541 if (ret) {
d9811cfc 1542 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
40d3b8db
LG		 1543 return ret;
1544 }
b455159c
LG		 1545 }
1546 } else {
d9811cfc 1547 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
b455159c
LG		 1548 }
1549 }
1550
b4bb3aaf 1551 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
661b94f5 1552 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
b455159c 1553 if (ret) {
d9811cfc 1554 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
b455159c
LG		 1555 return ret;
1556 }
1557 }
1558
1559 return 0;
1560}
1561
1562static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
7b9c7e30 1563 struct pp_smu_wm_range_sets *clock_ranges)
b455159c 1564{
e7a95eea 1565 Watermarks_t *table = smu->smu_table.watermarks_table;
40d3b8db 1566 int ret = 0;
e7a95eea 1567 int i;
b455159c 1568
e7a95eea 1569 if (clock_ranges) {
7b9c7e30
EQ		 1570 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1571 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
e7a95eea
EQ		 1572 return -EINVAL;
1573
7b9c7e30
EQ		 1574 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1575 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1576 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1577 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1578 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1579 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1580 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1581 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1582 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1583
1584 table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1585 clock_ranges->reader_wm_sets[i].wm_inst;
e7a95eea 1586 }
b455159c 1587
7b9c7e30
EQ		 1588 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1589 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1590 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1591 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1592 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1593 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1594 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1595 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1596 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1597
1598 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1599 clock_ranges->writer_wm_sets[i].wm_inst;
e7a95eea
EQ		 1600 }
1601
1602 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1603 }
1604
1605 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1606 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
caad2613 1607 ret = smu_cmn_write_watermarks_table(smu);
40d3b8db 1608 if (ret) {
d9811cfc 1609 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
40d3b8db
LG		 1610 return ret;
1611 }
1612 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1613 }
1614
b455159c
LG		 1615 return 0;
1616}
1617
b455159c
LG		 1618static int sienna_cichlid_read_sensor(struct smu_context *smu,
1619 enum amd_pp_sensors sensor,
1620 void *data, uint32_t *size)
1621{
1622 int ret = 0;
7077b19a 1623 uint16_t *temp;
b455159c
LG		 1624
1625 if(!data || !size)
1626 return -EINVAL;
1627
1628 mutex_lock(&smu->sensor_lock);
1629 switch (sensor) {
1630 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
7077b19a
CG		 1631 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
1632 *(uint16_t *)data = *temp;
b455159c
LG		 1633 *size = 4;
1634 break;
1635 case AMDGPU_PP_SENSOR_MEM_LOAD:
60e317a2
AD		 1636 ret = sienna_cichlid_get_smu_metrics_data(smu,
1637 METRICS_AVERAGE_MEMACTIVITY,
1638 (uint32_t *)data);
1639 *size = 4;
1640 break;
b455159c 1641 case AMDGPU_PP_SENSOR_GPU_LOAD:
60e317a2
AD		 1642 ret = sienna_cichlid_get_smu_metrics_data(smu,
1643 METRICS_AVERAGE_GFXACTIVITY,
1644 (uint32_t *)data);
b455159c
LG		 1645 *size = 4;
1646 break;
1647 case AMDGPU_PP_SENSOR_GPU_POWER:
60e317a2
AD		 1648 ret = sienna_cichlid_get_smu_metrics_data(smu,
1649 METRICS_AVERAGE_SOCKETPOWER,
1650 (uint32_t *)data);
b455159c
LG		 1651 *size = 4;
1652 break;
1653 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
60e317a2
AD		 1654 ret = sienna_cichlid_get_smu_metrics_data(smu,
1655 METRICS_TEMPERATURE_HOTSPOT,
1656 (uint32_t *)data);
1657 *size = 4;
1658 break;
b455159c 1659 case AMDGPU_PP_SENSOR_EDGE_TEMP:
60e317a2
AD		 1660 ret = sienna_cichlid_get_smu_metrics_data(smu,
1661 METRICS_TEMPERATURE_EDGE,
1662 (uint32_t *)data);
1663 *size = 4;
1664 break;
b455159c 1665 case AMDGPU_PP_SENSOR_MEM_TEMP:
60e317a2
AD		 1666 ret = sienna_cichlid_get_smu_metrics_data(smu,
1667 METRICS_TEMPERATURE_MEM,
1668 (uint32_t *)data);
b455159c
LG		 1669 *size = 4;
1670 break;
e0f9e936
EQ		 1671 case AMDGPU_PP_SENSOR_GFX_MCLK:
1672 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1673 *(uint32_t *)data *= 100;
1674 *size = 4;
1675 break;
1676 case AMDGPU_PP_SENSOR_GFX_SCLK:
1677 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1678 *(uint32_t *)data *= 100;
1679 *size = 4;
1680 break;
b2febc99
EQ		 1681 case AMDGPU_PP_SENSOR_VDDGFX:
1682 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1683 *size = 4;
1684 break;
b455159c 1685 default:
b2febc99
EQ		 1686 ret = -EOPNOTSUPP;
1687 break;
b455159c
LG		 1688 }
1689 mutex_unlock(&smu->sensor_lock);
1690
1691 return ret;
1692}
1693
1694static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1695{
1696 uint32_t num_discrete_levels = 0;
1697 uint16_t *dpm_levels = NULL;
1698 uint16_t i = 0;
1699 struct smu_table_context *table_context = &smu->smu_table;
7077b19a
CG		 1700 DpmDescriptor_t *table_member1;
1701 uint16_t *table_member2;
b455159c
LG		 1702
1703 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1704 return -EINVAL;
1705
7077b19a
CG		 1706 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
1707 num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
1708 GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
1709 dpm_levels = table_member2;
b455159c
LG		 1710
1711 if (num_discrete_levels == 0 || dpm_levels == NULL)
1712 return -EINVAL;
1713
1714 *num_states = num_discrete_levels;
1715 for (i = 0; i < num_discrete_levels; i++) {
1716 /* convert to khz */
1717 *clocks_in_khz = (*dpm_levels) * 1000;
1718 clocks_in_khz++;
1719 dpm_levels++;
1720 }
1721
1722 return 0;
1723}
1724
1725static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1726 struct smu_temperature_range *range)
1727{
e02e4d51
EQ		 1728 struct smu_table_context *table_context = &smu->smu_table;
1729 struct smu_11_0_7_powerplay_table *powerplay_table =
1730 table_context->power_play_table;
7077b19a
CG		 1731 uint16_t *table_member;
1732 uint16_t temp_edge, temp_hotspot, temp_mem;
b455159c 1733
2b1f12a2 1734 if (!range)
b455159c
LG		 1735 return -EINVAL;
1736
0540eced
EQ		 1737 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1738
7077b19a
CG		 1739 GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
1740 temp_edge = table_member[TEMP_EDGE];
1741 temp_hotspot = table_member[TEMP_HOTSPOT];
1742 temp_mem = table_member[TEMP_MEM];
1743
1744 range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1745 range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
2b1f12a2 1746 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a
CG		 1747 range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1748 range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
2b1f12a2 1749 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a
CG		 1750 range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1751 range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
b455159c 1752 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a 1753
e02e4d51 1754 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
b455159c
LG		 1755
1756 return 0;
1757}
1758
1759static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1760 bool disable_memory_clock_switch)
1761{
1762 int ret = 0;
1763 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1764 (struct smu_11_0_max_sustainable_clocks *)
1765 smu->smu_table.max_sustainable_clocks;
1766 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1767 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1768
1769 if(smu->disable_uclk_switch == disable_memory_clock_switch)
1770 return 0;
1771
1772 if(disable_memory_clock_switch)
661b94f5 1773 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
b455159c 1774 else
661b94f5 1775 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
b455159c
LG		 1776
1777 if(!ret)
1778 smu->disable_uclk_switch = disable_memory_clock_switch;
1779
1780 return ret;
1781}
1782
488f211d
EQ		 1783static int sienna_cichlid_get_power_limit(struct smu_context *smu,
1784 uint32_t *current_power_limit,
1785 uint32_t *default_power_limit,
1786 uint32_t *max_power_limit)
b455159c 1787{
1e239fdd
EQ		 1788 struct smu_11_0_7_powerplay_table *powerplay_table =
1789 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
1e239fdd 1790 uint32_t power_limit, od_percent;
7077b19a
CG		 1791 uint16_t *table_member;
1792
1793 GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
1e239fdd
EQ		 1794
1795 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1e239fdd 1796 power_limit =
7077b19a 1797 table_member[PPT_THROTTLER_PPT0];
1e239fdd 1798 }
b455159c 1799
488f211d
EQ		 1800 if (current_power_limit)
1801 *current_power_limit = power_limit;
1802 if (default_power_limit)
1803 *default_power_limit = power_limit;
1e239fdd 1804
488f211d
EQ		 1805 if (max_power_limit) {
1806 if (smu->od_enabled) {
1807 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
1e239fdd 1808
488f211d
EQ		 1809 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1810
1811 power_limit *= (100 + od_percent);
1812 power_limit /= 100;
1813 }
1814 *max_power_limit = power_limit;
b455159c
LG		 1815 }
1816
b455159c
LG		 1817 return 0;
1818}
1819
08ccfe08
LG		 1820static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1821 uint32_t pcie_gen_cap,
1822 uint32_t pcie_width_cap)
1823{
0b590970 1824 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
7077b19a 1825
08ccfe08 1826 uint32_t smu_pcie_arg;
7077b19a 1827 uint8_t *table_member1, *table_member2;
0b590970 1828 int ret, i;
08ccfe08 1829
7077b19a
CG		 1830 GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
1831 GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
1832
0b590970
EQ		 1833 /* lclk dpm table setup */
1834 for (i = 0; i < MAX_PCIE_CONF; i++) {
7077b19a
CG		 1835 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = table_member1[i];
1836 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = table_member2[i];
0b590970 1837 }
08ccfe08
LG		 1838
1839 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1840 smu_pcie_arg = (i << 16) |
7077b19a
CG		 1841 ((table_member1[i] <= pcie_gen_cap) ?
1842 (table_member1[i] << 8) :
1843 (pcie_gen_cap << 8)) |
1844 ((table_member2[i] <= pcie_width_cap) ?
1845 table_member2[i] :
1846 pcie_width_cap);
08ccfe08 1847
66c86828 1848 ret = smu_cmn_send_smc_msg_with_param(smu,
7077b19a
CG		 1849 SMU_MSG_OverridePcieParameters,
1850 smu_pcie_arg,
1851 NULL);
08ccfe08
LG		 1852 if (ret)
1853 return ret;
1854
7077b19a 1855 if (table_member1[i] > pcie_gen_cap)
08ccfe08 1856 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
7077b19a 1857 if (table_member2[i] > pcie_width_cap)
08ccfe08
LG		 1858 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1859 }
1860
1861 return 0;
1862}
1863
38ed7b09 1864static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
258d290c
LG		 1865 enum smu_clk_type clk_type,
1866 uint32_t *min, uint32_t *max)
1867{
3bce90bf 1868 return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
258d290c
LG		 1869}
1870
aa75fa34
EQ		 1871static void sienna_cichlid_dump_od_table(struct smu_context *smu,
1872 OverDriveTable_t *od_table)
1873{
a2b6df4f
EQ		 1874 struct amdgpu_device *adev = smu->adev;
1875 uint32_t smu_version;
1876
aa75fa34
EQ		 1877 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
1878 od_table->GfxclkFmax);
1879 dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
1880 od_table->UclkFmax);
a2b6df4f
EQ		 1881
1882 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1d789535 1883 if (!((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
a2b6df4f
EQ		 1884 (smu_version < 0x003a2900)))
1885 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
aa75fa34
EQ		 1886}
1887
1888static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
1889{
1890 OverDriveTable_t *od_table =
1891 (OverDriveTable_t *)smu->smu_table.overdrive_table;
1892 OverDriveTable_t *boot_od_table =
1893 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
b521be9b
EQ		 1894 OverDriveTable_t *user_od_table =
1895 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
aa75fa34
EQ		 1896 int ret = 0;
1897
b521be9b
EQ		 1898 /*
1899 * For S3/S4/Runpm resume, no need to setup those overdrive tables again as
1900 * - either they already have the default OD settings got during cold bootup
1901 * - or they have some user customized OD settings which cannot be overwritten
1902 */
1903 if (smu->adev->in_suspend)
1904 return 0;
1905
aa75fa34 1906 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
b521be9b 1907 0, (void *)boot_od_table, false);
aa75fa34
EQ		 1908 if (ret) {
1909 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
1910 return ret;
1911 }
1912
b521be9b 1913 sienna_cichlid_dump_od_table(smu, boot_od_table);
aa75fa34 1914
b521be9b
EQ		 1915 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
1916 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
aa75fa34
EQ		 1917
1918 return 0;
1919}
1920
37a58f69
EQ		 1921static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
1922 struct smu_11_0_7_overdrive_table *od_table,
1923 enum SMU_11_0_7_ODSETTING_ID setting,
1924 uint32_t value)
1925{
1926 if (value < od_table->min[setting]) {
1927 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
1928 setting, value, od_table->min[setting]);
1929 return -EINVAL;
1930 }
1931 if (value > od_table->max[setting]) {
1932 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
1933 setting, value, od_table->max[setting]);
1934 return -EINVAL;
1935 }
1936
1937 return 0;
1938}
1939
1940static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
1941 enum PP_OD_DPM_TABLE_COMMAND type,
1942 long input[], uint32_t size)
1943{
1944 struct smu_table_context *table_context = &smu->smu_table;
1945 OverDriveTable_t *od_table =
1946 (OverDriveTable_t *)table_context->overdrive_table;
1947 struct smu_11_0_7_overdrive_table *od_settings =
1948 (struct smu_11_0_7_overdrive_table *)smu->od_settings;
a2b6df4f 1949 struct amdgpu_device *adev = smu->adev;
37a58f69
EQ		 1950 enum SMU_11_0_7_ODSETTING_ID freq_setting;
1951 uint16_t *freq_ptr;
1952 int i, ret = 0;
a2b6df4f 1953 uint32_t smu_version;
37a58f69
EQ		 1954
1955 if (!smu->od_enabled) {
1956 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
1957 return -EINVAL;
1958 }
1959
1960 if (!smu->od_settings) {
1961 dev_err(smu->adev->dev, "OD board limits are not set!\n");
1962 return -ENOENT;
1963 }
1964
1965 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
1966 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
1967 return -EINVAL;
1968 }
1969
1970 switch (type) {
1971 case PP_OD_EDIT_SCLK_VDDC_TABLE:
1972 if (!sienna_cichlid_is_od_feature_supported(od_settings,
1973 SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1974 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
1975 return -ENOTSUPP;
1976 }
1977
1978 for (i = 0; i < size; i += 2) {
1979 if (i + 2 > size) {
1980 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
1981 return -EINVAL;
1982 }
1983
1984 switch (input[i]) {
1985 case 0:
1986 if (input[i + 1] > od_table->GfxclkFmax) {
1987 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
1988 input[i + 1], od_table->GfxclkFmax);
1989 return -EINVAL;
1990 }
1991
1992 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
1993 freq_ptr = &od_table->GfxclkFmin;
1994 break;
1995
1996 case 1:
1997 if (input[i + 1] < od_table->GfxclkFmin) {
1998 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
1999 input[i + 1], od_table->GfxclkFmin);
2000 return -EINVAL;
2001 }
2002
2003 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
2004 freq_ptr = &od_table->GfxclkFmax;
2005 break;
2006
2007 default:
2008 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2009 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2010 return -EINVAL;
2011 }
2012
2013 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2014 freq_setting, input[i + 1]);
2015 if (ret)
2016 return ret;
2017
2018 *freq_ptr = (uint16_t)input[i + 1];
2019 }
2020 break;
2021
2022 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2023 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
2024 dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2025 return -ENOTSUPP;
2026 }
2027
2028 for (i = 0; i < size; i += 2) {
2029 if (i + 2 > size) {
2030 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2031 return -EINVAL;
2032 }
2033
2034 switch (input[i]) {
2035 case 0:
2036 if (input[i + 1] > od_table->UclkFmax) {
2037 dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2038 input[i + 1], od_table->UclkFmax);
2039 return -EINVAL;
2040 }
2041
2042 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
2043 freq_ptr = &od_table->UclkFmin;
2044 break;
2045
2046 case 1:
2047 if (input[i + 1] < od_table->UclkFmin) {
2048 dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2049 input[i + 1], od_table->UclkFmin);
2050 return -EINVAL;
2051 }
2052
2053 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
2054 freq_ptr = &od_table->UclkFmax;
2055 break;
2056
2057 default:
2058 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2059 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2060 return -EINVAL;
2061 }
2062
2063 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2064 freq_setting, input[i + 1]);
2065 if (ret)
2066 return ret;
2067
2068 *freq_ptr = (uint16_t)input[i + 1];
2069 }
2070 break;
2071
2072 case PP_OD_RESTORE_DEFAULT_TABLE:
2073 memcpy(table_context->overdrive_table,
2074 table_context->boot_overdrive_table,
2075 sizeof(OverDriveTable_t));
2076 fallthrough;
2077
2078 case PP_OD_COMMIT_DPM_TABLE:
b521be9b
EQ		 2079 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2080 sienna_cichlid_dump_od_table(smu, od_table);
2081 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2082 if (ret) {
2083 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2084 return ret;
2085 }
2086 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2087 smu->user_dpm_profile.user_od = true;
37a58f69 2088
b521be9b
EQ		 2089 if (!memcmp(table_context->user_overdrive_table,
2090 table_context->boot_overdrive_table,
2091 sizeof(OverDriveTable_t)))
2092 smu->user_dpm_profile.user_od = false;
37a58f69
EQ		 2093 }
2094 break;
2095
a2b6df4f
EQ		 2096 case PP_OD_EDIT_VDDGFX_OFFSET:
2097 if (size != 1) {
2098 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2099 return -EINVAL;
2100 }
2101
2102 /*
2103 * OD GFX Voltage Offset functionality is supported only by 58.41.0
2104 * and onwards SMU firmwares.
2105 */
2106 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1d789535 2107 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
a2b6df4f
EQ		 2108 (smu_version < 0x003a2900)) {
2109 dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2110 "only by 58.41.0 and onwards SMU firmwares!\n");
2111 return -EOPNOTSUPP;
2112 }
2113
2114 od_table->VddGfxOffset = (int16_t)input[0];
2115
2116 sienna_cichlid_dump_od_table(smu, od_table);
2117 break;
2118
37a58f69
EQ		 2119 default:
2120 return -ENOSYS;
2121 }
2122
2123 return ret;
2124}
2125
66b8a9c0
JC		 2126static int sienna_cichlid_run_btc(struct smu_context *smu)
2127{
dc78fea1
LT		 2128 int res;
2129
2130 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2131 if (res)
2132 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2133
2134 return res;
66b8a9c0
JC		 2135}
2136
13d75ead
EQ		 2137static int sienna_cichlid_baco_enter(struct smu_context *smu)
2138{
2139 struct amdgpu_device *adev = smu->adev;
2140
8b514e89 2141 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
13d75ead
EQ		 2142 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2143 else
2144 return smu_v11_0_baco_enter(smu);
2145}
2146
2147static int sienna_cichlid_baco_exit(struct smu_context *smu)
2148{
2149 struct amdgpu_device *adev = smu->adev;
2150
8b514e89 2151 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
13d75ead
EQ		 2152 /* Wait for PMFW handling for the Dstate change */
2153 msleep(10);
2154 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2155 } else {
2156 return smu_v11_0_baco_exit(smu);
2157 }
2158}
2159
ea8139d8
WS		 2160static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2161{
2162 struct amdgpu_device *adev = smu->adev;
2163 uint32_t val;
2164 u32 smu_version;
2165
2166 /**
2167 * SRIOV env will not support SMU mode1 reset
2168 * PM FW support mode1 reset from 58.26
2169 */
a7bae061 2170 smu_cmn_get_smc_version(smu, NULL, &smu_version);
ea8139d8
WS		 2171 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
2172 return false;
2173
2174 /**
2175 * mode1 reset relies on PSP, so we should check if
2176 * PSP is alive.
2177 */
2178 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2179 return val != 0x0;
2180}
2181
7077b19a
CG		 2182static void beige_goby_dump_pptable(struct smu_context *smu)
2183{
2184 struct smu_table_context *table_context = &smu->smu_table;
2185 PPTable_beige_goby_t *pptable = table_context->driver_pptable;
2186 int i;
2187
2188 dev_info(smu->adev->dev, "Dumped PPTable:\n");
2189
2190 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2191 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2192 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2193
2194 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2195 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2196 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2197 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2198 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2199 }
2200
2201 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2202 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2203 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2204 }
2205
2206 for (i = 0; i < TEMP_COUNT; i++) {
2207 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2208 }
2209
2210 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2211 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2212 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2213 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2214 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2215
2216 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2217 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2218 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2219 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2220 }
2221 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2222
2223 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2224
2225 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2226 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2227 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2228 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2229
2230 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2231
2232 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2233
2234 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2235 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2236 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2237 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2238
2239 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2240 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2241
2242 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2243 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2244 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2245 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2246 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2247 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2248 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2249 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2250
2251 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2252 " .VoltageMode = 0x%02x\n"
2253 " .SnapToDiscrete = 0x%02x\n"
2254 " .NumDiscreteLevels = 0x%02x\n"
2255 " .padding = 0x%02x\n"
2256 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2257 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2258 " .SsFmin = 0x%04x\n"
2259 " .Padding_16 = 0x%04x\n",
2260 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2261 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2262 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2263 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2264 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2265 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2266 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2267 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2268 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2269 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2270 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2271
2272 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2273 " .VoltageMode = 0x%02x\n"
2274 " .SnapToDiscrete = 0x%02x\n"
2275 " .NumDiscreteLevels = 0x%02x\n"
2276 " .padding = 0x%02x\n"
2277 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2278 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2279 " .SsFmin = 0x%04x\n"
2280 " .Padding_16 = 0x%04x\n",
2281 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2282 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2283 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2284 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2285 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2286 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2287 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2288 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2289 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2290 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2291 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2292
2293 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2294 " .VoltageMode = 0x%02x\n"
2295 " .SnapToDiscrete = 0x%02x\n"
2296 " .NumDiscreteLevels = 0x%02x\n"
2297 " .padding = 0x%02x\n"
2298 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2299 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2300 " .SsFmin = 0x%04x\n"
2301 " .Padding_16 = 0x%04x\n",
2302 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2303 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2304 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2305 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2306 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2307 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2308 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2309 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2310 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2311 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2312 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2313
2314 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2315 " .VoltageMode = 0x%02x\n"
2316 " .SnapToDiscrete = 0x%02x\n"
2317 " .NumDiscreteLevels = 0x%02x\n"
2318 " .padding = 0x%02x\n"
2319 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2320 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2321 " .SsFmin = 0x%04x\n"
2322 " .Padding_16 = 0x%04x\n",
2323 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2324 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2325 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2326 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2327 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2328 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2329 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2330 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2331 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2332 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2333 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2334
2335 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2336 " .VoltageMode = 0x%02x\n"
2337 " .SnapToDiscrete = 0x%02x\n"
2338 " .NumDiscreteLevels = 0x%02x\n"
2339 " .padding = 0x%02x\n"
2340 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2341 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2342 " .SsFmin = 0x%04x\n"
2343 " .Padding_16 = 0x%04x\n",
2344 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2345 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2346 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2347 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2348 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2349 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2350 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2351 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2352 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2353 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2354 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2355
2356 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2357 " .VoltageMode = 0x%02x\n"
2358 " .SnapToDiscrete = 0x%02x\n"
2359 " .NumDiscreteLevels = 0x%02x\n"
2360 " .padding = 0x%02x\n"
2361 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2362 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2363 " .SsFmin = 0x%04x\n"
2364 " .Padding_16 = 0x%04x\n",
2365 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2366 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2367 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2368 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2369 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2370 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2371 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2372 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2373 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2374 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2375 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2376
2377 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2378 " .VoltageMode = 0x%02x\n"
2379 " .SnapToDiscrete = 0x%02x\n"
2380 " .NumDiscreteLevels = 0x%02x\n"
2381 " .padding = 0x%02x\n"
2382 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2383 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2384 " .SsFmin = 0x%04x\n"
2385 " .Padding_16 = 0x%04x\n",
2386 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2387 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2388 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2389 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2390 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2391 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2392 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2393 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2394 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2395 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2396 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2397
2398 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2399 " .VoltageMode = 0x%02x\n"
2400 " .SnapToDiscrete = 0x%02x\n"
2401 " .NumDiscreteLevels = 0x%02x\n"
2402 " .padding = 0x%02x\n"
2403 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2404 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2405 " .SsFmin = 0x%04x\n"
2406 " .Padding_16 = 0x%04x\n",
2407 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2408 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2409 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2410 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2411 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2412 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2413 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2414 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2415 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2416 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2417 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2418
2419 dev_info(smu->adev->dev, "FreqTableGfx\n");
2420 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2421 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2422
2423 dev_info(smu->adev->dev, "FreqTableVclk\n");
2424 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2425 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2426
2427 dev_info(smu->adev->dev, "FreqTableDclk\n");
2428 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2429 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2430
2431 dev_info(smu->adev->dev, "FreqTableSocclk\n");
2432 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2433 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2434
2435 dev_info(smu->adev->dev, "FreqTableUclk\n");
2436 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2437 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2438
2439 dev_info(smu->adev->dev, "FreqTableFclk\n");
2440 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2441 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2442
2443 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2444 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2445 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2446 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2447 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2448 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2449 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2450 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2451 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2452
2453 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2454 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2455 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2456
2457 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2458 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2459
2460 dev_info(smu->adev->dev, "Mp0clkFreq\n");
2461 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2462 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2463
2464 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2465 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2466 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2467
2468 dev_info(smu->adev->dev, "MemVddciVoltage\n");
2469 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2470 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2471
2472 dev_info(smu->adev->dev, "MemMvddVoltage\n");
2473 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2474 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2475
2476 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2477 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2478 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2479 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2480 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2481
2482 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2483
2484 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2485 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2486 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2487 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2488 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2489 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2490 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2491 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2492 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2493 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2494 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2495
2496 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2497 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2498 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2499 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2500 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2501 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2502
2503 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2504 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2505 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2506 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2507 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2508
2509 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2510 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2511 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2512
2513 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2514 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2515 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2516 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2517
2518 dev_info(smu->adev->dev, "UclkDpmPstates\n");
2519 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2520 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2521
2522 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2523 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2524 pptable->UclkDpmSrcFreqRange.Fmin);
2525 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2526 pptable->UclkDpmSrcFreqRange.Fmax);
2527 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2528 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2529 pptable->UclkDpmTargFreqRange.Fmin);
2530 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2531 pptable->UclkDpmTargFreqRange.Fmax);
2532 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2533 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2534
2535 dev_info(smu->adev->dev, "PcieGenSpeed\n");
2536 for (i = 0; i < NUM_LINK_LEVELS; i++)
2537 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2538
2539 dev_info(smu->adev->dev, "PcieLaneCount\n");
2540 for (i = 0; i < NUM_LINK_LEVELS; i++)
2541 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2542
2543 dev_info(smu->adev->dev, "LclkFreq\n");
2544 for (i = 0; i < NUM_LINK_LEVELS; i++)
2545 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2546
2547 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2548 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2549
2550 dev_info(smu->adev->dev, "FanGain\n");
2551 for (i = 0; i < TEMP_COUNT; i++)
2552 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2553
2554 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2555 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2556 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2557 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2558 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2559 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2560 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2561 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2562 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2563 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2564 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2565 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2566
2567 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2568 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2569 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2570 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2571
2572 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2573 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2574 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2575 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2576
2577 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2578 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2579 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2580 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2581 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2582 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2583 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2584 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2585 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2586 pptable->dBtcGbGfxPll.a,
2587 pptable->dBtcGbGfxPll.b,
2588 pptable->dBtcGbGfxPll.c);
2589 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2590 pptable->dBtcGbGfxDfll.a,
2591 pptable->dBtcGbGfxDfll.b,
2592 pptable->dBtcGbGfxDfll.c);
2593 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2594 pptable->dBtcGbSoc.a,
2595 pptable->dBtcGbSoc.b,
2596 pptable->dBtcGbSoc.c);
2597 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2598 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2599 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2600 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2601 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2602 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2603
2604 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2605 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2606 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
2607 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2608 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
2609 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2610 }
2611
2612 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2613 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2614 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2615 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2616 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2617 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2618 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2619 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2620
2621 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2622 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2623
2624 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2625 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2626 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2627 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2628
2629 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2630 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2631 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2632 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2633
2634 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2635 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2636
2637 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2638 for (i = 0; i < NUM_XGMI_LEVELS; i++)
2639 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2640 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2641 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2642
2643 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2644 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2645 pptable->ReservedEquation0.a,
2646 pptable->ReservedEquation0.b,
2647 pptable->ReservedEquation0.c);
2648 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2649 pptable->ReservedEquation1.a,
2650 pptable->ReservedEquation1.b,
2651 pptable->ReservedEquation1.c);
2652 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2653 pptable->ReservedEquation2.a,
2654 pptable->ReservedEquation2.b,
2655 pptable->ReservedEquation2.c);
2656 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2657 pptable->ReservedEquation3.a,
2658 pptable->ReservedEquation3.b,
2659 pptable->ReservedEquation3.c);
2660
2661 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2662 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2663 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2664 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2665 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2666 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2667 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2668 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2669
2670 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2671 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2672 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2673 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2674 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2675 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2676
2677 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2678 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2679 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
2680 pptable->I2cControllers[i].Enabled);
2681 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
2682 pptable->I2cControllers[i].Speed);
2683 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
2684 pptable->I2cControllers[i].SlaveAddress);
2685 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
2686 pptable->I2cControllers[i].ControllerPort);
2687 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
2688 pptable->I2cControllers[i].ControllerName);
2689 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
2690 pptable->I2cControllers[i].ThermalThrotter);
2691 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
2692 pptable->I2cControllers[i].I2cProtocol);
2693 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
2694 pptable->I2cControllers[i].PaddingConfig);
2695 }
2696
2697 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2698 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2699 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2700 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2701
2702 dev_info(smu->adev->dev, "Board Parameters:\n");
2703 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2704 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2705 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2706 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2707 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2708 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2709 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2710 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2711
2712 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2713 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2714 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2715
2716 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2717 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2718 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2719
2720 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2721 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2722 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2723
2724 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2725 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2726 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2727
2728 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2729
2730 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2731 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2732 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2733 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2734 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2735 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2736 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2737 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2738 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2739 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2740 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2741 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2742 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2743 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2744 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2745 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2746
2747 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2748 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2749 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
2750
2751 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2752 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2753 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
2754
2755 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
2756 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2757
2758 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2759 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2760 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2761
2762 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2763 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2764 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2765 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2766 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2767
2768 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2769 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2770
2771 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
2772 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2773 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2774 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
2775 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2776 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2777 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
2778 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2779 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2780 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
2781 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2782 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2783
2784 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2785 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2786 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2787 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2788
2789 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2790 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2791 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2792 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2793 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2794 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2795 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2796 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2797 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2798 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2799 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2800
2801 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2802 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2803 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2804 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2805 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2806 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2807 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2808 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2809}
2810
b455159c
LG		 2811static void sienna_cichlid_dump_pptable(struct smu_context *smu)
2812{
2813 struct smu_table_context *table_context = &smu->smu_table;
2814 PPTable_t *pptable = table_context->driver_pptable;
2815 int i;
2816
1d789535 2817 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) {
7077b19a
CG		 2818 beige_goby_dump_pptable(smu);
2819 return;
2820 }
2821
d9811cfc 2822 dev_info(smu->adev->dev, "Dumped PPTable:\n");
b455159c 2823
d9811cfc
EQ		 2824 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2825 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2826 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
b455159c
LG		 2827
2828 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
d9811cfc
EQ		 2829 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2830 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2831 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2832 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
b455159c
LG		 2833 }
2834
2835 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
d9811cfc
EQ		 2836 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2837 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
b455159c
LG		 2838 }
2839
2840 for (i = 0; i < TEMP_COUNT; i++) {
d9811cfc 2841 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
b455159c
LG		 2842 }
2843
d9811cfc
EQ		 2844 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2845 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2846 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2847 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2848 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
b455159c 2849
d9811cfc 2850 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
b455159c 2851 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
d9811cfc
EQ		 2852 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2853 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
b455159c 2854 }
d9811cfc
EQ		 2855 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2856
2857 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2858
2859 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2860 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2861 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2862 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2863
2864 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2865 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
2866
2867 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2868 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
2869 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
2870 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
2871
2872 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2873 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2874 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2875 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2876
2877 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2878 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2879
2880 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2881 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2882 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2883 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2884 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2885 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2886 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2887 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2888
2889 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
b455159c
LG		 2890 " .VoltageMode = 0x%02x\n"
2891 " .SnapToDiscrete = 0x%02x\n"
2892 " .NumDiscreteLevels = 0x%02x\n"
2893 " .padding = 0x%02x\n"
2894 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2895 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2896 " .SsFmin = 0x%04x\n"
2897 " .Padding_16 = 0x%04x\n",
2898 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2899 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2900 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2901 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2902 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2903 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2904 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2905 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2906 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2907 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2908 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2909
d9811cfc 2910 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
b455159c
LG		 2911 " .VoltageMode = 0x%02x\n"
2912 " .SnapToDiscrete = 0x%02x\n"
2913 " .NumDiscreteLevels = 0x%02x\n"
2914 " .padding = 0x%02x\n"
2915 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2916 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2917 " .SsFmin = 0x%04x\n"
2918 " .Padding_16 = 0x%04x\n",
2919 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2920 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2921 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2922 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2923 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2924 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2925 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2926 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2927 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2928 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2929 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2930
d9811cfc 2931 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
b455159c
LG		 2932 " .VoltageMode = 0x%02x\n"
2933 " .SnapToDiscrete = 0x%02x\n"
2934 " .NumDiscreteLevels = 0x%02x\n"
2935 " .padding = 0x%02x\n"
2936 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2937 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2938 " .SsFmin = 0x%04x\n"
2939 " .Padding_16 = 0x%04x\n",
2940 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2941 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2942 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2943 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2944 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2945 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2946 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2947 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2948 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2949 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2950 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2951
d9811cfc 2952 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
b455159c
LG		 2953 " .VoltageMode = 0x%02x\n"
2954 " .SnapToDiscrete = 0x%02x\n"
2955 " .NumDiscreteLevels = 0x%02x\n"
2956 " .padding = 0x%02x\n"
2957 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2958 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2959 " .SsFmin = 0x%04x\n"
2960 " .Padding_16 = 0x%04x\n",
2961 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2962 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2963 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2964 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2965 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2966 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2967 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2968 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2969 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2970 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2971 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2972
d9811cfc 2973 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
b455159c
LG		 2974 " .VoltageMode = 0x%02x\n"
2975 " .SnapToDiscrete = 0x%02x\n"
2976 " .NumDiscreteLevels = 0x%02x\n"
2977 " .padding = 0x%02x\n"
2978 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2979 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2980 " .SsFmin = 0x%04x\n"
2981 " .Padding_16 = 0x%04x\n",
2982 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2983 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2984 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2985 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2986 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2987 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2988 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2989 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2990 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2991 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2992 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2993
d9811cfc 2994 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
b455159c
LG		 2995 " .VoltageMode = 0x%02x\n"
2996 " .SnapToDiscrete = 0x%02x\n"
2997 " .NumDiscreteLevels = 0x%02x\n"
2998 " .padding = 0x%02x\n"
2999 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3000 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3001 " .SsFmin = 0x%04x\n"
3002 " .Padding_16 = 0x%04x\n",
3003 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
3004 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
3005 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
3006 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
3007 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
3008 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
3009 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
3010 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
3011 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
3012 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
3013 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
3014
d9811cfc 3015 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
b455159c
LG		 3016 " .VoltageMode = 0x%02x\n"
3017 " .SnapToDiscrete = 0x%02x\n"
3018 " .NumDiscreteLevels = 0x%02x\n"
3019 " .padding = 0x%02x\n"
3020 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3021 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3022 " .SsFmin = 0x%04x\n"
3023 " .Padding_16 = 0x%04x\n",
3024 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
3025 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
3026 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
3027 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
3028 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
3029 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
3030 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
3031 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
3032 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
3033 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
3034 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
3035
d9811cfc 3036 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
b455159c
LG		 3037 " .VoltageMode = 0x%02x\n"
3038 " .SnapToDiscrete = 0x%02x\n"
3039 " .NumDiscreteLevels = 0x%02x\n"
3040 " .padding = 0x%02x\n"
3041 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3042 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3043 " .SsFmin = 0x%04x\n"
3044 " .Padding_16 = 0x%04x\n",
3045 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
3046 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
3047 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
3048 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
3049 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
3050 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
3051 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
3052 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
3053 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
3054 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
3055 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
3056
d9811cfc 3057 dev_info(smu->adev->dev, "FreqTableGfx\n");
b455159c 3058 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
d9811cfc 3059 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
b455159c 3060
d9811cfc 3061 dev_info(smu->adev->dev, "FreqTableVclk\n");
b455159c 3062 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
d9811cfc 3063 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
b455159c 3064
d9811cfc 3065 dev_info(smu->adev->dev, "FreqTableDclk\n");
b455159c 3066 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
d9811cfc 3067 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
b455159c 3068
d9811cfc 3069 dev_info(smu->adev->dev, "FreqTableSocclk\n");
b455159c 3070 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
d9811cfc 3071 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
b455159c 3072
d9811cfc 3073 dev_info(smu->adev->dev, "FreqTableUclk\n");
b455159c 3074 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3075 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
b455159c 3076
d9811cfc 3077 dev_info(smu->adev->dev, "FreqTableFclk\n");
b455159c 3078 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
d9811cfc
EQ		 3079 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
3080
d9811cfc
EQ		 3081 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
3082 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
3083 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
3084 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
3085 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
3086 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
3087 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
3088 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
3089 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
3090
3091 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
b455159c 3092 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3093 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
b455159c 3094
d9811cfc
EQ		 3095 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
3096 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
b455159c 3097
d9811cfc 3098 dev_info(smu->adev->dev, "Mp0clkFreq\n");
b455159c 3099 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc 3100 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
b455159c 3101
d9811cfc 3102 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
b455159c 3103 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc 3104 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
b455159c 3105
d9811cfc 3106 dev_info(smu->adev->dev, "MemVddciVoltage\n");
b455159c 3107 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3108 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
b455159c 3109
d9811cfc 3110 dev_info(smu->adev->dev, "MemMvddVoltage\n");
b455159c 3111 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc
EQ		 3112 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
3113
3114 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
3115 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
3116 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
3117 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
3118 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
3119
3120 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
3121
3122 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
3123 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
3124 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
3125 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
3126 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
3127 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
3128 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
3129 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
3130 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
3131 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
3132 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
3133
3134 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
3135 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
3136 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
3137 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
3138 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
3139 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
3140
3141 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
3142 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
3143 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
3144 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
3145 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
3146
3147 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
b455159c 3148 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
d9811cfc 3149 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
b455159c 3150
d9811cfc
EQ		 3151 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
3152 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
3153 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
3154 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
b455159c 3155
d9811cfc 3156 dev_info(smu->adev->dev, "UclkDpmPstates\n");
b455159c 3157 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3158 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
b455159c 3159
d9811cfc
EQ		 3160 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
3161 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
b455159c 3162 pptable->UclkDpmSrcFreqRange.Fmin);
d9811cfc 3163 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
b455159c 3164 pptable->UclkDpmSrcFreqRange.Fmax);
d9811cfc
EQ		 3165 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
3166 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
b455159c 3167 pptable->UclkDpmTargFreqRange.Fmin);
d9811cfc 3168 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
b455159c 3169 pptable->UclkDpmTargFreqRange.Fmax);
d9811cfc
EQ		 3170 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
3171 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
b455159c 3172
d9811cfc 3173 dev_info(smu->adev->dev, "PcieGenSpeed\n");
b455159c 3174 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3175 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
b455159c 3176
d9811cfc 3177 dev_info(smu->adev->dev, "PcieLaneCount\n");
b455159c 3178 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3179 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
b455159c 3180
d9811cfc 3181 dev_info(smu->adev->dev, "LclkFreq\n");
b455159c 3182 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3183 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
b455159c 3184
d9811cfc
EQ		 3185 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
3186 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
b455159c 3187
d9811cfc 3188 dev_info(smu->adev->dev, "FanGain\n");
b455159c 3189 for (i = 0; i < TEMP_COUNT; i++)
d9811cfc
EQ		 3190 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
3191
3192 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
3193 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
3194 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
3195 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
3196 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
3197 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
3198 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
3199 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
3200 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
3201 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
3202 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
3203 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
3204
3205 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
3206 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
3207 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
3208 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
3209
3210 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
3211 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
3212 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
3213 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
3214
3215 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3216 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
3217 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
3218 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
d9811cfc 3219 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3220 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
3221 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
3222 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
d9811cfc 3223 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3224 pptable->dBtcGbGfxPll.a,
3225 pptable->dBtcGbGfxPll.b,
3226 pptable->dBtcGbGfxPll.c);
d9811cfc 3227 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3228 pptable->dBtcGbGfxDfll.a,
3229 pptable->dBtcGbGfxDfll.b,
3230 pptable->dBtcGbGfxDfll.c);
d9811cfc 3231 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3232 pptable->dBtcGbSoc.a,
3233 pptable->dBtcGbSoc.b,
3234 pptable->dBtcGbSoc.c);
d9811cfc 3235 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
b455159c
LG		 3236 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
3237 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
d9811cfc 3238 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
b455159c
LG		 3239 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
3240 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
3241
d9811cfc 3242 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
b455159c 3243 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
d9811cfc 3244 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
b455159c 3245 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
d9811cfc 3246 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
b455159c
LG		 3247 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
3248 }
3249
d9811cfc 3250 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3251 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
3252 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
3253 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
d9811cfc 3254 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3255 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
3256 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
3257 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
3258
d9811cfc
EQ		 3259 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
3260 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
b455159c 3261
d9811cfc
EQ		 3262 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
3263 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
3264 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
3265 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
b455159c 3266
d9811cfc
EQ		 3267 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
3268 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
3269 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
3270 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
b455159c 3271
d9811cfc
EQ		 3272 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
3273 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
b455159c 3274
d9811cfc 3275 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
b455159c 3276 for (i = 0; i < NUM_XGMI_LEVELS; i++)
d9811cfc
EQ		 3277 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
3278 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
3279 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
b455159c 3280
d9811cfc
EQ		 3281 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
3282 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3283 pptable->ReservedEquation0.a,
3284 pptable->ReservedEquation0.b,
3285 pptable->ReservedEquation0.c);
d9811cfc 3286 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3287 pptable->ReservedEquation1.a,
3288 pptable->ReservedEquation1.b,
3289 pptable->ReservedEquation1.c);
d9811cfc 3290 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3291 pptable->ReservedEquation2.a,
3292 pptable->ReservedEquation2.b,
3293 pptable->ReservedEquation2.c);
d9811cfc 3294 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3295 pptable->ReservedEquation3.a,
3296 pptable->ReservedEquation3.b,
3297 pptable->ReservedEquation3.c);
3298
d9811cfc
EQ		 3299 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3300 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3301 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3302 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3303 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3304 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3305 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3306 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
d9811cfc
EQ		 3307
3308 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3309 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3310 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3311 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3312 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3313 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
b455159c
LG		 3314
3315 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
d9811cfc
EQ		 3316 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3317 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
b455159c 3318 pptable->I2cControllers[i].Enabled);
d9811cfc 3319 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
b455159c 3320 pptable->I2cControllers[i].Speed);
d9811cfc 3321 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
b455159c 3322 pptable->I2cControllers[i].SlaveAddress);
d9811cfc 3323 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
b455159c 3324 pptable->I2cControllers[i].ControllerPort);
d9811cfc 3325 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
b455159c 3326 pptable->I2cControllers[i].ControllerName);
d9811cfc 3327 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
b455159c 3328 pptable->I2cControllers[i].ThermalThrotter);
d9811cfc 3329 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
b455159c 3330 pptable->I2cControllers[i].I2cProtocol);
d9811cfc 3331 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
b455159c
LG		 3332 pptable->I2cControllers[i].PaddingConfig);
3333 }
3334
d9811cfc
EQ		 3335 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3336 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3337 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3338 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3339
3340 dev_info(smu->adev->dev, "Board Parameters:\n");
3341 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3342 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3343 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3344 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3345 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3346 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3347 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3348 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3349
3350 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3351 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3352 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3353
3354 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3355 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3356 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3357
3358 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3359 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3360 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3361
3362 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3363 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3364 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3365
3366 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3367
3368 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3369 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3370 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3371 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3372 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3373 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3374 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3375 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3376 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3377 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3378 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3379 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3380 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3381 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3382 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3383 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3384
3385 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3386 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3387 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3388
3389 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3390 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3391 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3392
f0f3d68e 3393 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
d9811cfc
EQ		 3394 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3395
3396 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3397 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3398 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3399
3400 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3401 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3402 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3403 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3404 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3405
3406 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3407 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3408
3409 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
b455159c 3410 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3411 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3412 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
b455159c 3413 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3414 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3415 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
b455159c 3416 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3417 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3418 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
b455159c 3419 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3420 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3421
3422 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3423 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3424 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3425 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3426
3427 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3428 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3429 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3430 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3431 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3432 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3433 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3434 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3435 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3436 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3437 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
d9811cfc
EQ		 3438
3439 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3440 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3441 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3442 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3443 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3444 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3445 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3446 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
b455159c
LG		 3447}
3448
5125c96a 3449static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
ebe57d0c 3450 struct i2c_msg *msg, int num_msgs)
bc50ca29 3451{
5125c96a 3452 struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
ebfc2533
EQ		 3453 struct smu_context *smu = adev->powerplay.pp_handle;
3454 struct smu_table_context *smu_table = &smu->smu_table;
bc50ca29 3455 struct smu_table *table = &smu_table->driver_table;
5125c96a 3456 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
ebe57d0c
LT		 3457 int i, j, r, c;
3458 u16 dir;
d74a09c8 3459
5125c96a
AD		 3460 req = kzalloc(sizeof(*req), GFP_KERNEL);
3461 if (!req)
3462 return -ENOMEM;
bc50ca29 3463
5125c96a
AD		 3464 req->I2CcontrollerPort = 1;
3465 req->I2CSpeed = I2C_SPEED_FAST_400K;
ebe57d0c
LT		 3466 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
3467 dir = msg[0].flags & I2C_M_RD;
bc50ca29 3468
ebe57d0c
LT		 3469 for (c = i = 0; i < num_msgs; i++) {
3470 for (j = 0; j < msg[i].len; j++, c++) {
3471 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
bc50ca29 3472
5125c96a
AD		 3473 if (!(msg[i].flags & I2C_M_RD)) {
3474 /* write */
3475 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
ebe57d0c
LT		 3476 cmd->ReadWriteData = msg[i].buf[j];
3477 }
3478
3479 if ((dir ^ msg[i].flags) & I2C_M_RD) {
3480 /* The direction changes.
3481 */
3482 dir = msg[i].flags & I2C_M_RD;
3483 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
5125c96a 3484 }
14df5650 3485
ebe57d0c
LT		 3486 req->NumCmds++;
3487
14df5650
AG		 3488 /*
3489 * Insert STOP if we are at the last byte of either last
3490 * message for the transaction or the client explicitly
3491 * requires a STOP at this particular message.
3492 */
ebe57d0c
LT		 3493 if ((j == msg[i].len - 1) &&
3494 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
3495 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
5125c96a 3496 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
ebe57d0c 3497 }
5125c96a 3498 }
d74a09c8 3499 }
ebfc2533
EQ		 3500 mutex_lock(&smu->mutex);
3501 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
3502 mutex_unlock(&smu->mutex);
5125c96a
AD		 3503 if (r)
3504 goto fail;
bc50ca29 3505
ebe57d0c
LT		 3506 for (c = i = 0; i < num_msgs; i++) {
3507 if (!(msg[i].flags & I2C_M_RD)) {
3508 c += msg[i].len;
3509 continue;
3510 }
3511 for (j = 0; j < msg[i].len; j++, c++) {
3512 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
bc50ca29 3513
ebe57d0c 3514 msg[i].buf[j] = cmd->ReadWriteData;
bc50ca29
AD		 3515 }
3516 }
ebe57d0c 3517 r = num_msgs;
bc50ca29 3518fail:
5125c96a 3519 kfree(req);
5125c96a 3520 return r;
bc50ca29
AD		 3521}
3522
3523static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
3524{
3525 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3526}
3527
3528
3529static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
3530 .master_xfer = sienna_cichlid_i2c_xfer,
3531 .functionality = sienna_cichlid_i2c_func,
3532};
3533
35ed2703 3534static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = {
c0838d3a 3535 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
16736627 3536 .max_read_len = MAX_SW_I2C_COMMANDS,
35ed2703 3537 .max_write_len = MAX_SW_I2C_COMMANDS,
16736627
LT		 3538 .max_comb_1st_msg_len = 2,
3539 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
35ed2703
AG		 3540};
3541
bc50ca29
AD		 3542static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
3543{
3544 struct amdgpu_device *adev = to_amdgpu_device(control);
3545 int res;
3546
bc50ca29 3547 control->owner = THIS_MODULE;
f4322d80 3548 control->class = I2C_CLASS_HWMON;
bc50ca29
AD		 3549 control->dev.parent = &adev->pdev->dev;
3550 control->algo = &sienna_cichlid_i2c_algo;
3551 snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
35ed2703 3552 control->quirks = &sienna_cichlid_i2c_control_quirks;
bc50ca29
AD		 3553
3554 res = i2c_add_adapter(control);
3555 if (res)
3556 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3557
3558 return res;
3559}
3560
3561static void sienna_cichlid_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
3562{
bc50ca29
AD		 3563 i2c_del_adapter(control);
3564}
3565
8ca78a0a
EQ		 3566static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
3567 void **table)
3568{
3569 struct smu_table_context *smu_table = &smu->smu_table;
f06d9511
GS		 3570 struct gpu_metrics_v1_3 *gpu_metrics =
3571 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
b4b0b79d
EQ		 3572 SmuMetricsExternal_t metrics_external;
3573 SmuMetrics_t *metrics =
3574 &(metrics_external.SmuMetrics);
be22e2b9
EQ		 3575 SmuMetrics_V2_t *metrics_v2 =
3576 &(metrics_external.SmuMetrics_V2);
c524c1c9 3577 struct amdgpu_device *adev = smu->adev;
1d789535 3578 bool use_metrics_v2 = ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
be22e2b9
EQ		 3579 (smu->smc_fw_version >= 0x3A4300)) ? true : false;
3580 uint16_t average_gfx_activity;
8ca78a0a
EQ		 3581 int ret = 0;
3582
be22e2b9
EQ		 3583 mutex_lock(&smu->metrics_lock);
3584 ret = smu_cmn_get_metrics_table_locked(smu,
3585 &metrics_external,
3586 true);
3587 if (ret) {
3588 mutex_unlock(&smu->metrics_lock);
8ca78a0a 3589 return ret;
be22e2b9 3590 }
8ca78a0a 3591
f06d9511 3592 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
8ca78a0a 3593
be22e2b9
EQ		 3594 gpu_metrics->temperature_edge =
3595 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge;
3596 gpu_metrics->temperature_hotspot =
3597 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot;
3598 gpu_metrics->temperature_mem =
3599 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem;
3600 gpu_metrics->temperature_vrgfx =
3601 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx;
3602 gpu_metrics->temperature_vrsoc =
3603 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc;
3604 gpu_metrics->temperature_vrmem =
3605 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0;
3606
3607 gpu_metrics->average_gfx_activity =
3608 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3609 gpu_metrics->average_umc_activity =
3610 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity;
3611 gpu_metrics->average_mm_activity =
3612 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage;
3613
3614 gpu_metrics->average_socket_power =
3615 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower;
3616 gpu_metrics->energy_accumulator =
3617 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator;
3618
3a50403f
SK		 3619 if (metrics->CurrGfxVoltageOffset)
3620 gpu_metrics->voltage_gfx =
3621 (155000 - 625 * metrics->CurrGfxVoltageOffset) / 100;
3622 if (metrics->CurrMemVidOffset)
3623 gpu_metrics->voltage_mem =
3624 (155000 - 625 * metrics->CurrMemVidOffset) / 100;
3625 if (metrics->CurrSocVoltageOffset)
3626 gpu_metrics->voltage_soc =
3627 (155000 - 625 * metrics->CurrSocVoltageOffset) / 100;
3628
be22e2b9
EQ		 3629 average_gfx_activity = use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3630 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
3631 gpu_metrics->average_gfxclk_frequency =
3632 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs : metrics->AverageGfxclkFrequencyPostDs;
8ca78a0a 3633 else
be22e2b9
EQ		 3634 gpu_metrics->average_gfxclk_frequency =
3635 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs : metrics->AverageGfxclkFrequencyPreDs;
3636 gpu_metrics->average_uclk_frequency =
3637 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs : metrics->AverageUclkFrequencyPostDs;
3638 gpu_metrics->average_vclk0_frequency =
3639 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency;
3640 gpu_metrics->average_dclk0_frequency =
3641 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency;
3642 gpu_metrics->average_vclk1_frequency =
3643 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency;
3644 gpu_metrics->average_dclk1_frequency =
3645 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency;
3646
3647 gpu_metrics->current_gfxclk =
3648 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK];
3649 gpu_metrics->current_socclk =
3650 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK];
3651 gpu_metrics->current_uclk =
3652 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK];
3653 gpu_metrics->current_vclk0 =
3654 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0];
3655 gpu_metrics->current_dclk0 =
3656 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0];
3657 gpu_metrics->current_vclk1 =
3658 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1];
3659 gpu_metrics->current_dclk1 =
3660 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1];
3661
3662 gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu);
f06d9511 3663 gpu_metrics->indep_throttle_status =
be22e2b9 3664 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
f06d9511 3665 sienna_cichlid_throttler_map);
b4b0b79d 3666
be22e2b9 3667 gpu_metrics->current_fan_speed = use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
c524c1c9 3668
1d789535
AD		 3669 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) ||
3670 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) {
be22e2b9
EQ		 3671 gpu_metrics->pcie_link_width = use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
3672 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
c524c1c9
EQ		 3673 } else {
3674 gpu_metrics->pcie_link_width =
3675 smu_v11_0_get_current_pcie_link_width(smu);
3676 gpu_metrics->pcie_link_speed =
3677 smu_v11_0_get_current_pcie_link_speed(smu);
3678 }
8ca78a0a 3679
be22e2b9
EQ		 3680 mutex_unlock(&smu->metrics_lock);
3681
de4b7cd8
KW		 3682 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3683
8ca78a0a
EQ		 3684 *table = (void *)gpu_metrics;
3685
f06d9511 3686 return sizeof(struct gpu_metrics_v1_3);
8ca78a0a 3687}
bc50ca29 3688
3ddd0c90 3689static int sienna_cichlid_check_ecc_table_support(struct smu_context *smu)
3690{
3691 uint32_t if_version = 0xff, smu_version = 0xff;
3692 int ret = 0;
3693
3694 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
3695 if (ret)
3696 return -EOPNOTSUPP;
3697
3698 if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION)
3699 ret = -EOPNOTSUPP;
3700
3701 return ret;
3702}
3703
3704static ssize_t sienna_cichlid_get_ecc_info(struct smu_context *smu,
3705 void *table)
3706{
3707 struct smu_table_context *smu_table = &smu->smu_table;
3708 EccInfoTable_t *ecc_table = NULL;
3709 struct ecc_info_per_ch *ecc_info_per_channel = NULL;
3710 int i, ret = 0;
3711 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
3712
3713 ret = sienna_cichlid_check_ecc_table_support(smu);
3714 if (ret)
3715 return ret;
3716
3717 ret = smu_cmn_update_table(smu,
3718 SMU_TABLE_ECCINFO,
3719 0,
3720 smu_table->ecc_table,
3721 false);
3722 if (ret) {
3723 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n");
3724 return ret;
3725 }
3726
3727 ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
3728
3729 for (i = 0; i < SIENNA_CICHLID_UMC_CHANNEL_NUM; i++) {
3730 ecc_info_per_channel = &(eccinfo->ecc[i]);
3731 ecc_info_per_channel->ce_count_lo_chip =
3732 ecc_table->EccInfo[i].ce_count_lo_chip;
3733 ecc_info_per_channel->ce_count_hi_chip =
3734 ecc_table->EccInfo[i].ce_count_hi_chip;
3735 ecc_info_per_channel->mca_umc_status =
3736 ecc_table->EccInfo[i].mca_umc_status;
3737 ecc_info_per_channel->mca_umc_addr =
3738 ecc_table->EccInfo[i].mca_umc_addr;
3739 }
3740
3741 return ret;
3742}
05f39286
EQ		 3743static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
3744{
b804a75d
EQ		 3745 struct smu_table_context *table_context = &smu->smu_table;
3746 PPTable_t *smc_pptable = table_context->driver_pptable;
3747
3748 /*
3749 * Skip the MGpuFanBoost setting for those ASICs
3750 * which do not support it
3751 */
3752 if (!smc_pptable->MGpuFanBoostLimitRpm)
3753 return 0;
3754
05f39286
EQ		 3755 return smu_cmn_send_smc_msg_with_param(smu,
3756 SMU_MSG_SetMGpuFanBoostLimitRpm,
3757 0,
3758 NULL);
3759}
3760
76c71f00
EQ		 3761static int sienna_cichlid_gpo_control(struct smu_context *smu,
3762 bool enablement)
3763{
ac7804bb 3764 uint32_t smu_version;
76c71f00
EQ		 3765 int ret = 0;
3766
ac7804bb 3767
76c71f00 3768 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
ac7804bb
EQ		 3769 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
3770 if (ret)
3771 return ret;
3772
3773 if (enablement) {
3774 if (smu_version < 0x003a2500) {
3775 ret = smu_cmn_send_smc_msg_with_param(smu,
3776 SMU_MSG_SetGpoFeaturePMask,
3777 GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
3778 NULL);
3779 } else {
3780 ret = smu_cmn_send_smc_msg_with_param(smu,
3781 SMU_MSG_DisallowGpo,
3782 0,
3783 NULL);
3784 }
3785 } else {
3786 if (smu_version < 0x003a2500) {
3787 ret = smu_cmn_send_smc_msg_with_param(smu,
3788 SMU_MSG_SetGpoFeaturePMask,
3789 0,
3790 NULL);
3791 } else {
3792 ret = smu_cmn_send_smc_msg_with_param(smu,
3793 SMU_MSG_DisallowGpo,
3794 1,
3795 NULL);
3796 }
3797 }
76c71f00
EQ		 3798 }
3799
3800 return ret;
3801}
d7f52e29
EQ		 3802
3803static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
3804{
3805 uint32_t smu_version;
3806 int ret = 0;
3807
3808 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
3809 if (ret)
3810 return ret;
3811
3812 /*
3813 * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
3814 * onwards PMFWs.
3815 */
3816 if (smu_version < 0x003A2D00)
3817 return 0;
3818
3819 return smu_cmn_send_smc_msg_with_param(smu,
3820 SMU_MSG_Enable2ndUSB20Port,
3821 smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
3822 1 : 0,
3823 NULL);
3824}
3825
3826static int sienna_cichlid_system_features_control(struct smu_context *smu,
3827 bool en)
3828{
3829 int ret = 0;
3830
3831 if (en) {
3832 ret = sienna_cichlid_notify_2nd_usb20_port(smu);
3833 if (ret)
3834 return ret;
3835 }
3836
3837 return smu_v11_0_system_features_control(smu, en);
3838}
3839
1689fca0
EQ		 3840static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
3841 enum pp_mp1_state mp1_state)
3842{
9113a0fb
GC		 3843 int ret;
3844
1689fca0
EQ		 3845 switch (mp1_state) {
3846 case PP_MP1_STATE_UNLOAD:
9113a0fb
GC		 3847 ret = smu_cmn_set_mp1_state(smu, mp1_state);
3848 break;
1689fca0 3849 default:
9113a0fb
GC		 3850 /* Ignore others */
3851 ret = 0;
1689fca0
EQ		 3852 }
3853
9113a0fb 3854 return ret;
1689fca0
EQ		 3855}
3856
db5b5c67
AG		 3857static void sienna_cichlid_stb_init(struct smu_context *smu)
3858{
3859 struct amdgpu_device *adev = smu->adev;
3860 uint32_t reg;
3861
3862 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START);
3863 smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE);
3864
3865 /* STB is disabled */
3866 if (!smu->stb_context.enabled)
3867 return;
3868
3869 spin_lock_init(&smu->stb_context.lock);
3870
3871 /* STB buffer size in bytes as function of FIFO depth */
3872 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO);
3873 smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH);
3874 smu->stb_context.stb_buf_size *= SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES;
3875
3876 dev_info(smu->adev->dev, "STB initialized to %d entries",
3877 smu->stb_context.stb_buf_size / SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES);
3878
3879}
3880
6a8cf634
AD		 3881static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu,
3882 void *buf,
3883 uint32_t size)
db5b5c67
AG		 3884{
3885 uint32_t *p = buf;
3886 struct amdgpu_device *adev = smu->adev;
3887
3888 /* No need to disable interrupts for now as we don't lock it yet from ISR */
3889 spin_lock(&smu->stb_context.lock);
3890
3891 /*
3892 * Read the STB FIFO in units of 32bit since this is the accessor window
3893 * (register width) we have.
3894 */
3895 buf = ((char *) buf) + size;
3896 while ((void *)p < buf)
3897 *p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3));
3898
3899 spin_unlock(&smu->stb_context.lock);
3900
3901 return 0;
3902}
3903
b455159c 3904static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
b455159c
LG		 3905 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
3906 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
f6b4b4a1 3907 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
6fb176a7 3908 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
bc50ca29
AD		 3909 .i2c_init = sienna_cichlid_i2c_control_init,
3910 .i2c_fini = sienna_cichlid_i2c_control_fini,
b455159c
LG		 3911 .print_clk_levels = sienna_cichlid_print_clk_levels,
3912 .force_clk_levels = sienna_cichlid_force_clk_levels,
3913 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
b455159c
LG		 3914 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
3915 .display_config_changed = sienna_cichlid_display_config_changed,
3916 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
b455159c 3917 .is_dpm_running = sienna_cichlid_is_dpm_running,
0d8318e1 3918 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
d9ca7567 3919 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
b455159c
LG		 3920 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
3921 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
b455159c
LG		 3922 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
3923 .read_sensor = sienna_cichlid_read_sensor,
3924 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
b2785e25 3925 .set_performance_level = smu_v11_0_set_performance_level,
b455159c
LG		 3926 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
3927 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
3928 .get_power_limit = sienna_cichlid_get_power_limit,
08ccfe08 3929 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
b455159c
LG		 3930 .dump_pptable = sienna_cichlid_dump_pptable,
3931 .init_microcode = smu_v11_0_init_microcode,
3932 .load_microcode = smu_v11_0_load_microcode,
c1b353b7 3933 .init_smc_tables = sienna_cichlid_init_smc_tables,
b455159c
LG		 3934 .fini_smc_tables = smu_v11_0_fini_smc_tables,
3935 .init_power = smu_v11_0_init_power,
3936 .fini_power = smu_v11_0_fini_power,
3937 .check_fw_status = smu_v11_0_check_fw_status,
4a13b4ce 3938 .setup_pptable = sienna_cichlid_setup_pptable,
b455159c 3939 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
b455159c 3940 .check_fw_version = smu_v11_0_check_fw_version,
caad2613 3941 .write_pptable = smu_cmn_write_pptable,
b455159c
LG		 3942 .set_driver_table_location = smu_v11_0_set_driver_table_location,
3943 .set_tool_table_location = smu_v11_0_set_tool_table_location,
3944 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
d7f52e29 3945 .system_features_control = sienna_cichlid_system_features_control,
66c86828
EQ		 3946 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
3947 .send_smc_msg = smu_cmn_send_smc_msg,
31157341 3948 .init_display_count = NULL,
b455159c 3949 .set_allowed_mask = smu_v11_0_set_allowed_mask,
28251d72 3950 .get_enabled_mask = smu_cmn_get_enabled_mask,
b4bb3aaf 3951 .feature_is_enabled = smu_cmn_feature_is_enabled,
af5ba6d2 3952 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
31157341 3953 .notify_display_change = NULL,
b455159c 3954 .set_power_limit = smu_v11_0_set_power_limit,
b455159c
LG		 3955 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
3956 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
3957 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
ce63d8f8 3958 .set_min_dcef_deep_sleep = NULL,
b455159c
LG		 3959 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
3960 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
3961 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
0d8318e1 3962 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
f3289d04 3963 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
b455159c
LG		 3964 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
3965 .gfx_off_control = smu_v11_0_gfx_off_control,
3966 .register_irq_handler = smu_v11_0_register_irq_handler,
3967 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
3968 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
9fd4781b 3969 .baco_is_support = smu_v11_0_baco_is_support,
b455159c
LG		 3970 .baco_get_state = smu_v11_0_baco_get_state,
3971 .baco_set_state = smu_v11_0_baco_set_state,
13d75ead
EQ		 3972 .baco_enter = sienna_cichlid_baco_enter,
3973 .baco_exit = sienna_cichlid_baco_exit,
ea8139d8
WS		 3974 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
3975 .mode1_reset = smu_v11_0_mode1_reset,
258d290c 3976 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
10e96d89 3977 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
aa75fa34 3978 .set_default_od_settings = sienna_cichlid_set_default_od_settings,
37a58f69 3979 .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
b521be9b 3980 .restore_user_od_settings = smu_v11_0_restore_user_od_settings,
66b8a9c0 3981 .run_btc = sienna_cichlid_run_btc,
18a4b3de 3982 .set_power_source = smu_v11_0_set_power_source,
7dbf7805
EQ		 3983 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3984 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
8ca78a0a 3985 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
05f39286 3986 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
e988026f 3987 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
5ce99853 3988 .deep_sleep_control = smu_v11_0_deep_sleep_control,
3204ff3e 3989 .get_fan_parameters = sienna_cichlid_get_fan_parameters,
234676d6 3990 .interrupt_work = smu_v11_0_interrupt_work,
76c71f00 3991 .gpo_control = sienna_cichlid_gpo_control,
1689fca0 3992 .set_mp1_state = sienna_cichlid_set_mp1_state,
db5b5c67 3993 .stb_collect_info = sienna_cichlid_stb_get_data_direct,
3ddd0c90 3994 .get_ecc_info = sienna_cichlid_get_ecc_info,
b455159c
LG		 3995};
3996
3997void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
3998{
3999 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
6c339f37
EQ		 4000 smu->message_map = sienna_cichlid_message_map;
4001 smu->clock_map = sienna_cichlid_clk_map;
4002 smu->feature_map = sienna_cichlid_feature_mask_map;
4003 smu->table_map = sienna_cichlid_table_map;
4004 smu->pwr_src_map = sienna_cichlid_pwr_src_map;
4005 smu->workload_map = sienna_cichlid_workload_map;
b455159c 4006}
Linux 6.x block layer and io_uring tree(s)