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drm/amdgpu: disable 3DCGCG/CGLS temporarily due to stability issue
[linux-block.git] / drivers / gpu / drm / amd / pm / swsmu / smu11 / sienna_cichlid_ppt.c
CommitLineData
b455159c
LG		 1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
d8e0b16d
EQ		 24#define SWSMU_CODE_LAYER_L2
25
b455159c
LG		 26#include <linux/firmware.h>
27#include <linux/pci.h>
bc50ca29 28#include <linux/i2c.h>
b455159c 29#include "amdgpu.h"
2f60dd50 30#include "amdgpu_dpm.h"
b455159c 31#include "amdgpu_smu.h"
b455159c
LG		 32#include "atomfirmware.h"
33#include "amdgpu_atomfirmware.h"
22f2447c 34#include "amdgpu_atombios.h"
b455159c
LG		 35#include "smu_v11_0.h"
36#include "smu11_driver_if_sienna_cichlid.h"
37#include "soc15_common.h"
38#include "atom.h"
39#include "sienna_cichlid_ppt.h"
e05acd78 40#include "smu_v11_0_7_pptable.h"
b455159c 41#include "smu_v11_0_7_ppsmc.h"
40d3b8db 42#include "nbio/nbio_2_3_offset.h"
b7d25b5f 43#include "nbio/nbio_2_3_sh_mask.h"
e05acd78
LG		 44#include "thm/thm_11_0_2_offset.h"
45#include "thm/thm_11_0_2_sh_mask.h"
ea8139d8
WS		 46#include "mp/mp_11_0_offset.h"
47#include "mp/mp_11_0_sh_mask.h"
b455159c 48
6c339f37 49#include "asic_reg/mp/mp_11_0_sh_mask.h"
3ddd0c90 50#include "amdgpu_ras.h"
6c339f37
EQ		 51#include "smu_cmn.h"
52
55084d7f
EQ		 53/*
54 * DO NOT use these for err/warn/info/debug messages.
55 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
56 * They are more MGPU friendly.
57 */
58#undef pr_err
59#undef pr_warn
60#undef pr_info
61#undef pr_debug
62
b455159c
LG		 63#define FEATURE_MASK(feature) (1ULL << feature)
64#define SMC_DPM_FEATURE ( \
65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
fea905d4 66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65297d50 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
5cb74353 68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
4cd4f45b 69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
5f338f70 70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
ce7e5a6e
JC		 71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \
72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
b455159c 73
d817f375
LG		 74#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
75
7077b19a 76#define GET_PPTABLE_MEMBER(field, member) do {\
1d789535 77 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))\
7077b19a
CG		 78 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
79 else\
80 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
81} while(0)
82
db5b5c67
AG		 83/* STB FIFO depth is in 64bit units */
84#define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES 8
85
3ddd0c90 86/*
87 * SMU support ECCTABLE since version 58.70.0,
88 * use this to check whether ECCTABLE feature is supported.
89 */
90#define SUPPORT_ECCTABLE_SMU_VERSION 0x003a4600
91
7077b19a
CG		 92static int get_table_size(struct smu_context *smu)
93{
1d789535 94 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
7077b19a
CG		 95 return sizeof(PPTable_beige_goby_t);
96 else
97 return sizeof(PPTable_t);
98}
99
6c339f37
EQ		 100static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
101 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
102 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
103 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
91190db1
LG		 104 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
105 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
106 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
107 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
6c339f37
EQ		 108 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
109 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
110 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
111 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
112 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
113 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
114 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
91190db1 115 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
4215a119
HC		 116 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
117 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
91190db1
LG		 118 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
119 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
4215a119 120 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
91190db1
LG		 121 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
122 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
66b8a9c0 123 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
91190db1 124 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
4215a119
HC		 125 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
126 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
6c339f37 127 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
91190db1 128 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
6c339f37
EQ		 129 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
130 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
131 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
91190db1
LG		 132 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
133 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
134 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
135 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
136 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
137 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
138 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
139 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
6c339f37 140 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
91190db1
LG		 141 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
142 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
40f1dc52 143 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
6c339f37 144 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
91190db1
LG		 145 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
146 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
147 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
148 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
149 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
150 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
151 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
152 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
05f39286 153 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
76c71f00 154 MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0),
ac7804bb 155 MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0),
88dfd5d5 156 MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0),
b455159c
LG		 157};
158
6c339f37 159static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
b455159c
LG		 160 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
161 CLK_MAP(SCLK, PPCLK_GFXCLK),
162 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
163 CLK_MAP(FCLK, PPCLK_FCLK),
164 CLK_MAP(UCLK, PPCLK_UCLK),
165 CLK_MAP(MCLK, PPCLK_UCLK),
166 CLK_MAP(DCLK, PPCLK_DCLK_0),
9c0551f2
JC		 167 CLK_MAP(DCLK1, PPCLK_DCLK_1),
168 CLK_MAP(VCLK, PPCLK_VCLK_0),
b455159c
LG		 169 CLK_MAP(VCLK1, PPCLK_VCLK_1),
170 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
171 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
172 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
173 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
174};
175
6c339f37 176static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
b455159c
LG		 177 FEA_MAP(DPM_PREFETCHER),
178 FEA_MAP(DPM_GFXCLK),
31cb0dd9 179 FEA_MAP(DPM_GFX_GPO),
b455159c 180 FEA_MAP(DPM_UCLK),
e9073b43 181 FEA_MAP(DPM_FCLK),
b455159c
LG		 182 FEA_MAP(DPM_SOCCLK),
183 FEA_MAP(DPM_MP0CLK),
184 FEA_MAP(DPM_LINK),
185 FEA_MAP(DPM_DCEFCLK),
e9073b43 186 FEA_MAP(DPM_XGMI),
b455159c
LG		 187 FEA_MAP(MEM_VDDCI_SCALING),
188 FEA_MAP(MEM_MVDD_SCALING),
189 FEA_MAP(DS_GFXCLK),
190 FEA_MAP(DS_SOCCLK),
e9073b43 191 FEA_MAP(DS_FCLK),
b455159c
LG		 192 FEA_MAP(DS_LCLK),
193 FEA_MAP(DS_DCEFCLK),
194 FEA_MAP(DS_UCLK),
195 FEA_MAP(GFX_ULV),
196 FEA_MAP(FW_DSTATE),
197 FEA_MAP(GFXOFF),
198 FEA_MAP(BACO),
6fb176a7 199 FEA_MAP(MM_DPM_PG),
b455159c
LG		 200 FEA_MAP(RSMU_SMN_CG),
201 FEA_MAP(PPT),
202 FEA_MAP(TDC),
203 FEA_MAP(APCC_PLUS),
204 FEA_MAP(GTHR),
205 FEA_MAP(ACDC),
206 FEA_MAP(VR0HOT),
207 FEA_MAP(VR1HOT),
208 FEA_MAP(FW_CTF),
209 FEA_MAP(FAN_CONTROL),
210 FEA_MAP(THERMAL),
211 FEA_MAP(GFX_DCS),
212 FEA_MAP(RM),
213 FEA_MAP(LED_DISPLAY),
214 FEA_MAP(GFX_SS),
215 FEA_MAP(OUT_OF_BAND_MONITOR),
216 FEA_MAP(TEMP_DEPENDENT_VMIN),
217 FEA_MAP(MMHUB_PG),
218 FEA_MAP(ATHUB_PG),
cf06331f 219 FEA_MAP(APCC_DFLL),
b455159c
LG		 220};
221
6c339f37 222static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
b455159c
LG		 223 TAB_MAP(PPTABLE),
224 TAB_MAP(WATERMARKS),
225 TAB_MAP(AVFS_PSM_DEBUG),
226 TAB_MAP(AVFS_FUSE_OVERRIDE),
227 TAB_MAP(PMSTATUSLOG),
228 TAB_MAP(SMU_METRICS),
229 TAB_MAP(DRIVER_SMU_CONFIG),
230 TAB_MAP(ACTIVITY_MONITOR_COEFF),
231 TAB_MAP(OVERDRIVE),
232 TAB_MAP(I2C_COMMANDS),
233 TAB_MAP(PACE),
3ddd0c90 234 TAB_MAP(ECCINFO),
b455159c
LG		 235};
236
6c339f37 237static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
1d5ca713
LG		 238 PWR_MAP(AC),
239 PWR_MAP(DC),
240};
241
6c339f37 242static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
b455159c
LG		 243 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
244 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
245 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
246 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
247 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
4c4d5a49 248 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
b455159c
LG		 249 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
250};
251
f06d9511
GS		 252static const uint8_t sienna_cichlid_throttler_map[] = {
253 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
254 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
255 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
256 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
257 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
258 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
259 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
260 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
261 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
262 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
263 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
264 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
265 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
266 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
267 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
268 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
269 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
270 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
271};
272
b455159c
LG		 273static int
274sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
275 uint32_t *feature_mask, uint32_t num)
276{
fea905d4
LG		 277 struct amdgpu_device *adev = smu->adev;
278
b455159c
LG		 279 if (num > 2)
280 return -EINVAL;
281
282 memset(feature_mask, 0, sizeof(uint32_t) * num);
283
4cd4f45b 284 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
15dbe18f 285 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
ce7e5a6e 286 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
094cdf15 287 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
5f338f70 288 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
86a9eb3f 289 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
80c36f86 290 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
9aa60213
LG		 291 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
292 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
d28f4aa1 293 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
20d71dcc 294 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
d0d71970 295 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
886c8bc6
LG		 296 | FEATURE_MASK(FEATURE_PPT_BIT)
297 | FEATURE_MASK(FEATURE_TDC_BIT)
3fc006f5 298 | FEATURE_MASK(FEATURE_BACO_BIT)
cf06331f 299 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
35ed946c 300 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
1c58d429 301 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
b971df70
LG		 302 | FEATURE_MASK(FEATURE_THERMAL_BIT)
303 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
fea905d4 304
c96721eb 305 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
fea905d4 306 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
c96721eb
KF		 307 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
308 }
fea905d4 309
680602d6 310 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
1d789535 311 (adev->ip_versions[MP1_HWIP][0] > IP_VERSION(11, 0, 7)) &&
680602d6
KF		 312 !(adev->flags & AMD_IS_APU))
313 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
314
65297d50 315 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
fc17cd3f
LG		 316 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
317 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
318 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
65297d50 319
5cb74353
LG		 320 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
321 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
322
5f338f70
LG		 323 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
324 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
325
fea905d4
LG		 326 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
327 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
b455159c 328
62c1ea6b
LG		 329 if (adev->pm.pp_feature & PP_ULV_MASK)
330 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
331
02bb391d
LG		 332 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
333 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
334
e0da123a
LG		 335 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
336 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
337
b794616d
KF		 338 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
339 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
340
846938c2
KF		 341 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
342 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
343
6fb176a7
LG		 344 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
345 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
346 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
347
62826b86
KF		 348 if (smu->dc_controlled_by_gpio)
349 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
350
0ab5d711 351 if (amdgpu_device_should_use_aspm(adev))
6ef28889
KF		 352 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
353
b455159c
LG		 354 return 0;
355}
356
458020dd 357static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
b455159c 358{
4a13b4ce 359 struct smu_table_context *table_context = &smu->smu_table;
e05acd78 360 struct smu_11_0_7_powerplay_table *powerplay_table =
4a13b4ce
EQ		 361 table_context->power_play_table;
362 struct smu_baco_context *smu_baco = &smu->smu_baco;
458020dd
LL		 363 struct amdgpu_device *adev = smu->adev;
364 uint32_t val;
365
1b41d67e 366 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) {
458020dd
LL		 367 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
368 smu_baco->platform_support =
369 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
370 false;
371 }
372}
373
57301181
ES		 374static void sienna_cichlid_check_fan_support(struct smu_context *smu)
375{
376 struct smu_table_context *table_context = &smu->smu_table;
377 PPTable_t *pptable = table_context->driver_pptable;
378 uint64_t features = *(uint64_t *) pptable->FeaturesToRun;
379
380 /* Fan control is not possible if PPTable has it disabled */
381 smu->adev->pm.no_fan =
382 !(features & (1ULL << FEATURE_FAN_CONTROL_BIT));
383 if (smu->adev->pm.no_fan)
384 dev_info_once(smu->adev->dev,
385 "PMFW based fan control disabled");
386}
387
458020dd
LL		 388static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
389{
390 struct smu_table_context *table_context = &smu->smu_table;
391 struct smu_11_0_7_powerplay_table *powerplay_table =
392 table_context->power_play_table;
4a13b4ce 393
18a4b3de
EQ		 394 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
395 smu->dc_controlled_by_gpio = true;
396
458020dd 397 sienna_cichlid_check_bxco_support(smu);
57301181 398 sienna_cichlid_check_fan_support(smu);
4a13b4ce
EQ		 399
400 table_context->thermal_controller_type =
401 powerplay_table->thermal_controller_type;
402
aa75fa34
EQ		 403 /*
404 * Instead of having its own buffer space and get overdrive_table copied,
405 * smu->od_settings just points to the actual overdrive_table
406 */
407 smu->od_settings = &powerplay_table->overdrive_table;
408
b455159c
LG		 409 return 0;
410}
411
412static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
413{
dccc7c21
LG		 414 struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
415 int index, ret;
7077b19a 416 I2cControllerConfig_t *table_member;
dccc7c21
LG		 417
418 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
419 smc_dpm_info);
420
22f2447c 421 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
dccc7c21
LG		 422 (uint8_t **)&smc_dpm_table);
423 if (ret)
424 return ret;
7077b19a
CG		 425 GET_PPTABLE_MEMBER(I2cControllers, &table_member);
426 memcpy(table_member, smc_dpm_table->I2cControllers,
427 sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
20f5e6cf 428
b455159c
LG		 429 return 0;
430}
431
432static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
433{
b455159c 434 struct smu_table_context *table_context = &smu->smu_table;
e05acd78 435 struct smu_11_0_7_powerplay_table *powerplay_table =
4a13b4ce 436 table_context->power_play_table;
7077b19a 437 int table_size;
b455159c 438
7077b19a 439 table_size = get_table_size(smu);
b455159c 440 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
7077b19a 441 table_size);
b455159c 442
4a13b4ce
EQ		 443 return 0;
444}
b455159c 445
951be8be
EQ		 446static int sienna_cichlid_patch_pptable_quirk(struct smu_context *smu)
447{
448 struct amdgpu_device *adev = smu->adev;
449 uint32_t *board_reserved;
450 uint16_t *freq_table_gfx;
451 uint32_t i;
452
453 /* Fix some OEM SKU specific stability issues */
454 GET_PPTABLE_MEMBER(BoardReserved, &board_reserved);
455 if ((adev->pdev->device == 0x73DF) &&
456 (adev->pdev->revision == 0XC3) &&
457 (adev->pdev->subsystem_device == 0x16C2) &&
458 (adev->pdev->subsystem_vendor == 0x1043))
459 board_reserved[0] = 1387;
460
461 GET_PPTABLE_MEMBER(FreqTableGfx, &freq_table_gfx);
462 if ((adev->pdev->device == 0x73DF) &&
463 (adev->pdev->revision == 0XC3) &&
464 ((adev->pdev->subsystem_device == 0x16C2) ||
465 (adev->pdev->subsystem_device == 0x133C)) &&
466 (adev->pdev->subsystem_vendor == 0x1043)) {
467 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) {
468 if (freq_table_gfx[i] > 2500)
469 freq_table_gfx[i] = 2500;
470 }
471 }
472
473 return 0;
474}
475
4a13b4ce
EQ		 476static int sienna_cichlid_setup_pptable(struct smu_context *smu)
477{
478 int ret = 0;
b455159c 479
4a13b4ce
EQ		 480 ret = smu_v11_0_setup_pptable(smu);
481 if (ret)
482 return ret;
483
484 ret = sienna_cichlid_store_powerplay_table(smu);
485 if (ret)
486 return ret;
487
488 ret = sienna_cichlid_append_powerplay_table(smu);
489 if (ret)
490 return ret;
491
492 ret = sienna_cichlid_check_powerplay_table(smu);
493 if (ret)
494 return ret;
495
951be8be 496 return sienna_cichlid_patch_pptable_quirk(smu);
b455159c
LG		 497}
498
c1b353b7 499static int sienna_cichlid_tables_init(struct smu_context *smu)
b455159c
LG		 500{
501 struct smu_table_context *smu_table = &smu->smu_table;
c1b353b7 502 struct smu_table *tables = smu_table->tables;
7077b19a 503 int table_size;
b455159c 504
7077b19a
CG		 505 table_size = get_table_size(smu);
506 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
507 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c
LG		 508 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
509 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b4b0b79d 510 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
b455159c 511 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
bc50ca29
AD		 512 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
513 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c
LG		 514 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
515 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
516 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
517 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
518 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
f9e3fe46 519 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
b455159c 520 AMDGPU_GEM_DOMAIN_VRAM);
3ddd0c90 521 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
522 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
816d61d5
EQ		 523 SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfigExternal_t),
524 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c 525
b4b0b79d 526 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
b455159c 527 if (!smu_table->metrics_table)
8ca78a0a 528 goto err0_out;
b455159c
LG		 529 smu_table->metrics_time = 0;
530
f06d9511 531 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
8ca78a0a
EQ		 532 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
533 if (!smu_table->gpu_metrics_table)
534 goto err1_out;
535
40d3b8db
LG		 536 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
537 if (!smu_table->watermarks_table)
8ca78a0a 538 goto err2_out;
40d3b8db 539
3ddd0c90 540 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
541 if (!smu_table->ecc_table)
816d61d5
EQ		 542 goto err3_out;
543
544 smu_table->driver_smu_config_table =
545 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL);
546 if (!smu_table->driver_smu_config_table)
547 goto err4_out;
3ddd0c90 548
b455159c 549 return 0;
8ca78a0a 550
816d61d5
EQ		 551err4_out:
552 kfree(smu_table->ecc_table);
553err3_out:
554 kfree(smu_table->watermarks_table);
8ca78a0a
EQ		 555err2_out:
556 kfree(smu_table->gpu_metrics_table);
557err1_out:
558 kfree(smu_table->metrics_table);
559err0_out:
560 return -ENOMEM;
b455159c
LG		 561}
562
be22e2b9
EQ		 563static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu)
564{
565 struct smu_table_context *smu_table= &smu->smu_table;
566 SmuMetricsExternal_t *metrics_ext =
567 (SmuMetricsExternal_t *)(smu_table->metrics_table);
568 uint32_t throttler_status = 0;
569 int i;
570
1d789535 571 if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
7952fa0d
DS		 572 (smu->smc_fw_version >= 0x3A4900)) {
573 for (i = 0; i < THROTTLER_COUNT; i++)
574 throttler_status |=
575 (metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0);
576 } else if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
be22e2b9
EQ		 577 (smu->smc_fw_version >= 0x3A4300)) {
578 for (i = 0; i < THROTTLER_COUNT; i++)
579 throttler_status |=
580 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
581 } else {
582 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus;
583 }
584
585 return throttler_status;
586}
587
d6810d7d
S		 588static int sienna_cichlid_get_power_limit(struct smu_context *smu,
589 uint32_t *current_power_limit,
590 uint32_t *default_power_limit,
591 uint32_t *max_power_limit)
592{
593 struct smu_11_0_7_powerplay_table *powerplay_table =
594 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
595 uint32_t power_limit, od_percent;
596 uint16_t *table_member;
597
598 GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
599
600 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
601 power_limit =
602 table_member[PPT_THROTTLER_PPT0];
603 }
604
605 if (current_power_limit)
606 *current_power_limit = power_limit;
607 if (default_power_limit)
608 *default_power_limit = power_limit;
609
610 if (max_power_limit) {
611 if (smu->od_enabled) {
612 od_percent =
613 le32_to_cpu(powerplay_table->overdrive_table.max[
614 SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
615
616 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n",
617 od_percent, power_limit);
618
619 power_limit *= (100 + od_percent);
620 power_limit /= 100;
621 }
622 *max_power_limit = power_limit;
623 }
624
625 return 0;
626}
627
628static void sienna_cichlid_get_smartshift_power_percentage(struct smu_context *smu,
629 uint32_t *apu_percent,
630 uint32_t *dgpu_percent)
631{
632 struct smu_table_context *smu_table = &smu->smu_table;
633 SmuMetrics_V4_t *metrics_v4 =
634 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V4);
635 uint16_t powerRatio = 0;
636 uint16_t apu_power_limit = 0;
637 uint16_t dgpu_power_limit = 0;
638 uint32_t apu_boost = 0;
639 uint32_t dgpu_boost = 0;
640 uint32_t cur_power_limit;
641
642 if (metrics_v4->ApuSTAPMSmartShiftLimit != 0) {
643 sienna_cichlid_get_power_limit(smu, &cur_power_limit, NULL, NULL);
644 apu_power_limit = metrics_v4->ApuSTAPMLimit;
645 dgpu_power_limit = cur_power_limit;
646 powerRatio = (((apu_power_limit +
647 dgpu_power_limit) * 100) /
648 metrics_v4->ApuSTAPMSmartShiftLimit);
649 if (powerRatio > 100) {
650 apu_power_limit = (apu_power_limit * 100) /
651 powerRatio;
652 dgpu_power_limit = (dgpu_power_limit * 100) /
653 powerRatio;
654 }
655 if (metrics_v4->AverageApuSocketPower > apu_power_limit &&
656 apu_power_limit != 0) {
657 apu_boost = ((metrics_v4->AverageApuSocketPower -
658 apu_power_limit) * 100) /
659 apu_power_limit;
660 if (apu_boost > 100)
661 apu_boost = 100;
662 }
663
664 if (metrics_v4->AverageSocketPower > dgpu_power_limit &&
665 dgpu_power_limit != 0) {
666 dgpu_boost = ((metrics_v4->AverageSocketPower -
667 dgpu_power_limit) * 100) /
668 dgpu_power_limit;
669 if (dgpu_boost > 100)
670 dgpu_boost = 100;
671 }
672
673 if (dgpu_boost >= apu_boost)
674 apu_boost = 0;
675 else
676 dgpu_boost = 0;
677 }
678 *apu_percent = apu_boost;
679 *dgpu_percent = dgpu_boost;
680}
681
60ae4d67
EQ		 682static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
683 MetricsMember_t member,
684 uint32_t *value)
685{
686 struct smu_table_context *smu_table= &smu->smu_table;
b4b0b79d
EQ		 687 SmuMetrics_t *metrics =
688 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
be22e2b9
EQ		 689 SmuMetrics_V2_t *metrics_v2 =
690 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
7952fa0d
DS		 691 SmuMetrics_V3_t *metrics_v3 =
692 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V3);
693 bool use_metrics_v2 = false;
694 bool use_metrics_v3 = false;
be22e2b9 695 uint16_t average_gfx_activity;
60ae4d67 696 int ret = 0;
d6810d7d
S		 697 uint32_t apu_percent = 0;
698 uint32_t dgpu_percent = 0;
60ae4d67 699
396beb91
EQ		 700 switch (smu->adev->ip_versions[MP1_HWIP][0]) {
701 case IP_VERSION(11, 0, 7):
702 if (smu->smc_fw_version >= 0x3A4900)
703 use_metrics_v3 = true;
704 else if (smu->smc_fw_version >= 0x3A4300)
705 use_metrics_v2 = true;
706 break;
707 case IP_VERSION(11, 0, 11):
708 if (smu->smc_fw_version >= 0x412D00)
709 use_metrics_v2 = true;
710 break;
711 case IP_VERSION(11, 0, 12):
712 if (smu->smc_fw_version >= 0x3B2300)
713 use_metrics_v2 = true;
714 break;
715 case IP_VERSION(11, 0, 13):
716 if (smu->smc_fw_version >= 0x491100)
717 use_metrics_v2 = true;
718 break;
719 default:
720 break;
721 }
7952fa0d 722
da11407f
EQ		 723 ret = smu_cmn_get_metrics_table(smu,
724 NULL,
725 false);
726 if (ret)
60ae4d67 727 return ret;
60ae4d67 728
8c686254
EQ		 729 switch (member) {
730 case METRICS_CURR_GFXCLK:
7952fa0d
DS		 731 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
732 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] :
be22e2b9 733 metrics->CurrClock[PPCLK_GFXCLK];
8c686254
EQ		 734 break;
735 case METRICS_CURR_SOCCLK:
7952fa0d
DS		 736 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
737 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] :
be22e2b9 738 metrics->CurrClock[PPCLK_SOCCLK];
8c686254
EQ		 739 break;
740 case METRICS_CURR_UCLK:
7952fa0d
DS		 741 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
742 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] :
be22e2b9 743 metrics->CurrClock[PPCLK_UCLK];
8c686254
EQ		 744 break;
745 case METRICS_CURR_VCLK:
7952fa0d
DS		 746 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
747 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] :
be22e2b9 748 metrics->CurrClock[PPCLK_VCLK_0];
8c686254
EQ		 749 break;
750 case METRICS_CURR_VCLK1:
7952fa0d
DS		 751 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
752 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] :
be22e2b9 753 metrics->CurrClock[PPCLK_VCLK_1];
8c686254
EQ		 754 break;
755 case METRICS_CURR_DCLK:
7952fa0d
DS		 756 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
757 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] :
be22e2b9 758 metrics->CurrClock[PPCLK_DCLK_0];
8c686254
EQ		 759 break;
760 case METRICS_CURR_DCLK1:
7952fa0d
DS		 761 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
762 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
be22e2b9 763 metrics->CurrClock[PPCLK_DCLK_1];
8c686254 764 break;
9d09fa6f 765 case METRICS_CURR_DCEFCLK:
7952fa0d
DS		 766 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCEFCLK] :
767 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] :
be22e2b9 768 metrics->CurrClock[PPCLK_DCEFCLK];
9d09fa6f 769 break;
4e2b3e23 770 case METRICS_CURR_FCLK:
7952fa0d
DS		 771 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_FCLK] :
772 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] :
be22e2b9 773 metrics->CurrClock[PPCLK_FCLK];
4e2b3e23 774 break;
8c686254 775 case METRICS_AVERAGE_GFXCLK:
7952fa0d
DS		 776 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
777 use_metrics_v2 ? metrics_v2->AverageGfxActivity :
be22e2b9
EQ		 778 metrics->AverageGfxActivity;
779 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
7952fa0d
DS		 780 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
781 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
be22e2b9 782 metrics->AverageGfxclkFrequencyPostDs;
d817f375 783 else
7952fa0d
DS		 784 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
785 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
be22e2b9 786 metrics->AverageGfxclkFrequencyPreDs;
8c686254
EQ		 787 break;
788 case METRICS_AVERAGE_FCLK:
7952fa0d
DS		 789 *value = use_metrics_v3 ? metrics_v3->AverageFclkFrequencyPostDs :
790 use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs :
be22e2b9 791 metrics->AverageFclkFrequencyPostDs;
8c686254
EQ		 792 break;
793 case METRICS_AVERAGE_UCLK:
7952fa0d
DS		 794 *value = use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
795 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
be22e2b9 796 metrics->AverageUclkFrequencyPostDs;
8c686254
EQ		 797 break;
798 case METRICS_AVERAGE_GFXACTIVITY:
7952fa0d
DS		 799 *value = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
800 use_metrics_v2 ? metrics_v2->AverageGfxActivity :
be22e2b9 801 metrics->AverageGfxActivity;
8c686254
EQ		 802 break;
803 case METRICS_AVERAGE_MEMACTIVITY:
7952fa0d
DS		 804 *value = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
805 use_metrics_v2 ? metrics_v2->AverageUclkActivity :
be22e2b9 806 metrics->AverageUclkActivity;
8c686254
EQ		 807 break;
808 case METRICS_AVERAGE_SOCKETPOWER:
7952fa0d
DS		 809 *value = use_metrics_v3 ? metrics_v3->AverageSocketPower << 8 :
810 use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 :
be22e2b9 811 metrics->AverageSocketPower << 8;
8c686254
EQ		 812 break;
813 case METRICS_TEMPERATURE_EDGE:
7952fa0d
DS		 814 *value = (use_metrics_v3 ? metrics_v3->TemperatureEdge :
815 use_metrics_v2 ? metrics_v2->TemperatureEdge :
816 metrics->TemperatureEdge) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
8c686254
EQ		 817 break;
818 case METRICS_TEMPERATURE_HOTSPOT:
7952fa0d
DS		 819 *value = (use_metrics_v3 ? metrics_v3->TemperatureHotspot :
820 use_metrics_v2 ? metrics_v2->TemperatureHotspot :
821 metrics->TemperatureHotspot) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
8c686254
EQ		 822 break;
823 case METRICS_TEMPERATURE_MEM:
7952fa0d
DS		 824 *value = (use_metrics_v3 ? metrics_v3->TemperatureMem :
825 use_metrics_v2 ? metrics_v2->TemperatureMem :
826 metrics->TemperatureMem) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
8c686254
EQ		 827 break;
828 case METRICS_TEMPERATURE_VRGFX:
7952fa0d
DS		 829 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
830 use_metrics_v2 ? metrics_v2->TemperatureVrGfx :
831 metrics->TemperatureVrGfx) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
8c686254
EQ		 832 break;
833 case METRICS_TEMPERATURE_VRSOC:
7952fa0d
DS		 834 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
835 use_metrics_v2 ? metrics_v2->TemperatureVrSoc :
836 metrics->TemperatureVrSoc) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
8c686254
EQ		 837 break;
838 case METRICS_THROTTLER_STATUS:
be22e2b9 839 *value = sienna_cichlid_get_throttler_status_locked(smu);
8c686254
EQ		 840 break;
841 case METRICS_CURR_FANSPEED:
7952fa0d
DS		 842 *value = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
843 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
8c686254 844 break;
ebd9c071 845 case METRICS_UNIQUE_ID_UPPER32:
5e9c4451
KR		 846 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
847 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumUpper32 : 0;
ebd9c071
KR		 848 break;
849 case METRICS_UNIQUE_ID_LOWER32:
5e9c4451
KR		 850 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
851 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumLower32 : 0;
ebd9c071 852 break;
d6810d7d
S		 853 case METRICS_SS_APU_SHARE:
854 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
855 *value = apu_percent;
856 break;
857 case METRICS_SS_DGPU_SHARE:
858 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
859 *value = dgpu_percent;
860 break;
861
8c686254
EQ		 862 default:
863 *value = UINT_MAX;
864 break;
865 }
866
b455159c 867 return ret;
8c686254 868
b455159c
LG		 869}
870
871static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
872{
873 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
874
b455159c
LG		 875 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
876 GFP_KERNEL);
877 if (!smu_dpm->dpm_context)
878 return -ENOMEM;
879
880 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
881
882 return 0;
883}
884
db5b5c67
AG		 885static void sienna_cichlid_stb_init(struct smu_context *smu);
886
c1b353b7
EQ		 887static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
888{
748262eb 889 struct amdgpu_device *adev = smu->adev;
c1b353b7
EQ		 890 int ret = 0;
891
892 ret = sienna_cichlid_tables_init(smu);
893 if (ret)
894 return ret;
895
896 ret = sienna_cichlid_allocate_dpm_context(smu);
897 if (ret)
898 return ret;
899
748262eb 900 if (!amdgpu_sriov_vf(adev))
901 sienna_cichlid_stb_init(smu);
db5b5c67 902
c1b353b7
EQ		 903 return smu_v11_0_init_smc_tables(smu);
904}
905
b455159c
LG		 906static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
907{
90a89c31 908 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
90a89c31 909 struct smu_11_0_dpm_table *dpm_table;
85dec717 910 struct amdgpu_device *adev = smu->adev;
0b54122c 911 int i, ret = 0;
7077b19a 912 DpmDescriptor_t *table_member;
b455159c 913
90a89c31
EQ		 914 /* socclk dpm table setup */
915 dpm_table = &dpm_context->dpm_tables.soc_table;
7077b19a 916 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
b4bb3aaf 917 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
90a89c31
EQ		 918 ret = smu_v11_0_set_single_dpm_table(smu,
919 SMU_SOCCLK,
920 dpm_table);
921 if (ret)
922 return ret;
923 dpm_table->is_fine_grained =
7077b19a 924 !table_member[PPCLK_SOCCLK].SnapToDiscrete;
90a89c31
EQ		 925 } else {
926 dpm_table->count = 1;
927 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
928 dpm_table->dpm_levels[0].enabled = true;
929 dpm_table->min = dpm_table->dpm_levels[0].value;
930 dpm_table->max = dpm_table->dpm_levels[0].value;
931 }
b455159c 932
90a89c31
EQ		 933 /* gfxclk dpm table setup */
934 dpm_table = &dpm_context->dpm_tables.gfx_table;
b4bb3aaf 935 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
90a89c31
EQ		 936 ret = smu_v11_0_set_single_dpm_table(smu,
937 SMU_GFXCLK,
938 dpm_table);
939 if (ret)
940 return ret;
941 dpm_table->is_fine_grained =
7077b19a 942 !table_member[PPCLK_GFXCLK].SnapToDiscrete;
90a89c31
EQ		 943 } else {
944 dpm_table->count = 1;
945 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
946 dpm_table->dpm_levels[0].enabled = true;
947 dpm_table->min = dpm_table->dpm_levels[0].value;
948 dpm_table->max = dpm_table->dpm_levels[0].value;
949 }
b455159c 950
90a89c31
EQ		 951 /* uclk dpm table setup */
952 dpm_table = &dpm_context->dpm_tables.uclk_table;
b4bb3aaf 953 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
90a89c31
EQ		 954 ret = smu_v11_0_set_single_dpm_table(smu,
955 SMU_UCLK,
956 dpm_table);
957 if (ret)
958 return ret;
959 dpm_table->is_fine_grained =
7077b19a 960 !table_member[PPCLK_UCLK].SnapToDiscrete;
90a89c31
EQ		 961 } else {
962 dpm_table->count = 1;
963 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
964 dpm_table->dpm_levels[0].enabled = true;
965 dpm_table->min = dpm_table->dpm_levels[0].value;
966 dpm_table->max = dpm_table->dpm_levels[0].value;
967 }
b455159c 968
90a89c31
EQ		 969 /* fclk dpm table setup */
970 dpm_table = &dpm_context->dpm_tables.fclk_table;
b4bb3aaf 971 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
90a89c31
EQ		 972 ret = smu_v11_0_set_single_dpm_table(smu,
973 SMU_FCLK,
974 dpm_table);
975 if (ret)
976 return ret;
977 dpm_table->is_fine_grained =
7077b19a 978 !table_member[PPCLK_FCLK].SnapToDiscrete;
90a89c31
EQ		 979 } else {
980 dpm_table->count = 1;
981 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
982 dpm_table->dpm_levels[0].enabled = true;
983 dpm_table->min = dpm_table->dpm_levels[0].value;
984 dpm_table->max = dpm_table->dpm_levels[0].value;
985 }
b455159c 986
0b54122c
AD		 987 /* vclk0/1 dpm table setup */
988 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
989 if (adev->vcn.harvest_config & (1 << i))
990 continue;
b455159c 991
0b54122c 992 dpm_table = &dpm_context->dpm_tables.vclk_table;
85dec717
JC		 993 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
994 ret = smu_v11_0_set_single_dpm_table(smu,
0b54122c 995 i ? SMU_VCLK1 : SMU_VCLK,
85dec717
JC		 996 dpm_table);
997 if (ret)
998 return ret;
999 dpm_table->is_fine_grained =
0b54122c 1000 !table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete;
85dec717
JC		 1001 } else {
1002 dpm_table->count = 1;
0b54122c 1003 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
85dec717
JC		 1004 dpm_table->dpm_levels[0].enabled = true;
1005 dpm_table->min = dpm_table->dpm_levels[0].value;
1006 dpm_table->max = dpm_table->dpm_levels[0].value;
1007 }
90a89c31 1008 }
b455159c 1009
0b54122c
AD		 1010 /* dclk0/1 dpm table setup */
1011 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1012 if (adev->vcn.harvest_config & (1 << i))
1013 continue;
1014 dpm_table = &dpm_context->dpm_tables.dclk_table;
85dec717
JC		 1015 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1016 ret = smu_v11_0_set_single_dpm_table(smu,
0b54122c 1017 i ? SMU_DCLK1 : SMU_DCLK,
85dec717
JC		 1018 dpm_table);
1019 if (ret)
1020 return ret;
1021 dpm_table->is_fine_grained =
0b54122c 1022 !table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0].SnapToDiscrete;
85dec717
JC		 1023 } else {
1024 dpm_table->count = 1;
0b54122c 1025 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
85dec717
JC		 1026 dpm_table->dpm_levels[0].enabled = true;
1027 dpm_table->min = dpm_table->dpm_levels[0].value;
1028 dpm_table->max = dpm_table->dpm_levels[0].value;
1029 }
90a89c31
EQ		 1030 }
1031
1032 /* dcefclk dpm table setup */
1033 dpm_table = &dpm_context->dpm_tables.dcef_table;
b4bb3aaf 1034 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 1035 ret = smu_v11_0_set_single_dpm_table(smu,
1036 SMU_DCEFCLK,
1037 dpm_table);
1038 if (ret)
1039 return ret;
1040 dpm_table->is_fine_grained =
7077b19a 1041 !table_member[PPCLK_DCEFCLK].SnapToDiscrete;
90a89c31
EQ		 1042 } else {
1043 dpm_table->count = 1;
1044 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1045 dpm_table->dpm_levels[0].enabled = true;
1046 dpm_table->min = dpm_table->dpm_levels[0].value;
1047 dpm_table->max = dpm_table->dpm_levels[0].value;
1048 }
b455159c 1049
90a89c31
EQ		 1050 /* pixelclk dpm table setup */
1051 dpm_table = &dpm_context->dpm_tables.pixel_table;
b4bb3aaf 1052 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 1053 ret = smu_v11_0_set_single_dpm_table(smu,
1054 SMU_PIXCLK,
1055 dpm_table);
1056 if (ret)
1057 return ret;
1058 dpm_table->is_fine_grained =
7077b19a 1059 !table_member[PPCLK_PIXCLK].SnapToDiscrete;
90a89c31
EQ		 1060 } else {
1061 dpm_table->count = 1;
1062 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1063 dpm_table->dpm_levels[0].enabled = true;
1064 dpm_table->min = dpm_table->dpm_levels[0].value;
1065 dpm_table->max = dpm_table->dpm_levels[0].value;
1066 }
b455159c 1067
90a89c31
EQ		 1068 /* displayclk dpm table setup */
1069 dpm_table = &dpm_context->dpm_tables.display_table;
b4bb3aaf 1070 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 1071 ret = smu_v11_0_set_single_dpm_table(smu,
1072 SMU_DISPCLK,
1073 dpm_table);
1074 if (ret)
1075 return ret;
1076 dpm_table->is_fine_grained =
7077b19a 1077 !table_member[PPCLK_DISPCLK].SnapToDiscrete;
90a89c31
EQ		 1078 } else {
1079 dpm_table->count = 1;
1080 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1081 dpm_table->dpm_levels[0].enabled = true;
1082 dpm_table->min = dpm_table->dpm_levels[0].value;
1083 dpm_table->max = dpm_table->dpm_levels[0].value;
1084 }
b455159c 1085
90a89c31
EQ		 1086 /* phyclk dpm table setup */
1087 dpm_table = &dpm_context->dpm_tables.phy_table;
b4bb3aaf 1088 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 1089 ret = smu_v11_0_set_single_dpm_table(smu,
1090 SMU_PHYCLK,
1091 dpm_table);
1092 if (ret)
1093 return ret;
1094 dpm_table->is_fine_grained =
7077b19a 1095 !table_member[PPCLK_PHYCLK].SnapToDiscrete;
90a89c31
EQ		 1096 } else {
1097 dpm_table->count = 1;
1098 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1099 dpm_table->dpm_levels[0].enabled = true;
1100 dpm_table->min = dpm_table->dpm_levels[0].value;
1101 dpm_table->max = dpm_table->dpm_levels[0].value;
1102 }
b455159c
LG		 1103
1104 return 0;
1105}
1106
f6b4b4a1 1107static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
b455159c 1108{
d51dc613 1109 struct amdgpu_device *adev = smu->adev;
0b54122c 1110 int i, ret = 0;
b455159c 1111
0b54122c
AD		 1112 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1113 if (adev->vcn.harvest_config & (1 << i))
1114 continue;
b455159c 1115 /* vcn dpm on is a prerequisite for vcn power gate messages */
b4bb3aaf 1116 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
0b54122c
AD		 1117 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1118 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
1119 0x10000 * i, NULL);
6fb176a7
LG		 1120 if (ret)
1121 return ret;
b455159c 1122 }
b455159c
LG		 1123 }
1124
1125 return ret;
1126}
1127
6fb176a7
LG		 1128static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
1129{
6fb176a7
LG		 1130 int ret = 0;
1131
1132 if (enable) {
b4bb3aaf 1133 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 1134 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
6fb176a7
LG		 1135 if (ret)
1136 return ret;
6fb176a7 1137 }
6fb176a7 1138 } else {
b4bb3aaf 1139 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 1140 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
6fb176a7
LG		 1141 if (ret)
1142 return ret;
6fb176a7 1143 }
6fb176a7
LG		 1144 }
1145
1146 return ret;
1147}
1148
b455159c
LG		 1149static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
1150 enum smu_clk_type clk_type,
1151 uint32_t *value)
1152{
8c686254
EQ		 1153 MetricsMember_t member_type;
1154 int clk_id = 0;
b455159c 1155
6c339f37
EQ		 1156 clk_id = smu_cmn_to_asic_specific_index(smu,
1157 CMN2ASIC_MAPPING_CLK,
1158 clk_type);
b455159c
LG		 1159 if (clk_id < 0)
1160 return clk_id;
1161
8c686254
EQ		 1162 switch (clk_id) {
1163 case PPCLK_GFXCLK:
1164 member_type = METRICS_CURR_GFXCLK;
1165 break;
1166 case PPCLK_UCLK:
1167 member_type = METRICS_CURR_UCLK;
1168 break;
1169 case PPCLK_SOCCLK:
1170 member_type = METRICS_CURR_SOCCLK;
1171 break;
1172 case PPCLK_FCLK:
1173 member_type = METRICS_CURR_FCLK;
1174 break;
1175 case PPCLK_VCLK_0:
1176 member_type = METRICS_CURR_VCLK;
1177 break;
1178 case PPCLK_VCLK_1:
1179 member_type = METRICS_CURR_VCLK1;
1180 break;
1181 case PPCLK_DCLK_0:
1182 member_type = METRICS_CURR_DCLK;
1183 break;
1184 case PPCLK_DCLK_1:
1185 member_type = METRICS_CURR_DCLK1;
1186 break;
1187 case PPCLK_DCEFCLK:
1188 member_type = METRICS_CURR_DCEFCLK;
1189 break;
1190 default:
1191 return -EINVAL;
1192 }
1193
1194 return sienna_cichlid_get_smu_metrics_data(smu,
1195 member_type,
1196 value);
b455159c 1197
b455159c
LG		 1198}
1199
1200static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1201{
b455159c 1202 DpmDescriptor_t *dpm_desc = NULL;
7077b19a 1203 DpmDescriptor_t *table_member;
b455159c
LG		 1204 uint32_t clk_index = 0;
1205
7077b19a 1206 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
6c339f37
EQ		 1207 clk_index = smu_cmn_to_asic_specific_index(smu,
1208 CMN2ASIC_MAPPING_CLK,
1209 clk_type);
7077b19a 1210 dpm_desc = &table_member[clk_index];
b455159c
LG		 1211
1212 /* 0 - Fine grained DPM, 1 - Discrete DPM */
0ee56acc 1213 return dpm_desc->SnapToDiscrete == 0;
b455159c
LG		 1214}
1215
37a58f69
EQ		 1216static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
1217 enum SMU_11_0_7_ODFEATURE_CAP cap)
1218{
1219 return od_table->cap[cap];
1220}
1221
1222static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
1223 enum SMU_11_0_7_ODSETTING_ID setting,
1224 uint32_t *min, uint32_t *max)
1225{
1226 if (min)
1227 *min = od_table->min[setting];
1228 if (max)
1229 *max = od_table->max[setting];
1230}
1231
b455159c
LG		 1232static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
1233 enum smu_clk_type clk_type, char *buf)
1234{
b7d25b5f
LG		 1235 struct amdgpu_device *adev = smu->adev;
1236 struct smu_table_context *table_context = &smu->smu_table;
1237 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1238 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
7077b19a
CG		 1239 uint16_t *table_member;
1240
37a58f69
EQ		 1241 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
1242 OverDriveTable_t *od_table =
1243 (OverDriveTable_t *)table_context->overdrive_table;
b455159c
LG		 1244 int i, size = 0, ret = 0;
1245 uint32_t cur_value = 0, value = 0, count = 0;
1246 uint32_t freq_values[3] = {0};
1247 uint32_t mark_index = 0;
b7d25b5f 1248 uint32_t gen_speed, lane_width;
37a58f69 1249 uint32_t min_value, max_value;
a2b6df4f 1250 uint32_t smu_version;
b455159c 1251
8f48ba30
LY		 1252 smu_cmn_get_sysfs_buf(&buf, &size);
1253
b455159c
LG		 1254 switch (clk_type) {
1255 case SMU_GFXCLK:
1256 case SMU_SCLK:
1257 case SMU_SOCCLK:
1258 case SMU_MCLK:
1259 case SMU_UCLK:
1260 case SMU_FCLK:
78842457
DN		 1261 case SMU_VCLK:
1262 case SMU_VCLK1:
1263 case SMU_DCLK:
1264 case SMU_DCLK1:
b455159c 1265 case SMU_DCEFCLK:
5e6dc8fe 1266 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
b455159c 1267 if (ret)
258d290c 1268 goto print_clk_out;
b455159c 1269
d8d3493a 1270 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
b455159c 1271 if (ret)
258d290c 1272 goto print_clk_out;
b455159c
LG		 1273
1274 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1275 for (i = 0; i < count; i++) {
d8d3493a 1276 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
b455159c 1277 if (ret)
258d290c 1278 goto print_clk_out;
b455159c 1279
fe14c285 1280 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
b455159c
LG		 1281 cur_value == value ? "*" : "");
1282 }
1283 } else {
d8d3493a 1284 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
b455159c 1285 if (ret)
258d290c 1286 goto print_clk_out;
d8d3493a 1287 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
b455159c 1288 if (ret)
258d290c 1289 goto print_clk_out;
b455159c
LG		 1290
1291 freq_values[1] = cur_value;
1292 mark_index = cur_value == freq_values[0] ? 0 :
1293 cur_value == freq_values[2] ? 2 : 1;
b455159c 1294
891bacb8
KF		 1295 count = 3;
1296 if (mark_index != 1) {
1297 count = 2;
1298 freq_values[1] = freq_values[2];
1299 }
1300
1301 for (i = 0; i < count; i++) {
fe14c285 1302 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
891bacb8 1303 cur_value == freq_values[i] ? "*" : "");
b455159c
LG		 1304 }
1305
1306 }
1307 break;
b7d25b5f 1308 case SMU_PCIE:
f20c52f4
LG		 1309 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1310 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
7077b19a 1311 GET_PPTABLE_MEMBER(LclkFreq, &table_member);
b7d25b5f 1312 for (i = 0; i < NUM_LINK_LEVELS; i++)
fe14c285 1313 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
b7d25b5f
LG		 1314 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1315 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1316 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1317 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1318 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1319 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1320 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1321 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1322 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1323 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
7077b19a 1324 table_member[i],
b7d25b5f
LG		 1325 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1326 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1327 "*" : "");
1328 break;
37a58f69
EQ		 1329 case SMU_OD_SCLK:
1330 if (!smu->od_enabled || !od_table || !od_settings)
1331 break;
1332
1333 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1334 break;
1335
fe14c285
DP		 1336 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1337 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
37a58f69
EQ		 1338 break;
1339
1340 case SMU_OD_MCLK:
1341 if (!smu->od_enabled || !od_table || !od_settings)
1342 break;
1343
1344 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1345 break;
1346
fe14c285
DP		 1347 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1348 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
37a58f69
EQ		 1349 break;
1350
a2b6df4f
EQ		 1351 case SMU_OD_VDDGFX_OFFSET:
1352 if (!smu->od_enabled || !od_table || !od_settings)
1353 break;
1354
1355 /*
1356 * OD GFX Voltage Offset functionality is supported only by 58.41.0
1357 * and onwards SMU firmwares.
1358 */
1359 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1d789535 1360 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
a2b6df4f
EQ		 1361 (smu_version < 0x003a2900))
1362 break;
1363
fe14c285
DP		 1364 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1365 size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset);
a2b6df4f
EQ		 1366 break;
1367
37a58f69
EQ		 1368 case SMU_OD_RANGE:
1369 if (!smu->od_enabled || !od_table || !od_settings)
1370 break;
1371
8f48ba30 1372 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
37a58f69
EQ		 1373
1374 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1375 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1376 &min_value, NULL);
1377 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1378 NULL, &max_value);
fe14c285 1379 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
37a58f69
EQ		 1380 min_value, max_value);
1381 }
1382
1383 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1384 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1385 &min_value, NULL);
1386 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1387 NULL, &max_value);
fe14c285 1388 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
37a58f69
EQ		 1389 min_value, max_value);
1390 }
1391 break;
1392
b455159c
LG		 1393 default:
1394 break;
1395 }
1396
258d290c 1397print_clk_out:
b455159c
LG		 1398 return size;
1399}
1400
1401static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1402 enum smu_clk_type clk_type, uint32_t mask)
1403{
d3c98301 1404 int ret = 0;
b455159c
LG		 1405 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1406
1407 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1408 soft_max_level = mask ? (fls(mask) - 1) : 0;
1409
1410 switch (clk_type) {
1411 case SMU_GFXCLK:
1412 case SMU_SCLK:
1413 case SMU_SOCCLK:
1414 case SMU_MCLK:
1415 case SMU_UCLK:
b455159c 1416 case SMU_FCLK:
9ad9c8ac
LG		 1417 /* There is only 2 levels for fine grained DPM */
1418 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1419 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1420 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1421 }
1422
d8d3493a 1423 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
b455159c 1424 if (ret)
258d290c 1425 goto forec_level_out;
b455159c 1426
d8d3493a 1427 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
b455159c 1428 if (ret)
258d290c 1429 goto forec_level_out;
b455159c 1430
10e96d89 1431 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
b455159c 1432 if (ret)
258d290c 1433 goto forec_level_out;
b455159c 1434 break;
51ec6992
DP		 1435 case SMU_DCEFCLK:
1436 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1437 break;
b455159c
LG		 1438 default:
1439 break;
1440 }
1441
258d290c 1442forec_level_out:
d3c98301 1443 return 0;
b455159c
LG		 1444}
1445
1446static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1447{
62cc9dd1
EQ		 1448 struct smu_11_0_dpm_context *dpm_context =
1449 smu->smu_dpm.dpm_context;
1450 struct smu_11_0_dpm_table *gfx_table =
1451 &dpm_context->dpm_tables.gfx_table;
1452 struct smu_11_0_dpm_table *mem_table =
1453 &dpm_context->dpm_tables.uclk_table;
1454 struct smu_11_0_dpm_table *soc_table =
1455 &dpm_context->dpm_tables.soc_table;
1456 struct smu_umd_pstate_table *pstate_table =
1457 &smu->pstate_table;
60aac460 1458 struct amdgpu_device *adev = smu->adev;
62cc9dd1
EQ		 1459
1460 pstate_table->gfxclk_pstate.min = gfx_table->min;
1461 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1462
1463 pstate_table->uclk_pstate.min = mem_table->min;
1464 pstate_table->uclk_pstate.peak = mem_table->max;
1465
1466 pstate_table->socclk_pstate.min = soc_table->min;
1467 pstate_table->socclk_pstate.peak = soc_table->max;
60aac460 1468
9d6b2041
AD		 1469 switch (adev->ip_versions[MP1_HWIP][0]) {
1470 case IP_VERSION(11, 0, 7):
1471 case IP_VERSION(11, 0, 11):
60aac460
EQ		 1472 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
1473 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
0dc994fb 1474 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
60aac460 1475 break;
9d6b2041 1476 case IP_VERSION(11, 0, 12):
60aac460
EQ		 1477 pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK;
1478 pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK;
1479 pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK;
1480 break;
9d6b2041 1481 case IP_VERSION(11, 0, 13):
60aac460
EQ		 1482 pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK;
1483 pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK;
1484 pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK;
1485 break;
1486 default:
1487 break;
1488 }
b455159c 1489
62cc9dd1 1490 return 0;
b455159c
LG		 1491}
1492
b455159c
LG		 1493static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1494{
1495 int ret = 0;
1496 uint32_t max_freq = 0;
1497
1498 /* Sienna_Cichlid do not support to change display num currently */
1499 return 0;
1500#if 0
66c86828 1501 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
b455159c
LG		 1502 if (ret)
1503 return ret;
1504#endif
1505
b4bb3aaf 1506 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
e5ef784b 1507 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
b455159c
LG		 1508 if (ret)
1509 return ret;
661b94f5 1510 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
b455159c
LG		 1511 if (ret)
1512 return ret;
1513 }
1514
1515 return ret;
1516}
1517
1518static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1519{
1520 int ret = 0;
1521
b455159c 1522 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
7ade3ca9
EQ		 1523 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1524 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
b455159c 1525#if 0
66c86828 1526 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
40d3b8db
LG		 1527 smu->display_config->num_display,
1528 NULL);
b455159c
LG		 1529#endif
1530 if (ret)
1531 return ret;
1532 }
1533
1534 return ret;
1535}
1536
b455159c
LG		 1537static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1538{
1539 int ret = 0;
3d14a79b
KW		 1540 uint64_t feature_enabled;
1541
2d282665 1542 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
3d14a79b
KW		 1543 if (ret)
1544 return false;
1545
b455159c
LG		 1546 return !!(feature_enabled & SMC_DPM_FEATURE);
1547}
1548
d9ca7567
EQ		 1549static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1550 uint32_t *speed)
1551{
1552 if (!speed)
1553 return -EINVAL;
1554
1555 /*
1556 * For Sienna_Cichlid and later, the fan speed(rpm) reported
1557 * by pmfw is always trustable(even when the fan control feature
1558 * disabled or 0 RPM kicked in).
1559 */
1560 return sienna_cichlid_get_smu_metrics_data(smu,
1561 METRICS_CURR_FANSPEED,
1562 speed);
1563}
1564
3204ff3e
AD		 1565static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1566{
7077b19a 1567 uint16_t *table_member;
3204ff3e 1568
7077b19a
CG		 1569 GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
1570 smu->fan_max_rpm = *table_member;
3204ff3e
AD		 1571
1572 return 0;
1573}
1574
b455159c
LG		 1575static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1576{
f9e3fe46
EQ		 1577 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1578 DpmActivityMonitorCoeffInt_t *activity_monitor =
1579 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
b455159c
LG		 1580 uint32_t i, size = 0;
1581 int16_t workload_type = 0;
b455159c
LG		 1582 static const char *title[] = {
1583 "PROFILE_INDEX(NAME)",
1584 "CLOCK_TYPE(NAME)",
1585 "FPS",
1586 "MinFreqType",
1587 "MinActiveFreqType",
1588 "MinActiveFreq",
1589 "BoosterFreqType",
1590 "BoosterFreq",
1591 "PD_Data_limit_c",
1592 "PD_Data_error_coeff",
1593 "PD_Data_error_rate_coeff"};
1594 int result = 0;
1595
1596 if (!buf)
1597 return -EINVAL;
1598
fe14c285 1599 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
b455159c
LG		 1600 title[0], title[1], title[2], title[3], title[4], title[5],
1601 title[6], title[7], title[8], title[9], title[10]);
1602
1603 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1604 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
6c339f37
EQ		 1605 workload_type = smu_cmn_to_asic_specific_index(smu,
1606 CMN2ASIC_MAPPING_WORKLOAD,
1607 i);
b455159c
LG		 1608 if (workload_type < 0)
1609 return -EINVAL;
1610
caad2613 1611 result = smu_cmn_update_table(smu,
b455159c 1612 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
f9e3fe46 1613 (void *)(&activity_monitor_external), false);
b455159c 1614 if (result) {
d9811cfc 1615 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
b455159c
LG		 1616 return result;
1617 }
1618
fe14c285 1619 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
94a80b5b 1620 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
b455159c 1621
fe14c285 1622 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
b455159c
LG		 1623 " ",
1624 0,
1625 "GFXCLK",
f9e3fe46
EQ		 1626 activity_monitor->Gfx_FPS,
1627 activity_monitor->Gfx_MinFreqStep,
1628 activity_monitor->Gfx_MinActiveFreqType,
1629 activity_monitor->Gfx_MinActiveFreq,
1630 activity_monitor->Gfx_BoosterFreqType,
1631 activity_monitor->Gfx_BoosterFreq,
1632 activity_monitor->Gfx_PD_Data_limit_c,
1633 activity_monitor->Gfx_PD_Data_error_coeff,
1634 activity_monitor->Gfx_PD_Data_error_rate_coeff);
b455159c 1635
fe14c285 1636 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
b455159c
LG		 1637 " ",
1638 1,
1639 "SOCCLK",
f9e3fe46
EQ		 1640 activity_monitor->Fclk_FPS,
1641 activity_monitor->Fclk_MinFreqStep,
1642 activity_monitor->Fclk_MinActiveFreqType,
1643 activity_monitor->Fclk_MinActiveFreq,
1644 activity_monitor->Fclk_BoosterFreqType,
1645 activity_monitor->Fclk_BoosterFreq,
1646 activity_monitor->Fclk_PD_Data_limit_c,
1647 activity_monitor->Fclk_PD_Data_error_coeff,
1648 activity_monitor->Fclk_PD_Data_error_rate_coeff);
b455159c 1649
fe14c285 1650 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
b455159c
LG		 1651 " ",
1652 2,
1653 "MEMLK",
f9e3fe46
EQ		 1654 activity_monitor->Mem_FPS,
1655 activity_monitor->Mem_MinFreqStep,
1656 activity_monitor->Mem_MinActiveFreqType,
1657 activity_monitor->Mem_MinActiveFreq,
1658 activity_monitor->Mem_BoosterFreqType,
1659 activity_monitor->Mem_BoosterFreq,
1660 activity_monitor->Mem_PD_Data_limit_c,
1661 activity_monitor->Mem_PD_Data_error_coeff,
1662 activity_monitor->Mem_PD_Data_error_rate_coeff);
b455159c
LG		 1663 }
1664
1665 return size;
1666}
1667
1668static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1669{
f9e3fe46
EQ		 1670
1671 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1672 DpmActivityMonitorCoeffInt_t *activity_monitor =
1673 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
b455159c
LG		 1674 int workload_type, ret = 0;
1675
1676 smu->power_profile_mode = input[size];
1677
1678 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
d9811cfc 1679 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
b455159c
LG		 1680 return -EINVAL;
1681 }
1682
1683 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
b455159c 1684
caad2613 1685 ret = smu_cmn_update_table(smu,
b455159c 1686 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
f9e3fe46 1687 (void *)(&activity_monitor_external), false);
b455159c 1688 if (ret) {
d9811cfc 1689 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
b455159c
LG		 1690 return ret;
1691 }
1692
1693 switch (input[0]) {
1694 case 0: /* Gfxclk */
f9e3fe46
EQ		 1695 activity_monitor->Gfx_FPS = input[1];
1696 activity_monitor->Gfx_MinFreqStep = input[2];
1697 activity_monitor->Gfx_MinActiveFreqType = input[3];
1698 activity_monitor->Gfx_MinActiveFreq = input[4];
1699 activity_monitor->Gfx_BoosterFreqType = input[5];
1700 activity_monitor->Gfx_BoosterFreq = input[6];
1701 activity_monitor->Gfx_PD_Data_limit_c = input[7];
1702 activity_monitor->Gfx_PD_Data_error_coeff = input[8];
1703 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1704 break;
1705 case 1: /* Socclk */
f9e3fe46
EQ		 1706 activity_monitor->Fclk_FPS = input[1];
1707 activity_monitor->Fclk_MinFreqStep = input[2];
1708 activity_monitor->Fclk_MinActiveFreqType = input[3];
1709 activity_monitor->Fclk_MinActiveFreq = input[4];
1710 activity_monitor->Fclk_BoosterFreqType = input[5];
1711 activity_monitor->Fclk_BoosterFreq = input[6];
1712 activity_monitor->Fclk_PD_Data_limit_c = input[7];
1713 activity_monitor->Fclk_PD_Data_error_coeff = input[8];
1714 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1715 break;
1716 case 2: /* Memlk */
f9e3fe46
EQ		 1717 activity_monitor->Mem_FPS = input[1];
1718 activity_monitor->Mem_MinFreqStep = input[2];
1719 activity_monitor->Mem_MinActiveFreqType = input[3];
1720 activity_monitor->Mem_MinActiveFreq = input[4];
1721 activity_monitor->Mem_BoosterFreqType = input[5];
1722 activity_monitor->Mem_BoosterFreq = input[6];
1723 activity_monitor->Mem_PD_Data_limit_c = input[7];
1724 activity_monitor->Mem_PD_Data_error_coeff = input[8];
1725 activity_monitor->Mem_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1726 break;
1727 }
1728
caad2613 1729 ret = smu_cmn_update_table(smu,
b455159c 1730 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
f9e3fe46 1731 (void *)(&activity_monitor_external), true);
b455159c 1732 if (ret) {
d9811cfc 1733 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
b455159c
LG		 1734 return ret;
1735 }
1736 }
1737
1738 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
6c339f37
EQ		 1739 workload_type = smu_cmn_to_asic_specific_index(smu,
1740 CMN2ASIC_MAPPING_WORKLOAD,
1741 smu->power_profile_mode);
b455159c
LG		 1742 if (workload_type < 0)
1743 return -EINVAL;
66c86828 1744 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
b455159c
LG		 1745 1 << workload_type, NULL);
1746
1747 return ret;
1748}
1749
b455159c
LG		 1750static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1751{
1752 struct smu_clocks min_clocks = {0};
1753 struct pp_display_clock_request clock_req;
1754 int ret = 0;
1755
1756 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1757 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1758 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1759
7ade3ca9 1760 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
b455159c
LG		 1761 clock_req.clock_type = amd_pp_dcef_clock;
1762 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1763
1764 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1765 if (!ret) {
7ade3ca9 1766 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
66c86828 1767 ret = smu_cmn_send_smc_msg_with_param(smu,
40d3b8db
LG		 1768 SMU_MSG_SetMinDeepSleepDcefclk,
1769 min_clocks.dcef_clock_in_sr/100,
1770 NULL);
1771 if (ret) {
d9811cfc 1772 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
40d3b8db
LG		 1773 return ret;
1774 }
b455159c
LG		 1775 }
1776 } else {
d9811cfc 1777 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
b455159c
LG		 1778 }
1779 }
1780
b4bb3aaf 1781 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
661b94f5 1782 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
b455159c 1783 if (ret) {
d9811cfc 1784 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
b455159c
LG		 1785 return ret;
1786 }
1787 }
1788
1789 return 0;
1790}
1791
1792static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
7b9c7e30 1793 struct pp_smu_wm_range_sets *clock_ranges)
b455159c 1794{
e7a95eea 1795 Watermarks_t *table = smu->smu_table.watermarks_table;
40d3b8db 1796 int ret = 0;
e7a95eea 1797 int i;
b455159c 1798
e7a95eea 1799 if (clock_ranges) {
7b9c7e30
EQ		 1800 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1801 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
e7a95eea
EQ		 1802 return -EINVAL;
1803
7b9c7e30
EQ		 1804 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1805 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1806 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1807 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1808 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1809 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1810 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1811 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1812 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1813
1814 table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1815 clock_ranges->reader_wm_sets[i].wm_inst;
e7a95eea 1816 }
b455159c 1817
7b9c7e30
EQ		 1818 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1819 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1820 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1821 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1822 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1823 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1824 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1825 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1826 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1827
1828 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1829 clock_ranges->writer_wm_sets[i].wm_inst;
e7a95eea
EQ		 1830 }
1831
1832 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1833 }
1834
1835 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1836 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
caad2613 1837 ret = smu_cmn_write_watermarks_table(smu);
40d3b8db 1838 if (ret) {
d9811cfc 1839 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
40d3b8db
LG		 1840 return ret;
1841 }
1842 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1843 }
1844
b455159c
LG		 1845 return 0;
1846}
1847
b455159c
LG		 1848static int sienna_cichlid_read_sensor(struct smu_context *smu,
1849 enum amd_pp_sensors sensor,
1850 void *data, uint32_t *size)
1851{
1852 int ret = 0;
7077b19a 1853 uint16_t *temp;
d6810d7d 1854 struct amdgpu_device *adev = smu->adev;
b455159c
LG		 1855
1856 if(!data || !size)
1857 return -EINVAL;
1858
b455159c
LG		 1859 switch (sensor) {
1860 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
7077b19a
CG		 1861 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
1862 *(uint16_t *)data = *temp;
b455159c
LG		 1863 *size = 4;
1864 break;
1865 case AMDGPU_PP_SENSOR_MEM_LOAD:
60e317a2
AD		 1866 ret = sienna_cichlid_get_smu_metrics_data(smu,
1867 METRICS_AVERAGE_MEMACTIVITY,
1868 (uint32_t *)data);
1869 *size = 4;
1870 break;
b455159c 1871 case AMDGPU_PP_SENSOR_GPU_LOAD:
60e317a2
AD		 1872 ret = sienna_cichlid_get_smu_metrics_data(smu,
1873 METRICS_AVERAGE_GFXACTIVITY,
1874 (uint32_t *)data);
b455159c
LG		 1875 *size = 4;
1876 break;
1877 case AMDGPU_PP_SENSOR_GPU_POWER:
60e317a2
AD		 1878 ret = sienna_cichlid_get_smu_metrics_data(smu,
1879 METRICS_AVERAGE_SOCKETPOWER,
1880 (uint32_t *)data);
b455159c
LG		 1881 *size = 4;
1882 break;
1883 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
60e317a2
AD		 1884 ret = sienna_cichlid_get_smu_metrics_data(smu,
1885 METRICS_TEMPERATURE_HOTSPOT,
1886 (uint32_t *)data);
1887 *size = 4;
1888 break;
b455159c 1889 case AMDGPU_PP_SENSOR_EDGE_TEMP:
60e317a2
AD		 1890 ret = sienna_cichlid_get_smu_metrics_data(smu,
1891 METRICS_TEMPERATURE_EDGE,
1892 (uint32_t *)data);
1893 *size = 4;
1894 break;
b455159c 1895 case AMDGPU_PP_SENSOR_MEM_TEMP:
60e317a2
AD		 1896 ret = sienna_cichlid_get_smu_metrics_data(smu,
1897 METRICS_TEMPERATURE_MEM,
1898 (uint32_t *)data);
b455159c
LG		 1899 *size = 4;
1900 break;
e0f9e936
EQ		 1901 case AMDGPU_PP_SENSOR_GFX_MCLK:
1902 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1903 *(uint32_t *)data *= 100;
1904 *size = 4;
1905 break;
1906 case AMDGPU_PP_SENSOR_GFX_SCLK:
1907 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1908 *(uint32_t *)data *= 100;
1909 *size = 4;
1910 break;
b2febc99
EQ		 1911 case AMDGPU_PP_SENSOR_VDDGFX:
1912 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1913 *size = 4;
1914 break;
d6810d7d
S		 1915 case AMDGPU_PP_SENSOR_SS_APU_SHARE:
1916 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) {
1917 ret = sienna_cichlid_get_smu_metrics_data(smu,
1918 METRICS_SS_APU_SHARE, (uint32_t *)data);
1919 *size = 4;
1920 } else {
1921 ret = -EOPNOTSUPP;
1922 }
1923 break;
1924 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
1925 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) {
1926 ret = sienna_cichlid_get_smu_metrics_data(smu,
1927 METRICS_SS_DGPU_SHARE, (uint32_t *)data);
1928 *size = 4;
1929 } else {
1930 ret = -EOPNOTSUPP;
1931 }
1932 break;
b455159c 1933 default:
b2febc99
EQ		 1934 ret = -EOPNOTSUPP;
1935 break;
b455159c 1936 }
b455159c
LG		 1937
1938 return ret;
1939}
1940
ebd9c071
KR		 1941static void sienna_cichlid_get_unique_id(struct smu_context *smu)
1942{
1943 struct amdgpu_device *adev = smu->adev;
1944 uint32_t upper32 = 0, lower32 = 0;
1945
1946 /* Only supported as of version 0.58.83.0 and only on Sienna Cichlid */
1947 if (smu->smc_fw_version < 0x3A5300 ||
1948 smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7))
1949 return;
1950
1951 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32))
1952 goto out;
1953 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32))
1954 goto out;
1955
1956out:
1957
1958 adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1959 if (adev->serial[0] == '\0')
1960 sprintf(adev->serial, "%016llx", adev->unique_id);
1961}
1962
b455159c
LG		 1963static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1964{
1965 uint32_t num_discrete_levels = 0;
1966 uint16_t *dpm_levels = NULL;
1967 uint16_t i = 0;
1968 struct smu_table_context *table_context = &smu->smu_table;
7077b19a
CG		 1969 DpmDescriptor_t *table_member1;
1970 uint16_t *table_member2;
b455159c
LG		 1971
1972 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1973 return -EINVAL;
1974
7077b19a
CG		 1975 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
1976 num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
1977 GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
1978 dpm_levels = table_member2;
b455159c
LG		 1979
1980 if (num_discrete_levels == 0 || dpm_levels == NULL)
1981 return -EINVAL;
1982
1983 *num_states = num_discrete_levels;
1984 for (i = 0; i < num_discrete_levels; i++) {
1985 /* convert to khz */
1986 *clocks_in_khz = (*dpm_levels) * 1000;
1987 clocks_in_khz++;
1988 dpm_levels++;
1989 }
1990
1991 return 0;
1992}
1993
1994static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1995 struct smu_temperature_range *range)
1996{
e02e4d51
EQ		 1997 struct smu_table_context *table_context = &smu->smu_table;
1998 struct smu_11_0_7_powerplay_table *powerplay_table =
1999 table_context->power_play_table;
7077b19a
CG		 2000 uint16_t *table_member;
2001 uint16_t temp_edge, temp_hotspot, temp_mem;
b455159c 2002
2b1f12a2 2003 if (!range)
b455159c
LG		 2004 return -EINVAL;
2005
0540eced
EQ		 2006 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
2007
7077b19a
CG		 2008 GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
2009 temp_edge = table_member[TEMP_EDGE];
2010 temp_hotspot = table_member[TEMP_HOTSPOT];
2011 temp_mem = table_member[TEMP_MEM];
2012
2013 range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2014 range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
2b1f12a2 2015 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a
CG		 2016 range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2017 range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
2b1f12a2 2018 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a
CG		 2019 range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2020 range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
b455159c 2021 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a 2022
e02e4d51 2023 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
b455159c
LG		 2024
2025 return 0;
2026}
2027
2028static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
2029 bool disable_memory_clock_switch)
2030{
2031 int ret = 0;
2032 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
2033 (struct smu_11_0_max_sustainable_clocks *)
2034 smu->smu_table.max_sustainable_clocks;
2035 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
2036 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
2037
2038 if(smu->disable_uclk_switch == disable_memory_clock_switch)
2039 return 0;
2040
2041 if(disable_memory_clock_switch)
661b94f5 2042 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
b455159c 2043 else
661b94f5 2044 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
b455159c
LG		 2045
2046 if(!ret)
2047 smu->disable_uclk_switch = disable_memory_clock_switch;
2048
2049 return ret;
2050}
2051
08ccfe08
LG		 2052static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
2053 uint32_t pcie_gen_cap,
2054 uint32_t pcie_width_cap)
2055{
0b590970 2056 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
7077b19a 2057
08ccfe08 2058 uint32_t smu_pcie_arg;
7077b19a 2059 uint8_t *table_member1, *table_member2;
0b590970 2060 int ret, i;
08ccfe08 2061
7077b19a
CG		 2062 GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
2063 GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
2064
0b590970
EQ		 2065 /* lclk dpm table setup */
2066 for (i = 0; i < MAX_PCIE_CONF; i++) {
7077b19a
CG		 2067 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = table_member1[i];
2068 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = table_member2[i];
0b590970 2069 }
08ccfe08
LG		 2070
2071 for (i = 0; i < NUM_LINK_LEVELS; i++) {
2072 smu_pcie_arg = (i << 16) |
7077b19a
CG		 2073 ((table_member1[i] <= pcie_gen_cap) ?
2074 (table_member1[i] << 8) :
2075 (pcie_gen_cap << 8)) |
2076 ((table_member2[i] <= pcie_width_cap) ?
2077 table_member2[i] :
2078 pcie_width_cap);
08ccfe08 2079
66c86828 2080 ret = smu_cmn_send_smc_msg_with_param(smu,
7077b19a
CG		 2081 SMU_MSG_OverridePcieParameters,
2082 smu_pcie_arg,
2083 NULL);
08ccfe08
LG		 2084 if (ret)
2085 return ret;
2086
7077b19a 2087 if (table_member1[i] > pcie_gen_cap)
08ccfe08 2088 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
7077b19a 2089 if (table_member2[i] > pcie_width_cap)
08ccfe08
LG		 2090 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
2091 }
2092
2093 return 0;
2094}
2095
38ed7b09 2096static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
258d290c
LG		 2097 enum smu_clk_type clk_type,
2098 uint32_t *min, uint32_t *max)
2099{
3bce90bf 2100 return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
258d290c
LG		 2101}
2102
aa75fa34
EQ		 2103static void sienna_cichlid_dump_od_table(struct smu_context *smu,
2104 OverDriveTable_t *od_table)
2105{
a2b6df4f
EQ		 2106 struct amdgpu_device *adev = smu->adev;
2107 uint32_t smu_version;
2108
aa75fa34
EQ		 2109 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
2110 od_table->GfxclkFmax);
2111 dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
2112 od_table->UclkFmax);
a2b6df4f
EQ		 2113
2114 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1d789535 2115 if (!((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
a2b6df4f
EQ		 2116 (smu_version < 0x003a2900)))
2117 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
aa75fa34
EQ		 2118}
2119
2120static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
2121{
2122 OverDriveTable_t *od_table =
2123 (OverDriveTable_t *)smu->smu_table.overdrive_table;
2124 OverDriveTable_t *boot_od_table =
2125 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
b521be9b
EQ		 2126 OverDriveTable_t *user_od_table =
2127 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
aa75fa34
EQ		 2128 int ret = 0;
2129
b521be9b
EQ		 2130 /*
2131 * For S3/S4/Runpm resume, no need to setup those overdrive tables again as
2132 * - either they already have the default OD settings got during cold bootup
2133 * - or they have some user customized OD settings which cannot be overwritten
2134 */
2135 if (smu->adev->in_suspend)
2136 return 0;
2137
aa75fa34 2138 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
b521be9b 2139 0, (void *)boot_od_table, false);
aa75fa34
EQ		 2140 if (ret) {
2141 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2142 return ret;
2143 }
2144
b521be9b 2145 sienna_cichlid_dump_od_table(smu, boot_od_table);
aa75fa34 2146
b521be9b
EQ		 2147 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
2148 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
aa75fa34
EQ		 2149
2150 return 0;
2151}
2152
37a58f69
EQ		 2153static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
2154 struct smu_11_0_7_overdrive_table *od_table,
2155 enum SMU_11_0_7_ODSETTING_ID setting,
2156 uint32_t value)
2157{
2158 if (value < od_table->min[setting]) {
2159 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
2160 setting, value, od_table->min[setting]);
2161 return -EINVAL;
2162 }
2163 if (value > od_table->max[setting]) {
2164 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
2165 setting, value, od_table->max[setting]);
2166 return -EINVAL;
2167 }
2168
2169 return 0;
2170}
2171
2172static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
2173 enum PP_OD_DPM_TABLE_COMMAND type,
2174 long input[], uint32_t size)
2175{
2176 struct smu_table_context *table_context = &smu->smu_table;
2177 OverDriveTable_t *od_table =
2178 (OverDriveTable_t *)table_context->overdrive_table;
2179 struct smu_11_0_7_overdrive_table *od_settings =
2180 (struct smu_11_0_7_overdrive_table *)smu->od_settings;
a2b6df4f 2181 struct amdgpu_device *adev = smu->adev;
37a58f69
EQ		 2182 enum SMU_11_0_7_ODSETTING_ID freq_setting;
2183 uint16_t *freq_ptr;
2184 int i, ret = 0;
a2b6df4f 2185 uint32_t smu_version;
37a58f69
EQ		 2186
2187 if (!smu->od_enabled) {
2188 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2189 return -EINVAL;
2190 }
2191
2192 if (!smu->od_settings) {
2193 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2194 return -ENOENT;
2195 }
2196
2197 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2198 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2199 return -EINVAL;
2200 }
2201
2202 switch (type) {
2203 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2204 if (!sienna_cichlid_is_od_feature_supported(od_settings,
2205 SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
2206 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2207 return -ENOTSUPP;
2208 }
2209
2210 for (i = 0; i < size; i += 2) {
2211 if (i + 2 > size) {
2212 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2213 return -EINVAL;
2214 }
2215
2216 switch (input[i]) {
2217 case 0:
2218 if (input[i + 1] > od_table->GfxclkFmax) {
2219 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2220 input[i + 1], od_table->GfxclkFmax);
2221 return -EINVAL;
2222 }
2223
2224 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
2225 freq_ptr = &od_table->GfxclkFmin;
2226 break;
2227
2228 case 1:
2229 if (input[i + 1] < od_table->GfxclkFmin) {
2230 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2231 input[i + 1], od_table->GfxclkFmin);
2232 return -EINVAL;
2233 }
2234
2235 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
2236 freq_ptr = &od_table->GfxclkFmax;
2237 break;
2238
2239 default:
2240 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2241 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2242 return -EINVAL;
2243 }
2244
2245 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2246 freq_setting, input[i + 1]);
2247 if (ret)
2248 return ret;
2249
2250 *freq_ptr = (uint16_t)input[i + 1];
2251 }
2252 break;
2253
2254 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2255 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
2256 dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2257 return -ENOTSUPP;
2258 }
2259
2260 for (i = 0; i < size; i += 2) {
2261 if (i + 2 > size) {
2262 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2263 return -EINVAL;
2264 }
2265
2266 switch (input[i]) {
2267 case 0:
2268 if (input[i + 1] > od_table->UclkFmax) {
2269 dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2270 input[i + 1], od_table->UclkFmax);
2271 return -EINVAL;
2272 }
2273
2274 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
2275 freq_ptr = &od_table->UclkFmin;
2276 break;
2277
2278 case 1:
2279 if (input[i + 1] < od_table->UclkFmin) {
2280 dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2281 input[i + 1], od_table->UclkFmin);
2282 return -EINVAL;
2283 }
2284
2285 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
2286 freq_ptr = &od_table->UclkFmax;
2287 break;
2288
2289 default:
2290 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2291 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2292 return -EINVAL;
2293 }
2294
2295 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2296 freq_setting, input[i + 1]);
2297 if (ret)
2298 return ret;
2299
2300 *freq_ptr = (uint16_t)input[i + 1];
2301 }
2302 break;
2303
2304 case PP_OD_RESTORE_DEFAULT_TABLE:
2305 memcpy(table_context->overdrive_table,
2306 table_context->boot_overdrive_table,
2307 sizeof(OverDriveTable_t));
2308 fallthrough;
2309
2310 case PP_OD_COMMIT_DPM_TABLE:
b521be9b
EQ		 2311 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2312 sienna_cichlid_dump_od_table(smu, od_table);
2313 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2314 if (ret) {
2315 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2316 return ret;
2317 }
2318 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2319 smu->user_dpm_profile.user_od = true;
37a58f69 2320
b521be9b
EQ		 2321 if (!memcmp(table_context->user_overdrive_table,
2322 table_context->boot_overdrive_table,
2323 sizeof(OverDriveTable_t)))
2324 smu->user_dpm_profile.user_od = false;
37a58f69
EQ		 2325 }
2326 break;
2327
a2b6df4f
EQ		 2328 case PP_OD_EDIT_VDDGFX_OFFSET:
2329 if (size != 1) {
2330 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2331 return -EINVAL;
2332 }
2333
2334 /*
2335 * OD GFX Voltage Offset functionality is supported only by 58.41.0
2336 * and onwards SMU firmwares.
2337 */
2338 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1d789535 2339 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
a2b6df4f
EQ		 2340 (smu_version < 0x003a2900)) {
2341 dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2342 "only by 58.41.0 and onwards SMU firmwares!\n");
2343 return -EOPNOTSUPP;
2344 }
2345
2346 od_table->VddGfxOffset = (int16_t)input[0];
2347
2348 sienna_cichlid_dump_od_table(smu, od_table);
2349 break;
2350
37a58f69
EQ		 2351 default:
2352 return -ENOSYS;
2353 }
2354
2355 return ret;
2356}
2357
66b8a9c0
JC		 2358static int sienna_cichlid_run_btc(struct smu_context *smu)
2359{
dc78fea1
LT		 2360 int res;
2361
2362 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2363 if (res)
2364 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2365
2366 return res;
66b8a9c0
JC		 2367}
2368
13d75ead
EQ		 2369static int sienna_cichlid_baco_enter(struct smu_context *smu)
2370{
2371 struct amdgpu_device *adev = smu->adev;
2372
8b514e89 2373 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
13d75ead
EQ		 2374 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2375 else
2376 return smu_v11_0_baco_enter(smu);
2377}
2378
2379static int sienna_cichlid_baco_exit(struct smu_context *smu)
2380{
2381 struct amdgpu_device *adev = smu->adev;
2382
8b514e89 2383 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
13d75ead
EQ		 2384 /* Wait for PMFW handling for the Dstate change */
2385 msleep(10);
2386 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2387 } else {
2388 return smu_v11_0_baco_exit(smu);
2389 }
2390}
2391
ea8139d8
WS		 2392static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2393{
2394 struct amdgpu_device *adev = smu->adev;
2395 uint32_t val;
2396 u32 smu_version;
2397
2398 /**
2399 * SRIOV env will not support SMU mode1 reset
2400 * PM FW support mode1 reset from 58.26
2401 */
a7bae061 2402 smu_cmn_get_smc_version(smu, NULL, &smu_version);
ea8139d8
WS		 2403 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
2404 return false;
2405
2406 /**
2407 * mode1 reset relies on PSP, so we should check if
2408 * PSP is alive.
2409 */
2410 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2411 return val != 0x0;
2412}
2413
7077b19a
CG		 2414static void beige_goby_dump_pptable(struct smu_context *smu)
2415{
2416 struct smu_table_context *table_context = &smu->smu_table;
2417 PPTable_beige_goby_t *pptable = table_context->driver_pptable;
2418 int i;
2419
2420 dev_info(smu->adev->dev, "Dumped PPTable:\n");
2421
2422 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2423 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2424 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2425
2426 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2427 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2428 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2429 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2430 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2431 }
2432
2433 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2434 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2435 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2436 }
2437
2438 for (i = 0; i < TEMP_COUNT; i++) {
2439 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2440 }
2441
2442 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2443 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2444 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2445 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2446 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2447
2448 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2449 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2450 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2451 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2452 }
2453 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2454
2455 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2456
2457 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2458 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2459 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2460 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2461
2462 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2463
2464 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2465
2466 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2467 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2468 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2469 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2470
2471 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2472 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2473
2474 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2475 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2476 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2477 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2478 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2479 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2480 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2481 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2482
2483 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2484 " .VoltageMode = 0x%02x\n"
2485 " .SnapToDiscrete = 0x%02x\n"
2486 " .NumDiscreteLevels = 0x%02x\n"
2487 " .padding = 0x%02x\n"
2488 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2489 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2490 " .SsFmin = 0x%04x\n"
2491 " .Padding_16 = 0x%04x\n",
2492 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2493 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2494 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2495 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2496 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2497 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2498 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2499 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2500 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2501 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2502 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2503
2504 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2505 " .VoltageMode = 0x%02x\n"
2506 " .SnapToDiscrete = 0x%02x\n"
2507 " .NumDiscreteLevels = 0x%02x\n"
2508 " .padding = 0x%02x\n"
2509 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2510 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2511 " .SsFmin = 0x%04x\n"
2512 " .Padding_16 = 0x%04x\n",
2513 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2514 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2515 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2516 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2517 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2518 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2519 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2520 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2521 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2522 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2523 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2524
2525 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2526 " .VoltageMode = 0x%02x\n"
2527 " .SnapToDiscrete = 0x%02x\n"
2528 " .NumDiscreteLevels = 0x%02x\n"
2529 " .padding = 0x%02x\n"
2530 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2531 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2532 " .SsFmin = 0x%04x\n"
2533 " .Padding_16 = 0x%04x\n",
2534 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2535 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2536 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2537 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2538 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2539 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2540 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2541 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2542 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2543 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2544 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2545
2546 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2547 " .VoltageMode = 0x%02x\n"
2548 " .SnapToDiscrete = 0x%02x\n"
2549 " .NumDiscreteLevels = 0x%02x\n"
2550 " .padding = 0x%02x\n"
2551 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2552 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2553 " .SsFmin = 0x%04x\n"
2554 " .Padding_16 = 0x%04x\n",
2555 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2556 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2557 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2558 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2559 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2560 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2561 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2562 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2563 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2564 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2565 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2566
2567 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2568 " .VoltageMode = 0x%02x\n"
2569 " .SnapToDiscrete = 0x%02x\n"
2570 " .NumDiscreteLevels = 0x%02x\n"
2571 " .padding = 0x%02x\n"
2572 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2573 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2574 " .SsFmin = 0x%04x\n"
2575 " .Padding_16 = 0x%04x\n",
2576 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2577 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2578 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2579 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2580 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2581 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2582 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2583 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2584 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2585 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2586 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2587
2588 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2589 " .VoltageMode = 0x%02x\n"
2590 " .SnapToDiscrete = 0x%02x\n"
2591 " .NumDiscreteLevels = 0x%02x\n"
2592 " .padding = 0x%02x\n"
2593 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2594 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2595 " .SsFmin = 0x%04x\n"
2596 " .Padding_16 = 0x%04x\n",
2597 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2598 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2599 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2600 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2601 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2602 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2603 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2604 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2605 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2606 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2607 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2608
2609 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2610 " .VoltageMode = 0x%02x\n"
2611 " .SnapToDiscrete = 0x%02x\n"
2612 " .NumDiscreteLevels = 0x%02x\n"
2613 " .padding = 0x%02x\n"
2614 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2615 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2616 " .SsFmin = 0x%04x\n"
2617 " .Padding_16 = 0x%04x\n",
2618 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2619 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2620 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2621 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2622 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2623 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2624 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2625 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2626 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2627 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2628 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2629
2630 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2631 " .VoltageMode = 0x%02x\n"
2632 " .SnapToDiscrete = 0x%02x\n"
2633 " .NumDiscreteLevels = 0x%02x\n"
2634 " .padding = 0x%02x\n"
2635 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2636 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2637 " .SsFmin = 0x%04x\n"
2638 " .Padding_16 = 0x%04x\n",
2639 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2640 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2641 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2642 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2643 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2644 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2645 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2646 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2647 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2648 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2649 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2650
2651 dev_info(smu->adev->dev, "FreqTableGfx\n");
2652 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2653 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2654
2655 dev_info(smu->adev->dev, "FreqTableVclk\n");
2656 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2657 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2658
2659 dev_info(smu->adev->dev, "FreqTableDclk\n");
2660 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2661 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2662
2663 dev_info(smu->adev->dev, "FreqTableSocclk\n");
2664 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2665 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2666
2667 dev_info(smu->adev->dev, "FreqTableUclk\n");
2668 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2669 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2670
2671 dev_info(smu->adev->dev, "FreqTableFclk\n");
2672 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2673 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2674
2675 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2676 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2677 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2678 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2679 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2680 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2681 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2682 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2683 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2684
2685 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2686 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2687 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2688
2689 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2690 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2691
2692 dev_info(smu->adev->dev, "Mp0clkFreq\n");
2693 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2694 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2695
2696 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2697 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2698 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2699
2700 dev_info(smu->adev->dev, "MemVddciVoltage\n");
2701 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2702 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2703
2704 dev_info(smu->adev->dev, "MemMvddVoltage\n");
2705 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2706 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2707
2708 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2709 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2710 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2711 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2712 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2713
2714 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2715
2716 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2717 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2718 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2719 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2720 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2721 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2722 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2723 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2724 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2725 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2726 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2727
2728 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2729 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2730 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2731 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2732 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2733 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2734
2735 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2736 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2737 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2738 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2739 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2740
2741 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2742 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2743 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2744
2745 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2746 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2747 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2748 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2749
2750 dev_info(smu->adev->dev, "UclkDpmPstates\n");
2751 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2752 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2753
2754 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2755 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2756 pptable->UclkDpmSrcFreqRange.Fmin);
2757 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2758 pptable->UclkDpmSrcFreqRange.Fmax);
2759 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2760 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2761 pptable->UclkDpmTargFreqRange.Fmin);
2762 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2763 pptable->UclkDpmTargFreqRange.Fmax);
2764 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2765 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2766
2767 dev_info(smu->adev->dev, "PcieGenSpeed\n");
2768 for (i = 0; i < NUM_LINK_LEVELS; i++)
2769 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2770
2771 dev_info(smu->adev->dev, "PcieLaneCount\n");
2772 for (i = 0; i < NUM_LINK_LEVELS; i++)
2773 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2774
2775 dev_info(smu->adev->dev, "LclkFreq\n");
2776 for (i = 0; i < NUM_LINK_LEVELS; i++)
2777 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2778
2779 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2780 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2781
2782 dev_info(smu->adev->dev, "FanGain\n");
2783 for (i = 0; i < TEMP_COUNT; i++)
2784 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2785
2786 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2787 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2788 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2789 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2790 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2791 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2792 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2793 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2794 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2795 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2796 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2797 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2798
2799 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2800 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2801 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2802 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2803
2804 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2805 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2806 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2807 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2808
2809 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2810 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2811 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2812 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2813 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2814 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2815 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2816 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2817 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2818 pptable->dBtcGbGfxPll.a,
2819 pptable->dBtcGbGfxPll.b,
2820 pptable->dBtcGbGfxPll.c);
2821 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2822 pptable->dBtcGbGfxDfll.a,
2823 pptable->dBtcGbGfxDfll.b,
2824 pptable->dBtcGbGfxDfll.c);
2825 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2826 pptable->dBtcGbSoc.a,
2827 pptable->dBtcGbSoc.b,
2828 pptable->dBtcGbSoc.c);
2829 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2830 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2831 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2832 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2833 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2834 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2835
2836 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2837 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2838 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
2839 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2840 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
2841 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2842 }
2843
2844 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2845 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2846 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2847 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2848 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2849 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2850 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2851 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2852
2853 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2854 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2855
2856 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2857 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2858 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2859 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2860
2861 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2862 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2863 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2864 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2865
2866 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2867 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2868
2869 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2870 for (i = 0; i < NUM_XGMI_LEVELS; i++)
2871 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2872 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2873 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2874
2875 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2876 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2877 pptable->ReservedEquation0.a,
2878 pptable->ReservedEquation0.b,
2879 pptable->ReservedEquation0.c);
2880 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2881 pptable->ReservedEquation1.a,
2882 pptable->ReservedEquation1.b,
2883 pptable->ReservedEquation1.c);
2884 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2885 pptable->ReservedEquation2.a,
2886 pptable->ReservedEquation2.b,
2887 pptable->ReservedEquation2.c);
2888 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2889 pptable->ReservedEquation3.a,
2890 pptable->ReservedEquation3.b,
2891 pptable->ReservedEquation3.c);
2892
2893 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2894 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2895 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2896 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2897 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2898 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2899 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2900 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2901
2902 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2903 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2904 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2905 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2906 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2907 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2908
2909 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2910 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2911 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
2912 pptable->I2cControllers[i].Enabled);
2913 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
2914 pptable->I2cControllers[i].Speed);
2915 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
2916 pptable->I2cControllers[i].SlaveAddress);
2917 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
2918 pptable->I2cControllers[i].ControllerPort);
2919 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
2920 pptable->I2cControllers[i].ControllerName);
2921 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
2922 pptable->I2cControllers[i].ThermalThrotter);
2923 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
2924 pptable->I2cControllers[i].I2cProtocol);
2925 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
2926 pptable->I2cControllers[i].PaddingConfig);
2927 }
2928
2929 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2930 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2931 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2932 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2933
2934 dev_info(smu->adev->dev, "Board Parameters:\n");
2935 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2936 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2937 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2938 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2939 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2940 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2941 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2942 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2943
2944 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2945 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2946 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2947
2948 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2949 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2950 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2951
2952 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2953 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2954 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2955
2956 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2957 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2958 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2959
2960 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2961
2962 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2963 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2964 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2965 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2966 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2967 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2968 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2969 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2970 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2971 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2972 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2973 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2974 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2975 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2976 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2977 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2978
2979 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2980 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2981 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
2982
2983 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2984 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2985 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
2986
2987 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
2988 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2989
2990 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2991 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2992 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2993
2994 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2995 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2996 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2997 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2998 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2999
3000 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3001 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3002
3003 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3004 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3005 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3006 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3007 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3008 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3009 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3010 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3011 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3012 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3013 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3014 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3015
3016 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3017 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3018 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3019 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3020
3021 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3022 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3023 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3024 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3025 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3026 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3027 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3028 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3029 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3030 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3031 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3032
3033 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3034 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3035 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3036 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3037 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3038 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3039 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3040 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3041}
3042
b455159c
LG		 3043static void sienna_cichlid_dump_pptable(struct smu_context *smu)
3044{
3045 struct smu_table_context *table_context = &smu->smu_table;
3046 PPTable_t *pptable = table_context->driver_pptable;
3047 int i;
3048
1d789535 3049 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) {
7077b19a
CG		 3050 beige_goby_dump_pptable(smu);
3051 return;
3052 }
3053
d9811cfc 3054 dev_info(smu->adev->dev, "Dumped PPTable:\n");
b455159c 3055
d9811cfc
EQ		 3056 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
3057 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
3058 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
b455159c
LG		 3059
3060 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
d9811cfc
EQ		 3061 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
3062 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
3063 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
3064 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
b455159c
LG		 3065 }
3066
3067 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
d9811cfc
EQ		 3068 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
3069 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
b455159c
LG		 3070 }
3071
3072 for (i = 0; i < TEMP_COUNT; i++) {
d9811cfc 3073 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
b455159c
LG		 3074 }
3075
d9811cfc
EQ		 3076 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
3077 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
3078 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
3079 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
3080 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
b455159c 3081
d9811cfc 3082 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
b455159c 3083 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
d9811cfc
EQ		 3084 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
3085 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
b455159c 3086 }
d9811cfc
EQ		 3087 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
3088
3089 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
3090
3091 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
3092 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
3093 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
3094 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
3095
3096 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
3097 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
3098
3099 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
3100 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
3101 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
3102 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
3103
3104 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
3105 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
3106 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
3107 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
3108
3109 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
3110 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
3111
3112 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
3113 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
3114 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
3115 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
3116 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
3117 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
3118 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
3119 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
3120
3121 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
b455159c
LG		 3122 " .VoltageMode = 0x%02x\n"
3123 " .SnapToDiscrete = 0x%02x\n"
3124 " .NumDiscreteLevels = 0x%02x\n"
3125 " .padding = 0x%02x\n"
3126 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3127 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3128 " .SsFmin = 0x%04x\n"
3129 " .Padding_16 = 0x%04x\n",
3130 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
3131 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
3132 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
3133 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
3134 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
3135 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
3136 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
3137 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
3138 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
3139 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
3140 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
3141
d9811cfc 3142 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
b455159c
LG		 3143 " .VoltageMode = 0x%02x\n"
3144 " .SnapToDiscrete = 0x%02x\n"
3145 " .NumDiscreteLevels = 0x%02x\n"
3146 " .padding = 0x%02x\n"
3147 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3148 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3149 " .SsFmin = 0x%04x\n"
3150 " .Padding_16 = 0x%04x\n",
3151 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
3152 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
3153 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
3154 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
3155 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
3156 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
3157 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
3158 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
3159 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
3160 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
3161 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
3162
d9811cfc 3163 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
b455159c
LG		 3164 " .VoltageMode = 0x%02x\n"
3165 " .SnapToDiscrete = 0x%02x\n"
3166 " .NumDiscreteLevels = 0x%02x\n"
3167 " .padding = 0x%02x\n"
3168 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3169 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3170 " .SsFmin = 0x%04x\n"
3171 " .Padding_16 = 0x%04x\n",
3172 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
3173 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
3174 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
3175 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
3176 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
3177 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
3178 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
3179 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
3180 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
3181 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
3182 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
3183
d9811cfc 3184 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
b455159c
LG		 3185 " .VoltageMode = 0x%02x\n"
3186 " .SnapToDiscrete = 0x%02x\n"
3187 " .NumDiscreteLevels = 0x%02x\n"
3188 " .padding = 0x%02x\n"
3189 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3190 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3191 " .SsFmin = 0x%04x\n"
3192 " .Padding_16 = 0x%04x\n",
3193 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
3194 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
3195 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
3196 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
3197 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
3198 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
3199 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
3200 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
3201 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
3202 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
3203 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
3204
d9811cfc 3205 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
b455159c
LG		 3206 " .VoltageMode = 0x%02x\n"
3207 " .SnapToDiscrete = 0x%02x\n"
3208 " .NumDiscreteLevels = 0x%02x\n"
3209 " .padding = 0x%02x\n"
3210 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3211 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3212 " .SsFmin = 0x%04x\n"
3213 " .Padding_16 = 0x%04x\n",
3214 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
3215 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
3216 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
3217 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
3218 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
3219 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
3220 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
3221 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
3222 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
3223 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
3224 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
3225
d9811cfc 3226 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
b455159c
LG		 3227 " .VoltageMode = 0x%02x\n"
3228 " .SnapToDiscrete = 0x%02x\n"
3229 " .NumDiscreteLevels = 0x%02x\n"
3230 " .padding = 0x%02x\n"
3231 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3232 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3233 " .SsFmin = 0x%04x\n"
3234 " .Padding_16 = 0x%04x\n",
3235 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
3236 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
3237 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
3238 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
3239 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
3240 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
3241 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
3242 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
3243 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
3244 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
3245 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
3246
d9811cfc 3247 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
b455159c
LG		 3248 " .VoltageMode = 0x%02x\n"
3249 " .SnapToDiscrete = 0x%02x\n"
3250 " .NumDiscreteLevels = 0x%02x\n"
3251 " .padding = 0x%02x\n"
3252 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3253 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3254 " .SsFmin = 0x%04x\n"
3255 " .Padding_16 = 0x%04x\n",
3256 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
3257 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
3258 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
3259 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
3260 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
3261 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
3262 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
3263 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
3264 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
3265 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
3266 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
3267
d9811cfc 3268 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
b455159c
LG		 3269 " .VoltageMode = 0x%02x\n"
3270 " .SnapToDiscrete = 0x%02x\n"
3271 " .NumDiscreteLevels = 0x%02x\n"
3272 " .padding = 0x%02x\n"
3273 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3274 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3275 " .SsFmin = 0x%04x\n"
3276 " .Padding_16 = 0x%04x\n",
3277 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
3278 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
3279 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
3280 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
3281 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
3282 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
3283 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
3284 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
3285 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
3286 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
3287 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
3288
d9811cfc 3289 dev_info(smu->adev->dev, "FreqTableGfx\n");
b455159c 3290 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
d9811cfc 3291 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
b455159c 3292
d9811cfc 3293 dev_info(smu->adev->dev, "FreqTableVclk\n");
b455159c 3294 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
d9811cfc 3295 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
b455159c 3296
d9811cfc 3297 dev_info(smu->adev->dev, "FreqTableDclk\n");
b455159c 3298 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
d9811cfc 3299 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
b455159c 3300
d9811cfc 3301 dev_info(smu->adev->dev, "FreqTableSocclk\n");
b455159c 3302 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
d9811cfc 3303 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
b455159c 3304
d9811cfc 3305 dev_info(smu->adev->dev, "FreqTableUclk\n");
b455159c 3306 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3307 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
b455159c 3308
d9811cfc 3309 dev_info(smu->adev->dev, "FreqTableFclk\n");
b455159c 3310 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
d9811cfc
EQ		 3311 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
3312
d9811cfc
EQ		 3313 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
3314 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
3315 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
3316 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
3317 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
3318 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
3319 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
3320 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
3321 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
3322
3323 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
b455159c 3324 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3325 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
b455159c 3326
d9811cfc
EQ		 3327 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
3328 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
b455159c 3329
d9811cfc 3330 dev_info(smu->adev->dev, "Mp0clkFreq\n");
b455159c 3331 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc 3332 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
b455159c 3333
d9811cfc 3334 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
b455159c 3335 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc 3336 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
b455159c 3337
d9811cfc 3338 dev_info(smu->adev->dev, "MemVddciVoltage\n");
b455159c 3339 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3340 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
b455159c 3341
d9811cfc 3342 dev_info(smu->adev->dev, "MemMvddVoltage\n");
b455159c 3343 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc
EQ		 3344 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
3345
3346 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
3347 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
3348 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
3349 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
3350 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
3351
3352 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
3353
3354 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
3355 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
3356 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
3357 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
3358 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
3359 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
3360 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
3361 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
3362 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
3363 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
3364 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
3365
3366 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
3367 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
3368 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
3369 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
3370 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
3371 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
3372
3373 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
3374 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
3375 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
3376 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
3377 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
3378
3379 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
b455159c 3380 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
d9811cfc 3381 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
b455159c 3382
d9811cfc
EQ		 3383 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
3384 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
3385 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
3386 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
b455159c 3387
d9811cfc 3388 dev_info(smu->adev->dev, "UclkDpmPstates\n");
b455159c 3389 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3390 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
b455159c 3391
d9811cfc
EQ		 3392 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
3393 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
b455159c 3394 pptable->UclkDpmSrcFreqRange.Fmin);
d9811cfc 3395 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
b455159c 3396 pptable->UclkDpmSrcFreqRange.Fmax);
d9811cfc
EQ		 3397 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
3398 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
b455159c 3399 pptable->UclkDpmTargFreqRange.Fmin);
d9811cfc 3400 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
b455159c 3401 pptable->UclkDpmTargFreqRange.Fmax);
d9811cfc
EQ		 3402 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
3403 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
b455159c 3404
d9811cfc 3405 dev_info(smu->adev->dev, "PcieGenSpeed\n");
b455159c 3406 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3407 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
b455159c 3408
d9811cfc 3409 dev_info(smu->adev->dev, "PcieLaneCount\n");
b455159c 3410 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3411 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
b455159c 3412
d9811cfc 3413 dev_info(smu->adev->dev, "LclkFreq\n");
b455159c 3414 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3415 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
b455159c 3416
d9811cfc
EQ		 3417 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
3418 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
b455159c 3419
d9811cfc 3420 dev_info(smu->adev->dev, "FanGain\n");
b455159c 3421 for (i = 0; i < TEMP_COUNT; i++)
d9811cfc
EQ		 3422 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
3423
3424 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
3425 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
3426 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
3427 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
3428 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
3429 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
3430 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
3431 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
3432 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
3433 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
3434 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
3435 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
3436
3437 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
3438 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
3439 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
3440 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
3441
3442 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
3443 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
3444 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
3445 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
3446
3447 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3448 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
3449 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
3450 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
d9811cfc 3451 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3452 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
3453 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
3454 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
d9811cfc 3455 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3456 pptable->dBtcGbGfxPll.a,
3457 pptable->dBtcGbGfxPll.b,
3458 pptable->dBtcGbGfxPll.c);
d9811cfc 3459 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3460 pptable->dBtcGbGfxDfll.a,
3461 pptable->dBtcGbGfxDfll.b,
3462 pptable->dBtcGbGfxDfll.c);
d9811cfc 3463 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3464 pptable->dBtcGbSoc.a,
3465 pptable->dBtcGbSoc.b,
3466 pptable->dBtcGbSoc.c);
d9811cfc 3467 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
b455159c
LG		 3468 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
3469 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
d9811cfc 3470 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
b455159c
LG		 3471 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
3472 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
3473
d9811cfc 3474 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
b455159c 3475 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
d9811cfc 3476 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
b455159c 3477 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
d9811cfc 3478 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
b455159c
LG		 3479 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
3480 }
3481
d9811cfc 3482 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3483 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
3484 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
3485 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
d9811cfc 3486 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3487 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
3488 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
3489 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
3490
d9811cfc
EQ		 3491 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
3492 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
b455159c 3493
d9811cfc
EQ		 3494 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
3495 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
3496 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
3497 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
b455159c 3498
d9811cfc
EQ		 3499 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
3500 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
3501 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
3502 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
b455159c 3503
d9811cfc
EQ		 3504 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
3505 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
b455159c 3506
d9811cfc 3507 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
b455159c 3508 for (i = 0; i < NUM_XGMI_LEVELS; i++)
d9811cfc
EQ		 3509 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
3510 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
3511 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
b455159c 3512
d9811cfc
EQ		 3513 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
3514 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3515 pptable->ReservedEquation0.a,
3516 pptable->ReservedEquation0.b,
3517 pptable->ReservedEquation0.c);
d9811cfc 3518 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3519 pptable->ReservedEquation1.a,
3520 pptable->ReservedEquation1.b,
3521 pptable->ReservedEquation1.c);
d9811cfc 3522 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3523 pptable->ReservedEquation2.a,
3524 pptable->ReservedEquation2.b,
3525 pptable->ReservedEquation2.c);
d9811cfc 3526 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3527 pptable->ReservedEquation3.a,
3528 pptable->ReservedEquation3.b,
3529 pptable->ReservedEquation3.c);
3530
d9811cfc
EQ		 3531 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3532 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3533 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3534 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3535 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3536 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3537 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3538 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
d9811cfc
EQ		 3539
3540 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3541 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3542 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3543 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3544 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3545 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
b455159c
LG		 3546
3547 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
d9811cfc
EQ		 3548 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3549 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
b455159c 3550 pptable->I2cControllers[i].Enabled);
d9811cfc 3551 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
b455159c 3552 pptable->I2cControllers[i].Speed);
d9811cfc 3553 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
b455159c 3554 pptable->I2cControllers[i].SlaveAddress);
d9811cfc 3555 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
b455159c 3556 pptable->I2cControllers[i].ControllerPort);
d9811cfc 3557 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
b455159c 3558 pptable->I2cControllers[i].ControllerName);
d9811cfc 3559 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
b455159c 3560 pptable->I2cControllers[i].ThermalThrotter);
d9811cfc 3561 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
b455159c 3562 pptable->I2cControllers[i].I2cProtocol);
d9811cfc 3563 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
b455159c
LG		 3564 pptable->I2cControllers[i].PaddingConfig);
3565 }
3566
d9811cfc
EQ		 3567 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3568 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3569 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3570 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3571
3572 dev_info(smu->adev->dev, "Board Parameters:\n");
3573 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3574 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3575 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3576 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3577 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3578 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3579 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3580 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3581
3582 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3583 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3584 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3585
3586 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3587 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3588 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3589
3590 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3591 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3592 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3593
3594 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3595 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3596 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3597
3598 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3599
3600 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3601 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3602 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3603 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3604 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3605 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3606 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3607 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3608 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3609 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3610 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3611 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3612 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3613 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3614 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3615 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3616
3617 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3618 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3619 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3620
3621 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3622 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3623 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3624
f0f3d68e 3625 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
d9811cfc
EQ		 3626 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3627
3628 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3629 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3630 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3631
3632 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3633 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3634 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3635 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3636 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3637
3638 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3639 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3640
3641 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
b455159c 3642 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3643 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3644 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
b455159c 3645 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3646 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3647 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
b455159c 3648 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3649 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3650 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
b455159c 3651 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3652 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3653
3654 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3655 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3656 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3657 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3658
3659 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3660 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3661 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3662 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3663 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3664 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3665 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3666 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3667 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3668 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3669 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
d9811cfc
EQ		 3670
3671 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3672 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3673 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3674 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3675 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3676 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3677 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3678 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
b455159c
LG		 3679}
3680
5125c96a 3681static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
ebe57d0c 3682 struct i2c_msg *msg, int num_msgs)
bc50ca29 3683{
2f60dd50
LT		 3684 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
3685 struct amdgpu_device *adev = smu_i2c->adev;
ebfc2533
EQ		 3686 struct smu_context *smu = adev->powerplay.pp_handle;
3687 struct smu_table_context *smu_table = &smu->smu_table;
bc50ca29 3688 struct smu_table *table = &smu_table->driver_table;
5125c96a 3689 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
ebe57d0c
LT		 3690 int i, j, r, c;
3691 u16 dir;
d74a09c8 3692
e281d594
AD		 3693 if (!adev->pm.dpm_enabled)
3694 return -EBUSY;
3695
5125c96a
AD		 3696 req = kzalloc(sizeof(*req), GFP_KERNEL);
3697 if (!req)
3698 return -ENOMEM;
bc50ca29 3699
2f60dd50 3700 req->I2CcontrollerPort = smu_i2c->port;
5125c96a 3701 req->I2CSpeed = I2C_SPEED_FAST_400K;
ebe57d0c
LT		 3702 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
3703 dir = msg[0].flags & I2C_M_RD;
bc50ca29 3704
ebe57d0c
LT		 3705 for (c = i = 0; i < num_msgs; i++) {
3706 for (j = 0; j < msg[i].len; j++, c++) {
3707 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
bc50ca29 3708
5125c96a
AD		 3709 if (!(msg[i].flags & I2C_M_RD)) {
3710 /* write */
3711 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
ebe57d0c
LT		 3712 cmd->ReadWriteData = msg[i].buf[j];
3713 }
3714
3715 if ((dir ^ msg[i].flags) & I2C_M_RD) {
3716 /* The direction changes.
3717 */
3718 dir = msg[i].flags & I2C_M_RD;
3719 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
5125c96a 3720 }
14df5650 3721
ebe57d0c
LT		 3722 req->NumCmds++;
3723
14df5650
AG		 3724 /*
3725 * Insert STOP if we are at the last byte of either last
3726 * message for the transaction or the client explicitly
3727 * requires a STOP at this particular message.
3728 */
ebe57d0c
LT		 3729 if ((j == msg[i].len - 1) &&
3730 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
3731 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
5125c96a 3732 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
ebe57d0c 3733 }
5125c96a 3734 }
d74a09c8 3735 }
e0638c7a 3736 mutex_lock(&adev->pm.mutex);
ebfc2533 3737 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
e0638c7a 3738 mutex_unlock(&adev->pm.mutex);
5125c96a
AD		 3739 if (r)
3740 goto fail;
bc50ca29 3741
ebe57d0c
LT		 3742 for (c = i = 0; i < num_msgs; i++) {
3743 if (!(msg[i].flags & I2C_M_RD)) {
3744 c += msg[i].len;
3745 continue;
3746 }
3747 for (j = 0; j < msg[i].len; j++, c++) {
3748 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
bc50ca29 3749
ebe57d0c 3750 msg[i].buf[j] = cmd->ReadWriteData;
bc50ca29
AD		 3751 }
3752 }
ebe57d0c 3753 r = num_msgs;
bc50ca29 3754fail:
5125c96a 3755 kfree(req);
5125c96a 3756 return r;
bc50ca29
AD		 3757}
3758
3759static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
3760{
3761 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3762}
3763
3764
3765static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
3766 .master_xfer = sienna_cichlid_i2c_xfer,
3767 .functionality = sienna_cichlid_i2c_func,
3768};
3769
35ed2703 3770static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = {
c0838d3a 3771 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
16736627 3772 .max_read_len = MAX_SW_I2C_COMMANDS,
35ed2703 3773 .max_write_len = MAX_SW_I2C_COMMANDS,
16736627
LT		 3774 .max_comb_1st_msg_len = 2,
3775 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
35ed2703
AG		 3776};
3777
2f60dd50 3778static int sienna_cichlid_i2c_control_init(struct smu_context *smu)
bc50ca29 3779{
2f60dd50
LT		 3780 struct amdgpu_device *adev = smu->adev;
3781 int res, i;
3782
3783 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3784 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3785 struct i2c_adapter *control = &smu_i2c->adapter;
3786
3787 smu_i2c->adev = adev;
3788 smu_i2c->port = i;
3789 mutex_init(&smu_i2c->mutex);
3790 control->owner = THIS_MODULE;
3791 control->class = I2C_CLASS_HWMON;
3792 control->dev.parent = &adev->pdev->dev;
3793 control->algo = &sienna_cichlid_i2c_algo;
3794 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
3795 control->quirks = &sienna_cichlid_i2c_control_quirks;
3796 i2c_set_adapdata(control, smu_i2c);
3797
3798 res = i2c_add_adapter(control);
3799 if (res) {
3800 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3801 goto Out_err;
3802 }
3803 }
3804 /* assign the buses used for the FRU EEPROM and RAS EEPROM */
3805 /* XXX ideally this would be something in a vbios data table */
3806 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
3807 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
bc50ca29 3808
2f60dd50
LT		 3809 return 0;
3810Out_err:
3811 for ( ; i >= 0; i--) {
3812 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3813 struct i2c_adapter *control = &smu_i2c->adapter;
bc50ca29 3814
2f60dd50
LT		 3815 i2c_del_adapter(control);
3816 }
bc50ca29
AD		 3817 return res;
3818}
3819
2f60dd50 3820static void sienna_cichlid_i2c_control_fini(struct smu_context *smu)
bc50ca29 3821{
2f60dd50
LT		 3822 struct amdgpu_device *adev = smu->adev;
3823 int i;
3824
3825 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3826 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3827 struct i2c_adapter *control = &smu_i2c->adapter;
3828
3829 i2c_del_adapter(control);
3830 }
3831 adev->pm.ras_eeprom_i2c_bus = NULL;
3832 adev->pm.fru_eeprom_i2c_bus = NULL;
bc50ca29
AD		 3833}
3834
8ca78a0a
EQ		 3835static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
3836 void **table)
3837{
3838 struct smu_table_context *smu_table = &smu->smu_table;
f06d9511
GS		 3839 struct gpu_metrics_v1_3 *gpu_metrics =
3840 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
b4b0b79d
EQ		 3841 SmuMetricsExternal_t metrics_external;
3842 SmuMetrics_t *metrics =
3843 &(metrics_external.SmuMetrics);
be22e2b9
EQ		 3844 SmuMetrics_V2_t *metrics_v2 =
3845 &(metrics_external.SmuMetrics_V2);
7952fa0d
DS		 3846 SmuMetrics_V3_t *metrics_v3 =
3847 &(metrics_external.SmuMetrics_V3);
c524c1c9 3848 struct amdgpu_device *adev = smu->adev;
7952fa0d
DS		 3849 bool use_metrics_v2 = false;
3850 bool use_metrics_v3 = false;
be22e2b9 3851 uint16_t average_gfx_activity;
8ca78a0a
EQ		 3852 int ret = 0;
3853
396beb91
EQ		 3854 switch (smu->adev->ip_versions[MP1_HWIP][0]) {
3855 case IP_VERSION(11, 0, 7):
3856 if (smu->smc_fw_version >= 0x3A4900)
3857 use_metrics_v3 = true;
3858 else if (smu->smc_fw_version >= 0x3A4300)
3859 use_metrics_v2 = true;
3860 break;
3861 case IP_VERSION(11, 0, 11):
3862 if (smu->smc_fw_version >= 0x412D00)
3863 use_metrics_v2 = true;
3864 break;
3865 case IP_VERSION(11, 0, 12):
3866 if (smu->smc_fw_version >= 0x3B2300)
3867 use_metrics_v2 = true;
3868 break;
3869 case IP_VERSION(11, 0, 13):
3870 if (smu->smc_fw_version >= 0x491100)
3871 use_metrics_v2 = true;
3872 break;
3873 default:
3874 break;
3875 }
7952fa0d 3876
da11407f
EQ		 3877 ret = smu_cmn_get_metrics_table(smu,
3878 &metrics_external,
3879 true);
3880 if (ret)
8ca78a0a 3881 return ret;
8ca78a0a 3882
f06d9511 3883 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
8ca78a0a 3884
7952fa0d 3885 gpu_metrics->temperature_edge = use_metrics_v3 ? metrics_v3->TemperatureEdge :
be22e2b9 3886 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge;
7952fa0d 3887 gpu_metrics->temperature_hotspot = use_metrics_v3 ? metrics_v3->TemperatureHotspot :
be22e2b9 3888 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot;
7952fa0d 3889 gpu_metrics->temperature_mem = use_metrics_v3 ? metrics_v3->TemperatureMem :
be22e2b9 3890 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem;
7952fa0d 3891 gpu_metrics->temperature_vrgfx = use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
be22e2b9 3892 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx;
7952fa0d 3893 gpu_metrics->temperature_vrsoc = use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
be22e2b9 3894 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc;
7952fa0d 3895 gpu_metrics->temperature_vrmem = use_metrics_v3 ? metrics_v3->TemperatureVrMem0 :
be22e2b9
EQ		 3896 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0;
3897
7952fa0d 3898 gpu_metrics->average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
be22e2b9 3899 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
7952fa0d 3900 gpu_metrics->average_umc_activity = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
be22e2b9 3901 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity;
7952fa0d
DS		 3902 gpu_metrics->average_mm_activity = use_metrics_v3 ?
3903 (metrics_v3->VcnUsagePercentage0 + metrics_v3->VcnUsagePercentage1) / 2 :
be22e2b9
EQ		 3904 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage;
3905
7952fa0d 3906 gpu_metrics->average_socket_power = use_metrics_v3 ? metrics_v3->AverageSocketPower :
be22e2b9 3907 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower;
7952fa0d 3908 gpu_metrics->energy_accumulator = use_metrics_v3 ? metrics_v3->EnergyAccumulator :
be22e2b9
EQ		 3909 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator;
3910
3a50403f
SK		 3911 if (metrics->CurrGfxVoltageOffset)
3912 gpu_metrics->voltage_gfx =
3913 (155000 - 625 * metrics->CurrGfxVoltageOffset) / 100;
3914 if (metrics->CurrMemVidOffset)
3915 gpu_metrics->voltage_mem =
3916 (155000 - 625 * metrics->CurrMemVidOffset) / 100;
3917 if (metrics->CurrSocVoltageOffset)
3918 gpu_metrics->voltage_soc =
3919 (155000 - 625 * metrics->CurrSocVoltageOffset) / 100;
3920
7952fa0d
DS		 3921 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
3922 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
be22e2b9
EQ		 3923 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
3924 gpu_metrics->average_gfxclk_frequency =
7952fa0d
DS		 3925 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
3926 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
3927 metrics->AverageGfxclkFrequencyPostDs;
8ca78a0a 3928 else
be22e2b9 3929 gpu_metrics->average_gfxclk_frequency =
7952fa0d
DS		 3930 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
3931 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
3932 metrics->AverageGfxclkFrequencyPreDs;
3933
be22e2b9 3934 gpu_metrics->average_uclk_frequency =
7952fa0d
DS		 3935 use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
3936 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
3937 metrics->AverageUclkFrequencyPostDs;
3938 gpu_metrics->average_vclk0_frequency = use_metrics_v3 ? metrics_v3->AverageVclk0Frequency :
be22e2b9 3939 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency;
7952fa0d 3940 gpu_metrics->average_dclk0_frequency = use_metrics_v3 ? metrics_v3->AverageDclk0Frequency :
be22e2b9 3941 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency;
7952fa0d 3942 gpu_metrics->average_vclk1_frequency = use_metrics_v3 ? metrics_v3->AverageVclk1Frequency :
be22e2b9 3943 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency;
7952fa0d 3944 gpu_metrics->average_dclk1_frequency = use_metrics_v3 ? metrics_v3->AverageDclk1Frequency :
be22e2b9
EQ		 3945 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency;
3946
7952fa0d 3947 gpu_metrics->current_gfxclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
be22e2b9 3948 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK];
7952fa0d 3949 gpu_metrics->current_socclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
be22e2b9 3950 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK];
7952fa0d 3951 gpu_metrics->current_uclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
be22e2b9 3952 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK];
7952fa0d 3953 gpu_metrics->current_vclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
be22e2b9 3954 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0];
7952fa0d 3955 gpu_metrics->current_dclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
be22e2b9 3956 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0];
7952fa0d 3957 gpu_metrics->current_vclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
be22e2b9 3958 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1];
7952fa0d 3959 gpu_metrics->current_dclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
be22e2b9
EQ		 3960 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1];
3961
3962 gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu);
f06d9511 3963 gpu_metrics->indep_throttle_status =
be22e2b9 3964 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
f06d9511 3965 sienna_cichlid_throttler_map);
b4b0b79d 3966
7952fa0d
DS		 3967 gpu_metrics->current_fan_speed = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
3968 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
c524c1c9 3969
1d789535
AD		 3970 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) ||
3971 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) {
7952fa0d
DS		 3972 gpu_metrics->pcie_link_width = use_metrics_v3 ? metrics_v3->PcieWidth :
3973 use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
3974 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v3 ? metrics_v3->PcieRate :
3975 use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
c524c1c9
EQ		 3976 } else {
3977 gpu_metrics->pcie_link_width =
3978 smu_v11_0_get_current_pcie_link_width(smu);
3979 gpu_metrics->pcie_link_speed =
3980 smu_v11_0_get_current_pcie_link_speed(smu);
3981 }
8ca78a0a 3982
de4b7cd8
KW		 3983 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3984
8ca78a0a
EQ		 3985 *table = (void *)gpu_metrics;
3986
f06d9511 3987 return sizeof(struct gpu_metrics_v1_3);
8ca78a0a 3988}
bc50ca29 3989
3ddd0c90 3990static int sienna_cichlid_check_ecc_table_support(struct smu_context *smu)
3991{
3992 uint32_t if_version = 0xff, smu_version = 0xff;
3993 int ret = 0;
3994
3995 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
3996 if (ret)
3997 return -EOPNOTSUPP;
3998
3999 if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION)
4000 ret = -EOPNOTSUPP;
4001
4002 return ret;
4003}
4004
4005static ssize_t sienna_cichlid_get_ecc_info(struct smu_context *smu,
4006 void *table)
4007{
4008 struct smu_table_context *smu_table = &smu->smu_table;
4009 EccInfoTable_t *ecc_table = NULL;
4010 struct ecc_info_per_ch *ecc_info_per_channel = NULL;
4011 int i, ret = 0;
4012 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
4013
4014 ret = sienna_cichlid_check_ecc_table_support(smu);
4015 if (ret)
4016 return ret;
4017
4018 ret = smu_cmn_update_table(smu,
4019 SMU_TABLE_ECCINFO,
4020 0,
4021 smu_table->ecc_table,
4022 false);
4023 if (ret) {
4024 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n");
4025 return ret;
4026 }
4027
4028 ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
4029
4030 for (i = 0; i < SIENNA_CICHLID_UMC_CHANNEL_NUM; i++) {
4031 ecc_info_per_channel = &(eccinfo->ecc[i]);
4032 ecc_info_per_channel->ce_count_lo_chip =
4033 ecc_table->EccInfo[i].ce_count_lo_chip;
4034 ecc_info_per_channel->ce_count_hi_chip =
4035 ecc_table->EccInfo[i].ce_count_hi_chip;
4036 ecc_info_per_channel->mca_umc_status =
4037 ecc_table->EccInfo[i].mca_umc_status;
4038 ecc_info_per_channel->mca_umc_addr =
4039 ecc_table->EccInfo[i].mca_umc_addr;
4040 }
4041
4042 return ret;
4043}
05f39286
EQ		 4044static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
4045{
f4e2a66d 4046 uint16_t *mgpu_fan_boost_limit_rpm;
b804a75d 4047
f4e2a66d 4048 GET_PPTABLE_MEMBER(MGpuFanBoostLimitRpm, &mgpu_fan_boost_limit_rpm);
b804a75d
EQ		 4049 /*
4050 * Skip the MGpuFanBoost setting for those ASICs
4051 * which do not support it
4052 */
f4e2a66d 4053 if (*mgpu_fan_boost_limit_rpm == 0)
b804a75d
EQ		 4054 return 0;
4055
05f39286
EQ		 4056 return smu_cmn_send_smc_msg_with_param(smu,
4057 SMU_MSG_SetMGpuFanBoostLimitRpm,
4058 0,
4059 NULL);
4060}
4061
76c71f00
EQ		 4062static int sienna_cichlid_gpo_control(struct smu_context *smu,
4063 bool enablement)
4064{
ac7804bb 4065 uint32_t smu_version;
76c71f00
EQ		 4066 int ret = 0;
4067
ac7804bb 4068
7ade3ca9 4069 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
ac7804bb
EQ		 4070 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
4071 if (ret)
4072 return ret;
4073
4074 if (enablement) {
4075 if (smu_version < 0x003a2500) {
4076 ret = smu_cmn_send_smc_msg_with_param(smu,
4077 SMU_MSG_SetGpoFeaturePMask,
4078 GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
4079 NULL);
4080 } else {
4081 ret = smu_cmn_send_smc_msg_with_param(smu,
4082 SMU_MSG_DisallowGpo,
4083 0,
4084 NULL);
4085 }
4086 } else {
4087 if (smu_version < 0x003a2500) {
4088 ret = smu_cmn_send_smc_msg_with_param(smu,
4089 SMU_MSG_SetGpoFeaturePMask,
4090 0,
4091 NULL);
4092 } else {
4093 ret = smu_cmn_send_smc_msg_with_param(smu,
4094 SMU_MSG_DisallowGpo,
4095 1,
4096 NULL);
4097 }
4098 }
76c71f00
EQ		 4099 }
4100
4101 return ret;
4102}
d7f52e29
EQ		 4103
4104static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
4105{
4106 uint32_t smu_version;
4107 int ret = 0;
4108
4109 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
4110 if (ret)
4111 return ret;
4112
4113 /*
4114 * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
4115 * onwards PMFWs.
4116 */
4117 if (smu_version < 0x003A2D00)
4118 return 0;
4119
4120 return smu_cmn_send_smc_msg_with_param(smu,
4121 SMU_MSG_Enable2ndUSB20Port,
4122 smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
4123 1 : 0,
4124 NULL);
4125}
4126
4127static int sienna_cichlid_system_features_control(struct smu_context *smu,
4128 bool en)
4129{
4130 int ret = 0;
4131
4132 if (en) {
4133 ret = sienna_cichlid_notify_2nd_usb20_port(smu);
4134 if (ret)
4135 return ret;
4136 }
4137
4138 return smu_v11_0_system_features_control(smu, en);
4139}
4140
1689fca0
EQ		 4141static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
4142 enum pp_mp1_state mp1_state)
4143{
9113a0fb
GC		 4144 int ret;
4145
1689fca0
EQ		 4146 switch (mp1_state) {
4147 case PP_MP1_STATE_UNLOAD:
9113a0fb
GC		 4148 ret = smu_cmn_set_mp1_state(smu, mp1_state);
4149 break;
1689fca0 4150 default:
9113a0fb
GC		 4151 /* Ignore others */
4152 ret = 0;
1689fca0
EQ		 4153 }
4154
9113a0fb 4155 return ret;
1689fca0
EQ		 4156}
4157
db5b5c67
AG		 4158static void sienna_cichlid_stb_init(struct smu_context *smu)
4159{
4160 struct amdgpu_device *adev = smu->adev;
4161 uint32_t reg;
4162
4163 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START);
4164 smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE);
4165
4166 /* STB is disabled */
4167 if (!smu->stb_context.enabled)
4168 return;
4169
4170 spin_lock_init(&smu->stb_context.lock);
4171
4172 /* STB buffer size in bytes as function of FIFO depth */
4173 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO);
4174 smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH);
4175 smu->stb_context.stb_buf_size *= SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES;
4176
4177 dev_info(smu->adev->dev, "STB initialized to %d entries",
4178 smu->stb_context.stb_buf_size / SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES);
4179
4180}
4181
c85bf88b
EQ		 4182static int sienna_cichlid_get_default_config_table_settings(struct smu_context *smu,
4183 struct config_table_setting *table)
4184{
4185 struct amdgpu_device *adev = smu->adev;
4186
4187 if (!table)
4188 return -EINVAL;
4189
4190 table->gfxclk_average_tau = 10;
4191 table->socclk_average_tau = 10;
4192 table->fclk_average_tau = 10;
4193 table->uclk_average_tau = 10;
4194 table->gfx_activity_average_tau = 10;
4195 table->mem_activity_average_tau = 10;
4196 table->socket_power_average_tau = 100;
ab9d97d6 4197 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7))
c85bf88b
EQ		 4198 table->apu_socket_power_average_tau = 100;
4199
4200 return 0;
4201}
4202
4203static int sienna_cichlid_set_config_table(struct smu_context *smu,
4204 struct config_table_setting *table)
4205{
4206 DriverSmuConfigExternal_t driver_smu_config_table;
4207
4208 if (!table)
4209 return -EINVAL;
4210
4211 memset(&driver_smu_config_table,
4212 0,
4213 sizeof(driver_smu_config_table));
4214 driver_smu_config_table.DriverSmuConfig.GfxclkAverageLpfTau =
4215 table->gfxclk_average_tau;
4216 driver_smu_config_table.DriverSmuConfig.FclkAverageLpfTau =
4217 table->fclk_average_tau;
4218 driver_smu_config_table.DriverSmuConfig.UclkAverageLpfTau =
4219 table->uclk_average_tau;
4220 driver_smu_config_table.DriverSmuConfig.GfxActivityLpfTau =
4221 table->gfx_activity_average_tau;
4222 driver_smu_config_table.DriverSmuConfig.UclkActivityLpfTau =
4223 table->mem_activity_average_tau;
4224 driver_smu_config_table.DriverSmuConfig.SocketPowerLpfTau =
4225 table->socket_power_average_tau;
4226
4227 return smu_cmn_update_table(smu,
4228 SMU_TABLE_DRIVER_SMU_CONFIG,
4229 0,
4230 (void *)&driver_smu_config_table,
4231 true);
4232}
4233
6a8cf634
AD		 4234static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu,
4235 void *buf,
4236 uint32_t size)
db5b5c67
AG		 4237{
4238 uint32_t *p = buf;
4239 struct amdgpu_device *adev = smu->adev;
4240
4241 /* No need to disable interrupts for now as we don't lock it yet from ISR */
4242 spin_lock(&smu->stb_context.lock);
4243
4244 /*
4245 * Read the STB FIFO in units of 32bit since this is the accessor window
4246 * (register width) we have.
4247 */
4248 buf = ((char *) buf) + size;
4249 while ((void *)p < buf)
4250 *p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3));
4251
4252 spin_unlock(&smu->stb_context.lock);
4253
4254 return 0;
4255}
4256
b455159c 4257static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
b455159c
LG		 4258 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
4259 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
f6b4b4a1 4260 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
6fb176a7 4261 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
bc50ca29
AD		 4262 .i2c_init = sienna_cichlid_i2c_control_init,
4263 .i2c_fini = sienna_cichlid_i2c_control_fini,
b455159c
LG		 4264 .print_clk_levels = sienna_cichlid_print_clk_levels,
4265 .force_clk_levels = sienna_cichlid_force_clk_levels,
4266 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
b455159c
LG		 4267 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
4268 .display_config_changed = sienna_cichlid_display_config_changed,
4269 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
b455159c 4270 .is_dpm_running = sienna_cichlid_is_dpm_running,
0d8318e1 4271 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
d9ca7567 4272 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
b455159c
LG		 4273 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
4274 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
b455159c
LG		 4275 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
4276 .read_sensor = sienna_cichlid_read_sensor,
4277 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
b2785e25 4278 .set_performance_level = smu_v11_0_set_performance_level,
b455159c
LG		 4279 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
4280 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
4281 .get_power_limit = sienna_cichlid_get_power_limit,
08ccfe08 4282 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
b455159c
LG		 4283 .dump_pptable = sienna_cichlid_dump_pptable,
4284 .init_microcode = smu_v11_0_init_microcode,
4285 .load_microcode = smu_v11_0_load_microcode,
c1b353b7 4286 .init_smc_tables = sienna_cichlid_init_smc_tables,
b455159c
LG		 4287 .fini_smc_tables = smu_v11_0_fini_smc_tables,
4288 .init_power = smu_v11_0_init_power,
4289 .fini_power = smu_v11_0_fini_power,
4290 .check_fw_status = smu_v11_0_check_fw_status,
4a13b4ce 4291 .setup_pptable = sienna_cichlid_setup_pptable,
b455159c 4292 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
b455159c 4293 .check_fw_version = smu_v11_0_check_fw_version,
caad2613 4294 .write_pptable = smu_cmn_write_pptable,
b455159c
LG		 4295 .set_driver_table_location = smu_v11_0_set_driver_table_location,
4296 .set_tool_table_location = smu_v11_0_set_tool_table_location,
4297 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
d7f52e29 4298 .system_features_control = sienna_cichlid_system_features_control,
66c86828
EQ		 4299 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
4300 .send_smc_msg = smu_cmn_send_smc_msg,
31157341 4301 .init_display_count = NULL,
b455159c 4302 .set_allowed_mask = smu_v11_0_set_allowed_mask,
28251d72 4303 .get_enabled_mask = smu_cmn_get_enabled_mask,
b4bb3aaf 4304 .feature_is_enabled = smu_cmn_feature_is_enabled,
af5ba6d2 4305 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
31157341 4306 .notify_display_change = NULL,
b455159c 4307 .set_power_limit = smu_v11_0_set_power_limit,
b455159c
LG		 4308 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
4309 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
4310 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
ce63d8f8 4311 .set_min_dcef_deep_sleep = NULL,
b455159c
LG		 4312 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
4313 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
4314 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
0d8318e1 4315 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
f3289d04 4316 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
b455159c
LG		 4317 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
4318 .gfx_off_control = smu_v11_0_gfx_off_control,
4319 .register_irq_handler = smu_v11_0_register_irq_handler,
4320 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
4321 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
9fd4781b 4322 .baco_is_support = smu_v11_0_baco_is_support,
b455159c
LG		 4323 .baco_get_state = smu_v11_0_baco_get_state,
4324 .baco_set_state = smu_v11_0_baco_set_state,
13d75ead
EQ		 4325 .baco_enter = sienna_cichlid_baco_enter,
4326 .baco_exit = sienna_cichlid_baco_exit,
ea8139d8
WS		 4327 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
4328 .mode1_reset = smu_v11_0_mode1_reset,
258d290c 4329 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
10e96d89 4330 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
aa75fa34 4331 .set_default_od_settings = sienna_cichlid_set_default_od_settings,
37a58f69 4332 .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
b521be9b 4333 .restore_user_od_settings = smu_v11_0_restore_user_od_settings,
66b8a9c0 4334 .run_btc = sienna_cichlid_run_btc,
18a4b3de 4335 .set_power_source = smu_v11_0_set_power_source,
7dbf7805
EQ		 4336 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
4337 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
8ca78a0a 4338 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
05f39286 4339 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
e988026f 4340 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
5ce99853 4341 .deep_sleep_control = smu_v11_0_deep_sleep_control,
3204ff3e 4342 .get_fan_parameters = sienna_cichlid_get_fan_parameters,
234676d6 4343 .interrupt_work = smu_v11_0_interrupt_work,
76c71f00 4344 .gpo_control = sienna_cichlid_gpo_control,
1689fca0 4345 .set_mp1_state = sienna_cichlid_set_mp1_state,
db5b5c67 4346 .stb_collect_info = sienna_cichlid_stb_get_data_direct,
3ddd0c90 4347 .get_ecc_info = sienna_cichlid_get_ecc_info,
c85bf88b
EQ		 4348 .get_default_config_table_settings = sienna_cichlid_get_default_config_table_settings,
4349 .set_config_table = sienna_cichlid_set_config_table,
ebd9c071 4350 .get_unique_id = sienna_cichlid_get_unique_id,
b455159c
LG		 4351};
4352
4353void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
4354{
4355 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
6c339f37
EQ		 4356 smu->message_map = sienna_cichlid_message_map;
4357 smu->clock_map = sienna_cichlid_clk_map;
4358 smu->feature_map = sienna_cichlid_feature_mask_map;
4359 smu->table_map = sienna_cichlid_table_map;
4360 smu->pwr_src_map = sienna_cichlid_pwr_src_map;
4361 smu->workload_map = sienna_cichlid_workload_map;
da1db031 4362 smu_v11_0_set_smu_mailbox_registers(smu);
b455159c 4363}
Linux 6.x block layer and io_uring tree(s)