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drm/amdgpu: EEPROM: add explicit read and write
[linux-block.git] / drivers / gpu / drm / amd / pm / swsmu / smu11 / sienna_cichlid_ppt.c
CommitLineData
b455159c
LG		 1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
d8e0b16d
EQ		 24#define SWSMU_CODE_LAYER_L2
25
b455159c
LG		 26#include <linux/firmware.h>
27#include <linux/pci.h>
bc50ca29 28#include <linux/i2c.h>
b455159c
LG		 29#include "amdgpu.h"
30#include "amdgpu_smu.h"
b455159c
LG		 31#include "atomfirmware.h"
32#include "amdgpu_atomfirmware.h"
22f2447c 33#include "amdgpu_atombios.h"
b455159c
LG		 34#include "smu_v11_0.h"
35#include "smu11_driver_if_sienna_cichlid.h"
36#include "soc15_common.h"
37#include "atom.h"
38#include "sienna_cichlid_ppt.h"
e05acd78 39#include "smu_v11_0_7_pptable.h"
b455159c 40#include "smu_v11_0_7_ppsmc.h"
40d3b8db 41#include "nbio/nbio_2_3_offset.h"
b7d25b5f 42#include "nbio/nbio_2_3_sh_mask.h"
e05acd78
LG		 43#include "thm/thm_11_0_2_offset.h"
44#include "thm/thm_11_0_2_sh_mask.h"
ea8139d8
WS		 45#include "mp/mp_11_0_offset.h"
46#include "mp/mp_11_0_sh_mask.h"
b455159c 47
6c339f37
EQ		 48#include "asic_reg/mp/mp_11_0_sh_mask.h"
49#include "smu_cmn.h"
50
55084d7f
EQ		 51/*
52 * DO NOT use these for err/warn/info/debug messages.
53 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
54 * They are more MGPU friendly.
55 */
56#undef pr_err
57#undef pr_warn
58#undef pr_info
59#undef pr_debug
60
bc50ca29
AD		 61#define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
62
b455159c
LG		 63#define FEATURE_MASK(feature) (1ULL << feature)
64#define SMC_DPM_FEATURE ( \
65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
fea905d4 66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65297d50 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
5cb74353 68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
4cd4f45b 69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
5f338f70 70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
ce7e5a6e
JC		 71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \
72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
b455159c 73
d817f375
LG		 74#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
75
7077b19a
CG		 76#define GET_PPTABLE_MEMBER(field, member) do {\
77 if (smu->adev->asic_type == CHIP_BEIGE_GOBY)\
78 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
79 else\
80 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
81} while(0)
82
83static int get_table_size(struct smu_context *smu)
84{
85 if (smu->adev->asic_type == CHIP_BEIGE_GOBY)
86 return sizeof(PPTable_beige_goby_t);
87 else
88 return sizeof(PPTable_t);
89}
90
6c339f37
EQ		 91static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
92 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
93 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
94 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
91190db1
LG		 95 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
96 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
97 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
98 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
6c339f37
EQ		 99 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
100 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
101 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
102 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
103 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
104 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
105 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
91190db1 106 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
4215a119
HC		 107 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
108 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
91190db1
LG		 109 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
110 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
4215a119 111 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
91190db1
LG		 112 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
113 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
66b8a9c0 114 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
91190db1 115 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
4215a119
HC		 116 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
117 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
6c339f37 118 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
91190db1 119 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
6c339f37
EQ		 120 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
121 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
122 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
91190db1
LG		 123 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
124 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
125 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
126 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
127 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
128 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
129 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
130 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
6c339f37 131 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
91190db1
LG		 132 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
133 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
134 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
6c339f37 135 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
91190db1
LG		 136 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
137 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
138 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
139 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
140 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
141 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
142 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
143 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
05f39286 144 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
76c71f00 145 MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0),
ac7804bb 146 MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0),
88dfd5d5 147 MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0),
b455159c
LG		 148};
149
6c339f37 150static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
b455159c
LG		 151 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
152 CLK_MAP(SCLK, PPCLK_GFXCLK),
153 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
154 CLK_MAP(FCLK, PPCLK_FCLK),
155 CLK_MAP(UCLK, PPCLK_UCLK),
156 CLK_MAP(MCLK, PPCLK_UCLK),
157 CLK_MAP(DCLK, PPCLK_DCLK_0),
9c0551f2
JC		 158 CLK_MAP(DCLK1, PPCLK_DCLK_1),
159 CLK_MAP(VCLK, PPCLK_VCLK_0),
b455159c
LG		 160 CLK_MAP(VCLK1, PPCLK_VCLK_1),
161 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
162 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
163 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
164 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
165};
166
6c339f37 167static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
b455159c
LG		 168 FEA_MAP(DPM_PREFETCHER),
169 FEA_MAP(DPM_GFXCLK),
31cb0dd9 170 FEA_MAP(DPM_GFX_GPO),
b455159c 171 FEA_MAP(DPM_UCLK),
e9073b43 172 FEA_MAP(DPM_FCLK),
b455159c
LG		 173 FEA_MAP(DPM_SOCCLK),
174 FEA_MAP(DPM_MP0CLK),
175 FEA_MAP(DPM_LINK),
176 FEA_MAP(DPM_DCEFCLK),
e9073b43 177 FEA_MAP(DPM_XGMI),
b455159c
LG		 178 FEA_MAP(MEM_VDDCI_SCALING),
179 FEA_MAP(MEM_MVDD_SCALING),
180 FEA_MAP(DS_GFXCLK),
181 FEA_MAP(DS_SOCCLK),
e9073b43 182 FEA_MAP(DS_FCLK),
b455159c
LG		 183 FEA_MAP(DS_LCLK),
184 FEA_MAP(DS_DCEFCLK),
185 FEA_MAP(DS_UCLK),
186 FEA_MAP(GFX_ULV),
187 FEA_MAP(FW_DSTATE),
188 FEA_MAP(GFXOFF),
189 FEA_MAP(BACO),
6fb176a7 190 FEA_MAP(MM_DPM_PG),
b455159c
LG		 191 FEA_MAP(RSMU_SMN_CG),
192 FEA_MAP(PPT),
193 FEA_MAP(TDC),
194 FEA_MAP(APCC_PLUS),
195 FEA_MAP(GTHR),
196 FEA_MAP(ACDC),
197 FEA_MAP(VR0HOT),
198 FEA_MAP(VR1HOT),
199 FEA_MAP(FW_CTF),
200 FEA_MAP(FAN_CONTROL),
201 FEA_MAP(THERMAL),
202 FEA_MAP(GFX_DCS),
203 FEA_MAP(RM),
204 FEA_MAP(LED_DISPLAY),
205 FEA_MAP(GFX_SS),
206 FEA_MAP(OUT_OF_BAND_MONITOR),
207 FEA_MAP(TEMP_DEPENDENT_VMIN),
208 FEA_MAP(MMHUB_PG),
209 FEA_MAP(ATHUB_PG),
cf06331f 210 FEA_MAP(APCC_DFLL),
b455159c
LG		 211};
212
6c339f37 213static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
b455159c
LG		 214 TAB_MAP(PPTABLE),
215 TAB_MAP(WATERMARKS),
216 TAB_MAP(AVFS_PSM_DEBUG),
217 TAB_MAP(AVFS_FUSE_OVERRIDE),
218 TAB_MAP(PMSTATUSLOG),
219 TAB_MAP(SMU_METRICS),
220 TAB_MAP(DRIVER_SMU_CONFIG),
221 TAB_MAP(ACTIVITY_MONITOR_COEFF),
222 TAB_MAP(OVERDRIVE),
223 TAB_MAP(I2C_COMMANDS),
224 TAB_MAP(PACE),
225};
226
6c339f37 227static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
1d5ca713
LG		 228 PWR_MAP(AC),
229 PWR_MAP(DC),
230};
231
6c339f37 232static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
b455159c
LG		 233 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
234 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
235 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
236 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
237 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
4c4d5a49 238 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
b455159c
LG		 239 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
240};
241
f06d9511
GS		 242static const uint8_t sienna_cichlid_throttler_map[] = {
243 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
244 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
245 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
246 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
247 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
248 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
249 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
250 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
251 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
252 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
253 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
254 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
255 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
256 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
257 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
258 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
259 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
260 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
261};
262
b455159c
LG		 263static int
264sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
265 uint32_t *feature_mask, uint32_t num)
266{
fea905d4
LG		 267 struct amdgpu_device *adev = smu->adev;
268
b455159c
LG		 269 if (num > 2)
270 return -EINVAL;
271
272 memset(feature_mask, 0, sizeof(uint32_t) * num);
273
4cd4f45b 274 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
15dbe18f 275 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
ce7e5a6e 276 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
094cdf15 277 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
5f338f70 278 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
86a9eb3f 279 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
80c36f86 280 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
9aa60213
LG		 281 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
282 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
d28f4aa1 283 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
20d71dcc 284 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
d0d71970 285 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
886c8bc6
LG		 286 | FEATURE_MASK(FEATURE_PPT_BIT)
287 | FEATURE_MASK(FEATURE_TDC_BIT)
3fc006f5 288 | FEATURE_MASK(FEATURE_BACO_BIT)
cf06331f 289 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
35ed946c 290 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
1c58d429 291 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
b971df70
LG		 292 | FEATURE_MASK(FEATURE_THERMAL_BIT)
293 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
fea905d4 294
c96721eb 295 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
fea905d4 296 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
c96721eb
KF		 297 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
298 }
fea905d4 299
680602d6
KF		 300 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
301 (adev->asic_type > CHIP_SIENNA_CICHLID) &&
302 !(adev->flags & AMD_IS_APU))
303 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
304
65297d50 305 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
fc17cd3f
LG		 306 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
307 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
308 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
65297d50 309
5cb74353
LG		 310 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
312
5f338f70
LG		 313 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
315
fea905d4
LG		 316 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
b455159c 318
62c1ea6b
LG		 319 if (adev->pm.pp_feature & PP_ULV_MASK)
320 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
321
02bb391d
LG		 322 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
323 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
324
e0da123a
LG		 325 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
327
b794616d
KF		 328 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
329 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
330
846938c2
KF		 331 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
332 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
333
6fb176a7
LG		 334 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
335 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
336 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
337
62826b86
KF		 338 if (smu->dc_controlled_by_gpio)
339 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
340
0064b0ce 341 if (amdgpu_aspm)
6ef28889
KF		 342 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
343
b455159c
LG		 344 return 0;
345}
346
458020dd 347static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
b455159c 348{
4a13b4ce 349 struct smu_table_context *table_context = &smu->smu_table;
e05acd78 350 struct smu_11_0_7_powerplay_table *powerplay_table =
4a13b4ce
EQ		 351 table_context->power_play_table;
352 struct smu_baco_context *smu_baco = &smu->smu_baco;
458020dd
LL		 353 struct amdgpu_device *adev = smu->adev;
354 uint32_t val;
355
356 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO ||
357 powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO) {
358 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
359 smu_baco->platform_support =
360 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
361 false;
362 }
363}
364
365static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
366{
367 struct smu_table_context *table_context = &smu->smu_table;
368 struct smu_11_0_7_powerplay_table *powerplay_table =
369 table_context->power_play_table;
4a13b4ce 370
18a4b3de
EQ		 371 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
372 smu->dc_controlled_by_gpio = true;
373
458020dd 374 sienna_cichlid_check_bxco_support(smu);
4a13b4ce
EQ		 375
376 table_context->thermal_controller_type =
377 powerplay_table->thermal_controller_type;
378
aa75fa34
EQ		 379 /*
380 * Instead of having its own buffer space and get overdrive_table copied,
381 * smu->od_settings just points to the actual overdrive_table
382 */
383 smu->od_settings = &powerplay_table->overdrive_table;
384
b455159c
LG		 385 return 0;
386}
387
388static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
389{
dccc7c21
LG		 390 struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
391 int index, ret;
7077b19a 392 I2cControllerConfig_t *table_member;
dccc7c21
LG		 393
394 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
395 smc_dpm_info);
396
22f2447c 397 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
dccc7c21
LG		 398 (uint8_t **)&smc_dpm_table);
399 if (ret)
400 return ret;
7077b19a
CG		 401 GET_PPTABLE_MEMBER(I2cControllers, &table_member);
402 memcpy(table_member, smc_dpm_table->I2cControllers,
403 sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
969c8d16 404
b455159c
LG		 405 return 0;
406}
407
408static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
409{
b455159c 410 struct smu_table_context *table_context = &smu->smu_table;
e05acd78 411 struct smu_11_0_7_powerplay_table *powerplay_table =
4a13b4ce 412 table_context->power_play_table;
7077b19a 413 int table_size;
b455159c 414
7077b19a 415 table_size = get_table_size(smu);
b455159c 416 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
7077b19a 417 table_size);
b455159c 418
4a13b4ce
EQ		 419 return 0;
420}
b455159c 421
4a13b4ce
EQ		 422static int sienna_cichlid_setup_pptable(struct smu_context *smu)
423{
424 int ret = 0;
b455159c 425
4a13b4ce
EQ		 426 ret = smu_v11_0_setup_pptable(smu);
427 if (ret)
428 return ret;
429
430 ret = sienna_cichlid_store_powerplay_table(smu);
431 if (ret)
432 return ret;
433
434 ret = sienna_cichlid_append_powerplay_table(smu);
435 if (ret)
436 return ret;
437
438 ret = sienna_cichlid_check_powerplay_table(smu);
439 if (ret)
440 return ret;
441
442 return ret;
b455159c
LG		 443}
444
c1b353b7 445static int sienna_cichlid_tables_init(struct smu_context *smu)
b455159c
LG		 446{
447 struct smu_table_context *smu_table = &smu->smu_table;
c1b353b7 448 struct smu_table *tables = smu_table->tables;
7077b19a 449 int table_size;
b455159c 450
7077b19a
CG		 451 table_size = get_table_size(smu);
452 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
453 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c
LG		 454 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
455 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b4b0b79d 456 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
b455159c 457 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
bc50ca29
AD		 458 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
459 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
b455159c
LG		 460 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
461 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
462 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
463 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
464 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
f9e3fe46 465 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
b455159c
LG		 466 AMDGPU_GEM_DOMAIN_VRAM);
467
b4b0b79d 468 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
b455159c 469 if (!smu_table->metrics_table)
8ca78a0a 470 goto err0_out;
b455159c
LG		 471 smu_table->metrics_time = 0;
472
f06d9511 473 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
8ca78a0a
EQ		 474 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
475 if (!smu_table->gpu_metrics_table)
476 goto err1_out;
477
40d3b8db
LG		 478 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
479 if (!smu_table->watermarks_table)
8ca78a0a 480 goto err2_out;
40d3b8db 481
b455159c 482 return 0;
8ca78a0a
EQ		 483
484err2_out:
485 kfree(smu_table->gpu_metrics_table);
486err1_out:
487 kfree(smu_table->metrics_table);
488err0_out:
489 return -ENOMEM;
b455159c
LG		 490}
491
60ae4d67
EQ		 492static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
493 MetricsMember_t member,
494 uint32_t *value)
495{
496 struct smu_table_context *smu_table= &smu->smu_table;
b4b0b79d
EQ		 497 SmuMetrics_t *metrics =
498 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
60ae4d67
EQ		 499 int ret = 0;
500
501 mutex_lock(&smu->metrics_lock);
502
fceafc9b
EQ		 503 ret = smu_cmn_get_metrics_table_locked(smu,
504 NULL,
505 false);
60ae4d67
EQ		 506 if (ret) {
507 mutex_unlock(&smu->metrics_lock);
508 return ret;
509 }
510
8c686254
EQ		 511 switch (member) {
512 case METRICS_CURR_GFXCLK:
513 *value = metrics->CurrClock[PPCLK_GFXCLK];
514 break;
515 case METRICS_CURR_SOCCLK:
516 *value = metrics->CurrClock[PPCLK_SOCCLK];
517 break;
518 case METRICS_CURR_UCLK:
519 *value = metrics->CurrClock[PPCLK_UCLK];
520 break;
521 case METRICS_CURR_VCLK:
522 *value = metrics->CurrClock[PPCLK_VCLK_0];
523 break;
524 case METRICS_CURR_VCLK1:
525 *value = metrics->CurrClock[PPCLK_VCLK_1];
526 break;
527 case METRICS_CURR_DCLK:
528 *value = metrics->CurrClock[PPCLK_DCLK_0];
529 break;
530 case METRICS_CURR_DCLK1:
531 *value = metrics->CurrClock[PPCLK_DCLK_1];
532 break;
9d09fa6f
ND		 533 case METRICS_CURR_DCEFCLK:
534 *value = metrics->CurrClock[PPCLK_DCEFCLK];
535 break;
4e2b3e23
KF		 536 case METRICS_CURR_FCLK:
537 *value = metrics->CurrClock[PPCLK_FCLK];
538 break;
8c686254 539 case METRICS_AVERAGE_GFXCLK:
d817f375
LG		 540 if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
541 *value = metrics->AverageGfxclkFrequencyPostDs;
542 else
543 *value = metrics->AverageGfxclkFrequencyPreDs;
8c686254
EQ		 544 break;
545 case METRICS_AVERAGE_FCLK:
d817f375 546 *value = metrics->AverageFclkFrequencyPostDs;
8c686254
EQ		 547 break;
548 case METRICS_AVERAGE_UCLK:
d817f375 549 *value = metrics->AverageUclkFrequencyPostDs;
8c686254
EQ		 550 break;
551 case METRICS_AVERAGE_GFXACTIVITY:
552 *value = metrics->AverageGfxActivity;
553 break;
554 case METRICS_AVERAGE_MEMACTIVITY:
555 *value = metrics->AverageUclkActivity;
556 break;
557 case METRICS_AVERAGE_SOCKETPOWER:
558 *value = metrics->AverageSocketPower << 8;
559 break;
560 case METRICS_TEMPERATURE_EDGE:
561 *value = metrics->TemperatureEdge *
562 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
563 break;
564 case METRICS_TEMPERATURE_HOTSPOT:
565 *value = metrics->TemperatureHotspot *
566 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
567 break;
568 case METRICS_TEMPERATURE_MEM:
569 *value = metrics->TemperatureMem *
570 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
571 break;
572 case METRICS_TEMPERATURE_VRGFX:
573 *value = metrics->TemperatureVrGfx *
574 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
575 break;
576 case METRICS_TEMPERATURE_VRSOC:
577 *value = metrics->TemperatureVrSoc *
578 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
579 break;
580 case METRICS_THROTTLER_STATUS:
581 *value = metrics->ThrottlerStatus;
582 break;
583 case METRICS_CURR_FANSPEED:
584 *value = metrics->CurrFanSpeed;
585 break;
586 default:
587 *value = UINT_MAX;
588 break;
589 }
590
b455159c
LG		 591 mutex_unlock(&smu->metrics_lock);
592
593 return ret;
8c686254 594
b455159c
LG		 595}
596
597static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
598{
599 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
600
b455159c
LG		 601 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
602 GFP_KERNEL);
603 if (!smu_dpm->dpm_context)
604 return -ENOMEM;
605
606 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
607
608 return 0;
609}
610
c1b353b7
EQ		 611static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
612{
613 int ret = 0;
614
615 ret = sienna_cichlid_tables_init(smu);
616 if (ret)
617 return ret;
618
619 ret = sienna_cichlid_allocate_dpm_context(smu);
620 if (ret)
621 return ret;
622
623 return smu_v11_0_init_smc_tables(smu);
624}
625
b455159c
LG		 626static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
627{
90a89c31 628 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
90a89c31 629 struct smu_11_0_dpm_table *dpm_table;
85dec717 630 struct amdgpu_device *adev = smu->adev;
90a89c31 631 int ret = 0;
7077b19a 632 DpmDescriptor_t *table_member;
b455159c 633
90a89c31
EQ		 634 /* socclk dpm table setup */
635 dpm_table = &dpm_context->dpm_tables.soc_table;
7077b19a 636 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
b4bb3aaf 637 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
90a89c31
EQ		 638 ret = smu_v11_0_set_single_dpm_table(smu,
639 SMU_SOCCLK,
640 dpm_table);
641 if (ret)
642 return ret;
643 dpm_table->is_fine_grained =
7077b19a 644 !table_member[PPCLK_SOCCLK].SnapToDiscrete;
90a89c31
EQ		 645 } else {
646 dpm_table->count = 1;
647 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
648 dpm_table->dpm_levels[0].enabled = true;
649 dpm_table->min = dpm_table->dpm_levels[0].value;
650 dpm_table->max = dpm_table->dpm_levels[0].value;
651 }
b455159c 652
90a89c31
EQ		 653 /* gfxclk dpm table setup */
654 dpm_table = &dpm_context->dpm_tables.gfx_table;
b4bb3aaf 655 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
90a89c31
EQ		 656 ret = smu_v11_0_set_single_dpm_table(smu,
657 SMU_GFXCLK,
658 dpm_table);
659 if (ret)
660 return ret;
661 dpm_table->is_fine_grained =
7077b19a 662 !table_member[PPCLK_GFXCLK].SnapToDiscrete;
90a89c31
EQ		 663 } else {
664 dpm_table->count = 1;
665 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
666 dpm_table->dpm_levels[0].enabled = true;
667 dpm_table->min = dpm_table->dpm_levels[0].value;
668 dpm_table->max = dpm_table->dpm_levels[0].value;
669 }
b455159c 670
90a89c31
EQ		 671 /* uclk dpm table setup */
672 dpm_table = &dpm_context->dpm_tables.uclk_table;
b4bb3aaf 673 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
90a89c31
EQ		 674 ret = smu_v11_0_set_single_dpm_table(smu,
675 SMU_UCLK,
676 dpm_table);
677 if (ret)
678 return ret;
679 dpm_table->is_fine_grained =
7077b19a 680 !table_member[PPCLK_UCLK].SnapToDiscrete;
90a89c31
EQ		 681 } else {
682 dpm_table->count = 1;
683 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
684 dpm_table->dpm_levels[0].enabled = true;
685 dpm_table->min = dpm_table->dpm_levels[0].value;
686 dpm_table->max = dpm_table->dpm_levels[0].value;
687 }
b455159c 688
90a89c31
EQ		 689 /* fclk dpm table setup */
690 dpm_table = &dpm_context->dpm_tables.fclk_table;
b4bb3aaf 691 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
90a89c31
EQ		 692 ret = smu_v11_0_set_single_dpm_table(smu,
693 SMU_FCLK,
694 dpm_table);
695 if (ret)
696 return ret;
697 dpm_table->is_fine_grained =
7077b19a 698 !table_member[PPCLK_FCLK].SnapToDiscrete;
90a89c31
EQ		 699 } else {
700 dpm_table->count = 1;
701 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
702 dpm_table->dpm_levels[0].enabled = true;
703 dpm_table->min = dpm_table->dpm_levels[0].value;
704 dpm_table->max = dpm_table->dpm_levels[0].value;
705 }
b455159c 706
90a89c31
EQ		 707 /* vclk0 dpm table setup */
708 dpm_table = &dpm_context->dpm_tables.vclk_table;
b4bb3aaf 709 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
90a89c31
EQ		 710 ret = smu_v11_0_set_single_dpm_table(smu,
711 SMU_VCLK,
712 dpm_table);
713 if (ret)
714 return ret;
715 dpm_table->is_fine_grained =
7077b19a 716 !table_member[PPCLK_VCLK_0].SnapToDiscrete;
90a89c31
EQ		 717 } else {
718 dpm_table->count = 1;
719 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
720 dpm_table->dpm_levels[0].enabled = true;
721 dpm_table->min = dpm_table->dpm_levels[0].value;
722 dpm_table->max = dpm_table->dpm_levels[0].value;
723 }
b455159c 724
90a89c31 725 /* vclk1 dpm table setup */
85dec717
JC		 726 if (adev->vcn.num_vcn_inst > 1) {
727 dpm_table = &dpm_context->dpm_tables.vclk1_table;
728 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
729 ret = smu_v11_0_set_single_dpm_table(smu,
730 SMU_VCLK1,
731 dpm_table);
732 if (ret)
733 return ret;
734 dpm_table->is_fine_grained =
7077b19a 735 !table_member[PPCLK_VCLK_1].SnapToDiscrete;
85dec717
JC		 736 } else {
737 dpm_table->count = 1;
738 dpm_table->dpm_levels[0].value =
739 smu->smu_table.boot_values.vclk / 100;
740 dpm_table->dpm_levels[0].enabled = true;
741 dpm_table->min = dpm_table->dpm_levels[0].value;
742 dpm_table->max = dpm_table->dpm_levels[0].value;
743 }
90a89c31 744 }
b455159c 745
90a89c31
EQ		 746 /* dclk0 dpm table setup */
747 dpm_table = &dpm_context->dpm_tables.dclk_table;
b4bb3aaf 748 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
90a89c31
EQ		 749 ret = smu_v11_0_set_single_dpm_table(smu,
750 SMU_DCLK,
751 dpm_table);
752 if (ret)
753 return ret;
754 dpm_table->is_fine_grained =
7077b19a 755 !table_member[PPCLK_DCLK_0].SnapToDiscrete;
90a89c31
EQ		 756 } else {
757 dpm_table->count = 1;
758 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
759 dpm_table->dpm_levels[0].enabled = true;
760 dpm_table->min = dpm_table->dpm_levels[0].value;
761 dpm_table->max = dpm_table->dpm_levels[0].value;
762 }
763
764 /* dclk1 dpm table setup */
85dec717
JC		 765 if (adev->vcn.num_vcn_inst > 1) {
766 dpm_table = &dpm_context->dpm_tables.dclk1_table;
767 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
768 ret = smu_v11_0_set_single_dpm_table(smu,
769 SMU_DCLK1,
770 dpm_table);
771 if (ret)
772 return ret;
773 dpm_table->is_fine_grained =
7077b19a 774 !table_member[PPCLK_DCLK_1].SnapToDiscrete;
85dec717
JC		 775 } else {
776 dpm_table->count = 1;
777 dpm_table->dpm_levels[0].value =
778 smu->smu_table.boot_values.dclk / 100;
779 dpm_table->dpm_levels[0].enabled = true;
780 dpm_table->min = dpm_table->dpm_levels[0].value;
781 dpm_table->max = dpm_table->dpm_levels[0].value;
782 }
90a89c31
EQ		 783 }
784
785 /* dcefclk dpm table setup */
786 dpm_table = &dpm_context->dpm_tables.dcef_table;
b4bb3aaf 787 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 788 ret = smu_v11_0_set_single_dpm_table(smu,
789 SMU_DCEFCLK,
790 dpm_table);
791 if (ret)
792 return ret;
793 dpm_table->is_fine_grained =
7077b19a 794 !table_member[PPCLK_DCEFCLK].SnapToDiscrete;
90a89c31
EQ		 795 } else {
796 dpm_table->count = 1;
797 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
798 dpm_table->dpm_levels[0].enabled = true;
799 dpm_table->min = dpm_table->dpm_levels[0].value;
800 dpm_table->max = dpm_table->dpm_levels[0].value;
801 }
b455159c 802
90a89c31
EQ		 803 /* pixelclk dpm table setup */
804 dpm_table = &dpm_context->dpm_tables.pixel_table;
b4bb3aaf 805 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 806 ret = smu_v11_0_set_single_dpm_table(smu,
807 SMU_PIXCLK,
808 dpm_table);
809 if (ret)
810 return ret;
811 dpm_table->is_fine_grained =
7077b19a 812 !table_member[PPCLK_PIXCLK].SnapToDiscrete;
90a89c31
EQ		 813 } else {
814 dpm_table->count = 1;
815 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
816 dpm_table->dpm_levels[0].enabled = true;
817 dpm_table->min = dpm_table->dpm_levels[0].value;
818 dpm_table->max = dpm_table->dpm_levels[0].value;
819 }
b455159c 820
90a89c31
EQ		 821 /* displayclk dpm table setup */
822 dpm_table = &dpm_context->dpm_tables.display_table;
b4bb3aaf 823 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 824 ret = smu_v11_0_set_single_dpm_table(smu,
825 SMU_DISPCLK,
826 dpm_table);
827 if (ret)
828 return ret;
829 dpm_table->is_fine_grained =
7077b19a 830 !table_member[PPCLK_DISPCLK].SnapToDiscrete;
90a89c31
EQ		 831 } else {
832 dpm_table->count = 1;
833 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
834 dpm_table->dpm_levels[0].enabled = true;
835 dpm_table->min = dpm_table->dpm_levels[0].value;
836 dpm_table->max = dpm_table->dpm_levels[0].value;
837 }
b455159c 838
90a89c31
EQ		 839 /* phyclk dpm table setup */
840 dpm_table = &dpm_context->dpm_tables.phy_table;
b4bb3aaf 841 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
90a89c31
EQ		 842 ret = smu_v11_0_set_single_dpm_table(smu,
843 SMU_PHYCLK,
844 dpm_table);
845 if (ret)
846 return ret;
847 dpm_table->is_fine_grained =
7077b19a 848 !table_member[PPCLK_PHYCLK].SnapToDiscrete;
90a89c31
EQ		 849 } else {
850 dpm_table->count = 1;
851 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
852 dpm_table->dpm_levels[0].enabled = true;
853 dpm_table->min = dpm_table->dpm_levels[0].value;
854 dpm_table->max = dpm_table->dpm_levels[0].value;
855 }
b455159c
LG		 856
857 return 0;
858}
859
f6b4b4a1 860static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
b455159c 861{
d51dc613 862 struct amdgpu_device *adev = smu->adev;
b455159c
LG		 863 int ret = 0;
864
865 if (enable) {
866 /* vcn dpm on is a prerequisite for vcn power gate messages */
b4bb3aaf 867 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 868 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
6fb176a7
LG		 869 if (ret)
870 return ret;
6ec46653 871 if (adev->vcn.num_vcn_inst > 1) {
66c86828 872 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
d51dc613
JC		 873 0x10000, NULL);
874 if (ret)
875 return ret;
876 }
b455159c 877 }
b455159c 878 } else {
b4bb3aaf 879 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 880 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
6fb176a7
LG		 881 if (ret)
882 return ret;
6ec46653 883 if (adev->vcn.num_vcn_inst > 1) {
66c86828 884 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
d51dc613
JC		 885 0x10000, NULL);
886 if (ret)
887 return ret;
888 }
b455159c 889 }
b455159c
LG		 890 }
891
892 return ret;
893}
894
6fb176a7
LG		 895static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
896{
6fb176a7
LG		 897 int ret = 0;
898
899 if (enable) {
b4bb3aaf 900 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 901 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
6fb176a7
LG		 902 if (ret)
903 return ret;
6fb176a7 904 }
6fb176a7 905 } else {
b4bb3aaf 906 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
66c86828 907 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
6fb176a7
LG		 908 if (ret)
909 return ret;
6fb176a7 910 }
6fb176a7
LG		 911 }
912
913 return ret;
914}
915
b455159c
LG		 916static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
917 enum smu_clk_type clk_type,
918 uint32_t *value)
919{
8c686254
EQ		 920 MetricsMember_t member_type;
921 int clk_id = 0;
b455159c 922
6c339f37
EQ		 923 clk_id = smu_cmn_to_asic_specific_index(smu,
924 CMN2ASIC_MAPPING_CLK,
925 clk_type);
b455159c
LG		 926 if (clk_id < 0)
927 return clk_id;
928
8c686254
EQ		 929 switch (clk_id) {
930 case PPCLK_GFXCLK:
931 member_type = METRICS_CURR_GFXCLK;
932 break;
933 case PPCLK_UCLK:
934 member_type = METRICS_CURR_UCLK;
935 break;
936 case PPCLK_SOCCLK:
937 member_type = METRICS_CURR_SOCCLK;
938 break;
939 case PPCLK_FCLK:
940 member_type = METRICS_CURR_FCLK;
941 break;
942 case PPCLK_VCLK_0:
943 member_type = METRICS_CURR_VCLK;
944 break;
945 case PPCLK_VCLK_1:
946 member_type = METRICS_CURR_VCLK1;
947 break;
948 case PPCLK_DCLK_0:
949 member_type = METRICS_CURR_DCLK;
950 break;
951 case PPCLK_DCLK_1:
952 member_type = METRICS_CURR_DCLK1;
953 break;
954 case PPCLK_DCEFCLK:
955 member_type = METRICS_CURR_DCEFCLK;
956 break;
957 default:
958 return -EINVAL;
959 }
960
961 return sienna_cichlid_get_smu_metrics_data(smu,
962 member_type,
963 value);
b455159c 964
b455159c
LG		 965}
966
967static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
968{
b455159c 969 DpmDescriptor_t *dpm_desc = NULL;
7077b19a 970 DpmDescriptor_t *table_member;
b455159c
LG		 971 uint32_t clk_index = 0;
972
7077b19a 973 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
6c339f37
EQ		 974 clk_index = smu_cmn_to_asic_specific_index(smu,
975 CMN2ASIC_MAPPING_CLK,
976 clk_type);
7077b19a 977 dpm_desc = &table_member[clk_index];
b455159c
LG		 978
979 /* 0 - Fine grained DPM, 1 - Discrete DPM */
0ee56acc 980 return dpm_desc->SnapToDiscrete == 0;
b455159c
LG		 981}
982
37a58f69
EQ		 983static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
984 enum SMU_11_0_7_ODFEATURE_CAP cap)
985{
986 return od_table->cap[cap];
987}
988
989static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
990 enum SMU_11_0_7_ODSETTING_ID setting,
991 uint32_t *min, uint32_t *max)
992{
993 if (min)
994 *min = od_table->min[setting];
995 if (max)
996 *max = od_table->max[setting];
997}
998
b455159c
LG		 999static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
1000 enum smu_clk_type clk_type, char *buf)
1001{
b7d25b5f
LG		 1002 struct amdgpu_device *adev = smu->adev;
1003 struct smu_table_context *table_context = &smu->smu_table;
1004 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1005 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
7077b19a
CG		 1006 uint16_t *table_member;
1007
37a58f69
EQ		 1008 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
1009 OverDriveTable_t *od_table =
1010 (OverDriveTable_t *)table_context->overdrive_table;
b455159c
LG		 1011 int i, size = 0, ret = 0;
1012 uint32_t cur_value = 0, value = 0, count = 0;
1013 uint32_t freq_values[3] = {0};
1014 uint32_t mark_index = 0;
b7d25b5f 1015 uint32_t gen_speed, lane_width;
37a58f69 1016 uint32_t min_value, max_value;
a2b6df4f 1017 uint32_t smu_version;
b455159c
LG		 1018
1019 switch (clk_type) {
1020 case SMU_GFXCLK:
1021 case SMU_SCLK:
1022 case SMU_SOCCLK:
1023 case SMU_MCLK:
1024 case SMU_UCLK:
1025 case SMU_FCLK:
78842457
DN		 1026 case SMU_VCLK:
1027 case SMU_VCLK1:
1028 case SMU_DCLK:
1029 case SMU_DCLK1:
b455159c 1030 case SMU_DCEFCLK:
5e6dc8fe 1031 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
b455159c 1032 if (ret)
258d290c 1033 goto print_clk_out;
b455159c 1034
ba818620
KF		 1035 /* no need to disable gfxoff when retrieving the current gfxclk */
1036 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1037 amdgpu_gfx_off_ctrl(adev, false);
1038
d8d3493a 1039 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
b455159c 1040 if (ret)
258d290c 1041 goto print_clk_out;
b455159c
LG		 1042
1043 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1044 for (i = 0; i < count; i++) {
d8d3493a 1045 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
b455159c 1046 if (ret)
258d290c 1047 goto print_clk_out;
b455159c
LG		 1048
1049 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
1050 cur_value == value ? "*" : "");
1051 }
1052 } else {
d8d3493a 1053 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
b455159c 1054 if (ret)
258d290c 1055 goto print_clk_out;
d8d3493a 1056 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
b455159c 1057 if (ret)
258d290c 1058 goto print_clk_out;
b455159c
LG		 1059
1060 freq_values[1] = cur_value;
1061 mark_index = cur_value == freq_values[0] ? 0 :
1062 cur_value == freq_values[2] ? 2 : 1;
b455159c 1063
891bacb8
KF		 1064 count = 3;
1065 if (mark_index != 1) {
1066 count = 2;
1067 freq_values[1] = freq_values[2];
1068 }
1069
1070 for (i = 0; i < count; i++) {
b455159c 1071 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
891bacb8 1072 cur_value == freq_values[i] ? "*" : "");
b455159c
LG		 1073 }
1074
1075 }
1076 break;
b7d25b5f 1077 case SMU_PCIE:
f20c52f4
LG		 1078 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1079 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
7077b19a 1080 GET_PPTABLE_MEMBER(LclkFreq, &table_member);
b7d25b5f
LG		 1081 for (i = 0; i < NUM_LINK_LEVELS; i++)
1082 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
1083 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1084 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1085 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1086 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1087 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1088 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1089 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1090 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1091 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1092 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
7077b19a 1093 table_member[i],
b7d25b5f
LG		 1094 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1095 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1096 "*" : "");
1097 break;
37a58f69
EQ		 1098 case SMU_OD_SCLK:
1099 if (!smu->od_enabled || !od_table || !od_settings)
1100 break;
1101
1102 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1103 break;
1104
1105 size += sprintf(buf + size, "OD_SCLK:\n");
1106 size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1107 break;
1108
1109 case SMU_OD_MCLK:
1110 if (!smu->od_enabled || !od_table || !od_settings)
1111 break;
1112
1113 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1114 break;
1115
1116 size += sprintf(buf + size, "OD_MCLK:\n");
1117 size += sprintf(buf + size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
1118 break;
1119
a2b6df4f
EQ		 1120 case SMU_OD_VDDGFX_OFFSET:
1121 if (!smu->od_enabled || !od_table || !od_settings)
1122 break;
1123
1124 /*
1125 * OD GFX Voltage Offset functionality is supported only by 58.41.0
1126 * and onwards SMU firmwares.
1127 */
1128 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1129 if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1130 (smu_version < 0x003a2900))
1131 break;
1132
1133 size += sprintf(buf + size, "OD_VDDGFX_OFFSET:\n");
1134 size += sprintf(buf + size, "%dmV\n", od_table->VddGfxOffset);
1135 break;
1136
37a58f69
EQ		 1137 case SMU_OD_RANGE:
1138 if (!smu->od_enabled || !od_table || !od_settings)
1139 break;
1140
1141 size = sprintf(buf, "%s:\n", "OD_RANGE");
1142
1143 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1144 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1145 &min_value, NULL);
1146 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1147 NULL, &max_value);
1148 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
1149 min_value, max_value);
1150 }
1151
1152 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1153 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1154 &min_value, NULL);
1155 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1156 NULL, &max_value);
1157 size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
1158 min_value, max_value);
1159 }
1160 break;
1161
b455159c
LG		 1162 default:
1163 break;
1164 }
1165
258d290c
LG		 1166print_clk_out:
1167 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1168 amdgpu_gfx_off_ctrl(adev, true);
1169
b455159c
LG		 1170 return size;
1171}
1172
1173static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1174 enum smu_clk_type clk_type, uint32_t mask)
1175{
258d290c 1176 struct amdgpu_device *adev = smu->adev;
b455159c
LG		 1177 int ret = 0, size = 0;
1178 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1179
1180 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1181 soft_max_level = mask ? (fls(mask) - 1) : 0;
1182
258d290c
LG		 1183 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1184 amdgpu_gfx_off_ctrl(adev, false);
1185
b455159c
LG		 1186 switch (clk_type) {
1187 case SMU_GFXCLK:
1188 case SMU_SCLK:
1189 case SMU_SOCCLK:
1190 case SMU_MCLK:
1191 case SMU_UCLK:
b455159c 1192 case SMU_FCLK:
9ad9c8ac
LG		 1193 /* There is only 2 levels for fine grained DPM */
1194 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1195 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1196 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1197 }
1198
d8d3493a 1199 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
b455159c 1200 if (ret)
258d290c 1201 goto forec_level_out;
b455159c 1202
d8d3493a 1203 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
b455159c 1204 if (ret)
258d290c 1205 goto forec_level_out;
b455159c 1206
10e96d89 1207 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
b455159c 1208 if (ret)
258d290c 1209 goto forec_level_out;
b455159c 1210 break;
51ec6992
DP		 1211 case SMU_DCEFCLK:
1212 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1213 break;
b455159c
LG		 1214 default:
1215 break;
1216 }
1217
258d290c
LG		 1218forec_level_out:
1219 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1220 amdgpu_gfx_off_ctrl(adev, true);
1221
b455159c
LG		 1222 return size;
1223}
1224
1225static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1226{
62cc9dd1
EQ		 1227 struct smu_11_0_dpm_context *dpm_context =
1228 smu->smu_dpm.dpm_context;
1229 struct smu_11_0_dpm_table *gfx_table =
1230 &dpm_context->dpm_tables.gfx_table;
1231 struct smu_11_0_dpm_table *mem_table =
1232 &dpm_context->dpm_tables.uclk_table;
1233 struct smu_11_0_dpm_table *soc_table =
1234 &dpm_context->dpm_tables.soc_table;
1235 struct smu_umd_pstate_table *pstate_table =
1236 &smu->pstate_table;
1237
1238 pstate_table->gfxclk_pstate.min = gfx_table->min;
1239 pstate_table->gfxclk_pstate.peak = gfx_table->max;
0dc994fb
EQ		 1240 if (gfx_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK)
1241 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
62cc9dd1
EQ		 1242
1243 pstate_table->uclk_pstate.min = mem_table->min;
1244 pstate_table->uclk_pstate.peak = mem_table->max;
0dc994fb
EQ		 1245 if (mem_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK)
1246 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
62cc9dd1
EQ		 1247
1248 pstate_table->socclk_pstate.min = soc_table->min;
1249 pstate_table->socclk_pstate.peak = soc_table->max;
0dc994fb
EQ		 1250 if (soc_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK)
1251 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
b455159c 1252
62cc9dd1 1253 return 0;
b455159c
LG		 1254}
1255
b455159c
LG		 1256static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1257{
1258 int ret = 0;
1259 uint32_t max_freq = 0;
1260
1261 /* Sienna_Cichlid do not support to change display num currently */
1262 return 0;
1263#if 0
66c86828 1264 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
b455159c
LG		 1265 if (ret)
1266 return ret;
1267#endif
1268
b4bb3aaf 1269 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
e5ef784b 1270 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
b455159c
LG		 1271 if (ret)
1272 return ret;
661b94f5 1273 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
b455159c
LG		 1274 if (ret)
1275 return ret;
1276 }
1277
1278 return ret;
1279}
1280
1281static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1282{
1283 int ret = 0;
1284
b455159c 1285 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
4d942ae3
EQ		 1286 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1287 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
b455159c 1288#if 0
66c86828 1289 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
40d3b8db
LG		 1290 smu->display_config->num_display,
1291 NULL);
b455159c
LG		 1292#endif
1293 if (ret)
1294 return ret;
1295 }
1296
1297 return ret;
1298}
1299
b455159c
LG		 1300static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1301{
1302 int ret = 0;
1303 uint32_t feature_mask[2];
3d14a79b
KW		 1304 uint64_t feature_enabled;
1305
28251d72 1306 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
3d14a79b
KW		 1307 if (ret)
1308 return false;
1309
1310 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1311
b455159c
LG		 1312 return !!(feature_enabled & SMC_DPM_FEATURE);
1313}
1314
4954a76a
AD		 1315static int sienna_cichlid_get_fan_speed_percent(struct smu_context *smu,
1316 uint32_t *speed)
b455159c 1317{
4954a76a
AD		 1318 int ret;
1319 u32 rpm;
1320
b455159c
LG		 1321 if (!speed)
1322 return -EINVAL;
1323
4954a76a
AD		 1324 switch (smu_v11_0_get_fan_control_mode(smu)) {
1325 case AMD_FAN_CTRL_AUTO:
1326 ret = sienna_cichlid_get_smu_metrics_data(smu,
1327 METRICS_CURR_FANSPEED,
1328 &rpm);
1329 if (!ret && smu->fan_max_rpm)
1330 *speed = rpm * 100 / smu->fan_max_rpm;
1331 return ret;
1332 default:
1333 *speed = smu->user_dpm_profile.fan_speed_percent;
1334 return 0;
1335 }
b455159c
LG		 1336}
1337
3204ff3e
AD		 1338static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1339{
7077b19a 1340 uint16_t *table_member;
3204ff3e 1341
7077b19a
CG		 1342 GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
1343 smu->fan_max_rpm = *table_member;
3204ff3e
AD		 1344
1345 return 0;
1346}
1347
b455159c
LG		 1348static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1349{
f9e3fe46
EQ		 1350 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1351 DpmActivityMonitorCoeffInt_t *activity_monitor =
1352 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
b455159c
LG		 1353 uint32_t i, size = 0;
1354 int16_t workload_type = 0;
1355 static const char *profile_name[] = {
1356 "BOOTUP_DEFAULT",
1357 "3D_FULL_SCREEN",
1358 "POWER_SAVING",
1359 "VIDEO",
1360 "VR",
1361 "COMPUTE",
1362 "CUSTOM"};
1363 static const char *title[] = {
1364 "PROFILE_INDEX(NAME)",
1365 "CLOCK_TYPE(NAME)",
1366 "FPS",
1367 "MinFreqType",
1368 "MinActiveFreqType",
1369 "MinActiveFreq",
1370 "BoosterFreqType",
1371 "BoosterFreq",
1372 "PD_Data_limit_c",
1373 "PD_Data_error_coeff",
1374 "PD_Data_error_rate_coeff"};
1375 int result = 0;
1376
1377 if (!buf)
1378 return -EINVAL;
1379
1380 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1381 title[0], title[1], title[2], title[3], title[4], title[5],
1382 title[6], title[7], title[8], title[9], title[10]);
1383
1384 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1385 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
6c339f37
EQ		 1386 workload_type = smu_cmn_to_asic_specific_index(smu,
1387 CMN2ASIC_MAPPING_WORKLOAD,
1388 i);
b455159c
LG		 1389 if (workload_type < 0)
1390 return -EINVAL;
1391
caad2613 1392 result = smu_cmn_update_table(smu,
b455159c 1393 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
f9e3fe46 1394 (void *)(&activity_monitor_external), false);
b455159c 1395 if (result) {
d9811cfc 1396 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
b455159c
LG		 1397 return result;
1398 }
1399
1400 size += sprintf(buf + size, "%2d %14s%s:\n",
1401 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1402
1403 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1404 " ",
1405 0,
1406 "GFXCLK",
f9e3fe46
EQ		 1407 activity_monitor->Gfx_FPS,
1408 activity_monitor->Gfx_MinFreqStep,
1409 activity_monitor->Gfx_MinActiveFreqType,
1410 activity_monitor->Gfx_MinActiveFreq,
1411 activity_monitor->Gfx_BoosterFreqType,
1412 activity_monitor->Gfx_BoosterFreq,
1413 activity_monitor->Gfx_PD_Data_limit_c,
1414 activity_monitor->Gfx_PD_Data_error_coeff,
1415 activity_monitor->Gfx_PD_Data_error_rate_coeff);
b455159c
LG		 1416
1417 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1418 " ",
1419 1,
1420 "SOCCLK",
f9e3fe46
EQ		 1421 activity_monitor->Fclk_FPS,
1422 activity_monitor->Fclk_MinFreqStep,
1423 activity_monitor->Fclk_MinActiveFreqType,
1424 activity_monitor->Fclk_MinActiveFreq,
1425 activity_monitor->Fclk_BoosterFreqType,
1426 activity_monitor->Fclk_BoosterFreq,
1427 activity_monitor->Fclk_PD_Data_limit_c,
1428 activity_monitor->Fclk_PD_Data_error_coeff,
1429 activity_monitor->Fclk_PD_Data_error_rate_coeff);
b455159c
LG		 1430
1431 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1432 " ",
1433 2,
1434 "MEMLK",
f9e3fe46
EQ		 1435 activity_monitor->Mem_FPS,
1436 activity_monitor->Mem_MinFreqStep,
1437 activity_monitor->Mem_MinActiveFreqType,
1438 activity_monitor->Mem_MinActiveFreq,
1439 activity_monitor->Mem_BoosterFreqType,
1440 activity_monitor->Mem_BoosterFreq,
1441 activity_monitor->Mem_PD_Data_limit_c,
1442 activity_monitor->Mem_PD_Data_error_coeff,
1443 activity_monitor->Mem_PD_Data_error_rate_coeff);
b455159c
LG		 1444 }
1445
1446 return size;
1447}
1448
1449static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1450{
f9e3fe46
EQ		 1451
1452 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1453 DpmActivityMonitorCoeffInt_t *activity_monitor =
1454 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
b455159c
LG		 1455 int workload_type, ret = 0;
1456
1457 smu->power_profile_mode = input[size];
1458
1459 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
d9811cfc 1460 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
b455159c
LG		 1461 return -EINVAL;
1462 }
1463
1464 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
b455159c 1465
caad2613 1466 ret = smu_cmn_update_table(smu,
b455159c 1467 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
f9e3fe46 1468 (void *)(&activity_monitor_external), false);
b455159c 1469 if (ret) {
d9811cfc 1470 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
b455159c
LG		 1471 return ret;
1472 }
1473
1474 switch (input[0]) {
1475 case 0: /* Gfxclk */
f9e3fe46
EQ		 1476 activity_monitor->Gfx_FPS = input[1];
1477 activity_monitor->Gfx_MinFreqStep = input[2];
1478 activity_monitor->Gfx_MinActiveFreqType = input[3];
1479 activity_monitor->Gfx_MinActiveFreq = input[4];
1480 activity_monitor->Gfx_BoosterFreqType = input[5];
1481 activity_monitor->Gfx_BoosterFreq = input[6];
1482 activity_monitor->Gfx_PD_Data_limit_c = input[7];
1483 activity_monitor->Gfx_PD_Data_error_coeff = input[8];
1484 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1485 break;
1486 case 1: /* Socclk */
f9e3fe46
EQ		 1487 activity_monitor->Fclk_FPS = input[1];
1488 activity_monitor->Fclk_MinFreqStep = input[2];
1489 activity_monitor->Fclk_MinActiveFreqType = input[3];
1490 activity_monitor->Fclk_MinActiveFreq = input[4];
1491 activity_monitor->Fclk_BoosterFreqType = input[5];
1492 activity_monitor->Fclk_BoosterFreq = input[6];
1493 activity_monitor->Fclk_PD_Data_limit_c = input[7];
1494 activity_monitor->Fclk_PD_Data_error_coeff = input[8];
1495 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1496 break;
1497 case 2: /* Memlk */
f9e3fe46
EQ		 1498 activity_monitor->Mem_FPS = input[1];
1499 activity_monitor->Mem_MinFreqStep = input[2];
1500 activity_monitor->Mem_MinActiveFreqType = input[3];
1501 activity_monitor->Mem_MinActiveFreq = input[4];
1502 activity_monitor->Mem_BoosterFreqType = input[5];
1503 activity_monitor->Mem_BoosterFreq = input[6];
1504 activity_monitor->Mem_PD_Data_limit_c = input[7];
1505 activity_monitor->Mem_PD_Data_error_coeff = input[8];
1506 activity_monitor->Mem_PD_Data_error_rate_coeff = input[9];
b455159c
LG		 1507 break;
1508 }
1509
caad2613 1510 ret = smu_cmn_update_table(smu,
b455159c 1511 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
f9e3fe46 1512 (void *)(&activity_monitor_external), true);
b455159c 1513 if (ret) {
d9811cfc 1514 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
b455159c
LG		 1515 return ret;
1516 }
1517 }
1518
1519 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
6c339f37
EQ		 1520 workload_type = smu_cmn_to_asic_specific_index(smu,
1521 CMN2ASIC_MAPPING_WORKLOAD,
1522 smu->power_profile_mode);
b455159c
LG		 1523 if (workload_type < 0)
1524 return -EINVAL;
66c86828 1525 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
b455159c
LG		 1526 1 << workload_type, NULL);
1527
1528 return ret;
1529}
1530
b455159c
LG		 1531static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1532{
1533 struct smu_clocks min_clocks = {0};
1534 struct pp_display_clock_request clock_req;
1535 int ret = 0;
1536
1537 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1538 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1539 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1540
4d942ae3 1541 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
b455159c
LG		 1542 clock_req.clock_type = amd_pp_dcef_clock;
1543 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1544
1545 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1546 if (!ret) {
4d942ae3 1547 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
66c86828 1548 ret = smu_cmn_send_smc_msg_with_param(smu,
40d3b8db
LG		 1549 SMU_MSG_SetMinDeepSleepDcefclk,
1550 min_clocks.dcef_clock_in_sr/100,
1551 NULL);
1552 if (ret) {
d9811cfc 1553 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
40d3b8db
LG		 1554 return ret;
1555 }
b455159c
LG		 1556 }
1557 } else {
d9811cfc 1558 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
b455159c
LG		 1559 }
1560 }
1561
b4bb3aaf 1562 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
661b94f5 1563 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
b455159c 1564 if (ret) {
d9811cfc 1565 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
b455159c
LG		 1566 return ret;
1567 }
1568 }
1569
1570 return 0;
1571}
1572
1573static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
7b9c7e30 1574 struct pp_smu_wm_range_sets *clock_ranges)
b455159c 1575{
e7a95eea 1576 Watermarks_t *table = smu->smu_table.watermarks_table;
40d3b8db 1577 int ret = 0;
e7a95eea 1578 int i;
b455159c 1579
e7a95eea 1580 if (clock_ranges) {
7b9c7e30
EQ		 1581 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1582 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
e7a95eea
EQ		 1583 return -EINVAL;
1584
7b9c7e30
EQ		 1585 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1586 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1587 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1588 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1589 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1590 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1591 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1592 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1593 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1594
1595 table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1596 clock_ranges->reader_wm_sets[i].wm_inst;
e7a95eea 1597 }
b455159c 1598
7b9c7e30
EQ		 1599 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1600 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1601 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1602 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1603 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1604 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1605 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1606 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1607 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1608
1609 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1610 clock_ranges->writer_wm_sets[i].wm_inst;
e7a95eea
EQ		 1611 }
1612
1613 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1614 }
1615
1616 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1617 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
caad2613 1618 ret = smu_cmn_write_watermarks_table(smu);
40d3b8db 1619 if (ret) {
d9811cfc 1620 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
40d3b8db
LG		 1621 return ret;
1622 }
1623 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1624 }
1625
b455159c
LG		 1626 return 0;
1627}
1628
b455159c
LG		 1629static int sienna_cichlid_read_sensor(struct smu_context *smu,
1630 enum amd_pp_sensors sensor,
1631 void *data, uint32_t *size)
1632{
1633 int ret = 0;
7077b19a 1634 uint16_t *temp;
b455159c
LG		 1635
1636 if(!data || !size)
1637 return -EINVAL;
1638
1639 mutex_lock(&smu->sensor_lock);
1640 switch (sensor) {
1641 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
7077b19a
CG		 1642 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
1643 *(uint16_t *)data = *temp;
b455159c
LG		 1644 *size = 4;
1645 break;
1646 case AMDGPU_PP_SENSOR_MEM_LOAD:
60e317a2
AD		 1647 ret = sienna_cichlid_get_smu_metrics_data(smu,
1648 METRICS_AVERAGE_MEMACTIVITY,
1649 (uint32_t *)data);
1650 *size = 4;
1651 break;
b455159c 1652 case AMDGPU_PP_SENSOR_GPU_LOAD:
60e317a2
AD		 1653 ret = sienna_cichlid_get_smu_metrics_data(smu,
1654 METRICS_AVERAGE_GFXACTIVITY,
1655 (uint32_t *)data);
b455159c
LG		 1656 *size = 4;
1657 break;
1658 case AMDGPU_PP_SENSOR_GPU_POWER:
60e317a2
AD		 1659 ret = sienna_cichlid_get_smu_metrics_data(smu,
1660 METRICS_AVERAGE_SOCKETPOWER,
1661 (uint32_t *)data);
b455159c
LG		 1662 *size = 4;
1663 break;
1664 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
60e317a2
AD		 1665 ret = sienna_cichlid_get_smu_metrics_data(smu,
1666 METRICS_TEMPERATURE_HOTSPOT,
1667 (uint32_t *)data);
1668 *size = 4;
1669 break;
b455159c 1670 case AMDGPU_PP_SENSOR_EDGE_TEMP:
60e317a2
AD		 1671 ret = sienna_cichlid_get_smu_metrics_data(smu,
1672 METRICS_TEMPERATURE_EDGE,
1673 (uint32_t *)data);
1674 *size = 4;
1675 break;
b455159c 1676 case AMDGPU_PP_SENSOR_MEM_TEMP:
60e317a2
AD		 1677 ret = sienna_cichlid_get_smu_metrics_data(smu,
1678 METRICS_TEMPERATURE_MEM,
1679 (uint32_t *)data);
b455159c
LG		 1680 *size = 4;
1681 break;
e0f9e936
EQ		 1682 case AMDGPU_PP_SENSOR_GFX_MCLK:
1683 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1684 *(uint32_t *)data *= 100;
1685 *size = 4;
1686 break;
1687 case AMDGPU_PP_SENSOR_GFX_SCLK:
1688 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1689 *(uint32_t *)data *= 100;
1690 *size = 4;
1691 break;
b2febc99
EQ		 1692 case AMDGPU_PP_SENSOR_VDDGFX:
1693 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1694 *size = 4;
1695 break;
b455159c 1696 default:
b2febc99
EQ		 1697 ret = -EOPNOTSUPP;
1698 break;
b455159c
LG		 1699 }
1700 mutex_unlock(&smu->sensor_lock);
1701
1702 return ret;
1703}
1704
1705static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1706{
1707 uint32_t num_discrete_levels = 0;
1708 uint16_t *dpm_levels = NULL;
1709 uint16_t i = 0;
1710 struct smu_table_context *table_context = &smu->smu_table;
7077b19a
CG		 1711 DpmDescriptor_t *table_member1;
1712 uint16_t *table_member2;
b455159c
LG		 1713
1714 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1715 return -EINVAL;
1716
7077b19a
CG		 1717 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
1718 num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
1719 GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
1720 dpm_levels = table_member2;
b455159c
LG		 1721
1722 if (num_discrete_levels == 0 || dpm_levels == NULL)
1723 return -EINVAL;
1724
1725 *num_states = num_discrete_levels;
1726 for (i = 0; i < num_discrete_levels; i++) {
1727 /* convert to khz */
1728 *clocks_in_khz = (*dpm_levels) * 1000;
1729 clocks_in_khz++;
1730 dpm_levels++;
1731 }
1732
1733 return 0;
1734}
1735
1736static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1737 struct smu_temperature_range *range)
1738{
e02e4d51
EQ		 1739 struct smu_table_context *table_context = &smu->smu_table;
1740 struct smu_11_0_7_powerplay_table *powerplay_table =
1741 table_context->power_play_table;
7077b19a
CG		 1742 uint16_t *table_member;
1743 uint16_t temp_edge, temp_hotspot, temp_mem;
b455159c 1744
2b1f12a2 1745 if (!range)
b455159c
LG		 1746 return -EINVAL;
1747
0540eced
EQ		 1748 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1749
7077b19a
CG		 1750 GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
1751 temp_edge = table_member[TEMP_EDGE];
1752 temp_hotspot = table_member[TEMP_HOTSPOT];
1753 temp_mem = table_member[TEMP_MEM];
1754
1755 range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1756 range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
2b1f12a2 1757 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a
CG		 1758 range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1759 range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
2b1f12a2 1760 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a
CG		 1761 range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1762 range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
b455159c 1763 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
7077b19a 1764
e02e4d51 1765 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
b455159c
LG		 1766
1767 return 0;
1768}
1769
1770static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1771 bool disable_memory_clock_switch)
1772{
1773 int ret = 0;
1774 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1775 (struct smu_11_0_max_sustainable_clocks *)
1776 smu->smu_table.max_sustainable_clocks;
1777 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1778 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1779
1780 if(smu->disable_uclk_switch == disable_memory_clock_switch)
1781 return 0;
1782
1783 if(disable_memory_clock_switch)
661b94f5 1784 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
b455159c 1785 else
661b94f5 1786 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
b455159c
LG		 1787
1788 if(!ret)
1789 smu->disable_uclk_switch = disable_memory_clock_switch;
1790
1791 return ret;
1792}
1793
488f211d
EQ		 1794static int sienna_cichlid_get_power_limit(struct smu_context *smu,
1795 uint32_t *current_power_limit,
1796 uint32_t *default_power_limit,
1797 uint32_t *max_power_limit)
b455159c 1798{
1e239fdd
EQ		 1799 struct smu_11_0_7_powerplay_table *powerplay_table =
1800 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
1e239fdd 1801 uint32_t power_limit, od_percent;
7077b19a
CG		 1802 uint16_t *table_member;
1803
1804 GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
1e239fdd
EQ		 1805
1806 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1e239fdd 1807 power_limit =
7077b19a 1808 table_member[PPT_THROTTLER_PPT0];
1e239fdd 1809 }
b455159c 1810
488f211d
EQ		 1811 if (current_power_limit)
1812 *current_power_limit = power_limit;
1813 if (default_power_limit)
1814 *default_power_limit = power_limit;
1e239fdd 1815
488f211d
EQ		 1816 if (max_power_limit) {
1817 if (smu->od_enabled) {
1818 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
1e239fdd 1819
488f211d
EQ		 1820 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1821
1822 power_limit *= (100 + od_percent);
1823 power_limit /= 100;
1824 }
1825 *max_power_limit = power_limit;
b455159c
LG		 1826 }
1827
b455159c
LG		 1828 return 0;
1829}
1830
08ccfe08
LG		 1831static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1832 uint32_t pcie_gen_cap,
1833 uint32_t pcie_width_cap)
1834{
0b590970 1835 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
7077b19a 1836
08ccfe08 1837 uint32_t smu_pcie_arg;
7077b19a 1838 uint8_t *table_member1, *table_member2;
0b590970 1839 int ret, i;
08ccfe08 1840
7077b19a
CG		 1841 GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
1842 GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
1843
0b590970
EQ		 1844 /* lclk dpm table setup */
1845 for (i = 0; i < MAX_PCIE_CONF; i++) {
7077b19a
CG		 1846 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = table_member1[i];
1847 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = table_member2[i];
0b590970 1848 }
08ccfe08
LG		 1849
1850 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1851 smu_pcie_arg = (i << 16) |
7077b19a
CG		 1852 ((table_member1[i] <= pcie_gen_cap) ?
1853 (table_member1[i] << 8) :
1854 (pcie_gen_cap << 8)) |
1855 ((table_member2[i] <= pcie_width_cap) ?
1856 table_member2[i] :
1857 pcie_width_cap);
08ccfe08 1858
66c86828 1859 ret = smu_cmn_send_smc_msg_with_param(smu,
7077b19a
CG		 1860 SMU_MSG_OverridePcieParameters,
1861 smu_pcie_arg,
1862 NULL);
08ccfe08
LG		 1863 if (ret)
1864 return ret;
1865
7077b19a 1866 if (table_member1[i] > pcie_gen_cap)
08ccfe08 1867 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
7077b19a 1868 if (table_member2[i] > pcie_width_cap)
08ccfe08
LG		 1869 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1870 }
1871
1872 return 0;
1873}
1874
38ed7b09 1875static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
258d290c
LG		 1876 enum smu_clk_type clk_type,
1877 uint32_t *min, uint32_t *max)
1878{
1879 struct amdgpu_device *adev = smu->adev;
1880 int ret;
1881
1882 if (clk_type == SMU_GFXCLK)
1883 amdgpu_gfx_off_ctrl(adev, false);
1884 ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
1885 if (clk_type == SMU_GFXCLK)
1886 amdgpu_gfx_off_ctrl(adev, true);
1887
1888 return ret;
1889}
1890
aa75fa34
EQ		 1891static void sienna_cichlid_dump_od_table(struct smu_context *smu,
1892 OverDriveTable_t *od_table)
1893{
a2b6df4f
EQ		 1894 struct amdgpu_device *adev = smu->adev;
1895 uint32_t smu_version;
1896
aa75fa34
EQ		 1897 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
1898 od_table->GfxclkFmax);
1899 dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
1900 od_table->UclkFmax);
a2b6df4f
EQ		 1901
1902 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1903 if (!((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1904 (smu_version < 0x003a2900)))
1905 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
aa75fa34
EQ		 1906}
1907
1908static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
1909{
1910 OverDriveTable_t *od_table =
1911 (OverDriveTable_t *)smu->smu_table.overdrive_table;
1912 OverDriveTable_t *boot_od_table =
1913 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
1914 int ret = 0;
1915
1916 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
1917 0, (void *)od_table, false);
1918 if (ret) {
1919 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
1920 return ret;
1921 }
1922
1923 memcpy(boot_od_table, od_table, sizeof(OverDriveTable_t));
1924
1925 sienna_cichlid_dump_od_table(smu, od_table);
1926
1927 return 0;
1928}
1929
37a58f69
EQ		 1930static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
1931 struct smu_11_0_7_overdrive_table *od_table,
1932 enum SMU_11_0_7_ODSETTING_ID setting,
1933 uint32_t value)
1934{
1935 if (value < od_table->min[setting]) {
1936 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
1937 setting, value, od_table->min[setting]);
1938 return -EINVAL;
1939 }
1940 if (value > od_table->max[setting]) {
1941 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
1942 setting, value, od_table->max[setting]);
1943 return -EINVAL;
1944 }
1945
1946 return 0;
1947}
1948
1949static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
1950 enum PP_OD_DPM_TABLE_COMMAND type,
1951 long input[], uint32_t size)
1952{
1953 struct smu_table_context *table_context = &smu->smu_table;
1954 OverDriveTable_t *od_table =
1955 (OverDriveTable_t *)table_context->overdrive_table;
1956 struct smu_11_0_7_overdrive_table *od_settings =
1957 (struct smu_11_0_7_overdrive_table *)smu->od_settings;
a2b6df4f 1958 struct amdgpu_device *adev = smu->adev;
37a58f69
EQ		 1959 enum SMU_11_0_7_ODSETTING_ID freq_setting;
1960 uint16_t *freq_ptr;
1961 int i, ret = 0;
a2b6df4f 1962 uint32_t smu_version;
37a58f69
EQ		 1963
1964 if (!smu->od_enabled) {
1965 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
1966 return -EINVAL;
1967 }
1968
1969 if (!smu->od_settings) {
1970 dev_err(smu->adev->dev, "OD board limits are not set!\n");
1971 return -ENOENT;
1972 }
1973
1974 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
1975 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
1976 return -EINVAL;
1977 }
1978
1979 switch (type) {
1980 case PP_OD_EDIT_SCLK_VDDC_TABLE:
1981 if (!sienna_cichlid_is_od_feature_supported(od_settings,
1982 SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1983 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
1984 return -ENOTSUPP;
1985 }
1986
1987 for (i = 0; i < size; i += 2) {
1988 if (i + 2 > size) {
1989 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
1990 return -EINVAL;
1991 }
1992
1993 switch (input[i]) {
1994 case 0:
1995 if (input[i + 1] > od_table->GfxclkFmax) {
1996 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
1997 input[i + 1], od_table->GfxclkFmax);
1998 return -EINVAL;
1999 }
2000
2001 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
2002 freq_ptr = &od_table->GfxclkFmin;
2003 break;
2004
2005 case 1:
2006 if (input[i + 1] < od_table->GfxclkFmin) {
2007 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2008 input[i + 1], od_table->GfxclkFmin);
2009 return -EINVAL;
2010 }
2011
2012 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
2013 freq_ptr = &od_table->GfxclkFmax;
2014 break;
2015
2016 default:
2017 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2018 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2019 return -EINVAL;
2020 }
2021
2022 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2023 freq_setting, input[i + 1]);
2024 if (ret)
2025 return ret;
2026
2027 *freq_ptr = (uint16_t)input[i + 1];
2028 }
2029 break;
2030
2031 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2032 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
2033 dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2034 return -ENOTSUPP;
2035 }
2036
2037 for (i = 0; i < size; i += 2) {
2038 if (i + 2 > size) {
2039 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2040 return -EINVAL;
2041 }
2042
2043 switch (input[i]) {
2044 case 0:
2045 if (input[i + 1] > od_table->UclkFmax) {
2046 dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2047 input[i + 1], od_table->UclkFmax);
2048 return -EINVAL;
2049 }
2050
2051 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
2052 freq_ptr = &od_table->UclkFmin;
2053 break;
2054
2055 case 1:
2056 if (input[i + 1] < od_table->UclkFmin) {
2057 dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2058 input[i + 1], od_table->UclkFmin);
2059 return -EINVAL;
2060 }
2061
2062 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
2063 freq_ptr = &od_table->UclkFmax;
2064 break;
2065
2066 default:
2067 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2068 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2069 return -EINVAL;
2070 }
2071
2072 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2073 freq_setting, input[i + 1]);
2074 if (ret)
2075 return ret;
2076
2077 *freq_ptr = (uint16_t)input[i + 1];
2078 }
2079 break;
2080
2081 case PP_OD_RESTORE_DEFAULT_TABLE:
2082 memcpy(table_context->overdrive_table,
2083 table_context->boot_overdrive_table,
2084 sizeof(OverDriveTable_t));
2085 fallthrough;
2086
2087 case PP_OD_COMMIT_DPM_TABLE:
2088 sienna_cichlid_dump_od_table(smu, od_table);
2089
2090 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
2091 0, (void *)od_table, true);
2092 if (ret) {
2093 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2094 return ret;
2095 }
2096 break;
2097
a2b6df4f
EQ		 2098 case PP_OD_EDIT_VDDGFX_OFFSET:
2099 if (size != 1) {
2100 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2101 return -EINVAL;
2102 }
2103
2104 /*
2105 * OD GFX Voltage Offset functionality is supported only by 58.41.0
2106 * and onwards SMU firmwares.
2107 */
2108 smu_cmn_get_smc_version(smu, NULL, &smu_version);
2109 if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
2110 (smu_version < 0x003a2900)) {
2111 dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2112 "only by 58.41.0 and onwards SMU firmwares!\n");
2113 return -EOPNOTSUPP;
2114 }
2115
2116 od_table->VddGfxOffset = (int16_t)input[0];
2117
2118 sienna_cichlid_dump_od_table(smu, od_table);
2119 break;
2120
37a58f69
EQ		 2121 default:
2122 return -ENOSYS;
2123 }
2124
2125 return ret;
2126}
2127
66b8a9c0
JC		 2128static int sienna_cichlid_run_btc(struct smu_context *smu)
2129{
2130 return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2131}
2132
13d75ead
EQ		 2133static int sienna_cichlid_baco_enter(struct smu_context *smu)
2134{
2135 struct amdgpu_device *adev = smu->adev;
2136
2137 if (adev->in_runpm)
2138 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2139 else
2140 return smu_v11_0_baco_enter(smu);
2141}
2142
2143static int sienna_cichlid_baco_exit(struct smu_context *smu)
2144{
2145 struct amdgpu_device *adev = smu->adev;
2146
2147 if (adev->in_runpm) {
2148 /* Wait for PMFW handling for the Dstate change */
2149 msleep(10);
2150 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2151 } else {
2152 return smu_v11_0_baco_exit(smu);
2153 }
2154}
2155
ea8139d8
WS		 2156static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2157{
2158 struct amdgpu_device *adev = smu->adev;
2159 uint32_t val;
2160 u32 smu_version;
2161
2162 /**
2163 * SRIOV env will not support SMU mode1 reset
2164 * PM FW support mode1 reset from 58.26
2165 */
a7bae061 2166 smu_cmn_get_smc_version(smu, NULL, &smu_version);
ea8139d8
WS		 2167 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
2168 return false;
2169
2170 /**
2171 * mode1 reset relies on PSP, so we should check if
2172 * PSP is alive.
2173 */
2174 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2175 return val != 0x0;
2176}
2177
7077b19a
CG		 2178static void beige_goby_dump_pptable(struct smu_context *smu)
2179{
2180 struct smu_table_context *table_context = &smu->smu_table;
2181 PPTable_beige_goby_t *pptable = table_context->driver_pptable;
2182 int i;
2183
2184 dev_info(smu->adev->dev, "Dumped PPTable:\n");
2185
2186 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2187 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2188 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2189
2190 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2191 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2192 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2193 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2194 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2195 }
2196
2197 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2198 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2199 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2200 }
2201
2202 for (i = 0; i < TEMP_COUNT; i++) {
2203 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2204 }
2205
2206 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2207 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2208 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2209 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2210 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2211
2212 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2213 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2214 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2215 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2216 }
2217 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2218
2219 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2220
2221 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2222 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2223 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2224 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2225
2226 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2227
2228 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2229
2230 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2231 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2232 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2233 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2234
2235 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2236 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2237
2238 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2239 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2240 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2241 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2242 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2243 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2244 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2245 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2246
2247 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2248 " .VoltageMode = 0x%02x\n"
2249 " .SnapToDiscrete = 0x%02x\n"
2250 " .NumDiscreteLevels = 0x%02x\n"
2251 " .padding = 0x%02x\n"
2252 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2253 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2254 " .SsFmin = 0x%04x\n"
2255 " .Padding_16 = 0x%04x\n",
2256 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2257 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2258 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2259 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2260 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2261 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2262 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2263 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2264 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2265 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2266 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2267
2268 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2269 " .VoltageMode = 0x%02x\n"
2270 " .SnapToDiscrete = 0x%02x\n"
2271 " .NumDiscreteLevels = 0x%02x\n"
2272 " .padding = 0x%02x\n"
2273 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2274 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2275 " .SsFmin = 0x%04x\n"
2276 " .Padding_16 = 0x%04x\n",
2277 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2278 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2279 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2280 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2281 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2282 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2283 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2284 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2285 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2286 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2287 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2288
2289 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2290 " .VoltageMode = 0x%02x\n"
2291 " .SnapToDiscrete = 0x%02x\n"
2292 " .NumDiscreteLevels = 0x%02x\n"
2293 " .padding = 0x%02x\n"
2294 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2295 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2296 " .SsFmin = 0x%04x\n"
2297 " .Padding_16 = 0x%04x\n",
2298 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2299 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2300 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2301 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2302 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2303 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2304 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2305 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2306 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2307 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2308 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2309
2310 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2311 " .VoltageMode = 0x%02x\n"
2312 " .SnapToDiscrete = 0x%02x\n"
2313 " .NumDiscreteLevels = 0x%02x\n"
2314 " .padding = 0x%02x\n"
2315 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2316 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2317 " .SsFmin = 0x%04x\n"
2318 " .Padding_16 = 0x%04x\n",
2319 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2320 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2321 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2322 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2323 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2324 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2325 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2326 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2327 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2328 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2329 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2330
2331 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2332 " .VoltageMode = 0x%02x\n"
2333 " .SnapToDiscrete = 0x%02x\n"
2334 " .NumDiscreteLevels = 0x%02x\n"
2335 " .padding = 0x%02x\n"
2336 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2337 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2338 " .SsFmin = 0x%04x\n"
2339 " .Padding_16 = 0x%04x\n",
2340 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2341 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2342 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2343 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2344 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2345 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2346 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2347 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2348 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2349 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2350 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2351
2352 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2353 " .VoltageMode = 0x%02x\n"
2354 " .SnapToDiscrete = 0x%02x\n"
2355 " .NumDiscreteLevels = 0x%02x\n"
2356 " .padding = 0x%02x\n"
2357 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2358 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2359 " .SsFmin = 0x%04x\n"
2360 " .Padding_16 = 0x%04x\n",
2361 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2362 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2363 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2364 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2365 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2366 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2367 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2368 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2369 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2370 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2371 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2372
2373 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2374 " .VoltageMode = 0x%02x\n"
2375 " .SnapToDiscrete = 0x%02x\n"
2376 " .NumDiscreteLevels = 0x%02x\n"
2377 " .padding = 0x%02x\n"
2378 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2379 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2380 " .SsFmin = 0x%04x\n"
2381 " .Padding_16 = 0x%04x\n",
2382 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2383 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2384 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2385 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2386 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2387 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2388 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2389 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2390 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2391 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2392 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2393
2394 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2395 " .VoltageMode = 0x%02x\n"
2396 " .SnapToDiscrete = 0x%02x\n"
2397 " .NumDiscreteLevels = 0x%02x\n"
2398 " .padding = 0x%02x\n"
2399 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2400 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2401 " .SsFmin = 0x%04x\n"
2402 " .Padding_16 = 0x%04x\n",
2403 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2404 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2405 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2406 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2407 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2408 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2409 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2410 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2411 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2412 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2413 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2414
2415 dev_info(smu->adev->dev, "FreqTableGfx\n");
2416 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2417 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2418
2419 dev_info(smu->adev->dev, "FreqTableVclk\n");
2420 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2421 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2422
2423 dev_info(smu->adev->dev, "FreqTableDclk\n");
2424 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2425 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2426
2427 dev_info(smu->adev->dev, "FreqTableSocclk\n");
2428 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2429 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2430
2431 dev_info(smu->adev->dev, "FreqTableUclk\n");
2432 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2433 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2434
2435 dev_info(smu->adev->dev, "FreqTableFclk\n");
2436 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2437 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2438
2439 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2440 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2441 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2442 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2443 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2444 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2445 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2446 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2447 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2448
2449 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2450 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2451 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2452
2453 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2454 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2455
2456 dev_info(smu->adev->dev, "Mp0clkFreq\n");
2457 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2458 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2459
2460 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2461 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2462 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2463
2464 dev_info(smu->adev->dev, "MemVddciVoltage\n");
2465 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2466 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2467
2468 dev_info(smu->adev->dev, "MemMvddVoltage\n");
2469 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2470 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2471
2472 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2473 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2474 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2475 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2476 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2477
2478 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2479
2480 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2481 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2482 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2483 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2484 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2485 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2486 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2487 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2488 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2489 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2490 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2491
2492 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2493 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2494 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2495 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2496 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2497 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2498
2499 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2500 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2501 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2502 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2503 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2504
2505 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2506 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2507 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2508
2509 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2510 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2511 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2512 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2513
2514 dev_info(smu->adev->dev, "UclkDpmPstates\n");
2515 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2516 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2517
2518 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2519 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2520 pptable->UclkDpmSrcFreqRange.Fmin);
2521 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2522 pptable->UclkDpmSrcFreqRange.Fmax);
2523 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2524 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2525 pptable->UclkDpmTargFreqRange.Fmin);
2526 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2527 pptable->UclkDpmTargFreqRange.Fmax);
2528 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2529 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2530
2531 dev_info(smu->adev->dev, "PcieGenSpeed\n");
2532 for (i = 0; i < NUM_LINK_LEVELS; i++)
2533 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2534
2535 dev_info(smu->adev->dev, "PcieLaneCount\n");
2536 for (i = 0; i < NUM_LINK_LEVELS; i++)
2537 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2538
2539 dev_info(smu->adev->dev, "LclkFreq\n");
2540 for (i = 0; i < NUM_LINK_LEVELS; i++)
2541 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2542
2543 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2544 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2545
2546 dev_info(smu->adev->dev, "FanGain\n");
2547 for (i = 0; i < TEMP_COUNT; i++)
2548 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2549
2550 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2551 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2552 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2553 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2554 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2555 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2556 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2557 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2558 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2559 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2560 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2561 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2562
2563 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2564 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2565 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2566 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2567
2568 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2569 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2570 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2571 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2572
2573 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2574 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2575 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2576 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2577 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2578 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2579 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2580 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2581 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2582 pptable->dBtcGbGfxPll.a,
2583 pptable->dBtcGbGfxPll.b,
2584 pptable->dBtcGbGfxPll.c);
2585 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2586 pptable->dBtcGbGfxDfll.a,
2587 pptable->dBtcGbGfxDfll.b,
2588 pptable->dBtcGbGfxDfll.c);
2589 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2590 pptable->dBtcGbSoc.a,
2591 pptable->dBtcGbSoc.b,
2592 pptable->dBtcGbSoc.c);
2593 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2594 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2595 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2596 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2597 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2598 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2599
2600 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2601 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2602 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
2603 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2604 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
2605 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2606 }
2607
2608 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2609 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2610 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2611 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2612 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2613 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2614 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2615 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2616
2617 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2618 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2619
2620 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2621 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2622 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2623 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2624
2625 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2626 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2627 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2628 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2629
2630 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2631 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2632
2633 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2634 for (i = 0; i < NUM_XGMI_LEVELS; i++)
2635 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2636 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2637 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2638
2639 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2640 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2641 pptable->ReservedEquation0.a,
2642 pptable->ReservedEquation0.b,
2643 pptable->ReservedEquation0.c);
2644 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2645 pptable->ReservedEquation1.a,
2646 pptable->ReservedEquation1.b,
2647 pptable->ReservedEquation1.c);
2648 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2649 pptable->ReservedEquation2.a,
2650 pptable->ReservedEquation2.b,
2651 pptable->ReservedEquation2.c);
2652 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2653 pptable->ReservedEquation3.a,
2654 pptable->ReservedEquation3.b,
2655 pptable->ReservedEquation3.c);
2656
2657 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2658 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2659 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2660 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2661 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2662 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2663 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2664 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2665
2666 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2667 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2668 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2669 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2670 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2671 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2672
2673 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2674 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2675 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
2676 pptable->I2cControllers[i].Enabled);
2677 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
2678 pptable->I2cControllers[i].Speed);
2679 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
2680 pptable->I2cControllers[i].SlaveAddress);
2681 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
2682 pptable->I2cControllers[i].ControllerPort);
2683 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
2684 pptable->I2cControllers[i].ControllerName);
2685 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
2686 pptable->I2cControllers[i].ThermalThrotter);
2687 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
2688 pptable->I2cControllers[i].I2cProtocol);
2689 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
2690 pptable->I2cControllers[i].PaddingConfig);
2691 }
2692
2693 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2694 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2695 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2696 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2697
2698 dev_info(smu->adev->dev, "Board Parameters:\n");
2699 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2700 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2701 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2702 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2703 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2704 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2705 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2706 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2707
2708 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2709 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2710 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2711
2712 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2713 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2714 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2715
2716 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2717 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2718 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2719
2720 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2721 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2722 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2723
2724 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2725
2726 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2727 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2728 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2729 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2730 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2731 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2732 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2733 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2734 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2735 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2736 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2737 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2738 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2739 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2740 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2741 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2742
2743 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2744 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2745 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
2746
2747 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2748 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2749 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
2750
2751 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
2752 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2753
2754 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2755 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2756 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2757
2758 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2759 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2760 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2761 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2762 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2763
2764 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2765 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2766
2767 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
2768 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2769 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2770 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
2771 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2772 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2773 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
2774 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2775 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2776 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
2777 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2778 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2779
2780 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2781 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2782 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2783 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2784
2785 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2786 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2787 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2788 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2789 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2790 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2791 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2792 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2793 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2794 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2795 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2796
2797 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2798 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2799 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2800 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2801 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2802 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2803 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2804 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2805}
2806
b455159c
LG		 2807static void sienna_cichlid_dump_pptable(struct smu_context *smu)
2808{
2809 struct smu_table_context *table_context = &smu->smu_table;
2810 PPTable_t *pptable = table_context->driver_pptable;
2811 int i;
2812
7077b19a
CG		 2813 if (smu->adev->asic_type == CHIP_BEIGE_GOBY) {
2814 beige_goby_dump_pptable(smu);
2815 return;
2816 }
2817
d9811cfc 2818 dev_info(smu->adev->dev, "Dumped PPTable:\n");
b455159c 2819
d9811cfc
EQ		 2820 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2821 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2822 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
b455159c
LG		 2823
2824 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
d9811cfc
EQ		 2825 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2826 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2827 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2828 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
b455159c
LG		 2829 }
2830
2831 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
d9811cfc
EQ		 2832 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2833 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
b455159c
LG		 2834 }
2835
2836 for (i = 0; i < TEMP_COUNT; i++) {
d9811cfc 2837 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
b455159c
LG		 2838 }
2839
d9811cfc
EQ		 2840 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2841 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2842 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2843 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2844 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
b455159c 2845
d9811cfc 2846 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
b455159c 2847 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
d9811cfc
EQ		 2848 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2849 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
b455159c 2850 }
d9811cfc
EQ		 2851 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2852
2853 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2854
2855 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2856 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2857 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2858 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2859
2860 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2861 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
2862
2863 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2864 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
2865 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
2866 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
2867
2868 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2869 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2870 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2871 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2872
2873 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2874 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2875
2876 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2877 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2878 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2879 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2880 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2881 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2882 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2883 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2884
2885 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
b455159c
LG		 2886 " .VoltageMode = 0x%02x\n"
2887 " .SnapToDiscrete = 0x%02x\n"
2888 " .NumDiscreteLevels = 0x%02x\n"
2889 " .padding = 0x%02x\n"
2890 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2891 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2892 " .SsFmin = 0x%04x\n"
2893 " .Padding_16 = 0x%04x\n",
2894 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2895 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2896 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2897 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2898 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2899 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2900 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2901 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2902 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2903 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2904 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2905
d9811cfc 2906 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
b455159c
LG		 2907 " .VoltageMode = 0x%02x\n"
2908 " .SnapToDiscrete = 0x%02x\n"
2909 " .NumDiscreteLevels = 0x%02x\n"
2910 " .padding = 0x%02x\n"
2911 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2912 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2913 " .SsFmin = 0x%04x\n"
2914 " .Padding_16 = 0x%04x\n",
2915 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2916 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2917 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2918 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2919 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2920 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2921 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2922 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2923 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2924 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2925 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2926
d9811cfc 2927 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
b455159c
LG		 2928 " .VoltageMode = 0x%02x\n"
2929 " .SnapToDiscrete = 0x%02x\n"
2930 " .NumDiscreteLevels = 0x%02x\n"
2931 " .padding = 0x%02x\n"
2932 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2933 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2934 " .SsFmin = 0x%04x\n"
2935 " .Padding_16 = 0x%04x\n",
2936 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2937 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2938 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2939 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2940 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2941 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2942 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2943 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2944 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2945 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2946 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2947
d9811cfc 2948 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
b455159c
LG		 2949 " .VoltageMode = 0x%02x\n"
2950 " .SnapToDiscrete = 0x%02x\n"
2951 " .NumDiscreteLevels = 0x%02x\n"
2952 " .padding = 0x%02x\n"
2953 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2954 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2955 " .SsFmin = 0x%04x\n"
2956 " .Padding_16 = 0x%04x\n",
2957 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2958 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2959 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2960 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2961 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2962 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2963 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2964 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2965 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2966 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2967 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2968
d9811cfc 2969 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
b455159c
LG		 2970 " .VoltageMode = 0x%02x\n"
2971 " .SnapToDiscrete = 0x%02x\n"
2972 " .NumDiscreteLevels = 0x%02x\n"
2973 " .padding = 0x%02x\n"
2974 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2975 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2976 " .SsFmin = 0x%04x\n"
2977 " .Padding_16 = 0x%04x\n",
2978 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2979 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2980 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2981 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2982 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2983 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2984 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2985 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2986 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2987 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2988 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2989
d9811cfc 2990 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
b455159c
LG		 2991 " .VoltageMode = 0x%02x\n"
2992 " .SnapToDiscrete = 0x%02x\n"
2993 " .NumDiscreteLevels = 0x%02x\n"
2994 " .padding = 0x%02x\n"
2995 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2996 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2997 " .SsFmin = 0x%04x\n"
2998 " .Padding_16 = 0x%04x\n",
2999 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
3000 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
3001 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
3002 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
3003 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
3004 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
3005 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
3006 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
3007 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
3008 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
3009 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
3010
d9811cfc 3011 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
b455159c
LG		 3012 " .VoltageMode = 0x%02x\n"
3013 " .SnapToDiscrete = 0x%02x\n"
3014 " .NumDiscreteLevels = 0x%02x\n"
3015 " .padding = 0x%02x\n"
3016 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3017 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3018 " .SsFmin = 0x%04x\n"
3019 " .Padding_16 = 0x%04x\n",
3020 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
3021 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
3022 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
3023 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
3024 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
3025 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
3026 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
3027 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
3028 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
3029 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
3030 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
3031
d9811cfc 3032 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
b455159c
LG		 3033 " .VoltageMode = 0x%02x\n"
3034 " .SnapToDiscrete = 0x%02x\n"
3035 " .NumDiscreteLevels = 0x%02x\n"
3036 " .padding = 0x%02x\n"
3037 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3038 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3039 " .SsFmin = 0x%04x\n"
3040 " .Padding_16 = 0x%04x\n",
3041 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
3042 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
3043 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
3044 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
3045 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
3046 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
3047 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
3048 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
3049 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
3050 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
3051 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
3052
d9811cfc 3053 dev_info(smu->adev->dev, "FreqTableGfx\n");
b455159c 3054 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
d9811cfc 3055 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
b455159c 3056
d9811cfc 3057 dev_info(smu->adev->dev, "FreqTableVclk\n");
b455159c 3058 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
d9811cfc 3059 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
b455159c 3060
d9811cfc 3061 dev_info(smu->adev->dev, "FreqTableDclk\n");
b455159c 3062 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
d9811cfc 3063 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
b455159c 3064
d9811cfc 3065 dev_info(smu->adev->dev, "FreqTableSocclk\n");
b455159c 3066 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
d9811cfc 3067 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
b455159c 3068
d9811cfc 3069 dev_info(smu->adev->dev, "FreqTableUclk\n");
b455159c 3070 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3071 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
b455159c 3072
d9811cfc 3073 dev_info(smu->adev->dev, "FreqTableFclk\n");
b455159c 3074 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
d9811cfc
EQ		 3075 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
3076
d9811cfc
EQ		 3077 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
3078 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
3079 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
3080 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
3081 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
3082 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
3083 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
3084 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
3085 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
3086
3087 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
b455159c 3088 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3089 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
b455159c 3090
d9811cfc
EQ		 3091 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
3092 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
b455159c 3093
d9811cfc 3094 dev_info(smu->adev->dev, "Mp0clkFreq\n");
b455159c 3095 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc 3096 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
b455159c 3097
d9811cfc 3098 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
b455159c 3099 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
d9811cfc 3100 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
b455159c 3101
d9811cfc 3102 dev_info(smu->adev->dev, "MemVddciVoltage\n");
b455159c 3103 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3104 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
b455159c 3105
d9811cfc 3106 dev_info(smu->adev->dev, "MemMvddVoltage\n");
b455159c 3107 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc
EQ		 3108 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
3109
3110 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
3111 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
3112 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
3113 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
3114 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
3115
3116 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
3117
3118 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
3119 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
3120 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
3121 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
3122 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
3123 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
3124 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
3125 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
3126 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
3127 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
3128 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
3129
3130 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
3131 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
3132 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
3133 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
3134 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
3135 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
3136
3137 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
3138 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
3139 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
3140 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
3141 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
3142
3143 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
b455159c 3144 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
d9811cfc 3145 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
b455159c 3146
d9811cfc
EQ		 3147 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
3148 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
3149 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
3150 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
b455159c 3151
d9811cfc 3152 dev_info(smu->adev->dev, "UclkDpmPstates\n");
b455159c 3153 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
d9811cfc 3154 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
b455159c 3155
d9811cfc
EQ		 3156 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
3157 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
b455159c 3158 pptable->UclkDpmSrcFreqRange.Fmin);
d9811cfc 3159 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
b455159c 3160 pptable->UclkDpmSrcFreqRange.Fmax);
d9811cfc
EQ		 3161 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
3162 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
b455159c 3163 pptable->UclkDpmTargFreqRange.Fmin);
d9811cfc 3164 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
b455159c 3165 pptable->UclkDpmTargFreqRange.Fmax);
d9811cfc
EQ		 3166 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
3167 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
b455159c 3168
d9811cfc 3169 dev_info(smu->adev->dev, "PcieGenSpeed\n");
b455159c 3170 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3171 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
b455159c 3172
d9811cfc 3173 dev_info(smu->adev->dev, "PcieLaneCount\n");
b455159c 3174 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3175 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
b455159c 3176
d9811cfc 3177 dev_info(smu->adev->dev, "LclkFreq\n");
b455159c 3178 for (i = 0; i < NUM_LINK_LEVELS; i++)
d9811cfc 3179 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
b455159c 3180
d9811cfc
EQ		 3181 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
3182 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
b455159c 3183
d9811cfc 3184 dev_info(smu->adev->dev, "FanGain\n");
b455159c 3185 for (i = 0; i < TEMP_COUNT; i++)
d9811cfc
EQ		 3186 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
3187
3188 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
3189 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
3190 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
3191 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
3192 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
3193 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
3194 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
3195 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
3196 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
3197 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
3198 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
3199 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
3200
3201 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
3202 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
3203 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
3204 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
3205
3206 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
3207 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
3208 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
3209 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
3210
3211 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3212 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
3213 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
3214 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
d9811cfc 3215 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3216 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
3217 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
3218 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
d9811cfc 3219 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3220 pptable->dBtcGbGfxPll.a,
3221 pptable->dBtcGbGfxPll.b,
3222 pptable->dBtcGbGfxPll.c);
d9811cfc 3223 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3224 pptable->dBtcGbGfxDfll.a,
3225 pptable->dBtcGbGfxDfll.b,
3226 pptable->dBtcGbGfxDfll.c);
d9811cfc 3227 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3228 pptable->dBtcGbSoc.a,
3229 pptable->dBtcGbSoc.b,
3230 pptable->dBtcGbSoc.c);
d9811cfc 3231 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
b455159c
LG		 3232 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
3233 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
d9811cfc 3234 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
b455159c
LG		 3235 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
3236 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
3237
d9811cfc 3238 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
b455159c 3239 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
d9811cfc 3240 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
b455159c 3241 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
d9811cfc 3242 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
b455159c
LG		 3243 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
3244 }
3245
d9811cfc 3246 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3247 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
3248 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
3249 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
d9811cfc 3250 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3251 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
3252 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
3253 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
3254
d9811cfc
EQ		 3255 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
3256 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
b455159c 3257
d9811cfc
EQ		 3258 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
3259 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
3260 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
3261 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
b455159c 3262
d9811cfc
EQ		 3263 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
3264 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
3265 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
3266 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
b455159c 3267
d9811cfc
EQ		 3268 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
3269 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
b455159c 3270
d9811cfc 3271 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
b455159c 3272 for (i = 0; i < NUM_XGMI_LEVELS; i++)
d9811cfc
EQ		 3273 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
3274 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
3275 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
b455159c 3276
d9811cfc
EQ		 3277 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
3278 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3279 pptable->ReservedEquation0.a,
3280 pptable->ReservedEquation0.b,
3281 pptable->ReservedEquation0.c);
d9811cfc 3282 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3283 pptable->ReservedEquation1.a,
3284 pptable->ReservedEquation1.b,
3285 pptable->ReservedEquation1.c);
d9811cfc 3286 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3287 pptable->ReservedEquation2.a,
3288 pptable->ReservedEquation2.b,
3289 pptable->ReservedEquation2.c);
d9811cfc 3290 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
b455159c
LG		 3291 pptable->ReservedEquation3.a,
3292 pptable->ReservedEquation3.b,
3293 pptable->ReservedEquation3.c);
3294
d9811cfc
EQ		 3295 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3296 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3297 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3298 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3299 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3300 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3301 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3302 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
d9811cfc
EQ		 3303
3304 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3305 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3306 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3307 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3308 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3309 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
b455159c
LG		 3310
3311 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
d9811cfc
EQ		 3312 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3313 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
b455159c 3314 pptable->I2cControllers[i].Enabled);
d9811cfc 3315 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
b455159c 3316 pptable->I2cControllers[i].Speed);
d9811cfc 3317 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
b455159c 3318 pptable->I2cControllers[i].SlaveAddress);
d9811cfc 3319 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
b455159c 3320 pptable->I2cControllers[i].ControllerPort);
d9811cfc 3321 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
b455159c 3322 pptable->I2cControllers[i].ControllerName);
d9811cfc 3323 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
b455159c 3324 pptable->I2cControllers[i].ThermalThrotter);
d9811cfc 3325 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
b455159c 3326 pptable->I2cControllers[i].I2cProtocol);
d9811cfc 3327 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
b455159c
LG		 3328 pptable->I2cControllers[i].PaddingConfig);
3329 }
3330
d9811cfc
EQ		 3331 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3332 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3333 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3334 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3335
3336 dev_info(smu->adev->dev, "Board Parameters:\n");
3337 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3338 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3339 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3340 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3341 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3342 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3343 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3344 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3345
3346 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3347 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3348 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3349
3350 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3351 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3352 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3353
3354 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3355 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3356 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3357
3358 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3359 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3360 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3361
3362 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3363
3364 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3365 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3366 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3367 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3368 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3369 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3370 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3371 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3372 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3373 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3374 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3375 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3376 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3377 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3378 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3379 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3380
3381 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3382 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3383 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3384
3385 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3386 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3387 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3388
f0f3d68e 3389 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
d9811cfc
EQ		 3390 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3391
3392 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3393 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3394 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3395
3396 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3397 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3398 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3399 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3400 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3401
3402 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3403 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3404
3405 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
b455159c 3406 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3407 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3408 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
b455159c 3409 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3410 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3411 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
b455159c 3412 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3413 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3414 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
b455159c 3415 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
d9811cfc
EQ		 3416 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3417
3418 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3419 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3420 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3421 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3422
3423 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3424 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3425 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3426 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3427 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3428 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3429 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3430 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3431 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3432 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3433 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
d9811cfc
EQ		 3434
3435 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3436 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3437 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3438 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3439 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3440 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3441 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3442 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
b455159c
LG		 3443}
3444
5125c96a
AD		 3445static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
3446 struct i2c_msg *msgs, int num)
bc50ca29 3447{
5125c96a 3448 struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
bc50ca29
AD		 3449 struct smu_table_context *smu_table = &adev->smu.smu_table;
3450 struct smu_table *table = &smu_table->driver_table;
5125c96a 3451 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
14df5650
AG		 3452 short available_bytes = MAX_SW_I2C_COMMANDS;
3453 int i, j, r, c, num_done = 0;
5125c96a
AD		 3454 u8 slave;
3455
3456 /* only support a single slave addr per transaction */
3457 slave = msgs[0].addr;
3458 for (i = 0; i < num; i++) {
3459 if (slave != msgs[i].addr)
3460 return -EINVAL;
14df5650
AG		 3461
3462 available_bytes -= msgs[i].len;
3463 if (available_bytes >= 0) {
3464 num_done++;
3465 } else {
3466 /* This message and all the follwing won't be processed */
3467 available_bytes += msgs[i].len;
3468 break;
3469 }
d74a09c8
AD		 3470 }
3471
5125c96a
AD		 3472 req = kzalloc(sizeof(*req), GFP_KERNEL);
3473 if (!req)
3474 return -ENOMEM;
bc50ca29 3475
5125c96a
AD		 3476 req->I2CcontrollerPort = 1;
3477 req->I2CSpeed = I2C_SPEED_FAST_400K;
3478 req->SlaveAddress = slave << 1; /* 8 bit addresses */
14df5650 3479 req->NumCmds = MAX_SW_I2C_COMMANDS - available_bytes;;
bc50ca29 3480
5125c96a 3481 c = 0;
14df5650 3482 for (i = 0; i < num_done; i++) {
5125c96a 3483 struct i2c_msg *msg = &msgs[i];
bc50ca29 3484
14df5650 3485 for (j = 0; j < msg->len; j++) {
5125c96a 3486 SwI2cCmd_t *cmd = &req->SwI2cCmds[c++];
bc50ca29 3487
5125c96a
AD		 3488 if (!(msg[i].flags & I2C_M_RD)) {
3489 /* write */
3490 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
3491 cmd->ReadWriteData = msg->buf[j];
3492 }
14df5650
AG		 3493
3494 /*
3495 * Insert STOP if we are at the last byte of either last
3496 * message for the transaction or the client explicitly
3497 * requires a STOP at this particular message.
3498 */
3499 if ((j == msg->len -1 ) &&
3500 ((i == num_done - 1) || (msg[i].flags & I2C_M_STOP)))
5125c96a 3501 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
6a0a55a2 3502
965ec37c 3503 if ((j == 0) && !(msg[i].flags & I2C_M_NOSTART))
5125c96a
AD		 3504 cmd->CmdConfig |= CMDCONFIG_RESTART_BIT;
3505 }
d74a09c8 3506 }
bc50ca29 3507 mutex_lock(&adev->smu.mutex);
5125c96a 3508 r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
bc50ca29 3509 mutex_unlock(&adev->smu.mutex);
5125c96a
AD		 3510 if (r)
3511 goto fail;
bc50ca29 3512
5125c96a 3513 c = 0;
14df5650 3514 for (i = 0; i < num_done; i++) {
5125c96a 3515 struct i2c_msg *msg = &msgs[i];
bc50ca29 3516
14df5650 3517 for (j = 0; j < msg->len; j++) {
5125c96a 3518 SwI2cCmd_t *cmd = &res->SwI2cCmds[c++];
bc50ca29 3519
5125c96a
AD		 3520 if (msg[i].flags & I2C_M_RD)
3521 msg->buf[j] = cmd->ReadWriteData;
bc50ca29
AD		 3522 }
3523 }
14df5650 3524 r = num_done;
bc50ca29
AD		 3525
3526fail:
5125c96a
AD		 3527 kfree(req);
3528
3529 return r;
bc50ca29
AD		 3530}
3531
3532static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
3533{
3534 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3535}
3536
3537
3538static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
3539 .master_xfer = sienna_cichlid_i2c_xfer,
3540 .functionality = sienna_cichlid_i2c_func,
3541};
3542
35ed2703
AG		 3543static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = {
3544 .max_read_len = MAX_SW_I2C_COMMANDS,
3545 .max_write_len = MAX_SW_I2C_COMMANDS,
3546};
3547
bc50ca29
AD		 3548static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
3549{
3550 struct amdgpu_device *adev = to_amdgpu_device(control);
3551 int res;
3552
bc50ca29 3553 control->owner = THIS_MODULE;
f4322d80 3554 control->class = I2C_CLASS_HWMON;
bc50ca29
AD		 3555 control->dev.parent = &adev->pdev->dev;
3556 control->algo = &sienna_cichlid_i2c_algo;
3557 snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
35ed2703 3558 control->quirks = &sienna_cichlid_i2c_control_quirks;
bc50ca29
AD		 3559
3560 res = i2c_add_adapter(control);
3561 if (res)
3562 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3563
3564 return res;
3565}
3566
3567static void sienna_cichlid_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
3568{
bc50ca29
AD		 3569 i2c_del_adapter(control);
3570}
3571
8ca78a0a
EQ		 3572static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
3573 void **table)
3574{
3575 struct smu_table_context *smu_table = &smu->smu_table;
f06d9511
GS		 3576 struct gpu_metrics_v1_3 *gpu_metrics =
3577 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
b4b0b79d
EQ		 3578 SmuMetricsExternal_t metrics_external;
3579 SmuMetrics_t *metrics =
3580 &(metrics_external.SmuMetrics);
c524c1c9
EQ		 3581 struct amdgpu_device *adev = smu->adev;
3582 uint32_t smu_version;
8ca78a0a
EQ		 3583 int ret = 0;
3584
fceafc9b 3585 ret = smu_cmn_get_metrics_table(smu,
b4b0b79d 3586 &metrics_external,
fceafc9b 3587 true);
60ae4d67 3588 if (ret)
8ca78a0a 3589 return ret;
8ca78a0a 3590
f06d9511 3591 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
8ca78a0a 3592
b4b0b79d
EQ		 3593 gpu_metrics->temperature_edge = metrics->TemperatureEdge;
3594 gpu_metrics->temperature_hotspot = metrics->TemperatureHotspot;
3595 gpu_metrics->temperature_mem = metrics->TemperatureMem;
3596 gpu_metrics->temperature_vrgfx = metrics->TemperatureVrGfx;
3597 gpu_metrics->temperature_vrsoc = metrics->TemperatureVrSoc;
3598 gpu_metrics->temperature_vrmem = metrics->TemperatureVrMem0;
8ca78a0a 3599
b4b0b79d
EQ		 3600 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity;
3601 gpu_metrics->average_umc_activity = metrics->AverageUclkActivity;
3602 gpu_metrics->average_mm_activity = metrics->VcnActivityPercentage;
8ca78a0a 3603
b4b0b79d
EQ		 3604 gpu_metrics->average_socket_power = metrics->AverageSocketPower;
3605 gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
8ca78a0a 3606
b4b0b79d
EQ		 3607 if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
3608 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
8ca78a0a 3609 else
b4b0b79d
EQ		 3610 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs;
3611 gpu_metrics->average_uclk_frequency = metrics->AverageUclkFrequencyPostDs;
3612 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency;
3613 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency;
3614 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency;
3615 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency;
3616
3617 gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK];
3618 gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK];
3619 gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];
3620 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0];
3621 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0];
3622 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1];
3623 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1];
3624
3625 gpu_metrics->throttle_status = metrics->ThrottlerStatus;
f06d9511
GS		 3626 gpu_metrics->indep_throttle_status =
3627 smu_cmn_get_indep_throttler_status(metrics->ThrottlerStatus,
3628 sienna_cichlid_throttler_map);
b4b0b79d
EQ		 3629
3630 gpu_metrics->current_fan_speed = metrics->CurrFanSpeed;
8ca78a0a 3631
c524c1c9
EQ		 3632 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
3633 if (ret)
3634 return ret;
3635
3636 if (((adev->asic_type == CHIP_SIENNA_CICHLID) && smu_version > 0x003A1E00) ||
3637 ((adev->asic_type == CHIP_NAVY_FLOUNDER) && smu_version > 0x00410400)) {
3638 gpu_metrics->pcie_link_width = metrics->PcieWidth;
3639 gpu_metrics->pcie_link_speed = link_speed[metrics->PcieRate];
3640 } else {
3641 gpu_metrics->pcie_link_width =
3642 smu_v11_0_get_current_pcie_link_width(smu);
3643 gpu_metrics->pcie_link_speed =
3644 smu_v11_0_get_current_pcie_link_speed(smu);
3645 }
8ca78a0a 3646
de4b7cd8
KW		 3647 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3648
8ca78a0a
EQ		 3649 *table = (void *)gpu_metrics;
3650
f06d9511 3651 return sizeof(struct gpu_metrics_v1_3);
8ca78a0a 3652}
bc50ca29 3653
05f39286
EQ		 3654static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
3655{
b804a75d
EQ		 3656 struct smu_table_context *table_context = &smu->smu_table;
3657 PPTable_t *smc_pptable = table_context->driver_pptable;
3658
3659 /*
3660 * Skip the MGpuFanBoost setting for those ASICs
3661 * which do not support it
3662 */
3663 if (!smc_pptable->MGpuFanBoostLimitRpm)
3664 return 0;
3665
05f39286
EQ		 3666 return smu_cmn_send_smc_msg_with_param(smu,
3667 SMU_MSG_SetMGpuFanBoostLimitRpm,
3668 0,
3669 NULL);
3670}
3671
76c71f00
EQ		 3672static int sienna_cichlid_gpo_control(struct smu_context *smu,
3673 bool enablement)
3674{
ac7804bb 3675 uint32_t smu_version;
76c71f00
EQ		 3676 int ret = 0;
3677
ac7804bb 3678
76c71f00 3679 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
ac7804bb
EQ		 3680 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
3681 if (ret)
3682 return ret;
3683
3684 if (enablement) {
3685 if (smu_version < 0x003a2500) {
3686 ret = smu_cmn_send_smc_msg_with_param(smu,
3687 SMU_MSG_SetGpoFeaturePMask,
3688 GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
3689 NULL);
3690 } else {
3691 ret = smu_cmn_send_smc_msg_with_param(smu,
3692 SMU_MSG_DisallowGpo,
3693 0,
3694 NULL);
3695 }
3696 } else {
3697 if (smu_version < 0x003a2500) {
3698 ret = smu_cmn_send_smc_msg_with_param(smu,
3699 SMU_MSG_SetGpoFeaturePMask,
3700 0,
3701 NULL);
3702 } else {
3703 ret = smu_cmn_send_smc_msg_with_param(smu,
3704 SMU_MSG_DisallowGpo,
3705 1,
3706 NULL);
3707 }
3708 }
76c71f00
EQ		 3709 }
3710
3711 return ret;
3712}
d7f52e29
EQ		 3713
3714static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
3715{
3716 uint32_t smu_version;
3717 int ret = 0;
3718
3719 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
3720 if (ret)
3721 return ret;
3722
3723 /*
3724 * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
3725 * onwards PMFWs.
3726 */
3727 if (smu_version < 0x003A2D00)
3728 return 0;
3729
3730 return smu_cmn_send_smc_msg_with_param(smu,
3731 SMU_MSG_Enable2ndUSB20Port,
3732 smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
3733 1 : 0,
3734 NULL);
3735}
3736
3737static int sienna_cichlid_system_features_control(struct smu_context *smu,
3738 bool en)
3739{
3740 int ret = 0;
3741
3742 if (en) {
3743 ret = sienna_cichlid_notify_2nd_usb20_port(smu);
3744 if (ret)
3745 return ret;
3746 }
3747
3748 return smu_v11_0_system_features_control(smu, en);
3749}
3750
1689fca0
EQ		 3751static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
3752 enum pp_mp1_state mp1_state)
3753{
9113a0fb
GC		 3754 int ret;
3755
1689fca0
EQ		 3756 switch (mp1_state) {
3757 case PP_MP1_STATE_UNLOAD:
9113a0fb
GC		 3758 ret = smu_cmn_set_mp1_state(smu, mp1_state);
3759 break;
1689fca0 3760 default:
9113a0fb
GC		 3761 /* Ignore others */
3762 ret = 0;
1689fca0
EQ		 3763 }
3764
9113a0fb 3765 return ret;
1689fca0
EQ		 3766}
3767
b455159c 3768static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
b455159c
LG		 3769 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
3770 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
f6b4b4a1 3771 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
6fb176a7 3772 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
bc50ca29
AD		 3773 .i2c_init = sienna_cichlid_i2c_control_init,
3774 .i2c_fini = sienna_cichlid_i2c_control_fini,
b455159c
LG		 3775 .print_clk_levels = sienna_cichlid_print_clk_levels,
3776 .force_clk_levels = sienna_cichlid_force_clk_levels,
3777 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
b455159c
LG		 3778 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
3779 .display_config_changed = sienna_cichlid_display_config_changed,
3780 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
b455159c 3781 .is_dpm_running = sienna_cichlid_is_dpm_running,
4954a76a 3782 .get_fan_speed_percent = sienna_cichlid_get_fan_speed_percent,
b455159c
LG		 3783 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
3784 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
b455159c
LG		 3785 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
3786 .read_sensor = sienna_cichlid_read_sensor,
3787 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
b2785e25 3788 .set_performance_level = smu_v11_0_set_performance_level,
b455159c
LG		 3789 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
3790 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
3791 .get_power_limit = sienna_cichlid_get_power_limit,
08ccfe08 3792 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
b455159c
LG		 3793 .dump_pptable = sienna_cichlid_dump_pptable,
3794 .init_microcode = smu_v11_0_init_microcode,
3795 .load_microcode = smu_v11_0_load_microcode,
c1b353b7 3796 .init_smc_tables = sienna_cichlid_init_smc_tables,
b455159c
LG		 3797 .fini_smc_tables = smu_v11_0_fini_smc_tables,
3798 .init_power = smu_v11_0_init_power,
3799 .fini_power = smu_v11_0_fini_power,
3800 .check_fw_status = smu_v11_0_check_fw_status,
4a13b4ce 3801 .setup_pptable = sienna_cichlid_setup_pptable,
b455159c 3802 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
b455159c 3803 .check_fw_version = smu_v11_0_check_fw_version,
caad2613 3804 .write_pptable = smu_cmn_write_pptable,
b455159c
LG		 3805 .set_driver_table_location = smu_v11_0_set_driver_table_location,
3806 .set_tool_table_location = smu_v11_0_set_tool_table_location,
3807 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
d7f52e29 3808 .system_features_control = sienna_cichlid_system_features_control,
66c86828
EQ		 3809 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
3810 .send_smc_msg = smu_cmn_send_smc_msg,
31157341 3811 .init_display_count = NULL,
b455159c 3812 .set_allowed_mask = smu_v11_0_set_allowed_mask,
28251d72 3813 .get_enabled_mask = smu_cmn_get_enabled_mask,
b4bb3aaf 3814 .feature_is_enabled = smu_cmn_feature_is_enabled,
af5ba6d2 3815 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
31157341 3816 .notify_display_change = NULL,
b455159c 3817 .set_power_limit = smu_v11_0_set_power_limit,
b455159c
LG		 3818 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
3819 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
3820 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
ce63d8f8 3821 .set_min_dcef_deep_sleep = NULL,
b455159c
LG		 3822 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
3823 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
3824 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
cd305137 3825 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
b455159c
LG		 3826 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
3827 .gfx_off_control = smu_v11_0_gfx_off_control,
3828 .register_irq_handler = smu_v11_0_register_irq_handler,
3829 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
3830 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
9fd4781b 3831 .baco_is_support = smu_v11_0_baco_is_support,
b455159c
LG		 3832 .baco_get_state = smu_v11_0_baco_get_state,
3833 .baco_set_state = smu_v11_0_baco_set_state,
13d75ead
EQ		 3834 .baco_enter = sienna_cichlid_baco_enter,
3835 .baco_exit = sienna_cichlid_baco_exit,
ea8139d8
WS		 3836 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
3837 .mode1_reset = smu_v11_0_mode1_reset,
258d290c 3838 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
10e96d89 3839 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
aa75fa34 3840 .set_default_od_settings = sienna_cichlid_set_default_od_settings,
37a58f69 3841 .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
66b8a9c0 3842 .run_btc = sienna_cichlid_run_btc,
18a4b3de 3843 .set_power_source = smu_v11_0_set_power_source,
7dbf7805
EQ		 3844 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3845 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
8ca78a0a 3846 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
05f39286 3847 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
e988026f 3848 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
5ce99853 3849 .deep_sleep_control = smu_v11_0_deep_sleep_control,
3204ff3e 3850 .get_fan_parameters = sienna_cichlid_get_fan_parameters,
234676d6 3851 .interrupt_work = smu_v11_0_interrupt_work,
76c71f00 3852 .gpo_control = sienna_cichlid_gpo_control,
1689fca0 3853 .set_mp1_state = sienna_cichlid_set_mp1_state,
b455159c
LG		 3854};
3855
3856void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
3857{
3858 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
6c339f37
EQ		 3859 smu->message_map = sienna_cichlid_message_map;
3860 smu->clock_map = sienna_cichlid_clk_map;
3861 smu->feature_map = sienna_cichlid_feature_mask_map;
3862 smu->table_map = sienna_cichlid_table_map;
3863 smu->pwr_src_map = sienna_cichlid_pwr_src_map;
3864 smu->workload_map = sienna_cichlid_workload_map;
b455159c 3865}
Linux 6.x block layer and io_uring tree(s)