[linux-2.6-block.git] / drivers / gpu / drm / amd / pm / powerplay / hwmgr / vega20_baco.c

/*
 * Copyright 2018 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include "amdgpu.h"
#include "soc15.h"
#include "soc15_hw_ip.h"
#include "soc15_common.h"
#include "vega20_inc.h"
#include "vega20_ppsmc.h"
#include "vega20_baco.h"
#include "vega20_smumgr.h"

#include "amdgpu_ras.h"

static const struct soc15_baco_cmd_entry clean_baco_tbl[] = {
	{CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_6), 0, 0, 0, 0},
	{CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_7), 0, 0, 0, 0},
};

bool vega20_get_bamaco_support(struct pp_hwmgr *hwmgr)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
	uint32_t reg;

	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
		return false;

	if (((RREG32(0x17569) & 0x20000000) >> 29) == 0x1) {
		reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);

		if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
			return true;
	}

	return false;
}

int vega20_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
	uint32_t reg;

	reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);

	if (reg & BACO_CNTL__BACO_MODE_MASK)
		/* gfx has already entered BACO state */
		*state = BACO_STATE_IN;
	else
		*state = BACO_STATE_OUT;
	return 0;
}

int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
	enum BACO_STATE cur_state;
	uint32_t data;

	vega20_baco_get_state(hwmgr, &cur_state);

	if (cur_state == state)
		/* aisc already in the target state */
		return 0;

	if (state == BACO_STATE_IN) {
		if (!ras || !adev->ras_enabled) {
			data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
			data |= 0x80000000;
			WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);

			if (smum_send_msg_to_smc_with_parameter(hwmgr,
					PPSMC_MSG_EnterBaco, 0, NULL))
				return -EINVAL;
		} else {
			if (smum_send_msg_to_smc_with_parameter(hwmgr,
					PPSMC_MSG_EnterBaco, 1, NULL))
				return -EINVAL;
		}

	} else if (state == BACO_STATE_OUT) {
		if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ExitBaco, NULL))
			return -EINVAL;
		if (!soc15_baco_program_registers(hwmgr, clean_baco_tbl,
						     ARRAY_SIZE(clean_baco_tbl)))
			return -EINVAL;
	}

	return 0;
}

int vega20_baco_apply_vdci_flush_workaround(struct pp_hwmgr *hwmgr)
{
	int ret = 0;

	ret = vega20_set_pptable_driver_address(hwmgr);
	if (ret)
		return ret;

	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_BacoWorkAroundFlushVDCI, NULL);
}
Commit	Line	Data
94b94438 AD	1	/*
	2	* Copyright 2018 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
3177b3c5 JQ	23	#include "amdgpu.h"
	24	#include "soc15.h"
	25	#include "soc15_hw_ip.h"
	26	#include "soc15_common.h"
	27	#include "vega20_inc.h"
	28	#include "vega20_ppsmc.h"
	29	#include "vega20_baco.h"
0c5ccf14	30	#include "vega20_smumgr.h"
3177b3c5	31
df9331e5	32	#include "amdgpu_ras.h"
3177b3c5	33
ffa702d2	34	static const struct soc15_baco_cmd_entry clean_baco_tbl[] = {
3177b3c5 JQ	35	{CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_6), 0, 0, 0, 0},
	36	{CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_7), 0, 0, 0, 0},
	37	};
	38
1b199594	39	bool vega20_get_bamaco_support(struct pp_hwmgr *hwmgr)
3177b3c5 JQ	40	{
	41	struct amdgpu_device adev = (struct amdgpu_device )(hwmgr->adev);
	42	uint32_t reg;
	43
3177b3c5	44	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
fbbcb3f2	45	return false;
3177b3c5 JQ	46
	47	if (((RREG32(0x17569) & 0x20000000) >> 29) == 0x1) {
	48	reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);
	49
	50	if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
fbbcb3f2	51	return true;
3177b3c5 JQ	52	}
3177b3c5 JQ	53
fbbcb3f2	54	return false;
3177b3c5 JQ	55	}
	56
	57	int vega20_baco_get_state(struct pp_hwmgr hwmgr, enum BACO_STATE state)
	58	{
	59	struct amdgpu_device adev = (struct amdgpu_device )(hwmgr->adev);
	60	uint32_t reg;
	61
	62	reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);
	63
	64	if (reg & BACO_CNTL__BACO_MODE_MASK)
	65	/* gfx has already entered BACO state */
	66	*state = BACO_STATE_IN;
	67	else
	68	*state = BACO_STATE_OUT;
	69	return 0;
	70	}
	71
	72	int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
	73	{
	74	struct amdgpu_device adev = (struct amdgpu_device )(hwmgr->adev);
df9331e5	75	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3177b3c5 JQ	76	enum BACO_STATE cur_state;
	77	uint32_t data;
	78
	79	vega20_baco_get_state(hwmgr, &cur_state);
	80
	81	if (cur_state == state)
	82	/* aisc already in the target state */
	83	return 0;
	84
	85	if (state == BACO_STATE_IN) {
8ab0d6f0	86	if (!ras \|\| !adev->ras_enabled) {
df9331e5 LM	87	data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
	88	data \|= 0x80000000;
	89	WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
3177b3c5	90
ffa702d2	91	if (smum_send_msg_to_smc_with_parameter(hwmgr,
a0ec2256	92	PPSMC_MSG_EnterBaco, 0, NULL))
16562d32 LM	93	return -EINVAL;
16562d32 LM	94	} else {
ffa702d2	95	if (smum_send_msg_to_smc_with_parameter(hwmgr,
a0ec2256	96	PPSMC_MSG_EnterBaco, 1, NULL))
16562d32 LM	97	return -EINVAL;
16562d32 LM	98	}
3177b3c5 JQ	99
3177b3c5 JQ	100	} else if (state == BACO_STATE_OUT) {
a0ec2256	101	if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ExitBaco, NULL))
41d3ae4b	102	return -EINVAL;
3177b3c5 JQ	103	if (!soc15_baco_program_registers(hwmgr, clean_baco_tbl,
3177b3c5 JQ	104	ARRAY_SIZE(clean_baco_tbl)))
41d3ae4b	105	return -EINVAL;
3177b3c5 JQ	106	}
	107
	108	return 0;
	109	}
0c5ccf14 EQ	110
	111	int vega20_baco_apply_vdci_flush_workaround(struct pp_hwmgr *hwmgr)
	112	{
	113	int ret = 0;
	114
	115	ret = vega20_set_pptable_driver_address(hwmgr);
	116	if (ret)
	117	return ret;
	118
a0ec2256	119	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_BacoWorkAroundFlushVDCI, NULL);
0c5ccf14	120	}