Commit | Line | Data |
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d38ceaf9 | 1 | /* |
9ce6aae1 AD |
2 | * Copyright 2017 Advanced Micro Devices, Inc. |
3 | * | |
d38ceaf9 AD |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Rafał Miłecki <zajec5@gmail.com> | |
23 | * Alex Deucher <alexdeucher@gmail.com> | |
24 | */ | |
fdf2f6c5 | 25 | |
d38ceaf9 AD |
26 | #include "amdgpu.h" |
27 | #include "amdgpu_drv.h" | |
28 | #include "amdgpu_pm.h" | |
29 | #include "amdgpu_dpm.h" | |
30 | #include "atom.h" | |
fdf2f6c5 | 31 | #include <linux/pci.h> |
d38ceaf9 AD |
32 | #include <linux/hwmon.h> |
33 | #include <linux/hwmon-sysfs.h> | |
ddf74e79 | 34 | #include <linux/nospec.h> |
b9a9294b | 35 | #include <linux/pm_runtime.h> |
517cb957 | 36 | #include <asm/processor.h> |
1b5708ff | 37 | |
2adc1156 EQ |
38 | static const struct hwmon_temp_label { |
39 | enum PP_HWMON_TEMP channel; | |
40 | const char *label; | |
41 | } temp_label[] = { | |
42 | {PP_TEMP_EDGE, "edge"}, | |
43 | {PP_TEMP_JUNCTION, "junction"}, | |
44 | {PP_TEMP_MEM, "mem"}, | |
45 | }; | |
46 | ||
3867e370 DP |
47 | const char * const amdgpu_pp_profile_name[] = { |
48 | "BOOTUP_DEFAULT", | |
49 | "3D_FULL_SCREEN", | |
50 | "POWER_SAVING", | |
51 | "VIDEO", | |
52 | "VR", | |
53 | "COMPUTE", | |
334682ae KF |
54 | "CUSTOM", |
55 | "WINDOW_3D", | |
31865e96 PY |
56 | "CAPPED", |
57 | "UNCAPPED", | |
3867e370 DP |
58 | }; |
59 | ||
ca8d40ca AD |
60 | /** |
61 | * DOC: power_dpm_state | |
62 | * | |
dc85db25 AD |
63 | * The power_dpm_state file is a legacy interface and is only provided for |
64 | * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting | |
65 | * certain power related parameters. The file power_dpm_state is used for this. | |
ca8d40ca | 66 | * It accepts the following arguments: |
dc85db25 | 67 | * |
ca8d40ca | 68 | * - battery |
dc85db25 | 69 | * |
ca8d40ca | 70 | * - balanced |
dc85db25 | 71 | * |
ca8d40ca AD |
72 | * - performance |
73 | * | |
74 | * battery | |
75 | * | |
76 | * On older GPUs, the vbios provided a special power state for battery | |
77 | * operation. Selecting battery switched to this state. This is no | |
78 | * longer provided on newer GPUs so the option does nothing in that case. | |
79 | * | |
80 | * balanced | |
81 | * | |
82 | * On older GPUs, the vbios provided a special power state for balanced | |
83 | * operation. Selecting balanced switched to this state. This is no | |
84 | * longer provided on newer GPUs so the option does nothing in that case. | |
85 | * | |
86 | * performance | |
87 | * | |
88 | * On older GPUs, the vbios provided a special power state for performance | |
89 | * operation. Selecting performance switched to this state. This is no | |
90 | * longer provided on newer GPUs so the option does nothing in that case. | |
91 | * | |
92 | */ | |
93 | ||
4e01847c KW |
94 | static ssize_t amdgpu_get_power_dpm_state(struct device *dev, |
95 | struct device_attribute *attr, | |
96 | char *buf) | |
d38ceaf9 AD |
97 | { |
98 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 99 | struct amdgpu_device *adev = drm_to_adev(ddev); |
1b5708ff | 100 | enum amd_pm_state_type pm; |
b9a9294b | 101 | int ret; |
1b5708ff | 102 | |
53b3f8f4 | 103 | if (amdgpu_in_reset(adev)) |
48b270bb | 104 | return -EPERM; |
d2ae842d AD |
105 | if (adev->in_suspend && !adev->in_runpm) |
106 | return -EPERM; | |
48b270bb | 107 | |
b9a9294b | 108 | ret = pm_runtime_get_sync(ddev->dev); |
66429300 AD |
109 | if (ret < 0) { |
110 | pm_runtime_put_autosuspend(ddev->dev); | |
b9a9294b | 111 | return ret; |
66429300 | 112 | } |
b9a9294b | 113 | |
79c65f3f | 114 | amdgpu_dpm_get_current_power_state(adev, &pm); |
d38ceaf9 | 115 | |
b9a9294b AD |
116 | pm_runtime_mark_last_busy(ddev->dev); |
117 | pm_runtime_put_autosuspend(ddev->dev); | |
118 | ||
a9ca9bb3 TT |
119 | return sysfs_emit(buf, "%s\n", |
120 | (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : | |
121 | (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); | |
d38ceaf9 AD |
122 | } |
123 | ||
4e01847c KW |
124 | static ssize_t amdgpu_set_power_dpm_state(struct device *dev, |
125 | struct device_attribute *attr, | |
126 | const char *buf, | |
127 | size_t count) | |
d38ceaf9 AD |
128 | { |
129 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 130 | struct amdgpu_device *adev = drm_to_adev(ddev); |
1b5708ff | 131 | enum amd_pm_state_type state; |
b9a9294b | 132 | int ret; |
d38ceaf9 | 133 | |
53b3f8f4 | 134 | if (amdgpu_in_reset(adev)) |
48b270bb | 135 | return -EPERM; |
d2ae842d AD |
136 | if (adev->in_suspend && !adev->in_runpm) |
137 | return -EPERM; | |
48b270bb | 138 | |
d38ceaf9 | 139 | if (strncmp("battery", buf, strlen("battery")) == 0) |
1b5708ff | 140 | state = POWER_STATE_TYPE_BATTERY; |
d38ceaf9 | 141 | else if (strncmp("balanced", buf, strlen("balanced")) == 0) |
1b5708ff | 142 | state = POWER_STATE_TYPE_BALANCED; |
d38ceaf9 | 143 | else if (strncmp("performance", buf, strlen("performance")) == 0) |
1b5708ff | 144 | state = POWER_STATE_TYPE_PERFORMANCE; |
27414cd4 AD |
145 | else |
146 | return -EINVAL; | |
d38ceaf9 | 147 | |
b9a9294b | 148 | ret = pm_runtime_get_sync(ddev->dev); |
66429300 AD |
149 | if (ret < 0) { |
150 | pm_runtime_put_autosuspend(ddev->dev); | |
b9a9294b | 151 | return ret; |
66429300 | 152 | } |
b9a9294b | 153 | |
79c65f3f | 154 | amdgpu_dpm_set_power_state(adev, state); |
1b5708ff | 155 | |
b9a9294b AD |
156 | pm_runtime_mark_last_busy(ddev->dev); |
157 | pm_runtime_put_autosuspend(ddev->dev); | |
158 | ||
d38ceaf9 AD |
159 | return count; |
160 | } | |
161 | ||
8567f681 AD |
162 | |
163 | /** | |
164 | * DOC: power_dpm_force_performance_level | |
165 | * | |
166 | * The amdgpu driver provides a sysfs API for adjusting certain power | |
167 | * related parameters. The file power_dpm_force_performance_level is | |
168 | * used for this. It accepts the following arguments: | |
dc85db25 | 169 | * |
8567f681 | 170 | * - auto |
dc85db25 | 171 | * |
8567f681 | 172 | * - low |
dc85db25 | 173 | * |
8567f681 | 174 | * - high |
dc85db25 | 175 | * |
8567f681 | 176 | * - manual |
dc85db25 | 177 | * |
8567f681 | 178 | * - profile_standard |
dc85db25 | 179 | * |
8567f681 | 180 | * - profile_min_sclk |
dc85db25 | 181 | * |
8567f681 | 182 | * - profile_min_mclk |
dc85db25 | 183 | * |
8567f681 AD |
184 | * - profile_peak |
185 | * | |
186 | * auto | |
187 | * | |
188 | * When auto is selected, the driver will attempt to dynamically select | |
189 | * the optimal power profile for current conditions in the driver. | |
190 | * | |
191 | * low | |
192 | * | |
193 | * When low is selected, the clocks are forced to the lowest power state. | |
194 | * | |
195 | * high | |
196 | * | |
197 | * When high is selected, the clocks are forced to the highest power state. | |
198 | * | |
199 | * manual | |
200 | * | |
201 | * When manual is selected, the user can manually adjust which power states | |
202 | * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk, | |
203 | * and pp_dpm_pcie files and adjust the power state transition heuristics | |
204 | * via the pp_power_profile_mode sysfs file. | |
205 | * | |
206 | * profile_standard | |
207 | * profile_min_sclk | |
208 | * profile_min_mclk | |
209 | * profile_peak | |
210 | * | |
211 | * When the profiling modes are selected, clock and power gating are | |
212 | * disabled and the clocks are set for different profiling cases. This | |
213 | * mode is recommended for profiling specific work loads where you do | |
214 | * not want clock or power gating for clock fluctuation to interfere | |
215 | * with your results. profile_standard sets the clocks to a fixed clock | |
216 | * level which varies from asic to asic. profile_min_sclk forces the sclk | |
217 | * to the lowest level. profile_min_mclk forces the mclk to the lowest level. | |
218 | * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels. | |
219 | * | |
220 | */ | |
221 | ||
4e01847c KW |
222 | static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev, |
223 | struct device_attribute *attr, | |
224 | char *buf) | |
d38ceaf9 AD |
225 | { |
226 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 227 | struct amdgpu_device *adev = drm_to_adev(ddev); |
cd4d7464 | 228 | enum amd_dpm_forced_level level = 0xff; |
b9a9294b | 229 | int ret; |
d38ceaf9 | 230 | |
53b3f8f4 | 231 | if (amdgpu_in_reset(adev)) |
48b270bb | 232 | return -EPERM; |
d2ae842d AD |
233 | if (adev->in_suspend && !adev->in_runpm) |
234 | return -EPERM; | |
48b270bb | 235 | |
b9a9294b | 236 | ret = pm_runtime_get_sync(ddev->dev); |
66429300 AD |
237 | if (ret < 0) { |
238 | pm_runtime_put_autosuspend(ddev->dev); | |
b9a9294b | 239 | return ret; |
66429300 | 240 | } |
0c67df48 | 241 | |
79c65f3f | 242 | level = amdgpu_dpm_get_performance_level(adev); |
cd4d7464 | 243 | |
b9a9294b AD |
244 | pm_runtime_mark_last_busy(ddev->dev); |
245 | pm_runtime_put_autosuspend(ddev->dev); | |
246 | ||
a9ca9bb3 TT |
247 | return sysfs_emit(buf, "%s\n", |
248 | (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" : | |
249 | (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" : | |
250 | (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" : | |
251 | (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" : | |
252 | (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" : | |
253 | (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" : | |
254 | (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" : | |
255 | (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" : | |
256 | (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" : | |
257 | "unknown"); | |
d38ceaf9 AD |
258 | } |
259 | ||
4e01847c KW |
260 | static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev, |
261 | struct device_attribute *attr, | |
262 | const char *buf, | |
263 | size_t count) | |
d38ceaf9 AD |
264 | { |
265 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 266 | struct amdgpu_device *adev = drm_to_adev(ddev); |
e5d03ac2 | 267 | enum amd_dpm_forced_level level; |
d38ceaf9 AD |
268 | int ret = 0; |
269 | ||
53b3f8f4 | 270 | if (amdgpu_in_reset(adev)) |
48b270bb | 271 | return -EPERM; |
d2ae842d AD |
272 | if (adev->in_suspend && !adev->in_runpm) |
273 | return -EPERM; | |
48b270bb | 274 | |
d38ceaf9 | 275 | if (strncmp("low", buf, strlen("low")) == 0) { |
e5d03ac2 | 276 | level = AMD_DPM_FORCED_LEVEL_LOW; |
d38ceaf9 | 277 | } else if (strncmp("high", buf, strlen("high")) == 0) { |
e5d03ac2 | 278 | level = AMD_DPM_FORCED_LEVEL_HIGH; |
d38ceaf9 | 279 | } else if (strncmp("auto", buf, strlen("auto")) == 0) { |
e5d03ac2 | 280 | level = AMD_DPM_FORCED_LEVEL_AUTO; |
f3898ea1 | 281 | } else if (strncmp("manual", buf, strlen("manual")) == 0) { |
e5d03ac2 | 282 | level = AMD_DPM_FORCED_LEVEL_MANUAL; |
570272d2 RZ |
283 | } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) { |
284 | level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT; | |
285 | } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) { | |
286 | level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD; | |
287 | } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) { | |
288 | level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK; | |
289 | } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) { | |
290 | level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK; | |
291 | } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) { | |
292 | level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; | |
6be64246 LL |
293 | } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) { |
294 | level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM; | |
570272d2 | 295 | } else { |
b9a9294b | 296 | return -EINVAL; |
d38ceaf9 | 297 | } |
1b5708ff | 298 | |
b9a9294b | 299 | ret = pm_runtime_get_sync(ddev->dev); |
66429300 AD |
300 | if (ret < 0) { |
301 | pm_runtime_put_autosuspend(ddev->dev); | |
b9a9294b | 302 | return ret; |
66429300 | 303 | } |
b9a9294b | 304 | |
8cda7a4f | 305 | mutex_lock(&adev->pm.stable_pstate_ctx_lock); |
79c65f3f EQ |
306 | if (amdgpu_dpm_force_performance_level(adev, level)) { |
307 | pm_runtime_mark_last_busy(ddev->dev); | |
308 | pm_runtime_put_autosuspend(ddev->dev); | |
8cda7a4f | 309 | mutex_unlock(&adev->pm.stable_pstate_ctx_lock); |
79c65f3f | 310 | return -EINVAL; |
d38ceaf9 | 311 | } |
8cda7a4f AD |
312 | /* override whatever a user ctx may have set */ |
313 | adev->pm.stable_pstate_ctx = NULL; | |
314 | mutex_unlock(&adev->pm.stable_pstate_ctx_lock); | |
79c65f3f | 315 | |
b9a9294b AD |
316 | pm_runtime_mark_last_busy(ddev->dev); |
317 | pm_runtime_put_autosuspend(ddev->dev); | |
570272d2 | 318 | |
f1403342 | 319 | return count; |
d38ceaf9 AD |
320 | } |
321 | ||
f3898ea1 EH |
322 | static ssize_t amdgpu_get_pp_num_states(struct device *dev, |
323 | struct device_attribute *attr, | |
324 | char *buf) | |
325 | { | |
326 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 327 | struct amdgpu_device *adev = drm_to_adev(ddev); |
f3898ea1 | 328 | struct pp_states_info data; |
09b6744c DP |
329 | uint32_t i; |
330 | int buf_len, ret; | |
f3898ea1 | 331 | |
53b3f8f4 | 332 | if (amdgpu_in_reset(adev)) |
48b270bb | 333 | return -EPERM; |
d2ae842d AD |
334 | if (adev->in_suspend && !adev->in_runpm) |
335 | return -EPERM; | |
48b270bb | 336 | |
b9a9294b | 337 | ret = pm_runtime_get_sync(ddev->dev); |
66429300 AD |
338 | if (ret < 0) { |
339 | pm_runtime_put_autosuspend(ddev->dev); | |
b9a9294b | 340 | return ret; |
66429300 | 341 | } |
b9a9294b | 342 | |
79c65f3f | 343 | if (amdgpu_dpm_get_pp_num_states(adev, &data)) |
6f81b2d0 | 344 | memset(&data, 0, sizeof(data)); |
f3898ea1 | 345 | |
b9a9294b AD |
346 | pm_runtime_mark_last_busy(ddev->dev); |
347 | pm_runtime_put_autosuspend(ddev->dev); | |
348 | ||
09b6744c | 349 | buf_len = sysfs_emit(buf, "states: %d\n", data.nums); |
f3898ea1 | 350 | for (i = 0; i < data.nums; i++) |
09b6744c | 351 | buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i, |
f3898ea1 EH |
352 | (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" : |
353 | (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" : | |
354 | (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" : | |
355 | (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default"); | |
356 | ||
357 | return buf_len; | |
358 | } | |
359 | ||
360 | static ssize_t amdgpu_get_pp_cur_state(struct device *dev, | |
361 | struct device_attribute *attr, | |
362 | char *buf) | |
363 | { | |
364 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 365 | struct amdgpu_device *adev = drm_to_adev(ddev); |
2b24c199 | 366 | struct pp_states_info data = {0}; |
f3898ea1 | 367 | enum amd_pm_state_type pm = 0; |
ea2d0bf8 | 368 | int i = 0, ret = 0; |
f3898ea1 | 369 | |
53b3f8f4 | 370 | if (amdgpu_in_reset(adev)) |
48b270bb | 371 | return -EPERM; |
d2ae842d AD |
372 | if (adev->in_suspend && !adev->in_runpm) |
373 | return -EPERM; | |
48b270bb | 374 | |
b9a9294b | 375 | ret = pm_runtime_get_sync(ddev->dev); |
66429300 AD |
376 | if (ret < 0) { |
377 | pm_runtime_put_autosuspend(ddev->dev); | |
b9a9294b | 378 | return ret; |
66429300 | 379 | } |
b9a9294b | 380 | |
79c65f3f EQ |
381 | amdgpu_dpm_get_current_power_state(adev, &pm); |
382 | ||
383 | ret = amdgpu_dpm_get_pp_num_states(adev, &data); | |
f3898ea1 | 384 | |
b9a9294b AD |
385 | pm_runtime_mark_last_busy(ddev->dev); |
386 | pm_runtime_put_autosuspend(ddev->dev); | |
387 | ||
79c65f3f EQ |
388 | if (ret) |
389 | return ret; | |
390 | ||
ea2d0bf8 KW |
391 | for (i = 0; i < data.nums; i++) { |
392 | if (pm == data.states[i]) | |
393 | break; | |
f3898ea1 EH |
394 | } |
395 | ||
ea2d0bf8 KW |
396 | if (i == data.nums) |
397 | i = -EINVAL; | |
398 | ||
a9ca9bb3 | 399 | return sysfs_emit(buf, "%d\n", i); |
f3898ea1 EH |
400 | } |
401 | ||
402 | static ssize_t amdgpu_get_pp_force_state(struct device *dev, | |
403 | struct device_attribute *attr, | |
404 | char *buf) | |
405 | { | |
406 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 407 | struct amdgpu_device *adev = drm_to_adev(ddev); |
f3898ea1 | 408 | |
53b3f8f4 | 409 | if (amdgpu_in_reset(adev)) |
48b270bb | 410 | return -EPERM; |
d2ae842d AD |
411 | if (adev->in_suspend && !adev->in_runpm) |
412 | return -EPERM; | |
48b270bb | 413 | |
d698a2c4 | 414 | if (adev->pm.pp_force_state_enabled) |
cd4d7464 RZ |
415 | return amdgpu_get_pp_cur_state(dev, attr, buf); |
416 | else | |
a9ca9bb3 | 417 | return sysfs_emit(buf, "\n"); |
f3898ea1 EH |
418 | } |
419 | ||
420 | static ssize_t amdgpu_set_pp_force_state(struct device *dev, | |
421 | struct device_attribute *attr, | |
422 | const char *buf, | |
423 | size_t count) | |
424 | { | |
425 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 426 | struct amdgpu_device *adev = drm_to_adev(ddev); |
f3898ea1 | 427 | enum amd_pm_state_type state = 0; |
79c65f3f | 428 | struct pp_states_info data; |
041bf022 | 429 | unsigned long idx; |
f3898ea1 EH |
430 | int ret; |
431 | ||
53b3f8f4 | 432 | if (amdgpu_in_reset(adev)) |
48b270bb | 433 | return -EPERM; |
d2ae842d AD |
434 | if (adev->in_suspend && !adev->in_runpm) |
435 | return -EPERM; | |
48b270bb | 436 | |
d698a2c4 | 437 | adev->pm.pp_force_state_enabled = false; |
b9a9294b | 438 | |
79c65f3f EQ |
439 | if (strlen(buf) == 1) |
440 | return count; | |
f3898ea1 | 441 | |
79c65f3f EQ |
442 | ret = kstrtoul(buf, 0, &idx); |
443 | if (ret || idx >= ARRAY_SIZE(data.states)) | |
444 | return -EINVAL; | |
b9a9294b | 445 | |
79c65f3f | 446 | idx = array_index_nospec(idx, ARRAY_SIZE(data.states)); |
b9a9294b | 447 | |
79c65f3f EQ |
448 | ret = pm_runtime_get_sync(ddev->dev); |
449 | if (ret < 0) { | |
b9a9294b | 450 | pm_runtime_put_autosuspend(ddev->dev); |
79c65f3f EQ |
451 | return ret; |
452 | } | |
453 | ||
454 | ret = amdgpu_dpm_get_pp_num_states(adev, &data); | |
455 | if (ret) | |
456 | goto err_out; | |
457 | ||
458 | state = data.states[idx]; | |
459 | ||
460 | /* only set user selected power states */ | |
461 | if (state != POWER_STATE_TYPE_INTERNAL_BOOT && | |
462 | state != POWER_STATE_TYPE_DEFAULT) { | |
463 | ret = amdgpu_dpm_dispatch_task(adev, | |
464 | AMD_PP_TASK_ENABLE_USER_STATE, &state); | |
465 | if (ret) | |
466 | goto err_out; | |
467 | ||
d698a2c4 | 468 | adev->pm.pp_force_state_enabled = true; |
f3898ea1 | 469 | } |
b9a9294b | 470 | |
79c65f3f EQ |
471 | pm_runtime_mark_last_busy(ddev->dev); |
472 | pm_runtime_put_autosuspend(ddev->dev); | |
473 | ||
f3898ea1 | 474 | return count; |
79c65f3f EQ |
475 | |
476 | err_out: | |
477 | pm_runtime_mark_last_busy(ddev->dev); | |
478 | pm_runtime_put_autosuspend(ddev->dev); | |
479 | return ret; | |
f3898ea1 EH |
480 | } |
481 | ||
d54bb40f AD |
482 | /** |
483 | * DOC: pp_table | |
484 | * | |
485 | * The amdgpu driver provides a sysfs API for uploading new powerplay | |
486 | * tables. The file pp_table is used for this. Reading the file | |
487 | * will dump the current power play table. Writing to the file | |
488 | * will attempt to upload a new powerplay table and re-initialize | |
489 | * powerplay using that new table. | |
490 | * | |
491 | */ | |
492 | ||
f3898ea1 EH |
493 | static ssize_t amdgpu_get_pp_table(struct device *dev, |
494 | struct device_attribute *attr, | |
495 | char *buf) | |
496 | { | |
497 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 498 | struct amdgpu_device *adev = drm_to_adev(ddev); |
f3898ea1 | 499 | char *table = NULL; |
b9a9294b | 500 | int size, ret; |
f3898ea1 | 501 | |
53b3f8f4 | 502 | if (amdgpu_in_reset(adev)) |
48b270bb | 503 | return -EPERM; |
d2ae842d AD |
504 | if (adev->in_suspend && !adev->in_runpm) |
505 | return -EPERM; | |
48b270bb | 506 | |
b9a9294b | 507 | ret = pm_runtime_get_sync(ddev->dev); |
66429300 AD |
508 | if (ret < 0) { |
509 | pm_runtime_put_autosuspend(ddev->dev); | |
b9a9294b | 510 | return ret; |
66429300 | 511 | } |
b9a9294b | 512 | |
79c65f3f EQ |
513 | size = amdgpu_dpm_get_pp_table(adev, &table); |
514 | ||
515 | pm_runtime_mark_last_busy(ddev->dev); | |
516 | pm_runtime_put_autosuspend(ddev->dev); | |
517 | ||
518 | if (size <= 0) | |
519 | return size; | |
f3898ea1 EH |
520 | |
521 | if (size >= PAGE_SIZE) | |
522 | size = PAGE_SIZE - 1; | |
523 | ||
1684d3ba | 524 | memcpy(buf, table, size); |
f3898ea1 EH |
525 | |
526 | return size; | |
527 | } | |
528 | ||
529 | static ssize_t amdgpu_set_pp_table(struct device *dev, | |
530 | struct device_attribute *attr, | |
531 | const char *buf, | |
532 | size_t count) | |
533 | { | |
534 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 535 | struct amdgpu_device *adev = drm_to_adev(ddev); |
289921b0 | 536 | int ret = 0; |
f3898ea1 | 537 | |
53b3f8f4 | 538 | if (amdgpu_in_reset(adev)) |
48b270bb | 539 | return -EPERM; |
d2ae842d AD |
540 | if (adev->in_suspend && !adev->in_runpm) |
541 | return -EPERM; | |
48b270bb | 542 | |
b9a9294b | 543 | ret = pm_runtime_get_sync(ddev->dev); |
66429300 AD |
544 | if (ret < 0) { |
545 | pm_runtime_put_autosuspend(ddev->dev); | |
b9a9294b | 546 | return ret; |
66429300 | 547 | } |
b9a9294b | 548 | |
8f4828d0 | 549 | ret = amdgpu_dpm_set_pp_table(adev, buf, count); |
f3898ea1 | 550 | |
b9a9294b AD |
551 | pm_runtime_mark_last_busy(ddev->dev); |
552 | pm_runtime_put_autosuspend(ddev->dev); | |
553 | ||
79c65f3f EQ |
554 | if (ret) |
555 | return ret; | |
556 | ||
f3898ea1 EH |
557 | return count; |
558 | } | |
559 | ||
4e418c34 AD |
560 | /** |
561 | * DOC: pp_od_clk_voltage | |
562 | * | |
563 | * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages | |
564 | * in each power level within a power state. The pp_od_clk_voltage is used for | |
565 | * this. | |
566 | * | |
ccda42a4 AD |
567 | * Note that the actual memory controller clock rate are exposed, not |
568 | * the effective memory clock of the DRAMs. To translate it, use the | |
569 | * following formula: | |
570 | * | |
571 | * Clock conversion (Mhz): | |
572 | * | |
573 | * HBM: effective_memory_clock = memory_controller_clock * 1 | |
574 | * | |
575 | * G5: effective_memory_clock = memory_controller_clock * 1 | |
576 | * | |
577 | * G6: effective_memory_clock = memory_controller_clock * 2 | |
578 | * | |
579 | * DRAM data rate (MT/s): | |
580 | * | |
581 | * HBM: effective_memory_clock * 2 = data_rate | |
582 | * | |
583 | * G5: effective_memory_clock * 4 = data_rate | |
584 | * | |
585 | * G6: effective_memory_clock * 8 = data_rate | |
586 | * | |
587 | * Bandwidth (MB/s): | |
588 | * | |
589 | * data_rate * vram_bit_width / 8 = memory_bandwidth | |
590 | * | |
591 | * Some examples: | |
592 | * | |
593 | * G5 on RX460: | |
594 | * | |
595 | * memory_controller_clock = 1750 Mhz | |
596 | * | |
597 | * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz | |
598 | * | |
599 | * data rate = 1750 * 4 = 7000 MT/s | |
600 | * | |
601 | * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s | |
602 | * | |
603 | * G6 on RX5700: | |
604 | * | |
605 | * memory_controller_clock = 875 Mhz | |
606 | * | |
607 | * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz | |
608 | * | |
609 | * data rate = 1750 * 8 = 14000 MT/s | |
610 | * | |
611 | * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s | |
612 | * | |
d5bf2653 EQ |
613 | * < For Vega10 and previous ASICs > |
614 | * | |
4e418c34 | 615 | * Reading the file will display: |
dc85db25 | 616 | * |
4e418c34 | 617 | * - a list of engine clock levels and voltages labeled OD_SCLK |
dc85db25 | 618 | * |
4e418c34 | 619 | * - a list of memory clock levels and voltages labeled OD_MCLK |
dc85db25 | 620 | * |
4e418c34 AD |
621 | * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE |
622 | * | |
623 | * To manually adjust these settings, first select manual using | |
624 | * power_dpm_force_performance_level. Enter a new value for each | |
625 | * level by writing a string that contains "s/m level clock voltage" to | |
626 | * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz | |
627 | * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at | |
628 | * 810 mV. When you have edited all of the states as needed, write | |
629 | * "c" (commit) to the file to commit your changes. If you want to reset to the | |
630 | * default power levels, write "r" (reset) to the file to reset them. | |
631 | * | |
d5bf2653 | 632 | * |
bd09331a | 633 | * < For Vega20 and newer ASICs > |
d5bf2653 EQ |
634 | * |
635 | * Reading the file will display: | |
636 | * | |
637 | * - minimum and maximum engine clock labeled OD_SCLK | |
638 | * | |
37a58f69 EQ |
639 | * - minimum(not available for Vega20 and Navi1x) and maximum memory |
640 | * clock labeled OD_MCLK | |
d5bf2653 | 641 | * |
b1f82cb2 | 642 | * - three <frequency, voltage> points labeled OD_VDDC_CURVE. |
8f4f5f0b EQ |
643 | * They can be used to calibrate the sclk voltage curve. This is |
644 | * available for Vega20 and NV1X. | |
645 | * | |
646 | * - voltage offset for the six anchor points of the v/f curve labeled | |
647 | * OD_VDDC_CURVE. They can be used to calibrate the v/f curve. This | |
648 | * is only availabe for some SMU13 ASICs. | |
d5bf2653 | 649 | * |
a2b6df4f EQ |
650 | * - voltage offset(in mV) applied on target voltage calculation. |
651 | * This is available for Sienna Cichlid, Navy Flounder and Dimgrey | |
652 | * Cavefish. For these ASICs, the target voltage calculation can be | |
653 | * illustrated by "voltage = voltage calculated from v/f curve + | |
654 | * overdrive vddgfx offset" | |
655 | * | |
d5bf2653 EQ |
656 | * - a list of valid ranges for sclk, mclk, and voltage curve points |
657 | * labeled OD_RANGE | |
658 | * | |
0487bbb4 AD |
659 | * < For APUs > |
660 | * | |
661 | * Reading the file will display: | |
662 | * | |
663 | * - minimum and maximum engine clock labeled OD_SCLK | |
664 | * | |
665 | * - a list of valid ranges for sclk labeled OD_RANGE | |
666 | * | |
3dc8077f AD |
667 | * < For VanGogh > |
668 | * | |
669 | * Reading the file will display: | |
670 | * | |
671 | * - minimum and maximum engine clock labeled OD_SCLK | |
672 | * - minimum and maximum core clocks labeled OD_CCLK | |
673 | * | |
674 | * - a list of valid ranges for sclk and cclk labeled OD_RANGE | |
675 | * | |
d5bf2653 EQ |
676 | * To manually adjust these settings: |
677 | * | |
678 | * - First select manual using power_dpm_force_performance_level | |
679 | * | |
680 | * - For clock frequency setting, enter a new value by writing a | |
681 | * string that contains "s/m index clock" to the file. The index | |
682 | * should be 0 if to set minimum clock. And 1 if to set maximum | |
683 | * clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz. | |
3dc8077f AD |
684 | * "m 1 800" will update maximum mclk to be 800Mhz. For core |
685 | * clocks on VanGogh, the string contains "p core index clock". | |
686 | * E.g., "p 2 0 800" would set the minimum core clock on core | |
687 | * 2 to 800Mhz. | |
d5bf2653 | 688 | * |
8f4f5f0b EQ |
689 | * For sclk voltage curve, |
690 | * - For NV1X, enter the new values by writing a string that | |
691 | * contains "vc point clock voltage" to the file. The points | |
692 | * are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will update | |
693 | * point1 with clock set as 300Mhz and voltage as 600mV. "vc 2 | |
694 | * 1000 1000" will update point3 with clock set as 1000Mhz and | |
695 | * voltage 1000mV. | |
696 | * - For SMU13 ASICs, enter the new values by writing a string that | |
697 | * contains "vc anchor_point_index voltage_offset" to the file. | |
698 | * There are total six anchor points defined on the v/f curve with | |
699 | * index as 0 - 5. | |
700 | * - "vc 0 10" will update the voltage offset for point1 as 10mv. | |
701 | * - "vc 5 -10" will update the voltage offset for point6 as -10mv. | |
d5bf2653 | 702 | * |
a2b6df4f EQ |
703 | * To update the voltage offset applied for gfxclk/voltage calculation, |
704 | * enter the new value by writing a string that contains "vo offset". | |
705 | * This is supported by Sienna Cichlid, Navy Flounder and Dimgrey Cavefish. | |
706 | * And the offset can be a positive or negative value. | |
707 | * | |
d5bf2653 EQ |
708 | * - When you have edited all of the states as needed, write "c" (commit) |
709 | * to the file to commit your changes | |
710 | * | |
711 | * - If you want to reset to the default power levels, write "r" (reset) | |
712 | * to the file to reset them | |
713 | * | |
4e418c34 AD |
714 | */ |
715 | ||
e3933f26 RZ |
716 | static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev, |
717 | struct device_attribute *attr, | |
718 | const char *buf, | |
719 | size_t count) | |
720 | { | |
721 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 722 | struct amdgpu_device *adev = drm_to_adev(ddev); |
e3933f26 RZ |
723 | int ret; |
724 | uint32_t parameter_size = 0; | |
725 | long parameter[64]; | |
726 | char buf_cpy[128]; | |
727 | char *tmp_str; | |
728 | char *sub_str; | |
729 | const char delimiter[3] = {' ', '\n', '\0'}; | |
730 | uint32_t type; | |
731 | ||
53b3f8f4 | 732 | if (amdgpu_in_reset(adev)) |
48b270bb | 733 | return -EPERM; |
d2ae842d AD |
734 | if (adev->in_suspend && !adev->in_runpm) |
735 | return -EPERM; | |
48b270bb | 736 | |
e3933f26 RZ |
737 | if (count > 127) |
738 | return -EINVAL; | |
739 | ||
740 | if (*buf == 's') | |
741 | type = PP_OD_EDIT_SCLK_VDDC_TABLE; | |
0d90d0dd HR |
742 | else if (*buf == 'p') |
743 | type = PP_OD_EDIT_CCLK_VDDC_TABLE; | |
e3933f26 RZ |
744 | else if (*buf == 'm') |
745 | type = PP_OD_EDIT_MCLK_VDDC_TABLE; | |
e1b3bcaa | 746 | else if (*buf == 'r') |
e3933f26 RZ |
747 | type = PP_OD_RESTORE_DEFAULT_TABLE; |
748 | else if (*buf == 'c') | |
749 | type = PP_OD_COMMIT_DPM_TABLE; | |
d5bf2653 EQ |
750 | else if (!strncmp(buf, "vc", 2)) |
751 | type = PP_OD_EDIT_VDDC_CURVE; | |
a2b6df4f EQ |
752 | else if (!strncmp(buf, "vo", 2)) |
753 | type = PP_OD_EDIT_VDDGFX_OFFSET; | |
e3933f26 RZ |
754 | else |
755 | return -EINVAL; | |
756 | ||
757 | memcpy(buf_cpy, buf, count+1); | |
758 | ||
759 | tmp_str = buf_cpy; | |
760 | ||
a2b6df4f EQ |
761 | if ((type == PP_OD_EDIT_VDDC_CURVE) || |
762 | (type == PP_OD_EDIT_VDDGFX_OFFSET)) | |
d5bf2653 | 763 | tmp_str++; |
e3933f26 RZ |
764 | while (isspace(*++tmp_str)); |
765 | ||
ce7c1d04 | 766 | while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) { |
aec1d870 MC |
767 | if (strlen(sub_str) == 0) |
768 | continue; | |
e3933f26 RZ |
769 | ret = kstrtol(sub_str, 0, ¶meter[parameter_size]); |
770 | if (ret) | |
771 | return -EINVAL; | |
772 | parameter_size++; | |
773 | ||
774 | while (isspace(*tmp_str)) | |
775 | tmp_str++; | |
776 | } | |
777 | ||
b9a9294b | 778 | ret = pm_runtime_get_sync(ddev->dev); |
66429300 AD |
779 | if (ret < 0) { |
780 | pm_runtime_put_autosuspend(ddev->dev); | |
b9a9294b | 781 | return ret; |
66429300 | 782 | } |
b9a9294b | 783 | |
79c65f3f EQ |
784 | if (amdgpu_dpm_set_fine_grain_clk_vol(adev, |
785 | type, | |
786 | parameter, | |
787 | parameter_size)) | |
788 | goto err_out; | |
12a6727d | 789 | |
79c65f3f EQ |
790 | if (amdgpu_dpm_odn_edit_dpm_table(adev, type, |
791 | parameter, parameter_size)) | |
792 | goto err_out; | |
e388cc47 | 793 | |
8f4828d0 | 794 | if (type == PP_OD_COMMIT_DPM_TABLE) { |
79c65f3f EQ |
795 | if (amdgpu_dpm_dispatch_task(adev, |
796 | AMD_PP_TASK_READJUST_POWER_STATE, | |
797 | NULL)) | |
798 | goto err_out; | |
e3933f26 | 799 | } |
8f4828d0 | 800 | |
b9a9294b AD |
801 | pm_runtime_mark_last_busy(ddev->dev); |
802 | pm_runtime_put_autosuspend(ddev->dev); | |
e3933f26 | 803 | |
f1403342 | 804 | return count; |
79c65f3f EQ |
805 | |
806 | err_out: | |
807 | pm_runtime_mark_last_busy(ddev->dev); | |
808 | pm_runtime_put_autosuspend(ddev->dev); | |
809 | return -EINVAL; | |
e3933f26 RZ |
810 | } |
811 | ||
812 | static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev, | |
813 | struct device_attribute *attr, | |
814 | char *buf) | |
815 | { | |
816 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 817 | struct amdgpu_device *adev = drm_to_adev(ddev); |
c8cb19c7 | 818 | int size = 0; |
b9a9294b | 819 | int ret; |
c8cb19c7 DP |
820 | enum pp_clock_type od_clocks[6] = { |
821 | OD_SCLK, | |
822 | OD_MCLK, | |
823 | OD_VDDC_CURVE, | |
824 | OD_RANGE, | |
825 | OD_VDDGFX_OFFSET, | |
826 | OD_CCLK, | |
827 | }; | |
828 | uint clk_index; | |
e3933f26 | 829 | |
53b3f8f4 | 830 | if (amdgpu_in_reset(adev)) |
48b270bb | 831 | return -EPERM; |
d2ae842d AD |
832 | if (adev->in_suspend && !adev->in_runpm) |
833 | return -EPERM; | |
48b270bb | 834 | |
b9a9294b | 835 | ret = pm_runtime_get_sync(ddev->dev); |
66429300 AD |
836 | if (ret < 0) { |
837 | pm_runtime_put_autosuspend(ddev->dev); | |
b9a9294b | 838 | return ret; |
66429300 | 839 | } |
b9a9294b | 840 | |
c8cb19c7 DP |
841 | for (clk_index = 0 ; clk_index < 6 ; clk_index++) { |
842 | ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size); | |
843 | if (ret) | |
844 | break; | |
e3933f26 | 845 | } |
c8cb19c7 DP |
846 | if (ret == -ENOENT) { |
847 | size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf); | |
ab22ecab JE |
848 | size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size); |
849 | size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size); | |
850 | size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size); | |
851 | size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size); | |
852 | size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size); | |
c8cb19c7 DP |
853 | } |
854 | ||
855 | if (size == 0) | |
856 | size = sysfs_emit(buf, "\n"); | |
857 | ||
b9a9294b AD |
858 | pm_runtime_mark_last_busy(ddev->dev); |
859 | pm_runtime_put_autosuspend(ddev->dev); | |
e3933f26 | 860 | |
b9a9294b | 861 | return size; |
e3933f26 RZ |
862 | } |
863 | ||
7ca881a8 | 864 | /** |
98eb03bb | 865 | * DOC: pp_features |
7ca881a8 EQ |
866 | * |
867 | * The amdgpu driver provides a sysfs API for adjusting what powerplay | |
98eb03bb | 868 | * features to be enabled. The file pp_features is used for this. And |
7ca881a8 EQ |
869 | * this is only available for Vega10 and later dGPUs. |
870 | * | |
871 | * Reading back the file will show you the followings: | |
872 | * - Current ppfeature masks | |
873 | * - List of the all supported powerplay features with their naming, | |
874 | * bitmasks and enablement status('Y'/'N' means "enabled"/"disabled"). | |
875 | * | |
876 | * To manually enable or disable a specific feature, just set or clear | |
877 | * the corresponding bit from original ppfeature masks and input the | |
878 | * new ppfeature masks. | |
879 | */ | |
4e01847c KW |
880 | static ssize_t amdgpu_set_pp_features(struct device *dev, |
881 | struct device_attribute *attr, | |
882 | const char *buf, | |
883 | size_t count) | |
7ca881a8 EQ |
884 | { |
885 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 886 | struct amdgpu_device *adev = drm_to_adev(ddev); |
7ca881a8 EQ |
887 | uint64_t featuremask; |
888 | int ret; | |
889 | ||
53b3f8f4 | 890 | if (amdgpu_in_reset(adev)) |
48b270bb | 891 | return -EPERM; |
d2ae842d AD |
892 | if (adev->in_suspend && !adev->in_runpm) |
893 | return -EPERM; | |
48b270bb | 894 | |
7ca881a8 EQ |
895 | ret = kstrtou64(buf, 0, &featuremask); |
896 | if (ret) | |
897 | return -EINVAL; | |
898 | ||
b9a9294b | 899 | ret = pm_runtime_get_sync(ddev->dev); |
66429300 AD |
900 | if (ret < 0) { |
901 | pm_runtime_put_autosuspend(ddev->dev); | |
b9a9294b | 902 | return ret; |
66429300 | 903 | } |
b9a9294b | 904 | |
79c65f3f EQ |
905 | ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask); |
906 | ||
b9a9294b AD |
907 | pm_runtime_mark_last_busy(ddev->dev); |
908 | pm_runtime_put_autosuspend(ddev->dev); | |
7ca881a8 | 909 | |
79c65f3f EQ |
910 | if (ret) |
911 | return -EINVAL; | |
912 | ||
7ca881a8 EQ |
913 | return count; |
914 | } | |
915 | ||
4e01847c KW |
916 | static ssize_t amdgpu_get_pp_features(struct device *dev, |
917 | struct device_attribute *attr, | |
918 | char *buf) | |
7ca881a8 EQ |
919 | { |
920 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 921 | struct amdgpu_device *adev = drm_to_adev(ddev); |
b9a9294b AD |
922 | ssize_t size; |
923 | int ret; | |
7ca881a8 | 924 | |
53b3f8f4 | 925 | if (amdgpu_in_reset(adev)) |
48b270bb | 926 | return -EPERM; |
d2ae842d AD |
927 | if (adev->in_suspend && !adev->in_runpm) |
928 | return -EPERM; | |
48b270bb | 929 | |
b9a9294b | 930 | ret = pm_runtime_get_sync(ddev->dev); |
66429300 AD |
931 | if (ret < 0) { |
932 | pm_runtime_put_autosuspend(ddev->dev); | |
b9a9294b | 933 | return ret; |
66429300 | 934 | } |
b9a9294b | 935 | |
79c65f3f EQ |
936 | size = amdgpu_dpm_get_ppfeature_status(adev, buf); |
937 | if (size <= 0) | |
09b6744c | 938 | size = sysfs_emit(buf, "\n"); |
b9a9294b AD |
939 | |
940 | pm_runtime_mark_last_busy(ddev->dev); | |
941 | pm_runtime_put_autosuspend(ddev->dev); | |
7ca881a8 | 942 | |
b9a9294b | 943 | return size; |
7ca881a8 EQ |
944 | } |
945 | ||
271dc908 | 946 | /** |
a667b75c | 947 | * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie |
271dc908 AD |
948 | * |
949 | * The amdgpu driver provides a sysfs API for adjusting what power levels | |
950 | * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk, | |
d7e28e2d EQ |
951 | * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for |
952 | * this. | |
d7337ca2 | 953 | * |
d7e28e2d EQ |
954 | * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for |
955 | * Vega10 and later ASICs. | |
828e37ef | 956 | * pp_dpm_fclk interface is only available for Vega20 and later ASICs. |
271dc908 AD |
957 | * |
958 | * Reading back the files will show you the available power levels within | |
959 | * the power state and the clock information for those levels. | |
960 | * | |
961 | * To manually adjust these states, first select manual using | |
48edde39 | 962 | * power_dpm_force_performance_level. |
a667b75c | 963 | * Secondly, enter a new value for each level by inputing a string that |
48edde39 | 964 | * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie" |
a667b75c AD |
965 | * E.g., |
966 | * | |
967 | * .. code-block:: bash | |
968 | * | |
969 | * echo "4 5 6" > pp_dpm_sclk | |
970 | * | |
971 | * will enable sclk levels 4, 5, and 6. | |
d7e28e2d EQ |
972 | * |
973 | * NOTE: change to the dcefclk max dpm level is not supported now | |
271dc908 AD |
974 | */ |
975 | ||
2ea092e5 DP |
976 | static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev, |
977 | enum pp_clock_type type, | |
f3898ea1 EH |
978 | char *buf) |
979 | { | |
980 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 981 | struct amdgpu_device *adev = drm_to_adev(ddev); |
c8cb19c7 DP |
982 | int size = 0; |
983 | int ret = 0; | |
f3898ea1 | 984 | |
53b3f8f4 | 985 | if (amdgpu_in_reset(adev)) |
48b270bb | 986 | return -EPERM; |
d2ae842d AD |
987 | if (adev->in_suspend && !adev->in_runpm) |
988 | return -EPERM; | |
48b270bb | 989 | |
b9a9294b | 990 | ret = pm_runtime_get_sync(ddev->dev); |
66429300 AD |
991 | if (ret < 0) { |
992 | pm_runtime_put_autosuspend(ddev->dev); | |
b9a9294b | 993 | return ret; |
66429300 | 994 | } |
b9a9294b | 995 | |
c8cb19c7 DP |
996 | ret = amdgpu_dpm_emit_clock_levels(adev, type, buf, &size); |
997 | if (ret == -ENOENT) | |
998 | size = amdgpu_dpm_print_clock_levels(adev, type, buf); | |
999 | ||
1000 | if (size == 0) | |
09b6744c | 1001 | size = sysfs_emit(buf, "\n"); |
b9a9294b AD |
1002 | |
1003 | pm_runtime_mark_last_busy(ddev->dev); | |
1004 | pm_runtime_put_autosuspend(ddev->dev); | |
1005 | ||
1006 | return size; | |
f3898ea1 EH |
1007 | } |
1008 | ||
4b4bd048 KC |
1009 | /* |
1010 | * Worst case: 32 bits individually specified, in octal at 12 characters | |
1011 | * per line (+1 for \n). | |
1012 | */ | |
1013 | #define AMDGPU_MASK_BUF_MAX (32 * 13) | |
1014 | ||
1015 | static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask) | |
f3898ea1 | 1016 | { |
f3898ea1 | 1017 | int ret; |
c915ef89 | 1018 | unsigned long level; |
48edde39 | 1019 | char *sub_str = NULL; |
1020 | char *tmp; | |
4b4bd048 | 1021 | char buf_cpy[AMDGPU_MASK_BUF_MAX + 1]; |
48edde39 | 1022 | const char delimiter[3] = {' ', '\n', '\0'}; |
4b4bd048 | 1023 | size_t bytes; |
f3898ea1 | 1024 | |
4b4bd048 KC |
1025 | *mask = 0; |
1026 | ||
1027 | bytes = min(count, sizeof(buf_cpy) - 1); | |
1028 | memcpy(buf_cpy, buf, bytes); | |
1029 | buf_cpy[bytes] = '\0'; | |
48edde39 | 1030 | tmp = buf_cpy; |
ce7c1d04 | 1031 | while ((sub_str = strsep(&tmp, delimiter)) != NULL) { |
48edde39 | 1032 | if (strlen(sub_str)) { |
c915ef89 DC |
1033 | ret = kstrtoul(sub_str, 0, &level); |
1034 | if (ret || level > 31) | |
4b4bd048 KC |
1035 | return -EINVAL; |
1036 | *mask |= 1 << level; | |
48edde39 | 1037 | } else |
1038 | break; | |
f3898ea1 | 1039 | } |
4b4bd048 KC |
1040 | |
1041 | return 0; | |
1042 | } | |
1043 | ||
2ea092e5 DP |
1044 | static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev, |
1045 | enum pp_clock_type type, | |
4b4bd048 KC |
1046 | const char *buf, |
1047 | size_t count) | |
1048 | { | |
1049 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 1050 | struct amdgpu_device *adev = drm_to_adev(ddev); |
4b4bd048 KC |
1051 | int ret; |
1052 | uint32_t mask = 0; | |
1053 | ||
53b3f8f4 | 1054 | if (amdgpu_in_reset(adev)) |
48b270bb | 1055 | return -EPERM; |
d2ae842d AD |
1056 | if (adev->in_suspend && !adev->in_runpm) |
1057 | return -EPERM; | |
48b270bb | 1058 | |
4b4bd048 KC |
1059 | ret = amdgpu_read_mask(buf, count, &mask); |
1060 | if (ret) | |
1061 | return ret; | |
1062 | ||
b9a9294b | 1063 | ret = pm_runtime_get_sync(ddev->dev); |
66429300 AD |
1064 | if (ret < 0) { |
1065 | pm_runtime_put_autosuspend(ddev->dev); | |
b9a9294b | 1066 | return ret; |
66429300 | 1067 | } |
b9a9294b | 1068 | |
79c65f3f | 1069 | ret = amdgpu_dpm_force_clock_level(adev, type, mask); |
241dbbb1 | 1070 | |
b9a9294b AD |
1071 | pm_runtime_mark_last_busy(ddev->dev); |
1072 | pm_runtime_put_autosuspend(ddev->dev); | |
1073 | ||
241dbbb1 EQ |
1074 | if (ret) |
1075 | return -EINVAL; | |
cd4d7464 | 1076 | |
f3898ea1 EH |
1077 | return count; |
1078 | } | |
1079 | ||
2ea092e5 | 1080 | static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev, |
f3898ea1 EH |
1081 | struct device_attribute *attr, |
1082 | char *buf) | |
1083 | { | |
2ea092e5 DP |
1084 | return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf); |
1085 | } | |
b9a9294b | 1086 | |
2ea092e5 DP |
1087 | static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, |
1088 | struct device_attribute *attr, | |
1089 | const char *buf, | |
1090 | size_t count) | |
1091 | { | |
1092 | return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count); | |
1093 | } | |
b9a9294b | 1094 | |
2ea092e5 DP |
1095 | static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev, |
1096 | struct device_attribute *attr, | |
1097 | char *buf) | |
1098 | { | |
1099 | return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf); | |
f3898ea1 EH |
1100 | } |
1101 | ||
1102 | static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, | |
1103 | struct device_attribute *attr, | |
1104 | const char *buf, | |
1105 | size_t count) | |
1106 | { | |
2ea092e5 | 1107 | return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count); |
f3898ea1 EH |
1108 | } |
1109 | ||
d7337ca2 EQ |
1110 | static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev, |
1111 | struct device_attribute *attr, | |
1112 | char *buf) | |
1113 | { | |
2ea092e5 | 1114 | return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf); |
d7337ca2 EQ |
1115 | } |
1116 | ||
1117 | static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev, | |
1118 | struct device_attribute *attr, | |
1119 | const char *buf, | |
1120 | size_t count) | |
1121 | { | |
2ea092e5 | 1122 | return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count); |
d7337ca2 EQ |
1123 | } |
1124 | ||
828e37ef EQ |
1125 | static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev, |
1126 | struct device_attribute *attr, | |
1127 | char *buf) | |
1128 | { | |
2ea092e5 | 1129 | return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf); |
828e37ef EQ |
1130 | } |
1131 | ||
1132 | static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev, | |
1133 | struct device_attribute *attr, | |
1134 | const char *buf, | |
1135 | size_t count) | |
1136 | { | |
2ea092e5 | 1137 | return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count); |
828e37ef EQ |
1138 | } |
1139 | ||
9577b0ec XD |
1140 | static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev, |
1141 | struct device_attribute *attr, | |
1142 | char *buf) | |
1143 | { | |
2ea092e5 | 1144 | return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf); |
9577b0ec XD |
1145 | } |
1146 | ||
1147 | static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev, | |
1148 | struct device_attribute *attr, | |
1149 | const char *buf, | |
1150 | size_t count) | |
1151 | { | |
2ea092e5 | 1152 | return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count); |
9577b0ec XD |
1153 | } |
1154 | ||
d7001e72 TL |
1155 | static ssize_t amdgpu_get_pp_dpm_vclk1(struct device *dev, |
1156 | struct device_attribute *attr, | |
1157 | char *buf) | |
1158 | { | |
1159 | return amdgpu_get_pp_dpm_clock(dev, PP_VCLK1, buf); | |
1160 | } | |
1161 | ||
1162 | static ssize_t amdgpu_set_pp_dpm_vclk1(struct device *dev, | |
1163 | struct device_attribute *attr, | |
1164 | const char *buf, | |
1165 | size_t count) | |
1166 | { | |
1167 | return amdgpu_set_pp_dpm_clock(dev, PP_VCLK1, buf, count); | |
1168 | } | |
1169 | ||
9577b0ec XD |
1170 | static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev, |
1171 | struct device_attribute *attr, | |
1172 | char *buf) | |
1173 | { | |
2ea092e5 | 1174 | return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf); |
9577b0ec XD |
1175 | } |
1176 | ||
1177 | static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev, | |
1178 | struct device_attribute *attr, | |
1179 | const char *buf, | |
1180 | size_t count) | |
1181 | { | |
2ea092e5 | 1182 | return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count); |
9577b0ec XD |
1183 | } |
1184 | ||
d7001e72 TL |
1185 | static ssize_t amdgpu_get_pp_dpm_dclk1(struct device *dev, |
1186 | struct device_attribute *attr, | |
1187 | char *buf) | |
1188 | { | |
1189 | return amdgpu_get_pp_dpm_clock(dev, PP_DCLK1, buf); | |
1190 | } | |
1191 | ||
1192 | static ssize_t amdgpu_set_pp_dpm_dclk1(struct device *dev, | |
1193 | struct device_attribute *attr, | |
1194 | const char *buf, | |
1195 | size_t count) | |
1196 | { | |
1197 | return amdgpu_set_pp_dpm_clock(dev, PP_DCLK1, buf, count); | |
1198 | } | |
1199 | ||
d7e28e2d EQ |
1200 | static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev, |
1201 | struct device_attribute *attr, | |
1202 | char *buf) | |
1203 | { | |
2ea092e5 | 1204 | return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf); |
d7e28e2d EQ |
1205 | } |
1206 | ||
1207 | static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev, | |
1208 | struct device_attribute *attr, | |
1209 | const char *buf, | |
1210 | size_t count) | |
1211 | { | |
2ea092e5 | 1212 | return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count); |
d7e28e2d EQ |
1213 | } |
1214 | ||
f3898ea1 EH |
1215 | static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev, |
1216 | struct device_attribute *attr, | |
1217 | char *buf) | |
1218 | { | |
2ea092e5 | 1219 | return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf); |
f3898ea1 EH |
1220 | } |
1221 | ||
1222 | static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, | |
1223 | struct device_attribute *attr, | |
1224 | const char *buf, | |
1225 | size_t count) | |
1226 | { | |
2ea092e5 | 1227 | return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count); |
f3898ea1 EH |
1228 | } |
1229 | ||
428bafa8 EH |
1230 | static ssize_t amdgpu_get_pp_sclk_od(struct device *dev, |
1231 | struct device_attribute *attr, | |
1232 | char *buf) | |
1233 | { | |
1234 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 1235 | struct amdgpu_device *adev = drm_to_adev(ddev); |
428bafa8 | 1236 | uint32_t value = 0; |
b9a9294b | 1237 | int ret; |
428bafa8 | 1238 | |
53b3f8f4 | 1239 | if (amdgpu_in_reset(adev)) |
48b270bb | 1240 | return -EPERM; |
d2ae842d AD |
1241 | if (adev->in_suspend && !adev->in_runpm) |
1242 | return -EPERM; | |
48b270bb | 1243 | |
b9a9294b | 1244 | ret = pm_runtime_get_sync(ddev->dev); |
66429300 AD |
1245 | if (ret < 0) { |
1246 | pm_runtime_put_autosuspend(ddev->dev); | |
b9a9294b | 1247 | return ret; |
66429300 | 1248 | } |
b9a9294b | 1249 | |
79c65f3f | 1250 | value = amdgpu_dpm_get_sclk_od(adev); |
428bafa8 | 1251 | |
b9a9294b AD |
1252 | pm_runtime_mark_last_busy(ddev->dev); |
1253 | pm_runtime_put_autosuspend(ddev->dev); | |
1254 | ||
a9ca9bb3 | 1255 | return sysfs_emit(buf, "%d\n", value); |
428bafa8 EH |
1256 | } |
1257 | ||
1258 | static ssize_t amdgpu_set_pp_sclk_od(struct device *dev, | |
1259 | struct device_attribute *attr, | |
1260 | const char *buf, | |
1261 | size_t count) | |
1262 | { | |
1263 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 1264 | struct amdgpu_device *adev = drm_to_adev(ddev); |
428bafa8 EH |
1265 | int ret; |
1266 | long int value; | |
1267 | ||
53b3f8f4 | 1268 | if (amdgpu_in_reset(adev)) |
48b270bb | 1269 | return -EPERM; |
d2ae842d AD |
1270 | if (adev->in_suspend && !adev->in_runpm) |
1271 | return -EPERM; | |
48b270bb | 1272 | |
428bafa8 EH |
1273 | ret = kstrtol(buf, 0, &value); |
1274 | ||
b9a9294b AD |
1275 | if (ret) |
1276 | return -EINVAL; | |
1277 | ||
1278 | ret = pm_runtime_get_sync(ddev->dev); | |
66429300 AD |
1279 | if (ret < 0) { |
1280 | pm_runtime_put_autosuspend(ddev->dev); | |
b9a9294b | 1281 | return ret; |
66429300 | 1282 | } |
428bafa8 | 1283 | |
79c65f3f | 1284 | amdgpu_dpm_set_sclk_od(adev, (uint32_t)value); |
428bafa8 | 1285 | |
b9a9294b AD |
1286 | pm_runtime_mark_last_busy(ddev->dev); |
1287 | pm_runtime_put_autosuspend(ddev->dev); | |
1288 | ||
428bafa8 EH |
1289 | return count; |
1290 | } | |
1291 | ||
f2bdc05f EH |
1292 | static ssize_t amdgpu_get_pp_mclk_od(struct device *dev, |
1293 | struct device_attribute *attr, | |
1294 | char *buf) | |
1295 | { | |
1296 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 1297 | struct amdgpu_device *adev = drm_to_adev(ddev); |
f2bdc05f | 1298 | uint32_t value = 0; |
b9a9294b | 1299 | int ret; |
f2bdc05f | 1300 | |
53b3f8f4 | 1301 | if (amdgpu_in_reset(adev)) |
48b270bb | 1302 | return -EPERM; |
d2ae842d AD |
1303 | if (adev->in_suspend && !adev->in_runpm) |
1304 | return -EPERM; | |
48b270bb | 1305 | |
b9a9294b | 1306 | ret = pm_runtime_get_sync(ddev->dev); |
66429300 AD |
1307 | if (ret < 0) { |
1308 | pm_runtime_put_autosuspend(ddev->dev); | |
b9a9294b | 1309 | return ret; |
66429300 | 1310 | } |
b9a9294b | 1311 | |
79c65f3f | 1312 | value = amdgpu_dpm_get_mclk_od(adev); |
f2bdc05f | 1313 | |
b9a9294b AD |
1314 | pm_runtime_mark_last_busy(ddev->dev); |
1315 | pm_runtime_put_autosuspend(ddev->dev); | |
1316 | ||
a9ca9bb3 | 1317 | return sysfs_emit(buf, "%d\n", value); |
f2bdc05f EH |
1318 | } |
1319 | ||
1320 | static ssize_t amdgpu_set_pp_mclk_od(struct device *dev, | |
1321 | struct device_attribute *attr, | |
1322 | const char *buf, | |
1323 | size_t count) | |
1324 | { | |
1325 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 1326 | struct amdgpu_device *adev = drm_to_adev(ddev); |
f2bdc05f EH |
1327 | int ret; |
1328 | long int value; | |
1329 | ||
53b3f8f4 | 1330 | if (amdgpu_in_reset(adev)) |
48b270bb | 1331 | return -EPERM; |
d2ae842d AD |
1332 | if (adev->in_suspend && !adev->in_runpm) |
1333 | return -EPERM; | |
48b270bb | 1334 | |
f2bdc05f EH |
1335 | ret = kstrtol(buf, 0, &value); |
1336 | ||
b9a9294b AD |
1337 | if (ret) |
1338 | return -EINVAL; | |
1339 | ||
1340 | ret = pm_runtime_get_sync(ddev->dev); | |
66429300 AD |
1341 | if (ret < 0) { |
1342 | pm_runtime_put_autosuspend(ddev->dev); | |
b9a9294b | 1343 | return ret; |
66429300 | 1344 | } |
f2bdc05f | 1345 | |
79c65f3f | 1346 | amdgpu_dpm_set_mclk_od(adev, (uint32_t)value); |
f2bdc05f | 1347 | |
b9a9294b AD |
1348 | pm_runtime_mark_last_busy(ddev->dev); |
1349 | pm_runtime_put_autosuspend(ddev->dev); | |
1350 | ||
f2bdc05f EH |
1351 | return count; |
1352 | } | |
1353 | ||
6b2576f5 AD |
1354 | /** |
1355 | * DOC: pp_power_profile_mode | |
1356 | * | |
1357 | * The amdgpu driver provides a sysfs API for adjusting the heuristics | |
1358 | * related to switching between power levels in a power state. The file | |
1359 | * pp_power_profile_mode is used for this. | |
1360 | * | |
1361 | * Reading this file outputs a list of all of the predefined power profiles | |
1362 | * and the relevant heuristics settings for that profile. | |
1363 | * | |
1364 | * To select a profile or create a custom profile, first select manual using | |
1365 | * power_dpm_force_performance_level. Writing the number of a predefined | |
1366 | * profile to pp_power_profile_mode will enable those heuristics. To | |
1367 | * create a custom set of heuristics, write a string of numbers to the file | |
1368 | * starting with the number of the custom profile along with a setting | |
1369 | * for each heuristic parameter. Due to differences across asic families | |
1370 | * the heuristic parameters vary from family to family. | |
1371 | * | |
1372 | */ | |
1373 | ||
37c5c4db RZ |
1374 | static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev, |
1375 | struct device_attribute *attr, | |
1376 | char *buf) | |
1377 | { | |
1378 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 1379 | struct amdgpu_device *adev = drm_to_adev(ddev); |
b9a9294b AD |
1380 | ssize_t size; |
1381 | int ret; | |
37c5c4db | 1382 | |
53b3f8f4 | 1383 | if (amdgpu_in_reset(adev)) |
48b270bb | 1384 | return -EPERM; |
d2ae842d AD |
1385 | if (adev->in_suspend && !adev->in_runpm) |
1386 | return -EPERM; | |
48b270bb | 1387 | |
b9a9294b | 1388 | ret = pm_runtime_get_sync(ddev->dev); |
66429300 AD |
1389 | if (ret < 0) { |
1390 | pm_runtime_put_autosuspend(ddev->dev); | |
b9a9294b | 1391 | return ret; |
66429300 | 1392 | } |
b9a9294b | 1393 | |
79c65f3f EQ |
1394 | size = amdgpu_dpm_get_power_profile_mode(adev, buf); |
1395 | if (size <= 0) | |
09b6744c | 1396 | size = sysfs_emit(buf, "\n"); |
b9a9294b AD |
1397 | |
1398 | pm_runtime_mark_last_busy(ddev->dev); | |
1399 | pm_runtime_put_autosuspend(ddev->dev); | |
37c5c4db | 1400 | |
b9a9294b | 1401 | return size; |
37c5c4db RZ |
1402 | } |
1403 | ||
1404 | ||
1405 | static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev, | |
1406 | struct device_attribute *attr, | |
1407 | const char *buf, | |
1408 | size_t count) | |
1409 | { | |
7c8e0835 | 1410 | int ret; |
37c5c4db | 1411 | struct drm_device *ddev = dev_get_drvdata(dev); |
1348969a | 1412 | struct amdgpu_device *adev = drm_to_adev(ddev); |
37c5c4db RZ |
1413 | uint32_t parameter_size = 0; |
1414 | long parameter[64]; | |
1415 | char *sub_str, buf_cpy[128]; | |
1416 | char *tmp_str; | |
1417 | uint32_t i = 0; | |
1418 | char tmp[2]; | |
1419 | long int profile_mode = 0; | |
1420 | const char delimiter[3] = {' ', '\n', '\0'}; | |
1421 | ||
53b3f8f4 | 1422 | if (amdgpu_in_reset(adev)) |
48b270bb | 1423 | return -EPERM; |
d2ae842d AD |
1424 | if (adev->in_suspend && !adev->in_runpm) |
1425 | return -EPERM; | |
48b270bb | 1426 | |
37c5c4db RZ |
1427 | tmp[0] = *(buf); |
1428 | tmp[1] = '\0'; | |
1429 | ret = kstrtol(tmp, 0, &profile_mode); | |
1430 | if (ret) | |
b9a9294b | 1431 | return -EINVAL; |
37c5c4db RZ |
1432 | |
1433 | if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { | |
1434 | if (count < 2 || count > 127) | |
1435 | return -EINVAL; | |
1436 | while (isspace(*++buf)) | |
1437 | i++; | |
1438 | memcpy(buf_cpy, buf, count-i); | |
1439 | tmp_str = buf_cpy; | |
ce7c1d04 | 1440 | while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) { |
c2efbc3f EQ |
1441 | if (strlen(sub_str) == 0) |
1442 | continue; | |
37c5c4db | 1443 | ret = kstrtol(sub_str, 0, ¶meter[parameter_size]); |
b9a9294b AD |
1444 | if (ret) |
1445 | return -EINVAL; | |
37c5c4db RZ |
1446 | parameter_size++; |
1447 | while (isspace(*tmp_str)) | |
1448 | tmp_str++; | |
1449 | } | |
1450 | } | |
1451 | parameter[parameter_size] = profile_mode; | |
b9a9294b AD |
1452 | |
1453 | ret = pm_runtime_get_sync(ddev->dev); | |
66429300 AD |
1454 | if (ret < 0) { |
1455 | pm_runtime_put_autosuspend(ddev->dev); | |
b9a9294b | 1456 | return ret; |
66429300 | 1457 | } |
b9a9294b | 1458 | |
79c65f3f | 1459 | ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size); |
b9a9294b AD |
1460 | |
1461 | pm_runtime_mark_last_busy(ddev->dev); | |
1462 | pm_runtime_put_autosuspend(ddev->dev); | |
1463 | ||
37c5c4db RZ |
1464 | if (!ret) |
1465 | return count; | |
b9a9294b | 1466 | |
37c5c4db RZ |
1467 | return -EINVAL; |
1468 | } | |
1469 | ||
d78c227f ML |
1470 | static unsigned int amdgpu_hwmon_get_sensor_generic(struct amdgpu_device *adev, |
1471 | enum amd_pp_sensors sensor, | |
1472 | void *query) | |
1473 | { | |
1474 | int r, size = sizeof(uint32_t); | |
1475 | ||
1476 | if (amdgpu_in_reset(adev)) | |
1477 | return -EPERM; | |
1478 | if (adev->in_suspend && !adev->in_runpm) | |
1479 | return -EPERM; | |
1480 | ||
1481 | r = pm_runtime_get_sync(adev_to_drm(adev)->dev); | |
1482 | if (r < 0) { | |
1483 | pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); | |
1484 | return r; | |
1485 | } | |
1486 | ||
1487 | /* get the sensor value */ | |
1488 | r = amdgpu_dpm_read_sensor(adev, sensor, query, &size); | |
1489 | ||
1490 | pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); | |
1491 | pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); | |
1492 | ||
1493 | return r; | |
1494 | } | |
1495 | ||
b374d82d | 1496 | /** |
f503fe69 | 1497 | * DOC: gpu_busy_percent |
b374d82d TSD |
1498 | * |
1499 | * The amdgpu driver provides a sysfs API for reading how busy the GPU | |
1500 | * is as a percentage. The file gpu_busy_percent is used for this. | |
1501 | * The SMU firmware computes a percentage of load based on the | |
1502 | * aggregate activity level in the IP cores. | |
1503 | */ | |
4e01847c KW |
1504 | static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev, |
1505 | struct device_attribute *attr, | |
1506 | char *buf) | |
b374d82d TSD |
1507 | { |
1508 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 1509 | struct amdgpu_device *adev = drm_to_adev(ddev); |
d78c227f ML |
1510 | unsigned int value; |
1511 | int r; | |
b9a9294b | 1512 | |
d78c227f | 1513 | r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_LOAD, &value); |
b374d82d TSD |
1514 | if (r) |
1515 | return r; | |
1516 | ||
a9ca9bb3 | 1517 | return sysfs_emit(buf, "%d\n", value); |
b374d82d TSD |
1518 | } |
1519 | ||
f120386d EQ |
1520 | /** |
1521 | * DOC: mem_busy_percent | |
1522 | * | |
1523 | * The amdgpu driver provides a sysfs API for reading how busy the VRAM | |
1524 | * is as a percentage. The file mem_busy_percent is used for this. | |
1525 | * The SMU firmware computes a percentage of load based on the | |
1526 | * aggregate activity level in the IP cores. | |
1527 | */ | |
4e01847c KW |
1528 | static ssize_t amdgpu_get_mem_busy_percent(struct device *dev, |
1529 | struct device_attribute *attr, | |
1530 | char *buf) | |
f120386d EQ |
1531 | { |
1532 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 1533 | struct amdgpu_device *adev = drm_to_adev(ddev); |
d78c227f ML |
1534 | unsigned int value; |
1535 | int r; | |
b9a9294b | 1536 | |
d78c227f | 1537 | r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_LOAD, &value); |
f120386d EQ |
1538 | if (r) |
1539 | return r; | |
1540 | ||
a9ca9bb3 | 1541 | return sysfs_emit(buf, "%d\n", value); |
f120386d EQ |
1542 | } |
1543 | ||
b45e18ac KR |
1544 | /** |
1545 | * DOC: pcie_bw | |
1546 | * | |
1547 | * The amdgpu driver provides a sysfs API for estimating how much data | |
1548 | * has been received and sent by the GPU in the last second through PCIe. | |
1549 | * The file pcie_bw is used for this. | |
1550 | * The Perf counters count the number of received and sent messages and return | |
1551 | * those values, as well as the maximum payload size of a PCIe packet (mps). | |
1552 | * Note that it is not possible to easily and quickly obtain the size of each | |
1553 | * packet transmitted, so we output the max payload size (mps) to allow for | |
1554 | * quick estimation of the PCIe bandwidth usage | |
1555 | */ | |
1556 | static ssize_t amdgpu_get_pcie_bw(struct device *dev, | |
1557 | struct device_attribute *attr, | |
1558 | char *buf) | |
1559 | { | |
1560 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 1561 | struct amdgpu_device *adev = drm_to_adev(ddev); |
d08d692e | 1562 | uint64_t count0 = 0, count1 = 0; |
b9a9294b | 1563 | int ret; |
b45e18ac | 1564 | |
53b3f8f4 | 1565 | if (amdgpu_in_reset(adev)) |
48b270bb | 1566 | return -EPERM; |
d2ae842d AD |
1567 | if (adev->in_suspend && !adev->in_runpm) |
1568 | return -EPERM; | |
48b270bb | 1569 | |
d08d692e AD |
1570 | if (adev->flags & AMD_IS_APU) |
1571 | return -ENODATA; | |
1572 | ||
1573 | if (!adev->asic_funcs->get_pcie_usage) | |
1574 | return -ENODATA; | |
1575 | ||
b9a9294b | 1576 | ret = pm_runtime_get_sync(ddev->dev); |
66429300 AD |
1577 | if (ret < 0) { |
1578 | pm_runtime_put_autosuspend(ddev->dev); | |
b9a9294b | 1579 | return ret; |
66429300 | 1580 | } |
b9a9294b | 1581 | |
b45e18ac | 1582 | amdgpu_asic_get_pcie_usage(adev, &count0, &count1); |
b9a9294b AD |
1583 | |
1584 | pm_runtime_mark_last_busy(ddev->dev); | |
1585 | pm_runtime_put_autosuspend(ddev->dev); | |
1586 | ||
a9ca9bb3 TT |
1587 | return sysfs_emit(buf, "%llu %llu %i\n", |
1588 | count0, count1, pcie_get_mps(adev->pdev)); | |
b45e18ac KR |
1589 | } |
1590 | ||
fb2dbfd2 KR |
1591 | /** |
1592 | * DOC: unique_id | |
1593 | * | |
1594 | * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU | |
1595 | * The file unique_id is used for this. | |
1596 | * This will provide a Unique ID that will persist from machine to machine | |
1597 | * | |
1598 | * NOTE: This will only work for GFX9 and newer. This file will be absent | |
1599 | * on unsupported ASICs (GFX8 and older) | |
1600 | */ | |
1601 | static ssize_t amdgpu_get_unique_id(struct device *dev, | |
1602 | struct device_attribute *attr, | |
1603 | char *buf) | |
1604 | { | |
1605 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 1606 | struct amdgpu_device *adev = drm_to_adev(ddev); |
fb2dbfd2 | 1607 | |
53b3f8f4 | 1608 | if (amdgpu_in_reset(adev)) |
48b270bb | 1609 | return -EPERM; |
d2ae842d AD |
1610 | if (adev->in_suspend && !adev->in_runpm) |
1611 | return -EPERM; | |
48b270bb | 1612 | |
fb2dbfd2 | 1613 | if (adev->unique_id) |
a9ca9bb3 | 1614 | return sysfs_emit(buf, "%016llx\n", adev->unique_id); |
fb2dbfd2 KR |
1615 | |
1616 | return 0; | |
1617 | } | |
1618 | ||
b265bdbd EQ |
1619 | /** |
1620 | * DOC: thermal_throttling_logging | |
1621 | * | |
1622 | * Thermal throttling pulls down the clock frequency and thus the performance. | |
1623 | * It's an useful mechanism to protect the chip from overheating. Since it | |
1624 | * impacts performance, the user controls whether it is enabled and if so, | |
1625 | * the log frequency. | |
1626 | * | |
1627 | * Reading back the file shows you the status(enabled or disabled) and | |
1628 | * the interval(in seconds) between each thermal logging. | |
1629 | * | |
1630 | * Writing an integer to the file, sets a new logging interval, in seconds. | |
1631 | * The value should be between 1 and 3600. If the value is less than 1, | |
1632 | * thermal logging is disabled. Values greater than 3600 are ignored. | |
1633 | */ | |
1634 | static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev, | |
1635 | struct device_attribute *attr, | |
1636 | char *buf) | |
1637 | { | |
1638 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 1639 | struct amdgpu_device *adev = drm_to_adev(ddev); |
b265bdbd | 1640 | |
a9ca9bb3 TT |
1641 | return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n", |
1642 | adev_to_drm(adev)->unique, | |
1643 | atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled", | |
1644 | adev->throttling_logging_rs.interval / HZ + 1); | |
b265bdbd EQ |
1645 | } |
1646 | ||
1647 | static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev, | |
1648 | struct device_attribute *attr, | |
1649 | const char *buf, | |
1650 | size_t count) | |
1651 | { | |
1652 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 1653 | struct amdgpu_device *adev = drm_to_adev(ddev); |
b265bdbd EQ |
1654 | long throttling_logging_interval; |
1655 | unsigned long flags; | |
1656 | int ret = 0; | |
1657 | ||
1658 | ret = kstrtol(buf, 0, &throttling_logging_interval); | |
1659 | if (ret) | |
1660 | return ret; | |
1661 | ||
1662 | if (throttling_logging_interval > 3600) | |
1663 | return -EINVAL; | |
1664 | ||
1665 | if (throttling_logging_interval > 0) { | |
1666 | raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags); | |
1667 | /* | |
1668 | * Reset the ratelimit timer internals. | |
1669 | * This can effectively restart the timer. | |
1670 | */ | |
1671 | adev->throttling_logging_rs.interval = | |
1672 | (throttling_logging_interval - 1) * HZ; | |
1673 | adev->throttling_logging_rs.begin = 0; | |
1674 | adev->throttling_logging_rs.printed = 0; | |
1675 | adev->throttling_logging_rs.missed = 0; | |
1676 | raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags); | |
1677 | ||
1678 | atomic_set(&adev->throttling_logging_enabled, 1); | |
1679 | } else { | |
1680 | atomic_set(&adev->throttling_logging_enabled, 0); | |
1681 | } | |
1682 | ||
1683 | return count; | |
1684 | } | |
1685 | ||
c3ed0e72 KL |
1686 | /** |
1687 | * DOC: apu_thermal_cap | |
1688 | * | |
1689 | * The amdgpu driver provides a sysfs API for retrieving/updating thermal | |
1690 | * limit temperature in millidegrees Celsius | |
1691 | * | |
1692 | * Reading back the file shows you core limit value | |
1693 | * | |
1694 | * Writing an integer to the file, sets a new thermal limit. The value | |
1695 | * should be between 0 and 100. If the value is less than 0 or greater | |
1696 | * than 100, then the write request will be ignored. | |
1697 | */ | |
1698 | static ssize_t amdgpu_get_apu_thermal_cap(struct device *dev, | |
1699 | struct device_attribute *attr, | |
1700 | char *buf) | |
1701 | { | |
1702 | int ret, size; | |
1703 | u32 limit; | |
1704 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1705 | struct amdgpu_device *adev = drm_to_adev(ddev); | |
1706 | ||
1707 | ret = pm_runtime_get_sync(ddev->dev); | |
1708 | if (ret < 0) { | |
1709 | pm_runtime_put_autosuspend(ddev->dev); | |
1710 | return ret; | |
1711 | } | |
1712 | ||
1713 | ret = amdgpu_dpm_get_apu_thermal_limit(adev, &limit); | |
1714 | if (!ret) | |
1715 | size = sysfs_emit(buf, "%u\n", limit); | |
1716 | else | |
1717 | size = sysfs_emit(buf, "failed to get thermal limit\n"); | |
1718 | ||
1719 | pm_runtime_mark_last_busy(ddev->dev); | |
1720 | pm_runtime_put_autosuspend(ddev->dev); | |
1721 | ||
1722 | return size; | |
1723 | } | |
1724 | ||
1725 | static ssize_t amdgpu_set_apu_thermal_cap(struct device *dev, | |
1726 | struct device_attribute *attr, | |
1727 | const char *buf, | |
1728 | size_t count) | |
1729 | { | |
1730 | int ret; | |
1731 | u32 value; | |
1732 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1733 | struct amdgpu_device *adev = drm_to_adev(ddev); | |
1734 | ||
1735 | ret = kstrtou32(buf, 10, &value); | |
1736 | if (ret) | |
1737 | return ret; | |
1738 | ||
4d2c09d6 | 1739 | if (value > 100) { |
c3ed0e72 KL |
1740 | dev_err(dev, "Invalid argument !\n"); |
1741 | return -EINVAL; | |
1742 | } | |
1743 | ||
1744 | ret = pm_runtime_get_sync(ddev->dev); | |
1745 | if (ret < 0) { | |
1746 | pm_runtime_put_autosuspend(ddev->dev); | |
1747 | return ret; | |
1748 | } | |
1749 | ||
1750 | ret = amdgpu_dpm_set_apu_thermal_limit(adev, value); | |
1751 | if (ret) { | |
1752 | dev_err(dev, "failed to update thermal limit\n"); | |
1753 | return ret; | |
1754 | } | |
1755 | ||
1756 | pm_runtime_mark_last_busy(ddev->dev); | |
1757 | pm_runtime_put_autosuspend(ddev->dev); | |
1758 | ||
1759 | return count; | |
1760 | } | |
1761 | ||
25c933b1 EQ |
1762 | /** |
1763 | * DOC: gpu_metrics | |
1764 | * | |
1765 | * The amdgpu driver provides a sysfs API for retrieving current gpu | |
1766 | * metrics data. The file gpu_metrics is used for this. Reading the | |
1767 | * file will dump all the current gpu metrics data. | |
1768 | * | |
1769 | * These data include temperature, frequency, engines utilization, | |
1770 | * power consume, throttler status, fan speed and cpu core statistics( | |
1771 | * available for APU only). That's it will give a snapshot of all sensors | |
1772 | * at the same time. | |
1773 | */ | |
1774 | static ssize_t amdgpu_get_gpu_metrics(struct device *dev, | |
1775 | struct device_attribute *attr, | |
1776 | char *buf) | |
1777 | { | |
1778 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 1779 | struct amdgpu_device *adev = drm_to_adev(ddev); |
25c933b1 EQ |
1780 | void *gpu_metrics; |
1781 | ssize_t size = 0; | |
1782 | int ret; | |
1783 | ||
53b3f8f4 | 1784 | if (amdgpu_in_reset(adev)) |
25c933b1 | 1785 | return -EPERM; |
d2ae842d AD |
1786 | if (adev->in_suspend && !adev->in_runpm) |
1787 | return -EPERM; | |
25c933b1 EQ |
1788 | |
1789 | ret = pm_runtime_get_sync(ddev->dev); | |
1790 | if (ret < 0) { | |
1791 | pm_runtime_put_autosuspend(ddev->dev); | |
1792 | return ret; | |
1793 | } | |
1794 | ||
79c65f3f | 1795 | size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics); |
25c933b1 EQ |
1796 | if (size <= 0) |
1797 | goto out; | |
1798 | ||
1799 | if (size >= PAGE_SIZE) | |
1800 | size = PAGE_SIZE - 1; | |
1801 | ||
1802 | memcpy(buf, gpu_metrics, size); | |
1803 | ||
1804 | out: | |
1805 | pm_runtime_mark_last_busy(ddev->dev); | |
1806 | pm_runtime_put_autosuspend(ddev->dev); | |
1807 | ||
1808 | return size; | |
1809 | } | |
1810 | ||
494c1432 | 1811 | static int amdgpu_show_powershift_percent(struct device *dev, |
d78c227f | 1812 | char *buf, enum amd_pp_sensors sensor) |
a7673a1c S |
1813 | { |
1814 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1815 | struct amdgpu_device *adev = drm_to_adev(ddev); | |
494c1432 S |
1816 | uint32_t ss_power; |
1817 | int r = 0, i; | |
1818 | ||
d78c227f | 1819 | r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power); |
494c1432 S |
1820 | if (r == -EOPNOTSUPP) { |
1821 | /* sensor not available on dGPU, try to read from APU */ | |
1822 | adev = NULL; | |
1823 | mutex_lock(&mgpu_info.mutex); | |
1824 | for (i = 0; i < mgpu_info.num_gpu; i++) { | |
1825 | if (mgpu_info.gpu_ins[i].adev->flags & AMD_IS_APU) { | |
1826 | adev = mgpu_info.gpu_ins[i].adev; | |
1827 | break; | |
1828 | } | |
1829 | } | |
1830 | mutex_unlock(&mgpu_info.mutex); | |
1831 | if (adev) | |
d78c227f | 1832 | r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power); |
a7673a1c S |
1833 | } |
1834 | ||
d78c227f ML |
1835 | if (r) |
1836 | return r; | |
a7673a1c | 1837 | |
d78c227f | 1838 | return sysfs_emit(buf, "%u%%\n", ss_power); |
494c1432 | 1839 | } |
d78c227f | 1840 | |
494c1432 S |
1841 | /** |
1842 | * DOC: smartshift_apu_power | |
1843 | * | |
1844 | * The amdgpu driver provides a sysfs API for reporting APU power | |
1845 | * shift in percentage if platform supports smartshift. Value 0 means that | |
1846 | * there is no powershift and values between [1-100] means that the power | |
1847 | * is shifted to APU, the percentage of boost is with respect to APU power | |
1848 | * limit on the platform. | |
1849 | */ | |
a7673a1c | 1850 | |
494c1432 S |
1851 | static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr, |
1852 | char *buf) | |
1853 | { | |
d78c227f | 1854 | return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_APU_SHARE); |
494c1432 | 1855 | } |
a7673a1c | 1856 | |
494c1432 S |
1857 | /** |
1858 | * DOC: smartshift_dgpu_power | |
1859 | * | |
1860 | * The amdgpu driver provides a sysfs API for reporting dGPU power | |
1861 | * shift in percentage if platform supports smartshift. Value 0 means that | |
1862 | * there is no powershift and values between [1-100] means that the power is | |
1863 | * shifted to dGPU, the percentage of boost is with respect to dGPU power | |
1864 | * limit on the platform. | |
1865 | */ | |
1866 | ||
1867 | static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr, | |
1868 | char *buf) | |
1869 | { | |
d78c227f | 1870 | return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_DGPU_SHARE); |
a7673a1c S |
1871 | } |
1872 | ||
30d95a37 S |
1873 | /** |
1874 | * DOC: smartshift_bias | |
1875 | * | |
1876 | * The amdgpu driver provides a sysfs API for reporting the | |
1877 | * smartshift(SS2.0) bias level. The value ranges from -100 to 100 | |
1878 | * and the default is 0. -100 sets maximum preference to APU | |
1879 | * and 100 sets max perference to dGPU. | |
1880 | */ | |
1881 | ||
1882 | static ssize_t amdgpu_get_smartshift_bias(struct device *dev, | |
1883 | struct device_attribute *attr, | |
1884 | char *buf) | |
1885 | { | |
1886 | int r = 0; | |
1887 | ||
1888 | r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias); | |
1889 | ||
1890 | return r; | |
1891 | } | |
1892 | ||
1893 | static ssize_t amdgpu_set_smartshift_bias(struct device *dev, | |
1894 | struct device_attribute *attr, | |
1895 | const char *buf, size_t count) | |
1896 | { | |
1897 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1898 | struct amdgpu_device *adev = drm_to_adev(ddev); | |
1899 | int r = 0; | |
1900 | int bias = 0; | |
1901 | ||
1902 | if (amdgpu_in_reset(adev)) | |
1903 | return -EPERM; | |
1904 | if (adev->in_suspend && !adev->in_runpm) | |
1905 | return -EPERM; | |
1906 | ||
1907 | r = pm_runtime_get_sync(ddev->dev); | |
1908 | if (r < 0) { | |
1909 | pm_runtime_put_autosuspend(ddev->dev); | |
1910 | return r; | |
1911 | } | |
1912 | ||
1913 | r = kstrtoint(buf, 10, &bias); | |
1914 | if (r) | |
1915 | goto out; | |
1916 | ||
1917 | if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS) | |
1918 | bias = AMDGPU_SMARTSHIFT_MAX_BIAS; | |
1919 | else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS) | |
1920 | bias = AMDGPU_SMARTSHIFT_MIN_BIAS; | |
1921 | ||
1922 | amdgpu_smartshift_bias = bias; | |
1923 | r = count; | |
1924 | ||
bd4b9bb7 | 1925 | /* TODO: update bias level with SMU message */ |
30d95a37 S |
1926 | |
1927 | out: | |
1928 | pm_runtime_mark_last_busy(ddev->dev); | |
1929 | pm_runtime_put_autosuspend(ddev->dev); | |
1930 | return r; | |
1931 | } | |
1932 | ||
a7673a1c S |
1933 | static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, |
1934 | uint32_t mask, enum amdgpu_device_attr_states *states) | |
1935 | { | |
494c1432 | 1936 | if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev))) |
a7673a1c S |
1937 | *states = ATTR_STATE_UNSUPPORTED; |
1938 | ||
1939 | return 0; | |
1940 | } | |
1941 | ||
30d95a37 S |
1942 | static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, |
1943 | uint32_t mask, enum amdgpu_device_attr_states *states) | |
1944 | { | |
d78c227f | 1945 | uint32_t ss_power; |
30d95a37 S |
1946 | |
1947 | if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev))) | |
1948 | *states = ATTR_STATE_UNSUPPORTED; | |
d78c227f ML |
1949 | else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE, |
1950 | (void *)&ss_power)) | |
30d95a37 | 1951 | *states = ATTR_STATE_UNSUPPORTED; |
d78c227f ML |
1952 | else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE, |
1953 | (void *)&ss_power)) | |
30d95a37 S |
1954 | *states = ATTR_STATE_UNSUPPORTED; |
1955 | ||
1956 | return 0; | |
1957 | } | |
1958 | ||
4e01847c KW |
1959 | static struct amdgpu_device_attr amdgpu_device_attrs[] = { |
1960 | AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), | |
4215a119 | 1961 | AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), |
7884d0e9 JG |
1962 | AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), |
1963 | AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), | |
1964 | AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), | |
1965 | AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), | |
4e01847c KW |
1966 | AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), |
1967 | AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), | |
1968 | AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), | |
1969 | AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), | |
9577b0ec | 1970 | AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), |
d7001e72 | 1971 | AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk1, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), |
9577b0ec | 1972 | AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), |
d7001e72 | 1973 | AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk1, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), |
f3527a64 MN |
1974 | AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), |
1975 | AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), | |
4e01847c KW |
1976 | AMDGPU_DEVICE_ATTR_RW(pp_sclk_od, ATTR_FLAG_BASIC), |
1977 | AMDGPU_DEVICE_ATTR_RW(pp_mclk_od, ATTR_FLAG_BASIC), | |
ac82902d | 1978 | AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), |
4e01847c | 1979 | AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage, ATTR_FLAG_BASIC), |
ac82902d VC |
1980 | AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), |
1981 | AMDGPU_DEVICE_ATTR_RO(mem_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), | |
4e01847c | 1982 | AMDGPU_DEVICE_ATTR_RO(pcie_bw, ATTR_FLAG_BASIC), |
ac82902d VC |
1983 | AMDGPU_DEVICE_ATTR_RW(pp_features, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), |
1984 | AMDGPU_DEVICE_ATTR_RO(unique_id, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), | |
1985 | AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), | |
c3ed0e72 | 1986 | AMDGPU_DEVICE_ATTR_RW(apu_thermal_cap, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), |
ac82902d | 1987 | AMDGPU_DEVICE_ATTR_RO(gpu_metrics, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), |
a7673a1c S |
1988 | AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power, ATTR_FLAG_BASIC, |
1989 | .attr_update = ss_power_attr_update), | |
1990 | AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power, ATTR_FLAG_BASIC, | |
1991 | .attr_update = ss_power_attr_update), | |
30d95a37 S |
1992 | AMDGPU_DEVICE_ATTR_RW(smartshift_bias, ATTR_FLAG_BASIC, |
1993 | .attr_update = ss_bias_attr_update), | |
4e01847c KW |
1994 | }; |
1995 | ||
1996 | static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, | |
ba02fd6b | 1997 | uint32_t mask, enum amdgpu_device_attr_states *states) |
4e01847c KW |
1998 | { |
1999 | struct device_attribute *dev_attr = &attr->dev_attr; | |
8ecad8d6 LL |
2000 | uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0]; |
2001 | uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; | |
4e01847c | 2002 | const char *attr_name = dev_attr->attr.name; |
4e01847c KW |
2003 | |
2004 | if (!(attr->flags & mask)) { | |
ba02fd6b | 2005 | *states = ATTR_STATE_UNSUPPORTED; |
4e01847c KW |
2006 | return 0; |
2007 | } | |
2008 | ||
2009 | #define DEVICE_ATTR_IS(_name) (!strcmp(attr_name, #_name)) | |
2010 | ||
2011 | if (DEVICE_ATTR_IS(pp_dpm_socclk)) { | |
8ecad8d6 | 2012 | if (gc_ver < IP_VERSION(9, 0, 0)) |
ba02fd6b | 2013 | *states = ATTR_STATE_UNSUPPORTED; |
4e01847c | 2014 | } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) { |
8ecad8d6 | 2015 | if (gc_ver < IP_VERSION(9, 0, 0) || |
0127ab1b | 2016 | !amdgpu_device_has_display_hardware(adev)) |
ba02fd6b | 2017 | *states = ATTR_STATE_UNSUPPORTED; |
4e01847c | 2018 | } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) { |
8ecad8d6 | 2019 | if (mp1_ver < IP_VERSION(10, 0, 0)) |
ba02fd6b | 2020 | *states = ATTR_STATE_UNSUPPORTED; |
4e01847c | 2021 | } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) { |
ba02fd6b | 2022 | *states = ATTR_STATE_UNSUPPORTED; |
79c65f3f | 2023 | if (amdgpu_dpm_is_overdrive_supported(adev)) |
ba02fd6b | 2024 | *states = ATTR_STATE_SUPPORTED; |
4e01847c | 2025 | } else if (DEVICE_ATTR_IS(mem_busy_percent)) { |
8ecad8d6 | 2026 | if (adev->flags & AMD_IS_APU || gc_ver == IP_VERSION(9, 0, 1)) |
ba02fd6b | 2027 | *states = ATTR_STATE_UNSUPPORTED; |
4e01847c KW |
2028 | } else if (DEVICE_ATTR_IS(pcie_bw)) { |
2029 | /* PCIe Perf counters won't work on APU nodes */ | |
2030 | if (adev->flags & AMD_IS_APU) | |
ba02fd6b | 2031 | *states = ATTR_STATE_UNSUPPORTED; |
4e01847c | 2032 | } else if (DEVICE_ATTR_IS(unique_id)) { |
60044748 KR |
2033 | switch (gc_ver) { |
2034 | case IP_VERSION(9, 0, 1): | |
2035 | case IP_VERSION(9, 4, 0): | |
2036 | case IP_VERSION(9, 4, 1): | |
2037 | case IP_VERSION(9, 4, 2): | |
baf65745 | 2038 | case IP_VERSION(9, 4, 3): |
ebd9c071 | 2039 | case IP_VERSION(10, 3, 0): |
276c03a0 | 2040 | case IP_VERSION(11, 0, 0): |
35e67ca6 KR |
2041 | case IP_VERSION(11, 0, 1): |
2042 | case IP_VERSION(11, 0, 2): | |
4953856f | 2043 | case IP_VERSION(11, 0, 3): |
60044748 KR |
2044 | *states = ATTR_STATE_SUPPORTED; |
2045 | break; | |
2046 | default: | |
ba02fd6b | 2047 | *states = ATTR_STATE_UNSUPPORTED; |
60044748 | 2048 | } |
4e01847c | 2049 | } else if (DEVICE_ATTR_IS(pp_features)) { |
fc8e84a2 LL |
2050 | if ((adev->flags & AMD_IS_APU && |
2051 | gc_ver != IP_VERSION(9, 4, 3)) || | |
2052 | gc_ver < IP_VERSION(9, 0, 0)) | |
ba02fd6b | 2053 | *states = ATTR_STATE_UNSUPPORTED; |
25c933b1 | 2054 | } else if (DEVICE_ATTR_IS(gpu_metrics)) { |
8ecad8d6 | 2055 | if (gc_ver < IP_VERSION(9, 1, 0)) |
25c933b1 | 2056 | *states = ATTR_STATE_UNSUPPORTED; |
9577b0ec | 2057 | } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) { |
8ecad8d6 | 2058 | if (!(gc_ver == IP_VERSION(10, 3, 1) || |
a68bec2c | 2059 | gc_ver == IP_VERSION(10, 3, 0) || |
64440743 | 2060 | gc_ver == IP_VERSION(10, 1, 2) || |
3929f338 | 2061 | gc_ver == IP_VERSION(11, 0, 0) || |
2f68c414 | 2062 | gc_ver == IP_VERSION(11, 0, 2) || |
707b570f AK |
2063 | gc_ver == IP_VERSION(11, 0, 3) || |
2064 | gc_ver == IP_VERSION(9, 4, 3))) | |
9577b0ec | 2065 | *states = ATTR_STATE_UNSUPPORTED; |
0b872f65 TL |
2066 | } else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) { |
2067 | if (!((gc_ver == IP_VERSION(10, 3, 1) || | |
feae1bd8 TL |
2068 | gc_ver == IP_VERSION(10, 3, 0) || |
2069 | gc_ver == IP_VERSION(11, 0, 2) || | |
2070 | gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2)) | |
0b872f65 | 2071 | *states = ATTR_STATE_UNSUPPORTED; |
9577b0ec | 2072 | } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) { |
8ecad8d6 | 2073 | if (!(gc_ver == IP_VERSION(10, 3, 1) || |
a68bec2c | 2074 | gc_ver == IP_VERSION(10, 3, 0) || |
64440743 | 2075 | gc_ver == IP_VERSION(10, 1, 2) || |
3929f338 | 2076 | gc_ver == IP_VERSION(11, 0, 0) || |
2f68c414 | 2077 | gc_ver == IP_VERSION(11, 0, 2) || |
707b570f AK |
2078 | gc_ver == IP_VERSION(11, 0, 3) || |
2079 | gc_ver == IP_VERSION(9, 4, 3))) | |
9577b0ec | 2080 | *states = ATTR_STATE_UNSUPPORTED; |
0b872f65 TL |
2081 | } else if (DEVICE_ATTR_IS(pp_dpm_dclk1)) { |
2082 | if (!((gc_ver == IP_VERSION(10, 3, 1) || | |
feae1bd8 TL |
2083 | gc_ver == IP_VERSION(10, 3, 0) || |
2084 | gc_ver == IP_VERSION(11, 0, 2) || | |
2085 | gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2)) | |
0b872f65 | 2086 | *states = ATTR_STATE_UNSUPPORTED; |
a7505591 | 2087 | } else if (DEVICE_ATTR_IS(pp_power_profile_mode)) { |
79c65f3f | 2088 | if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP) |
a7505591 | 2089 | *states = ATTR_STATE_UNSUPPORTED; |
1b852572 DS |
2090 | else if (gc_ver == IP_VERSION(10, 3, 0) && amdgpu_sriov_vf(adev)) |
2091 | *states = ATTR_STATE_UNSUPPORTED; | |
4e01847c KW |
2092 | } |
2093 | ||
8ecad8d6 LL |
2094 | switch (gc_ver) { |
2095 | case IP_VERSION(9, 4, 1): | |
2096 | case IP_VERSION(9, 4, 2): | |
1d0e622f | 2097 | /* the Mi series card does not support standalone mclk/socclk/fclk level setting */ |
4e01847c KW |
2098 | if (DEVICE_ATTR_IS(pp_dpm_mclk) || |
2099 | DEVICE_ATTR_IS(pp_dpm_socclk) || | |
2100 | DEVICE_ATTR_IS(pp_dpm_fclk)) { | |
2101 | dev_attr->attr.mode &= ~S_IWUGO; | |
2102 | dev_attr->store = NULL; | |
2103 | } | |
1d0e622f | 2104 | break; |
1b852572 DS |
2105 | case IP_VERSION(10, 3, 0): |
2106 | if (DEVICE_ATTR_IS(power_dpm_force_performance_level) && | |
2107 | amdgpu_sriov_vf(adev)) { | |
2108 | dev_attr->attr.mode &= ~0222; | |
2109 | dev_attr->store = NULL; | |
2110 | } | |
2111 | break; | |
1d0e622f KW |
2112 | default: |
2113 | break; | |
4e01847c KW |
2114 | } |
2115 | ||
ede14a1b DP |
2116 | if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) { |
2117 | /* SMU MP1 does not support dcefclk level setting */ | |
8ecad8d6 | 2118 | if (gc_ver >= IP_VERSION(10, 0, 0)) { |
ede14a1b DP |
2119 | dev_attr->attr.mode &= ~S_IWUGO; |
2120 | dev_attr->store = NULL; | |
2121 | } | |
2122 | } | |
2123 | ||
e610941c YY |
2124 | /* setting should not be allowed from VF if not in one VF mode */ |
2125 | if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { | |
11c9cc95 MN |
2126 | dev_attr->attr.mode &= ~S_IWUGO; |
2127 | dev_attr->store = NULL; | |
2128 | } | |
2129 | ||
4e01847c KW |
2130 | #undef DEVICE_ATTR_IS |
2131 | ||
2132 | return 0; | |
2133 | } | |
2134 | ||
2135 | ||
2136 | static int amdgpu_device_attr_create(struct amdgpu_device *adev, | |
2137 | struct amdgpu_device_attr *attr, | |
ba02fd6b | 2138 | uint32_t mask, struct list_head *attr_list) |
4e01847c KW |
2139 | { |
2140 | int ret = 0; | |
ba02fd6b KW |
2141 | enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED; |
2142 | struct amdgpu_device_attr_entry *attr_entry; | |
25e6373a YW |
2143 | struct device_attribute *dev_attr; |
2144 | const char *name; | |
ba02fd6b | 2145 | |
4e01847c | 2146 | int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, |
ba02fd6b | 2147 | uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update; |
4e01847c | 2148 | |
25e6373a YW |
2149 | if (!attr) |
2150 | return -EINVAL; | |
2151 | ||
2152 | dev_attr = &attr->dev_attr; | |
2153 | name = dev_attr->attr.name; | |
4e01847c | 2154 | |
8a81028b | 2155 | attr_update = attr->attr_update ? attr->attr_update : default_attr_update; |
4e01847c | 2156 | |
ba02fd6b | 2157 | ret = attr_update(adev, attr, mask, &attr_states); |
4e01847c KW |
2158 | if (ret) { |
2159 | dev_err(adev->dev, "failed to update device file %s, ret = %d\n", | |
2160 | name, ret); | |
2161 | return ret; | |
2162 | } | |
2163 | ||
ba02fd6b | 2164 | if (attr_states == ATTR_STATE_UNSUPPORTED) |
4e01847c KW |
2165 | return 0; |
2166 | ||
2167 | ret = device_create_file(adev->dev, dev_attr); | |
2168 | if (ret) { | |
2169 | dev_err(adev->dev, "failed to create device file %s, ret = %d\n", | |
2170 | name, ret); | |
2171 | } | |
2172 | ||
ba02fd6b KW |
2173 | attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL); |
2174 | if (!attr_entry) | |
2175 | return -ENOMEM; | |
2176 | ||
2177 | attr_entry->attr = attr; | |
2178 | INIT_LIST_HEAD(&attr_entry->entry); | |
2179 | ||
2180 | list_add_tail(&attr_entry->entry, attr_list); | |
4e01847c KW |
2181 | |
2182 | return ret; | |
2183 | } | |
2184 | ||
2185 | static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr) | |
2186 | { | |
2187 | struct device_attribute *dev_attr = &attr->dev_attr; | |
2188 | ||
4e01847c | 2189 | device_remove_file(adev->dev, dev_attr); |
4e01847c KW |
2190 | } |
2191 | ||
ba02fd6b KW |
2192 | static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev, |
2193 | struct list_head *attr_list); | |
2194 | ||
4e01847c KW |
2195 | static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev, |
2196 | struct amdgpu_device_attr *attrs, | |
2197 | uint32_t counts, | |
ba02fd6b KW |
2198 | uint32_t mask, |
2199 | struct list_head *attr_list) | |
4e01847c KW |
2200 | { |
2201 | int ret = 0; | |
2202 | uint32_t i = 0; | |
2203 | ||
2204 | for (i = 0; i < counts; i++) { | |
ba02fd6b | 2205 | ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list); |
4e01847c KW |
2206 | if (ret) |
2207 | goto failed; | |
2208 | } | |
2209 | ||
2210 | return 0; | |
2211 | ||
2212 | failed: | |
ba02fd6b | 2213 | amdgpu_device_attr_remove_groups(adev, attr_list); |
4e01847c KW |
2214 | |
2215 | return ret; | |
2216 | } | |
2217 | ||
2218 | static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev, | |
ba02fd6b | 2219 | struct list_head *attr_list) |
4e01847c | 2220 | { |
ba02fd6b | 2221 | struct amdgpu_device_attr_entry *entry, *entry_tmp; |
4e01847c | 2222 | |
ba02fd6b KW |
2223 | if (list_empty(attr_list)) |
2224 | return ; | |
2225 | ||
2226 | list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) { | |
2227 | amdgpu_device_attr_remove(adev, entry->attr); | |
2228 | list_del(&entry->entry); | |
2229 | kfree(entry); | |
2230 | } | |
4e01847c | 2231 | } |
e3933f26 | 2232 | |
d38ceaf9 AD |
2233 | static ssize_t amdgpu_hwmon_show_temp(struct device *dev, |
2234 | struct device_attribute *attr, | |
2235 | char *buf) | |
2236 | { | |
2237 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
a34d1166 | 2238 | int channel = to_sensor_dev_attr(attr)->index; |
d78c227f | 2239 | int r, temp = 0; |
48b270bb | 2240 | |
a34d1166 EQ |
2241 | if (channel >= PP_TEMP_MAX) |
2242 | return -EINVAL; | |
2243 | ||
2244 | switch (channel) { | |
2245 | case PP_TEMP_JUNCTION: | |
2246 | /* get current junction temperature */ | |
d78c227f ML |
2247 | r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP, |
2248 | (void *)&temp); | |
a34d1166 EQ |
2249 | break; |
2250 | case PP_TEMP_EDGE: | |
2251 | /* get current edge temperature */ | |
d78c227f ML |
2252 | r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_EDGE_TEMP, |
2253 | (void *)&temp); | |
a34d1166 EQ |
2254 | break; |
2255 | case PP_TEMP_MEM: | |
2256 | /* get current memory temperature */ | |
d78c227f ML |
2257 | r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_TEMP, |
2258 | (void *)&temp); | |
b9a9294b AD |
2259 | break; |
2260 | default: | |
2261 | r = -EINVAL; | |
a34d1166 EQ |
2262 | break; |
2263 | } | |
d38ceaf9 | 2264 | |
b9a9294b AD |
2265 | if (r) |
2266 | return r; | |
2267 | ||
a9ca9bb3 | 2268 | return sysfs_emit(buf, "%d\n", temp); |
d38ceaf9 AD |
2269 | } |
2270 | ||
2271 | static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev, | |
2272 | struct device_attribute *attr, | |
2273 | char *buf) | |
2274 | { | |
2275 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
2276 | int hyst = to_sensor_dev_attr(attr)->index; | |
2277 | int temp; | |
2278 | ||
2279 | if (hyst) | |
2280 | temp = adev->pm.dpm.thermal.min_temp; | |
2281 | else | |
2282 | temp = adev->pm.dpm.thermal.max_temp; | |
2283 | ||
a9ca9bb3 | 2284 | return sysfs_emit(buf, "%d\n", temp); |
d38ceaf9 AD |
2285 | } |
2286 | ||
437ccd17 EQ |
2287 | static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev, |
2288 | struct device_attribute *attr, | |
2289 | char *buf) | |
2290 | { | |
2291 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
2292 | int hyst = to_sensor_dev_attr(attr)->index; | |
2293 | int temp; | |
2294 | ||
2295 | if (hyst) | |
2296 | temp = adev->pm.dpm.thermal.min_hotspot_temp; | |
2297 | else | |
2298 | temp = adev->pm.dpm.thermal.max_hotspot_crit_temp; | |
2299 | ||
a9ca9bb3 | 2300 | return sysfs_emit(buf, "%d\n", temp); |
437ccd17 EQ |
2301 | } |
2302 | ||
2303 | static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev, | |
2304 | struct device_attribute *attr, | |
2305 | char *buf) | |
2306 | { | |
2307 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
2308 | int hyst = to_sensor_dev_attr(attr)->index; | |
2309 | int temp; | |
2310 | ||
2311 | if (hyst) | |
2312 | temp = adev->pm.dpm.thermal.min_mem_temp; | |
2313 | else | |
2314 | temp = adev->pm.dpm.thermal.max_mem_crit_temp; | |
2315 | ||
a9ca9bb3 | 2316 | return sysfs_emit(buf, "%d\n", temp); |
437ccd17 EQ |
2317 | } |
2318 | ||
2adc1156 EQ |
2319 | static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev, |
2320 | struct device_attribute *attr, | |
2321 | char *buf) | |
2322 | { | |
2323 | int channel = to_sensor_dev_attr(attr)->index; | |
2324 | ||
2325 | if (channel >= PP_TEMP_MAX) | |
2326 | return -EINVAL; | |
2327 | ||
a9ca9bb3 | 2328 | return sysfs_emit(buf, "%s\n", temp_label[channel].label); |
2adc1156 EQ |
2329 | } |
2330 | ||
901cb599 EQ |
2331 | static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev, |
2332 | struct device_attribute *attr, | |
2333 | char *buf) | |
2334 | { | |
2335 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
2336 | int channel = to_sensor_dev_attr(attr)->index; | |
2337 | int temp = 0; | |
2338 | ||
2339 | if (channel >= PP_TEMP_MAX) | |
2340 | return -EINVAL; | |
2341 | ||
2342 | switch (channel) { | |
2343 | case PP_TEMP_JUNCTION: | |
2344 | temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp; | |
2345 | break; | |
2346 | case PP_TEMP_EDGE: | |
2347 | temp = adev->pm.dpm.thermal.max_edge_emergency_temp; | |
2348 | break; | |
2349 | case PP_TEMP_MEM: | |
2350 | temp = adev->pm.dpm.thermal.max_mem_emergency_temp; | |
2351 | break; | |
2352 | } | |
2353 | ||
a9ca9bb3 | 2354 | return sysfs_emit(buf, "%d\n", temp); |
901cb599 EQ |
2355 | } |
2356 | ||
d38ceaf9 AD |
2357 | static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev, |
2358 | struct device_attribute *attr, | |
2359 | char *buf) | |
2360 | { | |
2361 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
2362 | u32 pwm_mode = 0; | |
b9a9294b AD |
2363 | int ret; |
2364 | ||
53b3f8f4 | 2365 | if (amdgpu_in_reset(adev)) |
48b270bb | 2366 | return -EPERM; |
d2ae842d AD |
2367 | if (adev->in_suspend && !adev->in_runpm) |
2368 | return -EPERM; | |
48b270bb | 2369 | |
4a580877 | 2370 | ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); |
66429300 | 2371 | if (ret < 0) { |
4a580877 | 2372 | pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); |
b9a9294b | 2373 | return ret; |
66429300 | 2374 | } |
c9ffa427 | 2375 | |
79c65f3f | 2376 | ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); |
f46587bc | 2377 | |
4a580877 LT |
2378 | pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); |
2379 | pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); | |
b9a9294b | 2380 | |
79c65f3f EQ |
2381 | if (ret) |
2382 | return -EINVAL; | |
2383 | ||
fdf8eea5 | 2384 | return sysfs_emit(buf, "%u\n", pwm_mode); |
d38ceaf9 AD |
2385 | } |
2386 | ||
2387 | static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev, | |
2388 | struct device_attribute *attr, | |
2389 | const char *buf, | |
2390 | size_t count) | |
2391 | { | |
2392 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
b9a9294b | 2393 | int err, ret; |
d38ceaf9 AD |
2394 | int value; |
2395 | ||
53b3f8f4 | 2396 | if (amdgpu_in_reset(adev)) |
48b270bb | 2397 | return -EPERM; |
d2ae842d AD |
2398 | if (adev->in_suspend && !adev->in_runpm) |
2399 | return -EPERM; | |
48b270bb | 2400 | |
fcd90fee EQ |
2401 | err = kstrtoint(buf, 10, &value); |
2402 | if (err) | |
2403 | return err; | |
a76ff5af | 2404 | |
4a580877 | 2405 | ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); |
66429300 | 2406 | if (ret < 0) { |
4a580877 | 2407 | pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); |
b9a9294b | 2408 | return ret; |
66429300 | 2409 | } |
b9a9294b | 2410 | |
79c65f3f | 2411 | ret = amdgpu_dpm_set_fan_control_mode(adev, value); |
f46587bc | 2412 | |
4a580877 LT |
2413 | pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); |
2414 | pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); | |
b9a9294b | 2415 | |
79c65f3f EQ |
2416 | if (ret) |
2417 | return -EINVAL; | |
2418 | ||
d38ceaf9 AD |
2419 | return count; |
2420 | } | |
2421 | ||
2422 | static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev, | |
2423 | struct device_attribute *attr, | |
2424 | char *buf) | |
2425 | { | |
fdf8eea5 | 2426 | return sysfs_emit(buf, "%i\n", 0); |
d38ceaf9 AD |
2427 | } |
2428 | ||
2429 | static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev, | |
2430 | struct device_attribute *attr, | |
2431 | char *buf) | |
2432 | { | |
fdf8eea5 | 2433 | return sysfs_emit(buf, "%i\n", 255); |
d38ceaf9 AD |
2434 | } |
2435 | ||
2436 | static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev, | |
2437 | struct device_attribute *attr, | |
2438 | const char *buf, size_t count) | |
2439 | { | |
2440 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
2441 | int err; | |
2442 | u32 value; | |
b8a9c003 | 2443 | u32 pwm_mode; |
d38ceaf9 | 2444 | |
53b3f8f4 | 2445 | if (amdgpu_in_reset(adev)) |
48b270bb | 2446 | return -EPERM; |
d2ae842d AD |
2447 | if (adev->in_suspend && !adev->in_runpm) |
2448 | return -EPERM; | |
48b270bb | 2449 | |
79c65f3f EQ |
2450 | err = kstrtou32(buf, 10, &value); |
2451 | if (err) | |
2452 | return err; | |
2453 | ||
4a580877 | 2454 | err = pm_runtime_get_sync(adev_to_drm(adev)->dev); |
66429300 | 2455 | if (err < 0) { |
4a580877 | 2456 | pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); |
b9a9294b | 2457 | return err; |
66429300 | 2458 | } |
b9a9294b | 2459 | |
79c65f3f EQ |
2460 | err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); |
2461 | if (err) | |
2462 | goto out; | |
2463 | ||
b8a9c003 RZ |
2464 | if (pwm_mode != AMD_FAN_CTRL_MANUAL) { |
2465 | pr_info("manual fan speed control should be enabled first\n"); | |
79c65f3f EQ |
2466 | err = -EINVAL; |
2467 | goto out; | |
b8a9c003 RZ |
2468 | } |
2469 | ||
79c65f3f | 2470 | err = amdgpu_dpm_set_fan_speed_pwm(adev, value); |
b9a9294b | 2471 | |
79c65f3f | 2472 | out: |
4a580877 LT |
2473 | pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); |
2474 | pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); | |
b9a9294b AD |
2475 | |
2476 | if (err) | |
2477 | return err; | |
d38ceaf9 AD |
2478 | |
2479 | return count; | |
2480 | } | |
2481 | ||
2482 | static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev, | |
2483 | struct device_attribute *attr, | |
2484 | char *buf) | |
2485 | { | |
2486 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
2487 | int err; | |
cd4d7464 | 2488 | u32 speed = 0; |
d38ceaf9 | 2489 | |
53b3f8f4 | 2490 | if (amdgpu_in_reset(adev)) |
48b270bb | 2491 | return -EPERM; |
d2ae842d AD |
2492 | if (adev->in_suspend && !adev->in_runpm) |
2493 | return -EPERM; | |
48b270bb | 2494 | |
4a580877 | 2495 | err = pm_runtime_get_sync(adev_to_drm(adev)->dev); |
66429300 | 2496 | if (err < 0) { |
4a580877 | 2497 | pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); |
b9a9294b | 2498 | return err; |
66429300 | 2499 | } |
5ec36e2d | 2500 | |
79c65f3f | 2501 | err = amdgpu_dpm_get_fan_speed_pwm(adev, &speed); |
b9a9294b | 2502 | |
4a580877 LT |
2503 | pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); |
2504 | pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); | |
b9a9294b AD |
2505 | |
2506 | if (err) | |
2507 | return err; | |
d38ceaf9 | 2508 | |
fdf8eea5 | 2509 | return sysfs_emit(buf, "%i\n", speed); |
d38ceaf9 AD |
2510 | } |
2511 | ||
81c1514b GI |
2512 | static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev, |
2513 | struct device_attribute *attr, | |
2514 | char *buf) | |
2515 | { | |
2516 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
2517 | int err; | |
cd4d7464 | 2518 | u32 speed = 0; |
81c1514b | 2519 | |
53b3f8f4 | 2520 | if (amdgpu_in_reset(adev)) |
48b270bb | 2521 | return -EPERM; |
d2ae842d AD |
2522 | if (adev->in_suspend && !adev->in_runpm) |
2523 | return -EPERM; | |
48b270bb | 2524 | |
4a580877 | 2525 | err = pm_runtime_get_sync(adev_to_drm(adev)->dev); |
66429300 | 2526 | if (err < 0) { |
4a580877 | 2527 | pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); |
b9a9294b | 2528 | return err; |
66429300 | 2529 | } |
5ec36e2d | 2530 | |
79c65f3f | 2531 | err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed); |
b9a9294b | 2532 | |
4a580877 LT |
2533 | pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); |
2534 | pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); | |
b9a9294b AD |
2535 | |
2536 | if (err) | |
2537 | return err; | |
81c1514b | 2538 | |
fdf8eea5 | 2539 | return sysfs_emit(buf, "%i\n", speed); |
81c1514b GI |
2540 | } |
2541 | ||
c2870527 RZ |
2542 | static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev, |
2543 | struct device_attribute *attr, | |
2544 | char *buf) | |
2545 | { | |
2546 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
2547 | u32 min_rpm = 0; | |
c2870527 RZ |
2548 | int r; |
2549 | ||
d78c227f ML |
2550 | r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM, |
2551 | (void *)&min_rpm); | |
b9a9294b | 2552 | |
c2870527 RZ |
2553 | if (r) |
2554 | return r; | |
2555 | ||
a9ca9bb3 | 2556 | return sysfs_emit(buf, "%d\n", min_rpm); |
c2870527 RZ |
2557 | } |
2558 | ||
2559 | static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev, | |
2560 | struct device_attribute *attr, | |
2561 | char *buf) | |
2562 | { | |
2563 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
2564 | u32 max_rpm = 0; | |
c2870527 RZ |
2565 | int r; |
2566 | ||
d78c227f ML |
2567 | r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM, |
2568 | (void *)&max_rpm); | |
b9a9294b | 2569 | |
c2870527 RZ |
2570 | if (r) |
2571 | return r; | |
2572 | ||
a9ca9bb3 | 2573 | return sysfs_emit(buf, "%d\n", max_rpm); |
c2870527 RZ |
2574 | } |
2575 | ||
2576 | static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev, | |
2577 | struct device_attribute *attr, | |
2578 | char *buf) | |
2579 | { | |
2580 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
2581 | int err; | |
2582 | u32 rpm = 0; | |
c2870527 | 2583 | |
53b3f8f4 | 2584 | if (amdgpu_in_reset(adev)) |
48b270bb | 2585 | return -EPERM; |
d2ae842d AD |
2586 | if (adev->in_suspend && !adev->in_runpm) |
2587 | return -EPERM; | |
48b270bb | 2588 | |
4a580877 | 2589 | err = pm_runtime_get_sync(adev_to_drm(adev)->dev); |
66429300 | 2590 | if (err < 0) { |
4a580877 | 2591 | pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); |
b9a9294b | 2592 | return err; |
66429300 | 2593 | } |
c2870527 | 2594 | |
79c65f3f | 2595 | err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm); |
b9a9294b | 2596 | |
4a580877 LT |
2597 | pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); |
2598 | pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); | |
b9a9294b AD |
2599 | |
2600 | if (err) | |
2601 | return err; | |
c2870527 | 2602 | |
fdf8eea5 | 2603 | return sysfs_emit(buf, "%i\n", rpm); |
c2870527 RZ |
2604 | } |
2605 | ||
2606 | static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev, | |
2607 | struct device_attribute *attr, | |
2608 | const char *buf, size_t count) | |
2609 | { | |
2610 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
2611 | int err; | |
2612 | u32 value; | |
2613 | u32 pwm_mode; | |
2614 | ||
53b3f8f4 | 2615 | if (amdgpu_in_reset(adev)) |
48b270bb | 2616 | return -EPERM; |
d2ae842d AD |
2617 | if (adev->in_suspend && !adev->in_runpm) |
2618 | return -EPERM; | |
48b270bb | 2619 | |
79c65f3f EQ |
2620 | err = kstrtou32(buf, 10, &value); |
2621 | if (err) | |
2622 | return err; | |
2623 | ||
4a580877 | 2624 | err = pm_runtime_get_sync(adev_to_drm(adev)->dev); |
66429300 | 2625 | if (err < 0) { |
4a580877 | 2626 | pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); |
b9a9294b | 2627 | return err; |
66429300 | 2628 | } |
b9a9294b | 2629 | |
79c65f3f EQ |
2630 | err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); |
2631 | if (err) | |
2632 | goto out; | |
96026ce0 | 2633 | |
b9a9294b | 2634 | if (pwm_mode != AMD_FAN_CTRL_MANUAL) { |
79c65f3f EQ |
2635 | err = -ENODATA; |
2636 | goto out; | |
b9a9294b | 2637 | } |
c2870527 | 2638 | |
79c65f3f | 2639 | err = amdgpu_dpm_set_fan_speed_rpm(adev, value); |
b9a9294b | 2640 | |
79c65f3f | 2641 | out: |
4a580877 LT |
2642 | pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); |
2643 | pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); | |
b9a9294b AD |
2644 | |
2645 | if (err) | |
2646 | return err; | |
c2870527 RZ |
2647 | |
2648 | return count; | |
2649 | } | |
2650 | ||
2651 | static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev, | |
2652 | struct device_attribute *attr, | |
2653 | char *buf) | |
2654 | { | |
2655 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
2656 | u32 pwm_mode = 0; | |
b9a9294b AD |
2657 | int ret; |
2658 | ||
53b3f8f4 | 2659 | if (amdgpu_in_reset(adev)) |
48b270bb | 2660 | return -EPERM; |
d2ae842d AD |
2661 | if (adev->in_suspend && !adev->in_runpm) |
2662 | return -EPERM; | |
48b270bb | 2663 | |
4a580877 | 2664 | ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); |
66429300 | 2665 | if (ret < 0) { |
4a580877 | 2666 | pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); |
b9a9294b | 2667 | return ret; |
66429300 | 2668 | } |
c2870527 | 2669 | |
79c65f3f | 2670 | ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); |
f46587bc | 2671 | |
4a580877 LT |
2672 | pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); |
2673 | pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); | |
b9a9294b | 2674 | |
79c65f3f EQ |
2675 | if (ret) |
2676 | return -EINVAL; | |
2677 | ||
fdf8eea5 | 2678 | return sysfs_emit(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1); |
c2870527 RZ |
2679 | } |
2680 | ||
2681 | static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev, | |
2682 | struct device_attribute *attr, | |
2683 | const char *buf, | |
2684 | size_t count) | |
2685 | { | |
2686 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
2687 | int err; | |
2688 | int value; | |
2689 | u32 pwm_mode; | |
2690 | ||
53b3f8f4 | 2691 | if (amdgpu_in_reset(adev)) |
48b270bb | 2692 | return -EPERM; |
d2ae842d AD |
2693 | if (adev->in_suspend && !adev->in_runpm) |
2694 | return -EPERM; | |
48b270bb | 2695 | |
c2870527 RZ |
2696 | err = kstrtoint(buf, 10, &value); |
2697 | if (err) | |
2698 | return err; | |
2699 | ||
2700 | if (value == 0) | |
2701 | pwm_mode = AMD_FAN_CTRL_AUTO; | |
2702 | else if (value == 1) | |
2703 | pwm_mode = AMD_FAN_CTRL_MANUAL; | |
2704 | else | |
2705 | return -EINVAL; | |
2706 | ||
4a580877 | 2707 | err = pm_runtime_get_sync(adev_to_drm(adev)->dev); |
66429300 | 2708 | if (err < 0) { |
4a580877 | 2709 | pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); |
b9a9294b | 2710 | return err; |
66429300 | 2711 | } |
b9a9294b | 2712 | |
79c65f3f | 2713 | err = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode); |
c2870527 | 2714 | |
4a580877 LT |
2715 | pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); |
2716 | pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); | |
b9a9294b | 2717 | |
79c65f3f EQ |
2718 | if (err) |
2719 | return -EINVAL; | |
2720 | ||
c2870527 RZ |
2721 | return count; |
2722 | } | |
2723 | ||
2bd376bf AD |
2724 | static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev, |
2725 | struct device_attribute *attr, | |
2726 | char *buf) | |
2727 | { | |
2728 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
2bd376bf | 2729 | u32 vddgfx; |
d78c227f | 2730 | int r; |
2bd376bf | 2731 | |
2bd376bf | 2732 | /* get the voltage */ |
d78c227f ML |
2733 | r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDGFX, |
2734 | (void *)&vddgfx); | |
2bd376bf AD |
2735 | if (r) |
2736 | return r; | |
2737 | ||
a9ca9bb3 | 2738 | return sysfs_emit(buf, "%d\n", vddgfx); |
2bd376bf AD |
2739 | } |
2740 | ||
2741 | static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev, | |
2742 | struct device_attribute *attr, | |
2743 | char *buf) | |
2744 | { | |
a9ca9bb3 | 2745 | return sysfs_emit(buf, "vddgfx\n"); |
2bd376bf AD |
2746 | } |
2747 | ||
2748 | static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev, | |
2749 | struct device_attribute *attr, | |
2750 | char *buf) | |
2751 | { | |
2752 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
2bd376bf | 2753 | u32 vddnb; |
d78c227f | 2754 | int r; |
48b270bb | 2755 | |
2bd376bf | 2756 | /* only APUs have vddnb */ |
ccf9ef0b | 2757 | if (!(adev->flags & AMD_IS_APU)) |
2bd376bf AD |
2758 | return -EINVAL; |
2759 | ||
2bd376bf | 2760 | /* get the voltage */ |
d78c227f ML |
2761 | r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDNB, |
2762 | (void *)&vddnb); | |
2bd376bf AD |
2763 | if (r) |
2764 | return r; | |
2765 | ||
a9ca9bb3 | 2766 | return sysfs_emit(buf, "%d\n", vddnb); |
2bd376bf AD |
2767 | } |
2768 | ||
2769 | static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev, | |
2770 | struct device_attribute *attr, | |
2771 | char *buf) | |
2772 | { | |
a9ca9bb3 | 2773 | return sysfs_emit(buf, "vddnb\n"); |
2bd376bf AD |
2774 | } |
2775 | ||
d78c227f ML |
2776 | static unsigned int amdgpu_hwmon_get_power(struct device *dev, |
2777 | enum amd_pp_sensors sensor) | |
2976fc26 AD |
2778 | { |
2779 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
d78c227f | 2780 | unsigned int uw; |
5b79d048 | 2781 | u32 query = 0; |
d78c227f | 2782 | int r; |
b9a9294b | 2783 | |
d78c227f | 2784 | r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&query); |
2976fc26 AD |
2785 | if (r) |
2786 | return r; | |
2787 | ||
2788 | /* convert to microwatts */ | |
5b79d048 | 2789 | uw = (query >> 8) * 1000000 + (query & 0xff) * 1000; |
2976fc26 | 2790 | |
d78c227f ML |
2791 | return uw; |
2792 | } | |
2793 | ||
2794 | static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev, | |
2795 | struct device_attribute *attr, | |
2796 | char *buf) | |
2797 | { | |
2798 | unsigned int val; | |
2799 | ||
9366c2e8 | 2800 | val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_AVG_POWER); |
d78c227f ML |
2801 | if (val < 0) |
2802 | return val; | |
2803 | ||
2804 | return sysfs_emit(buf, "%u\n", val); | |
2976fc26 AD |
2805 | } |
2806 | ||
bb9f7b68 ML |
2807 | static ssize_t amdgpu_hwmon_show_power_input(struct device *dev, |
2808 | struct device_attribute *attr, | |
2809 | char *buf) | |
2810 | { | |
2811 | unsigned int val; | |
2812 | ||
47f1724d | 2813 | val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER); |
bb9f7b68 ML |
2814 | if (val < 0) |
2815 | return val; | |
2816 | ||
2817 | return sysfs_emit(buf, "%u\n", val); | |
2818 | } | |
2819 | ||
8d81bce7 RZ |
2820 | static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev, |
2821 | struct device_attribute *attr, | |
2822 | char *buf) | |
2823 | { | |
fdf8eea5 | 2824 | return sysfs_emit(buf, "%i\n", 0); |
8d81bce7 RZ |
2825 | } |
2826 | ||
91161b06 DP |
2827 | |
2828 | static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev, | |
2829 | struct device_attribute *attr, | |
2830 | char *buf, | |
2831 | enum pp_power_limit_level pp_limit_level) | |
8d81bce7 RZ |
2832 | { |
2833 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
a40a020d DP |
2834 | enum pp_power_type power_type = to_sensor_dev_attr(attr)->index; |
2835 | uint32_t limit; | |
b9a9294b AD |
2836 | ssize_t size; |
2837 | int r; | |
2838 | ||
53b3f8f4 | 2839 | if (amdgpu_in_reset(adev)) |
48b270bb | 2840 | return -EPERM; |
d2ae842d AD |
2841 | if (adev->in_suspend && !adev->in_runpm) |
2842 | return -EPERM; | |
48b270bb | 2843 | |
4a580877 | 2844 | r = pm_runtime_get_sync(adev_to_drm(adev)->dev); |
66429300 | 2845 | if (r < 0) { |
4a580877 | 2846 | pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); |
b9a9294b | 2847 | return r; |
66429300 | 2848 | } |
8d81bce7 | 2849 | |
79c65f3f | 2850 | r = amdgpu_dpm_get_power_limit(adev, &limit, |
91161b06 | 2851 | pp_limit_level, power_type); |
dc2a8240 DP |
2852 | |
2853 | if (!r) | |
09b6744c | 2854 | size = sysfs_emit(buf, "%u\n", limit * 1000000); |
dc2a8240 | 2855 | else |
09b6744c | 2856 | size = sysfs_emit(buf, "\n"); |
b9a9294b | 2857 | |
4a580877 LT |
2858 | pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); |
2859 | pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); | |
b9a9294b AD |
2860 | |
2861 | return size; | |
8d81bce7 RZ |
2862 | } |
2863 | ||
91161b06 DP |
2864 | |
2865 | static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev, | |
8d81bce7 RZ |
2866 | struct device_attribute *attr, |
2867 | char *buf) | |
2868 | { | |
91161b06 | 2869 | return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MAX); |
dc2a8240 | 2870 | |
91161b06 | 2871 | } |
b9a9294b | 2872 | |
91161b06 DP |
2873 | static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev, |
2874 | struct device_attribute *attr, | |
2875 | char *buf) | |
2876 | { | |
2877 | return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_CURRENT); | |
b9a9294b | 2878 | |
8d81bce7 RZ |
2879 | } |
2880 | ||
6e58941c EH |
2881 | static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev, |
2882 | struct device_attribute *attr, | |
2883 | char *buf) | |
2884 | { | |
91161b06 | 2885 | return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_DEFAULT); |
6e58941c | 2886 | |
6e58941c | 2887 | } |
91161b06 | 2888 | |
ae07970a XH |
2889 | static ssize_t amdgpu_hwmon_show_power_label(struct device *dev, |
2890 | struct device_attribute *attr, | |
2891 | char *buf) | |
2892 | { | |
3b99e8e3 | 2893 | struct amdgpu_device *adev = dev_get_drvdata(dev); |
8ecad8d6 | 2894 | uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; |
ae07970a | 2895 | |
8ecad8d6 | 2896 | if (gc_ver == IP_VERSION(10, 3, 1)) |
3b99e8e3 YW |
2897 | return sysfs_emit(buf, "%s\n", |
2898 | to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ? | |
2899 | "fastPPT" : "slowPPT"); | |
2900 | else | |
2901 | return sysfs_emit(buf, "PPT\n"); | |
ae07970a | 2902 | } |
8d81bce7 RZ |
2903 | |
2904 | static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, | |
2905 | struct device_attribute *attr, | |
2906 | const char *buf, | |
2907 | size_t count) | |
2908 | { | |
2909 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
ae07970a | 2910 | int limit_type = to_sensor_dev_attr(attr)->index; |
8d81bce7 RZ |
2911 | int err; |
2912 | u32 value; | |
2913 | ||
53b3f8f4 | 2914 | if (amdgpu_in_reset(adev)) |
48b270bb | 2915 | return -EPERM; |
d2ae842d AD |
2916 | if (adev->in_suspend && !adev->in_runpm) |
2917 | return -EPERM; | |
48b270bb | 2918 | |
c9ffa427 YT |
2919 | if (amdgpu_sriov_vf(adev)) |
2920 | return -EINVAL; | |
2921 | ||
8d81bce7 RZ |
2922 | err = kstrtou32(buf, 10, &value); |
2923 | if (err) | |
2924 | return err; | |
2925 | ||
2926 | value = value / 1000000; /* convert to Watt */ | |
ae07970a | 2927 | value |= limit_type << 24; |
b9a9294b | 2928 | |
4a580877 | 2929 | err = pm_runtime_get_sync(adev_to_drm(adev)->dev); |
66429300 | 2930 | if (err < 0) { |
4a580877 | 2931 | pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); |
b9a9294b | 2932 | return err; |
66429300 | 2933 | } |
b9a9294b | 2934 | |
79c65f3f | 2935 | err = amdgpu_dpm_set_power_limit(adev, value); |
b9a9294b | 2936 | |
4a580877 LT |
2937 | pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); |
2938 | pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); | |
8d81bce7 | 2939 | |
fcd90fee EQ |
2940 | if (err) |
2941 | return err; | |
2942 | ||
8d81bce7 RZ |
2943 | return count; |
2944 | } | |
2945 | ||
d0948af7 AD |
2946 | static ssize_t amdgpu_hwmon_show_sclk(struct device *dev, |
2947 | struct device_attribute *attr, | |
2948 | char *buf) | |
2949 | { | |
2950 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
d0948af7 | 2951 | uint32_t sclk; |
d78c227f | 2952 | int r; |
d0948af7 | 2953 | |
d0948af7 | 2954 | /* get the sclk */ |
d78c227f ML |
2955 | r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_SCLK, |
2956 | (void *)&sclk); | |
d0948af7 AD |
2957 | if (r) |
2958 | return r; | |
2959 | ||
a9ca9bb3 | 2960 | return sysfs_emit(buf, "%u\n", sclk * 10 * 1000); |
d0948af7 AD |
2961 | } |
2962 | ||
2963 | static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev, | |
2964 | struct device_attribute *attr, | |
2965 | char *buf) | |
2966 | { | |
a9ca9bb3 | 2967 | return sysfs_emit(buf, "sclk\n"); |
d0948af7 AD |
2968 | } |
2969 | ||
2970 | static ssize_t amdgpu_hwmon_show_mclk(struct device *dev, | |
2971 | struct device_attribute *attr, | |
2972 | char *buf) | |
2973 | { | |
2974 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
d0948af7 | 2975 | uint32_t mclk; |
d78c227f | 2976 | int r; |
d0948af7 | 2977 | |
d0948af7 | 2978 | /* get the sclk */ |
d78c227f ML |
2979 | r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_MCLK, |
2980 | (void *)&mclk); | |
d0948af7 AD |
2981 | if (r) |
2982 | return r; | |
2983 | ||
a9ca9bb3 | 2984 | return sysfs_emit(buf, "%u\n", mclk * 10 * 1000); |
d0948af7 AD |
2985 | } |
2986 | ||
2987 | static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev, | |
2988 | struct device_attribute *attr, | |
2989 | char *buf) | |
2990 | { | |
a9ca9bb3 | 2991 | return sysfs_emit(buf, "mclk\n"); |
d0948af7 | 2992 | } |
844c5419 AD |
2993 | |
2994 | /** | |
2995 | * DOC: hwmon | |
2996 | * | |
2997 | * The amdgpu driver exposes the following sensor interfaces: | |
dc85db25 | 2998 | * |
844c5419 | 2999 | * - GPU temperature (via the on-die sensor) |
dc85db25 | 3000 | * |
844c5419 | 3001 | * - GPU voltage |
dc85db25 | 3002 | * |
844c5419 | 3003 | * - Northbridge voltage (APUs only) |
dc85db25 | 3004 | * |
844c5419 | 3005 | * - GPU power |
dc85db25 | 3006 | * |
844c5419 AD |
3007 | * - GPU fan |
3008 | * | |
d0948af7 AD |
3009 | * - GPU gfx/compute engine clock |
3010 | * | |
3011 | * - GPU memory clock (dGPU only) | |
3012 | * | |
844c5419 | 3013 | * hwmon interfaces for GPU temperature: |
dc85db25 | 3014 | * |
a34d1166 EQ |
3015 | * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius |
3016 | * - temp2_input and temp3_input are supported on SOC15 dGPUs only | |
dc85db25 | 3017 | * |
2adc1156 EQ |
3018 | * - temp[1-3]_label: temperature channel label |
3019 | * - temp2_label and temp3_label are supported on SOC15 dGPUs only | |
3020 | * | |
437ccd17 EQ |
3021 | * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius |
3022 | * - temp2_crit and temp3_crit are supported on SOC15 dGPUs only | |
dc85db25 | 3023 | * |
437ccd17 EQ |
3024 | * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius |
3025 | * - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only | |
844c5419 | 3026 | * |
901cb599 EQ |
3027 | * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius |
3028 | * - these are supported on SOC15 dGPUs only | |
3029 | * | |
844c5419 | 3030 | * hwmon interfaces for GPU voltage: |
dc85db25 | 3031 | * |
844c5419 | 3032 | * - in0_input: the voltage on the GPU in millivolts |
dc85db25 | 3033 | * |
844c5419 AD |
3034 | * - in1_input: the voltage on the Northbridge in millivolts |
3035 | * | |
3036 | * hwmon interfaces for GPU power: | |
dc85db25 | 3037 | * |
29f5be8d | 3038 | * - power1_average: average power used by the SoC in microWatts. On APUs this includes the CPU. |
dc85db25 | 3039 | * |
bb9f7b68 ML |
3040 | * - power1_input: instantaneous power used by the SoC in microWatts. On APUs this includes the CPU. |
3041 | * | |
844c5419 | 3042 | * - power1_cap_min: minimum cap supported in microWatts |
dc85db25 | 3043 | * |
844c5419 | 3044 | * - power1_cap_max: maximum cap supported in microWatts |
dc85db25 | 3045 | * |
844c5419 AD |
3046 | * - power1_cap: selected power cap in microWatts |
3047 | * | |
3048 | * hwmon interfaces for GPU fan: | |
dc85db25 | 3049 | * |
844c5419 | 3050 | * - pwm1: pulse width modulation fan level (0-255) |
dc85db25 AD |
3051 | * |
3052 | * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control) | |
3053 | * | |
844c5419 | 3054 | * - pwm1_min: pulse width modulation fan control minimum level (0) |
dc85db25 | 3055 | * |
844c5419 | 3056 | * - pwm1_max: pulse width modulation fan control maximum level (255) |
dc85db25 | 3057 | * |
e5527d8c | 3058 | * - fan1_min: a minimum value Unit: revolution/min (RPM) |
c2870527 | 3059 | * |
e5527d8c | 3060 | * - fan1_max: a maximum value Unit: revolution/max (RPM) |
c2870527 | 3061 | * |
844c5419 AD |
3062 | * - fan1_input: fan speed in RPM |
3063 | * | |
879e723d | 3064 | * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM) |
c2870527 | 3065 | * |
879e723d | 3066 | * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable |
c2870527 | 3067 | * |
96401f7c EQ |
3068 | * NOTE: DO NOT set the fan speed via "pwm1" and "fan[1-\*]_target" interfaces at the same time. |
3069 | * That will get the former one overridden. | |
3070 | * | |
d0948af7 AD |
3071 | * hwmon interfaces for GPU clocks: |
3072 | * | |
3073 | * - freq1_input: the gfx/compute clock in hertz | |
3074 | * | |
3075 | * - freq2_input: the memory clock in hertz | |
3076 | * | |
844c5419 AD |
3077 | * You can use hwmon tools like sensors to view this information on your system. |
3078 | * | |
3079 | */ | |
3080 | ||
a34d1166 | 3081 | static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE); |
d38ceaf9 AD |
3082 | static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0); |
3083 | static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1); | |
901cb599 | 3084 | static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE); |
a34d1166 | 3085 | static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION); |
437ccd17 EQ |
3086 | static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0); |
3087 | static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1); | |
901cb599 | 3088 | static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION); |
a34d1166 | 3089 | static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM); |
437ccd17 EQ |
3090 | static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0); |
3091 | static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1); | |
901cb599 | 3092 | static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM); |
2adc1156 EQ |
3093 | static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE); |
3094 | static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION); | |
3095 | static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM); | |
d38ceaf9 AD |
3096 | static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0); |
3097 | static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0); | |
3098 | static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0); | |
3099 | static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0); | |
81c1514b | 3100 | static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0); |
c2870527 RZ |
3101 | static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0); |
3102 | static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0); | |
3103 | static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0); | |
3104 | static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0); | |
2bd376bf AD |
3105 | static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0); |
3106 | static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0); | |
3107 | static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0); | |
3108 | static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0); | |
2976fc26 | 3109 | static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0); |
bb9f7b68 | 3110 | static SENSOR_DEVICE_ATTR(power1_input, S_IRUGO, amdgpu_hwmon_show_power_input, NULL, 0); |
8d81bce7 RZ |
3111 | static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0); |
3112 | static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0); | |
3113 | static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0); | |
6e58941c | 3114 | static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0); |
ae07970a XH |
3115 | static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0); |
3116 | static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1); | |
3117 | static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1); | |
3118 | static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1); | |
3119 | static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1); | |
6e58941c | 3120 | static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1); |
ae07970a | 3121 | static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1); |
d0948af7 AD |
3122 | static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0); |
3123 | static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0); | |
3124 | static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0); | |
3125 | static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0); | |
d38ceaf9 AD |
3126 | |
3127 | static struct attribute *hwmon_attributes[] = { | |
3128 | &sensor_dev_attr_temp1_input.dev_attr.attr, | |
3129 | &sensor_dev_attr_temp1_crit.dev_attr.attr, | |
3130 | &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, | |
a34d1166 | 3131 | &sensor_dev_attr_temp2_input.dev_attr.attr, |
437ccd17 EQ |
3132 | &sensor_dev_attr_temp2_crit.dev_attr.attr, |
3133 | &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr, | |
a34d1166 | 3134 | &sensor_dev_attr_temp3_input.dev_attr.attr, |
437ccd17 EQ |
3135 | &sensor_dev_attr_temp3_crit.dev_attr.attr, |
3136 | &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr, | |
901cb599 EQ |
3137 | &sensor_dev_attr_temp1_emergency.dev_attr.attr, |
3138 | &sensor_dev_attr_temp2_emergency.dev_attr.attr, | |
3139 | &sensor_dev_attr_temp3_emergency.dev_attr.attr, | |
2adc1156 EQ |
3140 | &sensor_dev_attr_temp1_label.dev_attr.attr, |
3141 | &sensor_dev_attr_temp2_label.dev_attr.attr, | |
3142 | &sensor_dev_attr_temp3_label.dev_attr.attr, | |
d38ceaf9 AD |
3143 | &sensor_dev_attr_pwm1.dev_attr.attr, |
3144 | &sensor_dev_attr_pwm1_enable.dev_attr.attr, | |
3145 | &sensor_dev_attr_pwm1_min.dev_attr.attr, | |
3146 | &sensor_dev_attr_pwm1_max.dev_attr.attr, | |
81c1514b | 3147 | &sensor_dev_attr_fan1_input.dev_attr.attr, |
c2870527 RZ |
3148 | &sensor_dev_attr_fan1_min.dev_attr.attr, |
3149 | &sensor_dev_attr_fan1_max.dev_attr.attr, | |
3150 | &sensor_dev_attr_fan1_target.dev_attr.attr, | |
3151 | &sensor_dev_attr_fan1_enable.dev_attr.attr, | |
2bd376bf AD |
3152 | &sensor_dev_attr_in0_input.dev_attr.attr, |
3153 | &sensor_dev_attr_in0_label.dev_attr.attr, | |
3154 | &sensor_dev_attr_in1_input.dev_attr.attr, | |
3155 | &sensor_dev_attr_in1_label.dev_attr.attr, | |
2976fc26 | 3156 | &sensor_dev_attr_power1_average.dev_attr.attr, |
bb9f7b68 | 3157 | &sensor_dev_attr_power1_input.dev_attr.attr, |
8d81bce7 RZ |
3158 | &sensor_dev_attr_power1_cap_max.dev_attr.attr, |
3159 | &sensor_dev_attr_power1_cap_min.dev_attr.attr, | |
3160 | &sensor_dev_attr_power1_cap.dev_attr.attr, | |
6e58941c | 3161 | &sensor_dev_attr_power1_cap_default.dev_attr.attr, |
ae07970a XH |
3162 | &sensor_dev_attr_power1_label.dev_attr.attr, |
3163 | &sensor_dev_attr_power2_average.dev_attr.attr, | |
3164 | &sensor_dev_attr_power2_cap_max.dev_attr.attr, | |
3165 | &sensor_dev_attr_power2_cap_min.dev_attr.attr, | |
3166 | &sensor_dev_attr_power2_cap.dev_attr.attr, | |
6e58941c | 3167 | &sensor_dev_attr_power2_cap_default.dev_attr.attr, |
ae07970a | 3168 | &sensor_dev_attr_power2_label.dev_attr.attr, |
d0948af7 AD |
3169 | &sensor_dev_attr_freq1_input.dev_attr.attr, |
3170 | &sensor_dev_attr_freq1_label.dev_attr.attr, | |
3171 | &sensor_dev_attr_freq2_input.dev_attr.attr, | |
3172 | &sensor_dev_attr_freq2_label.dev_attr.attr, | |
d38ceaf9 AD |
3173 | NULL |
3174 | }; | |
3175 | ||
3176 | static umode_t hwmon_attributes_visible(struct kobject *kobj, | |
3177 | struct attribute *attr, int index) | |
3178 | { | |
cc29ec87 | 3179 | struct device *dev = kobj_to_dev(kobj); |
d38ceaf9 AD |
3180 | struct amdgpu_device *adev = dev_get_drvdata(dev); |
3181 | umode_t effective_mode = attr->mode; | |
8ecad8d6 | 3182 | uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; |
15419813 | 3183 | uint32_t tmp; |
d38ceaf9 | 3184 | |
c9ffa427 YT |
3185 | /* under multi-vf mode, the hwmon attributes are all not supported */ |
3186 | if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) | |
3187 | return 0; | |
3188 | ||
4f0f1b58 DS |
3189 | /* under pp one vf mode manage of hwmon attributes is not supported */ |
3190 | if (amdgpu_sriov_is_pp_one_vf(adev)) | |
3191 | effective_mode &= ~S_IWUSR; | |
3192 | ||
fc5a136d RZ |
3193 | /* Skip fan attributes if fan is not present */ |
3194 | if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr || | |
3195 | attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || | |
3196 | attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || | |
3197 | attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || | |
c2870527 RZ |
3198 | attr == &sensor_dev_attr_fan1_input.dev_attr.attr || |
3199 | attr == &sensor_dev_attr_fan1_min.dev_attr.attr || | |
3200 | attr == &sensor_dev_attr_fan1_max.dev_attr.attr || | |
3201 | attr == &sensor_dev_attr_fan1_target.dev_attr.attr || | |
3202 | attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) | |
fc5a136d | 3203 | return 0; |
135f9711 | 3204 | |
20a96cd3 AD |
3205 | /* Skip fan attributes on APU */ |
3206 | if ((adev->flags & AMD_IS_APU) && | |
3207 | (attr == &sensor_dev_attr_pwm1.dev_attr.attr || | |
3208 | attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || | |
3209 | attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || | |
3210 | attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || | |
3211 | attr == &sensor_dev_attr_fan1_input.dev_attr.attr || | |
3212 | attr == &sensor_dev_attr_fan1_min.dev_attr.attr || | |
3213 | attr == &sensor_dev_attr_fan1_max.dev_attr.attr || | |
3214 | attr == &sensor_dev_attr_fan1_target.dev_attr.attr || | |
3215 | attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) | |
3216 | return 0; | |
3217 | ||
35dab589 | 3218 | /* Skip crit temp on APU */ |
8572fa2a AK |
3219 | if ((((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ)) || |
3220 | (gc_ver == IP_VERSION(9, 4, 3))) && | |
35dab589 HR |
3221 | (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || |
3222 | attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr)) | |
3223 | return 0; | |
3224 | ||
1b5708ff | 3225 | /* Skip limit attributes if DPM is not enabled */ |
d38ceaf9 AD |
3226 | if (!adev->pm.dpm_enabled && |
3227 | (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || | |
27100735 AD |
3228 | attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr || |
3229 | attr == &sensor_dev_attr_pwm1.dev_attr.attr || | |
3230 | attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || | |
3231 | attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || | |
c2870527 RZ |
3232 | attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || |
3233 | attr == &sensor_dev_attr_fan1_input.dev_attr.attr || | |
3234 | attr == &sensor_dev_attr_fan1_min.dev_attr.attr || | |
3235 | attr == &sensor_dev_attr_fan1_max.dev_attr.attr || | |
3236 | attr == &sensor_dev_attr_fan1_target.dev_attr.attr || | |
3237 | attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) | |
d38ceaf9 AD |
3238 | return 0; |
3239 | ||
79c65f3f | 3240 | /* mask fan attributes if we have no bindings for this asic to expose */ |
685fae24 | 3241 | if (((amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) && |
79c65f3f | 3242 | attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ |
685fae24 | 3243 | ((amdgpu_dpm_get_fan_control_mode(adev, NULL) == -EOPNOTSUPP) && |
79c65f3f EQ |
3244 | attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ |
3245 | effective_mode &= ~S_IRUGO; | |
239873fc | 3246 | |
685fae24 | 3247 | if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) && |
79c65f3f | 3248 | attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ |
685fae24 | 3249 | ((amdgpu_dpm_set_fan_control_mode(adev, U32_MAX) == -EOPNOTSUPP) && |
79c65f3f EQ |
3250 | attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ |
3251 | effective_mode &= ~S_IWUSR; | |
d38ceaf9 | 3252 | |
8572fa2a | 3253 | /* not implemented yet for APUs other than GC 10.3.1 (vangogh) and 9.4.3 */ |
ae07970a | 3254 | if (((adev->family == AMDGPU_FAMILY_SI) || |
8572fa2a AK |
3255 | ((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)) && |
3256 | (gc_ver != IP_VERSION(9, 4, 3)))) && | |
367deb67 | 3257 | (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr || |
8ecad8d6 | 3258 | attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr || |
6e58941c EH |
3259 | attr == &sensor_dev_attr_power1_cap.dev_attr.attr || |
3260 | attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr)) | |
8d81bce7 RZ |
3261 | return 0; |
3262 | ||
89317d42 | 3263 | /* not implemented yet for APUs having < GC 9.3.0 (Renoir) */ |
367deb67 | 3264 | if (((adev->family == AMDGPU_FAMILY_SI) || |
8ecad8d6 | 3265 | ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) && |
367deb67 AD |
3266 | (attr == &sensor_dev_attr_power1_average.dev_attr.attr)) |
3267 | return 0; | |
3268 | ||
15419813 ML |
3269 | /* not all products support both average and instantaneous */ |
3270 | if (attr == &sensor_dev_attr_power1_average.dev_attr.attr && | |
3271 | amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&tmp) == -EOPNOTSUPP) | |
3272 | return 0; | |
3273 | if (attr == &sensor_dev_attr_power1_input.dev_attr.attr && | |
3274 | amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&tmp) == -EOPNOTSUPP) | |
3275 | return 0; | |
3276 | ||
79c65f3f | 3277 | /* hide max/min values if we can't both query and manage the fan */ |
685fae24 EQ |
3278 | if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) && |
3279 | (amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) && | |
3280 | (amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) && | |
3281 | (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP)) && | |
79c65f3f EQ |
3282 | (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || |
3283 | attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) | |
3284 | return 0; | |
239873fc | 3285 | |
685fae24 EQ |
3286 | if ((amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) && |
3287 | (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP) && | |
79c65f3f EQ |
3288 | (attr == &sensor_dev_attr_fan1_max.dev_attr.attr || |
3289 | attr == &sensor_dev_attr_fan1_min.dev_attr.attr)) | |
3290 | return 0; | |
c2870527 | 3291 | |
1cdd229b | 3292 | if ((adev->family == AMDGPU_FAMILY_SI || /* not implemented yet */ |
8572fa2a AK |
3293 | adev->family == AMDGPU_FAMILY_KV || /* not implemented yet */ |
3294 | (gc_ver == IP_VERSION(9, 4, 3))) && | |
1cdd229b JD |
3295 | (attr == &sensor_dev_attr_in0_input.dev_attr.attr || |
3296 | attr == &sensor_dev_attr_in0_label.dev_attr.attr)) | |
3297 | return 0; | |
3298 | ||
8572fa2a AK |
3299 | /* only APUs other than gc 9,4,3 have vddnb */ |
3300 | if ((!(adev->flags & AMD_IS_APU) || (gc_ver == IP_VERSION(9, 4, 3))) && | |
0d35bc78 AD |
3301 | (attr == &sensor_dev_attr_in1_input.dev_attr.attr || |
3302 | attr == &sensor_dev_attr_in1_label.dev_attr.attr)) | |
81c1514b GI |
3303 | return 0; |
3304 | ||
8572fa2a AK |
3305 | /* no mclk on APUs other than gc 9,4,3*/ |
3306 | if (((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(9, 4, 3))) && | |
d0948af7 AD |
3307 | (attr == &sensor_dev_attr_freq2_input.dev_attr.attr || |
3308 | attr == &sensor_dev_attr_freq2_label.dev_attr.attr)) | |
3309 | return 0; | |
3310 | ||
8ecad8d6 | 3311 | if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) && |
8572fa2a AK |
3312 | (gc_ver != IP_VERSION(9, 4, 3)) && |
3313 | (attr == &sensor_dev_attr_temp2_input.dev_attr.attr || | |
bfb4fd20 | 3314 | attr == &sensor_dev_attr_temp2_label.dev_attr.attr || |
1836bb0a | 3315 | attr == &sensor_dev_attr_temp2_crit.dev_attr.attr || |
bfb4fd20 | 3316 | attr == &sensor_dev_attr_temp3_input.dev_attr.attr || |
1836bb0a AK |
3317 | attr == &sensor_dev_attr_temp3_label.dev_attr.attr || |
3318 | attr == &sensor_dev_attr_temp3_crit.dev_attr.attr)) | |
8572fa2a AK |
3319 | return 0; |
3320 | ||
bfb4fd20 | 3321 | /* hotspot temperature for gc 9,4,3*/ |
8572fa2a AK |
3322 | if ((gc_ver == IP_VERSION(9, 4, 3)) && |
3323 | (attr == &sensor_dev_attr_temp1_input.dev_attr.attr || | |
3324 | attr == &sensor_dev_attr_temp1_label.dev_attr.attr)) | |
3325 | return 0; | |
3326 | ||
3327 | /* only SOC15 dGPUs support hotspot and mem temperatures */ | |
3328 | if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0) || | |
3329 | (gc_ver == IP_VERSION(9, 4, 3))) && | |
1836bb0a | 3330 | (attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr || |
901cb599 EQ |
3331 | attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr || |
3332 | attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr || | |
3333 | attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr || | |
bfb4fd20 | 3334 | attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr)) |
437ccd17 EQ |
3335 | return 0; |
3336 | ||
ae07970a | 3337 | /* only Vangogh has fast PPT limit and power labels */ |
8ecad8d6 | 3338 | if (!(gc_ver == IP_VERSION(10, 3, 1)) && |
ae07970a | 3339 | (attr == &sensor_dev_attr_power2_average.dev_attr.attr || |
8ecad8d6 | 3340 | attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr || |
ae07970a | 3341 | attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr || |
8ecad8d6 LL |
3342 | attr == &sensor_dev_attr_power2_cap.dev_attr.attr || |
3343 | attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr || | |
3344 | attr == &sensor_dev_attr_power2_label.dev_attr.attr)) | |
ae07970a XH |
3345 | return 0; |
3346 | ||
d38ceaf9 AD |
3347 | return effective_mode; |
3348 | } | |
3349 | ||
3350 | static const struct attribute_group hwmon_attrgroup = { | |
3351 | .attrs = hwmon_attributes, | |
3352 | .is_visible = hwmon_attributes_visible, | |
3353 | }; | |
3354 | ||
3355 | static const struct attribute_group *hwmon_groups[] = { | |
3356 | &hwmon_attrgroup, | |
3357 | NULL | |
3358 | }; | |
3359 | ||
d38ceaf9 AD |
3360 | int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) |
3361 | { | |
3362 | int ret; | |
4e01847c | 3363 | uint32_t mask = 0; |
d38ceaf9 | 3364 | |
c86f5ebf AD |
3365 | if (adev->pm.sysfs_initialized) |
3366 | return 0; | |
3367 | ||
5fa99373 ZY |
3368 | INIT_LIST_HEAD(&adev->pm.pm_attr_list); |
3369 | ||
d2f52ac8 RZ |
3370 | if (adev->pm.dpm_enabled == 0) |
3371 | return 0; | |
3372 | ||
d38ceaf9 AD |
3373 | adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev, |
3374 | DRIVER_NAME, adev, | |
3375 | hwmon_groups); | |
3376 | if (IS_ERR(adev->pm.int_hwmon_dev)) { | |
3377 | ret = PTR_ERR(adev->pm.int_hwmon_dev); | |
3378 | dev_err(adev->dev, | |
3379 | "Unable to register hwmon device: %d\n", ret); | |
3380 | return ret; | |
3381 | } | |
3382 | ||
4e01847c KW |
3383 | switch (amdgpu_virt_get_sriov_vf_mode(adev)) { |
3384 | case SRIOV_VF_MODE_ONE_VF: | |
3385 | mask = ATTR_FLAG_ONEVF; | |
3386 | break; | |
3387 | case SRIOV_VF_MODE_MULTI_VF: | |
3388 | mask = 0; | |
3389 | break; | |
3390 | case SRIOV_VF_MODE_BARE_METAL: | |
3391 | default: | |
3392 | mask = ATTR_FLAG_MASK_ALL; | |
3393 | break; | |
8efd7275 ML |
3394 | } |
3395 | ||
4e01847c KW |
3396 | ret = amdgpu_device_attr_create_groups(adev, |
3397 | amdgpu_device_attrs, | |
3398 | ARRAY_SIZE(amdgpu_device_attrs), | |
ba02fd6b KW |
3399 | mask, |
3400 | &adev->pm.pm_attr_list); | |
4e01847c | 3401 | if (ret) |
fb2dbfd2 | 3402 | return ret; |
7ca881a8 | 3403 | |
c86f5ebf AD |
3404 | adev->pm.sysfs_initialized = true; |
3405 | ||
d38ceaf9 AD |
3406 | return 0; |
3407 | } | |
3408 | ||
3409 | void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) | |
3410 | { | |
3411 | if (adev->pm.int_hwmon_dev) | |
3412 | hwmon_device_unregister(adev->pm.int_hwmon_dev); | |
4e01847c | 3413 | |
ba02fd6b | 3414 | amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list); |
d38ceaf9 AD |
3415 | } |
3416 | ||
d38ceaf9 AD |
3417 | /* |
3418 | * Debugfs info | |
3419 | */ | |
3420 | #if defined(CONFIG_DEBUG_FS) | |
3421 | ||
517cb957 | 3422 | static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m, |
e1b3bcaa RS |
3423 | struct amdgpu_device *adev) |
3424 | { | |
517cb957 HR |
3425 | uint16_t *p_val; |
3426 | uint32_t size; | |
3427 | int i; | |
79c65f3f | 3428 | uint32_t num_cpu_cores = amdgpu_dpm_get_num_cpu_cores(adev); |
517cb957 | 3429 | |
79c65f3f EQ |
3430 | if (amdgpu_dpm_is_cclk_dpm_supported(adev)) { |
3431 | p_val = kcalloc(num_cpu_cores, sizeof(uint16_t), | |
517cb957 HR |
3432 | GFP_KERNEL); |
3433 | ||
3434 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK, | |
3435 | (void *)p_val, &size)) { | |
79c65f3f | 3436 | for (i = 0; i < num_cpu_cores; i++) |
517cb957 HR |
3437 | seq_printf(m, "\t%u MHz (CPU%d)\n", |
3438 | *(p_val + i), i); | |
3439 | } | |
3440 | ||
3441 | kfree(p_val); | |
3442 | } | |
3443 | } | |
3444 | ||
3de4ec57 TSD |
3445 | static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev) |
3446 | { | |
8ecad8d6 LL |
3447 | uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0]; |
3448 | uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; | |
cd7b0c66 | 3449 | uint32_t value; |
800c53d6 | 3450 | uint64_t value64 = 0; |
5b79d048 | 3451 | uint32_t query = 0; |
9f8df7d7 | 3452 | int size; |
3de4ec57 | 3453 | |
3de4ec57 | 3454 | /* GPU Clocks */ |
9f8df7d7 | 3455 | size = sizeof(value); |
3de4ec57 | 3456 | seq_printf(m, "GFX Clocks and Power:\n"); |
517cb957 HR |
3457 | |
3458 | amdgpu_debugfs_prints_cpu_info(m, adev); | |
3459 | ||
9f8df7d7 | 3460 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size)) |
3de4ec57 | 3461 | seq_printf(m, "\t%u MHz (MCLK)\n", value/100); |
9f8df7d7 | 3462 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size)) |
3de4ec57 | 3463 | seq_printf(m, "\t%u MHz (SCLK)\n", value/100); |
5ed8d656 RZ |
3464 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size)) |
3465 | seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100); | |
3466 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size)) | |
3467 | seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100); | |
9f8df7d7 | 3468 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size)) |
3de4ec57 | 3469 | seq_printf(m, "\t%u mV (VDDGFX)\n", value); |
9f8df7d7 | 3470 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size)) |
3de4ec57 | 3471 | seq_printf(m, "\t%u mV (VDDNB)\n", value); |
5b79d048 | 3472 | size = sizeof(uint32_t); |
9366c2e8 | 3473 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&query, &size)) |
5b79d048 | 3474 | seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff); |
a7dd9b97 AD |
3475 | size = sizeof(uint32_t); |
3476 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&query, &size)) | |
3477 | seq_printf(m, "\t%u.%u W (current GPU)\n", query >> 8, query & 0xff); | |
9f8df7d7 | 3478 | size = sizeof(value); |
3de4ec57 TSD |
3479 | seq_printf(m, "\n"); |
3480 | ||
3481 | /* GPU Temp */ | |
9f8df7d7 | 3482 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size)) |
3de4ec57 TSD |
3483 | seq_printf(m, "GPU Temperature: %u C\n", value/1000); |
3484 | ||
3485 | /* GPU Load */ | |
9f8df7d7 | 3486 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size)) |
3de4ec57 | 3487 | seq_printf(m, "GPU Load: %u %%\n", value); |
9b6eb00d TSD |
3488 | /* MEM Load */ |
3489 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size)) | |
3490 | seq_printf(m, "MEM Load: %u %%\n", value); | |
3491 | ||
3de4ec57 TSD |
3492 | seq_printf(m, "\n"); |
3493 | ||
505f8dbb AD |
3494 | /* SMC feature mask */ |
3495 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size)) | |
3496 | seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64); | |
3497 | ||
8ecad8d6 LL |
3498 | /* ASICs greater than CHIP_VEGA20 supports these sensors */ |
3499 | if (gc_ver != IP_VERSION(9, 4, 0) && mp1_ver > IP_VERSION(9, 0, 0)) { | |
1f96ecef EQ |
3500 | /* VCN clocks */ |
3501 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) { | |
3502 | if (!value) { | |
3503 | seq_printf(m, "VCN: Disabled\n"); | |
3504 | } else { | |
3505 | seq_printf(m, "VCN: Enabled\n"); | |
3506 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) | |
3507 | seq_printf(m, "\t%u MHz (DCLK)\n", value/100); | |
3508 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) | |
3509 | seq_printf(m, "\t%u MHz (VCLK)\n", value/100); | |
3510 | } | |
3de4ec57 | 3511 | } |
1f96ecef EQ |
3512 | seq_printf(m, "\n"); |
3513 | } else { | |
3514 | /* UVD clocks */ | |
3515 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) { | |
3516 | if (!value) { | |
3517 | seq_printf(m, "UVD: Disabled\n"); | |
3518 | } else { | |
3519 | seq_printf(m, "UVD: Enabled\n"); | |
3520 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) | |
3521 | seq_printf(m, "\t%u MHz (DCLK)\n", value/100); | |
3522 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) | |
3523 | seq_printf(m, "\t%u MHz (VCLK)\n", value/100); | |
3524 | } | |
3525 | } | |
3526 | seq_printf(m, "\n"); | |
3de4ec57 | 3527 | |
1f96ecef EQ |
3528 | /* VCE clocks */ |
3529 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) { | |
3530 | if (!value) { | |
3531 | seq_printf(m, "VCE: Disabled\n"); | |
3532 | } else { | |
3533 | seq_printf(m, "VCE: Enabled\n"); | |
3534 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size)) | |
3535 | seq_printf(m, "\t%u MHz (ECCLK)\n", value/100); | |
3536 | } | |
3de4ec57 TSD |
3537 | } |
3538 | } | |
3539 | ||
3540 | return 0; | |
3541 | } | |
3542 | ||
44762718 NC |
3543 | static const struct cg_flag_name clocks[] = { |
3544 | {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"}, | |
3545 | {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"}, | |
3546 | {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"}, | |
3547 | {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"}, | |
3548 | {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"}, | |
3549 | {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"}, | |
3550 | {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"}, | |
3551 | {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"}, | |
3552 | {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"}, | |
3553 | {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"}, | |
3554 | {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"}, | |
3555 | {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"}, | |
3556 | {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"}, | |
3557 | {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"}, | |
3558 | {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"}, | |
3559 | {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"}, | |
3560 | {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"}, | |
3561 | {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"}, | |
3562 | {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"}, | |
3563 | {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"}, | |
3564 | {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"}, | |
3565 | {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"}, | |
3566 | {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"}, | |
3567 | {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"}, | |
3568 | {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"}, | |
3569 | {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"}, | |
3570 | {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"}, | |
3571 | {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"}, | |
3572 | {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"}, | |
3573 | {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"}, | |
3574 | {AMD_CG_SUPPORT_REPEATER_FGCG, "Repeater Fine Grain Clock Gating"}, | |
3575 | {AMD_CG_SUPPORT_GFX_PERF_CLK, "Perfmon Clock Gating"}, | |
3576 | {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"}, | |
3577 | {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"}, | |
3578 | {0, NULL}, | |
3579 | }; | |
3580 | ||
25faeddc | 3581 | static void amdgpu_parse_cg_state(struct seq_file *m, u64 flags) |
a8503b15 HR |
3582 | { |
3583 | int i; | |
3584 | ||
3585 | for (i = 0; clocks[i].flag; i++) | |
3586 | seq_printf(m, "\t%s: %s\n", clocks[i].name, | |
3587 | (flags & clocks[i].flag) ? "On" : "Off"); | |
3588 | } | |
3589 | ||
373720f7 | 3590 | static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused) |
d38ceaf9 | 3591 | { |
373720f7 ND |
3592 | struct amdgpu_device *adev = (struct amdgpu_device *)m->private; |
3593 | struct drm_device *dev = adev_to_drm(adev); | |
25faeddc | 3594 | u64 flags = 0; |
b9a9294b AD |
3595 | int r; |
3596 | ||
53b3f8f4 | 3597 | if (amdgpu_in_reset(adev)) |
48b270bb | 3598 | return -EPERM; |
d2ae842d AD |
3599 | if (adev->in_suspend && !adev->in_runpm) |
3600 | return -EPERM; | |
48b270bb | 3601 | |
b9a9294b | 3602 | r = pm_runtime_get_sync(dev->dev); |
66429300 AD |
3603 | if (r < 0) { |
3604 | pm_runtime_put_autosuspend(dev->dev); | |
b9a9294b | 3605 | return r; |
66429300 | 3606 | } |
6cb2d4e4 | 3607 | |
79c65f3f | 3608 | if (amdgpu_dpm_debugfs_print_current_performance_level(adev, m)) { |
b9a9294b | 3609 | r = amdgpu_debugfs_pm_info_pp(m, adev); |
79c65f3f EQ |
3610 | if (r) |
3611 | goto out; | |
d38ceaf9 | 3612 | } |
81b41ff5 | 3613 | |
81b41ff5 | 3614 | amdgpu_device_ip_get_clockgating_state(adev, &flags); |
81b41ff5 | 3615 | |
25faeddc | 3616 | seq_printf(m, "Clock Gating Flags Mask: 0x%llx\n", flags); |
81b41ff5 EQ |
3617 | amdgpu_parse_cg_state(m, flags); |
3618 | seq_printf(m, "\n"); | |
d38ceaf9 | 3619 | |
81b41ff5 | 3620 | out: |
b9a9294b AD |
3621 | pm_runtime_mark_last_busy(dev->dev); |
3622 | pm_runtime_put_autosuspend(dev->dev); | |
3623 | ||
3624 | return r; | |
d38ceaf9 AD |
3625 | } |
3626 | ||
373720f7 ND |
3627 | DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info); |
3628 | ||
27ebf21f LL |
3629 | /* |
3630 | * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW | |
3631 | * | |
3632 | * Reads debug memory region allocated to PMFW | |
3633 | */ | |
3634 | static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf, | |
3635 | size_t size, loff_t *pos) | |
3636 | { | |
3637 | struct amdgpu_device *adev = file_inode(f)->i_private; | |
27ebf21f LL |
3638 | size_t smu_prv_buf_size; |
3639 | void *smu_prv_buf; | |
79c65f3f | 3640 | int ret = 0; |
27ebf21f LL |
3641 | |
3642 | if (amdgpu_in_reset(adev)) | |
3643 | return -EPERM; | |
3644 | if (adev->in_suspend && !adev->in_runpm) | |
3645 | return -EPERM; | |
3646 | ||
79c65f3f EQ |
3647 | ret = amdgpu_dpm_get_smu_prv_buf_details(adev, &smu_prv_buf, &smu_prv_buf_size); |
3648 | if (ret) | |
3649 | return ret; | |
27ebf21f LL |
3650 | |
3651 | if (!smu_prv_buf || !smu_prv_buf_size) | |
3652 | return -EINVAL; | |
3653 | ||
3654 | return simple_read_from_buffer(buf, size, pos, smu_prv_buf, | |
3655 | smu_prv_buf_size); | |
3656 | } | |
3657 | ||
3658 | static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = { | |
3659 | .owner = THIS_MODULE, | |
3660 | .open = simple_open, | |
3661 | .read = amdgpu_pm_prv_buffer_read, | |
3662 | .llseek = default_llseek, | |
3663 | }; | |
3664 | ||
d38ceaf9 AD |
3665 | #endif |
3666 | ||
373720f7 | 3667 | void amdgpu_debugfs_pm_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
3668 | { |
3669 | #if defined(CONFIG_DEBUG_FS) | |
373720f7 ND |
3670 | struct drm_minor *minor = adev_to_drm(adev)->primary; |
3671 | struct dentry *root = minor->debugfs_root; | |
3672 | ||
1613f346 FC |
3673 | if (!adev->pm.dpm_enabled) |
3674 | return; | |
3675 | ||
373720f7 ND |
3676 | debugfs_create_file("amdgpu_pm_info", 0444, root, adev, |
3677 | &amdgpu_debugfs_pm_info_fops); | |
3678 | ||
27ebf21f LL |
3679 | if (adev->pm.smu_prv_buffer_size > 0) |
3680 | debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root, | |
3681 | adev, | |
3682 | &amdgpu_debugfs_pm_prv_buffer_fops, | |
3683 | adev->pm.smu_prv_buffer_size); | |
1f5fc7a5 | 3684 | |
79c65f3f | 3685 | amdgpu_dpm_stb_debug_fs_init(adev); |
d38ceaf9 AD |
3686 | #endif |
3687 | } |