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Merge tag 'drm-intel-next-fixes-2016-07-25' of git://anongit.freedesktop.org/drm...
[linux-2.6-block.git] / drivers / gpu / drm / amd / include / cgs_common.h
CommitLineData
d03846af
CZ		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24#ifndef _CGS_COMMON_H
25#define _CGS_COMMON_H
26
404b2fa3 27#include "amd_shared.h"
bf3911b0 28
110e6f26
DA		 29struct cgs_device;
30
d03846af
CZ		 31/**
32 * enum cgs_gpu_mem_type - GPU memory types
33 */
34enum cgs_gpu_mem_type {
35 CGS_GPU_MEM_TYPE__VISIBLE_FB,
36 CGS_GPU_MEM_TYPE__INVISIBLE_FB,
37 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
38 CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB,
39 CGS_GPU_MEM_TYPE__GART_CACHEABLE,
40 CGS_GPU_MEM_TYPE__GART_WRITECOMBINE
41};
42
43/**
44 * enum cgs_ind_reg - Indirect register spaces
45 */
46enum cgs_ind_reg {
47 CGS_IND_REG__MMIO,
48 CGS_IND_REG__PCIE,
49 CGS_IND_REG__SMC,
50 CGS_IND_REG__UVD_CTX,
51 CGS_IND_REG__DIDT,
ccdbb20a 52 CGS_IND_REG_GC_CAC,
d03846af
CZ		 53 CGS_IND_REG__AUDIO_ENDPT
54};
55
56/**
57 * enum cgs_clock - Clocks controlled by the SMU
58 */
59enum cgs_clock {
60 CGS_CLOCK__SCLK,
61 CGS_CLOCK__MCLK,
62 CGS_CLOCK__VCLK,
63 CGS_CLOCK__DCLK,
64 CGS_CLOCK__ECLK,
65 CGS_CLOCK__ACLK,
66 CGS_CLOCK__ICLK,
67 /* ... */
68};
69
70/**
71 * enum cgs_engine - Engines that can be statically power-gated
72 */
73enum cgs_engine {
74 CGS_ENGINE__UVD,
75 CGS_ENGINE__VCE,
76 CGS_ENGINE__VP8,
77 CGS_ENGINE__ACP_DMA,
78 CGS_ENGINE__ACP_DSP0,
79 CGS_ENGINE__ACP_DSP1,
80 CGS_ENGINE__ISP,
81 /* ... */
82};
83
84/**
85 * enum cgs_voltage_planes - Voltage planes for external camera HW
86 */
87enum cgs_voltage_planes {
88 CGS_VOLTAGE_PLANE__SENSOR0,
89 CGS_VOLTAGE_PLANE__SENSOR1,
90 /* ... */
91};
92
bf3911b0
JZ		 93/*
94 * enum cgs_ucode_id - Firmware types for different IPs
95 */
96enum cgs_ucode_id {
97 CGS_UCODE_ID_SMU = 0,
735f002b 98 CGS_UCODE_ID_SMU_SK,
bf3911b0
JZ		 99 CGS_UCODE_ID_SDMA0,
100 CGS_UCODE_ID_SDMA1,
101 CGS_UCODE_ID_CP_CE,
102 CGS_UCODE_ID_CP_PFP,
103 CGS_UCODE_ID_CP_ME,
104 CGS_UCODE_ID_CP_MEC,
105 CGS_UCODE_ID_CP_MEC_JT1,
106 CGS_UCODE_ID_CP_MEC_JT2,
107 CGS_UCODE_ID_GMCON_RENG,
108 CGS_UCODE_ID_RLC_G,
109 CGS_UCODE_ID_MAXIMUM,
110};
111
5e618699
RZ		 112enum cgs_system_info_id {
113 CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1,
cfd316d5
AD		 114 CGS_SYSTEM_INFO_PCIE_GEN_INFO,
115 CGS_SYSTEM_INFO_PCIE_MLW,
08d33408
AD		 116 CGS_SYSTEM_INFO_CG_FLAGS,
117 CGS_SYSTEM_INFO_PG_FLAGS,
bacec898 118 CGS_SYSTEM_INFO_GFX_CU_INFO,
d826c982 119 CGS_SYSTEM_INFO_GFX_SE_INFO,
5e618699
RZ		 120 CGS_SYSTEM_INFO_ID_MAXIMUM,
121};
122
123struct cgs_system_info {
124 uint64_t size;
125 uint64_t info_id;
126 union {
127 void *ptr;
128 uint64_t value;
129 };
130 uint64_t padding[13];
131};
132
ba228ac8
AD		 133/*
134 * enum cgs_resource_type - GPU resource type
135 */
136enum cgs_resource_type {
137 CGS_RESOURCE_TYPE_MMIO = 0,
138 CGS_RESOURCE_TYPE_FB,
139 CGS_RESOURCE_TYPE_IO,
140 CGS_RESOURCE_TYPE_DOORBELL,
141 CGS_RESOURCE_TYPE_ROM,
142};
143
d03846af
CZ		 144/**
145 * struct cgs_clock_limits - Clock limits
146 *
147 * Clocks are specified in 10KHz units.
148 */
149struct cgs_clock_limits {
150 unsigned min; /**< Minimum supported frequency */
151 unsigned max; /**< Maxumim supported frequency */
152 unsigned sustainable; /**< Thermally sustainable frequency */
153};
154
bf3911b0
JZ		 155/**
156 * struct cgs_firmware_info - Firmware information
157 */
158struct cgs_firmware_info {
159 uint16_t version;
160 uint16_t feature_version;
161 uint32_t image_size;
162 uint64_t mc_addr;
163 void *kptr;
164};
165
47bf18b5
RZ		 166struct cgs_mode_info {
167 uint32_t refresh_rate;
168 uint32_t ref_clock;
169 uint32_t vblank_time_us;
170};
171
172struct cgs_display_info {
173 uint32_t display_count;
174 uint32_t active_display_mask;
175 struct cgs_mode_info *mode_info;
176};
177
d03846af
CZ		 178typedef unsigned long cgs_handle_t;
179
3f1d35a0
RZ		 180#define CGS_ACPI_METHOD_ATCS 0x53435441
181#define CGS_ACPI_METHOD_ATIF 0x46495441
182#define CGS_ACPI_METHOD_ATPX 0x58505441
183#define CGS_ACPI_FIELD_METHOD_NAME 0x00000001
184#define CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT 0x00000002
185#define CGS_ACPI_MAX_BUFFER_SIZE 256
186#define CGS_ACPI_TYPE_ANY 0x00
187#define CGS_ACPI_TYPE_INTEGER 0x01
188#define CGS_ACPI_TYPE_STRING 0x02
189#define CGS_ACPI_TYPE_BUFFER 0x03
190#define CGS_ACPI_TYPE_PACKAGE 0x04
191
192struct cgs_acpi_method_argument {
193 uint32_t type;
3f1d35a0
RZ		 194 uint32_t data_length;
195 union{
196 uint32_t value;
197 void *pointer;
198 };
199};
200
201struct cgs_acpi_method_info {
202 uint32_t size;
203 uint32_t field;
204 uint32_t input_count;
205 uint32_t name;
206 struct cgs_acpi_method_argument *pinput_argument;
207 uint32_t output_count;
208 struct cgs_acpi_method_argument *poutput_argument;
209 uint32_t padding[9];
210};
211
d03846af
CZ		 212/**
213 * cgs_gpu_mem_info() - Return information about memory heaps
214 * @cgs_device: opaque device handle
215 * @type: memory type
216 * @mc_start: Start MC address of the heap (output)
217 * @mc_size: MC address space size (output)
218 * @mem_size: maximum amount of memory available for allocation (output)
219 *
220 * This function returns information about memory heaps. The type
221 * parameter is used to select the memory heap. The mc_start and
222 * mc_size for GART heaps may be bigger than the memory available for
223 * allocation.
224 *
225 * mc_start and mc_size are undefined for non-contiguous FB memory
226 * types, since buffers allocated with these types may or may not be
227 * GART mapped.
228 *
229 * Return: 0 on success, -errno otherwise
230 */
110e6f26 231typedef int (*cgs_gpu_mem_info_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
d03846af
CZ		 232 uint64_t *mc_start, uint64_t *mc_size,
233 uint64_t *mem_size);
234
235/**
236 * cgs_gmap_kmem() - map kernel memory to GART aperture
237 * @cgs_device: opaque device handle
238 * @kmem: pointer to kernel memory
239 * @size: size to map
240 * @min_offset: minimum offset from start of GART aperture
241 * @max_offset: maximum offset from start of GART aperture
242 * @kmem_handle: kernel memory handle (output)
243 * @mcaddr: MC address (output)
244 *
245 * Return: 0 on success, -errno otherwise
246 */
110e6f26 247typedef int (*cgs_gmap_kmem_t)(struct cgs_device *cgs_device, void *kmem, uint64_t size,
d03846af
CZ		 248 uint64_t min_offset, uint64_t max_offset,
249 cgs_handle_t *kmem_handle, uint64_t *mcaddr);
250
251/**
252 * cgs_gunmap_kmem() - unmap kernel memory
253 * @cgs_device: opaque device handle
254 * @kmem_handle: kernel memory handle returned by gmap_kmem
255 *
256 * Return: 0 on success, -errno otherwise
257 */
110e6f26 258typedef int (*cgs_gunmap_kmem_t)(struct cgs_device *cgs_device, cgs_handle_t kmem_handle);
d03846af
CZ		 259
260/**
261 * cgs_alloc_gpu_mem() - Allocate GPU memory
262 * @cgs_device: opaque device handle
263 * @type: memory type
264 * @size: size in bytes
265 * @align: alignment in bytes
266 * @min_offset: minimum offset from start of heap
267 * @max_offset: maximum offset from start of heap
268 * @handle: memory handle (output)
269 *
270 * The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous
271 * memory allocation. This guarantees that the MC address returned by
272 * cgs_gmap_gpu_mem is not mapped through the GART. The non-contiguous
273 * FB memory types may be GART mapped depending on memory
274 * fragmentation and memory allocator policies.
275 *
276 * If min/max_offset are non-0, the allocation will be forced to
277 * reside between these offsets in its respective memory heap. The
278 * base address that the offset relates to, depends on the memory
279 * type.
280 *
281 * - CGS_GPU_MEM_TYPE__*_CONTIG_FB: FB MC base address
282 * - CGS_GPU_MEM_TYPE__GART_*: GART aperture base address
283 * - others: undefined, don't use with max_offset
284 *
285 * Return: 0 on success, -errno otherwise
286 */
110e6f26 287typedef int (*cgs_alloc_gpu_mem_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
d03846af
CZ		 288 uint64_t size, uint64_t align,
289 uint64_t min_offset, uint64_t max_offset,
290 cgs_handle_t *handle);
291
292/**
293 * cgs_free_gpu_mem() - Free GPU memory
294 * @cgs_device: opaque device handle
295 * @handle: memory handle returned by alloc or import
296 *
297 * Return: 0 on success, -errno otherwise
298 */
110e6f26 299typedef int (*cgs_free_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
d03846af
CZ		 300
301/**
302 * cgs_gmap_gpu_mem() - GPU-map GPU memory
303 * @cgs_device: opaque device handle
304 * @handle: memory handle returned by alloc or import
305 * @mcaddr: MC address (output)
306 *
307 * Ensures that a buffer is GPU accessible and returns its MC address.
308 *
309 * Return: 0 on success, -errno otherwise
310 */
110e6f26 311typedef int (*cgs_gmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle,
d03846af
CZ		 312 uint64_t *mcaddr);
313
314/**
315 * cgs_gunmap_gpu_mem() - GPU-unmap GPU memory
316 * @cgs_device: opaque device handle
317 * @handle: memory handle returned by alloc or import
318 *
319 * Allows the buffer to be migrated while it's not used by the GPU.
320 *
321 * Return: 0 on success, -errno otherwise
322 */
110e6f26 323typedef int (*cgs_gunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
d03846af
CZ		 324
325/**
326 * cgs_kmap_gpu_mem() - Kernel-map GPU memory
327 *
328 * @cgs_device: opaque device handle
329 * @handle: memory handle returned by alloc or import
330 * @map: Kernel virtual address the memory was mapped to (output)
331 *
332 * Return: 0 on success, -errno otherwise
333 */
110e6f26 334typedef int (*cgs_kmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle,
d03846af
CZ		 335 void **map);
336
337/**
338 * cgs_kunmap_gpu_mem() - Kernel-unmap GPU memory
339 * @cgs_device: opaque device handle
340 * @handle: memory handle returned by alloc or import
341 *
342 * Return: 0 on success, -errno otherwise
343 */
110e6f26 344typedef int (*cgs_kunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
d03846af
CZ		 345
346/**
347 * cgs_read_register() - Read an MMIO register
348 * @cgs_device: opaque device handle
349 * @offset: register offset
350 *
351 * Return: register value
352 */
110e6f26 353typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset);
d03846af
CZ		 354
355/**
356 * cgs_write_register() - Write an MMIO register
357 * @cgs_device: opaque device handle
358 * @offset: register offset
359 * @value: register value
360 */
110e6f26 361typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset,
d03846af
CZ		 362 uint32_t value);
363
364/**
365 * cgs_read_ind_register() - Read an indirect register
366 * @cgs_device: opaque device handle
367 * @offset: register offset
368 *
369 * Return: register value
370 */
110e6f26 371typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
d03846af
CZ		 372 unsigned index);
373
374/**
375 * cgs_write_ind_register() - Write an indirect register
376 * @cgs_device: opaque device handle
377 * @offset: register offset
378 * @value: register value
379 */
110e6f26 380typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
d03846af
CZ		 381 unsigned index, uint32_t value);
382
383/**
384 * cgs_read_pci_config_byte() - Read byte from PCI configuration space
385 * @cgs_device: opaque device handle
386 * @addr: address
387 *
388 * Return: Value read
389 */
110e6f26 390typedef uint8_t (*cgs_read_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr);
d03846af
CZ		 391
392/**
393 * cgs_read_pci_config_word() - Read word from PCI configuration space
394 * @cgs_device: opaque device handle
395 * @addr: address, must be word-aligned
396 *
397 * Return: Value read
398 */
110e6f26 399typedef uint16_t (*cgs_read_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr);
d03846af
CZ		 400
401/**
402 * cgs_read_pci_config_dword() - Read dword from PCI configuration space
403 * @cgs_device: opaque device handle
404 * @addr: address, must be dword-aligned
405 *
406 * Return: Value read
407 */
110e6f26 408typedef uint32_t (*cgs_read_pci_config_dword_t)(struct cgs_device *cgs_device,
d03846af
CZ		 409 unsigned addr);
410
411/**
412 * cgs_write_pci_config_byte() - Write byte to PCI configuration space
413 * @cgs_device: opaque device handle
414 * @addr: address
415 * @value: value to write
416 */
110e6f26 417typedef void (*cgs_write_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr,
d03846af
CZ		 418 uint8_t value);
419
420/**
421 * cgs_write_pci_config_word() - Write byte to PCI configuration space
422 * @cgs_device: opaque device handle
423 * @addr: address, must be word-aligned
424 * @value: value to write
425 */
110e6f26 426typedef void (*cgs_write_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr,
d03846af
CZ		 427 uint16_t value);
428
429/**
430 * cgs_write_pci_config_dword() - Write byte to PCI configuration space
431 * @cgs_device: opaque device handle
432 * @addr: address, must be dword-aligned
433 * @value: value to write
434 */
110e6f26 435typedef void (*cgs_write_pci_config_dword_t)(struct cgs_device *cgs_device, unsigned addr,
d03846af
CZ		 436 uint32_t value);
437
ba228ac8
AD		 438
439/**
440 * cgs_get_pci_resource() - provide access to a device resource (PCI BAR)
441 * @cgs_device: opaque device handle
442 * @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL)
443 * @size: size of the region
444 * @offset: offset from the start of the region
445 * @resource_base: base address (not including offset) returned
446 *
447 * Return: 0 on success, -errno otherwise
448 */
110e6f26 449typedef int (*cgs_get_pci_resource_t)(struct cgs_device *cgs_device,
ba228ac8
AD		 450 enum cgs_resource_type resource_type,
451 uint64_t size,
452 uint64_t offset,
453 uint64_t *resource_base);
454
d03846af
CZ		 455/**
456 * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table
457 * @cgs_device: opaque device handle
458 * @table: data table index
459 * @size: size of the table (output, may be NULL)
460 * @frev: table format revision (output, may be NULL)
461 * @crev: table content revision (output, may be NULL)
462 *
463 * Return: Pointer to start of the table, or NULL on failure
464 */
465typedef const void *(*cgs_atom_get_data_table_t)(
110e6f26 466 struct cgs_device *cgs_device, unsigned table,
d03846af
CZ		 467 uint16_t *size, uint8_t *frev, uint8_t *crev);
468
469/**
470 * cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions
471 * @cgs_device: opaque device handle
472 * @table: data table index
473 * @frev: table format revision (output, may be NULL)
474 * @crev: table content revision (output, may be NULL)
475 *
476 * Return: 0 on success, -errno otherwise
477 */
110e6f26 478typedef int (*cgs_atom_get_cmd_table_revs_t)(struct cgs_device *cgs_device, unsigned table,
d03846af
CZ		 479 uint8_t *frev, uint8_t *crev);
480
481/**
482 * cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table
483 * @cgs_device: opaque device handle
484 * @table: command table index
485 * @args: arguments
486 *
487 * Return: 0 on success, -errno otherwise
488 */
110e6f26 489typedef int (*cgs_atom_exec_cmd_table_t)(struct cgs_device *cgs_device,
d03846af
CZ		 490 unsigned table, void *args);
491
492/**
493 * cgs_create_pm_request() - Create a power management request
494 * @cgs_device: opaque device handle
495 * @request: handle of created PM request (output)
496 *
497 * Return: 0 on success, -errno otherwise
498 */
110e6f26 499typedef int (*cgs_create_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t *request);
d03846af
CZ		 500
501/**
502 * cgs_destroy_pm_request() - Destroy a power management request
503 * @cgs_device: opaque device handle
504 * @request: handle of created PM request
505 *
506 * Return: 0 on success, -errno otherwise
507 */
110e6f26 508typedef int (*cgs_destroy_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request);
d03846af
CZ		 509
510/**
511 * cgs_set_pm_request() - Activate or deactiveate a PM request
512 * @cgs_device: opaque device handle
513 * @request: PM request handle
514 * @active: 0 = deactivate, non-0 = activate
515 *
516 * While a PM request is active, its minimum clock requests are taken
517 * into account as the requested engines are powered up. When the
518 * request is inactive, the engines may be powered down and clocks may
519 * be lower, depending on other PM requests by other driver
520 * components.
521 *
522 * Return: 0 on success, -errno otherwise
523 */
110e6f26 524typedef int (*cgs_set_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request,
d03846af
CZ		 525 int active);
526
527/**
528 * cgs_pm_request_clock() - Request a minimum frequency for a specific clock
529 * @cgs_device: opaque device handle
530 * @request: PM request handle
531 * @clock: which clock?
532 * @freq: requested min. frequency in 10KHz units (0 to clear request)
533 *
534 * Return: 0 on success, -errno otherwise
535 */
110e6f26 536typedef int (*cgs_pm_request_clock_t)(struct cgs_device *cgs_device, cgs_handle_t request,
d03846af
CZ		 537 enum cgs_clock clock, unsigned freq);
538
539/**
540 * cgs_pm_request_engine() - Request an engine to be powered up
541 * @cgs_device: opaque device handle
542 * @request: PM request handle
543 * @engine: which engine?
544 * @powered: 0 = powered down, non-0 = powered up
545 *
546 * Return: 0 on success, -errno otherwise
547 */
110e6f26 548typedef int (*cgs_pm_request_engine_t)(struct cgs_device *cgs_device, cgs_handle_t request,
d03846af
CZ		 549 enum cgs_engine engine, int powered);
550
551/**
552 * cgs_pm_query_clock_limits() - Query clock frequency limits
553 * @cgs_device: opaque device handle
554 * @clock: which clock?
555 * @limits: clock limits
556 *
557 * Return: 0 on success, -errno otherwise
558 */
110e6f26 559typedef int (*cgs_pm_query_clock_limits_t)(struct cgs_device *cgs_device,
d03846af
CZ		 560 enum cgs_clock clock,
561 struct cgs_clock_limits *limits);
562
563/**
564 * cgs_set_camera_voltages() - Apply specific voltages to PMIC voltage planes
565 * @cgs_device: opaque device handle
566 * @mask: bitmask of voltages to change (1<<CGS_VOLTAGE_PLANE__xyz|...)
567 * @voltages: pointer to array of voltage values in 1mV units
568 *
569 * Return: 0 on success, -errno otherwise
570 */
110e6f26 571typedef int (*cgs_set_camera_voltages_t)(struct cgs_device *cgs_device, uint32_t mask,
d03846af 572 const uint32_t *voltages);
bf3911b0
JZ		 573/**
574 * cgs_get_firmware_info - Get the firmware information from core driver
575 * @cgs_device: opaque device handle
576 * @type: the firmware type
577 * @info: returend firmware information
578 *
579 * Return: 0 on success, -errno otherwise
580 */
110e6f26 581typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device,
bf3911b0
JZ		 582 enum cgs_ucode_id type,
583 struct cgs_firmware_info *info);
584
a392746a
ML		 585typedef int (*cgs_rel_firmware)(struct cgs_device *cgs_device,
586 enum cgs_ucode_id type);
587
110e6f26 588typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device,
404b2fa3 589 enum amd_ip_block_type block_type,
590 enum amd_powergating_state state);
591
110e6f26 592typedef int(*cgs_set_clockgating_state)(struct cgs_device *cgs_device,
404b2fa3 593 enum amd_ip_block_type block_type,
594 enum amd_clockgating_state state);
d03846af 595
47bf18b5 596typedef int(*cgs_get_active_displays_info)(
110e6f26 597 struct cgs_device *cgs_device,
47bf18b5
RZ		 598 struct cgs_display_info *info);
599
110e6f26 600typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled);
4c90080b 601
110e6f26 602typedef int (*cgs_call_acpi_method)(struct cgs_device *cgs_device,
3f1d35a0
RZ		 603 uint32_t acpi_method,
604 uint32_t acpi_function,
605 void *pinput, void *poutput,
606 uint32_t output_count,
607 uint32_t input_size,
608 uint32_t output_size);
5e618699 609
110e6f26 610typedef int (*cgs_query_system_info)(struct cgs_device *cgs_device,
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RZ		 611 struct cgs_system_info *sys_info);
612
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CZ		 613struct cgs_ops {
614 /* memory management calls (similar to KFD interface) */
615 cgs_gpu_mem_info_t gpu_mem_info;
616 cgs_gmap_kmem_t gmap_kmem;
617 cgs_gunmap_kmem_t gunmap_kmem;
618 cgs_alloc_gpu_mem_t alloc_gpu_mem;
619 cgs_free_gpu_mem_t free_gpu_mem;
620 cgs_gmap_gpu_mem_t gmap_gpu_mem;
621 cgs_gunmap_gpu_mem_t gunmap_gpu_mem;
622 cgs_kmap_gpu_mem_t kmap_gpu_mem;
623 cgs_kunmap_gpu_mem_t kunmap_gpu_mem;
624 /* MMIO access */
625 cgs_read_register_t read_register;
626 cgs_write_register_t write_register;
627 cgs_read_ind_register_t read_ind_register;
628 cgs_write_ind_register_t write_ind_register;
629 /* PCI configuration space access */
630 cgs_read_pci_config_byte_t read_pci_config_byte;
631 cgs_read_pci_config_word_t read_pci_config_word;
632 cgs_read_pci_config_dword_t read_pci_config_dword;
633 cgs_write_pci_config_byte_t write_pci_config_byte;
634 cgs_write_pci_config_word_t write_pci_config_word;
635 cgs_write_pci_config_dword_t write_pci_config_dword;
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AD		 636 /* PCI resources */
637 cgs_get_pci_resource_t get_pci_resource;
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CZ		 638 /* ATOM BIOS */
639 cgs_atom_get_data_table_t atom_get_data_table;
640 cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs;
641 cgs_atom_exec_cmd_table_t atom_exec_cmd_table;
642 /* Power management */
643 cgs_create_pm_request_t create_pm_request;
644 cgs_destroy_pm_request_t destroy_pm_request;
645 cgs_set_pm_request_t set_pm_request;
646 cgs_pm_request_clock_t pm_request_clock;
647 cgs_pm_request_engine_t pm_request_engine;
648 cgs_pm_query_clock_limits_t pm_query_clock_limits;
649 cgs_set_camera_voltages_t set_camera_voltages;
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JZ		 650 /* Firmware Info */
651 cgs_get_firmware_info get_firmware_info;
a392746a 652 cgs_rel_firmware rel_firmware;
404b2fa3 653 /* cg pg interface*/
654 cgs_set_powergating_state set_powergating_state;
655 cgs_set_clockgating_state set_clockgating_state;
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RZ		 656 /* display manager */
657 cgs_get_active_displays_info get_active_displays_info;
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RZ		 658 /* notify dpm enabled */
659 cgs_notify_dpm_enabled notify_dpm_enabled;
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RZ		 660 /* ACPI */
661 cgs_call_acpi_method call_acpi_method;
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RZ		 662 /* get system info */
663 cgs_query_system_info query_system_info;
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CZ		 664};
665
666struct cgs_os_ops; /* To be define in OS-specific CGS header */
667
668struct cgs_device
669{
670 const struct cgs_ops *ops;
671 const struct cgs_os_ops *os_ops;
672 /* to be embedded at the start of driver private structure */
673};
674
675/* Convenience macros that make CGS indirect function calls look like
676 * normal function calls */
677#define CGS_CALL(func,dev,...) \
678 (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__))
679#define CGS_OS_CALL(func,dev,...) \
680 (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__))
681
682#define cgs_gpu_mem_info(dev,type,mc_start,mc_size,mem_size) \
683 CGS_CALL(gpu_mem_info,dev,type,mc_start,mc_size,mem_size)
684#define cgs_gmap_kmem(dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) \
685 CGS_CALL(gmap_kmem,dev,kmem,size,min_off,max_off,kmem_handle,mcaddr)
97baee71 686#define cgs_gunmap_kmem(dev,kmem_handle) \
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CZ		 687 CGS_CALL(gunmap_kmem,dev,keme_handle)
688#define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle) \
689 CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle)
690#define cgs_free_gpu_mem(dev,handle) \
691 CGS_CALL(free_gpu_mem,dev,handle)
692#define cgs_gmap_gpu_mem(dev,handle,mcaddr) \
693 CGS_CALL(gmap_gpu_mem,dev,handle,mcaddr)
97baee71 694#define cgs_gunmap_gpu_mem(dev,handle) \
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CZ		 695 CGS_CALL(gunmap_gpu_mem,dev,handle)
696#define cgs_kmap_gpu_mem(dev,handle,map) \
697 CGS_CALL(kmap_gpu_mem,dev,handle,map)
698#define cgs_kunmap_gpu_mem(dev,handle) \
699 CGS_CALL(kunmap_gpu_mem,dev,handle)
700
701#define cgs_read_register(dev,offset) \
702 CGS_CALL(read_register,dev,offset)
703#define cgs_write_register(dev,offset,value) \
704 CGS_CALL(write_register,dev,offset,value)
705#define cgs_read_ind_register(dev,space,index) \
706 CGS_CALL(read_ind_register,dev,space,index)
707#define cgs_write_ind_register(dev,space,index,value) \
708 CGS_CALL(write_ind_register,dev,space,index,value)
709
710#define cgs_read_pci_config_byte(dev,addr) \
711 CGS_CALL(read_pci_config_byte,dev,addr)
712#define cgs_read_pci_config_word(dev,addr) \
713 CGS_CALL(read_pci_config_word,dev,addr)
714#define cgs_read_pci_config_dword(dev,addr) \
715 CGS_CALL(read_pci_config_dword,dev,addr)
716#define cgs_write_pci_config_byte(dev,addr,value) \
717 CGS_CALL(write_pci_config_byte,dev,addr,value)
718#define cgs_write_pci_config_word(dev,addr,value) \
719 CGS_CALL(write_pci_config_word,dev,addr,value)
720#define cgs_write_pci_config_dword(dev,addr,value) \
721 CGS_CALL(write_pci_config_dword,dev,addr,value)
722
723#define cgs_atom_get_data_table(dev,table,size,frev,crev) \
724 CGS_CALL(atom_get_data_table,dev,table,size,frev,crev)
725#define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \
726 CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev)
727#define cgs_atom_exec_cmd_table(dev,table,args) \
728 CGS_CALL(atom_exec_cmd_table,dev,table,args)
729
730#define cgs_create_pm_request(dev,request) \
731 CGS_CALL(create_pm_request,dev,request)
732#define cgs_destroy_pm_request(dev,request) \
733 CGS_CALL(destroy_pm_request,dev,request)
734#define cgs_set_pm_request(dev,request,active) \
735 CGS_CALL(set_pm_request,dev,request,active)
736#define cgs_pm_request_clock(dev,request,clock,freq) \
737 CGS_CALL(pm_request_clock,dev,request,clock,freq)
738#define cgs_pm_request_engine(dev,request,engine,powered) \
739 CGS_CALL(pm_request_engine,dev,request,engine,powered)
740#define cgs_pm_query_clock_limits(dev,clock,limits) \
741 CGS_CALL(pm_query_clock_limits,dev,clock,limits)
742#define cgs_set_camera_voltages(dev,mask,voltages) \
743 CGS_CALL(set_camera_voltages,dev,mask,voltages)
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JZ		 744#define cgs_get_firmware_info(dev, type, info) \
745 CGS_CALL(get_firmware_info, dev, type, info)
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ML		 746#define cgs_rel_firmware(dev, type) \
747 CGS_CALL(rel_firmware, dev, type)
404b2fa3 748#define cgs_set_powergating_state(dev, block_type, state) \
749 CGS_CALL(set_powergating_state, dev, block_type, state)
750#define cgs_set_clockgating_state(dev, block_type, state) \
751 CGS_CALL(set_clockgating_state, dev, block_type, state)
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RZ		 752#define cgs_notify_dpm_enabled(dev, enabled) \
753 CGS_CALL(notify_dpm_enabled, dev, enabled)
754
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RZ		 755#define cgs_get_active_displays_info(dev, info) \
756 CGS_CALL(get_active_displays_info, dev, info)
4c90080b 757
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RZ		 758#define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) \
759 CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)
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RZ		 760#define cgs_query_system_info(dev, sys_info) \
761 CGS_CALL(query_system_info, dev, sys_info)
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AD		 762#define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \
763 resource_base) \
764 CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \
765 resource_base)
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CZ		 766
767#endif /* _CGS_COMMON_H */
Linux 6.x block layer and io_uring tree(s)