[linux-block.git] / drivers / gpu / drm / amd / display / dmub / src / dmub_srv.c

/*
 * Copyright 2019 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#include "../inc/dmub_srv.h"
#include "dmub_dcn20.h"
#include "dmub_dcn21.h"
#include "dmub_trace_buffer.h"
#include "os_types.h"
/*
 * Note: the DMUB service is standalone. No additional headers should be
 * added below or above this line unless they reside within the DMUB
 * folder.
 */

/* Alignment for framebuffer memory. */
#define DMUB_FB_ALIGNMENT (1024 * 1024)

/* Stack size. */
#define DMUB_STACK_SIZE (128 * 1024)

/* Context size. */
#define DMUB_CONTEXT_SIZE (512 * 1024)

/* Mailbox size */
#define DMUB_MAILBOX_SIZE (DMUB_RB_SIZE)


/* Number of windows in use. */
#define DMUB_NUM_WINDOWS (DMUB_WINDOW_6_FW_STATE + 1)
/* Base addresses. */

#define DMUB_CW0_BASE (0x60000000)
#define DMUB_CW1_BASE (0x61000000)
#define DMUB_CW3_BASE (0x63000000)
#define DMUB_CW5_BASE (0x65000000)
#define DMUB_CW6_BASE (0x66000000)

static inline uint32_t dmub_align(uint32_t val, uint32_t factor)
{
	return (val + factor - 1) / factor * factor;
}

static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
{
	struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs;

	switch (asic) {
	case DMUB_ASIC_DCN20:
	case DMUB_ASIC_DCN21:
		funcs->reset = dmub_dcn20_reset;
		funcs->reset_release = dmub_dcn20_reset_release;
		funcs->backdoor_load = dmub_dcn20_backdoor_load;
		funcs->setup_windows = dmub_dcn20_setup_windows;
		funcs->setup_mailbox = dmub_dcn20_setup_mailbox;
		funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr;
		funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr;
		funcs->is_supported = dmub_dcn20_is_supported;
		funcs->is_hw_init = dmub_dcn20_is_hw_init;

		if (asic == DMUB_ASIC_DCN21) {
			funcs->backdoor_load = dmub_dcn21_backdoor_load;
			funcs->setup_windows = dmub_dcn21_setup_windows;
			funcs->is_auto_load_done = dmub_dcn21_is_auto_load_done;
			funcs->is_phy_init = dmub_dcn21_is_phy_init;
		}
		break;

	default:
		return false;
	}

	return true;
}

enum dmub_status dmub_srv_create(struct dmub_srv *dmub,
				 const struct dmub_srv_create_params *params)
{
	enum dmub_status status = DMUB_STATUS_OK;

	dmub_memset(dmub, 0, sizeof(*dmub));

	dmub->funcs = params->funcs;
	dmub->user_ctx = params->user_ctx;
	dmub->asic = params->asic;
	dmub->is_virtual = params->is_virtual;

	/* Setup asic dependent hardware funcs. */
	if (!dmub_srv_hw_setup(dmub, params->asic)) {
		status = DMUB_STATUS_INVALID;
		goto cleanup;
	}

	/* Override (some) hardware funcs based on user params. */
	if (params->hw_funcs) {
		if (params->hw_funcs->get_inbox1_rptr)
			dmub->hw_funcs.get_inbox1_rptr =
				params->hw_funcs->get_inbox1_rptr;

		if (params->hw_funcs->set_inbox1_wptr)
			dmub->hw_funcs.set_inbox1_wptr =
				params->hw_funcs->set_inbox1_wptr;

		if (params->hw_funcs->is_supported)
			dmub->hw_funcs.is_supported =
				params->hw_funcs->is_supported;
	}

	/* Sanity checks for required hw func pointers. */
	if (!dmub->hw_funcs.get_inbox1_rptr ||
	    !dmub->hw_funcs.set_inbox1_wptr) {
		status = DMUB_STATUS_INVALID;
		goto cleanup;
	}

cleanup:
	if (status == DMUB_STATUS_OK)
		dmub->sw_init = true;
	else
		dmub_srv_destroy(dmub);

	return status;
}

void dmub_srv_destroy(struct dmub_srv *dmub)
{
	dmub_memset(dmub, 0, sizeof(*dmub));
}

enum dmub_status
dmub_srv_calc_region_info(struct dmub_srv *dmub,
			  const struct dmub_srv_region_params *params,
			  struct dmub_srv_region_info *out)
{
	struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST];
	struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK];
	struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA];
	struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS];
	struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX];
	struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF];
	struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE];

	if (!dmub->sw_init)
		return DMUB_STATUS_INVALID;

	memset(out, 0, sizeof(*out));

	out->num_regions = DMUB_NUM_WINDOWS;

	inst->base = 0x0;
	inst->top = inst->base + params->inst_const_size;

	data->base = dmub_align(inst->top, 256);
	data->top = data->base + params->bss_data_size;

	stack->base = dmub_align(data->top, 256);
	stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE;

	bios->base = dmub_align(stack->top, 256);
	bios->top = bios->base + params->vbios_size;

	mail->base = dmub_align(bios->top, 256);
	mail->top = mail->base + DMUB_MAILBOX_SIZE;

	trace_buff->base = dmub_align(mail->top, 256);
	trace_buff->top = trace_buff->base + TRACE_BUF_SIZE;

	fw_state->base = dmub_align(trace_buff->top, 256);

	/* Align firmware state to size of cache line. */
	fw_state->top =
		fw_state->base + dmub_align(sizeof(struct dmub_fw_state), 64);

	out->fb_size = dmub_align(fw_state->top, 4096);

	return DMUB_STATUS_OK;
}

enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub,
				       const struct dmub_srv_fb_params *params,
				       struct dmub_srv_fb_info *out)
{
	uint8_t *cpu_base;
	uint64_t gpu_base;
	uint32_t i;

	if (!dmub->sw_init)
		return DMUB_STATUS_INVALID;

	memset(out, 0, sizeof(*out));

	if (params->region_info->num_regions != DMUB_NUM_WINDOWS)
		return DMUB_STATUS_INVALID;

	cpu_base = (uint8_t *)params->cpu_addr;
	gpu_base = params->gpu_addr;

	for (i = 0; i < DMUB_NUM_WINDOWS; ++i) {
		const struct dmub_region *reg =
			&params->region_info->regions[i];

		out->fb[i].cpu_addr = cpu_base + reg->base;
		out->fb[i].gpu_addr = gpu_base + reg->base;
		out->fb[i].size = reg->top - reg->base;
	}

	out->num_fb = DMUB_NUM_WINDOWS;

	return DMUB_STATUS_OK;
}

enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,
					 bool *is_supported)
{
	*is_supported = false;

	if (!dmub->sw_init)
		return DMUB_STATUS_INVALID;

	if (dmub->hw_funcs.is_supported)
		*is_supported = dmub->hw_funcs.is_supported(dmub);

	return DMUB_STATUS_OK;
}

enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init)
{
	*is_hw_init = false;

	if (!dmub->sw_init)
		return DMUB_STATUS_INVALID;

	if (dmub->hw_funcs.is_hw_init)
		*is_hw_init = dmub->hw_funcs.is_hw_init(dmub);

	return DMUB_STATUS_OK;
}

enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
				  const struct dmub_srv_hw_params *params)
{
	struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST];
	struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK];
	struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA];
	struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS];
	struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX];
	struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF];
	struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE];

	struct dmub_rb_init_params rb_params;
	struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6;
	struct dmub_region inbox1;

	if (!dmub->sw_init)
		return DMUB_STATUS_INVALID;

	dmub->fb_base = params->fb_base;
	dmub->fb_offset = params->fb_offset;
	dmub->psp_version = params->psp_version;

	if (inst_fb && data_fb) {
		cw0.offset.quad_part = inst_fb->gpu_addr;
		cw0.region.base = DMUB_CW0_BASE;
		cw0.region.top = cw0.region.base + inst_fb->size - 1;

		cw1.offset.quad_part = stack_fb->gpu_addr;
		cw1.region.base = DMUB_CW1_BASE;
		cw1.region.top = cw1.region.base + stack_fb->size - 1;

		if (params->load_inst_const && dmub->hw_funcs.backdoor_load)
			dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
	}

	if (dmub->hw_funcs.reset)
		dmub->hw_funcs.reset(dmub);

	if (inst_fb && data_fb && bios_fb && mail_fb && tracebuff_fb &&
	    fw_state_fb) {
		cw2.offset.quad_part = data_fb->gpu_addr;
		cw2.region.base = DMUB_CW0_BASE + inst_fb->size;
		cw2.region.top = cw2.region.base + data_fb->size;

		cw3.offset.quad_part = bios_fb->gpu_addr;
		cw3.region.base = DMUB_CW3_BASE;
		cw3.region.top = cw3.region.base + bios_fb->size;

		cw4.offset.quad_part = mail_fb->gpu_addr;
		cw4.region.base = cw3.region.top + 1;
		cw4.region.top = cw4.region.base + mail_fb->size;

		inbox1.base = cw4.region.base;
		inbox1.top = cw4.region.top;

		cw5.offset.quad_part = tracebuff_fb->gpu_addr;
		cw5.region.base = DMUB_CW5_BASE;
		cw5.region.top = cw5.region.base + tracebuff_fb->size;

		cw6.offset.quad_part = fw_state_fb->gpu_addr;
		cw6.region.base = DMUB_CW6_BASE;
		cw6.region.top = cw6.region.base + fw_state_fb->size;

		dmub->fw_state = fw_state_fb->cpu_addr;

		if (dmub->hw_funcs.setup_windows)
			dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4,
						     &cw5, &cw6);

		if (dmub->hw_funcs.setup_mailbox)
			dmub->hw_funcs.setup_mailbox(dmub, &inbox1);
	}

	if (mail_fb) {
		dmub_memset(&rb_params, 0, sizeof(rb_params));
		rb_params.ctx = dmub;
		rb_params.base_address = mail_fb->cpu_addr;
		rb_params.capacity = DMUB_RB_SIZE;

		dmub_rb_init(&dmub->inbox1_rb, &rb_params);
	}

	if (dmub->hw_funcs.reset_release)
		dmub->hw_funcs.reset_release(dmub);

	dmub->hw_init = true;

	return DMUB_STATUS_OK;
}

enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub,
				    const struct dmub_cmd_header *cmd)
{
	if (!dmub->hw_init)
		return DMUB_STATUS_INVALID;

	if (dmub_rb_push_front(&dmub->inbox1_rb, cmd))
		return DMUB_STATUS_OK;

	return DMUB_STATUS_QUEUE_FULL;
}

enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub)
{
	if (!dmub->hw_init)
		return DMUB_STATUS_INVALID;

	dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt);
	return DMUB_STATUS_OK;
}

enum dmub_status dmub_srv_cmd_submit(struct dmub_srv *dmub,
				     const struct dmub_cmd_header *cmd,
				     uint32_t timeout_us)
{
	uint32_t i = 0;

	if (!dmub->hw_init)
		return DMUB_STATUS_INVALID;

	for (i = 0; i <= timeout_us; ++i) {
		dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
		if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) {
			dmub->hw_funcs.set_inbox1_wptr(dmub,
						       dmub->inbox1_rb.wrpt);
			return DMUB_STATUS_OK;
		}

		udelay(1);
	}

	return DMUB_STATUS_TIMEOUT;
}

enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,
					     uint32_t timeout_us)
{
	uint32_t i;

	if (!dmub->hw_init)
		return DMUB_STATUS_INVALID;

	if (!dmub->hw_funcs.is_auto_load_done)
		return DMUB_STATUS_OK;

	for (i = 0; i <= timeout_us; i += 100) {
		if (dmub->hw_funcs.is_auto_load_done(dmub))
			return DMUB_STATUS_OK;

		udelay(100);
	}

	return DMUB_STATUS_TIMEOUT;
}

enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,
					    uint32_t timeout_us)
{
	uint32_t i = 0;

	if (!dmub->hw_init)
		return DMUB_STATUS_INVALID;

	if (!dmub->hw_funcs.is_phy_init)
		return DMUB_STATUS_OK;

	for (i = 0; i <= timeout_us; i += 10) {
		if (dmub->hw_funcs.is_phy_init(dmub))
			return DMUB_STATUS_OK;

		udelay(10);
	}

	return DMUB_STATUS_TIMEOUT;
}

enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,
					uint32_t timeout_us)
{
	uint32_t i;

	if (!dmub->hw_init)
		return DMUB_STATUS_INVALID;

	for (i = 0; i <= timeout_us; ++i) {
		dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
		if (dmub_rb_empty(&dmub->inbox1_rb))
			return DMUB_STATUS_OK;

		udelay(1);
	}

	return DMUB_STATUS_TIMEOUT;
}
Commit	Line	Data
7c008829 NK	1	/*
	2	* Copyright 2019 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#include "../inc/dmub_srv.h"
	27	#include "dmub_dcn20.h"
	28	#include "dmub_dcn21.h"
b9e9f11c YS	29	#include "dmub_trace_buffer.h"
b9e9f11c YS	30	#include "os_types.h"
7c008829 NK	31	/*
	32	* Note: the DMUB service is standalone. No additional headers should be
	33	* added below or above this line unless they reside within the DMUB
	34	* folder.
	35	*/
	36
	37	/* Alignment for framebuffer memory. */
	38	#define DMUB_FB_ALIGNMENT (1024 * 1024)
	39
	40	/* Stack size. */
	41	#define DMUB_STACK_SIZE (128 * 1024)
	42
	43	/* Context size. */
	44	#define DMUB_CONTEXT_SIZE (512 * 1024)
	45
	46	/* Mailbox size */
	47	#define DMUB_MAILBOX_SIZE (DMUB_RB_SIZE)
	48
7c008829 NK	49
7c008829 NK	50	/* Number of windows in use. */
2f39835c	51	#define DMUB_NUM_WINDOWS (DMUB_WINDOW_6_FW_STATE + 1)
7c008829 NK	52	/* Base addresses. */
	53
	54	#define DMUB_CW0_BASE (0x60000000)
	55	#define DMUB_CW1_BASE (0x61000000)
b9e9f11c	56	#define DMUB_CW3_BASE (0x63000000)
7c008829	57	#define DMUB_CW5_BASE (0x65000000)
2f39835c	58	#define DMUB_CW6_BASE (0x66000000)
7c008829 NK	59
	60	static inline uint32_t dmub_align(uint32_t val, uint32_t factor)
	61	{
	62	return (val + factor - 1) / factor * factor;
	63	}
	64
	65	static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
	66	{
	67	struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs;
	68
	69	switch (asic) {
	70	case DMUB_ASIC_DCN20:
	71	case DMUB_ASIC_DCN21:
	72	funcs->reset = dmub_dcn20_reset;
	73	funcs->reset_release = dmub_dcn20_reset_release;
	74	funcs->backdoor_load = dmub_dcn20_backdoor_load;
	75	funcs->setup_windows = dmub_dcn20_setup_windows;
	76	funcs->setup_mailbox = dmub_dcn20_setup_mailbox;
	77	funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr;
	78	funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr;
	79	funcs->is_supported = dmub_dcn20_is_supported;
c09eeee4	80	funcs->is_hw_init = dmub_dcn20_is_hw_init;
7c008829 NK	81
	82	if (asic == DMUB_ASIC_DCN21) {
	83	funcs->backdoor_load = dmub_dcn21_backdoor_load;
	84	funcs->setup_windows = dmub_dcn21_setup_windows;
	85	funcs->is_auto_load_done = dmub_dcn21_is_auto_load_done;
3c465370	86	funcs->is_phy_init = dmub_dcn21_is_phy_init;
7c008829 NK	87	}
	88	break;
	89
	90	default:
	91	return false;
	92	}
	93
	94	return true;
	95	}
	96
	97	enum dmub_status dmub_srv_create(struct dmub_srv *dmub,
	98	const struct dmub_srv_create_params *params)
	99	{
	100	enum dmub_status status = DMUB_STATUS_OK;
	101
	102	dmub_memset(dmub, 0, sizeof(*dmub));
	103
	104	dmub->funcs = params->funcs;
	105	dmub->user_ctx = params->user_ctx;
	106	dmub->asic = params->asic;
	107	dmub->is_virtual = params->is_virtual;
	108
	109	/* Setup asic dependent hardware funcs. */
	110	if (!dmub_srv_hw_setup(dmub, params->asic)) {
	111	status = DMUB_STATUS_INVALID;
	112	goto cleanup;
	113	}
	114
	115	/* Override (some) hardware funcs based on user params. */
	116	if (params->hw_funcs) {
	117	if (params->hw_funcs->get_inbox1_rptr)
	118	dmub->hw_funcs.get_inbox1_rptr =
	119	params->hw_funcs->get_inbox1_rptr;
	120
	121	if (params->hw_funcs->set_inbox1_wptr)
	122	dmub->hw_funcs.set_inbox1_wptr =
	123	params->hw_funcs->set_inbox1_wptr;
	124
	125	if (params->hw_funcs->is_supported)
	126	dmub->hw_funcs.is_supported =
	127	params->hw_funcs->is_supported;
	128	}
	129
	130	/* Sanity checks for required hw func pointers. */
	131	if (!dmub->hw_funcs.get_inbox1_rptr \|\|
	132	!dmub->hw_funcs.set_inbox1_wptr) {
	133	status = DMUB_STATUS_INVALID;
	134	goto cleanup;
	135	}
	136
	137	cleanup:
	138	if (status == DMUB_STATUS_OK)
	139	dmub->sw_init = true;
	140	else
	141	dmub_srv_destroy(dmub);
	142
	143	return status;
	144	}
	145
	146	void dmub_srv_destroy(struct dmub_srv *dmub)
	147	{
	148	dmub_memset(dmub, 0, sizeof(*dmub));
	149	}
	150
151	enum dmub_status
152	dmub_srv_calc_region_info(struct dmub_srv *dmub,
153	const struct dmub_srv_region_params *params,
154	struct dmub_srv_region_info *out)
155	{
156	struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST];
157	struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK];
158	struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA];
159	struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS];
160	struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX];
161	struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF];
2f39835c	162	struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE];
7c008829 NK	163
	164	if (!dmub->sw_init)
	165	return DMUB_STATUS_INVALID;
	166
	167	memset(out, 0, sizeof(*out));
	168
	169	out->num_regions = DMUB_NUM_WINDOWS;
	170
	171	inst->base = 0x0;
	172	inst->top = inst->base + params->inst_const_size;
	173
	174	data->base = dmub_align(inst->top, 256);
	175	data->top = data->base + params->bss_data_size;
	176
	177	stack->base = dmub_align(data->top, 256);
	178	stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE;
	179
	180	bios->base = dmub_align(stack->top, 256);
	181	bios->top = bios->base + params->vbios_size;
	182
	183	mail->base = dmub_align(bios->top, 256);
	184	mail->top = mail->base + DMUB_MAILBOX_SIZE;
	185
	186	trace_buff->base = dmub_align(mail->top, 256);
b9e9f11c	187	trace_buff->top = trace_buff->base + TRACE_BUF_SIZE;
7c008829	188
2f39835c NK	189	fw_state->base = dmub_align(trace_buff->top, 256);
	190
	191	/* Align firmware state to size of cache line. */
	192	fw_state->top =
	193	fw_state->base + dmub_align(sizeof(struct dmub_fw_state), 64);
	194
	195	out->fb_size = dmub_align(fw_state->top, 4096);
7c008829 NK	196
	197	return DMUB_STATUS_OK;
	198	}
	199
	200	enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub,
	201	const struct dmub_srv_fb_params *params,
	202	struct dmub_srv_fb_info *out)
	203	{
	204	uint8_t *cpu_base;
	205	uint64_t gpu_base;
	206	uint32_t i;
	207
	208	if (!dmub->sw_init)
	209	return DMUB_STATUS_INVALID;
	210
	211	memset(out, 0, sizeof(*out));
	212
	213	if (params->region_info->num_regions != DMUB_NUM_WINDOWS)
	214	return DMUB_STATUS_INVALID;
	215
	216	cpu_base = (uint8_t *)params->cpu_addr;
	217	gpu_base = params->gpu_addr;
	218
	219	for (i = 0; i < DMUB_NUM_WINDOWS; ++i) {
	220	const struct dmub_region *reg =
	221	&params->region_info->regions[i];
	222
	223	out->fb[i].cpu_addr = cpu_base + reg->base;
	224	out->fb[i].gpu_addr = gpu_base + reg->base;
	225	out->fb[i].size = reg->top - reg->base;
	226	}
	227
	228	out->num_fb = DMUB_NUM_WINDOWS;
	229
	230	return DMUB_STATUS_OK;
	231	}
	232
	233	enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,
	234	bool *is_supported)
	235	{
	236	*is_supported = false;
	237
	238	if (!dmub->sw_init)
	239	return DMUB_STATUS_INVALID;
	240
	241	if (dmub->hw_funcs.is_supported)
	242	*is_supported = dmub->hw_funcs.is_supported(dmub);
	243
	244	return DMUB_STATUS_OK;
	245	}
	246
c09eeee4 NK	247	enum dmub_status dmub_srv_is_hw_init(struct dmub_srv dmub, bool is_hw_init)
	248	{
	249	*is_hw_init = false;
	250
	251	if (!dmub->sw_init)
	252	return DMUB_STATUS_INVALID;
	253
	254	if (dmub->hw_funcs.is_hw_init)
	255	*is_hw_init = dmub->hw_funcs.is_hw_init(dmub);
	256
	257	return DMUB_STATUS_OK;
	258	}
	259
7c008829 NK	260	enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
	261	const struct dmub_srv_hw_params *params)
	262	{
	263	struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST];
	264	struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK];
	265	struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA];
	266	struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS];
	267	struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX];
	268	struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF];
2f39835c	269	struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE];
7c008829 NK	270
7c008829 NK	271	struct dmub_rb_init_params rb_params;
2f39835c	272	struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6;
7c008829 NK	273	struct dmub_region inbox1;
	274
	275	if (!dmub->sw_init)
	276	return DMUB_STATUS_INVALID;
	277
	278	dmub->fb_base = params->fb_base;
	279	dmub->fb_offset = params->fb_offset;
	280	dmub->psp_version = params->psp_version;
	281
	282	if (inst_fb && data_fb) {
	283	cw0.offset.quad_part = inst_fb->gpu_addr;
	284	cw0.region.base = DMUB_CW0_BASE;
	285	cw0.region.top = cw0.region.base + inst_fb->size - 1;
	286
	287	cw1.offset.quad_part = stack_fb->gpu_addr;
	288	cw1.region.base = DMUB_CW1_BASE;
	289	cw1.region.top = cw1.region.base + stack_fb->size - 1;
	290
ab16c736	291	if (params->load_inst_const && dmub->hw_funcs.backdoor_load)
7c008829 NK	292	dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
	293	}
	294
	295	if (dmub->hw_funcs.reset)
	296	dmub->hw_funcs.reset(dmub);
	297
2f39835c NK	298	if (inst_fb && data_fb && bios_fb && mail_fb && tracebuff_fb &&
2f39835c NK	299	fw_state_fb) {
7c008829 NK	300	cw2.offset.quad_part = data_fb->gpu_addr;
	301	cw2.region.base = DMUB_CW0_BASE + inst_fb->size;
	302	cw2.region.top = cw2.region.base + data_fb->size;
	303
	304	cw3.offset.quad_part = bios_fb->gpu_addr;
b9e9f11c	305	cw3.region.base = DMUB_CW3_BASE;
7c008829 NK	306	cw3.region.top = cw3.region.base + bios_fb->size;
	307
	308	cw4.offset.quad_part = mail_fb->gpu_addr;
	309	cw4.region.base = cw3.region.top + 1;
	310	cw4.region.top = cw4.region.base + mail_fb->size;
	311
	312	inbox1.base = cw4.region.base;
	313	inbox1.top = cw4.region.top;
	314
	315	cw5.offset.quad_part = tracebuff_fb->gpu_addr;
	316	cw5.region.base = DMUB_CW5_BASE;
	317	cw5.region.top = cw5.region.base + tracebuff_fb->size;
	318
2f39835c NK	319	cw6.offset.quad_part = fw_state_fb->gpu_addr;
	320	cw6.region.base = DMUB_CW6_BASE;
	321	cw6.region.top = cw6.region.base + fw_state_fb->size;
	322
	323	dmub->fw_state = fw_state_fb->cpu_addr;
	324
7c008829	325	if (dmub->hw_funcs.setup_windows)
2f39835c NK	326	dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4,
2f39835c NK	327	&cw5, &cw6);
7c008829 NK	328
	329	if (dmub->hw_funcs.setup_mailbox)
	330	dmub->hw_funcs.setup_mailbox(dmub, &inbox1);
	331	}
	332
	333	if (mail_fb) {
	334	dmub_memset(&rb_params, 0, sizeof(rb_params));
	335	rb_params.ctx = dmub;
	336	rb_params.base_address = mail_fb->cpu_addr;
	337	rb_params.capacity = DMUB_RB_SIZE;
	338
	339	dmub_rb_init(&dmub->inbox1_rb, &rb_params);
	340	}
	341
	342	if (dmub->hw_funcs.reset_release)
	343	dmub->hw_funcs.reset_release(dmub);
	344
	345	dmub->hw_init = true;
	346
	347	return DMUB_STATUS_OK;
	348	}
	349
	350	enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub,
	351	const struct dmub_cmd_header *cmd)
	352	{
	353	if (!dmub->hw_init)
	354	return DMUB_STATUS_INVALID;
	355
	356	if (dmub_rb_push_front(&dmub->inbox1_rb, cmd))
	357	return DMUB_STATUS_OK;
	358
	359	return DMUB_STATUS_QUEUE_FULL;
	360	}
	361
	362	enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub)
	363	{
	364	if (!dmub->hw_init)
	365	return DMUB_STATUS_INVALID;
	366
	367	dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt);
	368	return DMUB_STATUS_OK;
	369	}
	370
	371	enum dmub_status dmub_srv_cmd_submit(struct dmub_srv *dmub,
	372	const struct dmub_cmd_header *cmd,
	373	uint32_t timeout_us)
	374	{
	375	uint32_t i = 0;
	376
	377	if (!dmub->hw_init)
	378	return DMUB_STATUS_INVALID;
	379
	380	for (i = 0; i <= timeout_us; ++i) {
	381	dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
	382	if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) {
	383	dmub->hw_funcs.set_inbox1_wptr(dmub,
	384	dmub->inbox1_rb.wrpt);
	385	return DMUB_STATUS_OK;
	386	}
	387
	388	udelay(1);
	389	}
	390
	391	return DMUB_STATUS_TIMEOUT;
392	}
393
394	enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,
395	uint32_t timeout_us)
396	{
397	uint32_t i;
398
a4942118	399	if (!dmub->hw_init)
7c008829 NK	400	return DMUB_STATUS_INVALID;
7c008829 NK	401
a4942118 NK	402	if (!dmub->hw_funcs.is_auto_load_done)
	403	return DMUB_STATUS_OK;
	404
7c008829 NK	405	for (i = 0; i <= timeout_us; i += 100) {
	406	if (dmub->hw_funcs.is_auto_load_done(dmub))
	407	return DMUB_STATUS_OK;
	408
	409	udelay(100);
	410	}
	411
	412	return DMUB_STATUS_TIMEOUT;
	413	}
	414
	415	enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,
	416	uint32_t timeout_us)
	417	{
b9e9f11c	418	uint32_t i = 0;
7c008829	419
a4942118	420	if (!dmub->hw_init)
7c008829 NK	421	return DMUB_STATUS_INVALID;
7c008829 NK	422
a4942118 NK	423	if (!dmub->hw_funcs.is_phy_init)
	424	return DMUB_STATUS_OK;
	425
56fc13fe	426	for (i = 0; i <= timeout_us; i += 10) {
7c008829 NK	427	if (dmub->hw_funcs.is_phy_init(dmub))
	428	return DMUB_STATUS_OK;
	429
	430	udelay(10);
	431	}
	432
56fc13fe	433	return DMUB_STATUS_TIMEOUT;
7c008829 NK	434	}
	435
	436	enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,
	437	uint32_t timeout_us)
	438	{
	439	uint32_t i;
	440
	441	if (!dmub->hw_init)
	442	return DMUB_STATUS_INVALID;
	443
	444	for (i = 0; i <= timeout_us; ++i) {
	445	dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
	446	if (dmub_rb_empty(&dmub->inbox1_rb))
	447	return DMUB_STATUS_OK;
	448
	449	udelay(1);
	450	}
	451
	452	return DMUB_STATUS_TIMEOUT;
	453	}