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drm/amd/display: Add DCN35 DMUB
[linux-block.git] / drivers / gpu / drm / amd / display / dmub / src / dmub_srv.c
CommitLineData
7c008829
NK		 1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
cdca3f21 26#include "../dmub_srv.h"
7c008829
NK		 27#include "dmub_dcn20.h"
28#include "dmub_dcn21.h"
84034ad4 29#include "dmub_cmd.h"
5baebf61 30#include "dmub_dcn30.h"
3a83e4e6 31#include "dmub_dcn301.h"
36d26912 32#include "dmub_dcn302.h"
cd6d421e 33#include "dmub_dcn303.h"
b04cb192 34#include "dmub_dcn31.h"
26818260 35#include "dmub_dcn314.h"
5559c7ba 36#include "dmub_dcn315.h"
868f4357 37#include "dmub_dcn316.h"
ac2e555e 38#include "dmub_dcn32.h"
65138eb7 39#include "dmub_dcn35.h"
b9e9f11c 40#include "os_types.h"
7c008829
NK		 41/*
42 * Note: the DMUB service is standalone. No additional headers should be
43 * added below or above this line unless they reside within the DMUB
44 * folder.
45 */
46
47/* Alignment for framebuffer memory. */
48#define DMUB_FB_ALIGNMENT (1024 * 1024)
49
50/* Stack size. */
51#define DMUB_STACK_SIZE (128 * 1024)
52
53/* Context size. */
54#define DMUB_CONTEXT_SIZE (512 * 1024)
55
4f8e37db
MS		 56/* Mailbox size : Ring buffers are required for both inbox and outbox */
57#define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE))
7c008829 58
1f0674fd 59/* Default state size if meta is absent. */
891f016d 60#define DMUB_FW_STATE_SIZE (64 * 1024)
1f0674fd
NK		 61
62/* Default tracebuffer size if meta is absent. */
891f016d 63#define DMUB_TRACE_BUFFER_SIZE (64 * 1024)
7c008829 64
70732504 65
2277f01d
WW		 66/* Default scratch mem size. */
67#define DMUB_SCRATCH_MEM_SIZE (256)
68
7c008829 69/* Number of windows in use. */
2277f01d 70#define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL)
7c008829
NK		 71/* Base addresses. */
72
73#define DMUB_CW0_BASE (0x60000000)
74#define DMUB_CW1_BASE (0x61000000)
b9e9f11c 75#define DMUB_CW3_BASE (0x63000000)
562c805f 76#define DMUB_CW4_BASE (0x64000000)
7c008829 77#define DMUB_CW5_BASE (0x65000000)
2f39835c 78#define DMUB_CW6_BASE (0x66000000)
7c008829 79
70732504
YS		 80#define DMUB_REGION5_BASE (0xA0000000)
81
96182df9 82static struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs;
65138eb7 83static struct dmub_srv_dcn35_regs dmub_srv_dcn35_regs;
96182df9 84
7c008829
NK		 85static inline uint32_t dmub_align(uint32_t val, uint32_t factor)
86{
87 return (val + factor - 1) / factor * factor;
88}
89
c5d5b0ec 90void dmub_flush_buffer_mem(const struct dmub_fb *fb)
dee5d542
NK		 91{
92 const uint8_t *base = (const uint8_t *)fb->cpu_addr;
93 uint8_t buf[64];
94 uint32_t pos, end;
95
96 /**
97 * Read 64-byte chunks since we don't want to store a
98 * large temporary buffer for this purpose.
99 */
100 end = fb->size / sizeof(buf) * sizeof(buf);
101
102 for (pos = 0; pos < end; pos += sizeof(buf))
103 dmub_memcpy(buf, base + pos, sizeof(buf));
104
105 /* Read anything leftover into the buffer. */
106 if (end < fb->size)
107 dmub_memcpy(buf, base + pos, fb->size - end);
108}
109
1f0674fd 110static const struct dmub_fw_meta_info *
1328e395 111dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset)
1f0674fd
NK		 112{
113 const union dmub_fw_meta *meta;
114
a576b345 115 if (!blob || !blob_size)
1f0674fd
NK		 116 return NULL;
117
d5617541 118 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset)
1f0674fd
NK		 119 return NULL;
120
d5617541 121 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset -
1f0674fd
NK		 122 sizeof(union dmub_fw_meta));
123
124 if (meta->info.magic_value != DMUB_FW_META_MAGIC)
125 return NULL;
126
127 return &meta->info;
128}
129
1328e395
NK		 130static const struct dmub_fw_meta_info *
131dmub_get_fw_meta_info(const struct dmub_srv_region_params *params)
132{
133 const struct dmub_fw_meta_info *info = NULL;
134
135 if (params->fw_bss_data && params->bss_data_size) {
136 /* Legacy metadata region. */
137 info = dmub_get_fw_meta_info_from_blob(params->fw_bss_data,
138 params->bss_data_size,
139 DMUB_FW_META_OFFSET);
140 } else if (params->fw_inst_const && params->inst_const_size) {
141 /* Combined metadata region - can be aligned to 16-bytes. */
142 uint32_t i;
143
144 for (i = 0; i < 16; ++i) {
145 info = dmub_get_fw_meta_info_from_blob(
146 params->fw_inst_const, params->inst_const_size, i);
147
148 if (info)
149 break;
150 }
151 }
152
153 return info;
154}
155
7c008829
NK		 156static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
157{
158 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs;
159
160 switch (asic) {
161 case DMUB_ASIC_DCN20:
162 case DMUB_ASIC_DCN21:
5baebf61 163 case DMUB_ASIC_DCN30:
3a83e4e6 164 case DMUB_ASIC_DCN301:
36d26912 165 case DMUB_ASIC_DCN302:
cd6d421e 166 case DMUB_ASIC_DCN303:
01c229d9
NK		 167 dmub->regs = &dmub_srv_dcn20_regs;
168
7c008829
NK		 169 funcs->reset = dmub_dcn20_reset;
170 funcs->reset_release = dmub_dcn20_reset_release;
171 funcs->backdoor_load = dmub_dcn20_backdoor_load;
172 funcs->setup_windows = dmub_dcn20_setup_windows;
173 funcs->setup_mailbox = dmub_dcn20_setup_mailbox;
8f3589bb 174 funcs->get_inbox1_wptr = dmub_dcn20_get_inbox1_wptr;
7c008829
NK		 175 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr;
176 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr;
177 funcs->is_supported = dmub_dcn20_is_supported;
c09eeee4 178 funcs->is_hw_init = dmub_dcn20_is_hw_init;
fbbd3f8f
NK		 179 funcs->set_gpint = dmub_dcn20_set_gpint;
180 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked;
181 funcs->get_gpint_response = dmub_dcn20_get_gpint_response;
5fe6b98a
BL		 182 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status;
183 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options;
184 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence;
980d6042 185 funcs->get_current_time = dmub_dcn20_get_current_time;
7c008829 186
4f8e37db
MS		 187 // Out mailbox register access functions for RN and above
188 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox;
189 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr;
190 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr;
191
70732504
YS		 192 //outbox0 call stacks
193 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0;
194 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr;
195 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr;
196
2631ac1a
AT		 197 funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data;
198
499e4b1c 199 if (asic == DMUB_ASIC_DCN21)
01c229d9
NK		 200 dmub->regs = &dmub_srv_dcn21_regs;
201
5baebf61
BL		 202 if (asic == DMUB_ASIC_DCN30) {
203 dmub->regs = &dmub_srv_dcn30_regs;
204
5baebf61
BL		 205 funcs->backdoor_load = dmub_dcn30_backdoor_load;
206 funcs->setup_windows = dmub_dcn30_setup_windows;
207 }
3a83e4e6
RL		 208 if (asic == DMUB_ASIC_DCN301) {
209 dmub->regs = &dmub_srv_dcn301_regs;
210
211 funcs->backdoor_load = dmub_dcn30_backdoor_load;
212 funcs->setup_windows = dmub_dcn30_setup_windows;
213 }
36d26912
BL		 214 if (asic == DMUB_ASIC_DCN302) {
215 dmub->regs = &dmub_srv_dcn302_regs;
216
217 funcs->backdoor_load = dmub_dcn30_backdoor_load;
218 funcs->setup_windows = dmub_dcn30_setup_windows;
219 }
cd6d421e
AP		 220 if (asic == DMUB_ASIC_DCN303) {
221 dmub->regs = &dmub_srv_dcn303_regs;
222
223 funcs->backdoor_load = dmub_dcn30_backdoor_load;
224 funcs->setup_windows = dmub_dcn30_setup_windows;
225 }
7c008829 226 break;
b04cb192
NK		 227
228 case DMUB_ASIC_DCN31:
3137f792 229 case DMUB_ASIC_DCN31B:
cc35e752 230 case DMUB_ASIC_DCN314:
5559c7ba 231 case DMUB_ASIC_DCN315:
868f4357 232 case DMUB_ASIC_DCN316:
c35b6ea8 233 if (asic == DMUB_ASIC_DCN314) {
26818260 234 dmub->regs_dcn31 = &dmub_srv_dcn314_regs;
cd2e31a9 235 funcs->is_psrsu_supported = dmub_dcn314_is_psrsu_supported;
c35b6ea8 236 } else if (asic == DMUB_ASIC_DCN315) {
5559c7ba 237 dmub->regs_dcn31 = &dmub_srv_dcn315_regs;
c35b6ea8 238 } else if (asic == DMUB_ASIC_DCN316) {
868f4357 239 dmub->regs_dcn31 = &dmub_srv_dcn316_regs;
c35b6ea8 240 } else {
5559c7ba 241 dmub->regs_dcn31 = &dmub_srv_dcn31_regs;
c35b6ea8
ML		 242 funcs->is_psrsu_supported = dmub_dcn31_is_psrsu_supported;
243 }
b04cb192
NK		 244 funcs->reset = dmub_dcn31_reset;
245 funcs->reset_release = dmub_dcn31_reset_release;
246 funcs->backdoor_load = dmub_dcn31_backdoor_load;
247 funcs->setup_windows = dmub_dcn31_setup_windows;
248 funcs->setup_mailbox = dmub_dcn31_setup_mailbox;
8f3589bb 249 funcs->get_inbox1_wptr = dmub_dcn31_get_inbox1_wptr;
b04cb192
NK		 250 funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr;
251 funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr;
252 funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox;
253 funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr;
254 funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr;
255 funcs->is_supported = dmub_dcn31_is_supported;
256 funcs->is_hw_init = dmub_dcn31_is_hw_init;
257 funcs->set_gpint = dmub_dcn31_set_gpint;
258 funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked;
259 funcs->get_gpint_response = dmub_dcn31_get_gpint_response;
556a979d 260 funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout;
b04cb192 261 funcs->get_fw_status = dmub_dcn31_get_fw_boot_status;
6c3162d0 262 funcs->get_fw_boot_option = dmub_dcn31_get_fw_boot_option;
b04cb192
NK		 263 funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options;
264 funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence;
265 //outbox0 call stacks
266 funcs->setup_outbox0 = dmub_dcn31_setup_outbox0;
267 funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr;
268 funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr;
269
1d40ef90 270 funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data;
ac02dc34 271 funcs->should_detect = dmub_dcn31_should_detect;
b04cb192
NK		 272 funcs->get_current_time = dmub_dcn31_get_current_time;
273
274 break;
7c008829 275
ac2e555e
AP		 276 case DMUB_ASIC_DCN32:
277 case DMUB_ASIC_DCN321:
278 dmub->regs_dcn32 = &dmub_srv_dcn32_regs;
279 funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory;
280 funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd;
281 funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register;
282 funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register;
0b9dc439 283 funcs->subvp_save_surf_addr = dmub_dcn32_save_surf_addr;
ac2e555e
AP		 284 funcs->reset = dmub_dcn32_reset;
285 funcs->reset_release = dmub_dcn32_reset_release;
286 funcs->backdoor_load = dmub_dcn32_backdoor_load;
287 funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode;
288 funcs->setup_windows = dmub_dcn32_setup_windows;
289 funcs->setup_mailbox = dmub_dcn32_setup_mailbox;
8f3589bb 290 funcs->get_inbox1_wptr = dmub_dcn32_get_inbox1_wptr;
ac2e555e
AP		 291 funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr;
292 funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr;
293 funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox;
294 funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr;
295 funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr;
296 funcs->is_supported = dmub_dcn32_is_supported;
297 funcs->is_hw_init = dmub_dcn32_is_hw_init;
298 funcs->set_gpint = dmub_dcn32_set_gpint;
299 funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked;
300 funcs->get_gpint_response = dmub_dcn32_get_gpint_response;
301 funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout;
302 funcs->get_fw_status = dmub_dcn32_get_fw_boot_status;
303 funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options;
304 funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence;
305
306 /* outbox0 call stacks */
307 funcs->setup_outbox0 = dmub_dcn32_setup_outbox0;
308 funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr;
309 funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr;
310 funcs->get_current_time = dmub_dcn32_get_current_time;
311 funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data;
96182df9 312 funcs->init_reg_offsets = dmub_srv_dcn32_regs_init;
ac2e555e
AP		 313
314 break;
315
65138eb7
QZ		 316 case DMUB_ASIC_DCN35:
317 dmub->regs_dcn35 = &dmub_srv_dcn35_regs;
318 funcs->configure_dmub_in_system_memory = dmub_dcn35_configure_dmub_in_system_memory;
319 funcs->send_inbox0_cmd = dmub_dcn35_send_inbox0_cmd;
320 funcs->clear_inbox0_ack_register = dmub_dcn35_clear_inbox0_ack_register;
321 funcs->read_inbox0_ack_register = dmub_dcn35_read_inbox0_ack_register;
322 funcs->reset = dmub_dcn35_reset;
323 funcs->reset_release = dmub_dcn35_reset_release;
324 funcs->backdoor_load = dmub_dcn35_backdoor_load;
325 funcs->backdoor_load_zfb_mode = dmub_dcn35_backdoor_load_zfb_mode;
326 funcs->setup_windows = dmub_dcn35_setup_windows;
327 funcs->setup_mailbox = dmub_dcn35_setup_mailbox;
328 funcs->get_inbox1_wptr = dmub_dcn35_get_inbox1_wptr;
329 funcs->get_inbox1_rptr = dmub_dcn35_get_inbox1_rptr;
330 funcs->set_inbox1_wptr = dmub_dcn35_set_inbox1_wptr;
331 funcs->setup_out_mailbox = dmub_dcn35_setup_out_mailbox;
332 funcs->get_outbox1_wptr = dmub_dcn35_get_outbox1_wptr;
333 funcs->set_outbox1_rptr = dmub_dcn35_set_outbox1_rptr;
334 funcs->is_supported = dmub_dcn35_is_supported;
335 funcs->is_hw_init = dmub_dcn35_is_hw_init;
336 funcs->set_gpint = dmub_dcn35_set_gpint;
337 funcs->is_gpint_acked = dmub_dcn35_is_gpint_acked;
338 funcs->get_gpint_response = dmub_dcn35_get_gpint_response;
339 funcs->get_gpint_dataout = dmub_dcn35_get_gpint_dataout;
340 funcs->get_fw_status = dmub_dcn35_get_fw_boot_status;
341 funcs->get_fw_boot_option = dmub_dcn35_get_fw_boot_option;
342 funcs->enable_dmub_boot_options = dmub_dcn35_enable_dmub_boot_options;
343 funcs->skip_dmub_panel_power_sequence = dmub_dcn35_skip_dmub_panel_power_sequence;
344 //outbox0 call stacks
345 funcs->setup_outbox0 = dmub_dcn35_setup_outbox0;
346 funcs->get_outbox0_wptr = dmub_dcn35_get_outbox0_wptr;
347 funcs->set_outbox0_rptr = dmub_dcn35_set_outbox0_rptr;
348
349 funcs->get_current_time = dmub_dcn35_get_current_time;
350 funcs->get_diagnostic_data = dmub_dcn35_get_diagnostic_data;
351
352 funcs->init_reg_offsets = dmub_srv_dcn35_regs_init;
353
354 funcs->is_hw_powered_up = dmub_dcn35_is_hw_powered_up;
355 break;
356
7c008829
NK		 357 default:
358 return false;
359 }
360
361 return true;
362}
363
364enum dmub_status dmub_srv_create(struct dmub_srv *dmub,
365 const struct dmub_srv_create_params *params)
366{
367 enum dmub_status status = DMUB_STATUS_OK;
368
369 dmub_memset(dmub, 0, sizeof(*dmub));
370
371 dmub->funcs = params->funcs;
372 dmub->user_ctx = params->user_ctx;
373 dmub->asic = params->asic;
455802c7 374 dmub->fw_version = params->fw_version;
7c008829
NK		 375 dmub->is_virtual = params->is_virtual;
376
377 /* Setup asic dependent hardware funcs. */
378 if (!dmub_srv_hw_setup(dmub, params->asic)) {
379 status = DMUB_STATUS_INVALID;
380 goto cleanup;
381 }
382
383 /* Override (some) hardware funcs based on user params. */
384 if (params->hw_funcs) {
37ffa7a1
YS		 385 if (params->hw_funcs->emul_get_inbox1_rptr)
386 dmub->hw_funcs.emul_get_inbox1_rptr =
387 params->hw_funcs->emul_get_inbox1_rptr;
7c008829 388
37ffa7a1
YS		 389 if (params->hw_funcs->emul_set_inbox1_wptr)
390 dmub->hw_funcs.emul_set_inbox1_wptr =
391 params->hw_funcs->emul_set_inbox1_wptr;
7c008829
NK		 392
393 if (params->hw_funcs->is_supported)
394 dmub->hw_funcs.is_supported =
395 params->hw_funcs->is_supported;
396 }
397
398 /* Sanity checks for required hw func pointers. */
399 if (!dmub->hw_funcs.get_inbox1_rptr ||
400 !dmub->hw_funcs.set_inbox1_wptr) {
401 status = DMUB_STATUS_INVALID;
402 goto cleanup;
403 }
404
405cleanup:
406 if (status == DMUB_STATUS_OK)
407 dmub->sw_init = true;
408 else
409 dmub_srv_destroy(dmub);
410
411 return status;
412}
413
414void dmub_srv_destroy(struct dmub_srv *dmub)
415{
416 dmub_memset(dmub, 0, sizeof(*dmub));
417}
418
419enum dmub_status
420dmub_srv_calc_region_info(struct dmub_srv *dmub,
421 const struct dmub_srv_region_params *params,
422 struct dmub_srv_region_info *out)
423{
424 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST];
425 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK];
426 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA];
427 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS];
428 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX];
429 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF];
2f39835c 430 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE];
2277f01d 431 struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM];
1f0674fd
NK		 432 const struct dmub_fw_meta_info *fw_info;
433 uint32_t fw_state_size = DMUB_FW_STATE_SIZE;
434 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE;
2277f01d 435 uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE;
7c008829
NK		 436
437 if (!dmub->sw_init)
438 return DMUB_STATUS_INVALID;
439
440 memset(out, 0, sizeof(*out));
441
442 out->num_regions = DMUB_NUM_WINDOWS;
443
444 inst->base = 0x0;
445 inst->top = inst->base + params->inst_const_size;
446
447 data->base = dmub_align(inst->top, 256);
448 data->top = data->base + params->bss_data_size;
449
1f0674fd
NK		 450 /*
451 * All cache windows below should be aligned to the size
452 * of the DMCUB cache line, 64 bytes.
453 */
454
7c008829
NK		 455 stack->base = dmub_align(data->top, 256);
456 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE;
457
458 bios->base = dmub_align(stack->top, 256);
459 bios->top = bios->base + params->vbios_size;
460
461 mail->base = dmub_align(bios->top, 256);
462 mail->top = mail->base + DMUB_MAILBOX_SIZE;
463
a576b345 464 fw_info = dmub_get_fw_meta_info(params);
1f0674fd
NK		 465
466 if (fw_info) {
467 fw_state_size = fw_info->fw_region_size;
468 trace_buffer_size = fw_info->trace_buffer_size;
dc43d958
NK		 469
470 /**
471 * If DM didn't fill in a version, then fill it in based on
472 * the firmware meta now that we have it.
473 *
474 * TODO: Make it easier for driver to extract this out to
475 * pass during creation.
476 */
477 if (dmub->fw_version == 0)
478 dmub->fw_version = fw_info->fw_version;
1f0674fd
NK		 479 }
480
7c008829 481 trace_buff->base = dmub_align(mail->top, 256);
1f0674fd 482 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64);
7c008829 483
2f39835c 484 fw_state->base = dmub_align(trace_buff->top, 256);
1f0674fd 485 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64);
2f39835c 486
2277f01d
WW		 487 scratch_mem->base = dmub_align(fw_state->top, 256);
488 scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64);
489
490 out->fb_size = dmub_align(scratch_mem->top, 4096);
7c008829
NK		 491
492 return DMUB_STATUS_OK;
493}
494
495enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub,
496 const struct dmub_srv_fb_params *params,
497 struct dmub_srv_fb_info *out)
498{
499 uint8_t *cpu_base;
500 uint64_t gpu_base;
501 uint32_t i;
502
503 if (!dmub->sw_init)
504 return DMUB_STATUS_INVALID;
505
506 memset(out, 0, sizeof(*out));
507
508 if (params->region_info->num_regions != DMUB_NUM_WINDOWS)
509 return DMUB_STATUS_INVALID;
510
511 cpu_base = (uint8_t *)params->cpu_addr;
512 gpu_base = params->gpu_addr;
513
514 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) {
515 const struct dmub_region *reg =
516 &params->region_info->regions[i];
517
518 out->fb[i].cpu_addr = cpu_base + reg->base;
519 out->fb[i].gpu_addr = gpu_base + reg->base;
520 out->fb[i].size = reg->top - reg->base;
521 }
522
523 out->num_fb = DMUB_NUM_WINDOWS;
524
525 return DMUB_STATUS_OK;
526}
527
528enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,
529 bool *is_supported)
530{
531 *is_supported = false;
532
533 if (!dmub->sw_init)
534 return DMUB_STATUS_INVALID;
535
536 if (dmub->hw_funcs.is_supported)
537 *is_supported = dmub->hw_funcs.is_supported(dmub);
538
539 return DMUB_STATUS_OK;
540}
541
c09eeee4
NK		 542enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init)
543{
544 *is_hw_init = false;
545
546 if (!dmub->sw_init)
547 return DMUB_STATUS_INVALID;
548
e5f0b521
NK		 549 if (!dmub->hw_init)
550 return DMUB_STATUS_OK;
551
c09eeee4
NK		 552 if (dmub->hw_funcs.is_hw_init)
553 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub);
554
555 return DMUB_STATUS_OK;
556}
557
7c008829
NK		 558enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
559 const struct dmub_srv_hw_params *params)
560{
561 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST];
562 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK];
563 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA];
564 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS];
565 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX];
566 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF];
2f39835c 567 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE];
2277f01d 568 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM];
7c008829 569
70732504 570 struct dmub_rb_init_params rb_params, outbox0_rb_params;
2f39835c 571 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6;
70732504 572 struct dmub_region inbox1, outbox1, outbox0;
7c008829
NK		 573
574 if (!dmub->sw_init)
575 return DMUB_STATUS_INVALID;
576
6c8e1f3b
LHM		 577 if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb ||
578 !tracebuff_fb || !fw_state_fb || !scratch_mem_fb) {
579 ASSERT(0);
580 return DMUB_STATUS_INVALID;
581 }
582
7c008829
NK		 583 dmub->fb_base = params->fb_base;
584 dmub->fb_offset = params->fb_offset;
585 dmub->psp_version = params->psp_version;
586
d740a39c
NK		 587 if (dmub->hw_funcs.reset)
588 dmub->hw_funcs.reset(dmub);
589
154711aa
NK		 590 /* reset the cache of the last wptr as well now that hw is reset */
591 dmub->inbox1_last_wptr = 0;
592
6c8e1f3b
LHM		 593 cw0.offset.quad_part = inst_fb->gpu_addr;
594 cw0.region.base = DMUB_CW0_BASE;
595 cw0.region.top = cw0.region.base + inst_fb->size - 1;
7c008829 596
6c8e1f3b
LHM		 597 cw1.offset.quad_part = stack_fb->gpu_addr;
598 cw1.region.base = DMUB_CW1_BASE;
599 cw1.region.top = cw1.region.base + stack_fb->size - 1;
7c008829 600
ac2e555e
AP		 601 if (params->fw_in_system_memory && dmub->hw_funcs.configure_dmub_in_system_memory)
602 dmub->hw_funcs.configure_dmub_in_system_memory(dmub);
603
6c8e1f3b 604 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) {
4f8e37db 605 /**
6c8e1f3b
LHM		 606 * Read back all the instruction memory so we don't hang the
607 * DMCUB when backdoor loading if the write from x86 hasn't been
608 * flushed yet. This only occurs in backdoor loading.
4f8e37db 609 */
5e77c339
DV		 610 if (params->mem_access_type == DMUB_MEMORY_ACCESS_CPU)
611 dmub_flush_buffer_mem(inst_fb);
ac2e555e
AP		 612
613 if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode)
614 dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1);
615 else
616 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
6c8e1f3b 617 }
7c008829 618
6c8e1f3b
LHM		 619 cw2.offset.quad_part = data_fb->gpu_addr;
620 cw2.region.base = DMUB_CW0_BASE + inst_fb->size;
621 cw2.region.top = cw2.region.base + data_fb->size;
7c008829 622
6c8e1f3b
LHM		 623 cw3.offset.quad_part = bios_fb->gpu_addr;
624 cw3.region.base = DMUB_CW3_BASE;
625 cw3.region.top = cw3.region.base + bios_fb->size;
70732504 626
6c8e1f3b
LHM		 627 cw4.offset.quad_part = mail_fb->gpu_addr;
628 cw4.region.base = DMUB_CW4_BASE;
629 cw4.region.top = cw4.region.base + mail_fb->size;
70732504 630
6c8e1f3b
LHM		 631 /**
632 * Doubled the mailbox region to accomodate inbox and outbox.
633 * Note: Currently, currently total mailbox size is 16KB. It is split
634 * equally into 8KB between inbox and outbox. If this config is
635 * changed, then uncached base address configuration of outbox1
636 * has to be updated in funcs->setup_out_mailbox.
637 */
638 inbox1.base = cw4.region.base;
639 inbox1.top = cw4.region.base + DMUB_RB_SIZE;
640 outbox1.base = inbox1.top;
641 outbox1.top = cw4.region.top;
2f39835c 642
6c8e1f3b
LHM		 643 cw5.offset.quad_part = tracebuff_fb->gpu_addr;
644 cw5.region.base = DMUB_CW5_BASE;
645 cw5.region.top = cw5.region.base + tracebuff_fb->size;
2f39835c 646
6c8e1f3b
LHM		 647 outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET;
648 outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET;
2277f01d 649
6c8e1f3b
LHM		 650 cw6.offset.quad_part = fw_state_fb->gpu_addr;
651 cw6.region.base = DMUB_CW6_BASE;
652 cw6.region.top = cw6.region.base + fw_state_fb->size;
7c008829 653
6c8e1f3b 654 dmub->fw_state = fw_state_fb->cpu_addr;
70732504 655
6c8e1f3b 656 dmub->scratch_mem_fb = *scratch_mem_fb;
7c008829 657
6c8e1f3b
LHM		 658 if (dmub->hw_funcs.setup_windows)
659 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6);
7c008829 660
6c8e1f3b
LHM		 661 if (dmub->hw_funcs.setup_outbox0)
662 dmub->hw_funcs.setup_outbox0(dmub, &outbox0);
4f8e37db 663
6c8e1f3b
LHM		 664 if (dmub->hw_funcs.setup_mailbox)
665 dmub->hw_funcs.setup_mailbox(dmub, &inbox1);
666 if (dmub->hw_funcs.setup_out_mailbox)
667 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1);
4f8e37db 668
6c8e1f3b
LHM		 669 dmub_memset(&rb_params, 0, sizeof(rb_params));
670 rb_params.ctx = dmub;
671 rb_params.base_address = mail_fb->cpu_addr;
672 rb_params.capacity = DMUB_RB_SIZE;
673 dmub_rb_init(&dmub->inbox1_rb, &rb_params);
674
675 // Initialize outbox1 ring buffer
676 rb_params.ctx = dmub;
677 rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE);
678 rb_params.capacity = DMUB_RB_SIZE;
679 dmub_rb_init(&dmub->outbox1_rb, &rb_params);
7c008829 680
70732504
YS		 681 dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params));
682 outbox0_rb_params.ctx = dmub;
2dd88ce8 683 outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET);
3c934f45 684 outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64);
70732504
YS		 685 dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params);
686
4462bca7
EY		 687 /* Report to DMUB what features are supported by current driver */
688 if (dmub->hw_funcs.enable_dmub_boot_options)
689 dmub->hw_funcs.enable_dmub_boot_options(dmub, params);
690
e198a746 691 if (dmub->hw_funcs.skip_dmub_panel_power_sequence && !dmub->is_virtual)
ac2e555e
AP		 692 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub,
693 params->skip_panel_power_sequence);
694
e198a746 695 if (dmub->hw_funcs.reset_release && !dmub->is_virtual)
7c008829
NK		 696 dmub->hw_funcs.reset_release(dmub);
697
698 dmub->hw_init = true;
699
700 return DMUB_STATUS_OK;
701}
702
8f3589bb
JX		 703enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub)
704{
705 if (!dmub->sw_init)
706 return DMUB_STATUS_INVALID;
707
708 if (dmub->hw_funcs.get_inbox1_rptr && dmub->hw_funcs.get_inbox1_wptr) {
709 dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
710 dmub->inbox1_rb.wrpt = dmub->hw_funcs.get_inbox1_wptr(dmub);
711 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt;
712 }
713
714 return DMUB_STATUS_OK;
715}
716
0167da49
NK		 717enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub)
718{
719 if (!dmub->sw_init)
720 return DMUB_STATUS_INVALID;
721
0167da49
NK		 722 if (dmub->hw_funcs.reset)
723 dmub->hw_funcs.reset(dmub);
724
154711aa
NK		 725 /* mailboxes have been reset in hw, so reset the sw state as well */
726 dmub->inbox1_last_wptr = 0;
727 dmub->inbox1_rb.wrpt = 0;
728 dmub->inbox1_rb.rptr = 0;
729 dmub->outbox0_rb.wrpt = 0;
730 dmub->outbox0_rb.rptr = 0;
731 dmub->outbox1_rb.wrpt = 0;
732 dmub->outbox1_rb.rptr = 0;
733
0167da49
NK		 734 dmub->hw_init = false;
735
736 return DMUB_STATUS_OK;
737}
738
7c008829 739enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub,
0ed3bcc4 740 const union dmub_rb_cmd *cmd)
7c008829
NK		 741{
742 if (!dmub->hw_init)
743 return DMUB_STATUS_INVALID;
744
745 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd))
746 return DMUB_STATUS_OK;
747
748 return DMUB_STATUS_QUEUE_FULL;
749}
750
751enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub)
752{
a53b554b
NK		 753 struct dmub_rb flush_rb;
754
7c008829
NK		 755 if (!dmub->hw_init)
756 return DMUB_STATUS_INVALID;
757
b7408a06
NK		 758 /**
759 * Read back all the queued commands to ensure that they've
760 * been flushed to framebuffer memory. Otherwise DMCUB might
761 * read back stale, fully invalid or partially invalid data.
762 */
a53b554b
NK		 763 flush_rb = dmub->inbox1_rb;
764 flush_rb.rptr = dmub->inbox1_last_wptr;
765 dmub_rb_flush_pending(&flush_rb);
b7408a06 766
1da2fcc4 767 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt);
a53b554b
NK		 768
769 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt;
770
7c008829
NK		 771 return DMUB_STATUS_OK;
772}
773
65138eb7
QZ		 774bool dmub_srv_is_hw_pwr_up(struct dmub_srv *dmub)
775{
776 if (!dmub->hw_funcs.is_hw_powered_up)
777 return true;
778
779 return dmub->hw_funcs.is_hw_powered_up(dmub) &&
780 dmub->hw_funcs.is_hw_init(dmub);
781}
782
783enum dmub_status dmub_srv_wait_for_hw_pwr_up(struct dmub_srv *dmub,
784 uint32_t timeout_us)
785{
786 uint32_t i;
787
788 if (!dmub->hw_init)
789 return DMUB_STATUS_INVALID;
790
791 for (i = 0; i <= timeout_us; i += 100) {
792 if (dmub_srv_is_hw_pwr_up(dmub))
793 return DMUB_STATUS_OK;
794
795 udelay(100);
796 }
797
798 return DMUB_STATUS_TIMEOUT;
799}
800
7c008829
NK		 801enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,
802 uint32_t timeout_us)
803{
804 uint32_t i;
65138eb7 805 bool hw_on = true;
7c008829 806
a4942118 807 if (!dmub->hw_init)
7c008829
NK		 808 return DMUB_STATUS_INVALID;
809
64c51ea5 810 for (i = 0; i <= timeout_us; i += 100) {
5fe6b98a
BL		 811 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub);
812
65138eb7
QZ		 813 if (dmub->hw_funcs.is_hw_powered_up)
814 hw_on = dmub->hw_funcs.is_hw_powered_up(dmub);
815
816 if (status.bits.dal_fw && status.bits.mailbox_rdy && hw_on)
7c008829
NK		 817 return DMUB_STATUS_OK;
818
8f95ff28 819 udelay(100);
7c008829
NK		 820 }
821
56fc13fe 822 return DMUB_STATUS_TIMEOUT;
7c008829
NK		 823}
824
825enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,
826 uint32_t timeout_us)
827{
64df665f 828 uint32_t i, rptr;
7c008829
NK		 829
830 if (!dmub->hw_init)
831 return DMUB_STATUS_INVALID;
832
833 for (i = 0; i <= timeout_us; ++i) {
64df665f
WW		 834 rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
835
836 if (rptr > dmub->inbox1_rb.capacity)
837 return DMUB_STATUS_HW_FAILURE;
838
839 dmub->inbox1_rb.rptr = rptr;
840
7c008829
NK		 841 if (dmub_rb_empty(&dmub->inbox1_rb))
842 return DMUB_STATUS_OK;
843
844 udelay(1);
845 }
846
847 return DMUB_STATUS_TIMEOUT;
848}
fbbd3f8f
NK		 849
850enum dmub_status
851dmub_srv_send_gpint_command(struct dmub_srv *dmub,
852 enum dmub_gpint_command command_code,
853 uint16_t param, uint32_t timeout_us)
854{
855 union dmub_gpint_data_register reg;
856 uint32_t i;
857
858 if (!dmub->sw_init)
859 return DMUB_STATUS_INVALID;
860
861 if (!dmub->hw_funcs.set_gpint)
862 return DMUB_STATUS_INVALID;
863
864 if (!dmub->hw_funcs.is_gpint_acked)
865 return DMUB_STATUS_INVALID;
866
867 reg.bits.status = 1;
868 reg.bits.command_code = command_code;
869 reg.bits.param = param;
870
871 dmub->hw_funcs.set_gpint(dmub, reg);
872
873 for (i = 0; i < timeout_us; ++i) {
6bdb2e38
WW		 874 udelay(1);
875
fbbd3f8f
NK		 876 if (dmub->hw_funcs.is_gpint_acked(dmub, reg))
877 return DMUB_STATUS_OK;
878 }
879
880 return DMUB_STATUS_TIMEOUT;
881}
882
883enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub,
884 uint32_t *response)
885{
886 *response = 0;
887
888 if (!dmub->sw_init)
889 return DMUB_STATUS_INVALID;
890
891 if (!dmub->hw_funcs.get_gpint_response)
892 return DMUB_STATUS_INVALID;
893
894 *response = dmub->hw_funcs.get_gpint_response(dmub);
895
896 return DMUB_STATUS_OK;
897}
5fe6b98a 898
556a979d
CLC		 899enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub,
900 uint32_t *dataout)
901{
902 *dataout = 0;
903
904 if (!dmub->sw_init)
905 return DMUB_STATUS_INVALID;
906
907 if (!dmub->hw_funcs.get_gpint_dataout)
908 return DMUB_STATUS_INVALID;
909
910 *dataout = dmub->hw_funcs.get_gpint_dataout(dmub);
911
912 return DMUB_STATUS_OK;
913}
914
5fe6b98a
BL		 915enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub,
916 union dmub_fw_boot_status *status)
917{
918 status->all = 0;
919
920 if (!dmub->sw_init)
921 return DMUB_STATUS_INVALID;
922
923 if (dmub->hw_funcs.get_fw_status)
924 *status = dmub->hw_funcs.get_fw_status(dmub);
925
926 return DMUB_STATUS_OK;
927}
92f1fa0d 928
6c3162d0
CH		 929enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub,
930 union dmub_fw_boot_options *option)
931{
932 option->all = 0;
933
934 if (!dmub->sw_init)
935 return DMUB_STATUS_INVALID;
936
937 if (dmub->hw_funcs.get_fw_boot_option)
938 *option = dmub->hw_funcs.get_fw_boot_option(dmub);
939
940 return DMUB_STATUS_OK;
941}
942
b9f501c5
PH		 943enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub,
944 bool skip)
945{
946 if (!dmub->sw_init)
947 return DMUB_STATUS_INVALID;
948
949 if (dmub->hw_funcs.skip_dmub_panel_power_sequence && !dmub->is_virtual)
950 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, skip);
951
952 return DMUB_STATUS_OK;
953}
954
92f1fa0d
WW		 955enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub,
956 union dmub_rb_cmd *cmd)
957{
958 enum dmub_status status = DMUB_STATUS_OK;
959
960 // Queue command
961 status = dmub_srv_cmd_queue(dmub, cmd);
962
963 if (status != DMUB_STATUS_OK)
964 return status;
965
966 // Execute command
967 status = dmub_srv_cmd_execute(dmub);
968
969 if (status != DMUB_STATUS_OK)
970 return status;
971
972 // Wait for DMUB to process command
973 status = dmub_srv_wait_for_idle(dmub, 100000);
974
975 if (status != DMUB_STATUS_OK)
976 return status;
977
978 // Copy data back from ring buffer into command
979 dmub_rb_get_return_data(&dmub->inbox1_rb, cmd);
980
981 return status;
982}
70732504 983
3c934f45 984static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb,
70732504
YS		 985 void *entry)
986{
3c934f45 987 const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t);
70732504
YS		 988 uint64_t *dst = (uint64_t *)entry;
989 uint8_t i;
6804287b 990 uint8_t loop_count;
70732504 991
6804287b
YS		 992 if (rb->rptr == rb->wrpt)
993 return false;
994
995 loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t);
70732504 996 // copying data
6804287b 997 for (i = 0; i < loop_count; i++)
70732504
YS		 998 *dst++ = *src++;
999
3c934f45
YS		 1000 rb->rptr += sizeof(struct dmcub_trace_buf_entry);
1001
1002 rb->rptr %= rb->capacity;
1003
6804287b 1004 return true;
70732504
YS		 1005}
1006
6804287b 1007bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry)
70732504
YS		 1008{
1009 dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub);
1010
6804287b 1011 return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry);
70732504 1012}
2631ac1a
AT		 1013
1014bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)
1015{
1016 if (!dmub || !dmub->hw_funcs.get_diagnostic_data || !diag_data)
1017 return false;
1018 dmub->hw_funcs.get_diagnostic_data(dmub, diag_data);
1019 return true;
1020}
ac02dc34
EY		 1021
1022bool dmub_srv_should_detect(struct dmub_srv *dmub)
1023{
1024 if (!dmub->hw_init || !dmub->hw_funcs.should_detect)
1025 return false;
1026
1027 return dmub->hw_funcs.should_detect(dmub);
1028}
d493a024
AL		 1029
1030enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub)
1031{
e56e9ad0 1032 if (!dmub->hw_init || !dmub->hw_funcs.clear_inbox0_ack_register)
d493a024
AL		 1033 return DMUB_STATUS_INVALID;
1034
1035 dmub->hw_funcs.clear_inbox0_ack_register(dmub);
1036 return DMUB_STATUS_OK;
1037}
1038
1039enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us)
1040{
1041 uint32_t i = 0;
1042 uint32_t ack = 0;
1043
1044 if (!dmub->hw_init || !dmub->hw_funcs.read_inbox0_ack_register)
1045 return DMUB_STATUS_INVALID;
1046
1047 for (i = 0; i <= timeout_us; i++) {
1048 ack = dmub->hw_funcs.read_inbox0_ack_register(dmub);
1049 if (ack)
1050 return DMUB_STATUS_OK;
1051 }
1052 return DMUB_STATUS_TIMEOUT;
1053}
1054
1055enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub,
1056 union dmub_inbox0_data_register data)
1057{
e56e9ad0 1058 if (!dmub->hw_init || !dmub->hw_funcs.send_inbox0_cmd)
d493a024
AL		 1059 return DMUB_STATUS_INVALID;
1060
1061 dmub->hw_funcs.send_inbox0_cmd(dmub, data);
1062 return DMUB_STATUS_OK;
1063}
0b9dc439
AL		 1064
1065void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index)
1066{
1067 if (dmub->hw_funcs.subvp_save_surf_addr) {
1068 dmub->hw_funcs.subvp_save_surf_addr(dmub,
1069 addr,
1070 subvp_index);
1071 }
1072}
Linux 6.x block layer and io_uring tree(s)