[linux-block.git] / drivers / gpu / drm / amd / display / dc / inc / dc_link_dp.h

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#ifndef __DC_LINK_DP_H__
#define __DC_LINK_DP_H__

#define LINK_TRAINING_ATTEMPTS 4
#define LINK_TRAINING_RETRY_DELAY 50 /* ms */
#define LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD 3200 /*us*/
#define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 552 /*us*/
#define MAX_MTP_SLOT_COUNT 64
#define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50
#define TRAINING_AUX_RD_INTERVAL 100 //us
#define LINK_AUX_WAKE_TIMEOUT_MS 1500 // Timeout when trying to wake unresponsive DPRX.

struct dc_link;
struct dc_stream_state;
struct dc_link_settings;

enum {
	LINK_TRAINING_MAX_RETRY_COUNT = 5,
	/* to avoid infinite loop where-in the receiver
	 * switches between different VS
	 */
	LINK_TRAINING_MAX_CR_RETRY = 100,
	/*
	 * Some receivers fail to train on first try and are good
	 * on subsequent tries. 2 retries should be plenty. If we
	 * don't have a successful training then we don't expect to
	 * ever get one.
	 */
	LINK_TRAINING_MAX_VERIFY_RETRY = 2,
	PEAK_FACTOR_X1000 = 1006,
};

struct dc_link_settings dp_get_max_link_cap(struct dc_link *link);

bool dp_verify_link_cap_with_retries(
	struct dc_link *link,
	struct dc_link_settings *known_limit_link_setting,
	int attempts);

bool dp_validate_mode_timing(
	struct dc_link *link,
	const struct dc_crtc_timing *timing);

bool decide_edp_link_settings(struct dc_link *link,
		struct dc_link_settings *link_setting,
		uint32_t req_bw);

void decide_link_settings(
	struct dc_stream_state *stream,
	struct dc_link_settings *link_setting);

bool perform_link_training_with_retries(
	const struct dc_link_settings *link_setting,
	bool skip_video_pattern,
	int attempts,
	struct pipe_ctx *pipe_ctx,
	enum signal_type signal,
	bool do_fallback);

bool hpd_rx_irq_check_link_loss_status(
	struct dc_link *link,
	union hpd_irq_data *hpd_irq_dpcd_data);

bool is_mst_supported(struct dc_link *link);

bool detect_dp_sink_caps(struct dc_link *link);

void detect_edp_sink_caps(struct dc_link *link);

bool is_dp_active_dongle(const struct dc_link *link);

bool is_dp_branch_device(const struct dc_link *link);

bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing);

void dp_enable_mst_on_sink(struct dc_link *link, bool enable);

enum dp_panel_mode dp_get_panel_mode(struct dc_link *link);
void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode);

bool dp_overwrite_extended_receiver_cap(struct dc_link *link);

void dpcd_set_source_specific_data(struct dc_link *link);

void dpcd_write_cable_id_to_dprx(struct dc_link *link);

/* Write DPCD link configuration data. */
enum dc_status dpcd_set_link_settings(
	struct dc_link *link,
	const struct link_training_settings *lt_settings);
/* Write DPCD drive settings. */
enum dc_status dpcd_set_lane_settings(
	struct dc_link *link,
	const struct link_training_settings *link_training_setting,
	uint32_t offset);
/* Read training status and adjustment requests from DPCD. */
enum dc_status dp_get_lane_status_and_lane_adjust(
	struct dc_link *link,
	const struct link_training_settings *link_training_setting,
	union lane_status ln_status[LANE_COUNT_DP_MAX],
	union lane_align_status_updated *ln_align,
	union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
	uint32_t offset);

void dp_wait_for_training_aux_rd_interval(
	struct dc_link *link,
	uint32_t wait_in_micro_secs);

bool dp_is_cr_done(enum dc_lane_count ln_count,
	union lane_status *dpcd_lane_status);

enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count,
	union lane_status *dpcd_lane_status);

bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
	union lane_status *dpcd_lane_status);
bool dp_is_symbol_locked(enum dc_lane_count ln_count,
	union lane_status *dpcd_lane_status);
bool dp_is_interlane_aligned(union lane_align_status_updated align_status);

bool dp_is_max_vs_reached(
	const struct link_training_settings *lt_settings);
void dp_hw_to_dpcd_lane_settings(
	const struct link_training_settings *lt_settings,
	const struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
	union dpcd_training_lane dpcd_lane_settings[]);
void dp_decide_lane_settings(
	const struct link_training_settings *lt_settings,
	const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
	struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
	union dpcd_training_lane dpcd_lane_settings[]);

uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval);

enum dpcd_training_patterns
	dc_dp_training_pattern_to_dpcd_training_pattern(
	struct dc_link *link,
	enum dc_dp_training_pattern pattern);

uint8_t dc_dp_initialize_scrambling_data_symbols(
	struct dc_link *link,
	enum dc_dp_training_pattern pattern);

enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource *link_res, bool ready);
void dp_set_fec_enable(struct dc_link *link, bool enable);
bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update);
void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable);

/* Initialize output parameter lt_settings. */
void dp_decide_training_settings(
	struct dc_link *link,
	const struct dc_link_settings *link_setting,
	struct link_training_settings *lt_settings);

/* Convert PHY repeater count read from DPCD uint8_t. */
uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count);

/* Check DPCD training status registers to detect link loss. */
enum link_training_result dp_check_link_loss_status(
		struct dc_link *link,
		const struct link_training_settings *link_training_setting);

enum dc_status dpcd_configure_lttpr_mode(
		struct dc_link *link,
		struct link_training_settings *lt_settings);

enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings);
bool dpcd_write_128b_132b_sst_payload_allocation_table(
		const struct dc_stream_state *stream,
		struct dc_link *link,
		struct link_mst_stream_allocation_table *proposed_table,
		bool allocate);

enum dc_status dpcd_configure_channel_coding(
		struct dc_link *link,
		struct link_training_settings *lt_settings);

bool dpcd_poll_for_allocation_change_trigger(struct dc_link *link);

struct fixed31_32 calculate_sst_avg_time_slots_per_mtp(
		const struct dc_stream_state *stream,
		const struct dc_link *link);
void enable_dp_hpo_output(struct dc_link *link,
		const struct link_resource *link_res,
		const struct dc_link_settings *link_settings);
void disable_dp_hpo_output(struct dc_link *link,
		const struct link_resource *link_res,
		enum signal_type signal);
void setup_dp_hpo_stream(struct pipe_ctx *pipe_ctx, bool enable);
bool is_dp_128b_132b_signal(struct pipe_ctx *pipe_ctx);

bool dp_retrieve_lttpr_cap(struct dc_link *link);
void edp_panel_backlight_power_on(struct dc_link *link);
void dp_receiver_power_ctrl(struct dc_link *link, bool on);
void dp_source_sequence_trace(struct dc_link *link, uint8_t dp_test_mode);
void dp_enable_link_phy(
	struct dc_link *link,
	const struct link_resource *link_res,
	enum signal_type signal,
	enum clock_source_id clock_source,
	const struct dc_link_settings *link_settings);
void edp_add_delay_for_T9(struct dc_link *link);
bool edp_receiver_ready_T9(struct dc_link *link);
bool edp_receiver_ready_T7(struct dc_link *link);

void dp_disable_link_phy(struct dc_link *link, const struct link_resource *link_res,
		enum signal_type signal);

void dp_disable_link_phy_mst(struct dc_link *link, const struct link_resource *link_res,
		enum signal_type signal);

bool dp_set_hw_training_pattern(
		struct dc_link *link,
		const struct link_resource *link_res,
		enum dc_dp_training_pattern pattern,
		uint32_t offset);

void dp_set_hw_lane_settings(
		struct dc_link *link,
		const struct link_resource *link_res,
		const struct link_training_settings *link_settings,
		uint32_t offset);

void dp_set_hw_test_pattern(
		struct dc_link *link,
		const struct link_resource *link_res,
		enum dp_test_pattern test_pattern,
		uint8_t *custom_pattern,
		uint32_t custom_pattern_size);

void dp_retrain_link_dp_test(struct dc_link *link,
		struct dc_link_settings *link_setting,
		bool skip_video_pattern);
#endif /* __DC_LINK_DP_H__ */
Commit	Line	Data
4562236b HW	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#ifndef __DC_LINK_DP_H__
	27	#define __DC_LINK_DP_H__
	28
	29	#define LINK_TRAINING_ATTEMPTS 4
	30	#define LINK_TRAINING_RETRY_DELAY 50 /* ms */
c797ede0	31	#define LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD 3200 /us/
61aa7a6f	32	#define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 552 /us/
f01ee019	33	#define MAX_MTP_SLOT_COUNT 64
e84ecdc5 JK	34	#define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50
e84ecdc5 JK	35	#define TRAINING_AUX_RD_INTERVAL 100 //us
2944dbed	36	#define LINK_AUX_WAKE_TIMEOUT_MS 1500 // Timeout when trying to wake unresponsive DPRX.
4562236b	37
d0778ebf	38	struct dc_link;
0971c40e	39	struct dc_stream_state;
4562236b HW	40	struct dc_link_settings;
4562236b HW	41
e84ecdc5 JK	42	enum {
	43	LINK_TRAINING_MAX_RETRY_COUNT = 5,
	44	/* to avoid infinite loop where-in the receiver
	45	* switches between different VS
	46	*/
8a58e25b WL	47	LINK_TRAINING_MAX_CR_RETRY = 100,
	48	/*
	49	* Some receivers fail to train on first try and are good
	50	* on subsequent tries. 2 retries should be plenty. If we
	51	* don't have a successful training then we don't expect to
	52	* ever get one.
	53	*/
	54	LINK_TRAINING_MAX_VERIFY_RETRY = 2,
	55	PEAK_FACTOR_X1000 = 1006,
e84ecdc5 JK	56	};
e84ecdc5 JK	57
c282d951 WL	58	struct dc_link_settings dp_get_max_link_cap(struct dc_link *link);
c282d951 WL	59
e7f2c80c WL	60	bool dp_verify_link_cap_with_retries(
	61	struct dc_link *link,
	62	struct dc_link_settings *known_limit_link_setting,
	63	int attempts);
	64
4562236b	65	bool dp_validate_mode_timing(
d0778ebf	66	struct dc_link *link,
4562236b HW	67	const struct dc_crtc_timing *timing);
4562236b HW	68
8efd0f5a MS	69	bool decide_edp_link_settings(struct dc_link *link,
	70	struct dc_link_settings *link_setting,
	71	uint32_t req_bw);
	72
4562236b	73	void decide_link_settings(
0971c40e	74	struct dc_stream_state *stream,
4562236b HW	75	struct dc_link_settings *link_setting);
	76
	77	bool perform_link_training_with_retries(
4562236b HW	78	const struct dc_link_settings *link_setting,
4562236b HW	79	bool skip_video_pattern,
832aa63b PH	80	int attempts,
832aa63b PH	81	struct pipe_ctx *pipe_ctx,
82253671 JK	82	enum signal_type signal,
82253671 JK	83	bool do_fallback);
4562236b	84
d2aa1356 AP	85	bool hpd_rx_irq_check_link_loss_status(
	86	struct dc_link *link,
	87	union hpd_irq_data *hpd_irq_dpcd_data);
	88
d0778ebf	89	bool is_mst_supported(struct dc_link *link);
4562236b	90
cdb39798	91	bool detect_dp_sink_caps(struct dc_link *link);
4562236b	92
4654a2f7 RL	93	void detect_edp_sink_caps(struct dc_link *link);
4654a2f7 RL	94
d0778ebf	95	bool is_dp_active_dongle(const struct dc_link *link);
4562236b	96
36c9137b DZ	97	bool is_dp_branch_device(const struct dc_link *link);
36c9137b DZ	98
f9fc6f39 MS	99	bool is_edp_ilr_optimization_required(struct dc_link link, struct dc_crtc_timing crtc_timing);
f9fc6f39 MS	100
d0778ebf	101	void dp_enable_mst_on_sink(struct dc_link *link, bool enable);
07c84c7a	102
0b226322 DG	103	enum dp_panel_mode dp_get_panel_mode(struct dc_link *link);
	104	void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode);
	105
8547058b LH	106	bool dp_overwrite_extended_receiver_cap(struct dc_link *link);
8547058b LH	107
96577cf8	108	void dpcd_set_source_specific_data(struct dc_link *link);
4a3ad932	109
c595fb05	110	void dpcd_write_cable_id_to_dprx(struct dc_link *link);
4a3ad932	111
7211b605 JK	112	/* Write DPCD link configuration data. */
	113	enum dc_status dpcd_set_link_settings(
	114	struct dc_link *link,
	115	const struct link_training_settings *lt_settings);
e84ecdc5 JK	116	/* Write DPCD drive settings. */
	117	enum dc_status dpcd_set_lane_settings(
	118	struct dc_link *link,
	119	const struct link_training_settings *link_training_setting,
	120	uint32_t offset);
	121	/* Read training status and adjustment requests from DPCD. */
c224aac8	122	enum dc_status dp_get_lane_status_and_lane_adjust(
e84ecdc5 JK	123	struct dc_link *link,
e84ecdc5 JK	124	const struct link_training_settings *link_training_setting,
c224aac8 WL	125	union lane_status ln_status[LANE_COUNT_DP_MAX],
	126	union lane_align_status_updated *ln_align,
	127	union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
e84ecdc5 JK	128	uint32_t offset);
	129
	130	void dp_wait_for_training_aux_rd_interval(
	131	struct dc_link *link,
	132	uint32_t wait_in_micro_secs);
	133
	134	bool dp_is_cr_done(enum dc_lane_count ln_count,
	135	union lane_status *dpcd_lane_status);
	136
	137	enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count,
	138	union lane_status *dpcd_lane_status);
	139
0cb15885 JK	140	bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
	141	union lane_status *dpcd_lane_status);
	142	bool dp_is_symbol_locked(enum dc_lane_count ln_count,
	143	union lane_status *dpcd_lane_status);
	144	bool dp_is_interlane_aligned(union lane_align_status_updated align_status);
	145
e84ecdc5 JK	146	bool dp_is_max_vs_reached(
e84ecdc5 JK	147	const struct link_training_settings *lt_settings);
f6e54f06 WL	148	void dp_hw_to_dpcd_lane_settings(
	149	const struct link_training_settings *lt_settings,
	150	const struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
1b9728a0	151	union dpcd_training_lane dpcd_lane_settings[]);
c224aac8 WL	152	void dp_decide_lane_settings(
	153	const struct link_training_settings *lt_settings,
	154	const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
	155	struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
1b9728a0	156	union dpcd_training_lane dpcd_lane_settings[]);
e84ecdc5	157
0cb15885 JK	158	uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval);
0cb15885 JK	159
e84ecdc5 JK	160	enum dpcd_training_patterns
	161	dc_dp_training_pattern_to_dpcd_training_pattern(
	162	struct dc_link *link,
	163	enum dc_dp_training_pattern pattern);
	164
	165	uint8_t dc_dp_initialize_scrambling_data_symbols(
	166	struct dc_link *link,
	167	enum dc_dp_training_pattern pattern);
96577cf8	168
ef30f441	169	enum dc_status dp_set_fec_ready(struct dc_link link, const struct link_resource link_res, bool ready);
97bda032 HW	170	void dp_set_fec_enable(struct dc_link *link, bool enable);
97bda032 HW	171	bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
253a5591	172	bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update);
1a9e3d45	173	void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
ba32c50f	174	bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
8cf9575d MH	175	bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable);
8cf9575d MH	176
7211b605 JK	177	/* Initialize output parameter lt_settings. */
	178	void dp_decide_training_settings(
	179	struct dc_link *link,
	180	const struct dc_link_settings *link_setting,
7211b605 JK	181	struct link_training_settings *lt_settings);
7211b605 JK	182
573a0a03 JK	183	/* Convert PHY repeater count read from DPCD uint8_t. */
	184	uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count);
	185
	186	/* Check DPCD training status registers to detect link loss. */
	187	enum link_training_result dp_check_link_loss_status(
	188	struct dc_link *link,
	189	const struct link_training_settings *link_training_setting);
97bda032	190
7211b605 JK	191	enum dc_status dpcd_configure_lttpr_mode(
	192	struct dc_link *link,
	193	struct link_training_settings *lt_settings);
	194
55bac4a7	195	enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings);
f01ee019 FZ	196	bool dpcd_write_128b_132b_sst_payload_allocation_table(
	197	const struct dc_stream_state *stream,
	198	struct dc_link *link,
	199	struct link_mst_stream_allocation_table *proposed_table,
	200	bool allocate);
	201
	202	enum dc_status dpcd_configure_channel_coding(
	203	struct dc_link *link,
	204	struct link_training_settings *lt_settings);
	205
	206	bool dpcd_poll_for_allocation_change_trigger(struct dc_link *link);
	207
	208	struct fixed31_32 calculate_sst_avg_time_slots_per_mtp(
	209	const struct dc_stream_state *stream,
	210	const struct dc_link *link);
ef30f441 WL	211	void enable_dp_hpo_output(struct dc_link *link,
	212	const struct link_resource *link_res,
	213	const struct dc_link_settings *link_settings);
	214	void disable_dp_hpo_output(struct dc_link *link,
	215	const struct link_resource *link_res,
	216	enum signal_type signal);
f01ee019 FZ	217	void setup_dp_hpo_stream(struct pipe_ctx *pipe_ctx, bool enable);
f01ee019 FZ	218	bool is_dp_128b_132b_signal(struct pipe_ctx *pipe_ctx);
f01ee019	219
4d1d699f	220	bool dp_retrieve_lttpr_cap(struct dc_link *link);
0a043904	221	void edp_panel_backlight_power_on(struct dc_link *link);
dfabe597 WL	222	void dp_receiver_power_ctrl(struct dc_link *link, bool on);
	223	void dp_source_sequence_trace(struct dc_link *link, uint8_t dp_test_mode);
	224	void dp_enable_link_phy(
	225	struct dc_link *link,
	226	const struct link_resource *link_res,
	227	enum signal_type signal,
	228	enum clock_source_id clock_source,
	229	const struct dc_link_settings *link_settings);
	230	void edp_add_delay_for_T9(struct dc_link *link);
	231	bool edp_receiver_ready_T9(struct dc_link *link);
	232	bool edp_receiver_ready_T7(struct dc_link *link);
	233
	234	void dp_disable_link_phy(struct dc_link link, const struct link_resource link_res,
	235	enum signal_type signal);
	236
	237	void dp_disable_link_phy_mst(struct dc_link link, const struct link_resource link_res,
	238	enum signal_type signal);
	239
	240	bool dp_set_hw_training_pattern(
	241	struct dc_link *link,
	242	const struct link_resource *link_res,
	243	enum dc_dp_training_pattern pattern,
	244	uint32_t offset);
	245
	246	void dp_set_hw_lane_settings(
	247	struct dc_link *link,
	248	const struct link_resource *link_res,
	249	const struct link_training_settings *link_settings,
	250	uint32_t offset);
	251
	252	void dp_set_hw_test_pattern(
	253	struct dc_link *link,
	254	const struct link_resource *link_res,
	255	enum dp_test_pattern test_pattern,
	256	uint8_t *custom_pattern,
	257	uint32_t custom_pattern_size);
	258
	259	void dp_retrain_link_dp_test(struct dc_link *link,
	260	struct dc_link_settings *link_setting,
	261	bool skip_video_pattern);
4562236b	262	#endif /* __DC_LINK_DP_H__ */