[linux-block.git] / drivers / gpu / drm / amd / display / dc / inc / dc_link_dp.h

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#ifndef __DC_LINK_DP_H__
#define __DC_LINK_DP_H__

#define LINK_TRAINING_ATTEMPTS 4
#define LINK_TRAINING_RETRY_DELAY 50 /* ms */
#define LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD 3200 /*us*/
#define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 552 /*us*/

struct dc_link;
struct dc_stream_state;
struct dc_link_settings;

bool dp_verify_link_cap(
	struct dc_link *link,
	struct dc_link_settings *known_limit_link_setting,
	int *fail_count);

bool dp_verify_link_cap_with_retries(
	struct dc_link *link,
	struct dc_link_settings *known_limit_link_setting,
	int attempts);

bool dp_verify_mst_link_cap(
	struct dc_link *link);

bool dp_validate_mode_timing(
	struct dc_link *link,
	const struct dc_crtc_timing *timing);

bool decide_edp_link_settings(struct dc_link *link,
		struct dc_link_settings *link_setting,
		uint32_t req_bw);

void decide_link_settings(
	struct dc_stream_state *stream,
	struct dc_link_settings *link_setting);

bool perform_link_training_with_retries(
	const struct dc_link_settings *link_setting,
	bool skip_video_pattern,
	int attempts,
	struct pipe_ctx *pipe_ctx,
	enum signal_type signal,
	bool do_fallback);

bool is_mst_supported(struct dc_link *link);

bool detect_dp_sink_caps(struct dc_link *link);

void detect_edp_sink_caps(struct dc_link *link);

bool is_dp_active_dongle(const struct dc_link *link);

bool is_dp_branch_device(const struct dc_link *link);

bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing);

void dp_enable_mst_on_sink(struct dc_link *link, bool enable);

enum dp_panel_mode dp_get_panel_mode(struct dc_link *link);
void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode);

bool dp_overwrite_extended_receiver_cap(struct dc_link *link);

void dpcd_set_source_specific_data(struct dc_link *link);

void dp_set_fec_ready(struct dc_link *link, bool ready);
void dp_set_fec_enable(struct dc_link *link, bool enable);
bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable);
void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable);

/* Convert PHY repeater count read from DPCD uint8_t. */
uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count);

/* Check DPCD training status registers to detect link loss. */
enum link_training_result dp_check_link_loss_status(
		struct dc_link *link,
		const struct link_training_settings *link_training_setting);

enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings);
#endif /* __DC_LINK_DP_H__ */
Commit	Line	Data
4562236b HW	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#ifndef __DC_LINK_DP_H__
	27	#define __DC_LINK_DP_H__
	28
	29	#define LINK_TRAINING_ATTEMPTS 4
	30	#define LINK_TRAINING_RETRY_DELAY 50 /* ms */
c797ede0	31	#define LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD 3200 /us/
61aa7a6f	32	#define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 552 /us/
4562236b	33
d0778ebf	34	struct dc_link;
0971c40e	35	struct dc_stream_state;
4562236b HW	36	struct dc_link_settings;
4562236b HW	37
aafded88	38	bool dp_verify_link_cap(
d0778ebf	39	struct dc_link *link,
824474ba BL	40	struct dc_link_settings *known_limit_link_setting,
824474ba BL	41	int *fail_count);
4562236b	42
e7f2c80c WL	43	bool dp_verify_link_cap_with_retries(
	44	struct dc_link *link,
	45	struct dc_link_settings *known_limit_link_setting,
	46	int attempts);
	47
f537d474 LH	48	bool dp_verify_mst_link_cap(
	49	struct dc_link *link);
	50
4562236b	51	bool dp_validate_mode_timing(
d0778ebf	52	struct dc_link *link,
4562236b HW	53	const struct dc_crtc_timing *timing);
4562236b HW	54
8efd0f5a MS	55	bool decide_edp_link_settings(struct dc_link *link,
	56	struct dc_link_settings *link_setting,
	57	uint32_t req_bw);
	58
4562236b	59	void decide_link_settings(
0971c40e	60	struct dc_stream_state *stream,
4562236b HW	61	struct dc_link_settings *link_setting);
	62
	63	bool perform_link_training_with_retries(
4562236b HW	64	const struct dc_link_settings *link_setting,
4562236b HW	65	bool skip_video_pattern,
832aa63b PH	66	int attempts,
832aa63b PH	67	struct pipe_ctx *pipe_ctx,
82253671 JK	68	enum signal_type signal,
82253671 JK	69	bool do_fallback);
4562236b	70
d0778ebf	71	bool is_mst_supported(struct dc_link *link);
4562236b	72
cdb39798	73	bool detect_dp_sink_caps(struct dc_link *link);
4562236b	74
4654a2f7 RL	75	void detect_edp_sink_caps(struct dc_link *link);
4654a2f7 RL	76
d0778ebf	77	bool is_dp_active_dongle(const struct dc_link *link);
4562236b	78
36c9137b DZ	79	bool is_dp_branch_device(const struct dc_link *link);
36c9137b DZ	80
f9fc6f39 MS	81	bool is_edp_ilr_optimization_required(struct dc_link link, struct dc_crtc_timing crtc_timing);
f9fc6f39 MS	82
d0778ebf	83	void dp_enable_mst_on_sink(struct dc_link *link, bool enable);
07c84c7a	84
0b226322 DG	85	enum dp_panel_mode dp_get_panel_mode(struct dc_link *link);
	86	void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode);
	87
8547058b LH	88	bool dp_overwrite_extended_receiver_cap(struct dc_link *link);
8547058b LH	89
96577cf8 HW	90	void dpcd_set_source_specific_data(struct dc_link *link);
96577cf8 HW	91
97bda032 HW	92	void dp_set_fec_ready(struct dc_link *link, bool ready);
	93	void dp_set_fec_enable(struct dc_link *link, bool enable);
	94	bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
1a9e3d45 NC	95	bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable);
1a9e3d45 NC	96	void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
ba32c50f	97	bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
8cf9575d MH	98	bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable);
8cf9575d MH	99
573a0a03 JK	100	/* Convert PHY repeater count read from DPCD uint8_t. */
	101	uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count);
	102
	103	/* Check DPCD training status registers to detect link loss. */
	104	enum link_training_result dp_check_link_loss_status(
	105	struct dc_link *link,
	106	const struct link_training_settings *link_training_setting);
97bda032	107
55bac4a7	108	enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings);
4562236b	109	#endif /* __DC_LINK_DP_H__ */