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7966f319 QZ |
1 | /* SPDX-License-Identifier: MIT */ |
2 | /* | |
3 | * Copyright 2023 Advanced Micro Devices, Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
d30a584c SW |
23 | * Authors: AMD |
24 | * | |
7966f319 QZ |
25 | */ |
26 | ||
27 | #include "display_mode_core.h" | |
28 | #include "dml2_internal_types.h" | |
29 | #include "dml2_translation_helper.h" | |
30 | ||
31 | #define NUM_DCFCLK_STAS 5 | |
32 | ||
33 | void dml2_init_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_params_st *out) | |
34 | { | |
35 | switch (dml2->v20.dml_core_ctx.project) { | |
36 | ||
37 | case dml_project_dcn32: | |
38 | case dml_project_dcn321: | |
39 | default: | |
40 | // Hardcoded values for DCN32x | |
41 | out->vblank_nom_default_us = 600; | |
42 | out->rob_buffer_size_kbytes = 128; | |
43 | out->config_return_buffer_size_in_kbytes = 1280; | |
44 | out->config_return_buffer_segment_size_in_kbytes = 64; | |
45 | out->compressed_buffer_segment_size_in_kbytes = 64; | |
46 | out->meta_fifo_size_in_kentries = 22; | |
47 | out->zero_size_buffer_entries = 512; | |
48 | out->dpte_buffer_size_in_pte_reqs_luma = 68; | |
49 | out->dpte_buffer_size_in_pte_reqs_chroma = 36; | |
50 | out->dcc_meta_buffer_size_bytes = 6272; | |
51 | out->gpuvm_max_page_table_levels = 4; | |
52 | out->hostvm_max_page_table_levels = 0; | |
53 | out->pixel_chunk_size_kbytes = 8; | |
54 | //out->alpha_pixel_chunk_size_kbytes; | |
55 | out->min_pixel_chunk_size_bytes = 1024; | |
56 | out->meta_chunk_size_kbytes = 2; | |
57 | out->min_meta_chunk_size_bytes = 256; | |
58 | out->writeback_chunk_size_kbytes = 8; | |
59 | out->line_buffer_size_bits = 1171920; | |
60 | out->max_line_buffer_lines = 32; | |
61 | out->writeback_interface_buffer_size_kbytes = 90; | |
62 | //Number of pipes after DCN Pipe harvesting | |
63 | out->max_num_dpp = dml2->config.dcn_pipe_count; | |
64 | out->max_num_otg = dml2->config.dcn_pipe_count; | |
65 | out->max_num_wb = 1; | |
66 | out->max_dchub_pscl_bw_pix_per_clk = 4; | |
67 | out->max_pscl_lb_bw_pix_per_clk = 2; | |
68 | out->max_lb_vscl_bw_pix_per_clk = 4; | |
69 | out->max_vscl_hscl_bw_pix_per_clk = 4; | |
70 | out->max_hscl_ratio = 6; | |
71 | out->max_vscl_ratio = 6; | |
72 | out->max_hscl_taps = 8; | |
73 | out->max_vscl_taps = 8; | |
74 | out->dispclk_ramp_margin_percent = 1; | |
75 | out->dppclk_delay_subtotal = 47; | |
76 | out->dppclk_delay_scl = 50; | |
77 | out->dppclk_delay_scl_lb_only = 16; | |
78 | out->dppclk_delay_cnvc_formatter = 28; | |
79 | out->dppclk_delay_cnvc_cursor = 6; | |
80 | out->cursor_buffer_size = 16; | |
81 | out->cursor_chunk_size = 2; | |
82 | out->dispclk_delay_subtotal = 125; | |
83 | out->max_inter_dcn_tile_repeaters = 8; | |
84 | out->writeback_max_hscl_ratio = 1; | |
85 | out->writeback_max_vscl_ratio = 1; | |
86 | out->writeback_min_hscl_ratio = 1; | |
87 | out->writeback_min_vscl_ratio = 1; | |
88 | out->writeback_max_hscl_taps = 1; | |
89 | out->writeback_max_vscl_taps = 1; | |
90 | out->writeback_line_buffer_buffer_size = 0; | |
91 | out->num_dsc = 4; | |
92 | out->maximum_dsc_bits_per_component = 12; | |
93 | out->maximum_pixels_per_line_per_dsc_unit = 6016; | |
94 | out->dsc422_native_support = true; | |
95 | out->dcc_supported = true; | |
96 | out->ptoi_supported = false; | |
97 | ||
98 | out->gpuvm_enable = false; | |
99 | out->hostvm_enable = false; | |
100 | out->cursor_64bpp_support = false; | |
101 | out->dynamic_metadata_vm_enabled = false; | |
102 | ||
103 | out->max_num_hdmi_frl_outputs = 1; | |
104 | out->max_num_dp2p0_outputs = 2; | |
105 | out->max_num_dp2p0_streams = 4; | |
106 | break; | |
107 | ||
115009d1 QZ |
108 | case dml_project_dcn35: |
109 | case dml_project_dcn351: | |
110 | out->rob_buffer_size_kbytes = 64; | |
111 | out->config_return_buffer_size_in_kbytes = 1792; | |
112 | out->compressed_buffer_segment_size_in_kbytes = 64; | |
113 | out->meta_fifo_size_in_kentries = 32; | |
114 | out->zero_size_buffer_entries = 512; | |
115 | out->pixel_chunk_size_kbytes = 8; | |
116 | out->alpha_pixel_chunk_size_kbytes = 4; | |
117 | out->min_pixel_chunk_size_bytes = 1024; | |
118 | out->meta_chunk_size_kbytes = 2; | |
119 | out->min_meta_chunk_size_bytes = 256; | |
120 | out->writeback_chunk_size_kbytes = 8; | |
121 | out->dpte_buffer_size_in_pte_reqs_luma = 68; | |
122 | out->dpte_buffer_size_in_pte_reqs_chroma = 36; | |
123 | out->dcc_meta_buffer_size_bytes = 6272; | |
124 | out->gpuvm_enable = 1; | |
125 | out->hostvm_enable = 1; | |
126 | out->gpuvm_max_page_table_levels = 1; | |
127 | out->hostvm_max_page_table_levels = 2; | |
128 | out->num_dsc = 4; | |
129 | out->maximum_dsc_bits_per_component = 12; | |
130 | out->maximum_pixels_per_line_per_dsc_unit = 6016; | |
131 | out->dsc422_native_support = 1; | |
132 | out->line_buffer_size_bits = 986880; | |
133 | out->dcc_supported = 1; | |
134 | out->max_line_buffer_lines = 32; | |
135 | out->writeback_interface_buffer_size_kbytes = 90; | |
136 | out->max_num_dpp = 4; | |
137 | out->max_num_otg = 4; | |
138 | out->max_num_hdmi_frl_outputs = 1; | |
139 | out->max_num_dp2p0_outputs = 2; | |
140 | out->max_num_dp2p0_streams = 4; | |
141 | out->max_num_wb = 1; | |
142 | ||
143 | out->max_dchub_pscl_bw_pix_per_clk = 4; | |
144 | out->max_pscl_lb_bw_pix_per_clk = 2; | |
145 | out->max_lb_vscl_bw_pix_per_clk = 4; | |
146 | out->max_vscl_hscl_bw_pix_per_clk = 4; | |
147 | out->max_hscl_ratio = 6; | |
148 | out->max_vscl_ratio = 6; | |
149 | out->max_hscl_taps = 8; | |
150 | out->max_vscl_taps = 8; | |
151 | out->dispclk_ramp_margin_percent = 1.11; | |
152 | ||
153 | out->dppclk_delay_subtotal = 47; | |
154 | out->dppclk_delay_scl = 50; | |
155 | out->dppclk_delay_scl_lb_only = 16; | |
156 | out->dppclk_delay_cnvc_formatter = 28; | |
157 | out->dppclk_delay_cnvc_cursor = 6; | |
158 | out->dispclk_delay_subtotal = 125; | |
159 | ||
160 | out->dynamic_metadata_vm_enabled = false; | |
161 | out->max_inter_dcn_tile_repeaters = 8; | |
162 | out->cursor_buffer_size = 16; // kBytes | |
163 | out->cursor_chunk_size = 2; // kBytes | |
164 | ||
165 | out->writeback_line_buffer_buffer_size = 0; | |
166 | out->writeback_max_hscl_ratio = 1; | |
167 | out->writeback_max_vscl_ratio = 1; | |
168 | out->writeback_min_hscl_ratio = 1; | |
169 | out->writeback_min_vscl_ratio = 1; | |
170 | out->writeback_max_hscl_taps = 1; | |
171 | out->writeback_max_vscl_taps = 1; | |
172 | out->ptoi_supported = 0; | |
173 | ||
174 | out->vblank_nom_default_us = 668; /*not in dml, but in programming guide, hard coded in dml2_translate_ip_params*/ | |
175 | out->config_return_buffer_segment_size_in_kbytes = 64; /*required, but not exist,, hard coded in dml2_translate_ip_params*/ | |
176 | break; | |
177 | ||
7966f319 QZ |
178 | } |
179 | } | |
180 | ||
181 | void dml2_init_socbb_params(struct dml2_context *dml2, const struct dc *in_dc, struct soc_bounding_box_st *out) | |
182 | { | |
183 | out->dprefclk_mhz = dml2->config.bbox_overrides.dprefclk_mhz; | |
184 | out->xtalclk_mhz = dml2->config.bbox_overrides.xtalclk_mhz; | |
185 | out->pcierefclk_mhz = 100; | |
186 | out->refclk_mhz = dml2->config.bbox_overrides.dchub_refclk_mhz; | |
187 | ||
188 | out->max_outstanding_reqs = 512; | |
189 | out->pct_ideal_sdp_bw_after_urgent = 100; | |
190 | out->pct_ideal_fabric_bw_after_urgent = 67; | |
191 | out->pct_ideal_dram_bw_after_urgent_pixel_only = 20; | |
192 | out->pct_ideal_dram_bw_after_urgent_pixel_and_vm = 60; | |
193 | out->pct_ideal_dram_bw_after_urgent_vm_only = 30; | |
194 | out->pct_ideal_dram_bw_after_urgent_strobe = 67; | |
195 | out->max_avg_sdp_bw_use_normal_percent = 80; | |
196 | out->max_avg_fabric_bw_use_normal_percent = 60; | |
197 | out->max_avg_dram_bw_use_normal_percent = 15; | |
198 | out->max_avg_dram_bw_use_normal_strobe_percent = 50; | |
199 | ||
200 | out->urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096; | |
201 | out->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096; | |
202 | out->urgent_out_of_order_return_per_channel_vm_only_bytes = 4096; | |
203 | out->return_bus_width_bytes = 64; | |
204 | out->dram_channel_width_bytes = 2; | |
205 | out->fabric_datapath_to_dcn_data_return_bytes = 64; | |
206 | out->hostvm_min_page_size_kbytes = 0; | |
207 | out->gpuvm_min_page_size_kbytes = 256; | |
208 | out->phy_downspread_percent = 0.38; | |
209 | out->dcn_downspread_percent = 0.5; | |
210 | out->dispclk_dppclk_vco_speed_mhz = dml2->config.bbox_overrides.disp_pll_vco_speed_mhz; | |
211 | out->mall_allocated_for_dcn_mbytes = dml2->config.mall_cfg.max_cab_allocation_bytes / 1048576; // 64 or 32 MB; | |
212 | ||
213 | out->do_urgent_latency_adjustment = true; | |
214 | ||
215 | switch (dml2->v20.dml_core_ctx.project) { | |
216 | ||
217 | case dml_project_dcn32: | |
218 | default: | |
219 | out->num_chans = 24; | |
220 | out->round_trip_ping_latency_dcfclk_cycles = 263; | |
221 | out->smn_latency_us = 2; | |
222 | break; | |
223 | ||
224 | case dml_project_dcn321: | |
225 | out->num_chans = 8; | |
226 | out->round_trip_ping_latency_dcfclk_cycles = 207; | |
227 | out->smn_latency_us = 0; | |
228 | break; | |
229 | ||
115009d1 QZ |
230 | case dml_project_dcn35: |
231 | out->num_chans = 4; | |
232 | out->round_trip_ping_latency_dcfclk_cycles = 106; | |
233 | out->smn_latency_us = 2; | |
f9e7d4fa | 234 | out->dispclk_dppclk_vco_speed_mhz = 3600; |
115009d1 QZ |
235 | break; |
236 | ||
237 | case dml_project_dcn351: | |
238 | out->num_chans = 16; | |
239 | out->round_trip_ping_latency_dcfclk_cycles = 1100; | |
240 | out->smn_latency_us = 2; | |
241 | break; | |
7966f319 QZ |
242 | } |
243 | /* ---Overrides if available--- */ | |
244 | if (dml2->config.bbox_overrides.dram_num_chan) | |
245 | out->num_chans = dml2->config.bbox_overrides.dram_num_chan; | |
246 | ||
247 | if (dml2->config.bbox_overrides.dram_chanel_width_bytes) | |
248 | out->dram_channel_width_bytes = dml2->config.bbox_overrides.dram_chanel_width_bytes; | |
249 | } | |
250 | ||
251 | void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc, | |
252 | const struct soc_bounding_box_st *in_bbox, struct soc_states_st *out) | |
253 | { | |
254 | struct dml2_policy_build_synthetic_soc_states_scratch *s = &dml2->v20.scratch.create_scratch.build_synthetic_socbb_scratch; | |
255 | struct dml2_policy_build_synthetic_soc_states_params *p = &dml2->v20.scratch.build_synthetic_socbb_params; | |
256 | unsigned int dcfclk_stas_mhz[NUM_DCFCLK_STAS]; | |
257 | unsigned int i = 0; | |
258 | unsigned int transactions_per_mem_clock = 16; // project specific, depends on used Memory type | |
259 | ||
260 | p->dcfclk_stas_mhz = dcfclk_stas_mhz; | |
261 | p->num_dcfclk_stas = NUM_DCFCLK_STAS; | |
262 | p->in_bbox = in_bbox; | |
263 | p->out_states = out; | |
264 | p->in_states = &dml2->v20.scratch.create_scratch.in_states; | |
265 | ||
266 | ||
267 | /* Initial hardcoded values */ | |
268 | switch (dml2->v20.dml_core_ctx.project) { | |
269 | ||
270 | case dml_project_dcn32: | |
271 | default: | |
272 | p->in_states->num_states = 2; | |
273 | transactions_per_mem_clock = 16; | |
274 | p->in_states->state_array[0].socclk_mhz = 620.0; | |
275 | p->in_states->state_array[0].dscclk_mhz = 716.667; | |
276 | p->in_states->state_array[0].phyclk_mhz = 810; | |
277 | p->in_states->state_array[0].phyclk_d18_mhz = 667; | |
278 | p->in_states->state_array[0].phyclk_d32_mhz = 625; | |
279 | p->in_states->state_array[0].dtbclk_mhz = 1564.0; | |
280 | p->in_states->state_array[0].fabricclk_mhz = 450.0; | |
281 | p->in_states->state_array[0].dcfclk_mhz = 300.0; | |
282 | p->in_states->state_array[0].dispclk_mhz = 2150.0; | |
283 | p->in_states->state_array[0].dppclk_mhz = 2150.0; | |
284 | p->in_states->state_array[0].dram_speed_mts = 100 * transactions_per_mem_clock; | |
285 | ||
286 | p->in_states->state_array[0].urgent_latency_pixel_data_only_us = 4; | |
287 | p->in_states->state_array[0].urgent_latency_pixel_mixed_with_vm_data_us = 0; | |
288 | p->in_states->state_array[0].urgent_latency_vm_data_only_us = 0; | |
289 | p->in_states->state_array[0].writeback_latency_us = 12; | |
290 | p->in_states->state_array[0].urgent_latency_adjustment_fabric_clock_component_us = 1; | |
291 | p->in_states->state_array[0].urgent_latency_adjustment_fabric_clock_reference_mhz = 3000; | |
292 | p->in_states->state_array[0].sr_exit_z8_time_us = 0; | |
293 | p->in_states->state_array[0].sr_enter_plus_exit_z8_time_us = 0; | |
294 | p->in_states->state_array[0].dram_clock_change_latency_us = 400; | |
295 | p->in_states->state_array[0].use_ideal_dram_bw_strobe = true; | |
296 | p->in_states->state_array[0].sr_exit_time_us = 42.97; | |
297 | p->in_states->state_array[0].sr_enter_plus_exit_time_us = 49.94; | |
298 | p->in_states->state_array[0].fclk_change_latency_us = 20; | |
299 | p->in_states->state_array[0].usr_retraining_latency_us = 2; | |
300 | ||
301 | p->in_states->state_array[1].socclk_mhz = 1200.0; | |
302 | p->in_states->state_array[1].fabricclk_mhz = 2500.0; | |
303 | p->in_states->state_array[1].dcfclk_mhz = 1564.0; | |
304 | p->in_states->state_array[1].dram_speed_mts = 1125 * transactions_per_mem_clock; | |
305 | break; | |
306 | ||
307 | case dml_project_dcn321: | |
308 | p->in_states->num_states = 2; | |
309 | transactions_per_mem_clock = 16; | |
310 | p->in_states->state_array[0].socclk_mhz = 582.0; | |
311 | p->in_states->state_array[0].dscclk_mhz = 573.333; | |
312 | p->in_states->state_array[0].phyclk_mhz = 810; | |
313 | p->in_states->state_array[0].phyclk_d18_mhz = 667; | |
314 | p->in_states->state_array[0].phyclk_d32_mhz = 313; | |
315 | p->in_states->state_array[0].dtbclk_mhz = 1564.0; | |
316 | p->in_states->state_array[0].fabricclk_mhz = 450.0; | |
317 | p->in_states->state_array[0].dcfclk_mhz = 300.0; | |
318 | p->in_states->state_array[0].dispclk_mhz = 1720.0; | |
319 | p->in_states->state_array[0].dppclk_mhz = 1720.0; | |
320 | p->in_states->state_array[0].dram_speed_mts = 100 * transactions_per_mem_clock; | |
321 | ||
322 | p->in_states->state_array[0].urgent_latency_pixel_data_only_us = 4; | |
323 | p->in_states->state_array[0].urgent_latency_pixel_mixed_with_vm_data_us = 0; | |
324 | p->in_states->state_array[0].urgent_latency_vm_data_only_us = 0; | |
325 | p->in_states->state_array[0].writeback_latency_us = 12; | |
326 | p->in_states->state_array[0].urgent_latency_adjustment_fabric_clock_component_us = 1; | |
327 | p->in_states->state_array[0].urgent_latency_adjustment_fabric_clock_reference_mhz = 3000; | |
328 | p->in_states->state_array[0].sr_exit_z8_time_us = 0; | |
329 | p->in_states->state_array[0].sr_enter_plus_exit_z8_time_us = 0; | |
330 | p->in_states->state_array[0].dram_clock_change_latency_us = 400; | |
331 | p->in_states->state_array[0].use_ideal_dram_bw_strobe = true; | |
332 | p->in_states->state_array[0].sr_exit_time_us = 19.95; | |
333 | p->in_states->state_array[0].sr_enter_plus_exit_time_us = 24.36; | |
334 | p->in_states->state_array[0].fclk_change_latency_us = 7; | |
335 | p->in_states->state_array[0].usr_retraining_latency_us = 0; | |
336 | ||
337 | p->in_states->state_array[1].socclk_mhz = 1200.0; | |
338 | p->in_states->state_array[1].fabricclk_mhz = 2250.0; | |
339 | p->in_states->state_array[1].dcfclk_mhz = 1434.0; | |
340 | p->in_states->state_array[1].dram_speed_mts = 1000 * transactions_per_mem_clock; | |
341 | break; | |
7966f319 QZ |
342 | } |
343 | ||
80061d6b NK |
344 | /* Override from passed values, if available */ |
345 | for (i = 0; i < p->in_states->num_states; i++) { | |
346 | if (dml2->config.bbox_overrides.sr_exit_latency_us) { | |
347 | p->in_states->state_array[i].sr_exit_time_us = | |
348 | dml2->config.bbox_overrides.sr_exit_latency_us; | |
349 | } | |
350 | ||
351 | if (dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us) { | |
352 | p->in_states->state_array[i].sr_enter_plus_exit_time_us = | |
353 | dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us; | |
354 | } | |
355 | ||
356 | if (dml2->config.bbox_overrides.sr_exit_z8_time_us) { | |
357 | p->in_states->state_array[i].sr_exit_z8_time_us = | |
358 | dml2->config.bbox_overrides.sr_exit_z8_time_us; | |
359 | } | |
360 | ||
361 | if (dml2->config.bbox_overrides.sr_enter_plus_exit_z8_time_us) { | |
362 | p->in_states->state_array[i].sr_enter_plus_exit_z8_time_us = | |
363 | dml2->config.bbox_overrides.sr_enter_plus_exit_z8_time_us; | |
364 | } | |
365 | ||
366 | if (dml2->config.bbox_overrides.urgent_latency_us) { | |
367 | p->in_states->state_array[i].urgent_latency_pixel_data_only_us = | |
368 | dml2->config.bbox_overrides.urgent_latency_us; | |
369 | } | |
370 | ||
371 | if (dml2->config.bbox_overrides.dram_clock_change_latency_us) { | |
372 | p->in_states->state_array[i].dram_clock_change_latency_us = | |
373 | dml2->config.bbox_overrides.dram_clock_change_latency_us; | |
374 | } | |
375 | ||
376 | if (dml2->config.bbox_overrides.fclk_change_latency_us) { | |
377 | p->in_states->state_array[i].fclk_change_latency_us = | |
378 | dml2->config.bbox_overrides.fclk_change_latency_us; | |
379 | } | |
7966f319 QZ |
380 | } |
381 | ||
382 | /* DCFCLK stas values are project specific */ | |
383 | if ((dml2->v20.dml_core_ctx.project == dml_project_dcn32) || | |
384 | (dml2->v20.dml_core_ctx.project == dml_project_dcn321)) { | |
385 | p->dcfclk_stas_mhz[0] = p->in_states->state_array[0].dcfclk_mhz; | |
386 | p->dcfclk_stas_mhz[1] = 615; | |
387 | p->dcfclk_stas_mhz[2] = 906; | |
388 | p->dcfclk_stas_mhz[3] = 1324; | |
389 | p->dcfclk_stas_mhz[4] = p->in_states->state_array[1].dcfclk_mhz; | |
115009d1 QZ |
390 | } else if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 && |
391 | dml2->v20.dml_core_ctx.project != dml_project_dcn351) { | |
392 | p->dcfclk_stas_mhz[0] = 300; | |
393 | p->dcfclk_stas_mhz[1] = 615; | |
394 | p->dcfclk_stas_mhz[2] = 906; | |
395 | p->dcfclk_stas_mhz[3] = 1324; | |
396 | p->dcfclk_stas_mhz[4] = 1500; | |
7966f319 QZ |
397 | } |
398 | /* Copy clocks tables entries, if available */ | |
399 | if (dml2->config.bbox_overrides.clks_table.num_states) { | |
514312c0 | 400 | p->in_states->num_states = dml2->config.bbox_overrides.clks_table.num_states; |
7966f319 QZ |
401 | for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels; i++) { |
402 | p->in_states->state_array[i].dcfclk_mhz = dml2->config.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz; | |
403 | } | |
404 | ||
405 | p->dcfclk_stas_mhz[0] = dml2->config.bbox_overrides.clks_table.clk_entries[0].dcfclk_mhz; | |
406 | if (i > 1) | |
407 | p->dcfclk_stas_mhz[4] = dml2->config.bbox_overrides.clks_table.clk_entries[i-1].dcfclk_mhz; | |
408 | ||
409 | for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels; i++) { | |
410 | p->in_states->state_array[i].fabricclk_mhz = | |
411 | dml2->config.bbox_overrides.clks_table.clk_entries[i].fclk_mhz; | |
412 | } | |
413 | ||
414 | for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels; i++) { | |
415 | p->in_states->state_array[i].dram_speed_mts = | |
416 | dml2->config.bbox_overrides.clks_table.clk_entries[i].memclk_mhz * transactions_per_mem_clock; | |
417 | } | |
418 | ||
419 | for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels; i++) { | |
420 | p->in_states->state_array[i].socclk_mhz = | |
421 | dml2->config.bbox_overrides.clks_table.clk_entries[i].socclk_mhz; | |
422 | } | |
423 | ||
424 | for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels; i++) { | |
c1afbb71 FZ |
425 | if (dml2->config.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz > 0) |
426 | p->in_states->state_array[i].dtbclk_mhz = | |
427 | dml2->config.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz; | |
7966f319 QZ |
428 | } |
429 | ||
430 | for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels; i++) { | |
431 | p->in_states->state_array[i].dispclk_mhz = | |
432 | dml2->config.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz; | |
433 | p->in_states->state_array[i].dppclk_mhz = | |
434 | dml2->config.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz; | |
435 | } | |
436 | } | |
437 | ||
438 | dml2_policy_build_synthetic_soc_states(s, p); | |
27a6c493 SP |
439 | if (dml2->v20.dml_core_ctx.project == dml_project_dcn35 || |
440 | dml2->v20.dml_core_ctx.project == dml_project_dcn351) { | |
441 | // Override last out_state with data from last in_state | |
442 | // This will ensure that out_state contains max fclk | |
443 | memcpy(&p->out_states->state_array[p->out_states->num_states - 1], | |
444 | &p->in_states->state_array[p->in_states->num_states - 1], | |
445 | sizeof(struct soc_state_bounding_box_st)); | |
446 | } | |
7966f319 QZ |
447 | } |
448 | ||
449 | void dml2_translate_ip_params(const struct dc *in, struct ip_params_st *out) | |
450 | { | |
451 | const struct _vcs_dpi_ip_params_st *in_ip_params = &in->dml.ip; | |
452 | /* Copy over the IP params tp dml2_ctx */ | |
453 | out->compressed_buffer_segment_size_in_kbytes = in_ip_params->compressed_buffer_segment_size_in_kbytes; | |
454 | out->config_return_buffer_size_in_kbytes = in_ip_params->config_return_buffer_size_in_kbytes; | |
455 | out->cursor_buffer_size = in_ip_params->cursor_buffer_size; | |
456 | out->cursor_chunk_size = in_ip_params->cursor_chunk_size; | |
457 | out->dcc_meta_buffer_size_bytes = in_ip_params->dcc_meta_buffer_size_bytes; | |
458 | out->dcc_supported = in_ip_params->dcc_supported; | |
459 | out->dispclk_delay_subtotal = in_ip_params->dispclk_delay_subtotal; | |
460 | out->dispclk_ramp_margin_percent = in_ip_params->dispclk_ramp_margin_percent; | |
461 | out->dppclk_delay_cnvc_cursor = in_ip_params->dppclk_delay_cnvc_cursor; | |
462 | out->dppclk_delay_cnvc_formatter = in_ip_params->dppclk_delay_cnvc_formatter; | |
463 | out->dppclk_delay_scl = in_ip_params->dppclk_delay_scl; | |
464 | out->dppclk_delay_scl_lb_only = in_ip_params->dppclk_delay_scl_lb_only; | |
465 | out->dppclk_delay_subtotal = in_ip_params->dppclk_delay_subtotal; | |
466 | out->dpte_buffer_size_in_pte_reqs_chroma = in_ip_params->dpte_buffer_size_in_pte_reqs_chroma; | |
467 | out->dpte_buffer_size_in_pte_reqs_luma = in_ip_params->dpte_buffer_size_in_pte_reqs_luma; | |
468 | out->dsc422_native_support = in_ip_params->dsc422_native_support; | |
469 | out->dynamic_metadata_vm_enabled = in_ip_params->dynamic_metadata_vm_enabled; | |
470 | out->gpuvm_enable = in_ip_params->gpuvm_enable; | |
471 | out->gpuvm_max_page_table_levels = in_ip_params->gpuvm_max_page_table_levels; | |
472 | out->hostvm_enable = in_ip_params->hostvm_enable; | |
473 | out->hostvm_max_page_table_levels = in_ip_params->hostvm_max_page_table_levels; | |
474 | out->line_buffer_size_bits = in_ip_params->line_buffer_size_bits; | |
475 | out->maximum_dsc_bits_per_component = in_ip_params->maximum_dsc_bits_per_component; | |
476 | out->maximum_pixels_per_line_per_dsc_unit = in_ip_params->maximum_pixels_per_line_per_dsc_unit; | |
477 | out->max_dchub_pscl_bw_pix_per_clk = in_ip_params->max_dchub_pscl_bw_pix_per_clk; | |
478 | out->max_hscl_ratio = in_ip_params->max_hscl_ratio; | |
479 | out->max_hscl_taps = in_ip_params->max_hscl_taps; | |
480 | out->max_inter_dcn_tile_repeaters = in_ip_params->max_inter_dcn_tile_repeaters; | |
481 | out->max_lb_vscl_bw_pix_per_clk = in_ip_params->max_lb_vscl_bw_pix_per_clk; | |
482 | out->max_line_buffer_lines = in_ip_params->max_line_buffer_lines; | |
483 | out->max_num_dp2p0_outputs = in_ip_params->max_num_dp2p0_outputs; | |
484 | out->max_num_dp2p0_streams = in_ip_params->max_num_dp2p0_streams; | |
485 | out->max_num_dpp = in_ip_params->max_num_dpp; | |
486 | out->max_num_hdmi_frl_outputs = in_ip_params->max_num_hdmi_frl_outputs; | |
487 | out->max_num_otg = in_ip_params->max_num_otg; | |
488 | out->max_num_wb = in_ip_params->max_num_wb; | |
489 | out->max_pscl_lb_bw_pix_per_clk = in_ip_params->max_pscl_lb_bw_pix_per_clk; | |
490 | out->max_vscl_hscl_bw_pix_per_clk = in_ip_params->max_vscl_hscl_bw_pix_per_clk; | |
491 | out->max_vscl_ratio = in_ip_params->max_vscl_ratio; | |
492 | out->max_vscl_taps = in_ip_params->max_vscl_taps; | |
493 | out->meta_chunk_size_kbytes = in_ip_params->meta_chunk_size_kbytes; | |
494 | out->meta_fifo_size_in_kentries = in_ip_params->meta_fifo_size_in_kentries; | |
495 | out->min_meta_chunk_size_bytes = in_ip_params->min_meta_chunk_size_bytes; | |
496 | out->min_pixel_chunk_size_bytes = in_ip_params->min_pixel_chunk_size_bytes; | |
497 | out->num_dsc = in_ip_params->num_dsc; | |
498 | out->pixel_chunk_size_kbytes = in_ip_params->pixel_chunk_size_kbytes; | |
499 | out->ptoi_supported = in_ip_params->ptoi_supported; | |
500 | out->rob_buffer_size_kbytes = in_ip_params->rob_buffer_size_kbytes; | |
501 | out->writeback_chunk_size_kbytes = in_ip_params->writeback_chunk_size_kbytes; | |
502 | out->writeback_interface_buffer_size_kbytes = in_ip_params->writeback_interface_buffer_size_kbytes; | |
503 | out->writeback_line_buffer_buffer_size = in_ip_params->writeback_line_buffer_buffer_size; | |
504 | out->writeback_max_hscl_ratio = in_ip_params->writeback_max_hscl_ratio; | |
505 | out->writeback_max_hscl_taps = in_ip_params->writeback_max_hscl_taps; | |
506 | out->writeback_max_vscl_ratio = in_ip_params->writeback_max_vscl_ratio; | |
507 | out->writeback_max_vscl_taps = in_ip_params->writeback_max_vscl_taps; | |
508 | out->writeback_min_hscl_ratio = in_ip_params->writeback_min_hscl_ratio; | |
509 | out->writeback_min_vscl_ratio = in_ip_params->writeback_min_vscl_ratio; | |
510 | out->zero_size_buffer_entries = in_ip_params->zero_size_buffer_entries; | |
511 | ||
512 | /* As per hardcoded reference / discussions */ | |
513 | out->config_return_buffer_segment_size_in_kbytes = 64; | |
514 | //out->vblank_nom_default_us = 600; | |
515 | out->vblank_nom_default_us = in_ip_params->VBlankNomDefaultUS; | |
516 | } | |
517 | ||
518 | void dml2_translate_socbb_params(const struct dc *in, struct soc_bounding_box_st *out) | |
519 | { | |
520 | const struct _vcs_dpi_soc_bounding_box_st *in_soc_params = &in->dml.soc; | |
521 | /* Copy over the SOCBB params to dml2_ctx */ | |
522 | out->dispclk_dppclk_vco_speed_mhz = in_soc_params->dispclk_dppclk_vco_speed_mhz; | |
523 | out->do_urgent_latency_adjustment = in_soc_params->do_urgent_latency_adjustment; | |
524 | out->dram_channel_width_bytes = (dml_uint_t)in_soc_params->dram_channel_width_bytes; | |
525 | out->fabric_datapath_to_dcn_data_return_bytes = (dml_uint_t)in_soc_params->fabric_datapath_to_dcn_data_return_bytes; | |
22136ff2 TH |
526 | out->gpuvm_min_page_size_kbytes = in_soc_params->gpuvm_min_page_size_bytes / 1024; |
527 | out->hostvm_min_page_size_kbytes = in_soc_params->hostvm_min_page_size_bytes / 1024; | |
7966f319 QZ |
528 | out->mall_allocated_for_dcn_mbytes = (dml_uint_t)in_soc_params->mall_allocated_for_dcn_mbytes; |
529 | out->max_avg_dram_bw_use_normal_percent = in_soc_params->max_avg_dram_bw_use_normal_percent; | |
530 | out->max_avg_fabric_bw_use_normal_percent = in_soc_params->max_avg_fabric_bw_use_normal_percent; | |
531 | out->max_avg_dram_bw_use_normal_strobe_percent = in_soc_params->max_avg_dram_bw_use_normal_strobe_percent; | |
532 | out->max_avg_sdp_bw_use_normal_percent = in_soc_params->max_avg_sdp_bw_use_normal_percent; | |
533 | out->max_outstanding_reqs = in_soc_params->max_request_size_bytes; | |
534 | out->num_chans = in_soc_params->num_chans; | |
535 | out->pct_ideal_dram_bw_after_urgent_strobe = in_soc_params->pct_ideal_dram_bw_after_urgent_strobe; | |
536 | out->pct_ideal_dram_bw_after_urgent_vm_only = in_soc_params->pct_ideal_dram_sdp_bw_after_urgent_vm_only; | |
537 | out->pct_ideal_fabric_bw_after_urgent = in_soc_params->pct_ideal_fabric_bw_after_urgent; | |
538 | out->pct_ideal_sdp_bw_after_urgent = in_soc_params->pct_ideal_sdp_bw_after_urgent; | |
539 | out->phy_downspread_percent = in_soc_params->downspread_percent; | |
540 | out->refclk_mhz = 50; // As per hardcoded reference. | |
541 | out->return_bus_width_bytes = in_soc_params->return_bus_width_bytes; | |
542 | out->round_trip_ping_latency_dcfclk_cycles = in_soc_params->round_trip_ping_latency_dcfclk_cycles; | |
543 | out->smn_latency_us = in_soc_params->smn_latency_us; | |
544 | out->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = in_soc_params->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes; | |
545 | out->urgent_out_of_order_return_per_channel_pixel_only_bytes = in_soc_params->urgent_out_of_order_return_per_channel_pixel_only_bytes; | |
546 | out->urgent_out_of_order_return_per_channel_vm_only_bytes = in_soc_params->urgent_out_of_order_return_per_channel_vm_only_bytes; | |
547 | out->pct_ideal_dram_bw_after_urgent_pixel_and_vm = in_soc_params->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm; | |
548 | out->pct_ideal_dram_bw_after_urgent_pixel_only = in_soc_params->pct_ideal_dram_sdp_bw_after_urgent_pixel_only; | |
549 | out->dcn_downspread_percent = in_soc_params->dcn_downspread_percent; | |
550 | } | |
551 | ||
552 | void dml2_translate_soc_states(const struct dc *dc, struct soc_states_st *out, int num_states) | |
553 | { | |
554 | unsigned int i = 0; | |
555 | out->num_states = num_states; | |
556 | ||
557 | for (i = 0; i < out->num_states; i++) { | |
558 | out->state_array[i].dcfclk_mhz = dc->dml.soc.clock_limits[i].dcfclk_mhz; | |
559 | out->state_array[i].dispclk_mhz = dc->dml.soc.clock_limits[i].dispclk_mhz; | |
560 | out->state_array[i].dppclk_mhz = dc->dml.soc.clock_limits[i].dppclk_mhz; | |
561 | out->state_array[i].dram_speed_mts = dc->dml.soc.clock_limits[i].dram_speed_mts; | |
562 | out->state_array[i].dtbclk_mhz = dc->dml.soc.clock_limits[i].dtbclk_mhz; | |
563 | out->state_array[i].socclk_mhz = dc->dml.soc.clock_limits[i].socclk_mhz; | |
564 | out->state_array[i].fabricclk_mhz = dc->dml.soc.clock_limits[i].fabricclk_mhz; | |
565 | out->state_array[i].dscclk_mhz = dc->dml.soc.clock_limits[i].dscclk_mhz; | |
566 | out->state_array[i].phyclk_d18_mhz = dc->dml.soc.clock_limits[i].phyclk_d18_mhz; | |
567 | out->state_array[i].phyclk_d32_mhz = dc->dml.soc.clock_limits[i].phyclk_d32_mhz; | |
568 | out->state_array[i].phyclk_mhz = dc->dml.soc.clock_limits[i].phyclk_mhz; | |
569 | out->state_array[i].sr_enter_plus_exit_time_us = dc->dml.soc.sr_enter_plus_exit_time_us; | |
570 | out->state_array[i].sr_exit_time_us = dc->dml.soc.sr_exit_time_us; | |
571 | out->state_array[i].fclk_change_latency_us = dc->dml.soc.fclk_change_latency_us; | |
572 | out->state_array[i].dram_clock_change_latency_us = dc->dml.soc.dram_clock_change_latency_us; | |
573 | out->state_array[i].usr_retraining_latency_us = dc->dml.soc.usr_retraining_latency_us; | |
574 | out->state_array[i].writeback_latency_us = dc->dml.soc.writeback_latency_us; | |
575 | /* Driver initialized values for these are different than the spreadsheet. Use the | |
576 | * spreadsheet ones for now. We need to decided which ones to use. | |
577 | */ | |
578 | out->state_array[i].sr_exit_z8_time_us = dc->dml.soc.sr_exit_z8_time_us; | |
579 | out->state_array[i].sr_enter_plus_exit_z8_time_us = dc->dml.soc.sr_enter_plus_exit_z8_time_us; | |
580 | //out->state_array[i].sr_exit_z8_time_us = 5.20; | |
581 | //out->state_array[i].sr_enter_plus_exit_z8_time_us = 9.60; | |
582 | out->state_array[i].use_ideal_dram_bw_strobe = true; | |
583 | out->state_array[i].urgent_latency_pixel_data_only_us = dc->dml.soc.urgent_latency_pixel_data_only_us; | |
584 | out->state_array[i].urgent_latency_pixel_mixed_with_vm_data_us = dc->dml.soc.urgent_latency_pixel_mixed_with_vm_data_us; | |
585 | out->state_array[i].urgent_latency_vm_data_only_us = dc->dml.soc.urgent_latency_vm_data_only_us; | |
586 | out->state_array[i].urgent_latency_adjustment_fabric_clock_component_us = dc->dml.soc.urgent_latency_adjustment_fabric_clock_component_us; | |
587 | out->state_array[i].urgent_latency_adjustment_fabric_clock_reference_mhz = dc->dml.soc.urgent_latency_adjustment_fabric_clock_reference_mhz; | |
588 | } | |
589 | } | |
590 | ||
591 | static void populate_dml_timing_cfg_from_stream_state(struct dml_timing_cfg_st *out, unsigned int location, const struct dc_stream_state *in) | |
592 | { | |
593 | dml_uint_t hblank_start, vblank_start; | |
594 | ||
595 | out->HActive[location] = in->timing.h_addressable + in->timing.h_border_left + in->timing.h_border_right; | |
596 | out->VActive[location] = in->timing.v_addressable + in->timing.v_border_bottom + in->timing.v_border_top; | |
597 | out->RefreshRate[location] = ((in->timing.pix_clk_100hz * 100) / in->timing.h_total) / in->timing.v_total; | |
598 | out->VFrontPorch[location] = in->timing.v_front_porch; | |
599 | out->PixelClock[location] = in->timing.pix_clk_100hz / 10000.00; | |
2a6a491d SJK |
600 | if (in->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) |
601 | out->PixelClock[location] *= 2; | |
7966f319 QZ |
602 | out->HTotal[location] = in->timing.h_total; |
603 | out->VTotal[location] = in->timing.v_total; | |
604 | out->Interlace[location] = in->timing.flags.INTERLACE; | |
605 | hblank_start = in->timing.h_total - in->timing.h_front_porch; | |
606 | out->HBlankEnd[location] = hblank_start | |
607 | - in->timing.h_addressable | |
608 | - in->timing.h_border_left | |
609 | - in->timing.h_border_right; | |
610 | vblank_start = in->timing.v_total - in->timing.v_front_porch; | |
611 | out->VBlankEnd[location] = vblank_start | |
612 | - in->timing.v_addressable | |
613 | - in->timing.v_border_top | |
614 | - in->timing.v_border_bottom; | |
615 | out->DRRDisplay[location] = false; | |
616 | } | |
617 | ||
618 | static void populate_dml_output_cfg_from_stream_state(struct dml_output_cfg_st *out, unsigned int location, | |
619 | const struct dc_stream_state *in, const struct pipe_ctx *pipe) | |
620 | { | |
621 | unsigned int output_bpc; | |
622 | ||
623 | out->DSCEnable[location] = (enum dml_dsc_enable)in->timing.flags.DSC; | |
624 | out->OutputLinkDPLanes[location] = 4; // As per code in dcn20_resource.c | |
625 | out->DSCInputBitPerComponent[location] = 12; // As per code in dcn20_resource.c | |
626 | ||
627 | switch (in->signal) { | |
628 | case SIGNAL_TYPE_DISPLAY_PORT_MST: | |
629 | case SIGNAL_TYPE_DISPLAY_PORT: | |
630 | out->OutputEncoder[location] = dml_dp; | |
631 | if (is_dp2p0_output_encoder(pipe)) | |
632 | out->OutputEncoder[location] = dml_dp2p0; | |
633 | break; | |
7966f319 | 634 | case SIGNAL_TYPE_EDP: |
05638ff6 | 635 | out->OutputEncoder[location] = dml_edp; |
7966f319 QZ |
636 | break; |
637 | case SIGNAL_TYPE_HDMI_TYPE_A: | |
638 | case SIGNAL_TYPE_DVI_SINGLE_LINK: | |
639 | case SIGNAL_TYPE_DVI_DUAL_LINK: | |
640 | out->OutputEncoder[location] = dml_hdmi; | |
641 | break; | |
642 | default: | |
643 | out->OutputEncoder[location] = dml_dp; | |
644 | } | |
645 | ||
646 | switch (in->timing.display_color_depth) { | |
647 | case COLOR_DEPTH_666: | |
648 | output_bpc = 6; | |
649 | break; | |
650 | case COLOR_DEPTH_888: | |
651 | output_bpc = 8; | |
652 | break; | |
653 | case COLOR_DEPTH_101010: | |
654 | output_bpc = 10; | |
655 | break; | |
656 | case COLOR_DEPTH_121212: | |
657 | output_bpc = 12; | |
658 | break; | |
659 | case COLOR_DEPTH_141414: | |
660 | output_bpc = 14; | |
661 | break; | |
662 | case COLOR_DEPTH_161616: | |
663 | output_bpc = 16; | |
664 | break; | |
665 | case COLOR_DEPTH_999: | |
666 | output_bpc = 9; | |
667 | break; | |
668 | case COLOR_DEPTH_111111: | |
669 | output_bpc = 11; | |
670 | break; | |
671 | default: | |
672 | output_bpc = 8; | |
673 | break; | |
674 | } | |
675 | ||
676 | switch (in->timing.pixel_encoding) { | |
677 | case PIXEL_ENCODING_RGB: | |
678 | case PIXEL_ENCODING_YCBCR444: | |
679 | out->OutputFormat[location] = dml_444; | |
680 | out->OutputBpp[location] = (dml_float_t)output_bpc * 3; | |
681 | break; | |
682 | case PIXEL_ENCODING_YCBCR420: | |
683 | out->OutputFormat[location] = dml_420; | |
684 | out->OutputBpp[location] = (output_bpc * 3.0) / 2; | |
685 | break; | |
686 | case PIXEL_ENCODING_YCBCR422: | |
687 | if (in->timing.flags.DSC && !in->timing.dsc_cfg.ycbcr422_simple) | |
688 | out->OutputFormat[location] = dml_n422; | |
689 | else | |
690 | out->OutputFormat[location] = dml_s422; | |
691 | out->OutputBpp[location] = (dml_float_t)output_bpc * 2; | |
692 | break; | |
693 | default: | |
694 | out->OutputFormat[location] = dml_444; | |
695 | out->OutputBpp[location] = (dml_float_t)output_bpc * 3; | |
696 | break; | |
697 | } | |
698 | ||
699 | if (in->timing.flags.DSC) { | |
700 | out->OutputBpp[location] = in->timing.dsc_cfg.bits_per_pixel / 16.0; | |
701 | } | |
702 | ||
703 | // This has been false throughout DCN32x development. If needed we can change this later on. | |
704 | out->OutputMultistreamEn[location] = false; | |
705 | ||
706 | switch (in->signal) { | |
707 | case SIGNAL_TYPE_NONE: | |
708 | case SIGNAL_TYPE_DVI_SINGLE_LINK: | |
709 | case SIGNAL_TYPE_DVI_DUAL_LINK: | |
710 | case SIGNAL_TYPE_HDMI_TYPE_A: | |
711 | case SIGNAL_TYPE_LVDS: | |
712 | case SIGNAL_TYPE_RGB: | |
713 | case SIGNAL_TYPE_DISPLAY_PORT: | |
714 | case SIGNAL_TYPE_DISPLAY_PORT_MST: | |
715 | case SIGNAL_TYPE_EDP: | |
716 | case SIGNAL_TYPE_VIRTUAL: | |
717 | default: | |
718 | out->OutputLinkDPRate[location] = dml_dp_rate_na; | |
719 | break; | |
720 | } | |
721 | ||
722 | out->PixelClockBackEnd[location] = in->timing.pix_clk_100hz / 10000.00; | |
723 | ||
724 | out->AudioSampleLayout[location] = in->audio_info.modes->sample_size; | |
725 | out->AudioSampleRate[location] = in->audio_info.modes->max_bit_rate; | |
726 | ||
727 | out->OutputDisabled[location] = true; | |
728 | } | |
729 | ||
730 | static void populate_dummy_dml_surface_cfg(struct dml_surface_cfg_st *out, unsigned int location, const struct dc_stream_state *in) | |
731 | { | |
732 | out->SurfaceWidthY[location] = in->timing.h_addressable; | |
733 | out->SurfaceHeightY[location] = in->timing.v_addressable; | |
734 | out->SurfaceWidthC[location] = in->timing.h_addressable; | |
735 | out->SurfaceHeightC[location] = in->timing.v_addressable; | |
736 | out->PitchY[location] = ((out->SurfaceWidthY[location] + 127) / 128) * 128; | |
737 | out->PitchC[location] = 0; | |
738 | out->DCCEnable[location] = false; | |
739 | out->DCCMetaPitchY[location] = 0; | |
740 | out->DCCMetaPitchC[location] = 0; | |
741 | out->DCCRateLuma[location] = 1.0; | |
742 | out->DCCRateChroma[location] = 1.0; | |
743 | out->DCCFractionOfZeroSizeRequestsLuma[location] = 0; | |
744 | out->DCCFractionOfZeroSizeRequestsChroma[location] = 0; | |
745 | out->SurfaceTiling[location] = dml_sw_64kb_r_x; | |
746 | out->SourcePixelFormat[location] = dml_444_32; | |
747 | } | |
748 | ||
749 | static void populate_dml_surface_cfg_from_plane_state(enum dml_project_id dml2_project, struct dml_surface_cfg_st *out, unsigned int location, const struct dc_plane_state *in) | |
750 | { | |
751 | out->PitchY[location] = in->plane_size.surface_pitch; | |
752 | out->SurfaceHeightY[location] = in->plane_size.surface_size.height; | |
753 | out->SurfaceWidthY[location] = in->plane_size.surface_size.width; | |
969fe903 SJK |
754 | out->SurfaceHeightC[location] = in->plane_size.chroma_size.height; |
755 | out->SurfaceWidthC[location] = in->plane_size.chroma_size.width; | |
7966f319 QZ |
756 | out->PitchC[location] = in->plane_size.chroma_pitch; |
757 | out->DCCEnable[location] = in->dcc.enable; | |
758 | out->DCCMetaPitchY[location] = in->dcc.meta_pitch; | |
759 | out->DCCMetaPitchC[location] = in->dcc.meta_pitch_c; | |
760 | out->DCCRateLuma[location] = 1.0; | |
761 | out->DCCRateChroma[location] = 1.0; | |
762 | out->DCCFractionOfZeroSizeRequestsLuma[location] = in->dcc.independent_64b_blks; | |
763 | out->DCCFractionOfZeroSizeRequestsChroma[location] = in->dcc.independent_64b_blks_c; | |
764 | ||
765 | switch (dml2_project) { | |
766 | default: | |
767 | out->SurfaceTiling[location] = (enum dml_swizzle_mode)in->tiling_info.gfx9.swizzle; | |
768 | break; | |
769 | } | |
770 | ||
771 | switch (in->format) { | |
772 | case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: | |
773 | case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: | |
774 | out->SourcePixelFormat[location] = dml_420_8; | |
775 | break; | |
776 | case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: | |
777 | case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: | |
778 | out->SourcePixelFormat[location] = dml_420_10; | |
779 | break; | |
780 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: | |
781 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: | |
782 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: | |
783 | out->SourcePixelFormat[location] = dml_444_64; | |
784 | break; | |
785 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: | |
786 | case SURFACE_PIXEL_FORMAT_GRPH_RGB565: | |
787 | out->SourcePixelFormat[location] = dml_444_16; | |
788 | break; | |
789 | case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: | |
790 | out->SourcePixelFormat[location] = dml_444_8; | |
791 | break; | |
792 | case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: | |
793 | out->SourcePixelFormat[location] = dml_rgbe_alpha; | |
794 | break; | |
795 | default: | |
796 | out->SourcePixelFormat[location] = dml_444_32; | |
797 | break; | |
798 | } | |
799 | } | |
800 | ||
faf51b20 | 801 | static struct scaler_data get_scaler_data_for_plane(const struct dc_plane_state *in, struct dc_state *context) |
7966f319 QZ |
802 | { |
803 | int i; | |
faf51b20 FZ |
804 | struct pipe_ctx *temp_pipe = &context->res_ctx.temp_pipe; |
805 | ||
806 | memset(temp_pipe, 0, sizeof(struct pipe_ctx)); | |
7966f319 QZ |
807 | |
808 | for (i = 0; i < MAX_PIPES; i++) { | |
809 | const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |
810 | ||
811 | if (pipe->plane_state == in && !pipe->prev_odm_pipe) { | |
faf51b20 FZ |
812 | temp_pipe->stream = pipe->stream; |
813 | temp_pipe->plane_state = pipe->plane_state; | |
814 | temp_pipe->plane_res.scl_data.taps = pipe->plane_res.scl_data.taps; | |
815 | ||
816 | resource_build_scaling_params(temp_pipe); | |
7966f319 QZ |
817 | break; |
818 | } | |
819 | } | |
820 | ||
821 | ASSERT(i < MAX_PIPES); | |
faf51b20 | 822 | return temp_pipe->plane_res.scl_data; |
7966f319 QZ |
823 | } |
824 | ||
825 | static void populate_dummy_dml_plane_cfg(struct dml_plane_cfg_st *out, unsigned int location, const struct dc_stream_state *in) | |
826 | { | |
827 | out->CursorBPP[location] = dml_cur_32bit; | |
828 | out->CursorWidth[location] = 256; | |
829 | ||
830 | out->GPUVMMinPageSizeKBytes[location] = 256; | |
831 | ||
832 | out->ViewportWidth[location] = in->timing.h_addressable; | |
833 | out->ViewportHeight[location] = in->timing.v_addressable; | |
834 | out->ViewportStationary[location] = false; | |
835 | out->ViewportWidthChroma[location] = 0; | |
836 | out->ViewportHeightChroma[location] = 0; | |
837 | out->ViewportXStart[location] = 0; | |
838 | out->ViewportXStartC[location] = 0; | |
839 | out->ViewportYStart[location] = 0; | |
840 | out->ViewportYStartC[location] = 0; | |
841 | ||
842 | out->ScalerEnabled[location] = false; | |
843 | out->HRatio[location] = 1.0; | |
844 | out->VRatio[location] = 1.0; | |
845 | out->HRatioChroma[location] = 0; | |
846 | out->VRatioChroma[location] = 0; | |
847 | out->HTaps[location] = 1; | |
848 | out->VTaps[location] = 1; | |
849 | out->HTapsChroma[location] = 0; | |
850 | out->VTapsChroma[location] = 0; | |
851 | out->SourceScan[location] = dml_rotation_0; | |
852 | out->ScalerRecoutWidth[location] = in->timing.h_addressable; | |
853 | ||
854 | out->LBBitPerPixel[location] = 57; | |
855 | ||
856 | out->DynamicMetadataEnable[location] = false; | |
857 | ||
858 | out->NumberOfCursors[location] = 1; | |
859 | out->UseMALLForStaticScreen[location] = dml_use_mall_static_screen_disable; | |
860 | out->UseMALLForPStateChange[location] = dml_use_mall_pstate_change_disable; | |
861 | ||
862 | out->DETSizeOverride[location] = 256; | |
863 | ||
864 | out->ScalerEnabled[location] = false; | |
865 | } | |
866 | ||
faf51b20 | 867 | static void populate_dml_plane_cfg_from_plane_state(struct dml_plane_cfg_st *out, unsigned int location, const struct dc_plane_state *in, struct dc_state *context) |
7966f319 QZ |
868 | { |
869 | const struct scaler_data scaler_data = get_scaler_data_for_plane(in, context); | |
870 | ||
871 | out->CursorBPP[location] = dml_cur_32bit; | |
872 | out->CursorWidth[location] = 256; | |
873 | ||
874 | out->GPUVMMinPageSizeKBytes[location] = 256; | |
875 | ||
876 | out->ViewportWidth[location] = scaler_data.viewport.width; | |
877 | out->ViewportHeight[location] = scaler_data.viewport.height; | |
878 | out->ViewportWidthChroma[location] = scaler_data.viewport_c.width; | |
879 | out->ViewportHeightChroma[location] = scaler_data.viewport_c.height; | |
880 | out->ViewportXStart[location] = scaler_data.viewport.x; | |
881 | out->ViewportYStart[location] = scaler_data.viewport.y; | |
882 | out->ViewportXStartC[location] = scaler_data.viewport_c.x; | |
883 | out->ViewportYStartC[location] = scaler_data.viewport_c.y; | |
884 | out->ViewportStationary[location] = false; | |
885 | ||
886 | out->ScalerEnabled[location] = scaler_data.ratios.horz.value != dc_fixpt_one.value || | |
887 | scaler_data.ratios.horz_c.value != dc_fixpt_one.value || | |
888 | scaler_data.ratios.vert.value != dc_fixpt_one.value || | |
889 | scaler_data.ratios.vert_c.value != dc_fixpt_one.value; | |
890 | ||
891 | /* Current driver code base uses LBBitPerPixel as 57. There is a discrepancy | |
892 | * from the HW/DML teams about this value. Initialize LBBitPerPixel with the | |
893 | * value current used in Navi3x . | |
894 | */ | |
895 | ||
896 | out->LBBitPerPixel[location] = 57; | |
897 | ||
898 | if (out->ScalerEnabled[location] == false) { | |
899 | out->HRatio[location] = 1; | |
900 | out->HRatioChroma[location] = 1; | |
901 | out->VRatio[location] = 1; | |
902 | out->VRatioChroma[location] = 1; | |
903 | } else { | |
904 | /* Follow the original dml_wrapper.c code direction to fix scaling issues */ | |
905 | out->HRatio[location] = (dml_float_t)scaler_data.ratios.horz.value / (1ULL << 32); | |
906 | out->HRatioChroma[location] = (dml_float_t)scaler_data.ratios.horz_c.value / (1ULL << 32); | |
907 | out->VRatio[location] = (dml_float_t)scaler_data.ratios.vert.value / (1ULL << 32); | |
908 | out->VRatioChroma[location] = (dml_float_t)scaler_data.ratios.vert_c.value / (1ULL << 32); | |
909 | } | |
910 | ||
911 | if (!scaler_data.taps.h_taps) { | |
912 | out->HTaps[location] = 1; | |
913 | out->HTapsChroma[location] = 1; | |
914 | } else { | |
915 | out->HTaps[location] = scaler_data.taps.h_taps; | |
916 | out->HTapsChroma[location] = scaler_data.taps.h_taps_c; | |
917 | } | |
918 | if (!scaler_data.taps.v_taps) { | |
919 | out->VTaps[location] = 1; | |
920 | out->VTapsChroma[location] = 1; | |
921 | } else { | |
922 | out->VTaps[location] = scaler_data.taps.v_taps; | |
923 | out->VTapsChroma[location] = scaler_data.taps.v_taps_c; | |
924 | } | |
925 | ||
926 | out->SourceScan[location] = (enum dml_rotation_angle)in->rotation; | |
927 | out->ScalerRecoutWidth[location] = in->dst_rect.width; | |
928 | ||
929 | out->DynamicMetadataEnable[location] = false; | |
930 | out->DynamicMetadataLinesBeforeActiveRequired[location] = 0; | |
931 | out->DynamicMetadataTransmittedBytes[location] = 0; | |
932 | ||
933 | out->NumberOfCursors[location] = 1; | |
934 | } | |
935 | ||
936 | static unsigned int map_stream_to_dml_display_cfg(const struct dml2_context *dml2, | |
937 | const struct dc_stream_state *stream, const struct dml_display_cfg_st *dml_dispcfg) | |
938 | { | |
939 | int i = 0; | |
940 | int location = -1; | |
941 | ||
942 | for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { | |
943 | if (dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[i] && dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[i] == stream->stream_id) { | |
944 | location = i; | |
945 | break; | |
946 | } | |
947 | } | |
948 | ||
949 | return location; | |
950 | } | |
951 | ||
35c1d966 SJK |
952 | static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *context, const struct dc_plane_state *plane, |
953 | unsigned int stream_id, unsigned int plane_index, unsigned int *plane_id) | |
7966f319 QZ |
954 | { |
955 | int i, j; | |
35c1d966 | 956 | bool is_plane_duplicate = dml2->v20.scratch.plane_duplicate_exists; |
7966f319 QZ |
957 | |
958 | if (!plane_id) | |
959 | return false; | |
960 | ||
961 | for (i = 0; i < context->stream_count; i++) { | |
e47d7ca7 SJK |
962 | if (context->streams[i]->stream_id == stream_id) { |
963 | for (j = 0; j < context->stream_status[i].plane_count; j++) { | |
35c1d966 SJK |
964 | if (context->stream_status[i].plane_states[j] == plane && |
965 | (!is_plane_duplicate || (is_plane_duplicate && (j == plane_index)))) { | |
e47d7ca7 SJK |
966 | *plane_id = (i << 16) | j; |
967 | return true; | |
968 | } | |
7966f319 QZ |
969 | } |
970 | } | |
971 | } | |
972 | ||
973 | return false; | |
974 | } | |
975 | ||
e47d7ca7 | 976 | static unsigned int map_plane_to_dml_display_cfg(const struct dml2_context *dml2, const struct dc_plane_state *plane, |
35c1d966 | 977 | const struct dc_state *context, const struct dml_display_cfg_st *dml_dispcfg, unsigned int stream_id, int plane_index) |
7966f319 QZ |
978 | { |
979 | unsigned int plane_id; | |
980 | int i = 0; | |
981 | int location = -1; | |
982 | ||
35c1d966 | 983 | if (!get_plane_id(context->bw_ctx.dml2, context, plane, stream_id, plane_index, &plane_id)) { |
7966f319 QZ |
984 | ASSERT(false); |
985 | return -1; | |
986 | } | |
987 | ||
988 | for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { | |
989 | if (dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[i] && dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[i] == plane_id) { | |
990 | location = i; | |
991 | break; | |
992 | } | |
993 | } | |
994 | ||
995 | return location; | |
996 | } | |
997 | ||
998 | static void apply_legacy_svp_drr_settings(struct dml2_context *dml2, const struct dc_state *state, struct dml_display_cfg_st *dml_dispcfg) | |
999 | { | |
1000 | int i; | |
1001 | ||
1002 | if (state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { | |
1003 | ASSERT(state->stream_count == 1); | |
1004 | dml_dispcfg->timing.DRRDisplay[0] = true; | |
1005 | } else if (state->bw_ctx.bw.dcn.legacy_svp_drr_stream_index_valid) { | |
1006 | ||
1007 | for (i = 0; i < dml_dispcfg->num_timings; i++) { | |
1008 | if (dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[i] == state->streams[state->bw_ctx.bw.dcn.legacy_svp_drr_stream_index]->stream_id) | |
1009 | dml_dispcfg->timing.DRRDisplay[i] = true; | |
1010 | } | |
1011 | } | |
1012 | } | |
1013 | ||
35c1d966 SJK |
1014 | static void dml2_populate_pipe_to_plane_index_mapping(struct dml2_context *dml2, struct dc_state *state) |
1015 | { | |
1016 | unsigned int i; | |
1017 | unsigned int pipe_index = 0; | |
1018 | unsigned int plane_index = 0; | |
1019 | struct dml2_dml_to_dc_pipe_mapping *dml_to_dc_pipe_mapping = &dml2->v20.scratch.dml_to_dc_pipe_mapping; | |
1020 | ||
1021 | for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { | |
1022 | dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid[i] = false; | |
1023 | dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index[i] = 0; | |
1024 | } | |
1025 | ||
1026 | for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { | |
1027 | struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i]; | |
1028 | ||
1029 | if (!pipe || !pipe->stream || !pipe->plane_state) | |
1030 | continue; | |
1031 | ||
1032 | while (pipe) { | |
1033 | pipe_index = pipe->pipe_idx; | |
1034 | ||
1035 | if (pipe->stream && dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid[pipe_index] == false) { | |
1036 | dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index[pipe_index] = plane_index; | |
1037 | plane_index++; | |
1038 | dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid[pipe_index] = true; | |
1039 | } | |
1040 | ||
1041 | pipe = pipe->bottom_pipe; | |
1042 | } | |
1043 | ||
1044 | plane_index = 0; | |
1045 | } | |
1046 | } | |
1047 | ||
1048 | void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_state *context, struct dml_display_cfg_st *dml_dispcfg) | |
7966f319 | 1049 | { |
9ade4870 | 1050 | int i = 0, j = 0, k = 0; |
7966f319 | 1051 | int disp_cfg_stream_location, disp_cfg_plane_location; |
09a4ec5d | 1052 | enum mall_stream_type stream_mall_type; |
9ade4870 | 1053 | struct pipe_ctx *current_pipe_context; |
7966f319 QZ |
1054 | |
1055 | for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { | |
1056 | dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[i] = false; | |
1057 | dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[i] = false; | |
1058 | dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[i] = false; | |
1059 | dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[i] = false; | |
1060 | } | |
1061 | ||
1062 | //Generally these are set by referencing our latest BB/IP params in dcn32_resource.c file | |
33a6e409 TH |
1063 | dml_dispcfg->plane.GPUVMEnable = dml2->v20.dml_core_ctx.ip.gpuvm_enable; |
1064 | dml_dispcfg->plane.GPUVMMaxPageTableLevels = dml2->v20.dml_core_ctx.ip.gpuvm_max_page_table_levels; | |
1065 | dml_dispcfg->plane.HostVMEnable = dml2->v20.dml_core_ctx.ip.hostvm_enable; | |
1066 | dml_dispcfg->plane.HostVMMaxPageTableLevels = dml2->v20.dml_core_ctx.ip.hostvm_max_page_table_levels; | |
1067 | if (dml2->v20.dml_core_ctx.ip.hostvm_enable) | |
1068 | dml2->v20.dml_core_ctx.policy.AllowForPStateChangeOrStutterInVBlankFinal = dml_prefetch_support_uclk_fclk_and_stutter; | |
7966f319 | 1069 | |
35c1d966 SJK |
1070 | dml2_populate_pipe_to_plane_index_mapping(dml2, context); |
1071 | ||
7966f319 | 1072 | for (i = 0; i < context->stream_count; i++) { |
9ade4870 GT |
1073 | current_pipe_context = NULL; |
1074 | for (k = 0; k < MAX_PIPES; k++) { | |
1075 | /* find one pipe allocated to this stream for the purpose of getting | |
1076 | info about the link later */ | |
1077 | if (context->streams[i] == context->res_ctx.pipe_ctx[k].stream) { | |
1078 | current_pipe_context = &context->res_ctx.pipe_ctx[k]; | |
1079 | break; | |
1080 | } | |
1081 | } | |
7966f319 | 1082 | disp_cfg_stream_location = map_stream_to_dml_display_cfg(dml2, context->streams[i], dml_dispcfg); |
09a4ec5d | 1083 | stream_mall_type = dc_state_get_stream_subvp_type(context, context->streams[i]); |
7966f319 QZ |
1084 | |
1085 | if (disp_cfg_stream_location < 0) | |
1086 | disp_cfg_stream_location = dml_dispcfg->num_timings++; | |
1087 | ||
1088 | ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__); | |
1089 | ||
1090 | populate_dml_timing_cfg_from_stream_state(&dml_dispcfg->timing, disp_cfg_stream_location, context->streams[i]); | |
9ade4870 | 1091 | populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output, disp_cfg_stream_location, context->streams[i], current_pipe_context); |
7966f319 QZ |
1092 | switch (context->streams[i]->debug.force_odm_combine_segments) { |
1093 | case 2: | |
1094 | dml2->v20.dml_core_ctx.policy.ODMUse[disp_cfg_stream_location] = dml_odm_use_policy_combine_2to1; | |
1095 | break; | |
1096 | case 4: | |
1097 | dml2->v20.dml_core_ctx.policy.ODMUse[disp_cfg_stream_location] = dml_odm_use_policy_combine_4to1; | |
1098 | break; | |
1099 | default: | |
1100 | break; | |
1101 | } | |
1102 | ||
1103 | dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[disp_cfg_stream_location] = context->streams[i]->stream_id; | |
1104 | dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[disp_cfg_stream_location] = true; | |
1105 | ||
1106 | if (context->stream_status[i].plane_count == 0) { | |
1107 | disp_cfg_plane_location = dml_dispcfg->num_surfaces++; | |
1108 | ||
1109 | populate_dummy_dml_surface_cfg(&dml_dispcfg->surface, disp_cfg_plane_location, context->streams[i]); | |
1110 | populate_dummy_dml_plane_cfg(&dml_dispcfg->plane, disp_cfg_plane_location, context->streams[i]); | |
1111 | ||
1112 | dml_dispcfg->plane.BlendingAndTiming[disp_cfg_plane_location] = disp_cfg_stream_location; | |
1113 | ||
1114 | dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[disp_cfg_plane_location] = true; | |
1115 | } else { | |
1116 | for (j = 0; j < context->stream_status[i].plane_count; j++) { | |
e47d7ca7 | 1117 | disp_cfg_plane_location = map_plane_to_dml_display_cfg(dml2, |
35c1d966 | 1118 | context->stream_status[i].plane_states[j], context, dml_dispcfg, context->streams[i]->stream_id, j); |
7966f319 QZ |
1119 | |
1120 | if (disp_cfg_plane_location < 0) | |
1121 | disp_cfg_plane_location = dml_dispcfg->num_surfaces++; | |
1122 | ||
1123 | ASSERT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__); | |
1124 | ||
1125 | populate_dml_surface_cfg_from_plane_state(dml2->v20.dml_core_ctx.project, &dml_dispcfg->surface, disp_cfg_plane_location, context->stream_status[i].plane_states[j]); | |
1126 | populate_dml_plane_cfg_from_plane_state(&dml_dispcfg->plane, disp_cfg_plane_location, context->stream_status[i].plane_states[j], context); | |
1127 | ||
09a4ec5d | 1128 | if (stream_mall_type == SUBVP_MAIN) { |
7966f319 QZ |
1129 | dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_sub_viewport; |
1130 | dml_dispcfg->plane.UseMALLForStaticScreen[disp_cfg_plane_location] = dml_use_mall_static_screen_optimize; | |
09a4ec5d | 1131 | } else if (stream_mall_type == SUBVP_PHANTOM) { |
7966f319 QZ |
1132 | dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_phantom_pipe; |
1133 | dml_dispcfg->plane.UseMALLForStaticScreen[disp_cfg_plane_location] = dml_use_mall_static_screen_disable; | |
1134 | dml2->v20.dml_core_ctx.policy.ImmediateFlipRequirement[disp_cfg_plane_location] = dml_immediate_flip_not_required; | |
1135 | } else { | |
1136 | dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_disable; | |
1137 | dml_dispcfg->plane.UseMALLForStaticScreen[disp_cfg_plane_location] = dml_use_mall_static_screen_optimize; | |
1138 | } | |
1139 | ||
1140 | dml_dispcfg->plane.BlendingAndTiming[disp_cfg_plane_location] = disp_cfg_stream_location; | |
1141 | ||
35c1d966 | 1142 | if (get_plane_id(dml2, context, context->stream_status[i].plane_states[j], context->streams[i]->stream_id, j, |
e47d7ca7 | 1143 | &dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[disp_cfg_plane_location])) |
7966f319 QZ |
1144 | dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[disp_cfg_plane_location] = true; |
1145 | ||
1146 | if (j >= 1) { | |
1147 | populate_dml_timing_cfg_from_stream_state(&dml_dispcfg->timing, disp_cfg_plane_location, context->streams[i]); | |
9ade4870 | 1148 | populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output, disp_cfg_plane_location, context->streams[i], current_pipe_context); |
7966f319 QZ |
1149 | switch (context->streams[i]->debug.force_odm_combine_segments) { |
1150 | case 2: | |
1151 | dml2->v20.dml_core_ctx.policy.ODMUse[disp_cfg_plane_location] = dml_odm_use_policy_combine_2to1; | |
1152 | break; | |
1153 | case 4: | |
1154 | dml2->v20.dml_core_ctx.policy.ODMUse[disp_cfg_plane_location] = dml_odm_use_policy_combine_4to1; | |
1155 | break; | |
1156 | default: | |
1157 | break; | |
1158 | } | |
1159 | ||
09a4ec5d | 1160 | if (stream_mall_type == SUBVP_MAIN) |
7966f319 | 1161 | dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_sub_viewport; |
09a4ec5d | 1162 | else if (stream_mall_type == SUBVP_PHANTOM) |
7966f319 QZ |
1163 | dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_phantom_pipe; |
1164 | ||
1165 | dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[disp_cfg_plane_location] = context->streams[i]->stream_id; | |
1166 | dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[disp_cfg_plane_location] = true; | |
1167 | ||
1168 | dml_dispcfg->num_timings++; | |
1169 | } | |
1170 | } | |
1171 | } | |
1172 | } | |
1173 | ||
1174 | if (!dml2->config.use_native_pstate_optimization) | |
1175 | apply_legacy_svp_drr_settings(dml2, context, dml_dispcfg); | |
1176 | } | |
1177 | ||
1178 | void dml2_update_pipe_ctx_dchub_regs(struct _vcs_dpi_dml_display_rq_regs_st *rq_regs, | |
1179 | struct _vcs_dpi_dml_display_dlg_regs_st *disp_dlg_regs, | |
1180 | struct _vcs_dpi_dml_display_ttu_regs_st *disp_ttu_regs, | |
1181 | struct pipe_ctx *out) | |
1182 | { | |
1183 | memset(&out->rq_regs, 0, sizeof(out->rq_regs)); | |
1184 | out->rq_regs.rq_regs_l.chunk_size = rq_regs->rq_regs_l.chunk_size; | |
1185 | out->rq_regs.rq_regs_l.min_chunk_size = rq_regs->rq_regs_l.min_chunk_size; | |
1186 | out->rq_regs.rq_regs_l.meta_chunk_size = rq_regs->rq_regs_l.meta_chunk_size; | |
1187 | out->rq_regs.rq_regs_l.min_meta_chunk_size = rq_regs->rq_regs_l.min_meta_chunk_size; | |
1188 | out->rq_regs.rq_regs_l.dpte_group_size = rq_regs->rq_regs_l.dpte_group_size; | |
1189 | out->rq_regs.rq_regs_l.mpte_group_size = rq_regs->rq_regs_l.mpte_group_size; | |
1190 | out->rq_regs.rq_regs_l.swath_height = rq_regs->rq_regs_l.swath_height; | |
1191 | out->rq_regs.rq_regs_l.pte_row_height_linear = rq_regs->rq_regs_l.pte_row_height_linear; | |
1192 | ||
1193 | out->rq_regs.rq_regs_c.chunk_size = rq_regs->rq_regs_c.chunk_size; | |
1194 | out->rq_regs.rq_regs_c.min_chunk_size = rq_regs->rq_regs_c.min_chunk_size; | |
1195 | out->rq_regs.rq_regs_c.meta_chunk_size = rq_regs->rq_regs_c.meta_chunk_size; | |
1196 | out->rq_regs.rq_regs_c.min_meta_chunk_size = rq_regs->rq_regs_c.min_meta_chunk_size; | |
1197 | out->rq_regs.rq_regs_c.dpte_group_size = rq_regs->rq_regs_c.dpte_group_size; | |
1198 | out->rq_regs.rq_regs_c.mpte_group_size = rq_regs->rq_regs_c.mpte_group_size; | |
1199 | out->rq_regs.rq_regs_c.swath_height = rq_regs->rq_regs_c.swath_height; | |
1200 | out->rq_regs.rq_regs_c.pte_row_height_linear = rq_regs->rq_regs_c.pte_row_height_linear; | |
1201 | ||
1202 | out->rq_regs.drq_expansion_mode = rq_regs->drq_expansion_mode; | |
1203 | out->rq_regs.prq_expansion_mode = rq_regs->prq_expansion_mode; | |
1204 | out->rq_regs.mrq_expansion_mode = rq_regs->mrq_expansion_mode; | |
1205 | out->rq_regs.crq_expansion_mode = rq_regs->crq_expansion_mode; | |
1206 | out->rq_regs.plane1_base_address = rq_regs->plane1_base_address; | |
1207 | ||
1208 | memset(&out->dlg_regs, 0, sizeof(out->dlg_regs)); | |
1209 | out->dlg_regs.refcyc_h_blank_end = disp_dlg_regs->refcyc_h_blank_end; | |
1210 | out->dlg_regs.dlg_vblank_end = disp_dlg_regs->dlg_vblank_end; | |
1211 | out->dlg_regs.min_dst_y_next_start = disp_dlg_regs->min_dst_y_next_start; | |
1212 | out->dlg_regs.refcyc_per_htotal = disp_dlg_regs->refcyc_per_htotal; | |
1213 | out->dlg_regs.refcyc_x_after_scaler = disp_dlg_regs->refcyc_x_after_scaler; | |
1214 | out->dlg_regs.dst_y_after_scaler = disp_dlg_regs->dst_y_after_scaler; | |
1215 | out->dlg_regs.dst_y_prefetch = disp_dlg_regs->dst_y_prefetch; | |
1216 | out->dlg_regs.dst_y_per_vm_vblank = disp_dlg_regs->dst_y_per_vm_vblank; | |
1217 | out->dlg_regs.dst_y_per_row_vblank = disp_dlg_regs->dst_y_per_row_vblank; | |
1218 | out->dlg_regs.dst_y_per_vm_flip = disp_dlg_regs->dst_y_per_vm_flip; | |
1219 | out->dlg_regs.dst_y_per_row_flip = disp_dlg_regs->dst_y_per_row_flip; | |
1220 | out->dlg_regs.ref_freq_to_pix_freq = disp_dlg_regs->ref_freq_to_pix_freq; | |
1221 | out->dlg_regs.vratio_prefetch = disp_dlg_regs->vratio_prefetch; | |
1222 | out->dlg_regs.vratio_prefetch_c = disp_dlg_regs->vratio_prefetch_c; | |
1223 | out->dlg_regs.refcyc_per_pte_group_vblank_l = disp_dlg_regs->refcyc_per_pte_group_vblank_l; | |
1224 | out->dlg_regs.refcyc_per_pte_group_vblank_c = disp_dlg_regs->refcyc_per_pte_group_vblank_c; | |
1225 | out->dlg_regs.refcyc_per_meta_chunk_vblank_l = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; | |
1226 | out->dlg_regs.refcyc_per_meta_chunk_vblank_c = disp_dlg_regs->refcyc_per_meta_chunk_vblank_c; | |
1227 | out->dlg_regs.refcyc_per_pte_group_flip_l = disp_dlg_regs->refcyc_per_pte_group_flip_l; | |
1228 | out->dlg_regs.refcyc_per_pte_group_flip_c = disp_dlg_regs->refcyc_per_pte_group_flip_c; | |
1229 | out->dlg_regs.refcyc_per_meta_chunk_flip_l = disp_dlg_regs->refcyc_per_meta_chunk_flip_l; | |
1230 | out->dlg_regs.refcyc_per_meta_chunk_flip_c = disp_dlg_regs->refcyc_per_meta_chunk_flip_c; | |
1231 | out->dlg_regs.dst_y_per_pte_row_nom_l = disp_dlg_regs->dst_y_per_pte_row_nom_l; | |
1232 | out->dlg_regs.dst_y_per_pte_row_nom_c = disp_dlg_regs->dst_y_per_pte_row_nom_c; | |
1233 | out->dlg_regs.refcyc_per_pte_group_nom_l = disp_dlg_regs->refcyc_per_pte_group_nom_l; | |
1234 | out->dlg_regs.refcyc_per_pte_group_nom_c = disp_dlg_regs->refcyc_per_pte_group_nom_c; | |
1235 | out->dlg_regs.dst_y_per_meta_row_nom_l = disp_dlg_regs->dst_y_per_meta_row_nom_l; | |
1236 | out->dlg_regs.dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_c; | |
1237 | out->dlg_regs.refcyc_per_meta_chunk_nom_l = disp_dlg_regs->refcyc_per_meta_chunk_nom_l; | |
1238 | out->dlg_regs.refcyc_per_meta_chunk_nom_c = disp_dlg_regs->refcyc_per_meta_chunk_nom_c; | |
1239 | out->dlg_regs.refcyc_per_line_delivery_pre_l = disp_dlg_regs->refcyc_per_line_delivery_pre_l; | |
1240 | out->dlg_regs.refcyc_per_line_delivery_pre_c = disp_dlg_regs->refcyc_per_line_delivery_pre_c; | |
1241 | out->dlg_regs.refcyc_per_line_delivery_l = disp_dlg_regs->refcyc_per_line_delivery_l; | |
1242 | out->dlg_regs.refcyc_per_line_delivery_c = disp_dlg_regs->refcyc_per_line_delivery_c; | |
1243 | out->dlg_regs.refcyc_per_vm_group_vblank = disp_dlg_regs->refcyc_per_vm_group_vblank; | |
1244 | out->dlg_regs.refcyc_per_vm_group_flip = disp_dlg_regs->refcyc_per_vm_group_flip; | |
1245 | out->dlg_regs.refcyc_per_vm_req_vblank = disp_dlg_regs->refcyc_per_vm_req_vblank; | |
1246 | out->dlg_regs.refcyc_per_vm_req_flip = disp_dlg_regs->refcyc_per_vm_req_flip; | |
1247 | out->dlg_regs.dst_y_offset_cur0 = disp_dlg_regs->dst_y_offset_cur0; | |
1248 | out->dlg_regs.chunk_hdl_adjust_cur0 = disp_dlg_regs->chunk_hdl_adjust_cur0; | |
1249 | out->dlg_regs.dst_y_offset_cur1 = disp_dlg_regs->dst_y_offset_cur1; | |
1250 | out->dlg_regs.chunk_hdl_adjust_cur1 = disp_dlg_regs->chunk_hdl_adjust_cur1; | |
1251 | out->dlg_regs.vready_after_vcount0 = disp_dlg_regs->vready_after_vcount0; | |
1252 | out->dlg_regs.dst_y_delta_drq_limit = disp_dlg_regs->dst_y_delta_drq_limit; | |
1253 | out->dlg_regs.refcyc_per_vm_dmdata = disp_dlg_regs->refcyc_per_vm_dmdata; | |
1254 | out->dlg_regs.dmdata_dl_delta = disp_dlg_regs->dmdata_dl_delta; | |
1255 | ||
1256 | memset(&out->ttu_regs, 0, sizeof(out->ttu_regs)); | |
1257 | out->ttu_regs.qos_level_low_wm = disp_ttu_regs->qos_level_low_wm; | |
1258 | out->ttu_regs.qos_level_high_wm = disp_ttu_regs->qos_level_high_wm; | |
1259 | out->ttu_regs.min_ttu_vblank = disp_ttu_regs->min_ttu_vblank; | |
1260 | out->ttu_regs.qos_level_flip = disp_ttu_regs->qos_level_flip; | |
1261 | out->ttu_regs.refcyc_per_req_delivery_l = disp_ttu_regs->refcyc_per_req_delivery_l; | |
1262 | out->ttu_regs.refcyc_per_req_delivery_c = disp_ttu_regs->refcyc_per_req_delivery_c; | |
1263 | out->ttu_regs.refcyc_per_req_delivery_cur0 = disp_ttu_regs->refcyc_per_req_delivery_cur0; | |
1264 | out->ttu_regs.refcyc_per_req_delivery_cur1 = disp_ttu_regs->refcyc_per_req_delivery_cur1; | |
1265 | out->ttu_regs.refcyc_per_req_delivery_pre_l = disp_ttu_regs->refcyc_per_req_delivery_pre_l; | |
1266 | out->ttu_regs.refcyc_per_req_delivery_pre_c = disp_ttu_regs->refcyc_per_req_delivery_pre_c; | |
1267 | out->ttu_regs.refcyc_per_req_delivery_pre_cur0 = disp_ttu_regs->refcyc_per_req_delivery_pre_cur0; | |
1268 | out->ttu_regs.refcyc_per_req_delivery_pre_cur1 = disp_ttu_regs->refcyc_per_req_delivery_pre_cur1; | |
1269 | out->ttu_regs.qos_level_fixed_l = disp_ttu_regs->qos_level_fixed_l; | |
1270 | out->ttu_regs.qos_level_fixed_c = disp_ttu_regs->qos_level_fixed_c; | |
1271 | out->ttu_regs.qos_level_fixed_cur0 = disp_ttu_regs->qos_level_fixed_cur0; | |
1272 | out->ttu_regs.qos_level_fixed_cur1 = disp_ttu_regs->qos_level_fixed_cur1; | |
1273 | out->ttu_regs.qos_ramp_disable_l = disp_ttu_regs->qos_ramp_disable_l; | |
1274 | out->ttu_regs.qos_ramp_disable_c = disp_ttu_regs->qos_ramp_disable_c; | |
1275 | out->ttu_regs.qos_ramp_disable_cur0 = disp_ttu_regs->qos_ramp_disable_cur0; | |
1276 | out->ttu_regs.qos_ramp_disable_cur1 = disp_ttu_regs->qos_ramp_disable_cur1; | |
1277 | } |