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drm/amd/display: Add function to set pixels per cycle
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / dc / dml / display_mode_structs.h
CommitLineData
061bfa06
HW		 1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
c42656f8
DL		 25
26#include "dc_features.h"
16a8cb7c 27#include "display_mode_enums.h"
c42656f8 28
061bfa06
HW		 29#ifndef __DISPLAY_MODE_STRUCTS_H__
30#define __DISPLAY_MODE_STRUCTS_H__
31
cba5e870
DL		 32typedef struct _vcs_dpi_voltage_scaling_st voltage_scaling_st;
33typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st;
34typedef struct _vcs_dpi_ip_params_st ip_params_st;
35typedef struct _vcs_dpi_display_pipe_source_params_st display_pipe_source_params_st;
36typedef struct _vcs_dpi_display_output_params_st display_output_params_st;
cba5e870
DL		 37typedef struct _vcs_dpi_scaler_ratio_depth_st scaler_ratio_depth_st;
38typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st;
39typedef struct _vcs_dpi_display_pipe_dest_params_st display_pipe_dest_params_st;
40typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st;
41typedef struct _vcs_dpi_display_clocks_and_cfg_st display_clocks_and_cfg_st;
42typedef struct _vcs_dpi_display_e2e_pipe_params_st display_e2e_pipe_params_st;
cba5e870
DL		 43typedef struct _vcs_dpi_display_data_rq_misc_params_st display_data_rq_misc_params_st;
44typedef struct _vcs_dpi_display_data_rq_sizing_params_st display_data_rq_sizing_params_st;
45typedef struct _vcs_dpi_display_data_rq_dlg_params_st display_data_rq_dlg_params_st;
cba5e870
DL		 46typedef struct _vcs_dpi_display_rq_dlg_params_st display_rq_dlg_params_st;
47typedef struct _vcs_dpi_display_rq_sizing_params_st display_rq_sizing_params_st;
48typedef struct _vcs_dpi_display_rq_misc_params_st display_rq_misc_params_st;
49typedef struct _vcs_dpi_display_rq_params_st display_rq_params_st;
50typedef struct _vcs_dpi_display_dlg_regs_st display_dlg_regs_st;
51typedef struct _vcs_dpi_display_ttu_regs_st display_ttu_regs_st;
52typedef struct _vcs_dpi_display_data_rq_regs_st display_data_rq_regs_st;
53typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st;
54typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st;
cba5e870 55typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st;
6d04ee9d 56
dda4fb85
AP		 57typedef struct {
58 double UrgentWatermark;
59 double WritebackUrgentWatermark;
60 double DRAMClockChangeWatermark;
61 double FCLKChangeWatermark;
62 double WritebackDRAMClockChangeWatermark;
63 double WritebackFCLKChangeWatermark;
64 double StutterExitWatermark;
65 double StutterEnterPlusExitWatermark;
66 double Z8StutterExitWatermark;
67 double Z8StutterEnterPlusExitWatermark;
68 double USRRetrainingWatermark;
69} Watermarks;
70
71typedef struct {
72 double UrgentLatency;
73 double ExtraLatency;
74 double WritebackLatency;
75 double DRAMClockChangeLatency;
76 double FCLKChangeLatency;
77 double SRExitTime;
78 double SREnterPlusExitTime;
79 double SRExitZ8Time;
80 double SREnterPlusExitZ8Time;
81 double USRRetrainingLatencyPlusSMNLatency;
82} Latencies;
83
84typedef struct {
85 double Dppclk;
86 double Dispclk;
87 double PixelClock;
88 double DCFClkDeepSleep;
89 unsigned int DPPPerSurface;
90 bool ScalerEnabled;
91 enum dm_rotation_angle SourceRotation;
92 unsigned int ViewportHeight;
93 unsigned int ViewportHeightChroma;
94 unsigned int BlockWidth256BytesY;
95 unsigned int BlockHeight256BytesY;
96 unsigned int BlockWidth256BytesC;
97 unsigned int BlockHeight256BytesC;
98 unsigned int BlockWidthY;
99 unsigned int BlockHeightY;
100 unsigned int BlockWidthC;
101 unsigned int BlockHeightC;
102 unsigned int InterlaceEnable;
103 unsigned int NumberOfCursors;
104 unsigned int VBlank;
105 unsigned int HTotal;
106 unsigned int HActive;
107 bool DCCEnable;
108 enum odm_combine_mode ODMMode;
109 enum source_format_class SourcePixelFormat;
110 enum dm_swizzle_mode SurfaceTiling;
111 unsigned int BytePerPixelY;
112 unsigned int BytePerPixelC;
113 bool ProgressiveToInterlaceUnitInOPP;
114 double VRatio;
115 double VRatioChroma;
116 unsigned int VTaps;
117 unsigned int VTapsChroma;
118 unsigned int PitchY;
119 unsigned int DCCMetaPitchY;
120 unsigned int PitchC;
121 unsigned int DCCMetaPitchC;
122 bool ViewportStationary;
123 unsigned int ViewportXStart;
124 unsigned int ViewportYStart;
125 unsigned int ViewportXStartC;
126 unsigned int ViewportYStartC;
127 bool FORCE_ONE_ROW_FOR_FRAME;
128 unsigned int SwathHeightY;
129 unsigned int SwathHeightC;
130} DmlPipe;
131
132typedef struct {
133 double UrgentLatency;
134 double ExtraLatency;
135 double WritebackLatency;
136 double DRAMClockChangeLatency;
137 double FCLKChangeLatency;
138 double SRExitTime;
139 double SREnterPlusExitTime;
140 double SRExitZ8Time;
141 double SREnterPlusExitZ8Time;
142 double USRRetrainingLatency;
143 double SMNLatency;
144} SOCParametersList;
145
061bfa06 146struct _vcs_dpi_voltage_scaling_st {
6d04ee9d 147 int state;
cb94f78e 148 double dscclk_mhz;
061bfa06 149 double dcfclk_mhz;
6d04ee9d 150 double socclk_mhz;
728c0698 151 double phyclk_d18_mhz;
dda4fb85 152 double phyclk_d32_mhz;
bf28c2e2 153 double dram_speed_mts;
6d04ee9d 154 double fabricclk_mhz;
061bfa06 155 double dispclk_mhz;
a39a5816 156 double dram_bw_per_chan_gbps;
061bfa06 157 double phyclk_mhz;
6d04ee9d 158 double dppclk_mhz;
5fc11598 159 double dtbclk_mhz;
061bfa06
HW		 160};
161
cba5e870 162struct _vcs_dpi_soc_bounding_box_st {
c42656f8 163 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
1f474c87
LL		 164 /*
165 * This is a temporary stash for updating @clock_limits with the PMFW
166 * clock table. Do not use outside of *update_bw_boudning_box functions.
167 */
168 struct _vcs_dpi_voltage_scaling_st _clock_tmp[DC__VOLTAGE_STATES];
9b31b4e8 169 unsigned int num_states;
cba5e870
DL		 170 double sr_exit_time_us;
171 double sr_enter_plus_exit_time_us;
74458c08
NK		 172 double sr_exit_z8_time_us;
173 double sr_enter_plus_exit_z8_time_us;
cba5e870
DL		 174 double urgent_latency_us;
175 double urgent_latency_pixel_data_only_us;
176 double urgent_latency_pixel_mixed_with_vm_data_us;
177 double urgent_latency_vm_data_only_us;
dda4fb85
AP		 178 double usr_retraining_latency_us;
179 double smn_latency_us;
180 double fclk_change_latency_us;
181 double mall_allocated_for_dcn_mbytes;
182 double pct_ideal_fabric_bw_after_urgent;
183 double pct_ideal_dram_bw_after_urgent_strobe;
184 double max_avg_fabric_bw_use_normal_percent;
185 double max_avg_dram_bw_use_normal_strobe_percent;
186 enum dm_prefetch_modes allow_for_pstate_or_stutter_in_vblank_final;
cba5e870
DL		 187 double writeback_latency_us;
188 double ideal_dram_bw_after_urgent_percent;
189 double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly
190 double pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
191 double pct_ideal_dram_sdp_bw_after_urgent_vm_only;
1c994f2d 192 double pct_ideal_sdp_bw_after_urgent;
cba5e870
DL		 193 double max_avg_sdp_bw_use_normal_percent;
194 double max_avg_dram_bw_use_normal_percent;
195 unsigned int max_request_size_bytes;
196 double downspread_percent;
197 double dram_page_open_time_ns;
198 double dram_rw_turnaround_time_ns;
199 double dram_return_buffer_per_channel_bytes;
200 double dram_channel_width_bytes;
6d04ee9d
DL		 201 double fabric_datapath_to_dcn_data_return_bytes;
202 double dcn_downspread_percent;
203 double dispclk_dppclk_vco_speed_mhz;
3eea71e3 204 double dfs_vco_period_ps;
cba5e870
DL		 205 unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes;
206 unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
207 unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes;
208 unsigned int round_trip_ping_latency_dcfclk_cycles;
209 unsigned int urgent_out_of_order_return_per_channel_bytes;
210 unsigned int channel_interleave_bytes;
211 unsigned int num_banks;
212 unsigned int num_chans;
213 unsigned int vmm_page_size_bytes;
728c0698 214 unsigned int hostvm_min_page_size_bytes;
71e6bd2a 215 unsigned int gpuvm_min_page_size_bytes;
cba5e870 216 double dram_clock_change_latency_us;
057fc695 217 double dummy_pstate_latency_us;
cba5e870
DL		 218 double writeback_dram_clock_change_latency_us;
219 unsigned int return_bus_width_bytes;
220 unsigned int voltage_override;
221 double xfc_bus_transport_time_us;
222 double xfc_xbuf_latency_tolerance_us;
223 int use_urgent_burst_bw;
56260cbf 224 double min_dcfclk;
1071a0ec
IB		 225 bool do_urgent_latency_adjustment;
226 double urgent_latency_adjustment_fabric_clock_component_us;
227 double urgent_latency_adjustment_fabric_clock_reference_mhz;
5622b2d6 228 bool disable_dram_clock_change_vactive_support;
f00889dc 229 bool allow_dram_clock_one_display_vactive;
16a8cb7c 230 enum self_refresh_affinity allow_dram_self_refresh_or_dram_clock_change_in_vblank;
6d04ee9d
DL		 231};
232
cba5e870 233struct _vcs_dpi_ip_params_st {
38a509d5 234 bool use_min_dcfclk;
6725a88f 235 bool clamp_min_dcfclk;
cba5e870
DL		 236 bool gpuvm_enable;
237 bool hostvm_enable;
1c994f2d 238 bool dsc422_native_support;
cba5e870
DL		 239 unsigned int gpuvm_max_page_table_levels;
240 unsigned int hostvm_max_page_table_levels;
241 unsigned int hostvm_cached_page_table_levels;
242 unsigned int pte_group_size_bytes;
243 unsigned int max_inter_dcn_tile_repeaters;
244 unsigned int num_dsc;
245 unsigned int odm_capable;
246 unsigned int rob_buffer_size_kbytes;
247 unsigned int det_buffer_size_kbytes;
2e6e14c9 248 unsigned int min_comp_buffer_size_kbytes;
fb57452f
DL		 249 unsigned int dpte_buffer_size_in_pte_reqs_luma;
250 unsigned int dpte_buffer_size_in_pte_reqs_chroma;
cba5e870
DL		 251 unsigned int pde_proc_buffer_size_64k_reqs;
252 unsigned int dpp_output_buffer_pixels;
253 unsigned int opp_output_buffer_lines;
254 unsigned int pixel_chunk_size_kbytes;
dda4fb85
AP		 255 unsigned int alpha_pixel_chunk_size_kbytes;
256 unsigned int min_pixel_chunk_size_bytes;
257 unsigned int dcc_meta_buffer_size_bytes;
cba5e870
DL		 258 unsigned char pte_enable;
259 unsigned int pte_chunk_size_kbytes;
260 unsigned int meta_chunk_size_kbytes;
1c994f2d 261 unsigned int min_meta_chunk_size_bytes;
cba5e870
DL		 262 unsigned int writeback_chunk_size_kbytes;
263 unsigned int line_buffer_size_bits;
264 unsigned int max_line_buffer_lines;
265 unsigned int writeback_luma_buffer_size_kbytes;
266 unsigned int writeback_chroma_buffer_size_kbytes;
267 unsigned int writeback_chroma_line_buffer_width_pixels;
728c0698
HW		 268
269 unsigned int writeback_interface_buffer_size_kbytes;
270 unsigned int writeback_line_buffer_buffer_size;
271
728c0698
HW		 272 unsigned int writeback_10bpc420_supported;
273 double writeback_max_hscl_ratio;
274 double writeback_max_vscl_ratio;
275 double writeback_min_hscl_ratio;
276 double writeback_min_vscl_ratio;
091e3131 277 unsigned int maximum_dsc_bits_per_component;
dda4fb85 278 unsigned int maximum_pixels_per_line_per_dsc_unit;
728c0698
HW		 279 unsigned int writeback_max_hscl_taps;
280 unsigned int writeback_max_vscl_taps;
281 unsigned int writeback_line_buffer_luma_buffer_size;
282 unsigned int writeback_line_buffer_chroma_buffer_size;
5cb646d7 283
cba5e870
DL		 284 unsigned int max_page_table_levels;
285 unsigned int max_num_dpp;
286 unsigned int max_num_otg;
287 unsigned int cursor_chunk_size;
288 unsigned int cursor_buffer_size;
289 unsigned int max_num_wb;
290 unsigned int max_dchub_pscl_bw_pix_per_clk;
291 unsigned int max_pscl_lb_bw_pix_per_clk;
292 unsigned int max_lb_vscl_bw_pix_per_clk;
293 unsigned int max_vscl_hscl_bw_pix_per_clk;
294 double max_hscl_ratio;
295 double max_vscl_ratio;
296 unsigned int hscl_mults;
297 unsigned int vscl_mults;
298 unsigned int max_hscl_taps;
299 unsigned int max_vscl_taps;
300 unsigned int xfc_supported;
728c0698
HW		 301 unsigned int ptoi_supported;
302 unsigned int gfx7_compat_tiling_supported;
303
304 bool odm_combine_4to1_supported;
305 bool dynamic_metadata_vm_enabled;
306 unsigned int max_num_hdmi_frl_outputs;
307
cba5e870
DL		 308 unsigned int xfc_fill_constant_bytes;
309 double dispclk_ramp_margin_percent;
310 double xfc_fill_bw_overhead_percent;
311 double underscan_factor;
312 unsigned int min_vblank_lines;
313 unsigned int dppclk_delay_subtotal;
314 unsigned int dispclk_delay_subtotal;
47b0c91f 315 double dcfclk_cstate_latency;
cba5e870
DL		 316 unsigned int dppclk_delay_scl;
317 unsigned int dppclk_delay_scl_lb_only;
318 unsigned int dppclk_delay_cnvc_formatter;
319 unsigned int dppclk_delay_cnvc_cursor;
320 unsigned int is_line_buffer_bpp_fixed;
321 unsigned int line_buffer_fixed_bpp;
322 unsigned int dcc_supported;
74458c08
NK		 323 unsigned int config_return_buffer_size_in_kbytes;
324 unsigned int compressed_buffer_segment_size_in_kbytes;
325 unsigned int meta_fifo_size_in_kentries;
326 unsigned int zero_size_buffer_entries;
327 unsigned int compbuf_reserved_space_64b;
328 unsigned int compbuf_reserved_space_zs;
6d04ee9d 329
061bfa06
HW		 330 unsigned int IsLineBufferBppFixed;
331 unsigned int LineBufferFixedBpp;
061bfa06
HW		 332 unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
333 unsigned int bug_forcing_LC_req_same_size_fixed;
8f174fdb 334 unsigned int number_of_cursors;
dda4fb85
AP		 335 unsigned int max_num_dp2p0_outputs;
336 unsigned int max_num_dp2p0_streams;
84de5c2e 337 unsigned int VBlankNomDefaultUS;
061bfa06
HW		 338};
339
6d04ee9d
DL		 340struct _vcs_dpi_display_xfc_params_st {
341 double xfc_tslv_vready_offset_us;
342 double xfc_tslv_vupdate_width_us;
343 double xfc_tslv_vupdate_offset_us;
344 int xfc_slv_chunk_size_bytes;
345};
346
cba5e870
DL		 347struct _vcs_dpi_display_pipe_source_params_st {
348 int source_format;
1c994f2d
DL		 349 double dcc_fraction_of_zs_req_luma;
350 double dcc_fraction_of_zs_req_chroma;
cba5e870 351 unsigned char dcc;
cba5e870 352 unsigned int dcc_rate;
5fc11598 353 unsigned int dcc_rate_chroma;
cba5e870
DL		 354 unsigned char dcc_use_global;
355 unsigned char vm;
1c994f2d 356 bool unbounded_req_mode;
cba5e870
DL		 357 bool gpuvm; // gpuvm enabled
358 bool hostvm; // hostvm enabled
359 bool gpuvm_levels_force_en;
360 unsigned int gpuvm_levels_force;
361 bool hostvm_levels_force_en;
362 unsigned int hostvm_levels_force;
363 int source_scan;
dda4fb85 364 int source_rotation; // new in dml32
85f4bc0c 365 unsigned int det_size_override; // use to populate DETSizeOverride in vba struct
cba5e870
DL		 366 int sw_mode;
367 int macro_tile_size;
5fc11598 368 unsigned int surface_width_y;
71e6bd2a 369 unsigned int surface_height_y;
5fc11598
DL		 370 unsigned int surface_width_c;
371 unsigned int surface_height_c;
cba5e870
DL		 372 unsigned int viewport_width;
373 unsigned int viewport_height;
374 unsigned int viewport_y_y;
375 unsigned int viewport_y_c;
376 unsigned int viewport_width_c;
377 unsigned int viewport_height_c;
6566cae7
DL		 378 unsigned int viewport_width_max;
379 unsigned int viewport_height_max;
dda4fb85
AP		 380 unsigned int viewport_x_y;
381 unsigned int viewport_x_c;
382 bool viewport_stationary;
383 unsigned int dcc_rate_luma;
384 unsigned int gpuvm_min_page_size_kbytes;
385 unsigned int use_mall_for_pstate_change;
386 unsigned int use_mall_for_static_screen;
387 bool force_one_row_for_frame;
388 bool pte_buffer_mode;
cba5e870
DL		 389 unsigned int data_pitch;
390 unsigned int data_pitch_c;
391 unsigned int meta_pitch;
392 unsigned int meta_pitch_c;
393 unsigned int cur0_src_width;
394 int cur0_bpp;
395 unsigned int cur1_src_width;
396 int cur1_bpp;
397 int num_cursors;
398 unsigned char is_hsplit;
399 unsigned char dynamic_metadata_enable;
400 unsigned int dynamic_metadata_lines_before_active;
401 unsigned int dynamic_metadata_xmit_bytes;
402 unsigned int hsplit_grp;
403 unsigned char xfc_enable;
404 unsigned char xfc_slave;
728c0698 405 unsigned char immediate_flip;
6d04ee9d 406 struct _vcs_dpi_display_xfc_params_st xfc_params;
0623fdb0
CL		 407 //for vstartuplines calculation freesync
408 unsigned char v_total_min;
409 unsigned char v_total_max;
6d04ee9d
DL		 410};
411struct writeback_st {
412 int wb_src_height;
728c0698 413 int wb_src_width;
6d04ee9d
DL		 414 int wb_dst_width;
415 int wb_dst_height;
416 int wb_pixel_format;
417 int wb_htaps_luma;
418 int wb_vtaps_luma;
419 int wb_htaps_chroma;
420 int wb_vtaps_chroma;
dda4fb85
AP		 421 unsigned int wb_htaps;
422 unsigned int wb_vtaps;
f8931ea7
EB		 423 double wb_hratio;
424 double wb_vratio;
6d04ee9d
DL		 425};
426
dda4fb85
AP		 427struct display_audio_params_st {
428 unsigned int audio_sample_rate_khz;
429 int audio_sample_layout;
430};
431
cba5e870
DL		 432struct _vcs_dpi_display_output_params_st {
433 int dp_lanes;
486cc0ee 434 double output_bpp;
091e3131 435 unsigned int dsc_input_bpc;
cba5e870
DL		 436 int dsc_enable;
437 int wb_enable;
438 int num_active_wb;
cba5e870 439 int output_type;
91a51fbf 440 int is_virtual;
cba5e870 441 int output_format;
cba5e870 442 int dsc_slices;
3ab4cc65 443 int max_audio_sample_rate;
6d04ee9d 444 struct writeback_st wb;
dda4fb85
AP		 445 struct display_audio_params_st audio;
446 unsigned int output_bpc;
447 int dp_rate;
448 unsigned int dp_multistream_id;
449 bool dp_multistream_en;
6d04ee9d
DL		 450};
451
cba5e870
DL		 452struct _vcs_dpi_scaler_ratio_depth_st {
453 double hscl_ratio;
454 double vscl_ratio;
455 double hscl_ratio_c;
456 double vscl_ratio_c;
457 double vinit;
458 double vinit_c;
459 double vinit_bot;
460 double vinit_bot_c;
461 int lb_depth;
462 int scl_enable;
463};
464
465struct _vcs_dpi_scaler_taps_st {
466 unsigned int htaps;
467 unsigned int vtaps;
468 unsigned int htaps_c;
469 unsigned int vtaps_c;
470};
471
472struct _vcs_dpi_display_pipe_dest_params_st {
473 unsigned int recout_width;
474 unsigned int recout_height;
475 unsigned int full_recout_width;
476 unsigned int full_recout_height;
477 unsigned int hblank_start;
478 unsigned int hblank_end;
479 unsigned int vblank_start;
480 unsigned int vblank_end;
481 unsigned int htotal;
482 unsigned int vtotal;
1c994f2d 483 unsigned int vfront_porch;
cba5e870
DL		 484 unsigned int vactive;
485 unsigned int hactive;
486 unsigned int vstartup_start;
487 unsigned int vupdate_offset;
488 unsigned int vupdate_width;
489 unsigned int vready_offset;
490 unsigned char interlaced;
cba5e870
DL		 491 double pixel_rate_mhz;
492 unsigned char synchronized_vblank_all_planes;
493 unsigned char otg_inst;
5fc11598 494 unsigned int odm_combine;
5fbac0a5 495 unsigned char use_maximum_vstartup;
0623fdb0
CL		 496 unsigned int vtotal_max;
497 unsigned int vtotal_min;
dda4fb85
AP		 498 unsigned int refresh_rate;
499 bool synchronize_timings;
cba5e870
DL		 500};
501
502struct _vcs_dpi_display_pipe_params_st {
503 display_pipe_source_params_st src;
504 display_pipe_dest_params_st dest;
505 scaler_ratio_depth_st scale_ratio_depth;
506 scaler_taps_st scale_taps;
507};
508
509struct _vcs_dpi_display_clocks_and_cfg_st {
510 int voltage;
511 double dppclk_mhz;
512 double refclk_mhz;
513 double dispclk_mhz;
514 double dcfclk_mhz;
515 double socclk_mhz;
516};
517
518struct _vcs_dpi_display_e2e_pipe_params_st {
519 display_pipe_params_st pipe;
520 display_output_params_st dout;
521 display_clocks_and_cfg_st clks_cfg;
522};
523
cba5e870
DL		 524struct _vcs_dpi_display_data_rq_misc_params_st {
525 unsigned int full_swath_bytes;
526 unsigned int stored_swath_bytes;
527 unsigned int blk256_height;
528 unsigned int blk256_width;
529 unsigned int req_height;
530 unsigned int req_width;
531};
532
533struct _vcs_dpi_display_data_rq_sizing_params_st {
534 unsigned int chunk_bytes;
535 unsigned int min_chunk_bytes;
536 unsigned int meta_chunk_bytes;
537 unsigned int min_meta_chunk_bytes;
538 unsigned int mpte_group_bytes;
539 unsigned int dpte_group_bytes;
540};
541
542struct _vcs_dpi_display_data_rq_dlg_params_st {
543 unsigned int swath_width_ub;
544 unsigned int swath_height;
545 unsigned int req_per_swath_ub;
546 unsigned int meta_pte_bytes_per_frame_ub;
547 unsigned int dpte_req_per_row_ub;
548 unsigned int dpte_groups_per_row_ub;
549 unsigned int dpte_row_height;
550 unsigned int dpte_bytes_per_row_ub;
551 unsigned int meta_chunks_per_row_ub;
552 unsigned int meta_req_per_row_ub;
553 unsigned int meta_row_height;
554 unsigned int meta_bytes_per_row_ub;
555};
556
cba5e870
DL		 557struct _vcs_dpi_display_rq_dlg_params_st {
558 display_data_rq_dlg_params_st rq_l;
559 display_data_rq_dlg_params_st rq_c;
cba5e870
DL		 560};
561
562struct _vcs_dpi_display_rq_sizing_params_st {
563 display_data_rq_sizing_params_st rq_l;
564 display_data_rq_sizing_params_st rq_c;
565};
566
567struct _vcs_dpi_display_rq_misc_params_st {
568 display_data_rq_misc_params_st rq_l;
569 display_data_rq_misc_params_st rq_c;
570};
571
572struct _vcs_dpi_display_rq_params_st {
573 unsigned char yuv420;
574 unsigned char yuv420_10bpc;
71e6bd2a 575 unsigned char rgbe_alpha;
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DL		 576 display_rq_misc_params_st misc;
577 display_rq_sizing_params_st sizing;
578 display_rq_dlg_params_st dlg;
579};
580
581struct _vcs_dpi_display_dlg_regs_st {
582 unsigned int refcyc_h_blank_end;
583 unsigned int dlg_vblank_end;
584 unsigned int min_dst_y_next_start;
e5fc7825
GT		 585 unsigned int optimized_min_dst_y_next_start;
586 unsigned int optimized_min_dst_y_next_start_us;
cba5e870
DL		 587 unsigned int refcyc_per_htotal;
588 unsigned int refcyc_x_after_scaler;
589 unsigned int dst_y_after_scaler;
590 unsigned int dst_y_prefetch;
591 unsigned int dst_y_per_vm_vblank;
592 unsigned int dst_y_per_row_vblank;
593 unsigned int dst_y_per_vm_flip;
594 unsigned int dst_y_per_row_flip;
595 unsigned int ref_freq_to_pix_freq;
596 unsigned int vratio_prefetch;
597 unsigned int vratio_prefetch_c;
598 unsigned int refcyc_per_pte_group_vblank_l;
599 unsigned int refcyc_per_pte_group_vblank_c;
600 unsigned int refcyc_per_meta_chunk_vblank_l;
601 unsigned int refcyc_per_meta_chunk_vblank_c;
602 unsigned int refcyc_per_pte_group_flip_l;
603 unsigned int refcyc_per_pte_group_flip_c;
604 unsigned int refcyc_per_meta_chunk_flip_l;
605 unsigned int refcyc_per_meta_chunk_flip_c;
606 unsigned int dst_y_per_pte_row_nom_l;
607 unsigned int dst_y_per_pte_row_nom_c;
608 unsigned int refcyc_per_pte_group_nom_l;
609 unsigned int refcyc_per_pte_group_nom_c;
610 unsigned int dst_y_per_meta_row_nom_l;
611 unsigned int dst_y_per_meta_row_nom_c;
612 unsigned int refcyc_per_meta_chunk_nom_l;
613 unsigned int refcyc_per_meta_chunk_nom_c;
614 unsigned int refcyc_per_line_delivery_pre_l;
615 unsigned int refcyc_per_line_delivery_pre_c;
616 unsigned int refcyc_per_line_delivery_l;
617 unsigned int refcyc_per_line_delivery_c;
618 unsigned int chunk_hdl_adjust_cur0;
619 unsigned int chunk_hdl_adjust_cur1;
620 unsigned int vready_after_vcount0;
621 unsigned int dst_y_offset_cur0;
622 unsigned int dst_y_offset_cur1;
623 unsigned int xfc_reg_transfer_delay;
624 unsigned int xfc_reg_precharge_delay;
625 unsigned int xfc_reg_remote_surface_flip_latency;
626 unsigned int xfc_reg_prefetch_margin;
627 unsigned int dst_y_delta_drq_limit;
fb57452f
DL		 628 unsigned int refcyc_per_vm_group_vblank;
629 unsigned int refcyc_per_vm_group_flip;
630 unsigned int refcyc_per_vm_req_vblank;
631 unsigned int refcyc_per_vm_req_flip;
fbaf207f 632 unsigned int refcyc_per_vm_dmdata;
1c994f2d 633 unsigned int dmdata_dl_delta;
cba5e870
DL		 634};
635
636struct _vcs_dpi_display_ttu_regs_st {
637 unsigned int qos_level_low_wm;
638 unsigned int qos_level_high_wm;
639 unsigned int min_ttu_vblank;
640 unsigned int qos_level_flip;
641 unsigned int refcyc_per_req_delivery_l;
642 unsigned int refcyc_per_req_delivery_c;
643 unsigned int refcyc_per_req_delivery_cur0;
644 unsigned int refcyc_per_req_delivery_cur1;
645 unsigned int refcyc_per_req_delivery_pre_l;
646 unsigned int refcyc_per_req_delivery_pre_c;
647 unsigned int refcyc_per_req_delivery_pre_cur0;
648 unsigned int refcyc_per_req_delivery_pre_cur1;
649 unsigned int qos_level_fixed_l;
650 unsigned int qos_level_fixed_c;
651 unsigned int qos_level_fixed_cur0;
652 unsigned int qos_level_fixed_cur1;
653 unsigned int qos_ramp_disable_l;
654 unsigned int qos_ramp_disable_c;
655 unsigned int qos_ramp_disable_cur0;
656 unsigned int qos_ramp_disable_cur1;
657};
658
659struct _vcs_dpi_display_data_rq_regs_st {
660 unsigned int chunk_size;
661 unsigned int min_chunk_size;
662 unsigned int meta_chunk_size;
663 unsigned int min_meta_chunk_size;
664 unsigned int dpte_group_size;
665 unsigned int mpte_group_size;
666 unsigned int swath_height;
667 unsigned int pte_row_height_linear;
668};
669
670struct _vcs_dpi_display_rq_regs_st {
671 display_data_rq_regs_st rq_regs_l;
672 display_data_rq_regs_st rq_regs_c;
673 unsigned int drq_expansion_mode;
674 unsigned int prq_expansion_mode;
675 unsigned int mrq_expansion_mode;
676 unsigned int crq_expansion_mode;
677 unsigned int plane1_base_address;
98e95e4f
JP		 678 unsigned int aperture_low_addr; // bits [47:18]
679 unsigned int aperture_high_addr; // bits [47:18]
cba5e870
DL		 680};
681
682struct _vcs_dpi_display_dlg_sys_params_st {
683 double t_mclk_wm_us;
684 double t_urg_wm_us;
685 double t_sr_wm_us;
686 double t_extra_us;
687 double mem_trip_us;
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DL		 688 double deepsleep_dcfclk_mhz;
689 double total_flip_bw;
690 unsigned int total_flip_bytes;
691};
692
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DL		 693struct _vcs_dpi_display_arb_params_st {
694 int max_req_outstanding;
695 int min_req_outstanding;
696 int sat_level_us;
dda4fb85
AP		 697 int hvm_min_req_outstand_commit_threshold;
698 int hvm_max_qos_commit_threshold;
699 int compbuf_reserved_space_kbytes;
061bfa06
HW		 700};
701
702#endif /*__DISPLAY_MODE_STRUCTS_H__*/
Linux 6.x block layer and io_uring tree(s)