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061bfa06 HW |
1 | /* |
2 | * Copyright 2017 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | #ifndef __DISPLAY_MODE_STRUCTS_H__ | |
26 | #define __DISPLAY_MODE_STRUCTS_H__ | |
27 | ||
a39a5816 | 28 | #define MAX_CLOCK_LIMIT_STATES 9 |
4966c3d9 | 29 | |
cba5e870 DL |
30 | typedef struct _vcs_dpi_voltage_scaling_st voltage_scaling_st; |
31 | typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st; | |
32 | typedef struct _vcs_dpi_ip_params_st ip_params_st; | |
33 | typedef struct _vcs_dpi_display_pipe_source_params_st display_pipe_source_params_st; | |
34 | typedef struct _vcs_dpi_display_output_params_st display_output_params_st; | |
cba5e870 DL |
35 | typedef struct _vcs_dpi_scaler_ratio_depth_st scaler_ratio_depth_st; |
36 | typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st; | |
37 | typedef struct _vcs_dpi_display_pipe_dest_params_st display_pipe_dest_params_st; | |
38 | typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st; | |
39 | typedef struct _vcs_dpi_display_clocks_and_cfg_st display_clocks_and_cfg_st; | |
40 | typedef struct _vcs_dpi_display_e2e_pipe_params_st display_e2e_pipe_params_st; | |
cba5e870 DL |
41 | typedef struct _vcs_dpi_display_data_rq_misc_params_st display_data_rq_misc_params_st; |
42 | typedef struct _vcs_dpi_display_data_rq_sizing_params_st display_data_rq_sizing_params_st; | |
43 | typedef struct _vcs_dpi_display_data_rq_dlg_params_st display_data_rq_dlg_params_st; | |
cba5e870 DL |
44 | typedef struct _vcs_dpi_display_rq_dlg_params_st display_rq_dlg_params_st; |
45 | typedef struct _vcs_dpi_display_rq_sizing_params_st display_rq_sizing_params_st; | |
46 | typedef struct _vcs_dpi_display_rq_misc_params_st display_rq_misc_params_st; | |
47 | typedef struct _vcs_dpi_display_rq_params_st display_rq_params_st; | |
48 | typedef struct _vcs_dpi_display_dlg_regs_st display_dlg_regs_st; | |
49 | typedef struct _vcs_dpi_display_ttu_regs_st display_ttu_regs_st; | |
50 | typedef struct _vcs_dpi_display_data_rq_regs_st display_data_rq_regs_st; | |
51 | typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st; | |
52 | typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st; | |
cba5e870 | 53 | typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st; |
6d04ee9d | 54 | |
061bfa06 | 55 | struct _vcs_dpi_voltage_scaling_st { |
6d04ee9d | 56 | int state; |
cb94f78e | 57 | double dscclk_mhz; |
061bfa06 | 58 | double dcfclk_mhz; |
6d04ee9d | 59 | double socclk_mhz; |
728c0698 | 60 | double phyclk_d18_mhz; |
bf28c2e2 | 61 | double dram_speed_mts; |
6d04ee9d | 62 | double fabricclk_mhz; |
061bfa06 | 63 | double dispclk_mhz; |
a39a5816 | 64 | double dram_bw_per_chan_gbps; |
061bfa06 | 65 | double phyclk_mhz; |
6d04ee9d | 66 | double dppclk_mhz; |
5fc11598 | 67 | double dtbclk_mhz; |
061bfa06 HW |
68 | }; |
69 | ||
cba5e870 DL |
70 | struct _vcs_dpi_soc_bounding_box_st { |
71 | double sr_exit_time_us; | |
72 | double sr_enter_plus_exit_time_us; | |
73 | double urgent_latency_us; | |
74 | double urgent_latency_pixel_data_only_us; | |
75 | double urgent_latency_pixel_mixed_with_vm_data_us; | |
76 | double urgent_latency_vm_data_only_us; | |
77 | double writeback_latency_us; | |
78 | double ideal_dram_bw_after_urgent_percent; | |
79 | double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly | |
80 | double pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm; | |
81 | double pct_ideal_dram_sdp_bw_after_urgent_vm_only; | |
82 | double max_avg_sdp_bw_use_normal_percent; | |
83 | double max_avg_dram_bw_use_normal_percent; | |
84 | unsigned int max_request_size_bytes; | |
85 | double downspread_percent; | |
86 | double dram_page_open_time_ns; | |
87 | double dram_rw_turnaround_time_ns; | |
88 | double dram_return_buffer_per_channel_bytes; | |
89 | double dram_channel_width_bytes; | |
6d04ee9d DL |
90 | double fabric_datapath_to_dcn_data_return_bytes; |
91 | double dcn_downspread_percent; | |
92 | double dispclk_dppclk_vco_speed_mhz; | |
3eea71e3 | 93 | double dfs_vco_period_ps; |
cba5e870 DL |
94 | unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes; |
95 | unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes; | |
96 | unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes; | |
97 | unsigned int round_trip_ping_latency_dcfclk_cycles; | |
98 | unsigned int urgent_out_of_order_return_per_channel_bytes; | |
99 | unsigned int channel_interleave_bytes; | |
100 | unsigned int num_banks; | |
101 | unsigned int num_chans; | |
102 | unsigned int vmm_page_size_bytes; | |
728c0698 | 103 | unsigned int hostvm_min_page_size_bytes; |
71e6bd2a | 104 | unsigned int gpuvm_min_page_size_bytes; |
cba5e870 | 105 | double dram_clock_change_latency_us; |
057fc695 | 106 | double dummy_pstate_latency_us; |
cba5e870 DL |
107 | double writeback_dram_clock_change_latency_us; |
108 | unsigned int return_bus_width_bytes; | |
109 | unsigned int voltage_override; | |
110 | double xfc_bus_transport_time_us; | |
111 | double xfc_xbuf_latency_tolerance_us; | |
112 | int use_urgent_burst_bw; | |
8d6da3bb | 113 | unsigned int num_states; |
4966c3d9 | 114 | struct _vcs_dpi_voltage_scaling_st clock_limits[MAX_CLOCK_LIMIT_STATES]; |
1071a0ec IB |
115 | bool do_urgent_latency_adjustment; |
116 | double urgent_latency_adjustment_fabric_clock_component_us; | |
117 | double urgent_latency_adjustment_fabric_clock_reference_mhz; | |
5622b2d6 | 118 | bool disable_dram_clock_change_vactive_support; |
6d04ee9d DL |
119 | }; |
120 | ||
cba5e870 DL |
121 | struct _vcs_dpi_ip_params_st { |
122 | bool gpuvm_enable; | |
123 | bool hostvm_enable; | |
124 | unsigned int gpuvm_max_page_table_levels; | |
125 | unsigned int hostvm_max_page_table_levels; | |
126 | unsigned int hostvm_cached_page_table_levels; | |
127 | unsigned int pte_group_size_bytes; | |
128 | unsigned int max_inter_dcn_tile_repeaters; | |
129 | unsigned int num_dsc; | |
130 | unsigned int odm_capable; | |
131 | unsigned int rob_buffer_size_kbytes; | |
132 | unsigned int det_buffer_size_kbytes; | |
fb57452f DL |
133 | unsigned int dpte_buffer_size_in_pte_reqs_luma; |
134 | unsigned int dpte_buffer_size_in_pte_reqs_chroma; | |
cba5e870 DL |
135 | unsigned int pde_proc_buffer_size_64k_reqs; |
136 | unsigned int dpp_output_buffer_pixels; | |
137 | unsigned int opp_output_buffer_lines; | |
138 | unsigned int pixel_chunk_size_kbytes; | |
139 | unsigned char pte_enable; | |
140 | unsigned int pte_chunk_size_kbytes; | |
141 | unsigned int meta_chunk_size_kbytes; | |
142 | unsigned int writeback_chunk_size_kbytes; | |
143 | unsigned int line_buffer_size_bits; | |
144 | unsigned int max_line_buffer_lines; | |
145 | unsigned int writeback_luma_buffer_size_kbytes; | |
146 | unsigned int writeback_chroma_buffer_size_kbytes; | |
147 | unsigned int writeback_chroma_line_buffer_width_pixels; | |
728c0698 HW |
148 | |
149 | unsigned int writeback_interface_buffer_size_kbytes; | |
150 | unsigned int writeback_line_buffer_buffer_size; | |
151 | ||
728c0698 HW |
152 | unsigned int writeback_10bpc420_supported; |
153 | double writeback_max_hscl_ratio; | |
154 | double writeback_max_vscl_ratio; | |
155 | double writeback_min_hscl_ratio; | |
156 | double writeback_min_vscl_ratio; | |
157 | unsigned int writeback_max_hscl_taps; | |
158 | unsigned int writeback_max_vscl_taps; | |
159 | unsigned int writeback_line_buffer_luma_buffer_size; | |
160 | unsigned int writeback_line_buffer_chroma_buffer_size; | |
5cb646d7 | 161 | |
cba5e870 DL |
162 | unsigned int max_page_table_levels; |
163 | unsigned int max_num_dpp; | |
164 | unsigned int max_num_otg; | |
165 | unsigned int cursor_chunk_size; | |
166 | unsigned int cursor_buffer_size; | |
167 | unsigned int max_num_wb; | |
168 | unsigned int max_dchub_pscl_bw_pix_per_clk; | |
169 | unsigned int max_pscl_lb_bw_pix_per_clk; | |
170 | unsigned int max_lb_vscl_bw_pix_per_clk; | |
171 | unsigned int max_vscl_hscl_bw_pix_per_clk; | |
172 | double max_hscl_ratio; | |
173 | double max_vscl_ratio; | |
174 | unsigned int hscl_mults; | |
175 | unsigned int vscl_mults; | |
176 | unsigned int max_hscl_taps; | |
177 | unsigned int max_vscl_taps; | |
178 | unsigned int xfc_supported; | |
728c0698 HW |
179 | unsigned int ptoi_supported; |
180 | unsigned int gfx7_compat_tiling_supported; | |
181 | ||
182 | bool odm_combine_4to1_supported; | |
183 | bool dynamic_metadata_vm_enabled; | |
184 | unsigned int max_num_hdmi_frl_outputs; | |
185 | ||
cba5e870 DL |
186 | unsigned int xfc_fill_constant_bytes; |
187 | double dispclk_ramp_margin_percent; | |
188 | double xfc_fill_bw_overhead_percent; | |
189 | double underscan_factor; | |
190 | unsigned int min_vblank_lines; | |
191 | unsigned int dppclk_delay_subtotal; | |
192 | unsigned int dispclk_delay_subtotal; | |
47b0c91f | 193 | double dcfclk_cstate_latency; |
cba5e870 DL |
194 | unsigned int dppclk_delay_scl; |
195 | unsigned int dppclk_delay_scl_lb_only; | |
196 | unsigned int dppclk_delay_cnvc_formatter; | |
197 | unsigned int dppclk_delay_cnvc_cursor; | |
198 | unsigned int is_line_buffer_bpp_fixed; | |
199 | unsigned int line_buffer_fixed_bpp; | |
200 | unsigned int dcc_supported; | |
6d04ee9d | 201 | |
061bfa06 HW |
202 | unsigned int IsLineBufferBppFixed; |
203 | unsigned int LineBufferFixedBpp; | |
061bfa06 HW |
204 | unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one; |
205 | unsigned int bug_forcing_LC_req_same_size_fixed; | |
206 | }; | |
207 | ||
6d04ee9d DL |
208 | struct _vcs_dpi_display_xfc_params_st { |
209 | double xfc_tslv_vready_offset_us; | |
210 | double xfc_tslv_vupdate_width_us; | |
211 | double xfc_tslv_vupdate_offset_us; | |
212 | int xfc_slv_chunk_size_bytes; | |
213 | }; | |
214 | ||
cba5e870 DL |
215 | struct _vcs_dpi_display_pipe_source_params_st { |
216 | int source_format; | |
217 | unsigned char dcc; | |
cba5e870 | 218 | unsigned int dcc_rate; |
5fc11598 | 219 | unsigned int dcc_rate_chroma; |
cba5e870 DL |
220 | unsigned char dcc_use_global; |
221 | unsigned char vm; | |
222 | bool gpuvm; // gpuvm enabled | |
223 | bool hostvm; // hostvm enabled | |
224 | bool gpuvm_levels_force_en; | |
225 | unsigned int gpuvm_levels_force; | |
226 | bool hostvm_levels_force_en; | |
227 | unsigned int hostvm_levels_force; | |
228 | int source_scan; | |
229 | int sw_mode; | |
230 | int macro_tile_size; | |
5fc11598 | 231 | unsigned int surface_width_y; |
71e6bd2a | 232 | unsigned int surface_height_y; |
5fc11598 DL |
233 | unsigned int surface_width_c; |
234 | unsigned int surface_height_c; | |
cba5e870 DL |
235 | unsigned int viewport_width; |
236 | unsigned int viewport_height; | |
237 | unsigned int viewport_y_y; | |
238 | unsigned int viewport_y_c; | |
239 | unsigned int viewport_width_c; | |
240 | unsigned int viewport_height_c; | |
241 | unsigned int data_pitch; | |
242 | unsigned int data_pitch_c; | |
243 | unsigned int meta_pitch; | |
244 | unsigned int meta_pitch_c; | |
245 | unsigned int cur0_src_width; | |
246 | int cur0_bpp; | |
247 | unsigned int cur1_src_width; | |
248 | int cur1_bpp; | |
249 | int num_cursors; | |
250 | unsigned char is_hsplit; | |
251 | unsigned char dynamic_metadata_enable; | |
252 | unsigned int dynamic_metadata_lines_before_active; | |
253 | unsigned int dynamic_metadata_xmit_bytes; | |
254 | unsigned int hsplit_grp; | |
255 | unsigned char xfc_enable; | |
256 | unsigned char xfc_slave; | |
728c0698 | 257 | unsigned char immediate_flip; |
6d04ee9d | 258 | struct _vcs_dpi_display_xfc_params_st xfc_params; |
0623fdb0 CL |
259 | //for vstartuplines calculation freesync |
260 | unsigned char v_total_min; | |
261 | unsigned char v_total_max; | |
6d04ee9d DL |
262 | }; |
263 | struct writeback_st { | |
264 | int wb_src_height; | |
728c0698 | 265 | int wb_src_width; |
6d04ee9d DL |
266 | int wb_dst_width; |
267 | int wb_dst_height; | |
268 | int wb_pixel_format; | |
269 | int wb_htaps_luma; | |
270 | int wb_vtaps_luma; | |
271 | int wb_htaps_chroma; | |
272 | int wb_vtaps_chroma; | |
f8931ea7 EB |
273 | double wb_hratio; |
274 | double wb_vratio; | |
6d04ee9d DL |
275 | }; |
276 | ||
cba5e870 DL |
277 | struct _vcs_dpi_display_output_params_st { |
278 | int dp_lanes; | |
486cc0ee | 279 | double output_bpp; |
cba5e870 DL |
280 | int dsc_enable; |
281 | int wb_enable; | |
282 | int num_active_wb; | |
283 | int output_bpc; | |
284 | int output_type; | |
285 | int output_format; | |
cba5e870 | 286 | int dsc_slices; |
3ab4cc65 | 287 | int max_audio_sample_rate; |
6d04ee9d DL |
288 | struct writeback_st wb; |
289 | }; | |
290 | ||
cba5e870 DL |
291 | struct _vcs_dpi_scaler_ratio_depth_st { |
292 | double hscl_ratio; | |
293 | double vscl_ratio; | |
294 | double hscl_ratio_c; | |
295 | double vscl_ratio_c; | |
296 | double vinit; | |
297 | double vinit_c; | |
298 | double vinit_bot; | |
299 | double vinit_bot_c; | |
300 | int lb_depth; | |
301 | int scl_enable; | |
302 | }; | |
303 | ||
304 | struct _vcs_dpi_scaler_taps_st { | |
305 | unsigned int htaps; | |
306 | unsigned int vtaps; | |
307 | unsigned int htaps_c; | |
308 | unsigned int vtaps_c; | |
309 | }; | |
310 | ||
311 | struct _vcs_dpi_display_pipe_dest_params_st { | |
312 | unsigned int recout_width; | |
313 | unsigned int recout_height; | |
314 | unsigned int full_recout_width; | |
315 | unsigned int full_recout_height; | |
316 | unsigned int hblank_start; | |
317 | unsigned int hblank_end; | |
318 | unsigned int vblank_start; | |
319 | unsigned int vblank_end; | |
320 | unsigned int htotal; | |
321 | unsigned int vtotal; | |
322 | unsigned int vactive; | |
323 | unsigned int hactive; | |
324 | unsigned int vstartup_start; | |
325 | unsigned int vupdate_offset; | |
326 | unsigned int vupdate_width; | |
327 | unsigned int vready_offset; | |
328 | unsigned char interlaced; | |
d5ac4ff2 | 329 | unsigned char embedded; |
cba5e870 DL |
330 | double pixel_rate_mhz; |
331 | unsigned char synchronized_vblank_all_planes; | |
332 | unsigned char otg_inst; | |
5fc11598 | 333 | unsigned int odm_combine; |
5fbac0a5 | 334 | unsigned char use_maximum_vstartup; |
0623fdb0 CL |
335 | unsigned int vtotal_max; |
336 | unsigned int vtotal_min; | |
cba5e870 DL |
337 | }; |
338 | ||
339 | struct _vcs_dpi_display_pipe_params_st { | |
340 | display_pipe_source_params_st src; | |
341 | display_pipe_dest_params_st dest; | |
342 | scaler_ratio_depth_st scale_ratio_depth; | |
343 | scaler_taps_st scale_taps; | |
344 | }; | |
345 | ||
346 | struct _vcs_dpi_display_clocks_and_cfg_st { | |
347 | int voltage; | |
348 | double dppclk_mhz; | |
349 | double refclk_mhz; | |
350 | double dispclk_mhz; | |
351 | double dcfclk_mhz; | |
352 | double socclk_mhz; | |
353 | }; | |
354 | ||
355 | struct _vcs_dpi_display_e2e_pipe_params_st { | |
356 | display_pipe_params_st pipe; | |
357 | display_output_params_st dout; | |
358 | display_clocks_and_cfg_st clks_cfg; | |
359 | }; | |
360 | ||
cba5e870 DL |
361 | struct _vcs_dpi_display_data_rq_misc_params_st { |
362 | unsigned int full_swath_bytes; | |
363 | unsigned int stored_swath_bytes; | |
364 | unsigned int blk256_height; | |
365 | unsigned int blk256_width; | |
366 | unsigned int req_height; | |
367 | unsigned int req_width; | |
368 | }; | |
369 | ||
370 | struct _vcs_dpi_display_data_rq_sizing_params_st { | |
371 | unsigned int chunk_bytes; | |
372 | unsigned int min_chunk_bytes; | |
373 | unsigned int meta_chunk_bytes; | |
374 | unsigned int min_meta_chunk_bytes; | |
375 | unsigned int mpte_group_bytes; | |
376 | unsigned int dpte_group_bytes; | |
377 | }; | |
378 | ||
379 | struct _vcs_dpi_display_data_rq_dlg_params_st { | |
380 | unsigned int swath_width_ub; | |
381 | unsigned int swath_height; | |
382 | unsigned int req_per_swath_ub; | |
383 | unsigned int meta_pte_bytes_per_frame_ub; | |
384 | unsigned int dpte_req_per_row_ub; | |
385 | unsigned int dpte_groups_per_row_ub; | |
386 | unsigned int dpte_row_height; | |
387 | unsigned int dpte_bytes_per_row_ub; | |
388 | unsigned int meta_chunks_per_row_ub; | |
389 | unsigned int meta_req_per_row_ub; | |
390 | unsigned int meta_row_height; | |
391 | unsigned int meta_bytes_per_row_ub; | |
392 | }; | |
393 | ||
cba5e870 DL |
394 | struct _vcs_dpi_display_rq_dlg_params_st { |
395 | display_data_rq_dlg_params_st rq_l; | |
396 | display_data_rq_dlg_params_st rq_c; | |
cba5e870 DL |
397 | }; |
398 | ||
399 | struct _vcs_dpi_display_rq_sizing_params_st { | |
400 | display_data_rq_sizing_params_st rq_l; | |
401 | display_data_rq_sizing_params_st rq_c; | |
402 | }; | |
403 | ||
404 | struct _vcs_dpi_display_rq_misc_params_st { | |
405 | display_data_rq_misc_params_st rq_l; | |
406 | display_data_rq_misc_params_st rq_c; | |
407 | }; | |
408 | ||
409 | struct _vcs_dpi_display_rq_params_st { | |
410 | unsigned char yuv420; | |
411 | unsigned char yuv420_10bpc; | |
71e6bd2a | 412 | unsigned char rgbe_alpha; |
cba5e870 DL |
413 | display_rq_misc_params_st misc; |
414 | display_rq_sizing_params_st sizing; | |
415 | display_rq_dlg_params_st dlg; | |
416 | }; | |
417 | ||
418 | struct _vcs_dpi_display_dlg_regs_st { | |
419 | unsigned int refcyc_h_blank_end; | |
420 | unsigned int dlg_vblank_end; | |
421 | unsigned int min_dst_y_next_start; | |
422 | unsigned int refcyc_per_htotal; | |
423 | unsigned int refcyc_x_after_scaler; | |
424 | unsigned int dst_y_after_scaler; | |
425 | unsigned int dst_y_prefetch; | |
426 | unsigned int dst_y_per_vm_vblank; | |
427 | unsigned int dst_y_per_row_vblank; | |
428 | unsigned int dst_y_per_vm_flip; | |
429 | unsigned int dst_y_per_row_flip; | |
430 | unsigned int ref_freq_to_pix_freq; | |
431 | unsigned int vratio_prefetch; | |
432 | unsigned int vratio_prefetch_c; | |
433 | unsigned int refcyc_per_pte_group_vblank_l; | |
434 | unsigned int refcyc_per_pte_group_vblank_c; | |
435 | unsigned int refcyc_per_meta_chunk_vblank_l; | |
436 | unsigned int refcyc_per_meta_chunk_vblank_c; | |
437 | unsigned int refcyc_per_pte_group_flip_l; | |
438 | unsigned int refcyc_per_pte_group_flip_c; | |
439 | unsigned int refcyc_per_meta_chunk_flip_l; | |
440 | unsigned int refcyc_per_meta_chunk_flip_c; | |
441 | unsigned int dst_y_per_pte_row_nom_l; | |
442 | unsigned int dst_y_per_pte_row_nom_c; | |
443 | unsigned int refcyc_per_pte_group_nom_l; | |
444 | unsigned int refcyc_per_pte_group_nom_c; | |
445 | unsigned int dst_y_per_meta_row_nom_l; | |
446 | unsigned int dst_y_per_meta_row_nom_c; | |
447 | unsigned int refcyc_per_meta_chunk_nom_l; | |
448 | unsigned int refcyc_per_meta_chunk_nom_c; | |
449 | unsigned int refcyc_per_line_delivery_pre_l; | |
450 | unsigned int refcyc_per_line_delivery_pre_c; | |
451 | unsigned int refcyc_per_line_delivery_l; | |
452 | unsigned int refcyc_per_line_delivery_c; | |
453 | unsigned int chunk_hdl_adjust_cur0; | |
454 | unsigned int chunk_hdl_adjust_cur1; | |
455 | unsigned int vready_after_vcount0; | |
456 | unsigned int dst_y_offset_cur0; | |
457 | unsigned int dst_y_offset_cur1; | |
458 | unsigned int xfc_reg_transfer_delay; | |
459 | unsigned int xfc_reg_precharge_delay; | |
460 | unsigned int xfc_reg_remote_surface_flip_latency; | |
461 | unsigned int xfc_reg_prefetch_margin; | |
462 | unsigned int dst_y_delta_drq_limit; | |
fb57452f DL |
463 | unsigned int refcyc_per_vm_group_vblank; |
464 | unsigned int refcyc_per_vm_group_flip; | |
465 | unsigned int refcyc_per_vm_req_vblank; | |
466 | unsigned int refcyc_per_vm_req_flip; | |
fbaf207f | 467 | unsigned int refcyc_per_vm_dmdata; |
cba5e870 DL |
468 | }; |
469 | ||
470 | struct _vcs_dpi_display_ttu_regs_st { | |
471 | unsigned int qos_level_low_wm; | |
472 | unsigned int qos_level_high_wm; | |
473 | unsigned int min_ttu_vblank; | |
474 | unsigned int qos_level_flip; | |
475 | unsigned int refcyc_per_req_delivery_l; | |
476 | unsigned int refcyc_per_req_delivery_c; | |
477 | unsigned int refcyc_per_req_delivery_cur0; | |
478 | unsigned int refcyc_per_req_delivery_cur1; | |
479 | unsigned int refcyc_per_req_delivery_pre_l; | |
480 | unsigned int refcyc_per_req_delivery_pre_c; | |
481 | unsigned int refcyc_per_req_delivery_pre_cur0; | |
482 | unsigned int refcyc_per_req_delivery_pre_cur1; | |
483 | unsigned int qos_level_fixed_l; | |
484 | unsigned int qos_level_fixed_c; | |
485 | unsigned int qos_level_fixed_cur0; | |
486 | unsigned int qos_level_fixed_cur1; | |
487 | unsigned int qos_ramp_disable_l; | |
488 | unsigned int qos_ramp_disable_c; | |
489 | unsigned int qos_ramp_disable_cur0; | |
490 | unsigned int qos_ramp_disable_cur1; | |
491 | }; | |
492 | ||
493 | struct _vcs_dpi_display_data_rq_regs_st { | |
494 | unsigned int chunk_size; | |
495 | unsigned int min_chunk_size; | |
496 | unsigned int meta_chunk_size; | |
497 | unsigned int min_meta_chunk_size; | |
498 | unsigned int dpte_group_size; | |
499 | unsigned int mpte_group_size; | |
500 | unsigned int swath_height; | |
501 | unsigned int pte_row_height_linear; | |
502 | }; | |
503 | ||
504 | struct _vcs_dpi_display_rq_regs_st { | |
505 | display_data_rq_regs_st rq_regs_l; | |
506 | display_data_rq_regs_st rq_regs_c; | |
507 | unsigned int drq_expansion_mode; | |
508 | unsigned int prq_expansion_mode; | |
509 | unsigned int mrq_expansion_mode; | |
510 | unsigned int crq_expansion_mode; | |
511 | unsigned int plane1_base_address; | |
512 | }; | |
513 | ||
514 | struct _vcs_dpi_display_dlg_sys_params_st { | |
515 | double t_mclk_wm_us; | |
516 | double t_urg_wm_us; | |
517 | double t_sr_wm_us; | |
518 | double t_extra_us; | |
519 | double mem_trip_us; | |
520 | double t_srx_delay_us; | |
521 | double deepsleep_dcfclk_mhz; | |
522 | double total_flip_bw; | |
523 | unsigned int total_flip_bytes; | |
524 | }; | |
525 | ||
cba5e870 DL |
526 | struct _vcs_dpi_display_arb_params_st { |
527 | int max_req_outstanding; | |
528 | int min_req_outstanding; | |
529 | int sat_level_us; | |
061bfa06 HW |
530 | }; |
531 | ||
532 | #endif /*__DISPLAY_MODE_STRUCTS_H__*/ |