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235c6763 AP |
1 | /* |
2 | * Copyright 2022 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | ||
26 | #include "dce110/dce110_hw_sequencer.h" | |
27 | #include "dcn10/dcn10_hw_sequencer.h" | |
28 | #include "dcn20/dcn20_hwseq.h" | |
29 | #include "dcn21/dcn21_hwseq.h" | |
30 | #include "dcn30/dcn30_hwseq.h" | |
31 | #include "dcn31/dcn31_hwseq.h" | |
32 | #include "dcn32_hwseq.h" | |
33 | ||
34 | static const struct hw_sequencer_funcs dcn32_funcs = { | |
35 | .program_gamut_remap = dcn10_program_gamut_remap, | |
36 | .init_hw = dcn32_init_hw, | |
37 | .apply_ctx_to_hw = dce110_apply_ctx_to_hw, | |
38 | .apply_ctx_for_surface = NULL, | |
39 | .program_front_end_for_ctx = dcn20_program_front_end_for_ctx, | |
40 | .wait_for_pending_cleared = dcn10_wait_for_pending_cleared, | |
41 | .post_unlock_program_front_end = dcn20_post_unlock_program_front_end, | |
42 | .update_plane_addr = dcn20_update_plane_addr, | |
43 | .update_dchub = dcn10_update_dchub, | |
44 | .update_pending_status = dcn10_update_pending_status, | |
45 | .program_output_csc = dcn20_program_output_csc, | |
46 | .enable_accelerated_mode = dce110_enable_accelerated_mode, | |
47 | .enable_timing_synchronization = dcn10_enable_timing_synchronization, | |
48 | .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset, | |
49 | .update_info_frame = dcn31_update_info_frame, | |
50 | .send_immediate_sdp_message = dcn10_send_immediate_sdp_message, | |
51 | .enable_stream = dcn20_enable_stream, | |
52 | .disable_stream = dce110_disable_stream, | |
88ef4c5b | 53 | .unblank_stream = dcn32_unblank_stream, |
235c6763 AP |
54 | .blank_stream = dce110_blank_stream, |
55 | .enable_audio_stream = dce110_enable_audio_stream, | |
56 | .disable_audio_stream = dce110_disable_audio_stream, | |
57 | .disable_plane = dcn20_disable_plane, | |
58 | .pipe_control_lock = dcn20_pipe_control_lock, | |
59 | .interdependent_update_lock = dcn10_lock_all_pipes, | |
60 | .cursor_lock = dcn10_cursor_lock, | |
bbb6e5ae | 61 | .prepare_bandwidth = dcn30_prepare_bandwidth, |
235c6763 AP |
62 | .optimize_bandwidth = dcn20_optimize_bandwidth, |
63 | .update_bandwidth = dcn20_update_bandwidth, | |
64 | .set_drr = dcn10_set_drr, | |
65 | .get_position = dcn10_get_position, | |
66 | .set_static_screen_control = dcn10_set_static_screen_control, | |
67 | .setup_stereo = dcn10_setup_stereo, | |
68 | .set_avmute = dcn30_set_avmute, | |
69 | .log_hw_state = dcn10_log_hw_state, | |
70 | .get_hw_state = dcn10_get_hw_state, | |
71 | .clear_status_bits = dcn10_clear_status_bits, | |
72 | .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect, | |
73 | .edp_backlight_control = dce110_edp_backlight_control, | |
74 | .edp_power_control = dce110_edp_power_control, | |
75 | .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, | |
76 | .edp_wait_for_T12 = dce110_edp_wait_for_T12, | |
77 | .set_cursor_position = dcn10_set_cursor_position, | |
78 | .set_cursor_attribute = dcn10_set_cursor_attribute, | |
79 | .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level, | |
80 | .setup_periodic_interrupt = dcn10_setup_periodic_interrupt, | |
81 | .set_clock = dcn10_set_clock, | |
82 | .get_clock = dcn10_get_clock, | |
83 | .program_triplebuffer = dcn20_program_triple_buffer, | |
84 | .enable_writeback = dcn30_enable_writeback, | |
85 | .disable_writeback = dcn30_disable_writeback, | |
86 | .update_writeback = dcn30_update_writeback, | |
87 | .mmhubbub_warmup = dcn30_mmhubbub_warmup, | |
88 | .dmdata_status_done = dcn20_dmdata_status_done, | |
89 | .program_dmdata_engine = dcn30_program_dmdata_engine, | |
90 | .set_dmdata_attributes = dcn20_set_dmdata_attributes, | |
91 | .init_sys_ctx = dcn20_init_sys_ctx, | |
92 | .init_vm_ctx = dcn20_init_vm_ctx, | |
93 | .set_flip_control_gsl = dcn20_set_flip_control_gsl, | |
94 | .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync, | |
95 | .calc_vupdate_position = dcn10_calc_vupdate_position, | |
96 | .apply_idle_power_optimizations = dcn32_apply_idle_power_optimizations, | |
97 | .does_plane_fit_in_mall = dcn30_does_plane_fit_in_mall, | |
98 | .set_backlight_level = dcn21_set_backlight_level, | |
99 | .set_abm_immediate_disable = dcn21_set_abm_immediate_disable, | |
100 | .hardware_release = dcn30_hardware_release, | |
101 | .set_pipe = dcn21_set_pipe, | |
102 | .set_disp_pattern_generator = dcn30_set_disp_pattern_generator, | |
103 | .get_dcc_en_bits = dcn10_get_dcc_en_bits, | |
104 | .commit_subvp_config = dcn32_commit_subvp_config, | |
85f4bc0c | 105 | .subvp_pipe_control_lock = dcn32_subvp_pipe_control_lock, |
235c6763 | 106 | .update_visual_confirm_color = dcn20_update_visual_confirm_color, |
594b237b | 107 | .update_phy_state = dcn32_update_phy_state, |
235c6763 AP |
108 | }; |
109 | ||
110 | static const struct hwseq_private_funcs dcn32_private_funcs = { | |
111 | .init_pipes = dcn10_init_pipes, | |
112 | .update_plane_addr = dcn20_update_plane_addr, | |
113 | .plane_atomic_disconnect = dcn10_plane_atomic_disconnect, | |
114 | .update_mpcc = dcn20_update_mpcc, | |
90f33674 | 115 | .set_input_transfer_func = dcn32_set_input_transfer_func, |
235c6763 AP |
116 | .set_output_transfer_func = dcn32_set_output_transfer_func, |
117 | .power_down = dce110_power_down, | |
118 | .enable_display_power_gating = dcn10_dummy_display_power_gating, | |
119 | .blank_pixel_data = dcn20_blank_pixel_data, | |
120 | .reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap, | |
121 | .enable_stream_timing = dcn20_enable_stream_timing, | |
122 | .edp_backlight_control = dce110_edp_backlight_control, | |
123 | .disable_stream_gating = dcn20_disable_stream_gating, | |
124 | .enable_stream_gating = dcn20_enable_stream_gating, | |
125 | .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt, | |
126 | .did_underflow_occur = dcn10_did_underflow_occur, | |
127 | .init_blank = dcn20_init_blank, | |
128 | .disable_vga = dcn20_disable_vga, | |
129 | .bios_golden_init = dcn10_bios_golden_init, | |
130 | .plane_atomic_disable = dcn20_plane_atomic_disable, | |
131 | .plane_atomic_power_down = dcn10_plane_atomic_power_down, | |
132 | .enable_power_gating_plane = dcn32_enable_power_gating_plane, | |
133 | .hubp_pg_control = dcn32_hubp_pg_control, | |
134 | .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, | |
135 | .update_odm = dcn32_update_odm, | |
136 | .dsc_pg_control = dcn32_dsc_pg_control, | |
137 | .set_hdr_multiplier = dcn10_set_hdr_multiplier, | |
138 | .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, | |
139 | .wait_for_blank_complete = dcn20_wait_for_blank_complete, | |
140 | .dccg_init = dcn20_dccg_init, | |
90f33674 | 141 | .set_mcm_luts = dcn32_set_mcm_luts, |
235c6763 AP |
142 | .program_mall_pipe_config = dcn32_program_mall_pipe_config, |
143 | .subvp_update_force_pstate = dcn32_subvp_update_force_pstate, | |
144 | .update_mall_sel = dcn32_update_mall_sel, | |
49f59499 | 145 | .calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values, |
64a30aaf | 146 | .set_pixels_per_cycle = dcn32_set_pixels_per_cycle, |
88ef4c5b | 147 | .is_dp_dig_pixel_rate_div_policy = dcn32_is_dp_dig_pixel_rate_div_policy, |
235c6763 AP |
148 | }; |
149 | ||
150 | void dcn32_hw_sequencer_init_functions(struct dc *dc) | |
151 | { | |
152 | dc->hwss = dcn32_funcs; | |
153 | dc->hwseq->funcs = dcn32_private_funcs; | |
154 | ||
155 | if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { | |
156 | dc->hwss.init_hw = dcn20_fpga_init_hw; | |
157 | dc->hwseq->funcs.init_pipes = NULL; | |
158 | } | |
159 | } |