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drm/amd/display: Revert adding degamma coefficients
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / dc / dcn31 / dcn31_resource.c
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2083640f
NK		 1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27#include "dm_services.h"
28#include "dc.h"
29
30#include "dcn31/dcn31_init.h"
31
32#include "resource.h"
33#include "include/irq_service_interface.h"
34#include "dcn31_resource.h"
35
36#include "dcn20/dcn20_resource.h"
37#include "dcn30/dcn30_resource.h"
38
39#include "dcn10/dcn10_ipp.h"
40#include "dcn30/dcn30_hubbub.h"
41#include "dcn31/dcn31_hubbub.h"
42#include "dcn30/dcn30_mpc.h"
43#include "dcn31/dcn31_hubp.h"
44#include "irq/dcn31/irq_service_dcn31.h"
45#include "dcn30/dcn30_dpp.h"
46#include "dcn31/dcn31_optc.h"
47#include "dcn20/dcn20_hwseq.h"
48#include "dcn30/dcn30_hwseq.h"
49#include "dce110/dce110_hw_sequencer.h"
50#include "dcn30/dcn30_opp.h"
51#include "dcn20/dcn20_dsc.h"
52#include "dcn30/dcn30_vpg.h"
53#include "dcn30/dcn30_afmt.h"
54#include "dcn30/dcn30_dio_stream_encoder.h"
83228ebb 55#include "dcn31/dcn31_hpo_dp_stream_encoder.h"
3bc8d921 56#include "dcn31/dcn31_hpo_dp_link_encoder.h"
61452908 57#include "dcn31/dcn31_apg.h"
2083640f
NK		 58#include "dcn31/dcn31_dio_link_encoder.h"
59#include "dce/dce_clock_source.h"
60#include "dce/dce_audio.h"
61#include "dce/dce_hwseq.h"
62#include "clk_mgr.h"
63#include "virtual/virtual_stream_encoder.h"
64#include "dce110/dce110_resource.h"
65#include "dml/display_mode_vba.h"
66#include "dcn31/dcn31_dccg.h"
67#include "dcn10/dcn10_resource.h"
68#include "dcn31_panel_cntl.h"
69
70#include "dcn30/dcn30_dwb.h"
71#include "dcn30/dcn30_mmhubbub.h"
72
73// TODO: change include headers /amd/include/asic_reg after upstream
74#include "yellow_carp_offset.h"
75#include "dcn/dcn_3_1_2_offset.h"
76#include "dcn/dcn_3_1_2_sh_mask.h"
77#include "nbio/nbio_7_2_0_offset.h"
78#include "dpcs/dpcs_4_2_0_offset.h"
79#include "dpcs/dpcs_4_2_0_sh_mask.h"
80#include "mmhub/mmhub_2_3_0_offset.h"
81#include "mmhub/mmhub_2_3_0_sh_mask.h"
82
83
84#define regDCHUBBUB_DEBUG_CTRL_0 0x04d6
85#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2
86#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10
87#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L
88
89#include "reg_helper.h"
90#include "dce/dmub_abm.h"
91#include "dce/dmub_psr.h"
92#include "dce/dce_aux.h"
93#include "dce/dce_i2c.h"
94
95#include "dml/dcn30/display_mode_vba_30.h"
96#include "vm_helper.h"
97#include "dcn20/dcn20_vmid.h"
98
99#include "link_enc_cfg.h"
100
101#define DC_LOGGER_INIT(logger)
102#define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
103#define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
104
105#define DCN3_1_DEFAULT_DET_SIZE 384
106
107struct _vcs_dpi_ip_params_st dcn3_1_ip = {
108 .gpuvm_enable = 1,
109 .gpuvm_max_page_table_levels = 1,
110 .hostvm_enable = 1,
111 .hostvm_max_page_table_levels = 2,
112 .rob_buffer_size_kbytes = 64,
113 .det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE,
114 .config_return_buffer_size_in_kbytes = 1792,
115 .compressed_buffer_segment_size_in_kbytes = 64,
116 .meta_fifo_size_in_kentries = 32,
117 .zero_size_buffer_entries = 512,
118 .compbuf_reserved_space_64b = 256,
119 .compbuf_reserved_space_zs = 64,
120 .dpp_output_buffer_pixels = 2560,
121 .opp_output_buffer_lines = 1,
122 .pixel_chunk_size_kbytes = 8,
123 .meta_chunk_size_kbytes = 2,
124 .min_meta_chunk_size_bytes = 256,
125 .writeback_chunk_size_kbytes = 8,
126 .ptoi_supported = false,
127 .num_dsc = 3,
128 .maximum_dsc_bits_per_component = 10,
129 .dsc422_native_support = false,
130 .is_line_buffer_bpp_fixed = true,
131 .line_buffer_fixed_bpp = 48,
132 .line_buffer_size_bits = 789504,
133 .max_line_buffer_lines = 12,
134 .writeback_interface_buffer_size_kbytes = 90,
135 .max_num_dpp = 4,
136 .max_num_otg = 4,
137 .max_num_hdmi_frl_outputs = 1,
138 .max_num_wb = 1,
139 .max_dchub_pscl_bw_pix_per_clk = 4,
140 .max_pscl_lb_bw_pix_per_clk = 2,
141 .max_lb_vscl_bw_pix_per_clk = 4,
142 .max_vscl_hscl_bw_pix_per_clk = 4,
143 .max_hscl_ratio = 6,
144 .max_vscl_ratio = 6,
145 .max_hscl_taps = 8,
146 .max_vscl_taps = 8,
147 .dpte_buffer_size_in_pte_reqs_luma = 64,
148 .dpte_buffer_size_in_pte_reqs_chroma = 34,
149 .dispclk_ramp_margin_percent = 1,
150 .max_inter_dcn_tile_repeaters = 8,
151 .cursor_buffer_size = 16,
152 .cursor_chunk_size = 2,
153 .writeback_line_buffer_buffer_size = 0,
154 .writeback_min_hscl_ratio = 1,
155 .writeback_min_vscl_ratio = 1,
156 .writeback_max_hscl_ratio = 1,
157 .writeback_max_vscl_ratio = 1,
158 .writeback_max_hscl_taps = 1,
159 .writeback_max_vscl_taps = 1,
160 .dppclk_delay_subtotal = 46,
161 .dppclk_delay_scl = 50,
162 .dppclk_delay_scl_lb_only = 16,
163 .dppclk_delay_cnvc_formatter = 27,
164 .dppclk_delay_cnvc_cursor = 6,
165 .dispclk_delay_subtotal = 119,
166 .dynamic_metadata_vm_enabled = false,
167 .odm_combine_4to1_supported = false,
168 .dcc_supported = true,
169};
170
171struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = {
172 /*TODO: correct dispclk/dppclk voltage level determination*/
173 .clock_limits = {
174 {
175 .state = 0,
176 .dispclk_mhz = 1200.0,
177 .dppclk_mhz = 1200.0,
178 .phyclk_mhz = 600.0,
179 .phyclk_d18_mhz = 667.0,
180 .dscclk_mhz = 186.0,
181 .dtbclk_mhz = 625.0,
182 },
183 {
184 .state = 1,
185 .dispclk_mhz = 1200.0,
186 .dppclk_mhz = 1200.0,
187 .phyclk_mhz = 810.0,
188 .phyclk_d18_mhz = 667.0,
189 .dscclk_mhz = 209.0,
190 .dtbclk_mhz = 625.0,
191 },
192 {
193 .state = 2,
194 .dispclk_mhz = 1200.0,
195 .dppclk_mhz = 1200.0,
196 .phyclk_mhz = 810.0,
197 .phyclk_d18_mhz = 667.0,
198 .dscclk_mhz = 209.0,
199 .dtbclk_mhz = 625.0,
200 },
201 {
202 .state = 3,
203 .dispclk_mhz = 1200.0,
204 .dppclk_mhz = 1200.0,
205 .phyclk_mhz = 810.0,
206 .phyclk_d18_mhz = 667.0,
207 .dscclk_mhz = 371.0,
208 .dtbclk_mhz = 625.0,
209 },
210 {
211 .state = 4,
212 .dispclk_mhz = 1200.0,
213 .dppclk_mhz = 1200.0,
214 .phyclk_mhz = 810.0,
215 .phyclk_d18_mhz = 667.0,
216 .dscclk_mhz = 417.0,
217 .dtbclk_mhz = 625.0,
218 },
219 },
220 .num_states = 5,
221 .sr_exit_time_us = 9.0,
222 .sr_enter_plus_exit_time_us = 11.0,
223 .sr_exit_z8_time_us = 402.0,
224 .sr_enter_plus_exit_z8_time_us = 520.0,
225 .writeback_latency_us = 12.0,
a8e380fd 226 .dram_channel_width_bytes = 4,
2083640f
NK		 227 .round_trip_ping_latency_dcfclk_cycles = 106,
228 .urgent_latency_pixel_data_only_us = 4.0,
229 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
230 .urgent_latency_vm_data_only_us = 4.0,
231 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
232 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
233 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
234 .pct_ideal_sdp_bw_after_urgent = 80.0,
235 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0,
236 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
237 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,
238 .max_avg_sdp_bw_use_normal_percent = 60.0,
239 .max_avg_dram_bw_use_normal_percent = 60.0,
240 .fabric_datapath_to_dcn_data_return_bytes = 32,
241 .return_bus_width_bytes = 64,
242 .downspread_percent = 0.38,
243 .dcn_downspread_percent = 0.5,
244 .gpuvm_min_page_size_bytes = 4096,
245 .hostvm_min_page_size_bytes = 4096,
246 .do_urgent_latency_adjustment = false,
247 .urgent_latency_adjustment_fabric_clock_component_us = 0,
248 .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
249};
250
251enum dcn31_clk_src_array_id {
252 DCN31_CLK_SRC_PLL0,
253 DCN31_CLK_SRC_PLL1,
254 DCN31_CLK_SRC_PLL2,
255 DCN31_CLK_SRC_PLL3,
256 DCN31_CLK_SRC_PLL4,
257 DCN30_CLK_SRC_TOTAL
258};
259
260/* begin *********************
261 * macros to expend register list macro defined in HW object header file
262 */
263
264/* DCN */
265/* TODO awful hack. fixup dcn20_dwb.h */
266#undef BASE_INNER
267#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
268
269#define BASE(seg) BASE_INNER(seg)
270
271#define SR(reg_name)\
272 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
273 reg ## reg_name
274
275#define SRI(reg_name, block, id)\
276 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
277 reg ## block ## id ## _ ## reg_name
278
279#define SRI2(reg_name, block, id)\
280 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
281 reg ## reg_name
282
283#define SRIR(var_name, reg_name, block, id)\
284 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
285 reg ## block ## id ## _ ## reg_name
286
287#define SRII(reg_name, block, id)\
288 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
289 reg ## block ## id ## _ ## reg_name
290
291#define SRII_MPC_RMU(reg_name, block, id)\
292 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
293 reg ## block ## id ## _ ## reg_name
294
295#define SRII_DWB(reg_name, temp_name, block, id)\
296 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
297 reg ## block ## id ## _ ## temp_name
298
299#define DCCG_SRII(reg_name, block, id)\
300 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
301 reg ## block ## id ## _ ## reg_name
302
303#define VUPDATE_SRII(reg_name, block, id)\
304 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
305 reg ## reg_name ## _ ## block ## id
306
307/* NBIO */
308#define NBIO_BASE_INNER(seg) \
309 NBIO_BASE__INST0_SEG ## seg
310
311#define NBIO_BASE(seg) \
312 NBIO_BASE_INNER(seg)
313
314#define NBIO_SR(reg_name)\
315 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
316 regBIF_BX1_ ## reg_name
317
318/* MMHUB */
319#define MMHUB_BASE_INNER(seg) \
320 MMHUB_BASE__INST0_SEG ## seg
321
322#define MMHUB_BASE(seg) \
323 MMHUB_BASE_INNER(seg)
324
325#define MMHUB_SR(reg_name)\
326 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
327 mm ## reg_name
328
329/* CLOCK */
330#define CLK_BASE_INNER(seg) \
331 CLK_BASE__INST0_SEG ## seg
332
333#define CLK_BASE(seg) \
334 CLK_BASE_INNER(seg)
335
336#define CLK_SRI(reg_name, block, inst)\
337 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
338 reg ## block ## _ ## inst ## _ ## reg_name
339
340
341static const struct bios_registers bios_regs = {
342 NBIO_SR(BIOS_SCRATCH_3),
343 NBIO_SR(BIOS_SCRATCH_6)
344};
345
346#define clk_src_regs(index, pllid)\
347[index] = {\
348 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
349}
350
351static const struct dce110_clk_src_regs clk_src_regs[] = {
352 clk_src_regs(0, A),
353 clk_src_regs(1, B),
354 clk_src_regs(2, C),
355 clk_src_regs(3, D),
356 clk_src_regs(4, E)
357};
358
359static const struct dce110_clk_src_shift cs_shift = {
360 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
361};
362
363static const struct dce110_clk_src_mask cs_mask = {
364 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
365};
366
367#define abm_regs(id)\
368[id] = {\
b5ce6fe8 369 ABM_DCN302_REG_LIST(id)\
2083640f
NK		 370}
371
372static const struct dce_abm_registers abm_regs[] = {
373 abm_regs(0),
374 abm_regs(1),
375 abm_regs(2),
376 abm_regs(3),
377};
378
379static const struct dce_abm_shift abm_shift = {
380 ABM_MASK_SH_LIST_DCN30(__SHIFT)
381};
382
383static const struct dce_abm_mask abm_mask = {
384 ABM_MASK_SH_LIST_DCN30(_MASK)
385};
386
387#define audio_regs(id)\
388[id] = {\
389 AUD_COMMON_REG_LIST(id)\
390}
391
392static const struct dce_audio_registers audio_regs[] = {
393 audio_regs(0),
394 audio_regs(1),
395 audio_regs(2),
396 audio_regs(3),
397 audio_regs(4),
398 audio_regs(5),
399 audio_regs(6)
400};
401
402#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
403 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
404 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
405 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
406
407static const struct dce_audio_shift audio_shift = {
408 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
409};
410
411static const struct dce_audio_mask audio_mask = {
412 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
413};
414
415#define vpg_regs(id)\
416[id] = {\
417 VPG_DCN3_REG_LIST(id)\
418}
419
420static const struct dcn30_vpg_registers vpg_regs[] = {
421 vpg_regs(0),
422 vpg_regs(1),
423 vpg_regs(2),
424 vpg_regs(3),
425 vpg_regs(4),
426 vpg_regs(5),
427 vpg_regs(6),
428 vpg_regs(7),
429 vpg_regs(8),
430 vpg_regs(9),
431};
432
433static const struct dcn30_vpg_shift vpg_shift = {
434 DCN3_VPG_MASK_SH_LIST(__SHIFT)
435};
436
437static const struct dcn30_vpg_mask vpg_mask = {
438 DCN3_VPG_MASK_SH_LIST(_MASK)
439};
440
441#define afmt_regs(id)\
442[id] = {\
443 AFMT_DCN3_REG_LIST(id)\
444}
445
446static const struct dcn30_afmt_registers afmt_regs[] = {
447 afmt_regs(0),
448 afmt_regs(1),
449 afmt_regs(2),
450 afmt_regs(3),
451 afmt_regs(4),
452 afmt_regs(5)
453};
454
455static const struct dcn30_afmt_shift afmt_shift = {
456 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
457};
458
459static const struct dcn30_afmt_mask afmt_mask = {
460 DCN3_AFMT_MASK_SH_LIST(_MASK)
461};
462
61452908
FZ		 463#define apg_regs(id)\
464[id] = {\
465 APG_DCN31_REG_LIST(id)\
466}
467
468static const struct dcn31_apg_registers apg_regs[] = {
469 apg_regs(0),
470 apg_regs(1),
471 apg_regs(2),
472 apg_regs(3)
473};
474
475static const struct dcn31_apg_shift apg_shift = {
476 DCN31_APG_MASK_SH_LIST(__SHIFT)
477};
478
479static const struct dcn31_apg_mask apg_mask = {
480 DCN31_APG_MASK_SH_LIST(_MASK)
481};
482
2083640f
NK		 483#define stream_enc_regs(id)\
484[id] = {\
485 SE_DCN3_REG_LIST(id)\
486}
487
488static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
489 stream_enc_regs(0),
490 stream_enc_regs(1),
491 stream_enc_regs(2),
492 stream_enc_regs(3),
493 stream_enc_regs(4)
494};
495
496static const struct dcn10_stream_encoder_shift se_shift = {
497 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
498};
499
500static const struct dcn10_stream_encoder_mask se_mask = {
501 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
502};
503
504
505#define aux_regs(id)\
506[id] = {\
507 DCN2_AUX_REG_LIST(id)\
508}
509
510static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
511 aux_regs(0),
512 aux_regs(1),
513 aux_regs(2),
514 aux_regs(3),
515 aux_regs(4)
516};
517
518#define hpd_regs(id)\
519[id] = {\
520 HPD_REG_LIST(id)\
521}
522
523static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
524 hpd_regs(0),
525 hpd_regs(1),
526 hpd_regs(2),
527 hpd_regs(3),
528 hpd_regs(4)
529};
530
531#define link_regs(id, phyid)\
532[id] = {\
533 LE_DCN31_REG_LIST(id), \
534 UNIPHY_DCN2_REG_LIST(phyid), \
535 DPCS_DCN31_REG_LIST(id), \
536}
537
538static const struct dce110_aux_registers_shift aux_shift = {
539 DCN_AUX_MASK_SH_LIST(__SHIFT)
540};
541
542static const struct dce110_aux_registers_mask aux_mask = {
543 DCN_AUX_MASK_SH_LIST(_MASK)
544};
545
546static const struct dcn10_link_enc_registers link_enc_regs[] = {
547 link_regs(0, A),
548 link_regs(1, B),
549 link_regs(2, C),
550 link_regs(3, D),
551 link_regs(4, E)
552};
553
554static const struct dcn10_link_enc_shift le_shift = {
555 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
556 DPCS_DCN31_MASK_SH_LIST(__SHIFT)
557};
558
559static const struct dcn10_link_enc_mask le_mask = {
560 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
561 DPCS_DCN31_MASK_SH_LIST(_MASK)
562};
563
83228ebb
FZ		 564#define hpo_dp_stream_encoder_reg_list(id)\
565[id] = {\
566 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
567}
568
569static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
570 hpo_dp_stream_encoder_reg_list(0),
571 hpo_dp_stream_encoder_reg_list(1),
572 hpo_dp_stream_encoder_reg_list(2),
573 hpo_dp_stream_encoder_reg_list(3),
574};
575
576static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
577 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
578};
579
580static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
581 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
582};
583
3bc8d921
FZ		 584#define hpo_dp_link_encoder_reg_list(id)\
585[id] = {\
586 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
587 DCN3_1_RDPCSTX_REG_LIST(0),\
588 DCN3_1_RDPCSTX_REG_LIST(1),\
589 DCN3_1_RDPCSTX_REG_LIST(2),\
590 DCN3_1_RDPCSTX_REG_LIST(3),\
591 DCN3_1_RDPCSTX_REG_LIST(4)\
592}
593
594static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
595 hpo_dp_link_encoder_reg_list(0),
596 hpo_dp_link_encoder_reg_list(1),
597};
598
599static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
600 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
601};
602
603static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
604 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
605};
606
f01ee019
FZ		 607#define dpp_regs(id)\
608[id] = {\
609 DPP_REG_LIST_DCN30(id),\
610}
611
2083640f
NK		 612static const struct dcn3_dpp_registers dpp_regs[] = {
613 dpp_regs(0),
614 dpp_regs(1),
615 dpp_regs(2),
616 dpp_regs(3)
617};
618
619static const struct dcn3_dpp_shift tf_shift = {
620 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
621};
622
623static const struct dcn3_dpp_mask tf_mask = {
624 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
625};
626
627#define opp_regs(id)\
628[id] = {\
629 OPP_REG_LIST_DCN30(id),\
630}
631
632static const struct dcn20_opp_registers opp_regs[] = {
633 opp_regs(0),
634 opp_regs(1),
635 opp_regs(2),
636 opp_regs(3)
637};
638
639static const struct dcn20_opp_shift opp_shift = {
640 OPP_MASK_SH_LIST_DCN20(__SHIFT)
641};
642
643static const struct dcn20_opp_mask opp_mask = {
644 OPP_MASK_SH_LIST_DCN20(_MASK)
645};
646
647#define aux_engine_regs(id)\
648[id] = {\
649 AUX_COMMON_REG_LIST0(id), \
650 .AUXN_IMPCAL = 0, \
651 .AUXP_IMPCAL = 0, \
652 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
653}
654
655static const struct dce110_aux_registers aux_engine_regs[] = {
656 aux_engine_regs(0),
657 aux_engine_regs(1),
658 aux_engine_regs(2),
659 aux_engine_regs(3),
660 aux_engine_regs(4)
661};
662
663#define dwbc_regs_dcn3(id)\
664[id] = {\
665 DWBC_COMMON_REG_LIST_DCN30(id),\
666}
667
668static const struct dcn30_dwbc_registers dwbc30_regs[] = {
669 dwbc_regs_dcn3(0),
670};
671
672static const struct dcn30_dwbc_shift dwbc30_shift = {
673 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
674};
675
676static const struct dcn30_dwbc_mask dwbc30_mask = {
677 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
678};
679
680#define mcif_wb_regs_dcn3(id)\
681[id] = {\
682 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
683}
684
685static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
686 mcif_wb_regs_dcn3(0)
687};
688
689static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
690 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
691};
692
693static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
694 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
695};
696
697#define dsc_regsDCN20(id)\
698[id] = {\
699 DSC_REG_LIST_DCN20(id)\
700}
701
702static const struct dcn20_dsc_registers dsc_regs[] = {
703 dsc_regsDCN20(0),
704 dsc_regsDCN20(1),
705 dsc_regsDCN20(2)
706};
707
708static const struct dcn20_dsc_shift dsc_shift = {
709 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
710};
711
712static const struct dcn20_dsc_mask dsc_mask = {
713 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
714};
715
716static const struct dcn30_mpc_registers mpc_regs = {
717 MPC_REG_LIST_DCN3_0(0),
718 MPC_REG_LIST_DCN3_0(1),
719 MPC_REG_LIST_DCN3_0(2),
720 MPC_REG_LIST_DCN3_0(3),
721 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
722 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
723 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
724 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
725 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
726 MPC_RMU_REG_LIST_DCN3AG(0),
727 MPC_RMU_REG_LIST_DCN3AG(1),
728 //MPC_RMU_REG_LIST_DCN3AG(2),
729 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
730};
731
732static const struct dcn30_mpc_shift mpc_shift = {
733 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
734};
735
736static const struct dcn30_mpc_mask mpc_mask = {
737 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
738};
739
740#define optc_regs(id)\
741[id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
742
743static const struct dcn_optc_registers optc_regs[] = {
744 optc_regs(0),
745 optc_regs(1),
746 optc_regs(2),
747 optc_regs(3)
748};
749
750static const struct dcn_optc_shift optc_shift = {
751 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
752};
753
754static const struct dcn_optc_mask optc_mask = {
755 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
756};
757
758#define hubp_regs(id)\
759[id] = {\
760 HUBP_REG_LIST_DCN30(id)\
761}
762
763static const struct dcn_hubp2_registers hubp_regs[] = {
764 hubp_regs(0),
765 hubp_regs(1),
766 hubp_regs(2),
767 hubp_regs(3)
768};
769
770
771static const struct dcn_hubp2_shift hubp_shift = {
772 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
773};
774
775static const struct dcn_hubp2_mask hubp_mask = {
776 HUBP_MASK_SH_LIST_DCN31(_MASK)
777};
778static const struct dcn_hubbub_registers hubbub_reg = {
779 HUBBUB_REG_LIST_DCN31(0)
780};
781
782static const struct dcn_hubbub_shift hubbub_shift = {
783 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
784};
785
786static const struct dcn_hubbub_mask hubbub_mask = {
787 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
788};
789
790static const struct dccg_registers dccg_regs = {
791 DCCG_REG_LIST_DCN31()
792};
793
794static const struct dccg_shift dccg_shift = {
795 DCCG_MASK_SH_LIST_DCN31(__SHIFT)
796};
797
798static const struct dccg_mask dccg_mask = {
799 DCCG_MASK_SH_LIST_DCN31(_MASK)
800};
801
802
803#define SRII2(reg_name_pre, reg_name_post, id)\
804 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
805 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
806 reg ## reg_name_pre ## id ## _ ## reg_name_post
807
808
809#define HWSEQ_DCN31_REG_LIST()\
810 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
32f1d0cf 811 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
2083640f
NK		 812 SR(DIO_MEM_PWR_CTRL), \
813 SR(ODM_MEM_PWR_CTRL3), \
814 SR(DMU_MEM_PWR_CNTL), \
815 SR(MMHUBBUB_MEM_PWR_CNTL), \
816 SR(DCCG_GATE_DISABLE_CNTL), \
817 SR(DCCG_GATE_DISABLE_CNTL2), \
818 SR(DCFCLK_CNTL),\
819 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
820 SRII(PIXEL_RATE_CNTL, OTG, 0), \
821 SRII(PIXEL_RATE_CNTL, OTG, 1),\
822 SRII(PIXEL_RATE_CNTL, OTG, 2),\
823 SRII(PIXEL_RATE_CNTL, OTG, 3),\
824 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
825 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
826 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
827 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
828 SR(MICROSECOND_TIME_BASE_DIV), \
829 SR(MILLISECOND_TIME_BASE_DIV), \
830 SR(DISPCLK_FREQ_CHANGE_CNTL), \
831 SR(RBBMIF_TIMEOUT_DIS), \
832 SR(RBBMIF_TIMEOUT_DIS_2), \
833 SR(DCHUBBUB_CRC_CTRL), \
834 SR(DPP_TOP0_DPP_CRC_CTRL), \
835 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
836 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
837 SR(MPC_CRC_CTRL), \
838 SR(MPC_CRC_RESULT_GB), \
839 SR(MPC_CRC_RESULT_C), \
840 SR(MPC_CRC_RESULT_AR), \
841 SR(DOMAIN0_PG_CONFIG), \
842 SR(DOMAIN1_PG_CONFIG), \
843 SR(DOMAIN2_PG_CONFIG), \
844 SR(DOMAIN3_PG_CONFIG), \
845 SR(DOMAIN16_PG_CONFIG), \
846 SR(DOMAIN17_PG_CONFIG), \
847 SR(DOMAIN18_PG_CONFIG), \
848 SR(DOMAIN0_PG_STATUS), \
849 SR(DOMAIN1_PG_STATUS), \
850 SR(DOMAIN2_PG_STATUS), \
851 SR(DOMAIN3_PG_STATUS), \
852 SR(DOMAIN16_PG_STATUS), \
853 SR(DOMAIN17_PG_STATUS), \
854 SR(DOMAIN18_PG_STATUS), \
855 SR(D1VGA_CONTROL), \
856 SR(D2VGA_CONTROL), \
857 SR(D3VGA_CONTROL), \
858 SR(D4VGA_CONTROL), \
859 SR(D5VGA_CONTROL), \
860 SR(D6VGA_CONTROL), \
861 SR(DC_IP_REQUEST_CNTL), \
862 SR(AZALIA_AUDIO_DTO), \
863 SR(AZALIA_CONTROLLER_CLOCK_GATING)
864
865static const struct dce_hwseq_registers hwseq_reg = {
866 HWSEQ_DCN31_REG_LIST()
867};
868
869#define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
870 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
871 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
32f1d0cf 872 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
2083640f
NK		 873 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
874 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
875 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
876 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
877 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
878 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
879 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
880 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
881 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
882 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
883 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
884 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
885 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
886 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
887 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
888 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
889 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
890 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
891 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
892 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
893 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
894 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
895 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
896 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
897 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
898 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
899 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
900 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
901
902static const struct dce_hwseq_shift hwseq_shift = {
903 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
904};
905
906static const struct dce_hwseq_mask hwseq_mask = {
907 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
908};
909#define vmid_regs(id)\
910[id] = {\
911 DCN20_VMID_REG_LIST(id)\
912}
913
914static const struct dcn_vmid_registers vmid_regs[] = {
915 vmid_regs(0),
916 vmid_regs(1),
917 vmid_regs(2),
918 vmid_regs(3),
919 vmid_regs(4),
920 vmid_regs(5),
921 vmid_regs(6),
922 vmid_regs(7),
923 vmid_regs(8),
924 vmid_regs(9),
925 vmid_regs(10),
926 vmid_regs(11),
927 vmid_regs(12),
928 vmid_regs(13),
929 vmid_regs(14),
930 vmid_regs(15)
931};
932
933static const struct dcn20_vmid_shift vmid_shifts = {
934 DCN20_VMID_MASK_SH_LIST(__SHIFT)
935};
936
937static const struct dcn20_vmid_mask vmid_masks = {
938 DCN20_VMID_MASK_SH_LIST(_MASK)
939};
940
941static const struct resource_caps res_cap_dcn31 = {
942 .num_timing_generator = 4,
943 .num_opp = 4,
944 .num_video_plane = 4,
945 .num_audio = 5,
946 .num_stream_encoder = 5,
947 .num_dig_link_enc = 5,
83228ebb 948 .num_hpo_dp_stream_encoder = 4,
3bc8d921 949 .num_hpo_dp_link_encoder = 2,
2083640f
NK		 950 .num_pll = 5,
951 .num_dwb = 1,
952 .num_ddc = 5,
953 .num_vmid = 16,
954 .num_mpc_3dlut = 2,
955 .num_dsc = 3,
956};
957
958static const struct dc_plane_cap plane_cap = {
959 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
960 .blends_with_above = true,
961 .blends_with_below = true,
962 .per_pixel_alpha = true,
963
964 .pixel_format_support = {
965 .argb8888 = true,
966 .nv12 = true,
967 .fp16 = true,
968 .p010 = false,
969 .ayuv = false,
970 },
971
972 .max_upscale_factor = {
973 .argb8888 = 16000,
974 .nv12 = 16000,
975 .fp16 = 16000
976 },
977
978 // 6:1 downscaling ratio: 1000/6 = 166.666
979 .max_downscale_factor = {
980 .argb8888 = 167,
981 .nv12 = 167,
982 .fp16 = 167
983 },
984 64,
985 64
986};
987
988static const struct dc_debug_options debug_defaults_drv = {
989 .disable_dmcu = true,
990 .force_abm_enable = false,
991 .timing_trace = false,
992 .clock_trace = true,
993 .disable_pplib_clock_request = false,
994 .pipe_split_policy = MPC_SPLIT_AVOID,
995 .force_single_disp_pipe_split = false,
996 .disable_dcc = DCC_ENABLE,
997 .vsr_support = true,
998 .performance_trace = false,
999 .max_downscale_src_width = 7680,/*upto 8K*/
1000 .disable_pplib_wm_range = false,
1001 .scl_reset_length10 = true,
1002 .sanity_checks = false,
1003 .underflow_assert_delay_us = 0xFFFFFFFF,
1004 .dwb_fi_phase = -1, // -1 = disable,
1005 .dmub_command_table = true,
1006 .pstate_enabled = true,
1007 .use_max_lb = true,
2083640f
NK		 1008 .enable_mem_low_power = {
1009 .bits = {
1010 .vga = false,
1011 .i2c = false,
1012 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
1013 .dscl = false,
1014 .cm = false,
1015 .mpc = false,
1016 .optc = false,
1017 }
1018 },
1019 .optimize_edp_link_rate = true,
1020 .enable_sw_cntl_psr = true,
1021};
1022
1023static const struct dc_debug_options debug_defaults_diags = {
1024 .disable_dmcu = true,
1025 .force_abm_enable = false,
1026 .timing_trace = true,
1027 .clock_trace = true,
1028 .disable_dpp_power_gate = true,
1029 .disable_hubp_power_gate = true,
1030 .disable_clock_gate = true,
1031 .disable_pplib_clock_request = true,
1032 .disable_pplib_wm_range = true,
1033 .disable_stutter = false,
1034 .scl_reset_length10 = true,
1035 .dwb_fi_phase = -1, // -1 = disable
1036 .dmub_command_table = true,
1037 .enable_tri_buf = true,
1038 .use_max_lb = true
1039};
1040
1041static void dcn31_dpp_destroy(struct dpp **dpp)
1042{
1043 kfree(TO_DCN20_DPP(*dpp));
1044 *dpp = NULL;
1045}
1046
1047static struct dpp *dcn31_dpp_create(
1048 struct dc_context *ctx,
1049 uint32_t inst)
1050{
1051 struct dcn3_dpp *dpp =
1052 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
1053
1054 if (!dpp)
1055 return NULL;
1056
1057 if (dpp3_construct(dpp, ctx, inst,
1058 &dpp_regs[inst], &tf_shift, &tf_mask))
1059 return &dpp->base;
1060
1061 BREAK_TO_DEBUGGER();
1062 kfree(dpp);
1063 return NULL;
1064}
1065
1066static struct output_pixel_processor *dcn31_opp_create(
1067 struct dc_context *ctx, uint32_t inst)
1068{
1069 struct dcn20_opp *opp =
1070 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1071
1072 if (!opp) {
1073 BREAK_TO_DEBUGGER();
1074 return NULL;
1075 }
1076
1077 dcn20_opp_construct(opp, ctx, inst,
1078 &opp_regs[inst], &opp_shift, &opp_mask);
1079 return &opp->base;
1080}
1081
1082static struct dce_aux *dcn31_aux_engine_create(
1083 struct dc_context *ctx,
1084 uint32_t inst)
1085{
1086 struct aux_engine_dce110 *aux_engine =
1087 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
1088
1089 if (!aux_engine)
1090 return NULL;
1091
1092 dce110_aux_engine_construct(aux_engine, ctx, inst,
1093 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1094 &aux_engine_regs[inst],
1095 &aux_mask,
1096 &aux_shift,
1097 ctx->dc->caps.extended_aux_timeout_support);
1098
1099 return &aux_engine->base;
1100}
1101#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
1102
1103static const struct dce_i2c_registers i2c_hw_regs[] = {
1104 i2c_inst_regs(1),
1105 i2c_inst_regs(2),
1106 i2c_inst_regs(3),
1107 i2c_inst_regs(4),
1108 i2c_inst_regs(5),
1109};
1110
1111static const struct dce_i2c_shift i2c_shifts = {
1112 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
1113};
1114
1115static const struct dce_i2c_mask i2c_masks = {
1116 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
1117};
1118
1119static struct dce_i2c_hw *dcn31_i2c_hw_create(
1120 struct dc_context *ctx,
1121 uint32_t inst)
1122{
1123 struct dce_i2c_hw *dce_i2c_hw =
1124 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1125
1126 if (!dce_i2c_hw)
1127 return NULL;
1128
1129 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1130 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1131
1132 return dce_i2c_hw;
1133}
1134static struct mpc *dcn31_mpc_create(
1135 struct dc_context *ctx,
1136 int num_mpcc,
1137 int num_rmu)
1138{
1139 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1140 GFP_KERNEL);
1141
1142 if (!mpc30)
1143 return NULL;
1144
1145 dcn30_mpc_construct(mpc30, ctx,
1146 &mpc_regs,
1147 &mpc_shift,
1148 &mpc_mask,
1149 num_mpcc,
1150 num_rmu);
1151
1152 return &mpc30->base;
1153}
1154
1155static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1156{
1157 int i;
1158
1159 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1160 GFP_KERNEL);
1161
1162 if (!hubbub3)
1163 return NULL;
1164
1165 hubbub31_construct(hubbub3, ctx,
1166 &hubbub_reg,
1167 &hubbub_shift,
1168 &hubbub_mask,
1169 dcn3_1_ip.det_buffer_size_kbytes,
1170 dcn3_1_ip.pixel_chunk_size_kbytes,
1171 dcn3_1_ip.config_return_buffer_size_in_kbytes);
1172
1173
1174 for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
1175 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1176
1177 vmid->ctx = ctx;
1178
1179 vmid->regs = &vmid_regs[i];
1180 vmid->shifts = &vmid_shifts;
1181 vmid->masks = &vmid_masks;
1182 }
1183
1184 return &hubbub3->base;
1185}
1186
1187static struct timing_generator *dcn31_timing_generator_create(
1188 struct dc_context *ctx,
1189 uint32_t instance)
1190{
1191 struct optc *tgn10 =
1192 kzalloc(sizeof(struct optc), GFP_KERNEL);
1193
1194 if (!tgn10)
1195 return NULL;
1196
1197 tgn10->base.inst = instance;
1198 tgn10->base.ctx = ctx;
1199
1200 tgn10->tg_regs = &optc_regs[instance];
1201 tgn10->tg_shift = &optc_shift;
1202 tgn10->tg_mask = &optc_mask;
1203
1204 dcn31_timing_generator_init(tgn10);
1205
1206 return &tgn10->base;
1207}
1208
1209static const struct encoder_feature_support link_enc_feature = {
1210 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1211 .max_hdmi_pixel_clock = 600000,
1212 .hdmi_ycbcr420_supported = true,
1213 .dp_ycbcr420_supported = true,
1214 .fec_supported = true,
1215 .flags.bits.IS_HBR2_CAPABLE = true,
1216 .flags.bits.IS_HBR3_CAPABLE = true,
1217 .flags.bits.IS_TPS3_CAPABLE = true,
1218 .flags.bits.IS_TPS4_CAPABLE = true
1219};
1220
1221static struct link_encoder *dcn31_link_encoder_create(
1222 const struct encoder_init_data *enc_init_data)
1223{
1224 struct dcn20_link_encoder *enc20 =
1225 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1226
1227 if (!enc20)
1228 return NULL;
1229
1230 dcn31_link_encoder_construct(enc20,
1231 enc_init_data,
1232 &link_enc_feature,
1233 &link_enc_regs[enc_init_data->transmitter],
1234 &link_enc_aux_regs[enc_init_data->channel - 1],
1235 &link_enc_hpd_regs[enc_init_data->hpd_source],
1236 &le_shift,
1237 &le_mask);
1238
1239 return &enc20->enc10.base;
1240}
1241
1242/* Create a minimal link encoder object not associated with a particular
1243 * physical connector.
1244 * resource_funcs.link_enc_create_minimal
1245 */
1246static struct link_encoder *dcn31_link_enc_create_minimal(
1247 struct dc_context *ctx, enum engine_id eng_id)
1248{
1249 struct dcn20_link_encoder *enc20;
1250
1251 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1252 return NULL;
1253
1254 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1255 if (!enc20)
1256 return NULL;
1257
1258 dcn31_link_encoder_construct_minimal(
1259 enc20,
1260 ctx,
1261 &link_enc_feature,
1262 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1263 eng_id);
1264
1265 return &enc20->enc10.base;
1266}
1267
1268struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1269{
1270 struct dcn31_panel_cntl *panel_cntl =
1271 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1272
1273 if (!panel_cntl)
1274 return NULL;
1275
1276 dcn31_panel_cntl_construct(panel_cntl, init_data);
1277
1278 return &panel_cntl->base;
1279}
1280
1281static void read_dce_straps(
1282 struct dc_context *ctx,
1283 struct resource_straps *straps)
1284{
1285 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1286 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1287
1288}
1289
1290static struct audio *dcn31_create_audio(
1291 struct dc_context *ctx, unsigned int inst)
1292{
1293 return dce_audio_create(ctx, inst,
1294 &audio_regs[inst], &audio_shift, &audio_mask);
1295}
1296
1297static struct vpg *dcn31_vpg_create(
1298 struct dc_context *ctx,
1299 uint32_t inst)
1300{
1301 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
1302
1303 if (!vpg3)
1304 return NULL;
1305
1306 vpg3_construct(vpg3, ctx, inst,
1307 &vpg_regs[inst],
1308 &vpg_shift,
1309 &vpg_mask);
1310
1311 return &vpg3->base;
1312}
1313
1314static struct afmt *dcn31_afmt_create(
1315 struct dc_context *ctx,
1316 uint32_t inst)
1317{
1318 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1319
1320 if (!afmt3)
1321 return NULL;
1322
1323 afmt3_construct(afmt3, ctx, inst,
1324 &afmt_regs[inst],
1325 &afmt_shift,
1326 &afmt_mask);
1327
1328 return &afmt3->base;
1329}
1330
61452908
FZ		 1331static struct apg *dcn31_apg_create(
1332 struct dc_context *ctx,
1333 uint32_t inst)
1334{
1335 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1336
1337 if (!apg31)
1338 return NULL;
1339
1340 apg31_construct(apg31, ctx, inst,
1341 &apg_regs[inst],
1342 &apg_shift,
1343 &apg_mask);
1344
1345 return &apg31->base;
1346}
1347
2083640f
NK		 1348static struct stream_encoder *dcn31_stream_encoder_create(
1349 enum engine_id eng_id,
1350 struct dc_context *ctx)
1351{
1352 struct dcn10_stream_encoder *enc1;
1353 struct vpg *vpg;
1354 struct afmt *afmt;
1355 int vpg_inst;
1356 int afmt_inst;
1357
1358 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1359 if (eng_id <= ENGINE_ID_DIGF) {
1360 vpg_inst = eng_id;
1361 afmt_inst = eng_id;
1362 } else
1363 return NULL;
1364
1365 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1366 vpg = dcn31_vpg_create(ctx, vpg_inst);
1367 afmt = dcn31_afmt_create(ctx, afmt_inst);
1368
7b89bf83
AJ		 1369 if (!enc1 || !vpg || !afmt) {
1370 kfree(enc1);
1371 kfree(vpg);
1372 kfree(afmt);
2083640f 1373 return NULL;
7b89bf83 1374 }
2083640f
NK		 1375
1376 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1377 eng_id, vpg, afmt,
1378 &stream_enc_regs[eng_id],
1379 &se_shift, &se_mask);
1380
1381 return &enc1->base;
1382}
1383
83228ebb
FZ		 1384static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1385 enum engine_id eng_id,
1386 struct dc_context *ctx)
1387{
1388 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1389 struct vpg *vpg;
1390 struct apg *apg;
1391 uint32_t hpo_dp_inst;
1392 uint32_t vpg_inst;
1393 uint32_t apg_inst;
1394
1395 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1396 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1397
1398 /* Mapping of VPG register blocks to HPO DP block instance:
1399 * VPG[6] -> HPO_DP[0]
1400 * VPG[7] -> HPO_DP[1]
1401 * VPG[8] -> HPO_DP[2]
1402 * VPG[9] -> HPO_DP[3]
1403 */
1404 vpg_inst = hpo_dp_inst + 6;
1405
1406 /* Mapping of APG register blocks to HPO DP block instance:
1407 * APG[0] -> HPO_DP[0]
1408 * APG[1] -> HPO_DP[1]
1409 * APG[2] -> HPO_DP[2]
1410 * APG[3] -> HPO_DP[3]
1411 */
1412 apg_inst = hpo_dp_inst;
1413
1414 /* allocate HPO stream encoder and create VPG sub-block */
1415 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1416 vpg = dcn31_vpg_create(ctx, vpg_inst);
1417 apg = dcn31_apg_create(ctx, apg_inst);
1418
7b89bf83
AJ		 1419 if (!hpo_dp_enc31 || !vpg || !apg) {
1420 kfree(hpo_dp_enc31);
1421 kfree(vpg);
1422 kfree(apg);
83228ebb 1423 return NULL;
7b89bf83 1424 }
83228ebb
FZ		 1425
1426 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1427 hpo_dp_inst, eng_id, vpg, apg,
1428 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1429 &hpo_dp_se_shift, &hpo_dp_se_mask);
1430
1431 return &hpo_dp_enc31->base;
1432}
1433
3bc8d921
FZ		 1434static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1435 uint8_t inst,
1436 struct dc_context *ctx)
1437{
1438 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1439
1440 /* allocate HPO link encoder */
1441 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1442
1443 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1444 &hpo_dp_link_enc_regs[inst],
1445 &hpo_dp_le_shift, &hpo_dp_le_mask);
1446
1447 return &hpo_dp_enc31->base;
1448}
1449
2083640f
NK		 1450static struct dce_hwseq *dcn31_hwseq_create(
1451 struct dc_context *ctx)
1452{
1453 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1454
1455 if (hws) {
1456 hws->ctx = ctx;
1457 hws->regs = &hwseq_reg;
1458 hws->shifts = &hwseq_shift;
1459 hws->masks = &hwseq_mask;
f01ee019
FZ		 1460 /* DCN3.1 FPGA Workaround
1461 * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1462 * To do so, move calling function enable_stream_timing to only be done AFTER calling
1463 * function core_link_enable_stream
1464 */
1465 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
1466 hws->wa.dp_hpo_and_otg_sequence = true;
2083640f
NK		 1467 }
1468 return hws;
1469}
1470static const struct resource_create_funcs res_create_funcs = {
1471 .read_dce_straps = read_dce_straps,
1472 .create_audio = dcn31_create_audio,
1473 .create_stream_encoder = dcn31_stream_encoder_create,
83228ebb 1474 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
3bc8d921 1475 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
2083640f
NK		 1476 .create_hwseq = dcn31_hwseq_create,
1477};
1478
1479static const struct resource_create_funcs res_create_maximus_funcs = {
1480 .read_dce_straps = NULL,
1481 .create_audio = NULL,
1482 .create_stream_encoder = NULL,
83228ebb 1483 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
3bc8d921 1484 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
2083640f
NK		 1485 .create_hwseq = dcn31_hwseq_create,
1486};
1487
1488static void dcn31_resource_destruct(struct dcn31_resource_pool *pool)
1489{
1490 unsigned int i;
1491
1492 for (i = 0; i < pool->base.stream_enc_count; i++) {
1493 if (pool->base.stream_enc[i] != NULL) {
1494 if (pool->base.stream_enc[i]->vpg != NULL) {
1495 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1496 pool->base.stream_enc[i]->vpg = NULL;
1497 }
1498 if (pool->base.stream_enc[i]->afmt != NULL) {
1499 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1500 pool->base.stream_enc[i]->afmt = NULL;
1501 }
1502 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1503 pool->base.stream_enc[i] = NULL;
1504 }
1505 }
1506
83228ebb
FZ		 1507 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1508 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1509 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1510 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1511 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1512 }
1513 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1514 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1515 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1516 }
1517 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1518 pool->base.hpo_dp_stream_enc[i] = NULL;
1519 }
1520 }
1521
3bc8d921
FZ		 1522 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1523 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1524 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1525 pool->base.hpo_dp_link_enc[i] = NULL;
1526 }
1527 }
1528
2083640f
NK		 1529 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1530 if (pool->base.dscs[i] != NULL)
1531 dcn20_dsc_destroy(&pool->base.dscs[i]);
1532 }
1533
1534 if (pool->base.mpc != NULL) {
1535 kfree(TO_DCN20_MPC(pool->base.mpc));
1536 pool->base.mpc = NULL;
1537 }
1538 if (pool->base.hubbub != NULL) {
1539 kfree(pool->base.hubbub);
1540 pool->base.hubbub = NULL;
1541 }
1542 for (i = 0; i < pool->base.pipe_count; i++) {
1543 if (pool->base.dpps[i] != NULL)
1544 dcn31_dpp_destroy(&pool->base.dpps[i]);
1545
1546 if (pool->base.ipps[i] != NULL)
1547 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1548
1549 if (pool->base.hubps[i] != NULL) {
1550 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1551 pool->base.hubps[i] = NULL;
1552 }
1553
1554 if (pool->base.irqs != NULL) {
1555 dal_irq_service_destroy(&pool->base.irqs);
1556 }
1557 }
1558
1559 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1560 if (pool->base.engines[i] != NULL)
1561 dce110_engine_destroy(&pool->base.engines[i]);
1562 if (pool->base.hw_i2cs[i] != NULL) {
1563 kfree(pool->base.hw_i2cs[i]);
1564 pool->base.hw_i2cs[i] = NULL;
1565 }
1566 if (pool->base.sw_i2cs[i] != NULL) {
1567 kfree(pool->base.sw_i2cs[i]);
1568 pool->base.sw_i2cs[i] = NULL;
1569 }
1570 }
1571
1572 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1573 if (pool->base.opps[i] != NULL)
1574 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1575 }
1576
1577 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1578 if (pool->base.timing_generators[i] != NULL) {
1579 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1580 pool->base.timing_generators[i] = NULL;
1581 }
1582 }
1583
1584 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1585 if (pool->base.dwbc[i] != NULL) {
1586 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1587 pool->base.dwbc[i] = NULL;
1588 }
1589 if (pool->base.mcif_wb[i] != NULL) {
1590 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1591 pool->base.mcif_wb[i] = NULL;
1592 }
1593 }
1594
1595 for (i = 0; i < pool->base.audio_count; i++) {
1596 if (pool->base.audios[i])
1597 dce_aud_destroy(&pool->base.audios[i]);
1598 }
1599
1600 for (i = 0; i < pool->base.clk_src_count; i++) {
1601 if (pool->base.clock_sources[i] != NULL) {
1602 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1603 pool->base.clock_sources[i] = NULL;
1604 }
1605 }
1606
1607 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1608 if (pool->base.mpc_lut[i] != NULL) {
1609 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1610 pool->base.mpc_lut[i] = NULL;
1611 }
1612 if (pool->base.mpc_shaper[i] != NULL) {
1613 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1614 pool->base.mpc_shaper[i] = NULL;
1615 }
1616 }
1617
1618 if (pool->base.dp_clock_source != NULL) {
1619 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1620 pool->base.dp_clock_source = NULL;
1621 }
1622
1623 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1624 if (pool->base.multiple_abms[i] != NULL)
1625 dce_abm_destroy(&pool->base.multiple_abms[i]);
1626 }
1627
1628 if (pool->base.psr != NULL)
1629 dmub_psr_destroy(&pool->base.psr);
1630
1631 if (pool->base.dccg != NULL)
1632 dcn_dccg_destroy(&pool->base.dccg);
1633}
1634
1635static struct hubp *dcn31_hubp_create(
1636 struct dc_context *ctx,
1637 uint32_t inst)
1638{
1639 struct dcn20_hubp *hubp2 =
1640 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1641
1642 if (!hubp2)
1643 return NULL;
1644
1645 if (hubp31_construct(hubp2, ctx, inst,
1646 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1647 return &hubp2->base;
1648
1649 BREAK_TO_DEBUGGER();
1650 kfree(hubp2);
1651 return NULL;
1652}
1653
1654static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1655{
1656 int i;
1657 uint32_t pipe_count = pool->res_cap->num_dwb;
1658
1659 for (i = 0; i < pipe_count; i++) {
1660 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1661 GFP_KERNEL);
1662
1663 if (!dwbc30) {
1664 dm_error("DC: failed to create dwbc30!\n");
1665 return false;
1666 }
1667
1668 dcn30_dwbc_construct(dwbc30, ctx,
1669 &dwbc30_regs[i],
1670 &dwbc30_shift,
1671 &dwbc30_mask,
1672 i);
1673
1674 pool->dwbc[i] = &dwbc30->base;
1675 }
1676 return true;
1677}
1678
1679static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1680{
1681 int i;
1682 uint32_t pipe_count = pool->res_cap->num_dwb;
1683
1684 for (i = 0; i < pipe_count; i++) {
1685 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1686 GFP_KERNEL);
1687
1688 if (!mcif_wb30) {
1689 dm_error("DC: failed to create mcif_wb30!\n");
1690 return false;
1691 }
1692
1693 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1694 &mcif_wb30_regs[i],
1695 &mcif_wb30_shift,
1696 &mcif_wb30_mask,
1697 i);
1698
1699 pool->mcif_wb[i] = &mcif_wb30->base;
1700 }
1701 return true;
1702}
1703
1704static struct display_stream_compressor *dcn31_dsc_create(
1705 struct dc_context *ctx, uint32_t inst)
1706{
1707 struct dcn20_dsc *dsc =
1708 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1709
1710 if (!dsc) {
1711 BREAK_TO_DEBUGGER();
1712 return NULL;
1713 }
1714
1715 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1716 return &dsc->base;
1717}
1718
1719static void dcn31_destroy_resource_pool(struct resource_pool **pool)
1720{
1721 struct dcn31_resource_pool *dcn31_pool = TO_DCN31_RES_POOL(*pool);
1722
1723 dcn31_resource_destruct(dcn31_pool);
1724 kfree(dcn31_pool);
1725 *pool = NULL;
1726}
1727
1728static struct clock_source *dcn31_clock_source_create(
1729 struct dc_context *ctx,
1730 struct dc_bios *bios,
1731 enum clock_source_id id,
1732 const struct dce110_clk_src_regs *regs,
1733 bool dp_clk_src)
1734{
1735 struct dce110_clk_src *clk_src =
1736 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1737
1738 if (!clk_src)
1739 return NULL;
1740
1741 if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1742 regs, &cs_shift, &cs_mask)) {
1743 clk_src->base.dp_clk_src = dp_clk_src;
1744 return &clk_src->base;
1745 }
1746
1747 BREAK_TO_DEBUGGER();
1748 return NULL;
1749}
1750
1751static bool is_dual_plane(enum surface_pixel_format format)
1752{
1753 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1754}
1755
1756static int dcn31_populate_dml_pipes_from_context(
1757 struct dc *dc, struct dc_state *context,
1758 display_e2e_pipe_params_st *pipes,
1759 bool fast_validate)
1760{
1761 int i, pipe_cnt;
1762 struct resource_context *res_ctx = &context->res_ctx;
1763 struct pipe_ctx *pipe;
1764
1765 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1766
1767 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1768 struct dc_crtc_timing *timing;
1769
1770 if (!res_ctx->pipe_ctx[i].stream)
1771 continue;
1772 pipe = &res_ctx->pipe_ctx[i];
1773 timing = &pipe->stream->timing;
1774
1775 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1776 pipes[pipe_cnt].pipe.src.gpuvm = true;
1777 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
1778 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
1779 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1780 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1781 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1782
1783 if (pipes[pipe_cnt].dout.dsc_enable) {
1784 switch (timing->display_color_depth) {
1785 case COLOR_DEPTH_888:
1786 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1787 break;
1788 case COLOR_DEPTH_101010:
1789 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1790 break;
1791 case COLOR_DEPTH_121212:
1792 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1793 break;
1794 default:
1795 ASSERT(0);
1796 break;
1797 }
1798 }
1799
1800 pipe_cnt++;
1801 }
1802 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE;
1803 dc->config.enable_4to1MPC = false;
1804 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1805 if (is_dual_plane(pipe->plane_state->format)
1806 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
1807 dc->config.enable_4to1MPC = true;
1808 } else if (!is_dual_plane(pipe->plane_state->format)) {
1809 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1810 pipes[0].pipe.src.unbounded_req_mode = true;
1811 }
1812 }
1813
1814 return pipe_cnt;
1815}
1816
1817static void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
1818{
1819 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
1820 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
1821 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
1822 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
1823 }
1824}
1825
3e88cbb0 1826static void dcn31_calculate_wm_and_dlg_fp(
2083640f
NK		 1827 struct dc *dc, struct dc_state *context,
1828 display_e2e_pipe_params_st *pipes,
1829 int pipe_cnt,
1830 int vlevel)
1831{
1832 int i, pipe_idx;
1833 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1834
1835 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
1836 dcfclk = context->bw_ctx.dml.soc.min_dcfclk;
1837
bc204778
MS		 1838 /* We don't recalculate clocks for 0 pipe configs, which can block
1839 * S0i3 as high clocks will block low power states
1840 * Override any clocks that can block S0i3 to min here
1841 */
1842 if (pipe_cnt == 0) {
1843 context->bw_ctx.bw.dcn.clk.dcfclk_khz = dcfclk; // always should be vlevel 0
1844 return;
1845 }
1846
2083640f
NK		 1847 pipes[0].clks_cfg.voltage = vlevel;
1848 pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
1849 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
1850
1851#if 0 // TODO
1852 /* Set B:
1853 * TODO
1854 */
1855 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
1856 if (vlevel == 0) {
1857 pipes[0].clks_cfg.voltage = 1;
1858 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz;
1859 }
1860 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
1861 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
1862 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
1863 }
1864 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1865 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1866 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1867 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1868 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1869 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1870 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1871 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1872 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1873 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1874
1875 pipes[0].clks_cfg.voltage = vlevel;
1876 pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
1877
1878 /* Set C:
1879 * TODO
1880 */
1881 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
1882 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us;
1883 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
1884 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
1885 }
1886 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1887 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1888 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1889 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1890 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1891 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1892 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1893 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1894 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1895 context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1896
1897 /* Set D:
1898 * TODO
1899 */
1900 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
1901 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
1902 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
1903 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
1904 }
1905 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1906 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1907 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1908 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1909 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1910 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1911 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1912 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1913 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1914 context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1915#endif
1916
1917 /* Set A:
1918 * All clocks min required
1919 *
1920 * Set A calculated last so that following calculations are based on Set A
1921 */
1922 dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1923 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1924 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1925 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1926 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1927 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1928 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1929 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1930 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1931 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1932 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1933 /* TODO: remove: */
1934 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
1935 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
1936 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
1937 /* end remove*/
1938
1939 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1940 if (!context->res_ctx.pipe_ctx[i].stream)
1941 continue;
1942
1943 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
1944 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1945
1946 if (dc->config.forced_clocks) {
1947 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
1948 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
1949 }
1950 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
1951 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
1952 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1953 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
1954
1955 pipe_idx++;
1956 }
1957
1958 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1959}
1960
3e88cbb0
AD		 1961static void dcn31_calculate_wm_and_dlg(
1962 struct dc *dc, struct dc_state *context,
1963 display_e2e_pipe_params_st *pipes,
1964 int pipe_cnt,
1965 int vlevel)
1966{
1967 DC_FP_START();
1968 dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
1969 DC_FP_END();
1970}
1971
bc204778
MS		 1972bool dcn31_validate_bandwidth(struct dc *dc,
1973 struct dc_state *context,
1974 bool fast_validate)
1975{
1976 bool out = false;
1977
1978 BW_VAL_TRACE_SETUP();
1979
1980 int vlevel = 0;
1981 int pipe_cnt = 0;
1982 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1983 DC_LOGGER_INIT(dc->ctx->logger);
1984
1985 BW_VAL_TRACE_COUNT();
1986
1987 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
1988
1989 // Disable fast_validate to set min dcfclk in alculate_wm_and_dlg
1990 if (pipe_cnt == 0)
1991 fast_validate = false;
1992
1993 if (!out)
1994 goto validate_fail;
1995
1996 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1997
1998 if (fast_validate) {
1999 BW_VAL_TRACE_SKIP(fast);
2000 goto validate_out;
2001 }
2002
2003 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2004
2005 BW_VAL_TRACE_END_WATERMARKS();
2006
2007 goto validate_out;
2008
2009validate_fail:
f9e476c5 2010 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
bc204778
MS		 2011 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2012
2013 BW_VAL_TRACE_SKIP(fail);
2014 out = false;
2015
2016validate_out:
2017 kfree(pipes);
2018
2019 BW_VAL_TRACE_FINISH();
2020
2021 return out;
2022}
2023
2083640f
NK		 2024static struct dc_cap_funcs cap_funcs = {
2025 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
2026};
2027
2028static void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2029{
2030 struct clk_limit_table *clk_table = &bw_params->clk_table;
2031 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
2032 unsigned int i, closest_clk_lvl;
2033 int j;
2034
2035 // Default clock levels are used for diags, which may lead to overclocking.
2036 if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
2037 int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
2038
2039 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
2040 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count;
2041 dcn3_1_soc.num_chans = bw_params->num_channels;
2042
2043 ASSERT(clk_table->num_entries);
2044
2045 /* Prepass to find max clocks independent of voltage level. */
2046 for (i = 0; i < clk_table->num_entries; ++i) {
2047 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
2048 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
2049 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
2050 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
2051 }
2052
2053 for (i = 0; i < clk_table->num_entries; i++) {
2054 /* loop backwards*/
2055 for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) {
2056 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
2057 closest_clk_lvl = j;
2058 break;
2059 }
2060 }
2061
2062 clock_limits[i].state = i;
2063
2064 /* Clocks dependent on voltage level. */
2065 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
2066 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
2067 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
2068 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
2069
2070 /* Clocks independent of voltage level. */
2071 clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
2072 dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
2073
2074 clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
2075 dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
2076
2077 clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
2078 clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
2079 clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
2080 clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
2081 clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
2082 }
2083 for (i = 0; i < clk_table->num_entries; i++)
2084 dcn3_1_soc.clock_limits[i] = clock_limits[i];
2085 if (clk_table->num_entries) {
2086 dcn3_1_soc.num_states = clk_table->num_entries;
2087 }
2088 }
2089
2090 dcn3_1_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2091 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2092
2093 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
2094 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31);
2095 else
2096 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31_FPGA);
2097}
2098
2099static struct resource_funcs dcn31_res_pool_funcs = {
2100 .destroy = dcn31_destroy_resource_pool,
2101 .link_enc_create = dcn31_link_encoder_create,
2102 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
2103 .link_encs_assign = link_enc_cfg_link_encs_assign,
2104 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
2105 .panel_cntl_create = dcn31_panel_cntl_create,
bc204778 2106 .validate_bandwidth = dcn31_validate_bandwidth,
2083640f
NK		 2107 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
2108 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
2109 .populate_dml_pipes = dcn31_populate_dml_pipes_from_context,
2110 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
2111 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
2112 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2113 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2114 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
2115 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
2116 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2117 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
2118 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
2119 .update_bw_bounding_box = dcn31_update_bw_bounding_box,
2120 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2121};
2122
2123static struct clock_source *dcn30_clock_source_create(
2124 struct dc_context *ctx,
2125 struct dc_bios *bios,
2126 enum clock_source_id id,
2127 const struct dce110_clk_src_regs *regs,
2128 bool dp_clk_src)
2129{
2130 struct dce110_clk_src *clk_src =
2131 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
2132
2133 if (!clk_src)
2134 return NULL;
2135
2136 if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
2137 regs, &cs_shift, &cs_mask)) {
2138 clk_src->base.dp_clk_src = dp_clk_src;
2139 return &clk_src->base;
2140 }
2141
2142 BREAK_TO_DEBUGGER();
2143 return NULL;
2144}
2145
2146static bool dcn31_resource_construct(
2147 uint8_t num_virtual_links,
2148 struct dc *dc,
2149 struct dcn31_resource_pool *pool)
2150{
2151 int i;
2152 struct dc_context *ctx = dc->ctx;
2153 struct irq_service_init_data init_data;
2154
3e88cbb0
AD		 2155 DC_FP_START();
2156
2083640f
NK		 2157 ctx->dc_bios->regs = &bios_regs;
2158
2159 pool->base.res_cap = &res_cap_dcn31;
2160
2161 pool->base.funcs = &dcn31_res_pool_funcs;
2162
2163 /*************************************************
2164 * Resource + asic cap harcoding *
2165 *************************************************/
2166 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2167 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2168 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
2169 dc->caps.max_downscale_ratio = 600;
2170 dc->caps.i2c_speed_in_khz = 100;
2171 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
2172 dc->caps.max_cursor_size = 256;
2173 dc->caps.min_horizontal_blanking_period = 80;
2174 dc->caps.dmdata_alloc_size = 2048;
2175
2176 dc->caps.max_slave_planes = 1;
2177 dc->caps.max_slave_yuv_planes = 1;
2178 dc->caps.max_slave_rgb_planes = 1;
2179 dc->caps.post_blend_color_processing = true;
2180 dc->caps.force_dp_tps4_for_cp2520 = true;
f01ee019 2181 dc->caps.dp_hpo = true;
2083640f
NK		 2182 dc->caps.extended_aux_timeout_support = true;
2183 dc->caps.dmcub_support = true;
2184 dc->caps.is_apu = true;
2185
2186 /* Color pipeline capabilities */
2187 dc->caps.color.dpp.dcn_arch = 1;
2188 dc->caps.color.dpp.input_lut_shared = 0;
2189 dc->caps.color.dpp.icsc = 1;
2190 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2191 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2192 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2193 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2194 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2195 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2196 dc->caps.color.dpp.post_csc = 1;
2197 dc->caps.color.dpp.gamma_corr = 1;
2198 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2199
2200 dc->caps.color.dpp.hw_3d_lut = 1;
2201 dc->caps.color.dpp.ogam_ram = 1;
2202 // no OGAM ROM on DCN301
2203 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2204 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2205 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2206 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2207 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2208 dc->caps.color.dpp.ocsc = 0;
2209
2210 dc->caps.color.mpc.gamut_remap = 1;
2211 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
2212 dc->caps.color.mpc.ogam_ram = 1;
2213 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2214 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2215 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2216 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2217 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2218 dc->caps.color.mpc.ocsc = 1;
2219
ba18f235
WC		 2220 /* read VBIOS LTTPR caps */
2221 {
2222 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2223 enum bp_result bp_query_result;
2224 uint8_t is_vbios_lttpr_enable = 0;
2225
2226 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2227 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2228 }
2229
2230 /* interop bit is implicit */
2231 {
2232 dc->caps.vbios_lttpr_aware = true;
2233 }
2234 }
2235
2083640f
NK		 2236 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2237 dc->debug = debug_defaults_drv;
2238 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2239 dc->debug = debug_defaults_diags;
2240 } else
2241 dc->debug = debug_defaults_diags;
2242 // Init the vm_helper
2243 if (dc->vm_helper)
2244 vm_helper_init(dc->vm_helper, 16);
2245
2246 /*************************************************
2247 * Create resources *
2248 *************************************************/
2249
2250 /* Clock Sources for Pixel Clock*/
2251 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
2252 dcn30_clock_source_create(ctx, ctx->dc_bios,
2253 CLOCK_SOURCE_COMBO_PHY_PLL0,
2254 &clk_src_regs[0], false);
2255 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
2256 dcn30_clock_source_create(ctx, ctx->dc_bios,
2257 CLOCK_SOURCE_COMBO_PHY_PLL1,
2258 &clk_src_regs[1], false);
2259 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
2260 dcn30_clock_source_create(ctx, ctx->dc_bios,
2261 CLOCK_SOURCE_COMBO_PHY_PLL2,
2262 &clk_src_regs[2], false);
2263 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
2264 dcn30_clock_source_create(ctx, ctx->dc_bios,
2265 CLOCK_SOURCE_COMBO_PHY_PLL3,
2266 &clk_src_regs[3], false);
2267 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
2268 dcn30_clock_source_create(ctx, ctx->dc_bios,
2269 CLOCK_SOURCE_COMBO_PHY_PLL4,
2270 &clk_src_regs[4], false);
2271
2272 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2273
2274 /* todo: not reuse phy_pll registers */
2275 pool->base.dp_clock_source =
2276 dcn31_clock_source_create(ctx, ctx->dc_bios,
2277 CLOCK_SOURCE_ID_DP_DTO,
2278 &clk_src_regs[0], true);
2279
2280 for (i = 0; i < pool->base.clk_src_count; i++) {
2281 if (pool->base.clock_sources[i] == NULL) {
2282 dm_error("DC: failed to create clock sources!\n");
2283 BREAK_TO_DEBUGGER();
2284 goto create_fail;
2285 }
2286 }
2287
2288 /* TODO: DCCG */
2289 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2290 if (pool->base.dccg == NULL) {
2291 dm_error("DC: failed to create dccg!\n");
2292 BREAK_TO_DEBUGGER();
2293 goto create_fail;
2294 }
2295
2296 /* TODO: IRQ */
2297 init_data.ctx = dc->ctx;
2298 pool->base.irqs = dal_irq_service_dcn31_create(&init_data);
2299 if (!pool->base.irqs)
2300 goto create_fail;
2301
2302 /* HUBBUB */
2303 pool->base.hubbub = dcn31_hubbub_create(ctx);
2304 if (pool->base.hubbub == NULL) {
2305 BREAK_TO_DEBUGGER();
2306 dm_error("DC: failed to create hubbub!\n");
2307 goto create_fail;
2308 }
2309
2310 /* HUBPs, DPPs, OPPs and TGs */
2311 for (i = 0; i < pool->base.pipe_count; i++) {
2312 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
2313 if (pool->base.hubps[i] == NULL) {
2314 BREAK_TO_DEBUGGER();
2315 dm_error(
2316 "DC: failed to create hubps!\n");
2317 goto create_fail;
2318 }
2319
2320 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
2321 if (pool->base.dpps[i] == NULL) {
2322 BREAK_TO_DEBUGGER();
2323 dm_error(
2324 "DC: failed to create dpps!\n");
2325 goto create_fail;
2326 }
2327 }
2328
2329 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2330 pool->base.opps[i] = dcn31_opp_create(ctx, i);
2331 if (pool->base.opps[i] == NULL) {
2332 BREAK_TO_DEBUGGER();
2333 dm_error(
2334 "DC: failed to create output pixel processor!\n");
2335 goto create_fail;
2336 }
2337 }
2338
2339 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2340 pool->base.timing_generators[i] = dcn31_timing_generator_create(
2341 ctx, i);
2342 if (pool->base.timing_generators[i] == NULL) {
2343 BREAK_TO_DEBUGGER();
2344 dm_error("DC: failed to create tg!\n");
2345 goto create_fail;
2346 }
2347 }
2348 pool->base.timing_generator_count = i;
2349
2350 /* PSR */
2351 pool->base.psr = dmub_psr_create(ctx);
2352 if (pool->base.psr == NULL) {
2353 dm_error("DC: failed to create psr obj!\n");
2354 BREAK_TO_DEBUGGER();
2355 goto create_fail;
2356 }
2357
2358 /* ABM */
2359 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2360 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2361 &abm_regs[i],
2362 &abm_shift,
2363 &abm_mask);
2364 if (pool->base.multiple_abms[i] == NULL) {
2365 dm_error("DC: failed to create abm for pipe %d!\n", i);
2366 BREAK_TO_DEBUGGER();
2367 goto create_fail;
2368 }
2369 }
2370
2371 /* MPC and DSC */
2372 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2373 if (pool->base.mpc == NULL) {
2374 BREAK_TO_DEBUGGER();
2375 dm_error("DC: failed to create mpc!\n");
2376 goto create_fail;
2377 }
2378
2379 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2380 pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
2381 if (pool->base.dscs[i] == NULL) {
2382 BREAK_TO_DEBUGGER();
2383 dm_error("DC: failed to create display stream compressor %d!\n", i);
2384 goto create_fail;
2385 }
2386 }
2387
2388 /* DWB and MMHUBBUB */
2389 if (!dcn31_dwbc_create(ctx, &pool->base)) {
2390 BREAK_TO_DEBUGGER();
2391 dm_error("DC: failed to create dwbc!\n");
2392 goto create_fail;
2393 }
2394
2395 if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2396 BREAK_TO_DEBUGGER();
2397 dm_error("DC: failed to create mcif_wb!\n");
2398 goto create_fail;
2399 }
2400
2401 /* AUX and I2C */
2402 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2403 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2404 if (pool->base.engines[i] == NULL) {
2405 BREAK_TO_DEBUGGER();
2406 dm_error(
2407 "DC:failed to create aux engine!!\n");
2408 goto create_fail;
2409 }
2410 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2411 if (pool->base.hw_i2cs[i] == NULL) {
2412 BREAK_TO_DEBUGGER();
2413 dm_error(
2414 "DC:failed to create hw i2c!!\n");
2415 goto create_fail;
2416 }
2417 pool->base.sw_i2cs[i] = NULL;
2418 }
2419
2420 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2421 if (!resource_construct(num_virtual_links, dc, &pool->base,
2422 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2423 &res_create_funcs : &res_create_maximus_funcs)))
2424 goto create_fail;
2425
2426 /* HW Sequencer and Plane caps */
2427 dcn31_hw_sequencer_construct(dc);
2428
2429 dc->caps.max_planes = pool->base.pipe_count;
2430
2431 for (i = 0; i < dc->caps.max_planes; ++i)
2432 dc->caps.planes[i] = plane_cap;
2433
2434 dc->cap_funcs = cap_funcs;
2435
3e88cbb0
AD		 2436 DC_FP_END();
2437
2083640f
NK		 2438 return true;
2439
2440create_fail:
2441
3e88cbb0 2442 DC_FP_END();
2083640f
NK		 2443 dcn31_resource_destruct(pool);
2444
2445 return false;
2446}
2447
2448struct resource_pool *dcn31_create_resource_pool(
2449 const struct dc_init_data *init_data,
2450 struct dc *dc)
2451{
2452 struct dcn31_resource_pool *pool =
2453 kzalloc(sizeof(struct dcn31_resource_pool), GFP_KERNEL);
2454
2455 if (!pool)
2456 return NULL;
2457
2458 if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool))
2459 return &pool->base;
2460
2461 BREAK_TO_DEBUGGER();
2462 kfree(pool);
2463 return NULL;
2464}
Linux 6.x block layer and io_uring tree(s)