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3a83e4e6 RL |
1 | /* |
2 | * Copyright 2020 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | ||
26 | ||
27 | #include "dm_services.h" | |
28 | #include "dc.h" | |
29 | ||
30 | #include "dcn301_init.h" | |
31 | ||
32 | #include "resource.h" | |
33 | #include "include/irq_service_interface.h" | |
34 | #include "dcn30/dcn30_resource.h" | |
35 | #include "dcn301_resource.h" | |
36 | ||
37 | #include "dcn20/dcn20_resource.h" | |
38 | ||
39 | #include "dcn10/dcn10_ipp.h" | |
40 | #include "dcn301/dcn301_hubbub.h" | |
41 | #include "dcn30/dcn30_mpc.h" | |
42 | #include "dcn30/dcn30_hubp.h" | |
43 | #include "irq/dcn30/irq_service_dcn30.h" | |
44 | #include "dcn30/dcn30_dpp.h" | |
45 | #include "dcn30/dcn30_optc.h" | |
46 | #include "dcn20/dcn20_hwseq.h" | |
47 | #include "dcn30/dcn30_hwseq.h" | |
48 | #include "dce110/dce110_hw_sequencer.h" | |
49 | #include "dcn30/dcn30_opp.h" | |
50 | #include "dcn20/dcn20_dsc.h" | |
51 | #include "dcn30/dcn30_vpg.h" | |
52 | #include "dcn30/dcn30_afmt.h" | |
53 | #include "dce/dce_clock_source.h" | |
54 | #include "dce/dce_audio.h" | |
55 | #include "dce/dce_hwseq.h" | |
56 | #include "clk_mgr.h" | |
57 | #include "virtual/virtual_stream_encoder.h" | |
58 | #include "dce110/dce110_resource.h" | |
59 | #include "dml/display_mode_vba.h" | |
60 | #include "dcn301/dcn301_dccg.h" | |
61 | #include "dcn10/dcn10_resource.h" | |
62 | #include "dcn30/dcn30_dio_stream_encoder.h" | |
63 | #include "dcn301/dcn301_dio_link_encoder.h" | |
64 | #include "dcn301_panel_cntl.h" | |
65 | ||
66 | #include "vangogh_ip_offset.h" | |
67 | ||
68 | #include "dcn30/dcn30_dwb.h" | |
69 | #include "dcn30/dcn30_mmhubbub.h" | |
70 | ||
71 | #include "dcn/dcn_3_0_1_offset.h" | |
72 | #include "dcn/dcn_3_0_1_sh_mask.h" | |
73 | ||
74 | #include "nbio/nbio_7_2_0_offset.h" | |
75 | ||
f5041bc1 ZL |
76 | #include "dcn/dpcs_3_0_0_offset.h" |
77 | #include "dcn/dpcs_3_0_0_sh_mask.h" | |
78 | ||
3a83e4e6 RL |
79 | #include "reg_helper.h" |
80 | #include "dce/dmub_abm.h" | |
81 | #include "dce/dce_aux.h" | |
82 | #include "dce/dce_i2c.h" | |
83 | ||
84 | #include "dml/dcn30/display_mode_vba_30.h" | |
85 | #include "vm_helper.h" | |
86 | #include "dcn20/dcn20_vmid.h" | |
87 | #include "amdgpu_socbb.h" | |
88 | ||
89 | #define TO_DCN301_RES_POOL(pool)\ | |
90 | container_of(pool, struct dcn301_resource_pool, base) | |
91 | ||
92 | #define DC_LOGGER_INIT(logger) | |
93 | ||
94 | struct _vcs_dpi_ip_params_st dcn3_01_ip = { | |
95 | .odm_capable = 1, | |
96 | .gpuvm_enable = 1, | |
97 | .hostvm_enable = 1, | |
98 | .gpuvm_max_page_table_levels = 1, | |
99 | .hostvm_max_page_table_levels = 2, | |
100 | .hostvm_cached_page_table_levels = 0, | |
101 | .pte_group_size_bytes = 2048, | |
102 | .num_dsc = 3, | |
103 | .rob_buffer_size_kbytes = 184, | |
104 | .det_buffer_size_kbytes = 184, | |
105 | .dpte_buffer_size_in_pte_reqs_luma = 64, | |
106 | .dpte_buffer_size_in_pte_reqs_chroma = 32, | |
107 | .pde_proc_buffer_size_64k_reqs = 48, | |
108 | .dpp_output_buffer_pixels = 2560, | |
109 | .opp_output_buffer_lines = 1, | |
110 | .pixel_chunk_size_kbytes = 8, | |
111 | .meta_chunk_size_kbytes = 2, | |
112 | .writeback_chunk_size_kbytes = 8, | |
113 | .line_buffer_size_bits = 789504, | |
114 | .is_line_buffer_bpp_fixed = 0, // ? | |
115 | .line_buffer_fixed_bpp = 48, // ? | |
116 | .dcc_supported = true, | |
117 | .writeback_interface_buffer_size_kbytes = 90, | |
118 | .writeback_line_buffer_buffer_size = 656640, | |
119 | .max_line_buffer_lines = 12, | |
120 | .writeback_luma_buffer_size_kbytes = 12, // writeback_line_buffer_buffer_size = 656640 | |
121 | .writeback_chroma_buffer_size_kbytes = 8, | |
122 | .writeback_chroma_line_buffer_width_pixels = 4, | |
123 | .writeback_max_hscl_ratio = 1, | |
124 | .writeback_max_vscl_ratio = 1, | |
125 | .writeback_min_hscl_ratio = 1, | |
126 | .writeback_min_vscl_ratio = 1, | |
127 | .writeback_max_hscl_taps = 1, | |
128 | .writeback_max_vscl_taps = 1, | |
129 | .writeback_line_buffer_luma_buffer_size = 0, | |
130 | .writeback_line_buffer_chroma_buffer_size = 14643, | |
131 | .cursor_buffer_size = 8, | |
132 | .cursor_chunk_size = 2, | |
133 | .max_num_otg = 4, | |
134 | .max_num_dpp = 4, | |
135 | .max_num_wb = 1, | |
136 | .max_dchub_pscl_bw_pix_per_clk = 4, | |
137 | .max_pscl_lb_bw_pix_per_clk = 2, | |
138 | .max_lb_vscl_bw_pix_per_clk = 4, | |
139 | .max_vscl_hscl_bw_pix_per_clk = 4, | |
140 | .max_hscl_ratio = 6, | |
141 | .max_vscl_ratio = 6, | |
142 | .hscl_mults = 4, | |
143 | .vscl_mults = 4, | |
144 | .max_hscl_taps = 8, | |
145 | .max_vscl_taps = 8, | |
146 | .dispclk_ramp_margin_percent = 1, | |
147 | .underscan_factor = 1.11, | |
148 | .min_vblank_lines = 32, | |
149 | .dppclk_delay_subtotal = 46, | |
150 | .dynamic_metadata_vm_enabled = true, | |
151 | .dppclk_delay_scl_lb_only = 16, | |
152 | .dppclk_delay_scl = 50, | |
153 | .dppclk_delay_cnvc_formatter = 27, | |
154 | .dppclk_delay_cnvc_cursor = 6, | |
155 | .dispclk_delay_subtotal = 119, | |
156 | .dcfclk_cstate_latency = 5.2, // SRExitTime | |
157 | .max_inter_dcn_tile_repeaters = 8, | |
158 | .max_num_hdmi_frl_outputs = 0, | |
159 | .odm_combine_4to1_supported = true, | |
160 | ||
161 | .xfc_supported = false, | |
162 | .xfc_fill_bw_overhead_percent = 10.0, | |
163 | .xfc_fill_constant_bytes = 0, | |
164 | .gfx7_compat_tiling_supported = 0, | |
165 | .number_of_cursors = 1, | |
166 | }; | |
167 | ||
168 | struct _vcs_dpi_soc_bounding_box_st dcn3_01_soc = { | |
169 | .clock_limits = { | |
3a83e4e6 RL |
170 | { |
171 | .state = 0, | |
c6ce6d19 YS |
172 | .dram_speed_mts = 2400.0, |
173 | .fabricclk_mhz = 600, | |
174 | .socclk_mhz = 278.0, | |
175 | .dcfclk_mhz = 400.0, | |
176 | .dscclk_mhz = 206.0, | |
177 | .dppclk_mhz = 1015.0, | |
178 | .dispclk_mhz = 1015.0, | |
179 | .phyclk_mhz = 600.0, | |
180 | }, | |
181 | { | |
182 | .state = 1, | |
183 | .dram_speed_mts = 2400.0, | |
184 | .fabricclk_mhz = 688, | |
185 | .socclk_mhz = 278.0, | |
186 | .dcfclk_mhz = 400.0, | |
187 | .dscclk_mhz = 206.0, | |
188 | .dppclk_mhz = 1015.0, | |
3a83e4e6 | 189 | .dispclk_mhz = 1015.0, |
c6ce6d19 YS |
190 | .phyclk_mhz = 600.0, |
191 | }, | |
192 | { | |
193 | .state = 2, | |
194 | .dram_speed_mts = 4267.0, | |
195 | .fabricclk_mhz = 1067, | |
196 | .socclk_mhz = 278.0, | |
197 | .dcfclk_mhz = 608.0, | |
198 | .dscclk_mhz = 296.0, | |
3a83e4e6 | 199 | .dppclk_mhz = 1015.0, |
c6ce6d19 | 200 | .dispclk_mhz = 1015.0, |
3a83e4e6 | 201 | .phyclk_mhz = 810.0, |
c6ce6d19 YS |
202 | }, |
203 | ||
204 | { | |
205 | .state = 3, | |
206 | .dram_speed_mts = 4267.0, | |
207 | .fabricclk_mhz = 1067, | |
208 | .socclk_mhz = 715.0, | |
209 | .dcfclk_mhz = 676.0, | |
3a83e4e6 | 210 | .dscclk_mhz = 338.0, |
c6ce6d19 YS |
211 | .dppclk_mhz = 1015.0, |
212 | .dispclk_mhz = 1015.0, | |
213 | .phyclk_mhz = 810.0, | |
3a83e4e6 | 214 | }, |
c6ce6d19 | 215 | |
3a83e4e6 | 216 | { |
c6ce6d19 YS |
217 | .state = 4, |
218 | .dram_speed_mts = 4267.0, | |
219 | .fabricclk_mhz = 1067, | |
220 | .socclk_mhz = 953.0, | |
3a83e4e6 | 221 | .dcfclk_mhz = 810.0, |
c6ce6d19 | 222 | .dscclk_mhz = 338.0, |
3a83e4e6 | 223 | .dppclk_mhz = 1015.0, |
c6ce6d19 | 224 | .dispclk_mhz = 1015.0, |
3a83e4e6 | 225 | .phyclk_mhz = 810.0, |
c6ce6d19 | 226 | }, |
3a83e4e6 RL |
227 | }, |
228 | ||
229 | .sr_exit_time_us = 9.0, | |
230 | .sr_enter_plus_exit_time_us = 11.0, | |
231 | .urgent_latency_us = 4.0, | |
232 | .urgent_latency_pixel_data_only_us = 4.0, | |
233 | .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, | |
234 | .urgent_latency_vm_data_only_us = 4.0, | |
235 | .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, | |
236 | .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, | |
237 | .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, | |
238 | .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, | |
239 | .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0, | |
240 | .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, | |
241 | .max_avg_sdp_bw_use_normal_percent = 60.0, | |
242 | .max_avg_dram_bw_use_normal_percent = 60.0, | |
243 | .writeback_latency_us = 12.0, | |
244 | .max_request_size_bytes = 256, | |
245 | .dram_channel_width_bytes = 4, | |
246 | .fabric_datapath_to_dcn_data_return_bytes = 32, | |
247 | .dcn_downspread_percent = 0.5, | |
248 | .downspread_percent = 0.38, | |
249 | .dram_page_open_time_ns = 50.0, | |
250 | .dram_rw_turnaround_time_ns = 17.5, | |
251 | .dram_return_buffer_per_channel_bytes = 8192, | |
252 | .round_trip_ping_latency_dcfclk_cycles = 191, | |
253 | .urgent_out_of_order_return_per_channel_bytes = 4096, | |
254 | .channel_interleave_bytes = 256, | |
255 | .num_banks = 8, | |
256 | .num_chans = 4, | |
257 | .gpuvm_min_page_size_bytes = 4096, | |
258 | .hostvm_min_page_size_bytes = 4096, | |
259 | .dram_clock_change_latency_us = 23.84, | |
260 | .writeback_dram_clock_change_latency_us = 23.0, | |
261 | .return_bus_width_bytes = 64, | |
262 | .dispclk_dppclk_vco_speed_mhz = 3550, | |
263 | .xfc_bus_transport_time_us = 20, // ? | |
264 | .xfc_xbuf_latency_tolerance_us = 4, // ? | |
265 | .use_urgent_burst_bw = 1, // ? | |
c6ce6d19 | 266 | .num_states = 5, |
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267 | .do_urgent_latency_adjustment = false, |
268 | .urgent_latency_adjustment_fabric_clock_component_us = 0, | |
269 | .urgent_latency_adjustment_fabric_clock_reference_mhz = 0, | |
270 | }; | |
271 | ||
272 | enum dcn301_clk_src_array_id { | |
273 | DCN301_CLK_SRC_PLL0, | |
274 | DCN301_CLK_SRC_PLL1, | |
275 | DCN301_CLK_SRC_PLL2, | |
276 | DCN301_CLK_SRC_PLL3, | |
277 | DCN301_CLK_SRC_TOTAL | |
278 | }; | |
279 | ||
280 | /* begin ********************* | |
281 | * macros to expend register list macro defined in HW object header file | |
282 | */ | |
283 | ||
284 | /* DCN */ | |
285 | /* TODO awful hack. fixup dcn20_dwb.h */ | |
286 | #undef BASE_INNER | |
287 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg | |
288 | ||
289 | #define BASE(seg) BASE_INNER(seg) | |
290 | ||
291 | #define SR(reg_name)\ | |
292 | .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ | |
293 | mm ## reg_name | |
294 | ||
295 | #define SRI(reg_name, block, id)\ | |
296 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | |
297 | mm ## block ## id ## _ ## reg_name | |
298 | ||
299 | #define SRI2(reg_name, block, id)\ | |
300 | .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ | |
301 | mm ## reg_name | |
302 | ||
303 | #define SRIR(var_name, reg_name, block, id)\ | |
304 | .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | |
305 | mm ## block ## id ## _ ## reg_name | |
306 | ||
307 | #define SRII(reg_name, block, id)\ | |
308 | .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | |
309 | mm ## block ## id ## _ ## reg_name | |
310 | ||
311 | #define SRII2(reg_name_pre, reg_name_post, id)\ | |
312 | .reg_name_pre ## _ ## reg_name_post[id] = BASE(mm ## reg_name_pre \ | |
313 | ## id ## _ ## reg_name_post ## _BASE_IDX) + \ | |
314 | mm ## reg_name_pre ## id ## _ ## reg_name_post | |
315 | ||
316 | #define SRII_MPC_RMU(reg_name, block, id)\ | |
317 | .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | |
318 | mm ## block ## id ## _ ## reg_name | |
319 | ||
320 | #define SRII_DWB(reg_name, temp_name, block, id)\ | |
321 | .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ | |
322 | mm ## block ## id ## _ ## temp_name | |
323 | ||
324 | #define DCCG_SRII(reg_name, block, id)\ | |
325 | .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | |
326 | mm ## block ## id ## _ ## reg_name | |
327 | ||
328 | #define VUPDATE_SRII(reg_name, block, id)\ | |
329 | .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ | |
330 | mm ## reg_name ## _ ## block ## id | |
331 | ||
332 | /* NBIO */ | |
333 | #define NBIO_BASE_INNER(seg) \ | |
334 | NBIO_BASE__INST0_SEG ## seg | |
335 | ||
336 | #define NBIO_BASE(seg) \ | |
337 | NBIO_BASE_INNER(seg) | |
338 | ||
339 | #define NBIO_SR(reg_name)\ | |
340 | .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ | |
341 | regBIF_BX0_ ## reg_name | |
342 | ||
343 | /* MMHUB */ | |
344 | #define MMHUB_BASE_INNER(seg) \ | |
345 | MMHUB_BASE__INST0_SEG ## seg | |
346 | ||
347 | #define MMHUB_BASE(seg) \ | |
348 | MMHUB_BASE_INNER(seg) | |
349 | ||
350 | #define MMHUB_SR(reg_name)\ | |
351 | .reg_name = MMHUB_BASE(regMM ## reg_name ## _BASE_IDX) + \ | |
352 | regMM ## reg_name | |
353 | ||
354 | /* CLOCK */ | |
355 | #define CLK_BASE_INNER(seg) \ | |
356 | CLK_BASE__INST0_SEG ## seg | |
357 | ||
358 | #define CLK_BASE(seg) \ | |
359 | CLK_BASE_INNER(seg) | |
360 | ||
361 | #define CLK_SRI(reg_name, block, inst)\ | |
362 | .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ | |
363 | mm ## block ## _ ## inst ## _ ## reg_name | |
364 | ||
365 | static const struct bios_registers bios_regs = { | |
366 | NBIO_SR(BIOS_SCRATCH_3), | |
367 | NBIO_SR(BIOS_SCRATCH_6) | |
368 | }; | |
369 | ||
370 | #define clk_src_regs(index, pllid)\ | |
371 | [index] = {\ | |
372 | CS_COMMON_REG_LIST_DCN3_01(index, pllid),\ | |
373 | } | |
374 | ||
375 | static const struct dce110_clk_src_regs clk_src_regs[] = { | |
376 | clk_src_regs(0, A), | |
377 | clk_src_regs(1, B), | |
378 | clk_src_regs(2, C), | |
379 | clk_src_regs(3, D) | |
380 | }; | |
381 | ||
382 | static const struct dce110_clk_src_shift cs_shift = { | |
383 | CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) | |
384 | }; | |
385 | ||
386 | static const struct dce110_clk_src_mask cs_mask = { | |
387 | CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) | |
388 | }; | |
389 | ||
390 | #define abm_regs(id)\ | |
391 | [id] = {\ | |
392 | ABM_DCN301_REG_LIST(id)\ | |
393 | } | |
394 | ||
395 | static const struct dce_abm_registers abm_regs[] = { | |
396 | abm_regs(0), | |
397 | abm_regs(1), | |
398 | abm_regs(2), | |
399 | abm_regs(3), | |
400 | }; | |
401 | ||
402 | static const struct dce_abm_shift abm_shift = { | |
df043738 | 403 | ABM_MASK_SH_LIST_DCN30(__SHIFT) |
3a83e4e6 RL |
404 | }; |
405 | ||
406 | static const struct dce_abm_mask abm_mask = { | |
df043738 | 407 | ABM_MASK_SH_LIST_DCN30(_MASK) |
3a83e4e6 RL |
408 | }; |
409 | ||
410 | #define audio_regs(id)\ | |
411 | [id] = {\ | |
412 | AUD_COMMON_REG_LIST(id)\ | |
413 | } | |
414 | ||
415 | static const struct dce_audio_registers audio_regs[] = { | |
416 | audio_regs(0), | |
417 | audio_regs(1), | |
418 | audio_regs(2), | |
419 | audio_regs(3), | |
420 | audio_regs(4), | |
421 | audio_regs(5), | |
422 | audio_regs(6) | |
423 | }; | |
424 | ||
425 | #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ | |
426 | SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ | |
427 | SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ | |
428 | AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) | |
429 | ||
430 | static const struct dce_audio_shift audio_shift = { | |
431 | DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) | |
432 | }; | |
433 | ||
434 | static const struct dce_audio_mask audio_mask = { | |
435 | DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) | |
436 | }; | |
437 | ||
438 | #define vpg_regs(id)\ | |
439 | [id] = {\ | |
440 | VPG_DCN3_REG_LIST(id)\ | |
441 | } | |
442 | ||
443 | static const struct dcn30_vpg_registers vpg_regs[] = { | |
444 | vpg_regs(0), | |
445 | vpg_regs(1), | |
446 | vpg_regs(2), | |
447 | vpg_regs(3), | |
448 | }; | |
449 | ||
450 | static const struct dcn30_vpg_shift vpg_shift = { | |
451 | DCN3_VPG_MASK_SH_LIST(__SHIFT) | |
452 | }; | |
453 | ||
454 | static const struct dcn30_vpg_mask vpg_mask = { | |
455 | DCN3_VPG_MASK_SH_LIST(_MASK) | |
456 | }; | |
457 | ||
458 | #define afmt_regs(id)\ | |
459 | [id] = {\ | |
460 | AFMT_DCN3_REG_LIST(id)\ | |
461 | } | |
462 | ||
463 | static const struct dcn30_afmt_registers afmt_regs[] = { | |
464 | afmt_regs(0), | |
465 | afmt_regs(1), | |
466 | afmt_regs(2), | |
467 | afmt_regs(3), | |
468 | }; | |
469 | ||
470 | static const struct dcn30_afmt_shift afmt_shift = { | |
471 | DCN3_AFMT_MASK_SH_LIST(__SHIFT) | |
472 | }; | |
473 | ||
474 | static const struct dcn30_afmt_mask afmt_mask = { | |
475 | DCN3_AFMT_MASK_SH_LIST(_MASK) | |
476 | }; | |
477 | ||
478 | #define stream_enc_regs(id)\ | |
479 | [id] = {\ | |
480 | SE_DCN3_REG_LIST(id)\ | |
481 | } | |
482 | ||
483 | static const struct dcn10_stream_enc_registers stream_enc_regs[] = { | |
484 | stream_enc_regs(0), | |
485 | stream_enc_regs(1), | |
486 | stream_enc_regs(2), | |
487 | stream_enc_regs(3), | |
488 | }; | |
489 | ||
490 | static const struct dcn10_stream_encoder_shift se_shift = { | |
491 | SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) | |
492 | }; | |
493 | ||
494 | static const struct dcn10_stream_encoder_mask se_mask = { | |
495 | SE_COMMON_MASK_SH_LIST_DCN30(_MASK) | |
496 | }; | |
497 | ||
498 | ||
499 | #define aux_regs(id)\ | |
500 | [id] = {\ | |
501 | DCN2_AUX_REG_LIST(id)\ | |
502 | } | |
503 | ||
504 | static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { | |
505 | aux_regs(0), | |
506 | aux_regs(1), | |
507 | aux_regs(2), | |
508 | aux_regs(3), | |
509 | }; | |
510 | ||
511 | #define hpd_regs(id)\ | |
512 | [id] = {\ | |
513 | HPD_REG_LIST(id)\ | |
514 | } | |
515 | ||
516 | static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { | |
517 | hpd_regs(0), | |
518 | hpd_regs(1), | |
519 | hpd_regs(2), | |
520 | hpd_regs(3), | |
521 | }; | |
522 | ||
f5041bc1 | 523 | |
3a83e4e6 RL |
524 | #define link_regs(id, phyid)\ |
525 | [id] = {\ | |
526 | LE_DCN301_REG_LIST(id), \ | |
527 | UNIPHY_DCN2_REG_LIST(phyid), \ | |
f5041bc1 | 528 | DPCS_DCN2_REG_LIST(id), \ |
41fd932e | 529 | SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ |
3a83e4e6 RL |
530 | } |
531 | ||
532 | static const struct dce110_aux_registers_shift aux_shift = { | |
533 | DCN_AUX_MASK_SH_LIST(__SHIFT) | |
534 | }; | |
535 | ||
536 | static const struct dce110_aux_registers_mask aux_mask = { | |
537 | DCN_AUX_MASK_SH_LIST(_MASK) | |
538 | }; | |
539 | ||
540 | static const struct dcn10_link_enc_registers link_enc_regs[] = { | |
541 | link_regs(0, A), | |
542 | link_regs(1, B), | |
543 | link_regs(2, C), | |
544 | link_regs(3, D), | |
545 | }; | |
546 | ||
547 | static const struct dcn10_link_enc_shift le_shift = { | |
f5041bc1 ZL |
548 | LINK_ENCODER_MASK_SH_LIST_DCN301(__SHIFT),\ |
549 | DPCS_DCN2_MASK_SH_LIST(__SHIFT) | |
3a83e4e6 RL |
550 | }; |
551 | ||
552 | static const struct dcn10_link_enc_mask le_mask = { | |
f5041bc1 ZL |
553 | LINK_ENCODER_MASK_SH_LIST_DCN301(_MASK),\ |
554 | DPCS_DCN2_MASK_SH_LIST(_MASK) | |
3a83e4e6 RL |
555 | }; |
556 | ||
557 | #define panel_cntl_regs(id)\ | |
558 | [id] = {\ | |
559 | DCN301_PANEL_CNTL_REG_LIST(id),\ | |
560 | } | |
561 | ||
562 | static const struct dce_panel_cntl_registers panel_cntl_regs[] = { | |
563 | panel_cntl_regs(0), | |
564 | panel_cntl_regs(1), | |
565 | }; | |
566 | ||
567 | static const struct dcn301_panel_cntl_shift panel_cntl_shift = { | |
568 | DCN301_PANEL_CNTL_MASK_SH_LIST(__SHIFT) | |
569 | }; | |
570 | ||
571 | static const struct dcn301_panel_cntl_mask panel_cntl_mask = { | |
572 | DCN301_PANEL_CNTL_MASK_SH_LIST(_MASK) | |
573 | }; | |
574 | ||
575 | #define dpp_regs(id)\ | |
576 | [id] = {\ | |
577 | DPP_REG_LIST_DCN30(id),\ | |
578 | } | |
579 | ||
580 | static const struct dcn3_dpp_registers dpp_regs[] = { | |
581 | dpp_regs(0), | |
582 | dpp_regs(1), | |
583 | dpp_regs(2), | |
584 | dpp_regs(3), | |
585 | }; | |
586 | ||
587 | static const struct dcn3_dpp_shift tf_shift = { | |
588 | DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) | |
589 | }; | |
590 | ||
591 | static const struct dcn3_dpp_mask tf_mask = { | |
592 | DPP_REG_LIST_SH_MASK_DCN30(_MASK) | |
593 | }; | |
594 | ||
595 | #define opp_regs(id)\ | |
596 | [id] = {\ | |
597 | OPP_REG_LIST_DCN30(id),\ | |
598 | } | |
599 | ||
600 | static const struct dcn20_opp_registers opp_regs[] = { | |
601 | opp_regs(0), | |
602 | opp_regs(1), | |
603 | opp_regs(2), | |
604 | opp_regs(3), | |
605 | }; | |
606 | ||
607 | static const struct dcn20_opp_shift opp_shift = { | |
608 | OPP_MASK_SH_LIST_DCN20(__SHIFT) | |
609 | }; | |
610 | ||
611 | static const struct dcn20_opp_mask opp_mask = { | |
612 | OPP_MASK_SH_LIST_DCN20(_MASK) | |
613 | }; | |
614 | ||
615 | #define aux_engine_regs(id)\ | |
616 | [id] = {\ | |
617 | AUX_COMMON_REG_LIST0(id), \ | |
618 | .AUXN_IMPCAL = 0, \ | |
619 | .AUXP_IMPCAL = 0, \ | |
620 | .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ | |
621 | } | |
622 | ||
623 | static const struct dce110_aux_registers aux_engine_regs[] = { | |
624 | aux_engine_regs(0), | |
625 | aux_engine_regs(1), | |
626 | aux_engine_regs(2), | |
627 | aux_engine_regs(3), | |
628 | }; | |
629 | ||
630 | #define dwbc_regs_dcn3(id)\ | |
631 | [id] = {\ | |
632 | DWBC_COMMON_REG_LIST_DCN30(id),\ | |
633 | } | |
634 | ||
635 | static const struct dcn30_dwbc_registers dwbc30_regs[] = { | |
636 | dwbc_regs_dcn3(0), | |
637 | }; | |
638 | ||
639 | static const struct dcn30_dwbc_shift dwbc30_shift = { | |
640 | DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) | |
641 | }; | |
642 | ||
643 | static const struct dcn30_dwbc_mask dwbc30_mask = { | |
644 | DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) | |
645 | }; | |
646 | ||
647 | #define mcif_wb_regs_dcn3(id)\ | |
648 | [id] = {\ | |
649 | MCIF_WB_COMMON_REG_LIST_DCN30(id),\ | |
650 | } | |
651 | ||
652 | static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { | |
653 | mcif_wb_regs_dcn3(0) | |
654 | }; | |
655 | ||
656 | static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { | |
657 | MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) | |
658 | }; | |
659 | ||
660 | static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { | |
661 | MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) | |
662 | }; | |
663 | ||
664 | #define dsc_regsDCN20(id)\ | |
665 | [id] = {\ | |
666 | DSC_REG_LIST_DCN20(id)\ | |
667 | } | |
668 | ||
669 | static const struct dcn20_dsc_registers dsc_regs[] = { | |
670 | dsc_regsDCN20(0), | |
671 | dsc_regsDCN20(1), | |
672 | dsc_regsDCN20(2), | |
673 | }; | |
674 | ||
675 | static const struct dcn20_dsc_shift dsc_shift = { | |
676 | DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) | |
677 | }; | |
678 | ||
679 | static const struct dcn20_dsc_mask dsc_mask = { | |
680 | DSC_REG_LIST_SH_MASK_DCN20(_MASK) | |
681 | }; | |
682 | ||
683 | static const struct dcn30_mpc_registers mpc_regs = { | |
684 | MPC_REG_LIST_DCN3_0(0), | |
685 | MPC_REG_LIST_DCN3_0(1), | |
686 | MPC_REG_LIST_DCN3_0(2), | |
687 | MPC_REG_LIST_DCN3_0(3), | |
688 | MPC_OUT_MUX_REG_LIST_DCN3_0(0), | |
689 | MPC_OUT_MUX_REG_LIST_DCN3_0(1), | |
690 | MPC_OUT_MUX_REG_LIST_DCN3_0(2), | |
691 | MPC_OUT_MUX_REG_LIST_DCN3_0(3), | |
692 | MPC_RMU_GLOBAL_REG_LIST_DCN3AG, | |
693 | MPC_RMU_REG_LIST_DCN3AG(0), | |
694 | MPC_RMU_REG_LIST_DCN3AG(1), | |
695 | MPC_DWB_MUX_REG_LIST_DCN3_0(0), | |
696 | }; | |
697 | ||
698 | static const struct dcn30_mpc_shift mpc_shift = { | |
699 | MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) | |
700 | }; | |
701 | ||
702 | static const struct dcn30_mpc_mask mpc_mask = { | |
703 | MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) | |
704 | }; | |
705 | ||
706 | #define optc_regs(id)\ | |
707 | [id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)} | |
708 | ||
709 | ||
710 | static const struct dcn_optc_registers optc_regs[] = { | |
711 | optc_regs(0), | |
712 | optc_regs(1), | |
713 | optc_regs(2), | |
714 | optc_regs(3), | |
715 | }; | |
716 | ||
717 | static const struct dcn_optc_shift optc_shift = { | |
718 | OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) | |
719 | }; | |
720 | ||
721 | static const struct dcn_optc_mask optc_mask = { | |
722 | OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) | |
723 | }; | |
724 | ||
725 | #define hubp_regs(id)\ | |
726 | [id] = {\ | |
727 | HUBP_REG_LIST_DCN30(id)\ | |
728 | } | |
729 | ||
730 | static const struct dcn_hubp2_registers hubp_regs[] = { | |
731 | hubp_regs(0), | |
732 | hubp_regs(1), | |
733 | hubp_regs(2), | |
734 | hubp_regs(3), | |
735 | }; | |
736 | ||
737 | static const struct dcn_hubp2_shift hubp_shift = { | |
738 | HUBP_MASK_SH_LIST_DCN30(__SHIFT) | |
739 | }; | |
740 | ||
741 | static const struct dcn_hubp2_mask hubp_mask = { | |
742 | HUBP_MASK_SH_LIST_DCN30(_MASK) | |
743 | }; | |
744 | ||
745 | static const struct dcn_hubbub_registers hubbub_reg = { | |
746 | HUBBUB_REG_LIST_DCN301(0) | |
747 | }; | |
748 | ||
749 | static const struct dcn_hubbub_shift hubbub_shift = { | |
750 | HUBBUB_MASK_SH_LIST_DCN301(__SHIFT) | |
751 | }; | |
752 | ||
753 | static const struct dcn_hubbub_mask hubbub_mask = { | |
754 | HUBBUB_MASK_SH_LIST_DCN301(_MASK) | |
755 | }; | |
756 | ||
757 | static const struct dccg_registers dccg_regs = { | |
758 | DCCG_REG_LIST_DCN301() | |
759 | }; | |
760 | ||
761 | static const struct dccg_shift dccg_shift = { | |
762 | DCCG_MASK_SH_LIST_DCN301(__SHIFT) | |
763 | }; | |
764 | ||
765 | static const struct dccg_mask dccg_mask = { | |
766 | DCCG_MASK_SH_LIST_DCN301(_MASK) | |
767 | }; | |
768 | ||
769 | static const struct dce_hwseq_registers hwseq_reg = { | |
770 | HWSEQ_DCN301_REG_LIST() | |
771 | }; | |
772 | ||
773 | static const struct dce_hwseq_shift hwseq_shift = { | |
774 | HWSEQ_DCN301_MASK_SH_LIST(__SHIFT) | |
775 | }; | |
776 | ||
777 | static const struct dce_hwseq_mask hwseq_mask = { | |
778 | HWSEQ_DCN301_MASK_SH_LIST(_MASK) | |
779 | }; | |
780 | #define vmid_regs(id)\ | |
781 | [id] = {\ | |
782 | DCN20_VMID_REG_LIST(id)\ | |
783 | } | |
784 | ||
785 | static const struct dcn_vmid_registers vmid_regs[] = { | |
786 | vmid_regs(0), | |
787 | vmid_regs(1), | |
788 | vmid_regs(2), | |
789 | vmid_regs(3), | |
790 | vmid_regs(4), | |
791 | vmid_regs(5), | |
792 | vmid_regs(6), | |
793 | vmid_regs(7), | |
794 | vmid_regs(8), | |
795 | vmid_regs(9), | |
796 | vmid_regs(10), | |
797 | vmid_regs(11), | |
798 | vmid_regs(12), | |
799 | vmid_regs(13), | |
800 | vmid_regs(14), | |
801 | vmid_regs(15) | |
802 | }; | |
803 | ||
804 | static const struct dcn20_vmid_shift vmid_shifts = { | |
805 | DCN20_VMID_MASK_SH_LIST(__SHIFT) | |
806 | }; | |
807 | ||
808 | static const struct dcn20_vmid_mask vmid_masks = { | |
809 | DCN20_VMID_MASK_SH_LIST(_MASK) | |
810 | }; | |
811 | ||
812 | static const struct resource_caps res_cap_dcn301 = { | |
813 | .num_timing_generator = 4, | |
814 | .num_opp = 4, | |
815 | .num_video_plane = 4, | |
816 | .num_audio = 4, | |
817 | .num_stream_encoder = 4, | |
818 | .num_pll = 4, | |
819 | .num_dwb = 1, | |
820 | .num_ddc = 4, | |
821 | .num_vmid = 16, | |
822 | .num_mpc_3dlut = 2, | |
823 | .num_dsc = 3, | |
824 | }; | |
825 | ||
826 | static const struct dc_plane_cap plane_cap = { | |
827 | .type = DC_PLANE_TYPE_DCN_UNIVERSAL, | |
828 | .blends_with_above = true, | |
829 | .blends_with_below = true, | |
830 | .per_pixel_alpha = true, | |
831 | ||
832 | .pixel_format_support = { | |
833 | .argb8888 = true, | |
834 | .nv12 = true, | |
835 | .fp16 = true, | |
836 | .p010 = false, | |
837 | .ayuv = false, | |
838 | }, | |
839 | ||
840 | .max_upscale_factor = { | |
841 | .argb8888 = 16000, | |
842 | .nv12 = 16000, | |
843 | .fp16 = 16000 | |
844 | }, | |
845 | ||
846 | .max_downscale_factor = { | |
847 | .argb8888 = 600, | |
848 | .nv12 = 600, | |
849 | .fp16 = 600 | |
850 | }, | |
851 | 64, | |
852 | 64 | |
853 | }; | |
854 | ||
855 | static const struct dc_debug_options debug_defaults_drv = { | |
856 | .disable_dmcu = true, | |
857 | .force_abm_enable = false, | |
858 | .timing_trace = false, | |
859 | .clock_trace = true, | |
823b3169 SJK |
860 | .disable_dpp_power_gate = false, |
861 | .disable_hubp_power_gate = false, | |
3a83e4e6 RL |
862 | .disable_clock_gate = true, |
863 | .disable_pplib_clock_request = true, | |
864 | .disable_pplib_wm_range = true, | |
3a83e4e6 RL |
865 | .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, |
866 | .force_single_disp_pipe_split = false, | |
867 | .disable_dcc = DCC_ENABLE, | |
868 | .vsr_support = true, | |
869 | .performance_trace = false, | |
870 | .max_downscale_src_width = 7680,/*upto 8K*/ | |
871 | .scl_reset_length10 = true, | |
872 | .sanity_checks = false, | |
873 | .underflow_assert_delay_us = 0xFFFFFFFF, | |
874 | .dwb_fi_phase = -1, // -1 = disable | |
875 | .dmub_command_table = true, | |
876 | }; | |
877 | ||
878 | static const struct dc_debug_options debug_defaults_diags = { | |
879 | .disable_dmcu = true, | |
880 | .force_abm_enable = false, | |
881 | .timing_trace = true, | |
882 | .clock_trace = true, | |
823b3169 SJK |
883 | .disable_dpp_power_gate = false, |
884 | .disable_hubp_power_gate = false, | |
3a83e4e6 RL |
885 | .disable_clock_gate = true, |
886 | .disable_pplib_clock_request = true, | |
887 | .disable_pplib_wm_range = true, | |
888 | .disable_stutter = true, | |
889 | .scl_reset_length10 = true, | |
890 | .dwb_fi_phase = -1, // -1 = disable | |
891 | .dmub_command_table = true, | |
892 | }; | |
893 | ||
894 | void dcn301_dpp_destroy(struct dpp **dpp) | |
895 | { | |
896 | kfree(TO_DCN20_DPP(*dpp)); | |
897 | *dpp = NULL; | |
898 | } | |
899 | ||
900 | struct dpp *dcn301_dpp_create( | |
901 | struct dc_context *ctx, | |
902 | uint32_t inst) | |
903 | { | |
904 | struct dcn3_dpp *dpp = | |
905 | kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); | |
906 | ||
907 | if (!dpp) | |
908 | return NULL; | |
909 | ||
910 | if (dpp3_construct(dpp, ctx, inst, | |
911 | &dpp_regs[inst], &tf_shift, &tf_mask)) | |
912 | return &dpp->base; | |
913 | ||
914 | BREAK_TO_DEBUGGER(); | |
915 | kfree(dpp); | |
916 | return NULL; | |
917 | } | |
918 | struct output_pixel_processor *dcn301_opp_create( | |
919 | struct dc_context *ctx, uint32_t inst) | |
920 | { | |
921 | struct dcn20_opp *opp = | |
922 | kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); | |
923 | ||
924 | if (!opp) { | |
925 | BREAK_TO_DEBUGGER(); | |
926 | return NULL; | |
927 | } | |
928 | ||
929 | dcn20_opp_construct(opp, ctx, inst, | |
930 | &opp_regs[inst], &opp_shift, &opp_mask); | |
931 | return &opp->base; | |
932 | } | |
933 | ||
934 | struct dce_aux *dcn301_aux_engine_create( | |
935 | struct dc_context *ctx, | |
936 | uint32_t inst) | |
937 | { | |
938 | struct aux_engine_dce110 *aux_engine = | |
939 | kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); | |
940 | ||
941 | if (!aux_engine) | |
942 | return NULL; | |
943 | ||
944 | dce110_aux_engine_construct(aux_engine, ctx, inst, | |
945 | SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, | |
946 | &aux_engine_regs[inst], | |
947 | &aux_mask, | |
948 | &aux_shift, | |
949 | ctx->dc->caps.extended_aux_timeout_support); | |
950 | ||
951 | return &aux_engine->base; | |
952 | } | |
953 | #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } | |
954 | ||
955 | static const struct dce_i2c_registers i2c_hw_regs[] = { | |
956 | i2c_inst_regs(1), | |
957 | i2c_inst_regs(2), | |
958 | i2c_inst_regs(3), | |
959 | i2c_inst_regs(4), | |
960 | }; | |
961 | ||
962 | static const struct dce_i2c_shift i2c_shifts = { | |
963 | I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) | |
964 | }; | |
965 | ||
966 | static const struct dce_i2c_mask i2c_masks = { | |
967 | I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) | |
968 | }; | |
969 | ||
970 | struct dce_i2c_hw *dcn301_i2c_hw_create( | |
971 | struct dc_context *ctx, | |
972 | uint32_t inst) | |
973 | { | |
974 | struct dce_i2c_hw *dce_i2c_hw = | |
975 | kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); | |
976 | ||
977 | if (!dce_i2c_hw) | |
978 | return NULL; | |
979 | ||
980 | dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, | |
981 | &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); | |
982 | ||
983 | return dce_i2c_hw; | |
984 | } | |
985 | static struct mpc *dcn301_mpc_create( | |
986 | struct dc_context *ctx, | |
987 | int num_mpcc, | |
988 | int num_rmu) | |
989 | { | |
990 | struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), | |
991 | GFP_KERNEL); | |
992 | ||
993 | if (!mpc30) | |
994 | return NULL; | |
995 | ||
996 | dcn30_mpc_construct(mpc30, ctx, | |
997 | &mpc_regs, | |
998 | &mpc_shift, | |
999 | &mpc_mask, | |
1000 | num_mpcc, | |
1001 | num_rmu); | |
1002 | ||
1003 | return &mpc30->base; | |
1004 | } | |
1005 | ||
1006 | struct hubbub *dcn301_hubbub_create(struct dc_context *ctx) | |
1007 | { | |
1008 | int i; | |
1009 | ||
1010 | struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), | |
1011 | GFP_KERNEL); | |
1012 | ||
1013 | if (!hubbub3) | |
1014 | return NULL; | |
1015 | ||
1016 | hubbub301_construct(hubbub3, ctx, | |
1017 | &hubbub_reg, | |
1018 | &hubbub_shift, | |
1019 | &hubbub_mask); | |
1020 | ||
1021 | ||
1022 | for (i = 0; i < res_cap_dcn301.num_vmid; i++) { | |
1023 | struct dcn20_vmid *vmid = &hubbub3->vmid[i]; | |
1024 | ||
1025 | vmid->ctx = ctx; | |
1026 | ||
1027 | vmid->regs = &vmid_regs[i]; | |
1028 | vmid->shifts = &vmid_shifts; | |
1029 | vmid->masks = &vmid_masks; | |
1030 | } | |
1031 | ||
1032 | hubbub3->num_vmid = res_cap_dcn301.num_vmid; | |
1033 | ||
1034 | return &hubbub3->base; | |
1035 | } | |
1036 | ||
1037 | struct timing_generator *dcn301_timing_generator_create( | |
1038 | struct dc_context *ctx, | |
1039 | uint32_t instance) | |
1040 | { | |
1041 | struct optc *tgn10 = | |
1042 | kzalloc(sizeof(struct optc), GFP_KERNEL); | |
1043 | ||
1044 | if (!tgn10) | |
1045 | return NULL; | |
1046 | ||
1047 | tgn10->base.inst = instance; | |
1048 | tgn10->base.ctx = ctx; | |
1049 | ||
1050 | tgn10->tg_regs = &optc_regs[instance]; | |
1051 | tgn10->tg_shift = &optc_shift; | |
1052 | tgn10->tg_mask = &optc_mask; | |
1053 | ||
1054 | dcn30_timing_generator_init(tgn10); | |
1055 | ||
1056 | return &tgn10->base; | |
1057 | } | |
1058 | ||
1059 | static const struct encoder_feature_support link_enc_feature = { | |
1060 | .max_hdmi_deep_color = COLOR_DEPTH_121212, | |
1061 | .max_hdmi_pixel_clock = 600000, | |
1062 | .hdmi_ycbcr420_supported = true, | |
1063 | .dp_ycbcr420_supported = true, | |
1064 | .fec_supported = true, | |
1065 | .flags.bits.IS_HBR2_CAPABLE = true, | |
1066 | .flags.bits.IS_HBR3_CAPABLE = true, | |
1067 | .flags.bits.IS_TPS3_CAPABLE = true, | |
1068 | .flags.bits.IS_TPS4_CAPABLE = true | |
1069 | }; | |
1070 | ||
1071 | struct link_encoder *dcn301_link_encoder_create( | |
1072 | const struct encoder_init_data *enc_init_data) | |
1073 | { | |
1074 | struct dcn20_link_encoder *enc20 = | |
1075 | kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); | |
1076 | ||
1077 | if (!enc20) | |
1078 | return NULL; | |
1079 | ||
1080 | dcn301_link_encoder_construct(enc20, | |
1081 | enc_init_data, | |
1082 | &link_enc_feature, | |
1083 | &link_enc_regs[enc_init_data->transmitter], | |
1084 | &link_enc_aux_regs[enc_init_data->channel - 1], | |
1085 | &link_enc_hpd_regs[enc_init_data->hpd_source], | |
1086 | &le_shift, | |
1087 | &le_mask); | |
1088 | ||
1089 | return &enc20->enc10.base; | |
1090 | } | |
1091 | ||
1092 | struct panel_cntl *dcn301_panel_cntl_create(const struct panel_cntl_init_data *init_data) | |
1093 | { | |
1094 | struct dcn301_panel_cntl *panel_cntl = | |
1095 | kzalloc(sizeof(struct dcn301_panel_cntl), GFP_KERNEL); | |
1096 | ||
1097 | if (!panel_cntl) | |
1098 | return NULL; | |
1099 | ||
1100 | dcn301_panel_cntl_construct(panel_cntl, | |
1101 | init_data, | |
1102 | &panel_cntl_regs[init_data->inst], | |
1103 | &panel_cntl_shift, | |
1104 | &panel_cntl_mask); | |
1105 | ||
1106 | return &panel_cntl->base; | |
1107 | } | |
1108 | ||
1109 | ||
1110 | #define CTX ctx | |
1111 | ||
1112 | #define REG(reg_name) \ | |
1113 | (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) | |
1114 | ||
1115 | static uint32_t read_pipe_fuses(struct dc_context *ctx) | |
1116 | { | |
1117 | uint32_t value = REG_READ(CC_DC_PIPE_DIS); | |
1118 | /* RV1 support max 4 pipes */ | |
1119 | value = value & 0xf; | |
1120 | return value; | |
1121 | } | |
1122 | ||
1123 | ||
1124 | static void read_dce_straps( | |
1125 | struct dc_context *ctx, | |
1126 | struct resource_straps *straps) | |
1127 | { | |
1128 | generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), | |
1129 | FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); | |
1130 | ||
1131 | } | |
1132 | ||
1133 | static struct audio *dcn301_create_audio( | |
1134 | struct dc_context *ctx, unsigned int inst) | |
1135 | { | |
1136 | return dce_audio_create(ctx, inst, | |
1137 | &audio_regs[inst], &audio_shift, &audio_mask); | |
1138 | } | |
1139 | ||
1140 | static struct vpg *dcn301_vpg_create( | |
1141 | struct dc_context *ctx, | |
1142 | uint32_t inst) | |
1143 | { | |
1144 | struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); | |
1145 | ||
1146 | if (!vpg3) | |
1147 | return NULL; | |
1148 | ||
1149 | vpg3_construct(vpg3, ctx, inst, | |
1150 | &vpg_regs[inst], | |
1151 | &vpg_shift, | |
1152 | &vpg_mask); | |
1153 | ||
1154 | return &vpg3->base; | |
1155 | } | |
1156 | ||
1157 | static struct afmt *dcn301_afmt_create( | |
1158 | struct dc_context *ctx, | |
1159 | uint32_t inst) | |
1160 | { | |
1161 | struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); | |
1162 | ||
1163 | if (!afmt3) | |
1164 | return NULL; | |
1165 | ||
1166 | afmt3_construct(afmt3, ctx, inst, | |
1167 | &afmt_regs[inst], | |
1168 | &afmt_shift, | |
1169 | &afmt_mask); | |
1170 | ||
1171 | return &afmt3->base; | |
1172 | } | |
1173 | ||
1174 | struct stream_encoder *dcn301_stream_encoder_create( | |
1175 | enum engine_id eng_id, | |
1176 | struct dc_context *ctx) | |
1177 | { | |
1178 | struct dcn10_stream_encoder *enc1; | |
1179 | struct vpg *vpg; | |
1180 | struct afmt *afmt; | |
1181 | int vpg_inst; | |
1182 | int afmt_inst; | |
1183 | ||
1184 | /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ | |
1185 | if (eng_id <= ENGINE_ID_DIGF) { | |
1186 | vpg_inst = eng_id; | |
1187 | afmt_inst = eng_id; | |
1188 | } else | |
1189 | return NULL; | |
1190 | ||
1191 | enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); | |
1192 | vpg = dcn301_vpg_create(ctx, vpg_inst); | |
1193 | afmt = dcn301_afmt_create(ctx, afmt_inst); | |
1194 | ||
1195 | if (!enc1 || !vpg || !afmt) | |
1196 | return NULL; | |
1197 | ||
1198 | dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, | |
1199 | eng_id, vpg, afmt, | |
1200 | &stream_enc_regs[eng_id], | |
1201 | &se_shift, &se_mask); | |
1202 | ||
1203 | return &enc1->base; | |
1204 | } | |
1205 | ||
1206 | struct dce_hwseq *dcn301_hwseq_create( | |
1207 | struct dc_context *ctx) | |
1208 | { | |
1209 | struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); | |
1210 | ||
1211 | if (hws) { | |
1212 | hws->ctx = ctx; | |
1213 | hws->regs = &hwseq_reg; | |
1214 | hws->shifts = &hwseq_shift; | |
1215 | hws->masks = &hwseq_mask; | |
1216 | } | |
1217 | return hws; | |
1218 | } | |
1219 | static const struct resource_create_funcs res_create_funcs = { | |
1220 | .read_dce_straps = read_dce_straps, | |
1221 | .create_audio = dcn301_create_audio, | |
1222 | .create_stream_encoder = dcn301_stream_encoder_create, | |
1223 | .create_hwseq = dcn301_hwseq_create, | |
1224 | }; | |
1225 | ||
1226 | static const struct resource_create_funcs res_create_maximus_funcs = { | |
1227 | .read_dce_straps = NULL, | |
1228 | .create_audio = NULL, | |
1229 | .create_stream_encoder = NULL, | |
1230 | .create_hwseq = dcn301_hwseq_create, | |
1231 | }; | |
1232 | ||
3a83e4e6 RL |
1233 | static void dcn301_destruct(struct dcn301_resource_pool *pool) |
1234 | { | |
1235 | unsigned int i; | |
1236 | ||
1237 | for (i = 0; i < pool->base.stream_enc_count; i++) { | |
1238 | if (pool->base.stream_enc[i] != NULL) { | |
1239 | if (pool->base.stream_enc[i]->vpg != NULL) { | |
1240 | kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); | |
1241 | pool->base.stream_enc[i]->vpg = NULL; | |
1242 | } | |
1243 | if (pool->base.stream_enc[i]->afmt != NULL) { | |
1244 | kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); | |
1245 | pool->base.stream_enc[i]->afmt = NULL; | |
1246 | } | |
1247 | kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); | |
1248 | pool->base.stream_enc[i] = NULL; | |
1249 | } | |
1250 | } | |
1251 | ||
1252 | for (i = 0; i < pool->base.res_cap->num_dsc; i++) { | |
1253 | if (pool->base.dscs[i] != NULL) | |
1254 | dcn20_dsc_destroy(&pool->base.dscs[i]); | |
1255 | } | |
1256 | ||
1257 | if (pool->base.mpc != NULL) { | |
1258 | kfree(TO_DCN20_MPC(pool->base.mpc)); | |
1259 | pool->base.mpc = NULL; | |
1260 | } | |
1261 | if (pool->base.hubbub != NULL) { | |
1262 | kfree(pool->base.hubbub); | |
1263 | pool->base.hubbub = NULL; | |
1264 | } | |
1265 | for (i = 0; i < pool->base.pipe_count; i++) { | |
1266 | if (pool->base.dpps[i] != NULL) | |
1267 | dcn301_dpp_destroy(&pool->base.dpps[i]); | |
1268 | ||
1269 | if (pool->base.ipps[i] != NULL) | |
1270 | pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); | |
1271 | ||
1272 | if (pool->base.hubps[i] != NULL) { | |
1273 | kfree(TO_DCN20_HUBP(pool->base.hubps[i])); | |
1274 | pool->base.hubps[i] = NULL; | |
1275 | } | |
1276 | ||
1277 | if (pool->base.irqs != NULL) { | |
1278 | dal_irq_service_destroy(&pool->base.irqs); | |
1279 | } | |
1280 | } | |
1281 | ||
1282 | for (i = 0; i < pool->base.res_cap->num_ddc; i++) { | |
1283 | if (pool->base.engines[i] != NULL) | |
1284 | dce110_engine_destroy(&pool->base.engines[i]); | |
1285 | if (pool->base.hw_i2cs[i] != NULL) { | |
1286 | kfree(pool->base.hw_i2cs[i]); | |
1287 | pool->base.hw_i2cs[i] = NULL; | |
1288 | } | |
1289 | if (pool->base.sw_i2cs[i] != NULL) { | |
1290 | kfree(pool->base.sw_i2cs[i]); | |
1291 | pool->base.sw_i2cs[i] = NULL; | |
1292 | } | |
1293 | } | |
1294 | ||
1295 | for (i = 0; i < pool->base.res_cap->num_opp; i++) { | |
1296 | if (pool->base.opps[i] != NULL) | |
1297 | pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); | |
1298 | } | |
1299 | ||
1300 | for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { | |
1301 | if (pool->base.timing_generators[i] != NULL) { | |
1302 | kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); | |
1303 | pool->base.timing_generators[i] = NULL; | |
1304 | } | |
1305 | } | |
1306 | ||
1307 | for (i = 0; i < pool->base.res_cap->num_dwb; i++) { | |
1308 | if (pool->base.dwbc[i] != NULL) { | |
1309 | kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); | |
1310 | pool->base.dwbc[i] = NULL; | |
1311 | } | |
1312 | if (pool->base.mcif_wb[i] != NULL) { | |
1313 | kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); | |
1314 | pool->base.mcif_wb[i] = NULL; | |
1315 | } | |
1316 | } | |
1317 | ||
1318 | for (i = 0; i < pool->base.audio_count; i++) { | |
1319 | if (pool->base.audios[i]) | |
1320 | dce_aud_destroy(&pool->base.audios[i]); | |
1321 | } | |
1322 | ||
1323 | for (i = 0; i < pool->base.clk_src_count; i++) { | |
1324 | if (pool->base.clock_sources[i] != NULL) { | |
1325 | dcn20_clock_source_destroy(&pool->base.clock_sources[i]); | |
1326 | pool->base.clock_sources[i] = NULL; | |
1327 | } | |
1328 | } | |
1329 | ||
1330 | for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { | |
1331 | if (pool->base.mpc_lut[i] != NULL) { | |
1332 | dc_3dlut_func_release(pool->base.mpc_lut[i]); | |
1333 | pool->base.mpc_lut[i] = NULL; | |
1334 | } | |
1335 | if (pool->base.mpc_shaper[i] != NULL) { | |
1336 | dc_transfer_func_release(pool->base.mpc_shaper[i]); | |
1337 | pool->base.mpc_shaper[i] = NULL; | |
1338 | } | |
1339 | } | |
1340 | ||
1341 | if (pool->base.dp_clock_source != NULL) { | |
1342 | dcn20_clock_source_destroy(&pool->base.dp_clock_source); | |
1343 | pool->base.dp_clock_source = NULL; | |
1344 | } | |
1345 | ||
1346 | for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { | |
1347 | if (pool->base.multiple_abms[i] != NULL) | |
1348 | dce_abm_destroy(&pool->base.multiple_abms[i]); | |
1349 | } | |
1350 | ||
1351 | if (pool->base.dccg != NULL) | |
1352 | dcn_dccg_destroy(&pool->base.dccg); | |
3a83e4e6 RL |
1353 | } |
1354 | ||
1355 | struct hubp *dcn301_hubp_create( | |
1356 | struct dc_context *ctx, | |
1357 | uint32_t inst) | |
1358 | { | |
1359 | struct dcn20_hubp *hubp2 = | |
1360 | kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); | |
1361 | ||
1362 | if (!hubp2) | |
1363 | return NULL; | |
1364 | ||
1365 | if (hubp3_construct(hubp2, ctx, inst, | |
1366 | &hubp_regs[inst], &hubp_shift, &hubp_mask)) | |
1367 | return &hubp2->base; | |
1368 | ||
1369 | BREAK_TO_DEBUGGER(); | |
1370 | kfree(hubp2); | |
1371 | return NULL; | |
1372 | } | |
1373 | ||
1374 | bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) | |
1375 | { | |
1376 | int i; | |
1377 | uint32_t pipe_count = pool->res_cap->num_dwb; | |
1378 | ||
1379 | for (i = 0; i < pipe_count; i++) { | |
1380 | struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), | |
1381 | GFP_KERNEL); | |
1382 | ||
1383 | if (!dwbc30) { | |
1384 | dm_error("DC: failed to create dwbc30!\n"); | |
1385 | return false; | |
1386 | } | |
1387 | ||
1388 | dcn30_dwbc_construct(dwbc30, ctx, | |
1389 | &dwbc30_regs[i], | |
1390 | &dwbc30_shift, | |
1391 | &dwbc30_mask, | |
1392 | i); | |
1393 | ||
1394 | pool->dwbc[i] = &dwbc30->base; | |
1395 | } | |
1396 | return true; | |
1397 | } | |
1398 | ||
1399 | bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) | |
1400 | { | |
1401 | int i; | |
1402 | uint32_t pipe_count = pool->res_cap->num_dwb; | |
1403 | ||
1404 | for (i = 0; i < pipe_count; i++) { | |
1405 | struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), | |
1406 | GFP_KERNEL); | |
1407 | ||
1408 | if (!mcif_wb30) { | |
1409 | dm_error("DC: failed to create mcif_wb30!\n"); | |
1410 | return false; | |
1411 | } | |
1412 | ||
1413 | dcn30_mmhubbub_construct(mcif_wb30, ctx, | |
1414 | &mcif_wb30_regs[i], | |
1415 | &mcif_wb30_shift, | |
1416 | &mcif_wb30_mask, | |
1417 | i); | |
1418 | ||
1419 | pool->mcif_wb[i] = &mcif_wb30->base; | |
1420 | } | |
1421 | return true; | |
1422 | } | |
1423 | ||
1424 | static struct display_stream_compressor *dcn301_dsc_create( | |
1425 | struct dc_context *ctx, uint32_t inst) | |
1426 | { | |
1427 | struct dcn20_dsc *dsc = | |
1428 | kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); | |
1429 | ||
1430 | if (!dsc) { | |
1431 | BREAK_TO_DEBUGGER(); | |
1432 | return NULL; | |
1433 | } | |
1434 | ||
1435 | dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); | |
1436 | return &dsc->base; | |
1437 | } | |
1438 | ||
1439 | ||
1440 | static void dcn301_destroy_resource_pool(struct resource_pool **pool) | |
1441 | { | |
1442 | struct dcn301_resource_pool *dcn301_pool = TO_DCN301_RES_POOL(*pool); | |
1443 | ||
1444 | dcn301_destruct(dcn301_pool); | |
1445 | kfree(dcn301_pool); | |
1446 | *pool = NULL; | |
1447 | } | |
1448 | ||
1449 | static struct clock_source *dcn301_clock_source_create( | |
1450 | struct dc_context *ctx, | |
1451 | struct dc_bios *bios, | |
1452 | enum clock_source_id id, | |
1453 | const struct dce110_clk_src_regs *regs, | |
1454 | bool dp_clk_src) | |
1455 | { | |
1456 | struct dce110_clk_src *clk_src = | |
1457 | kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); | |
1458 | ||
1459 | if (!clk_src) | |
1460 | return NULL; | |
1461 | ||
1462 | if (dcn301_clk_src_construct(clk_src, ctx, bios, id, | |
1463 | regs, &cs_shift, &cs_mask)) { | |
1464 | clk_src->base.dp_clk_src = dp_clk_src; | |
1465 | return &clk_src->base; | |
1466 | } | |
1467 | ||
1468 | BREAK_TO_DEBUGGER(); | |
1469 | return NULL; | |
1470 | } | |
1471 | ||
1472 | static struct dc_cap_funcs cap_funcs = { | |
1473 | .get_dcc_compression_cap = dcn20_get_dcc_compression_cap | |
1474 | }; | |
1475 | ||
1476 | #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16))) | |
1477 | #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x)) | |
1478 | ||
1479 | static bool is_soc_bounding_box_valid(struct dc *dc) | |
1480 | { | |
1481 | uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; | |
1482 | ||
1483 | if (ASICREV_IS_VANGOGH(hw_internal_rev)) | |
1484 | return true; | |
1485 | ||
1486 | return false; | |
1487 | } | |
1488 | ||
1489 | static bool init_soc_bounding_box(struct dc *dc, | |
1490 | struct dcn301_resource_pool *pool) | |
1491 | { | |
1492 | const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box; | |
1493 | struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_01_soc; | |
1494 | struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_01_ip; | |
1495 | ||
1496 | DC_LOGGER_INIT(dc->ctx->logger); | |
1497 | ||
1498 | if (!bb && !is_soc_bounding_box_valid(dc)) { | |
1499 | DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); | |
1500 | return false; | |
1501 | } | |
1502 | ||
1503 | if (bb && !is_soc_bounding_box_valid(dc)) { | |
1504 | int i; | |
1505 | ||
1506 | dcn3_01_soc.sr_exit_time_us = | |
1507 | fixed16_to_double_to_cpu(bb->sr_exit_time_us); | |
1508 | dcn3_01_soc.sr_enter_plus_exit_time_us = | |
1509 | fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us); | |
1510 | dcn3_01_soc.urgent_latency_us = | |
1511 | fixed16_to_double_to_cpu(bb->urgent_latency_us); | |
1512 | dcn3_01_soc.urgent_latency_pixel_data_only_us = | |
1513 | fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us); | |
1514 | dcn3_01_soc.urgent_latency_pixel_mixed_with_vm_data_us = | |
1515 | fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us); | |
1516 | dcn3_01_soc.urgent_latency_vm_data_only_us = | |
1517 | fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us); | |
1518 | dcn3_01_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes = | |
1519 | le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes); | |
1520 | dcn3_01_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = | |
1521 | le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes); | |
1522 | dcn3_01_soc.urgent_out_of_order_return_per_channel_vm_only_bytes = | |
1523 | le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes); | |
1524 | dcn3_01_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = | |
1525 | fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only); | |
1526 | dcn3_01_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = | |
1527 | fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm); | |
1528 | dcn3_01_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only = | |
1529 | fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only); | |
1530 | dcn3_01_soc.max_avg_sdp_bw_use_normal_percent = | |
1531 | fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent); | |
1532 | dcn3_01_soc.max_avg_dram_bw_use_normal_percent = | |
1533 | fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent); | |
1534 | dcn3_01_soc.writeback_latency_us = | |
1535 | fixed16_to_double_to_cpu(bb->writeback_latency_us); | |
1536 | dcn3_01_soc.ideal_dram_bw_after_urgent_percent = | |
1537 | fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent); | |
1538 | dcn3_01_soc.max_request_size_bytes = | |
1539 | le32_to_cpu(bb->max_request_size_bytes); | |
1540 | dcn3_01_soc.dram_channel_width_bytes = | |
1541 | le32_to_cpu(bb->dram_channel_width_bytes); | |
1542 | dcn3_01_soc.fabric_datapath_to_dcn_data_return_bytes = | |
1543 | le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes); | |
1544 | dcn3_01_soc.dcn_downspread_percent = | |
1545 | fixed16_to_double_to_cpu(bb->dcn_downspread_percent); | |
1546 | dcn3_01_soc.downspread_percent = | |
1547 | fixed16_to_double_to_cpu(bb->downspread_percent); | |
1548 | dcn3_01_soc.dram_page_open_time_ns = | |
1549 | fixed16_to_double_to_cpu(bb->dram_page_open_time_ns); | |
1550 | dcn3_01_soc.dram_rw_turnaround_time_ns = | |
1551 | fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns); | |
1552 | dcn3_01_soc.dram_return_buffer_per_channel_bytes = | |
1553 | le32_to_cpu(bb->dram_return_buffer_per_channel_bytes); | |
1554 | dcn3_01_soc.round_trip_ping_latency_dcfclk_cycles = | |
1555 | le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles); | |
1556 | dcn3_01_soc.urgent_out_of_order_return_per_channel_bytes = | |
1557 | le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes); | |
1558 | dcn3_01_soc.channel_interleave_bytes = | |
1559 | le32_to_cpu(bb->channel_interleave_bytes); | |
1560 | dcn3_01_soc.num_banks = | |
1561 | le32_to_cpu(bb->num_banks); | |
1562 | dcn3_01_soc.num_chans = | |
1563 | le32_to_cpu(bb->num_chans); | |
1564 | dcn3_01_soc.gpuvm_min_page_size_bytes = | |
1565 | le32_to_cpu(bb->vmm_page_size_bytes); | |
1566 | dcn3_01_soc.dram_clock_change_latency_us = | |
1567 | fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us); | |
1568 | dcn3_01_soc.writeback_dram_clock_change_latency_us = | |
1569 | fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us); | |
1570 | dcn3_01_soc.return_bus_width_bytes = | |
1571 | le32_to_cpu(bb->return_bus_width_bytes); | |
1572 | dcn3_01_soc.dispclk_dppclk_vco_speed_mhz = | |
1573 | le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz); | |
1574 | dcn3_01_soc.xfc_bus_transport_time_us = | |
1575 | le32_to_cpu(bb->xfc_bus_transport_time_us); | |
1576 | dcn3_01_soc.xfc_xbuf_latency_tolerance_us = | |
1577 | le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us); | |
1578 | dcn3_01_soc.use_urgent_burst_bw = | |
1579 | le32_to_cpu(bb->use_urgent_burst_bw); | |
1580 | dcn3_01_soc.num_states = | |
1581 | le32_to_cpu(bb->num_states); | |
1582 | ||
1583 | for (i = 0; i < dcn3_01_soc.num_states; i++) { | |
1584 | dcn3_01_soc.clock_limits[i].state = | |
1585 | le32_to_cpu(bb->clock_limits[i].state); | |
1586 | dcn3_01_soc.clock_limits[i].dcfclk_mhz = | |
1587 | fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz); | |
1588 | dcn3_01_soc.clock_limits[i].fabricclk_mhz = | |
1589 | fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz); | |
1590 | dcn3_01_soc.clock_limits[i].dispclk_mhz = | |
1591 | fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz); | |
1592 | dcn3_01_soc.clock_limits[i].dppclk_mhz = | |
1593 | fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz); | |
1594 | dcn3_01_soc.clock_limits[i].phyclk_mhz = | |
1595 | fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz); | |
1596 | dcn3_01_soc.clock_limits[i].socclk_mhz = | |
1597 | fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz); | |
1598 | dcn3_01_soc.clock_limits[i].dscclk_mhz = | |
1599 | fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz); | |
1600 | dcn3_01_soc.clock_limits[i].dram_speed_mts = | |
1601 | fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts); | |
1602 | } | |
1603 | } | |
1604 | ||
9a3e698c YS |
1605 | loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; |
1606 | loaded_ip->max_num_dpp = pool->base.pipe_count; | |
1607 | dcn20_patch_bounding_box(dc, loaded_bb); | |
1608 | ||
1609 | if (!bb && dc->ctx->dc_bios->funcs->get_soc_bb_info) { | |
1610 | struct bp_soc_bb_info bb_info = {0}; | |
3a83e4e6 | 1611 | |
9a3e698c YS |
1612 | if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { |
1613 | if (bb_info.dram_clock_change_latency_100ns > 0) | |
1614 | dcn3_01_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10; | |
3a83e4e6 | 1615 | |
9a3e698c YS |
1616 | if (bb_info.dram_sr_enter_exit_latency_100ns > 0) |
1617 | dcn3_01_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10; | |
3a83e4e6 | 1618 | |
9a3e698c YS |
1619 | if (bb_info.dram_sr_exit_latency_100ns > 0) |
1620 | dcn3_01_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10; | |
3a83e4e6 | 1621 | } |
3a83e4e6 RL |
1622 | } |
1623 | ||
3a83e4e6 RL |
1624 | return true; |
1625 | } | |
1626 | ||
1627 | static void set_wm_ranges( | |
1628 | struct pp_smu_funcs *pp_smu, | |
1629 | struct _vcs_dpi_soc_bounding_box_st *loaded_bb) | |
1630 | { | |
1631 | struct pp_smu_wm_range_sets ranges = {0}; | |
1632 | int i; | |
1633 | ||
1634 | ranges.num_reader_wm_sets = 0; | |
1635 | ||
1636 | if (loaded_bb->num_states == 1) { | |
1637 | ranges.reader_wm_sets[0].wm_inst = 0; | |
1638 | ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; | |
1639 | ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; | |
1640 | ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; | |
1641 | ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; | |
1642 | ||
1643 | ranges.num_reader_wm_sets = 1; | |
1644 | } else if (loaded_bb->num_states > 1) { | |
1645 | for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { | |
1646 | ranges.reader_wm_sets[i].wm_inst = i; | |
1647 | ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; | |
1648 | ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; | |
1649 | ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0; | |
1650 | ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; | |
1651 | ||
1652 | ranges.num_reader_wm_sets = i + 1; | |
1653 | } | |
1654 | ||
1655 | ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; | |
1656 | ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; | |
1657 | } | |
1658 | ||
1659 | ranges.num_writer_wm_sets = 1; | |
1660 | ||
1661 | ranges.writer_wm_sets[0].wm_inst = 0; | |
1662 | ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; | |
1663 | ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; | |
1664 | ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; | |
1665 | ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; | |
1666 | ||
1667 | /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ | |
1668 | pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges); | |
1669 | } | |
1670 | ||
9a3e698c | 1671 | static void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) |
3a83e4e6 | 1672 | { |
9a3e698c YS |
1673 | struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc->res_pool); |
1674 | struct clk_limit_table *clk_table = &bw_params->clk_table; | |
1675 | struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; | |
1676 | unsigned int i, closest_clk_lvl; | |
1677 | int j; | |
1678 | ||
1679 | // Default clock levels are used for diags, which may lead to overclocking. | |
1680 | if (!IS_DIAG_DC(dc->ctx->dce_environment)) { | |
1681 | dcn3_01_ip.max_num_otg = pool->base.res_cap->num_timing_generator; | |
1682 | dcn3_01_ip.max_num_dpp = pool->base.pipe_count; | |
1683 | dcn3_01_soc.num_chans = bw_params->num_channels; | |
1684 | ||
1685 | ASSERT(clk_table->num_entries); | |
1686 | for (i = 0; i < clk_table->num_entries; i++) { | |
1687 | /* loop backwards*/ | |
1688 | for (closest_clk_lvl = 0, j = dcn3_01_soc.num_states - 1; j >= 0; j--) { | |
1689 | if ((unsigned int) dcn3_01_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { | |
1690 | closest_clk_lvl = j; | |
1691 | break; | |
1692 | } | |
1693 | } | |
3a83e4e6 | 1694 | |
9a3e698c YS |
1695 | clock_limits[i].state = i; |
1696 | clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; | |
1697 | clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; | |
1698 | clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; | |
1699 | clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; | |
1700 | ||
1701 | clock_limits[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz; | |
1702 | clock_limits[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz; | |
1703 | clock_limits[i].dram_bw_per_chan_gbps = dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; | |
1704 | clock_limits[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz; | |
1705 | clock_limits[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; | |
1706 | clock_limits[i].phyclk_d18_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; | |
1707 | clock_limits[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz; | |
1708 | } | |
1709 | for (i = 0; i < clk_table->num_entries; i++) | |
1710 | dcn3_01_soc.clock_limits[i] = clock_limits[i]; | |
1711 | if (clk_table->num_entries) { | |
1712 | dcn3_01_soc.num_states = clk_table->num_entries; | |
1713 | /* duplicate last level */ | |
1714 | dcn3_01_soc.clock_limits[dcn3_01_soc.num_states] = dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1]; | |
1715 | dcn3_01_soc.clock_limits[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states; | |
1716 | } | |
3a83e4e6 | 1717 | } |
3a83e4e6 | 1718 | |
3a83e4e6 RL |
1719 | dcn3_01_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; |
1720 | dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; | |
9a3e698c YS |
1721 | |
1722 | dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30); | |
3a83e4e6 RL |
1723 | } |
1724 | ||
1725 | static struct resource_funcs dcn301_res_pool_funcs = { | |
1726 | .destroy = dcn301_destroy_resource_pool, | |
1727 | .link_enc_create = dcn301_link_encoder_create, | |
1728 | .panel_cntl_create = dcn301_panel_cntl_create, | |
1729 | .validate_bandwidth = dcn30_validate_bandwidth, | |
1730 | .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, | |
1731 | .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, | |
1732 | .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, | |
1733 | .add_stream_to_ctx = dcn30_add_stream_to_ctx, | |
0eb31a82 | 1734 | .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, |
3a83e4e6 RL |
1735 | .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, |
1736 | .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, | |
1737 | .set_mcif_arb_params = dcn30_set_mcif_arb_params, | |
1738 | .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, | |
1739 | .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, | |
1740 | .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, | |
1741 | .update_bw_bounding_box = dcn301_update_bw_bounding_box | |
1742 | }; | |
1743 | ||
1744 | static bool dcn301_resource_construct( | |
1745 | uint8_t num_virtual_links, | |
1746 | struct dc *dc, | |
1747 | struct dcn301_resource_pool *pool) | |
1748 | { | |
1749 | int i, j; | |
1750 | struct dc_context *ctx = dc->ctx; | |
1751 | struct irq_service_init_data init_data; | |
1752 | uint32_t pipe_fuses = read_pipe_fuses(ctx); | |
1753 | uint32_t num_pipes = 0; | |
1754 | ||
1755 | DC_LOGGER_INIT(dc->ctx->logger); | |
1756 | ||
1757 | ctx->dc_bios->regs = &bios_regs; | |
1758 | ||
1759 | pool->base.res_cap = &res_cap_dcn301; | |
1760 | ||
1761 | pool->base.funcs = &dcn301_res_pool_funcs; | |
1762 | ||
1763 | /************************************************* | |
1764 | * Resource + asic cap harcoding * | |
1765 | *************************************************/ | |
1766 | pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; | |
1767 | pool->base.pipe_count = pool->base.res_cap->num_timing_generator; | |
1768 | pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; | |
1769 | dc->caps.max_downscale_ratio = 600; | |
1770 | dc->caps.i2c_speed_in_khz = 100; | |
e97978e8 | 1771 | dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a enabled by default*/ |
3a83e4e6 | 1772 | dc->caps.max_cursor_size = 256; |
06722b37 | 1773 | dc->caps.min_horizontal_blanking_period = 80; |
3a83e4e6 RL |
1774 | dc->caps.dmdata_alloc_size = 2048; |
1775 | dc->caps.max_slave_planes = 1; | |
1776 | dc->caps.is_apu = true; | |
1777 | dc->caps.post_blend_color_processing = true; | |
1778 | dc->caps.force_dp_tps4_for_cp2520 = true; | |
1779 | dc->caps.extended_aux_timeout_support = true; | |
1780 | #ifdef CONFIG_DRM_AMD_DC_DMUB | |
1781 | dc->caps.dmcub_support = true; | |
1782 | #endif | |
1783 | ||
1784 | /* Color pipeline capabilities */ | |
1785 | dc->caps.color.dpp.dcn_arch = 1; | |
1786 | dc->caps.color.dpp.input_lut_shared = 0; | |
1787 | dc->caps.color.dpp.icsc = 1; | |
1788 | dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr | |
1789 | dc->caps.color.dpp.dgam_rom_caps.srgb = 1; | |
1790 | dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; | |
1791 | dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; | |
1792 | dc->caps.color.dpp.dgam_rom_caps.pq = 1; | |
1793 | dc->caps.color.dpp.dgam_rom_caps.hlg = 1; | |
1794 | dc->caps.color.dpp.post_csc = 1; | |
1795 | dc->caps.color.dpp.gamma_corr = 1; | |
c6160900 | 1796 | dc->caps.color.dpp.dgam_rom_for_yuv = 0; |
3a83e4e6 RL |
1797 | |
1798 | dc->caps.color.dpp.hw_3d_lut = 1; | |
1799 | dc->caps.color.dpp.ogam_ram = 1; | |
1800 | // no OGAM ROM on DCN301 | |
1801 | dc->caps.color.dpp.ogam_rom_caps.srgb = 0; | |
1802 | dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; | |
1803 | dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; | |
1804 | dc->caps.color.dpp.ogam_rom_caps.pq = 0; | |
1805 | dc->caps.color.dpp.ogam_rom_caps.hlg = 0; | |
1806 | dc->caps.color.dpp.ocsc = 0; | |
1807 | ||
1808 | dc->caps.color.mpc.gamut_remap = 1; | |
1809 | dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 | |
1810 | dc->caps.color.mpc.ogam_ram = 1; | |
1811 | dc->caps.color.mpc.ogam_rom_caps.srgb = 0; | |
1812 | dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; | |
1813 | dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; | |
1814 | dc->caps.color.mpc.ogam_rom_caps.pq = 0; | |
1815 | dc->caps.color.mpc.ogam_rom_caps.hlg = 0; | |
1816 | dc->caps.color.mpc.ocsc = 1; | |
1817 | ||
1818 | if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) | |
1819 | dc->debug = debug_defaults_drv; | |
1820 | else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { | |
1821 | dc->debug = debug_defaults_diags; | |
1822 | } else | |
1823 | dc->debug = debug_defaults_diags; | |
1824 | // Init the vm_helper | |
1825 | if (dc->vm_helper) | |
1826 | vm_helper_init(dc->vm_helper, 16); | |
1827 | ||
1828 | /************************************************* | |
1829 | * Create resources * | |
1830 | *************************************************/ | |
1831 | ||
1832 | /* Clock Sources for Pixel Clock*/ | |
1833 | pool->base.clock_sources[DCN301_CLK_SRC_PLL0] = | |
1834 | dcn301_clock_source_create(ctx, ctx->dc_bios, | |
1835 | CLOCK_SOURCE_COMBO_PHY_PLL0, | |
1836 | &clk_src_regs[0], false); | |
1837 | pool->base.clock_sources[DCN301_CLK_SRC_PLL1] = | |
1838 | dcn301_clock_source_create(ctx, ctx->dc_bios, | |
1839 | CLOCK_SOURCE_COMBO_PHY_PLL1, | |
1840 | &clk_src_regs[1], false); | |
1841 | pool->base.clock_sources[DCN301_CLK_SRC_PLL2] = | |
1842 | dcn301_clock_source_create(ctx, ctx->dc_bios, | |
1843 | CLOCK_SOURCE_COMBO_PHY_PLL2, | |
1844 | &clk_src_regs[2], false); | |
1845 | pool->base.clock_sources[DCN301_CLK_SRC_PLL3] = | |
1846 | dcn301_clock_source_create(ctx, ctx->dc_bios, | |
1847 | CLOCK_SOURCE_COMBO_PHY_PLL3, | |
1848 | &clk_src_regs[3], false); | |
1849 | ||
1850 | pool->base.clk_src_count = DCN301_CLK_SRC_TOTAL; | |
1851 | ||
1852 | /* todo: not reuse phy_pll registers */ | |
1853 | pool->base.dp_clock_source = | |
1854 | dcn301_clock_source_create(ctx, ctx->dc_bios, | |
1855 | CLOCK_SOURCE_ID_DP_DTO, | |
1856 | &clk_src_regs[0], true); | |
1857 | ||
1858 | for (i = 0; i < pool->base.clk_src_count; i++) { | |
1859 | if (pool->base.clock_sources[i] == NULL) { | |
1860 | dm_error("DC: failed to create clock sources!\n"); | |
1861 | BREAK_TO_DEBUGGER(); | |
1862 | goto create_fail; | |
1863 | } | |
1864 | } | |
1865 | ||
1866 | /* DCCG */ | |
1867 | pool->base.dccg = dccg301_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); | |
1868 | if (pool->base.dccg == NULL) { | |
1869 | dm_error("DC: failed to create dccg!\n"); | |
1870 | BREAK_TO_DEBUGGER(); | |
1871 | goto create_fail; | |
1872 | } | |
1873 | ||
3a83e4e6 | 1874 | init_soc_bounding_box(dc, pool); |
9a3e698c | 1875 | |
3a83e4e6 RL |
1876 | if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges) |
1877 | set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc); | |
1878 | ||
1879 | num_pipes = dcn3_01_ip.max_num_dpp; | |
1880 | ||
1881 | for (i = 0; i < dcn3_01_ip.max_num_dpp; i++) | |
1882 | if (pipe_fuses & 1 << i) | |
1883 | num_pipes--; | |
1884 | dcn3_01_ip.max_num_dpp = num_pipes; | |
1885 | dcn3_01_ip.max_num_otg = num_pipes; | |
1886 | ||
1887 | ||
1888 | dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30); | |
1889 | ||
1890 | /* IRQ */ | |
1891 | init_data.ctx = dc->ctx; | |
1892 | pool->base.irqs = dal_irq_service_dcn30_create(&init_data); | |
1893 | if (!pool->base.irqs) | |
1894 | goto create_fail; | |
1895 | ||
1896 | /* HUBBUB */ | |
1897 | pool->base.hubbub = dcn301_hubbub_create(ctx); | |
1898 | if (pool->base.hubbub == NULL) { | |
1899 | BREAK_TO_DEBUGGER(); | |
1900 | dm_error("DC: failed to create hubbub!\n"); | |
1901 | goto create_fail; | |
1902 | } | |
1903 | ||
1904 | j = 0; | |
1905 | /* HUBPs, DPPs, OPPs and TGs */ | |
1906 | for (i = 0; i < pool->base.pipe_count; i++) { | |
1907 | ||
1908 | /* if pipe is disabled, skip instance of HW pipe, | |
1909 | * i.e, skip ASIC register instance | |
1910 | */ | |
1911 | if ((pipe_fuses & (1 << i)) != 0) { | |
1912 | DC_LOG_DEBUG("%s: fusing pipe %d\n", __func__, i); | |
1913 | continue; | |
1914 | } | |
1915 | ||
1916 | pool->base.hubps[j] = dcn301_hubp_create(ctx, i); | |
1917 | if (pool->base.hubps[j] == NULL) { | |
1918 | BREAK_TO_DEBUGGER(); | |
1919 | dm_error( | |
1920 | "DC: failed to create hubps!\n"); | |
1921 | goto create_fail; | |
1922 | } | |
1923 | ||
1924 | pool->base.dpps[j] = dcn301_dpp_create(ctx, i); | |
1925 | if (pool->base.dpps[j] == NULL) { | |
1926 | BREAK_TO_DEBUGGER(); | |
1927 | dm_error( | |
1928 | "DC: failed to create dpps!\n"); | |
1929 | goto create_fail; | |
1930 | } | |
1931 | ||
1932 | pool->base.opps[j] = dcn301_opp_create(ctx, i); | |
1933 | if (pool->base.opps[j] == NULL) { | |
1934 | BREAK_TO_DEBUGGER(); | |
1935 | dm_error( | |
1936 | "DC: failed to create output pixel processor!\n"); | |
1937 | goto create_fail; | |
1938 | } | |
1939 | ||
1940 | pool->base.timing_generators[j] = dcn301_timing_generator_create(ctx, i); | |
1941 | if (pool->base.timing_generators[j] == NULL) { | |
1942 | BREAK_TO_DEBUGGER(); | |
1943 | dm_error("DC: failed to create tg!\n"); | |
1944 | goto create_fail; | |
1945 | } | |
1946 | j++; | |
1947 | } | |
1948 | pool->base.timing_generator_count = j; | |
1949 | pool->base.pipe_count = j; | |
1950 | pool->base.mpcc_count = j; | |
1951 | ||
1952 | /* ABM (or ABMs for NV2x) */ | |
1953 | /* TODO: */ | |
1954 | for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { | |
f9dbefa8 | 1955 | pool->base.multiple_abms[i] = dmub_abm_create(ctx, |
3a83e4e6 RL |
1956 | &abm_regs[i], |
1957 | &abm_shift, | |
1958 | &abm_mask); | |
1959 | if (pool->base.multiple_abms[i] == NULL) { | |
1960 | dm_error("DC: failed to create abm for pipe %d!\n", i); | |
1961 | BREAK_TO_DEBUGGER(); | |
1962 | goto create_fail; | |
1963 | } | |
1964 | } | |
1965 | ||
1966 | /* MPC and DSC */ | |
1967 | pool->base.mpc = dcn301_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); | |
1968 | if (pool->base.mpc == NULL) { | |
1969 | BREAK_TO_DEBUGGER(); | |
1970 | dm_error("DC: failed to create mpc!\n"); | |
1971 | goto create_fail; | |
1972 | } | |
1973 | ||
1974 | for (i = 0; i < pool->base.res_cap->num_dsc; i++) { | |
1975 | pool->base.dscs[i] = dcn301_dsc_create(ctx, i); | |
1976 | if (pool->base.dscs[i] == NULL) { | |
1977 | BREAK_TO_DEBUGGER(); | |
1978 | dm_error("DC: failed to create display stream compressor %d!\n", i); | |
1979 | goto create_fail; | |
1980 | } | |
1981 | } | |
1982 | ||
1983 | /* DWB and MMHUBBUB */ | |
1984 | if (!dcn301_dwbc_create(ctx, &pool->base)) { | |
1985 | BREAK_TO_DEBUGGER(); | |
1986 | dm_error("DC: failed to create dwbc!\n"); | |
1987 | goto create_fail; | |
1988 | } | |
1989 | ||
1990 | if (!dcn301_mmhubbub_create(ctx, &pool->base)) { | |
1991 | BREAK_TO_DEBUGGER(); | |
1992 | dm_error("DC: failed to create mcif_wb!\n"); | |
1993 | goto create_fail; | |
1994 | } | |
1995 | ||
1996 | /* AUX and I2C */ | |
1997 | for (i = 0; i < pool->base.res_cap->num_ddc; i++) { | |
1998 | pool->base.engines[i] = dcn301_aux_engine_create(ctx, i); | |
1999 | if (pool->base.engines[i] == NULL) { | |
2000 | BREAK_TO_DEBUGGER(); | |
2001 | dm_error( | |
2002 | "DC:failed to create aux engine!!\n"); | |
2003 | goto create_fail; | |
2004 | } | |
2005 | pool->base.hw_i2cs[i] = dcn301_i2c_hw_create(ctx, i); | |
2006 | if (pool->base.hw_i2cs[i] == NULL) { | |
2007 | BREAK_TO_DEBUGGER(); | |
2008 | dm_error( | |
2009 | "DC:failed to create hw i2c!!\n"); | |
2010 | goto create_fail; | |
2011 | } | |
2012 | pool->base.sw_i2cs[i] = NULL; | |
2013 | } | |
2014 | ||
2015 | /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ | |
2016 | if (!resource_construct(num_virtual_links, dc, &pool->base, | |
2017 | (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? | |
2018 | &res_create_funcs : &res_create_maximus_funcs))) | |
2019 | goto create_fail; | |
2020 | ||
2021 | /* HW Sequencer and Plane caps */ | |
2022 | dcn301_hw_sequencer_construct(dc); | |
2023 | ||
2024 | dc->caps.max_planes = pool->base.pipe_count; | |
2025 | ||
2026 | for (i = 0; i < dc->caps.max_planes; ++i) | |
2027 | dc->caps.planes[i] = plane_cap; | |
2028 | ||
2029 | dc->cap_funcs = cap_funcs; | |
2030 | ||
2031 | return true; | |
2032 | ||
2033 | create_fail: | |
2034 | ||
2035 | dcn301_destruct(pool); | |
2036 | ||
2037 | return false; | |
2038 | } | |
2039 | ||
2040 | struct resource_pool *dcn301_create_resource_pool( | |
2041 | const struct dc_init_data *init_data, | |
2042 | struct dc *dc) | |
2043 | { | |
2044 | struct dcn301_resource_pool *pool = | |
2045 | kzalloc(sizeof(struct dcn301_resource_pool), GFP_KERNEL); | |
2046 | ||
2047 | if (!pool) | |
2048 | return NULL; | |
2049 | ||
2050 | if (dcn301_resource_construct(init_data->num_virtual_links, dc, pool)) | |
2051 | return &pool->base; | |
2052 | ||
2053 | BREAK_TO_DEBUGGER(); | |
2054 | kfree(pool); | |
2055 | return NULL; | |
2056 | } |