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drm/amd/display: Increase linebuffer pixel depth to 36bpp.
[linux-block.git] / drivers / gpu / drm / amd / display / dc / dcn30 / dcn30_dpp.c
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03f54d7d
BL		 1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services.h"
27#include "core_types.h"
28#include "reg_helper.h"
29#include "dcn30_dpp.h"
30#include "basics/conversion.h"
31#include "dcn30_cm_common.h"
32
33#define REG(reg)\
34 dpp->tf_regs->reg
35
36#define CTX \
37 dpp->base.ctx
38
39#undef FN
40#define FN(reg_name, field_name) \
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
42
43
44void dpp30_read_state(struct dpp *dpp_base,
45 struct dcn_dpp_state *s)
46{
47 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
48
49 REG_GET(DPP_CONTROL,
50 DPP_CLOCK_ENABLE, &s->is_enabled);
51
52 // TODO: Implement for DCN3
53}
54/*program post scaler scs block in dpp CM*/
55void dpp3_program_post_csc(
56 struct dpp *dpp_base,
57 enum dc_color_space color_space,
58 enum dcn10_input_csc_select input_select,
59 const struct out_csc_color_matrix *tbl_entry)
60{
61 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
62 int i;
63 int arr_size = sizeof(dpp_input_csc_matrix)/sizeof(struct dpp_input_csc_matrix);
64 const uint16_t *regval = NULL;
65 uint32_t cur_select = 0;
66 enum dcn10_input_csc_select select;
67 struct color_matrices_reg gam_regs;
68
69 if (input_select == INPUT_CSC_SELECT_BYPASS) {
70 REG_SET(CM_POST_CSC_CONTROL, 0, CM_POST_CSC_MODE, 0);
71 return;
72 }
73
74 if (tbl_entry == NULL) {
75 for (i = 0; i < arr_size; i++)
76 if (dpp_input_csc_matrix[i].color_space == color_space) {
77 regval = dpp_input_csc_matrix[i].regval;
78 break;
79 }
80
81 if (regval == NULL) {
82 BREAK_TO_DEBUGGER();
83 return;
84 }
85 } else {
86 regval = tbl_entry->regval;
87 }
88
89 /* determine which CSC matrix (icsc or coma) we are using
90 * currently. select the alternate set to double buffer
91 * the CSC update so CSC is updated on frame boundary
92 */
93 REG_GET(CM_POST_CSC_CONTROL,
94 CM_POST_CSC_MODE_CURRENT, &cur_select);
95
96 if (cur_select != INPUT_CSC_SELECT_ICSC)
97 select = INPUT_CSC_SELECT_ICSC;
98 else
99 select = INPUT_CSC_SELECT_COMA;
100
101 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11;
102 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_POST_CSC_C11;
103 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12;
104 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12;
105
106 if (select == INPUT_CSC_SELECT_ICSC) {
107
108 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_C11_C12);
109 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_C33_C34);
110
111 } else {
112
113 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_B_C11_C12);
114 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_B_C33_C34);
115
116 }
117
118 cm_helper_program_color_matrices(
119 dpp->base.ctx,
120 regval,
121 &gam_regs);
122
123 REG_SET(CM_POST_CSC_CONTROL, 0,
124 CM_POST_CSC_MODE, select);
125}
126
127
128/*CNVC degam unit has read only LUTs*/
129void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined tr)
130{
131 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
132 int pre_degam_en = 1;
133 int degamma_lut_selection = 0;
134
135 switch (tr) {
136 case TRANSFER_FUNCTION_LINEAR:
137 case TRANSFER_FUNCTION_UNITY:
138 pre_degam_en = 0; //bypass
139 break;
140 case TRANSFER_FUNCTION_SRGB:
141 degamma_lut_selection = 0;
142 break;
143 case TRANSFER_FUNCTION_BT709:
144 degamma_lut_selection = 4;
145 break;
146 case TRANSFER_FUNCTION_PQ:
147 degamma_lut_selection = 5;
148 break;
149 case TRANSFER_FUNCTION_HLG:
150 degamma_lut_selection = 6;
151 break;
152 case TRANSFER_FUNCTION_GAMMA22:
153 degamma_lut_selection = 1;
154 break;
155 case TRANSFER_FUNCTION_GAMMA24:
156 degamma_lut_selection = 2;
157 break;
158 case TRANSFER_FUNCTION_GAMMA26:
159 degamma_lut_selection = 3;
160 break;
161 default:
162 pre_degam_en = 0;
163 break;
164 }
165
166 REG_SET_2(PRE_DEGAM, 0,
167 PRE_DEGAM_MODE, pre_degam_en,
168 PRE_DEGAM_SELECT, degamma_lut_selection);
169}
170
171static void dpp3_cnv_setup (
172 struct dpp *dpp_base,
173 enum surface_pixel_format format,
174 enum expansion_mode mode,
175 struct dc_csc_transform input_csc_color_matrix,
176 enum dc_color_space input_color_space,
177 struct cnv_alpha_2bit_lut *alpha_2bit_lut)
178{
179 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
180 uint32_t pixel_format = 0;
181 uint32_t alpha_en = 1;
182 enum dc_color_space color_space = COLOR_SPACE_SRGB;
183 enum dcn10_input_csc_select select = INPUT_CSC_SELECT_BYPASS;
184 bool force_disable_cursor = false;
185 uint32_t is_2bit = 0;
186 uint32_t alpha_plane_enable = 0;
187 uint32_t dealpha_en = 0, dealpha_ablnd_en = 0;
188 uint32_t realpha_en = 0, realpha_ablnd_en = 0;
189 uint32_t program_prealpha_dealpha = 0;
190 struct out_csc_color_matrix tbl_entry;
191 int i;
192
193 REG_SET_2(FORMAT_CONTROL, 0,
194 CNVC_BYPASS, 0,
195 FORMAT_EXPANSION_MODE, mode);
196
197 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);
198 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);
199 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);
200 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);
201
202 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0);
203 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1);
204 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2);
205
206 switch (format) {
207 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
208 pixel_format = 1;
209 break;
210 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
211 pixel_format = 3;
212 alpha_en = 0;
213 break;
214 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
215 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
216 pixel_format = 8;
217 break;
218 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
219 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
220 pixel_format = 10;
221 is_2bit = 1;
222 break;
223 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
224 force_disable_cursor = false;
225 pixel_format = 65;
226 color_space = COLOR_SPACE_YCBCR709;
227 select = INPUT_CSC_SELECT_ICSC;
228 break;
229 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
230 force_disable_cursor = true;
231 pixel_format = 64;
232 color_space = COLOR_SPACE_YCBCR709;
233 select = INPUT_CSC_SELECT_ICSC;
234 break;
235 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
236 force_disable_cursor = true;
237 pixel_format = 67;
238 color_space = COLOR_SPACE_YCBCR709;
239 select = INPUT_CSC_SELECT_ICSC;
240 break;
241 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
242 force_disable_cursor = true;
243 pixel_format = 66;
244 color_space = COLOR_SPACE_YCBCR709;
245 select = INPUT_CSC_SELECT_ICSC;
246 break;
247 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
050cd3d6
MK		 248 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
249 pixel_format = 26; /* ARGB16161616_UNORM */
03f54d7d
BL		 250 break;
251 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
252 pixel_format = 24;
253 break;
254 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
255 pixel_format = 25;
256 break;
257 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
258 pixel_format = 12;
259 color_space = COLOR_SPACE_YCBCR709;
260 select = INPUT_CSC_SELECT_ICSC;
261 break;
262 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
263 pixel_format = 112;
264 break;
265 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
266 pixel_format = 113;
267 break;
268 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
269 pixel_format = 114;
270 color_space = COLOR_SPACE_YCBCR709;
271 select = INPUT_CSC_SELECT_ICSC;
272 is_2bit = 1;
273 break;
274 case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102:
275 pixel_format = 115;
276 color_space = COLOR_SPACE_YCBCR709;
277 select = INPUT_CSC_SELECT_ICSC;
278 is_2bit = 1;
279 break;
280 case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
281 pixel_format = 116;
282 alpha_plane_enable = 0;
283 break;
284 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
285 pixel_format = 116;
286 alpha_plane_enable = 1;
287 break;
288 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
289 pixel_format = 118;
290 break;
291 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
292 pixel_format = 119;
293 break;
294 default:
295 break;
296 }
297
298 if (is_2bit == 1 && alpha_2bit_lut != NULL) {
299 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
300 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
301 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2);
302 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3);
303 }
304
305 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0,
306 CNVC_SURFACE_PIXEL_FORMAT, pixel_format,
307 CNVC_ALPHA_PLANE_ENABLE, alpha_plane_enable);
308 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
309
310 if (program_prealpha_dealpha) {
311 dealpha_en = 1;
312 realpha_en = 1;
313 }
314 REG_SET_2(PRE_DEALPHA, 0,
315 PRE_DEALPHA_EN, dealpha_en,
316 PRE_DEALPHA_ABLND_EN, dealpha_ablnd_en);
317 REG_SET_2(PRE_REALPHA, 0,
318 PRE_REALPHA_EN, realpha_en,
319 PRE_REALPHA_ABLND_EN, realpha_ablnd_en);
320
321 /* If input adjustment exists, program the ICSC with those values. */
322 if (input_csc_color_matrix.enable_adjustment == true) {
323 for (i = 0; i < 12; i++)
324 tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
325
326 tbl_entry.color_space = input_color_space;
327
328 if (color_space >= COLOR_SPACE_YCBCR601)
329 select = INPUT_CSC_SELECT_ICSC;
330 else
331 select = INPUT_CSC_SELECT_BYPASS;
332
333 dpp3_program_post_csc(dpp_base, color_space, select,
334 &tbl_entry);
335 } else {
336 dpp3_program_post_csc(dpp_base, color_space, select, NULL);
337 }
338
339 if (force_disable_cursor) {
340 REG_UPDATE(CURSOR_CONTROL,
341 CURSOR_ENABLE, 0);
342 REG_UPDATE(CURSOR0_CONTROL,
343 CUR0_ENABLE, 0);
344 }
345}
346
347#define IDENTITY_RATIO(ratio) (dc_fixpt_u3d19(ratio) == (1 << 19))
348
349void dpp3_set_cursor_attributes(
350 struct dpp *dpp_base,
351 struct dc_cursor_attributes *cursor_attributes)
352{
353 enum dc_cursor_color_format color_format = cursor_attributes->color_format;
354 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
355 int cur_rom_en = 0;
356
357 if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
358 color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA)
359 cur_rom_en = 1;
360
361 REG_UPDATE_3(CURSOR0_CONTROL,
362 CUR0_MODE, color_format,
363 CUR0_EXPANSION_MODE, 0,
364 CUR0_ROM_EN, cur_rom_en);
365
366 if (color_format == CURSOR_MODE_MONO) {
367 /* todo: clarify what to program these to */
368 REG_UPDATE(CURSOR0_COLOR0,
369 CUR0_COLOR0, 0x00000000);
370 REG_UPDATE(CURSOR0_COLOR1,
371 CUR0_COLOR1, 0xFFFFFFFF);
372 }
373}
374
375
376bool dpp3_get_optimal_number_of_taps(
377 struct dpp *dpp,
378 struct scaler_data *scl_data,
379 const struct scaling_taps *in_taps)
380{
381 int num_part_y, num_part_c;
382 int max_taps_y, max_taps_c;
383 int min_taps_y, min_taps_c;
384 enum lb_memory_config lb_config;
385
386 /* Some ASICs does not support FP16 scaling, so we reject modes require this*/
387 if (scl_data->viewport.width != scl_data->h_active &&
388 scl_data->viewport.height != scl_data->v_active &&
389 dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&
390 scl_data->format == PIXEL_FORMAT_FP16)
391 return false;
392
393 if (scl_data->viewport.width > scl_data->h_active &&
394 dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
395 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
396 return false;
397
398 /*
399 * Set default taps if none are provided
400 * From programming guide: taps = min{ ceil(2*H_RATIO,1), 8} for downscaling
401 * taps = 4 for upscaling
402 */
403 if (in_taps->h_taps == 0) {
404 if (dc_fixpt_ceil(scl_data->ratios.horz) > 1)
405 scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8);
406 else
407 scl_data->taps.h_taps = 4;
408 } else
409 scl_data->taps.h_taps = in_taps->h_taps;
410 if (in_taps->v_taps == 0) {
411 if (dc_fixpt_ceil(scl_data->ratios.vert) > 1)
412 scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8);
413 else
414 scl_data->taps.v_taps = 4;
415 } else
416 scl_data->taps.v_taps = in_taps->v_taps;
417 if (in_taps->v_taps_c == 0) {
418 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 1)
419 scl_data->taps.v_taps_c = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert_c, 2)), 8);
420 else
421 scl_data->taps.v_taps_c = 4;
422 } else
423 scl_data->taps.v_taps_c = in_taps->v_taps_c;
424 if (in_taps->h_taps_c == 0) {
425 if (dc_fixpt_ceil(scl_data->ratios.horz_c) > 1)
426 scl_data->taps.h_taps_c = min(2 * dc_fixpt_ceil(scl_data->ratios.horz_c), 8);
427 else
428 scl_data->taps.h_taps_c = 4;
429 } else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1)
430 /* Only 1 and even h_taps_c are supported by hw */
431 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
432 else
433 scl_data->taps.h_taps_c = in_taps->h_taps_c;
434
435 /*Ensure we can support the requested number of vtaps*/
436 min_taps_y = dc_fixpt_ceil(scl_data->ratios.vert);
437 min_taps_c = dc_fixpt_ceil(scl_data->ratios.vert_c);
438
439 /* Use LB_MEMORY_CONFIG_3 for 4:2:0 */
440 if ((scl_data->format == PIXEL_FORMAT_420BPP8) || (scl_data->format == PIXEL_FORMAT_420BPP10))
441 lb_config = LB_MEMORY_CONFIG_3;
442 else
443 lb_config = LB_MEMORY_CONFIG_0;
444
445 dpp->caps->dscl_calc_lb_num_partitions(
446 scl_data, lb_config, &num_part_y, &num_part_c);
447
448 /* MAX_V_TAPS = MIN (NUM_LINES - MAX(CEILING(V_RATIO,1)-2, 0), 8) */
449 if (dc_fixpt_ceil(scl_data->ratios.vert) > 2)
450 max_taps_y = num_part_y - (dc_fixpt_ceil(scl_data->ratios.vert) - 2);
451 else
452 max_taps_y = num_part_y;
453
454 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 2)
455 max_taps_c = num_part_c - (dc_fixpt_ceil(scl_data->ratios.vert_c) - 2);
456 else
457 max_taps_c = num_part_c;
458
459 if (max_taps_y < min_taps_y)
460 return false;
461 else if (max_taps_c < min_taps_c)
462 return false;
463
464 if (scl_data->taps.v_taps > max_taps_y)
465 scl_data->taps.v_taps = max_taps_y;
466
467 if (scl_data->taps.v_taps_c > max_taps_c)
468 scl_data->taps.v_taps_c = max_taps_c;
469
470 if (!dpp->ctx->dc->debug.always_scale) {
471 if (IDENTITY_RATIO(scl_data->ratios.horz))
472 scl_data->taps.h_taps = 1;
473 if (IDENTITY_RATIO(scl_data->ratios.vert))
474 scl_data->taps.v_taps = 1;
475 if (IDENTITY_RATIO(scl_data->ratios.horz_c))
476 scl_data->taps.h_taps_c = 1;
477 if (IDENTITY_RATIO(scl_data->ratios.vert_c))
478 scl_data->taps.v_taps_c = 1;
479 }
480
481 return true;
482}
483
484void dpp3_cnv_set_bias_scale(
485 struct dpp *dpp_base,
486 struct dc_bias_and_scale *bias_and_scale)
487{
488 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
489
490 REG_UPDATE(FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, bias_and_scale->bias_red);
491 REG_UPDATE(FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, bias_and_scale->bias_green);
492 REG_UPDATE(FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, bias_and_scale->bias_blue);
493 REG_UPDATE(FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, bias_and_scale->scale_red);
494 REG_UPDATE(FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, bias_and_scale->scale_green);
495 REG_UPDATE(FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, bias_and_scale->scale_blue);
496}
497
498static void dpp3_power_on_blnd_lut(
499 struct dpp *dpp_base,
500 bool power_on)
501{
502 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
503
49d067dc
JL		 504 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
505 REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, power_on ? 0 : 3);
506 if (power_on)
507 REG_WAIT(CM_MEM_PWR_STATUS, BLNDGAM_MEM_PWR_STATE, 0, 1, 5);
508 } else {
509 REG_SET(CM_MEM_PWR_CTRL, 0,
510 BLNDGAM_MEM_PWR_FORCE, power_on == true ? 0 : 1);
511 }
03f54d7d
BL		 512}
513
00b0ac67
JL		 514static void dpp3_power_on_hdr3dlut(
515 struct dpp *dpp_base,
516 bool power_on)
517{
518 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
519
520 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
521 REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, power_on ? 0 : 3);
522 if (power_on)
523 REG_WAIT(CM_MEM_PWR_STATUS2, HDR3DLUT_MEM_PWR_STATE, 0, 1, 5);
524 }
525}
526
527static void dpp3_power_on_shaper(
528 struct dpp *dpp_base,
529 bool power_on)
530{
531 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
532
533 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
534 REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, power_on ? 0 : 3);
535 if (power_on)
536 REG_WAIT(CM_MEM_PWR_STATUS2, SHAPER_MEM_PWR_STATE, 0, 1, 5);
537 }
538}
539
03f54d7d
BL		 540static void dpp3_configure_blnd_lut(
541 struct dpp *dpp_base,
542 bool is_ram_a)
543{
544 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
545
546 REG_UPDATE_2(CM_BLNDGAM_LUT_CONTROL,
547 CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 7,
548 CM_BLNDGAM_LUT_HOST_SEL, is_ram_a == true ? 0 : 1);
549
550 REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0);
551}
552
553static void dpp3_program_blnd_pwl(
554 struct dpp *dpp_base,
555 const struct pwl_result_data *rgb,
556 uint32_t num)
557{
558 uint32_t i;
559 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
560 uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;
561 uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;
562 uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;
563
564 if (is_rgb_equal(rgb, num)) {
565 for (i = 0 ; i < num; i++)
566 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);
567 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);
568 } else {
569 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 4);
570 for (i = 0 ; i < num; i++)
571 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);
572 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);
573
574 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 2);
575 for (i = 0 ; i < num; i++)
576 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].green_reg);
577 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_green);
578
579 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 1);
580 for (i = 0 ; i < num; i++)
581 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].blue_reg);
582 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_blue);
583 }
584}
585
586static void dcn3_dpp_cm_get_reg_field(
587 struct dcn3_dpp *dpp,
588 struct dcn3_xfer_func_reg *reg)
589{
590 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
591 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
592 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
593 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
594 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
595 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
596 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
597 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
598
599 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
600 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
601 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
602 reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
603 reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
604 reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
605 reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;
606 reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;
607 reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
608 reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
609 reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
610 reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
611}
612
613/*program blnd lut RAM A*/
614static void dpp3_program_blnd_luta_settings(
615 struct dpp *dpp_base,
616 const struct pwl_params *params)
617{
618 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
619 struct dcn3_xfer_func_reg gam_regs;
620
621 dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);
622
623 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B);
624 gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G);
625 gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R);
626 gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B);
627 gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G);
628 gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R);
629 gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMA_END_CNTL1_B);
630 gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMA_END_CNTL2_B);
631 gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMA_END_CNTL1_G);
632 gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMA_END_CNTL2_G);
633 gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMA_END_CNTL1_R);
634 gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMA_END_CNTL2_R);
635 gam_regs.region_start = REG(CM_BLNDGAM_RAMA_REGION_0_1);
636 gam_regs.region_end = REG(CM_BLNDGAM_RAMA_REGION_32_33);
637
638 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);
639}
640
641/*program blnd lut RAM B*/
642static void dpp3_program_blnd_lutb_settings(
643 struct dpp *dpp_base,
644 const struct pwl_params *params)
645{
646 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
647 struct dcn3_xfer_func_reg gam_regs;
648
649 dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);
650
651 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMB_START_CNTL_B);
652 gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMB_START_CNTL_G);
653 gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMB_START_CNTL_R);
654 gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B);
655 gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G);
656 gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R);
657 gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMB_END_CNTL1_B);
658 gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMB_END_CNTL2_B);
659 gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMB_END_CNTL1_G);
660 gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMB_END_CNTL2_G);
661 gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMB_END_CNTL1_R);
662 gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMB_END_CNTL2_R);
663 gam_regs.region_start = REG(CM_BLNDGAM_RAMB_REGION_0_1);
664 gam_regs.region_end = REG(CM_BLNDGAM_RAMB_REGION_32_33);
665
666 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);
667}
668
669static enum dc_lut_mode dpp3_get_blndgam_current(struct dpp *dpp_base)
670{
671 enum dc_lut_mode mode;
672 uint32_t mode_current = 0;
673 uint32_t in_use = 0;
674
675 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
676
677 REG_GET(CM_BLNDGAM_CONTROL,
678 CM_BLNDGAM_MODE_CURRENT, &mode_current);
679 REG_GET(CM_BLNDGAM_CONTROL,
680 CM_BLNDGAM_SELECT_CURRENT, &in_use);
681
682 switch (mode_current) {
683 case 0:
684 case 1:
685 mode = LUT_BYPASS;
686 break;
687
688 case 2:
689 if (in_use == 0)
690 mode = LUT_RAM_A;
691 else
692 mode = LUT_RAM_B;
693 break;
694 default:
695 mode = LUT_BYPASS;
696 break;
697 }
698 return mode;
699}
700
701bool dpp3_program_blnd_lut(
702 struct dpp *dpp_base, const struct pwl_params *params)
703{
704 enum dc_lut_mode current_mode;
705 enum dc_lut_mode next_mode;
706 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
707
708 if (params == NULL) {
709 REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_MODE, 0);
49d067dc
JL		 710 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
711 dpp3_power_on_blnd_lut(dpp_base, false);
03f54d7d
BL		 712 return false;
713 }
714
715 current_mode = dpp3_get_blndgam_current(dpp_base);
716 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_B)
717 next_mode = LUT_RAM_A;
718 else
719 next_mode = LUT_RAM_B;
720
721 dpp3_power_on_blnd_lut(dpp_base, true);
74ef3bac 722 dpp3_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A);
03f54d7d
BL		 723
724 if (next_mode == LUT_RAM_A)
725 dpp3_program_blnd_luta_settings(dpp_base, params);
726 else
727 dpp3_program_blnd_lutb_settings(dpp_base, params);
728
729 dpp3_program_blnd_pwl(
730 dpp_base, params->rgb_resulted, params->hw_points_num);
731
732 REG_UPDATE_2(CM_BLNDGAM_CONTROL,
733 CM_BLNDGAM_MODE, 2,
734 CM_BLNDGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1);
735
736 return true;
737}
738
739
740static void dpp3_program_shaper_lut(
741 struct dpp *dpp_base,
742 const struct pwl_result_data *rgb,
743 uint32_t num)
744{
745 uint32_t i, red, green, blue;
746 uint32_t red_delta, green_delta, blue_delta;
747 uint32_t red_value, green_value, blue_value;
748
749 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
750
751 for (i = 0 ; i < num; i++) {
752
753 red = rgb[i].red_reg;
754 green = rgb[i].green_reg;
755 blue = rgb[i].blue_reg;
756
757 red_delta = rgb[i].delta_red_reg;
758 green_delta = rgb[i].delta_green_reg;
759 blue_delta = rgb[i].delta_blue_reg;
760
761 red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff);
762 green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff);
763 blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff);
764
765 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, red_value);
766 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, green_value);
767 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, blue_value);
768 }
769
770}
771
772static enum dc_lut_mode dpp3_get_shaper_current(struct dpp *dpp_base)
773{
774 enum dc_lut_mode mode;
775 uint32_t state_mode;
776 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
777
778 REG_GET(CM_SHAPER_CONTROL,
779 CM_SHAPER_MODE_CURRENT, &state_mode);
780
781 switch (state_mode) {
782 case 0:
783 mode = LUT_BYPASS;
784 break;
785 case 1:
786 mode = LUT_RAM_A;
787 break;
788 case 2:
789 mode = LUT_RAM_B;
790 break;
791 default:
792 mode = LUT_BYPASS;
793 break;
794 }
795 return mode;
796}
797
798static void dpp3_configure_shaper_lut(
799 struct dpp *dpp_base,
800 bool is_ram_a)
801{
802 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
803
804 REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,
805 CM_SHAPER_LUT_WRITE_EN_MASK, 7);
806 REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,
807 CM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1);
808 REG_SET(CM_SHAPER_LUT_INDEX, 0, CM_SHAPER_LUT_INDEX, 0);
809}
810
811/*program shaper RAM A*/
812
813static void dpp3_program_shaper_luta_settings(
814 struct dpp *dpp_base,
815 const struct pwl_params *params)
816{
817 const struct gamma_curve *curve;
818 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
819
820 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0,
821 CM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
822 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
823 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0,
824 CM_SHAPER_RAMA_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x,
825 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, 0);
826 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0,
827 CM_SHAPER_RAMA_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x,
828 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, 0);
829
830 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0,
831 CM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
832 CM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
833
834 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0,
835 CM_SHAPER_RAMA_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x,
836 CM_SHAPER_RAMA_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y);
837
838 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0,
839 CM_SHAPER_RAMA_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x,
840 CM_SHAPER_RAMA_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y);
841
842 curve = params->arr_curve_points;
843 REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0,
844 CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
845 CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
846 CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
847 CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
848
849 curve += 2;
850 REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0,
851 CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset,
852 CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
853 CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset,
854 CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
855
856 curve += 2;
857 REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0,
858 CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset,
859 CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
860 CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset,
861 CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
862
863 curve += 2;
864 REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0,
865 CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset,
866 CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
867 CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset,
868 CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
869
870 curve += 2;
871 REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0,
872 CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset,
873 CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
874 CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset,
875 CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
876
877 curve += 2;
878 REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0,
879 CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset,
880 CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
881 CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset,
882 CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
883
884 curve += 2;
885 REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0,
886 CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset,
887 CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
888 CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset,
889 CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
890
891 curve += 2;
892 REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0,
893 CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset,
894 CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
895 CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset,
896 CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
897
898 curve += 2;
899 REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0,
900 CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset,
901 CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
902 CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset,
903 CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
904
905 curve += 2;
906 REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0,
907 CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset,
908 CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
909 CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset,
910 CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
911
912 curve += 2;
913 REG_SET_4(CM_SHAPER_RAMA_REGION_20_21, 0,
914 CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset,
915 CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
916 CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset,
917 CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
918
919 curve += 2;
920 REG_SET_4(CM_SHAPER_RAMA_REGION_22_23, 0,
921 CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset,
922 CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
923 CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset,
924 CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
925
926 curve += 2;
927 REG_SET_4(CM_SHAPER_RAMA_REGION_24_25, 0,
928 CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset,
929 CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
930 CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset,
931 CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
932
933 curve += 2;
934 REG_SET_4(CM_SHAPER_RAMA_REGION_26_27, 0,
935 CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset,
936 CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
937 CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset,
938 CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
939
940 curve += 2;
941 REG_SET_4(CM_SHAPER_RAMA_REGION_28_29, 0,
942 CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset,
943 CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
944 CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset,
945 CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
946
947 curve += 2;
948 REG_SET_4(CM_SHAPER_RAMA_REGION_30_31, 0,
949 CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset,
950 CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
951 CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset,
952 CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
953
954 curve += 2;
955 REG_SET_4(CM_SHAPER_RAMA_REGION_32_33, 0,
956 CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset,
957 CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
958 CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset,
959 CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
960}
961
962/*program shaper RAM B*/
963static void dpp3_program_shaper_lutb_settings(
964 struct dpp *dpp_base,
965 const struct pwl_params *params)
966{
967 const struct gamma_curve *curve;
968 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
969
970 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0,
971 CM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
972 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0);
973 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0,
974 CM_SHAPER_RAMB_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x,
975 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, 0);
976 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0,
977 CM_SHAPER_RAMB_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x,
978 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, 0);
979
980 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0,
981 CM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
982 CM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
983
984 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_G, 0,
985 CM_SHAPER_RAMB_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x,
986 CM_SHAPER_RAMB_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y);
987
988 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_R, 0,
989 CM_SHAPER_RAMB_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x,
990 CM_SHAPER_RAMB_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y);
991
992 curve = params->arr_curve_points;
993 REG_SET_4(CM_SHAPER_RAMB_REGION_0_1, 0,
994 CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,
995 CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
996 CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,
997 CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
998
999 curve += 2;
1000 REG_SET_4(CM_SHAPER_RAMB_REGION_2_3, 0,
1001 CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset,
1002 CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
1003 CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset,
1004 CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
1005
1006 curve += 2;
1007 REG_SET_4(CM_SHAPER_RAMB_REGION_4_5, 0,
1008 CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset,
1009 CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
1010 CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset,
1011 CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
1012
1013 curve += 2;
1014 REG_SET_4(CM_SHAPER_RAMB_REGION_6_7, 0,
1015 CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset,
1016 CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
1017 CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset,
1018 CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
1019
1020 curve += 2;
1021 REG_SET_4(CM_SHAPER_RAMB_REGION_8_9, 0,
1022 CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset,
1023 CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
1024 CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset,
1025 CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
1026
1027 curve += 2;
1028 REG_SET_4(CM_SHAPER_RAMB_REGION_10_11, 0,
1029 CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset,
1030 CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
1031 CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset,
1032 CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
1033
1034 curve += 2;
1035 REG_SET_4(CM_SHAPER_RAMB_REGION_12_13, 0,
1036 CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset,
1037 CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
1038 CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset,
1039 CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
1040
1041 curve += 2;
1042 REG_SET_4(CM_SHAPER_RAMB_REGION_14_15, 0,
1043 CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset,
1044 CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
1045 CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset,
1046 CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
1047
1048 curve += 2;
1049 REG_SET_4(CM_SHAPER_RAMB_REGION_16_17, 0,
1050 CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset,
1051 CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
1052 CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset,
1053 CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
1054
1055 curve += 2;
1056 REG_SET_4(CM_SHAPER_RAMB_REGION_18_19, 0,
1057 CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset,
1058 CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
1059 CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset,
1060 CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
1061
1062 curve += 2;
1063 REG_SET_4(CM_SHAPER_RAMB_REGION_20_21, 0,
1064 CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset,
1065 CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
1066 CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset,
1067 CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
1068
1069 curve += 2;
1070 REG_SET_4(CM_SHAPER_RAMB_REGION_22_23, 0,
1071 CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset,
1072 CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
1073 CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset,
1074 CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
1075
1076 curve += 2;
1077 REG_SET_4(CM_SHAPER_RAMB_REGION_24_25, 0,
1078 CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset,
1079 CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
1080 CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset,
1081 CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
1082
1083 curve += 2;
1084 REG_SET_4(CM_SHAPER_RAMB_REGION_26_27, 0,
1085 CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset,
1086 CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
1087 CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset,
1088 CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
1089
1090 curve += 2;
1091 REG_SET_4(CM_SHAPER_RAMB_REGION_28_29, 0,
1092 CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset,
1093 CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
1094 CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset,
1095 CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
1096
1097 curve += 2;
1098 REG_SET_4(CM_SHAPER_RAMB_REGION_30_31, 0,
1099 CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset,
1100 CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
1101 CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset,
1102 CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
1103
1104 curve += 2;
1105 REG_SET_4(CM_SHAPER_RAMB_REGION_32_33, 0,
1106 CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset,
1107 CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
1108 CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset,
1109 CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
1110
1111}
1112
1113
1114bool dpp3_program_shaper(
1115 struct dpp *dpp_base,
1116 const struct pwl_params *params)
1117{
1118 enum dc_lut_mode current_mode;
1119 enum dc_lut_mode next_mode;
1120
1121 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1122
1123 if (params == NULL) {
1124 REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, 0);
00b0ac67
JL		 1125 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1126 dpp3_power_on_shaper(dpp_base, false);
03f54d7d
BL		 1127 return false;
1128 }
00b0ac67
JL		 1129
1130 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1131 dpp3_power_on_shaper(dpp_base, true);
1132
03f54d7d
BL		 1133 current_mode = dpp3_get_shaper_current(dpp_base);
1134
1135 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
1136 next_mode = LUT_RAM_B;
1137 else
1138 next_mode = LUT_RAM_A;
1139
74ef3bac 1140 dpp3_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A);
03f54d7d
BL		 1141
1142 if (next_mode == LUT_RAM_A)
1143 dpp3_program_shaper_luta_settings(dpp_base, params);
1144 else
1145 dpp3_program_shaper_lutb_settings(dpp_base, params);
1146
1147 dpp3_program_shaper_lut(
1148 dpp_base, params->rgb_resulted, params->hw_points_num);
1149
1150 REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);
1151
1152 return true;
1153
1154}
1155
1156static enum dc_lut_mode get3dlut_config(
1157 struct dpp *dpp_base,
1158 bool *is_17x17x17,
1159 bool *is_12bits_color_channel)
1160{
1161 uint32_t i_mode, i_enable_10bits, lut_size;
1162 enum dc_lut_mode mode;
1163 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1164
1165 REG_GET(CM_3DLUT_READ_WRITE_CONTROL,
1166 CM_3DLUT_30BIT_EN, &i_enable_10bits);
1167 REG_GET(CM_3DLUT_MODE,
1168 CM_3DLUT_MODE_CURRENT, &i_mode);
1169
1170 switch (i_mode) {
1171 case 0:
1172 mode = LUT_BYPASS;
1173 break;
1174 case 1:
1175 mode = LUT_RAM_A;
1176 break;
1177 case 2:
1178 mode = LUT_RAM_B;
1179 break;
1180 default:
1181 mode = LUT_BYPASS;
1182 break;
1183 }
1184 if (i_enable_10bits > 0)
1185 *is_12bits_color_channel = false;
1186 else
1187 *is_12bits_color_channel = true;
1188
1189 REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &lut_size);
1190
1191 if (lut_size == 0)
1192 *is_17x17x17 = true;
1193 else
1194 *is_17x17x17 = false;
1195
1196 return mode;
1197}
1198/*
1199 * select ramA or ramB, or bypass
1200 * select color channel size 10 or 12 bits
1201 * select 3dlut size 17x17x17 or 9x9x9
1202 */
1203static void dpp3_set_3dlut_mode(
1204 struct dpp *dpp_base,
1205 enum dc_lut_mode mode,
1206 bool is_color_channel_12bits,
1207 bool is_lut_size17x17x17)
1208{
1209 uint32_t lut_mode;
1210 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1211
1212 if (mode == LUT_BYPASS)
1213 lut_mode = 0;
1214 else if (mode == LUT_RAM_A)
1215 lut_mode = 1;
1216 else
1217 lut_mode = 2;
1218
1219 REG_UPDATE_2(CM_3DLUT_MODE,
1220 CM_3DLUT_MODE, lut_mode,
1221 CM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1);
1222}
1223
1224static void dpp3_select_3dlut_ram(
1225 struct dpp *dpp_base,
1226 enum dc_lut_mode mode,
1227 bool is_color_channel_12bits)
1228{
1229 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1230
1231 REG_UPDATE_2(CM_3DLUT_READ_WRITE_CONTROL,
1232 CM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,
1233 CM_3DLUT_30BIT_EN,
1234 is_color_channel_12bits == true ? 0:1);
1235}
1236
1237
1238
1239static void dpp3_set3dlut_ram12(
1240 struct dpp *dpp_base,
1241 const struct dc_rgb *lut,
1242 uint32_t entries)
1243{
1244 uint32_t i, red, green, blue, red1, green1, blue1;
1245 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1246
1247 for (i = 0 ; i < entries; i += 2) {
1248 red = lut[i].red<<4;
1249 green = lut[i].green<<4;
1250 blue = lut[i].blue<<4;
1251 red1 = lut[i+1].red<<4;
1252 green1 = lut[i+1].green<<4;
1253 blue1 = lut[i+1].blue<<4;
1254
1255 REG_SET_2(CM_3DLUT_DATA, 0,
1256 CM_3DLUT_DATA0, red,
1257 CM_3DLUT_DATA1, red1);
1258
1259 REG_SET_2(CM_3DLUT_DATA, 0,
1260 CM_3DLUT_DATA0, green,
1261 CM_3DLUT_DATA1, green1);
1262
1263 REG_SET_2(CM_3DLUT_DATA, 0,
1264 CM_3DLUT_DATA0, blue,
1265 CM_3DLUT_DATA1, blue1);
1266
1267 }
1268}
1269
1270/*
1271 * load selected lut with 10 bits color channels
1272 */
1273static void dpp3_set3dlut_ram10(
1274 struct dpp *dpp_base,
1275 const struct dc_rgb *lut,
1276 uint32_t entries)
1277{
1278 uint32_t i, red, green, blue, value;
1279 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1280
1281 for (i = 0; i < entries; i++) {
1282 red = lut[i].red;
1283 green = lut[i].green;
1284 blue = lut[i].blue;
1285
1286 value = (red<<20) | (green<<10) | blue;
1287
1288 REG_SET(CM_3DLUT_DATA_30BIT, 0, CM_3DLUT_DATA_30BIT, value);
1289 }
1290
1291}
1292
1293
1294static void dpp3_select_3dlut_ram_mask(
1295 struct dpp *dpp_base,
1296 uint32_t ram_selection_mask)
1297{
1298 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1299
1300 REG_UPDATE(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK,
1301 ram_selection_mask);
1302 REG_SET(CM_3DLUT_INDEX, 0, CM_3DLUT_INDEX, 0);
1303}
1304
1305bool dpp3_program_3dlut(
1306 struct dpp *dpp_base,
1307 struct tetrahedral_params *params)
1308{
1309 enum dc_lut_mode mode;
1310 bool is_17x17x17;
1311 bool is_12bits_color_channel;
1312 struct dc_rgb *lut0;
1313 struct dc_rgb *lut1;
1314 struct dc_rgb *lut2;
1315 struct dc_rgb *lut3;
1316 int lut_size0;
1317 int lut_size;
1318
1319 if (params == NULL) {
1320 dpp3_set_3dlut_mode(dpp_base, LUT_BYPASS, false, false);
00b0ac67
JL		 1321 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1322 dpp3_power_on_hdr3dlut(dpp_base, false);
03f54d7d
BL		 1323 return false;
1324 }
00b0ac67
JL		 1325
1326 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1327 dpp3_power_on_hdr3dlut(dpp_base, true);
1328
03f54d7d
BL		 1329 mode = get3dlut_config(dpp_base, &is_17x17x17, &is_12bits_color_channel);
1330
1331 if (mode == LUT_BYPASS || mode == LUT_RAM_B)
1332 mode = LUT_RAM_A;
1333 else
1334 mode = LUT_RAM_B;
1335
1336 is_17x17x17 = !params->use_tetrahedral_9;
1337 is_12bits_color_channel = params->use_12bits;
1338 if (is_17x17x17) {
1339 lut0 = params->tetrahedral_17.lut0;
1340 lut1 = params->tetrahedral_17.lut1;
1341 lut2 = params->tetrahedral_17.lut2;
1342 lut3 = params->tetrahedral_17.lut3;
1343 lut_size0 = sizeof(params->tetrahedral_17.lut0)/
1344 sizeof(params->tetrahedral_17.lut0[0]);
1345 lut_size = sizeof(params->tetrahedral_17.lut1)/
1346 sizeof(params->tetrahedral_17.lut1[0]);
1347 } else {
1348 lut0 = params->tetrahedral_9.lut0;
1349 lut1 = params->tetrahedral_9.lut1;
1350 lut2 = params->tetrahedral_9.lut2;
1351 lut3 = params->tetrahedral_9.lut3;
1352 lut_size0 = sizeof(params->tetrahedral_9.lut0)/
1353 sizeof(params->tetrahedral_9.lut0[0]);
1354 lut_size = sizeof(params->tetrahedral_9.lut1)/
1355 sizeof(params->tetrahedral_9.lut1[0]);
1356 }
1357
1358 dpp3_select_3dlut_ram(dpp_base, mode,
1359 is_12bits_color_channel);
1360 dpp3_select_3dlut_ram_mask(dpp_base, 0x1);
1361 if (is_12bits_color_channel)
1362 dpp3_set3dlut_ram12(dpp_base, lut0, lut_size0);
1363 else
1364 dpp3_set3dlut_ram10(dpp_base, lut0, lut_size0);
1365
1366 dpp3_select_3dlut_ram_mask(dpp_base, 0x2);
1367 if (is_12bits_color_channel)
1368 dpp3_set3dlut_ram12(dpp_base, lut1, lut_size);
1369 else
1370 dpp3_set3dlut_ram10(dpp_base, lut1, lut_size);
1371
1372 dpp3_select_3dlut_ram_mask(dpp_base, 0x4);
1373 if (is_12bits_color_channel)
1374 dpp3_set3dlut_ram12(dpp_base, lut2, lut_size);
1375 else
1376 dpp3_set3dlut_ram10(dpp_base, lut2, lut_size);
1377
1378 dpp3_select_3dlut_ram_mask(dpp_base, 0x8);
1379 if (is_12bits_color_channel)
1380 dpp3_set3dlut_ram12(dpp_base, lut3, lut_size);
1381 else
1382 dpp3_set3dlut_ram10(dpp_base, lut3, lut_size);
1383
1384
1385 dpp3_set_3dlut_mode(dpp_base, mode, is_12bits_color_channel,
1386 is_17x17x17);
1387
1388 return true;
1389}
1390static struct dpp_funcs dcn30_dpp_funcs = {
1391 .dpp_program_gamcor_lut = dpp3_program_gamcor_lut,
1392 .dpp_read_state = dpp30_read_state,
1393 .dpp_reset = dpp_reset,
1394 .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
1395 .dpp_get_optimal_number_of_taps = dpp3_get_optimal_number_of_taps,
1396 .dpp_set_gamut_remap = dpp3_cm_set_gamut_remap,
1397 .dpp_set_csc_adjustment = NULL,
1398 .dpp_set_csc_default = NULL,
1399 .dpp_program_regamma_pwl = NULL,
1400 .dpp_set_pre_degam = dpp3_set_pre_degam,
1401 .dpp_program_input_lut = NULL,
1402 .dpp_full_bypass = dpp1_full_bypass,
1403 .dpp_setup = dpp3_cnv_setup,
1404 .dpp_program_degamma_pwl = NULL,
1405 .dpp_program_cm_dealpha = dpp3_program_cm_dealpha,
1406 .dpp_program_cm_bias = dpp3_program_cm_bias,
03f54d7d
BL		 1407 .dpp_program_blnd_lut = dpp3_program_blnd_lut,
1408 .dpp_program_shaper_lut = dpp3_program_shaper,
1409 .dpp_program_3dlut = dpp3_program_3dlut,
03f54d7d
BL		 1410 .dpp_program_bias_and_scale = NULL,
1411 .dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer,
1412 .set_cursor_attributes = dpp3_set_cursor_attributes,
1413 .set_cursor_position = dpp1_set_cursor_position,
1414 .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
1415 .dpp_dppclk_control = dpp1_dppclk_control,
1416 .dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier,
1417};
1418
1419
1420static struct dpp_caps dcn30_dpp_cap = {
1421 .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT,
1422 .dscl_calc_lb_num_partitions = dscl2_calc_lb_num_partitions,
1423};
1424
1425bool dpp3_construct(
1426 struct dcn3_dpp *dpp,
1427 struct dc_context *ctx,
1428 uint32_t inst,
1429 const struct dcn3_dpp_registers *tf_regs,
1430 const struct dcn3_dpp_shift *tf_shift,
1431 const struct dcn3_dpp_mask *tf_mask)
1432{
1433 dpp->base.ctx = ctx;
1434
1435 dpp->base.inst = inst;
1436 dpp->base.funcs = &dcn30_dpp_funcs;
1437 dpp->base.caps = &dcn30_dpp_cap;
1438
1439 dpp->tf_regs = tf_regs;
1440 dpp->tf_shift = tf_shift;
1441 dpp->tf_mask = tf_mask;
1442
1443 dpp->lb_pixel_depth_supported =
1444 LB_PIXEL_DEPTH_18BPP |
1445 LB_PIXEL_DEPTH_24BPP |
a316db72
MK		 1446 LB_PIXEL_DEPTH_30BPP |
1447 LB_PIXEL_DEPTH_36BPP;
03f54d7d
BL		 1448
1449 dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;
1450 dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
1451
1452 return true;
1453}
1454
Linux 6.x block layer and io_uring tree(s)