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drm/amd/display: Add DCN3 DPP
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / dc / dcn30 / dcn30_dpp.c
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03f54d7d
BL		 1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services.h"
27#include "core_types.h"
28#include "reg_helper.h"
29#include "dcn30_dpp.h"
30#include "basics/conversion.h"
31#include "dcn30_cm_common.h"
32
33#define REG(reg)\
34 dpp->tf_regs->reg
35
36#define CTX \
37 dpp->base.ctx
38
39#undef FN
40#define FN(reg_name, field_name) \
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
42
43
44void dpp30_read_state(struct dpp *dpp_base,
45 struct dcn_dpp_state *s)
46{
47 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
48
49 REG_GET(DPP_CONTROL,
50 DPP_CLOCK_ENABLE, &s->is_enabled);
51
52 // TODO: Implement for DCN3
53}
54/*program post scaler scs block in dpp CM*/
55void dpp3_program_post_csc(
56 struct dpp *dpp_base,
57 enum dc_color_space color_space,
58 enum dcn10_input_csc_select input_select,
59 const struct out_csc_color_matrix *tbl_entry)
60{
61 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
62 int i;
63 int arr_size = sizeof(dpp_input_csc_matrix)/sizeof(struct dpp_input_csc_matrix);
64 const uint16_t *regval = NULL;
65 uint32_t cur_select = 0;
66 enum dcn10_input_csc_select select;
67 struct color_matrices_reg gam_regs;
68
69 if (input_select == INPUT_CSC_SELECT_BYPASS) {
70 REG_SET(CM_POST_CSC_CONTROL, 0, CM_POST_CSC_MODE, 0);
71 return;
72 }
73
74 if (tbl_entry == NULL) {
75 for (i = 0; i < arr_size; i++)
76 if (dpp_input_csc_matrix[i].color_space == color_space) {
77 regval = dpp_input_csc_matrix[i].regval;
78 break;
79 }
80
81 if (regval == NULL) {
82 BREAK_TO_DEBUGGER();
83 return;
84 }
85 } else {
86 regval = tbl_entry->regval;
87 }
88
89 /* determine which CSC matrix (icsc or coma) we are using
90 * currently. select the alternate set to double buffer
91 * the CSC update so CSC is updated on frame boundary
92 */
93 REG_GET(CM_POST_CSC_CONTROL,
94 CM_POST_CSC_MODE_CURRENT, &cur_select);
95
96 if (cur_select != INPUT_CSC_SELECT_ICSC)
97 select = INPUT_CSC_SELECT_ICSC;
98 else
99 select = INPUT_CSC_SELECT_COMA;
100
101 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11;
102 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_POST_CSC_C11;
103 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12;
104 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12;
105
106 if (select == INPUT_CSC_SELECT_ICSC) {
107
108 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_C11_C12);
109 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_C33_C34);
110
111 } else {
112
113 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_B_C11_C12);
114 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_B_C33_C34);
115
116 }
117
118 cm_helper_program_color_matrices(
119 dpp->base.ctx,
120 regval,
121 &gam_regs);
122
123 REG_SET(CM_POST_CSC_CONTROL, 0,
124 CM_POST_CSC_MODE, select);
125}
126
127
128/*CNVC degam unit has read only LUTs*/
129void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined tr)
130{
131 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
132 int pre_degam_en = 1;
133 int degamma_lut_selection = 0;
134
135 switch (tr) {
136 case TRANSFER_FUNCTION_LINEAR:
137 case TRANSFER_FUNCTION_UNITY:
138 pre_degam_en = 0; //bypass
139 break;
140 case TRANSFER_FUNCTION_SRGB:
141 degamma_lut_selection = 0;
142 break;
143 case TRANSFER_FUNCTION_BT709:
144 degamma_lut_selection = 4;
145 break;
146 case TRANSFER_FUNCTION_PQ:
147 degamma_lut_selection = 5;
148 break;
149 case TRANSFER_FUNCTION_HLG:
150 degamma_lut_selection = 6;
151 break;
152 case TRANSFER_FUNCTION_GAMMA22:
153 degamma_lut_selection = 1;
154 break;
155 case TRANSFER_FUNCTION_GAMMA24:
156 degamma_lut_selection = 2;
157 break;
158 case TRANSFER_FUNCTION_GAMMA26:
159 degamma_lut_selection = 3;
160 break;
161 default:
162 pre_degam_en = 0;
163 break;
164 }
165
166 REG_SET_2(PRE_DEGAM, 0,
167 PRE_DEGAM_MODE, pre_degam_en,
168 PRE_DEGAM_SELECT, degamma_lut_selection);
169}
170
171static void dpp3_cnv_setup (
172 struct dpp *dpp_base,
173 enum surface_pixel_format format,
174 enum expansion_mode mode,
175 struct dc_csc_transform input_csc_color_matrix,
176 enum dc_color_space input_color_space,
177 struct cnv_alpha_2bit_lut *alpha_2bit_lut)
178{
179 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
180 uint32_t pixel_format = 0;
181 uint32_t alpha_en = 1;
182 enum dc_color_space color_space = COLOR_SPACE_SRGB;
183 enum dcn10_input_csc_select select = INPUT_CSC_SELECT_BYPASS;
184 bool force_disable_cursor = false;
185 uint32_t is_2bit = 0;
186 uint32_t alpha_plane_enable = 0;
187 uint32_t dealpha_en = 0, dealpha_ablnd_en = 0;
188 uint32_t realpha_en = 0, realpha_ablnd_en = 0;
189 uint32_t program_prealpha_dealpha = 0;
190 struct out_csc_color_matrix tbl_entry;
191 int i;
192
193 REG_SET_2(FORMAT_CONTROL, 0,
194 CNVC_BYPASS, 0,
195 FORMAT_EXPANSION_MODE, mode);
196
197 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);
198 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);
199 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);
200 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);
201
202 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0);
203 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1);
204 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2);
205
206 switch (format) {
207 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
208 pixel_format = 1;
209 break;
210 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
211 pixel_format = 3;
212 alpha_en = 0;
213 break;
214 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
215 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
216 pixel_format = 8;
217 break;
218 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
219 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
220 pixel_format = 10;
221 is_2bit = 1;
222 break;
223 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
224 force_disable_cursor = false;
225 pixel_format = 65;
226 color_space = COLOR_SPACE_YCBCR709;
227 select = INPUT_CSC_SELECT_ICSC;
228 break;
229 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
230 force_disable_cursor = true;
231 pixel_format = 64;
232 color_space = COLOR_SPACE_YCBCR709;
233 select = INPUT_CSC_SELECT_ICSC;
234 break;
235 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
236 force_disable_cursor = true;
237 pixel_format = 67;
238 color_space = COLOR_SPACE_YCBCR709;
239 select = INPUT_CSC_SELECT_ICSC;
240 break;
241 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
242 force_disable_cursor = true;
243 pixel_format = 66;
244 color_space = COLOR_SPACE_YCBCR709;
245 select = INPUT_CSC_SELECT_ICSC;
246 break;
247 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
248 pixel_format = 22;
249 break;
250 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
251 pixel_format = 24;
252 break;
253 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
254 pixel_format = 25;
255 break;
256 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
257 pixel_format = 12;
258 color_space = COLOR_SPACE_YCBCR709;
259 select = INPUT_CSC_SELECT_ICSC;
260 break;
261 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
262 pixel_format = 112;
263 break;
264 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
265 pixel_format = 113;
266 break;
267 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
268 pixel_format = 114;
269 color_space = COLOR_SPACE_YCBCR709;
270 select = INPUT_CSC_SELECT_ICSC;
271 is_2bit = 1;
272 break;
273 case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102:
274 pixel_format = 115;
275 color_space = COLOR_SPACE_YCBCR709;
276 select = INPUT_CSC_SELECT_ICSC;
277 is_2bit = 1;
278 break;
279 case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
280 pixel_format = 116;
281 alpha_plane_enable = 0;
282 break;
283 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
284 pixel_format = 116;
285 alpha_plane_enable = 1;
286 break;
287 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
288 pixel_format = 118;
289 break;
290 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
291 pixel_format = 119;
292 break;
293 default:
294 break;
295 }
296
297 if (is_2bit == 1 && alpha_2bit_lut != NULL) {
298 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
299 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
300 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2);
301 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3);
302 }
303
304 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0,
305 CNVC_SURFACE_PIXEL_FORMAT, pixel_format,
306 CNVC_ALPHA_PLANE_ENABLE, alpha_plane_enable);
307 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
308
309 if (program_prealpha_dealpha) {
310 dealpha_en = 1;
311 realpha_en = 1;
312 }
313 REG_SET_2(PRE_DEALPHA, 0,
314 PRE_DEALPHA_EN, dealpha_en,
315 PRE_DEALPHA_ABLND_EN, dealpha_ablnd_en);
316 REG_SET_2(PRE_REALPHA, 0,
317 PRE_REALPHA_EN, realpha_en,
318 PRE_REALPHA_ABLND_EN, realpha_ablnd_en);
319
320 /* If input adjustment exists, program the ICSC with those values. */
321 if (input_csc_color_matrix.enable_adjustment == true) {
322 for (i = 0; i < 12; i++)
323 tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
324
325 tbl_entry.color_space = input_color_space;
326
327 if (color_space >= COLOR_SPACE_YCBCR601)
328 select = INPUT_CSC_SELECT_ICSC;
329 else
330 select = INPUT_CSC_SELECT_BYPASS;
331
332 dpp3_program_post_csc(dpp_base, color_space, select,
333 &tbl_entry);
334 } else {
335 dpp3_program_post_csc(dpp_base, color_space, select, NULL);
336 }
337
338 if (force_disable_cursor) {
339 REG_UPDATE(CURSOR_CONTROL,
340 CURSOR_ENABLE, 0);
341 REG_UPDATE(CURSOR0_CONTROL,
342 CUR0_ENABLE, 0);
343 }
344}
345
346#define IDENTITY_RATIO(ratio) (dc_fixpt_u3d19(ratio) == (1 << 19))
347
348void dpp3_set_cursor_attributes(
349 struct dpp *dpp_base,
350 struct dc_cursor_attributes *cursor_attributes)
351{
352 enum dc_cursor_color_format color_format = cursor_attributes->color_format;
353 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
354 int cur_rom_en = 0;
355
356 if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
357 color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA)
358 cur_rom_en = 1;
359
360 REG_UPDATE_3(CURSOR0_CONTROL,
361 CUR0_MODE, color_format,
362 CUR0_EXPANSION_MODE, 0,
363 CUR0_ROM_EN, cur_rom_en);
364
365 if (color_format == CURSOR_MODE_MONO) {
366 /* todo: clarify what to program these to */
367 REG_UPDATE(CURSOR0_COLOR0,
368 CUR0_COLOR0, 0x00000000);
369 REG_UPDATE(CURSOR0_COLOR1,
370 CUR0_COLOR1, 0xFFFFFFFF);
371 }
372}
373
374
375bool dpp3_get_optimal_number_of_taps(
376 struct dpp *dpp,
377 struct scaler_data *scl_data,
378 const struct scaling_taps *in_taps)
379{
380 int num_part_y, num_part_c;
381 int max_taps_y, max_taps_c;
382 int min_taps_y, min_taps_c;
383 enum lb_memory_config lb_config;
384
385 /* Some ASICs does not support FP16 scaling, so we reject modes require this*/
386 if (scl_data->viewport.width != scl_data->h_active &&
387 scl_data->viewport.height != scl_data->v_active &&
388 dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&
389 scl_data->format == PIXEL_FORMAT_FP16)
390 return false;
391
392 if (scl_data->viewport.width > scl_data->h_active &&
393 dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
394 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
395 return false;
396
397 /*
398 * Set default taps if none are provided
399 * From programming guide: taps = min{ ceil(2*H_RATIO,1), 8} for downscaling
400 * taps = 4 for upscaling
401 */
402 if (in_taps->h_taps == 0) {
403 if (dc_fixpt_ceil(scl_data->ratios.horz) > 1)
404 scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8);
405 else
406 scl_data->taps.h_taps = 4;
407 } else
408 scl_data->taps.h_taps = in_taps->h_taps;
409 if (in_taps->v_taps == 0) {
410 if (dc_fixpt_ceil(scl_data->ratios.vert) > 1)
411 scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8);
412 else
413 scl_data->taps.v_taps = 4;
414 } else
415 scl_data->taps.v_taps = in_taps->v_taps;
416 if (in_taps->v_taps_c == 0) {
417 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 1)
418 scl_data->taps.v_taps_c = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert_c, 2)), 8);
419 else
420 scl_data->taps.v_taps_c = 4;
421 } else
422 scl_data->taps.v_taps_c = in_taps->v_taps_c;
423 if (in_taps->h_taps_c == 0) {
424 if (dc_fixpt_ceil(scl_data->ratios.horz_c) > 1)
425 scl_data->taps.h_taps_c = min(2 * dc_fixpt_ceil(scl_data->ratios.horz_c), 8);
426 else
427 scl_data->taps.h_taps_c = 4;
428 } else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1)
429 /* Only 1 and even h_taps_c are supported by hw */
430 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
431 else
432 scl_data->taps.h_taps_c = in_taps->h_taps_c;
433
434 /*Ensure we can support the requested number of vtaps*/
435 min_taps_y = dc_fixpt_ceil(scl_data->ratios.vert);
436 min_taps_c = dc_fixpt_ceil(scl_data->ratios.vert_c);
437
438 /* Use LB_MEMORY_CONFIG_3 for 4:2:0 */
439 if ((scl_data->format == PIXEL_FORMAT_420BPP8) || (scl_data->format == PIXEL_FORMAT_420BPP10))
440 lb_config = LB_MEMORY_CONFIG_3;
441 else
442 lb_config = LB_MEMORY_CONFIG_0;
443
444 dpp->caps->dscl_calc_lb_num_partitions(
445 scl_data, lb_config, &num_part_y, &num_part_c);
446
447 /* MAX_V_TAPS = MIN (NUM_LINES - MAX(CEILING(V_RATIO,1)-2, 0), 8) */
448 if (dc_fixpt_ceil(scl_data->ratios.vert) > 2)
449 max_taps_y = num_part_y - (dc_fixpt_ceil(scl_data->ratios.vert) - 2);
450 else
451 max_taps_y = num_part_y;
452
453 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 2)
454 max_taps_c = num_part_c - (dc_fixpt_ceil(scl_data->ratios.vert_c) - 2);
455 else
456 max_taps_c = num_part_c;
457
458 if (max_taps_y < min_taps_y)
459 return false;
460 else if (max_taps_c < min_taps_c)
461 return false;
462
463 if (scl_data->taps.v_taps > max_taps_y)
464 scl_data->taps.v_taps = max_taps_y;
465
466 if (scl_data->taps.v_taps_c > max_taps_c)
467 scl_data->taps.v_taps_c = max_taps_c;
468
469 if (!dpp->ctx->dc->debug.always_scale) {
470 if (IDENTITY_RATIO(scl_data->ratios.horz))
471 scl_data->taps.h_taps = 1;
472 if (IDENTITY_RATIO(scl_data->ratios.vert))
473 scl_data->taps.v_taps = 1;
474 if (IDENTITY_RATIO(scl_data->ratios.horz_c))
475 scl_data->taps.h_taps_c = 1;
476 if (IDENTITY_RATIO(scl_data->ratios.vert_c))
477 scl_data->taps.v_taps_c = 1;
478 }
479
480 return true;
481}
482
483void dpp3_cnv_set_bias_scale(
484 struct dpp *dpp_base,
485 struct dc_bias_and_scale *bias_and_scale)
486{
487 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
488
489 REG_UPDATE(FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, bias_and_scale->bias_red);
490 REG_UPDATE(FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, bias_and_scale->bias_green);
491 REG_UPDATE(FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, bias_and_scale->bias_blue);
492 REG_UPDATE(FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, bias_and_scale->scale_red);
493 REG_UPDATE(FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, bias_and_scale->scale_green);
494 REG_UPDATE(FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, bias_and_scale->scale_blue);
495}
496
497static void dpp3_power_on_blnd_lut(
498 struct dpp *dpp_base,
499 bool power_on)
500{
501 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
502
503 REG_SET(CM_MEM_PWR_CTRL, 0,
504 BLNDGAM_MEM_PWR_FORCE, power_on == true ? 0:1);
505
506}
507
508static void dpp3_configure_blnd_lut(
509 struct dpp *dpp_base,
510 bool is_ram_a)
511{
512 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
513
514 REG_UPDATE_2(CM_BLNDGAM_LUT_CONTROL,
515 CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 7,
516 CM_BLNDGAM_LUT_HOST_SEL, is_ram_a == true ? 0 : 1);
517
518 REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0);
519}
520
521static void dpp3_program_blnd_pwl(
522 struct dpp *dpp_base,
523 const struct pwl_result_data *rgb,
524 uint32_t num)
525{
526 uint32_t i;
527 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
528 uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;
529 uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;
530 uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;
531
532 if (is_rgb_equal(rgb, num)) {
533 for (i = 0 ; i < num; i++)
534 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);
535 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);
536 } else {
537 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 4);
538 for (i = 0 ; i < num; i++)
539 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);
540 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);
541
542 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 2);
543 for (i = 0 ; i < num; i++)
544 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].green_reg);
545 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_green);
546
547 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 1);
548 for (i = 0 ; i < num; i++)
549 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].blue_reg);
550 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_blue);
551 }
552}
553
554static void dcn3_dpp_cm_get_reg_field(
555 struct dcn3_dpp *dpp,
556 struct dcn3_xfer_func_reg *reg)
557{
558 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
559 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
560 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
561 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
562 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
563 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
564 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
565 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
566
567 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
568 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
569 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
570 reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
571 reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
572 reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
573 reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;
574 reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;
575 reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
576 reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
577 reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
578 reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
579}
580
581/*program blnd lut RAM A*/
582static void dpp3_program_blnd_luta_settings(
583 struct dpp *dpp_base,
584 const struct pwl_params *params)
585{
586 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
587 struct dcn3_xfer_func_reg gam_regs;
588
589 dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);
590
591 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B);
592 gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G);
593 gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R);
594 gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B);
595 gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G);
596 gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R);
597 gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMA_END_CNTL1_B);
598 gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMA_END_CNTL2_B);
599 gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMA_END_CNTL1_G);
600 gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMA_END_CNTL2_G);
601 gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMA_END_CNTL1_R);
602 gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMA_END_CNTL2_R);
603 gam_regs.region_start = REG(CM_BLNDGAM_RAMA_REGION_0_1);
604 gam_regs.region_end = REG(CM_BLNDGAM_RAMA_REGION_32_33);
605
606 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);
607}
608
609/*program blnd lut RAM B*/
610static void dpp3_program_blnd_lutb_settings(
611 struct dpp *dpp_base,
612 const struct pwl_params *params)
613{
614 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
615 struct dcn3_xfer_func_reg gam_regs;
616
617 dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);
618
619 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMB_START_CNTL_B);
620 gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMB_START_CNTL_G);
621 gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMB_START_CNTL_R);
622 gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B);
623 gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G);
624 gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R);
625 gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMB_END_CNTL1_B);
626 gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMB_END_CNTL2_B);
627 gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMB_END_CNTL1_G);
628 gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMB_END_CNTL2_G);
629 gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMB_END_CNTL1_R);
630 gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMB_END_CNTL2_R);
631 gam_regs.region_start = REG(CM_BLNDGAM_RAMB_REGION_0_1);
632 gam_regs.region_end = REG(CM_BLNDGAM_RAMB_REGION_32_33);
633
634 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);
635}
636
637static enum dc_lut_mode dpp3_get_blndgam_current(struct dpp *dpp_base)
638{
639 enum dc_lut_mode mode;
640 uint32_t mode_current = 0;
641 uint32_t in_use = 0;
642
643 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
644
645 REG_GET(CM_BLNDGAM_CONTROL,
646 CM_BLNDGAM_MODE_CURRENT, &mode_current);
647 REG_GET(CM_BLNDGAM_CONTROL,
648 CM_BLNDGAM_SELECT_CURRENT, &in_use);
649
650 switch (mode_current) {
651 case 0:
652 case 1:
653 mode = LUT_BYPASS;
654 break;
655
656 case 2:
657 if (in_use == 0)
658 mode = LUT_RAM_A;
659 else
660 mode = LUT_RAM_B;
661 break;
662 default:
663 mode = LUT_BYPASS;
664 break;
665 }
666 return mode;
667}
668
669bool dpp3_program_blnd_lut(
670 struct dpp *dpp_base, const struct pwl_params *params)
671{
672 enum dc_lut_mode current_mode;
673 enum dc_lut_mode next_mode;
674 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
675
676 if (params == NULL) {
677 REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_MODE, 0);
678 return false;
679 }
680
681 current_mode = dpp3_get_blndgam_current(dpp_base);
682 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_B)
683 next_mode = LUT_RAM_A;
684 else
685 next_mode = LUT_RAM_B;
686
687 dpp3_power_on_blnd_lut(dpp_base, true);
688 dpp3_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A ? true:false);
689
690 if (next_mode == LUT_RAM_A)
691 dpp3_program_blnd_luta_settings(dpp_base, params);
692 else
693 dpp3_program_blnd_lutb_settings(dpp_base, params);
694
695 dpp3_program_blnd_pwl(
696 dpp_base, params->rgb_resulted, params->hw_points_num);
697
698 REG_UPDATE_2(CM_BLNDGAM_CONTROL,
699 CM_BLNDGAM_MODE, 2,
700 CM_BLNDGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1);
701
702 return true;
703}
704
705
706static void dpp3_program_shaper_lut(
707 struct dpp *dpp_base,
708 const struct pwl_result_data *rgb,
709 uint32_t num)
710{
711 uint32_t i, red, green, blue;
712 uint32_t red_delta, green_delta, blue_delta;
713 uint32_t red_value, green_value, blue_value;
714
715 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
716
717 for (i = 0 ; i < num; i++) {
718
719 red = rgb[i].red_reg;
720 green = rgb[i].green_reg;
721 blue = rgb[i].blue_reg;
722
723 red_delta = rgb[i].delta_red_reg;
724 green_delta = rgb[i].delta_green_reg;
725 blue_delta = rgb[i].delta_blue_reg;
726
727 red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff);
728 green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff);
729 blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff);
730
731 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, red_value);
732 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, green_value);
733 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, blue_value);
734 }
735
736}
737
738static enum dc_lut_mode dpp3_get_shaper_current(struct dpp *dpp_base)
739{
740 enum dc_lut_mode mode;
741 uint32_t state_mode;
742 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
743
744 REG_GET(CM_SHAPER_CONTROL,
745 CM_SHAPER_MODE_CURRENT, &state_mode);
746
747 switch (state_mode) {
748 case 0:
749 mode = LUT_BYPASS;
750 break;
751 case 1:
752 mode = LUT_RAM_A;
753 break;
754 case 2:
755 mode = LUT_RAM_B;
756 break;
757 default:
758 mode = LUT_BYPASS;
759 break;
760 }
761 return mode;
762}
763
764static void dpp3_configure_shaper_lut(
765 struct dpp *dpp_base,
766 bool is_ram_a)
767{
768 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
769
770 REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,
771 CM_SHAPER_LUT_WRITE_EN_MASK, 7);
772 REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,
773 CM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1);
774 REG_SET(CM_SHAPER_LUT_INDEX, 0, CM_SHAPER_LUT_INDEX, 0);
775}
776
777/*program shaper RAM A*/
778
779static void dpp3_program_shaper_luta_settings(
780 struct dpp *dpp_base,
781 const struct pwl_params *params)
782{
783 const struct gamma_curve *curve;
784 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
785
786 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0,
787 CM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
788 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
789 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0,
790 CM_SHAPER_RAMA_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x,
791 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, 0);
792 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0,
793 CM_SHAPER_RAMA_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x,
794 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, 0);
795
796 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0,
797 CM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
798 CM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
799
800 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0,
801 CM_SHAPER_RAMA_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x,
802 CM_SHAPER_RAMA_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y);
803
804 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0,
805 CM_SHAPER_RAMA_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x,
806 CM_SHAPER_RAMA_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y);
807
808 curve = params->arr_curve_points;
809 REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0,
810 CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
811 CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
812 CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
813 CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
814
815 curve += 2;
816 REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0,
817 CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset,
818 CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
819 CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset,
820 CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
821
822 curve += 2;
823 REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0,
824 CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset,
825 CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
826 CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset,
827 CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
828
829 curve += 2;
830 REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0,
831 CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset,
832 CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
833 CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset,
834 CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
835
836 curve += 2;
837 REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0,
838 CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset,
839 CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
840 CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset,
841 CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
842
843 curve += 2;
844 REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0,
845 CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset,
846 CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
847 CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset,
848 CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
849
850 curve += 2;
851 REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0,
852 CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset,
853 CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
854 CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset,
855 CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
856
857 curve += 2;
858 REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0,
859 CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset,
860 CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
861 CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset,
862 CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
863
864 curve += 2;
865 REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0,
866 CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset,
867 CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
868 CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset,
869 CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
870
871 curve += 2;
872 REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0,
873 CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset,
874 CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
875 CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset,
876 CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
877
878 curve += 2;
879 REG_SET_4(CM_SHAPER_RAMA_REGION_20_21, 0,
880 CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset,
881 CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
882 CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset,
883 CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
884
885 curve += 2;
886 REG_SET_4(CM_SHAPER_RAMA_REGION_22_23, 0,
887 CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset,
888 CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
889 CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset,
890 CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
891
892 curve += 2;
893 REG_SET_4(CM_SHAPER_RAMA_REGION_24_25, 0,
894 CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset,
895 CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
896 CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset,
897 CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
898
899 curve += 2;
900 REG_SET_4(CM_SHAPER_RAMA_REGION_26_27, 0,
901 CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset,
902 CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
903 CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset,
904 CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
905
906 curve += 2;
907 REG_SET_4(CM_SHAPER_RAMA_REGION_28_29, 0,
908 CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset,
909 CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
910 CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset,
911 CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
912
913 curve += 2;
914 REG_SET_4(CM_SHAPER_RAMA_REGION_30_31, 0,
915 CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset,
916 CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
917 CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset,
918 CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
919
920 curve += 2;
921 REG_SET_4(CM_SHAPER_RAMA_REGION_32_33, 0,
922 CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset,
923 CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
924 CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset,
925 CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
926}
927
928/*program shaper RAM B*/
929static void dpp3_program_shaper_lutb_settings(
930 struct dpp *dpp_base,
931 const struct pwl_params *params)
932{
933 const struct gamma_curve *curve;
934 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
935
936 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0,
937 CM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
938 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0);
939 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0,
940 CM_SHAPER_RAMB_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x,
941 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, 0);
942 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0,
943 CM_SHAPER_RAMB_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x,
944 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, 0);
945
946 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0,
947 CM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
948 CM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
949
950 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_G, 0,
951 CM_SHAPER_RAMB_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x,
952 CM_SHAPER_RAMB_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y);
953
954 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_R, 0,
955 CM_SHAPER_RAMB_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x,
956 CM_SHAPER_RAMB_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y);
957
958 curve = params->arr_curve_points;
959 REG_SET_4(CM_SHAPER_RAMB_REGION_0_1, 0,
960 CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,
961 CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
962 CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,
963 CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
964
965 curve += 2;
966 REG_SET_4(CM_SHAPER_RAMB_REGION_2_3, 0,
967 CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset,
968 CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
969 CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset,
970 CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
971
972 curve += 2;
973 REG_SET_4(CM_SHAPER_RAMB_REGION_4_5, 0,
974 CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset,
975 CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
976 CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset,
977 CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
978
979 curve += 2;
980 REG_SET_4(CM_SHAPER_RAMB_REGION_6_7, 0,
981 CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset,
982 CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
983 CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset,
984 CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
985
986 curve += 2;
987 REG_SET_4(CM_SHAPER_RAMB_REGION_8_9, 0,
988 CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset,
989 CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
990 CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset,
991 CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
992
993 curve += 2;
994 REG_SET_4(CM_SHAPER_RAMB_REGION_10_11, 0,
995 CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset,
996 CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
997 CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset,
998 CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
999
1000 curve += 2;
1001 REG_SET_4(CM_SHAPER_RAMB_REGION_12_13, 0,
1002 CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset,
1003 CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
1004 CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset,
1005 CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
1006
1007 curve += 2;
1008 REG_SET_4(CM_SHAPER_RAMB_REGION_14_15, 0,
1009 CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset,
1010 CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
1011 CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset,
1012 CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
1013
1014 curve += 2;
1015 REG_SET_4(CM_SHAPER_RAMB_REGION_16_17, 0,
1016 CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset,
1017 CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
1018 CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset,
1019 CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
1020
1021 curve += 2;
1022 REG_SET_4(CM_SHAPER_RAMB_REGION_18_19, 0,
1023 CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset,
1024 CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
1025 CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset,
1026 CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
1027
1028 curve += 2;
1029 REG_SET_4(CM_SHAPER_RAMB_REGION_20_21, 0,
1030 CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset,
1031 CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
1032 CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset,
1033 CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
1034
1035 curve += 2;
1036 REG_SET_4(CM_SHAPER_RAMB_REGION_22_23, 0,
1037 CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset,
1038 CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
1039 CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset,
1040 CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
1041
1042 curve += 2;
1043 REG_SET_4(CM_SHAPER_RAMB_REGION_24_25, 0,
1044 CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset,
1045 CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
1046 CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset,
1047 CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
1048
1049 curve += 2;
1050 REG_SET_4(CM_SHAPER_RAMB_REGION_26_27, 0,
1051 CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset,
1052 CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
1053 CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset,
1054 CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
1055
1056 curve += 2;
1057 REG_SET_4(CM_SHAPER_RAMB_REGION_28_29, 0,
1058 CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset,
1059 CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
1060 CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset,
1061 CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
1062
1063 curve += 2;
1064 REG_SET_4(CM_SHAPER_RAMB_REGION_30_31, 0,
1065 CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset,
1066 CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
1067 CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset,
1068 CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
1069
1070 curve += 2;
1071 REG_SET_4(CM_SHAPER_RAMB_REGION_32_33, 0,
1072 CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset,
1073 CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
1074 CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset,
1075 CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
1076
1077}
1078
1079
1080bool dpp3_program_shaper(
1081 struct dpp *dpp_base,
1082 const struct pwl_params *params)
1083{
1084 enum dc_lut_mode current_mode;
1085 enum dc_lut_mode next_mode;
1086
1087 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1088
1089 if (params == NULL) {
1090 REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, 0);
1091 return false;
1092 }
1093 current_mode = dpp3_get_shaper_current(dpp_base);
1094
1095 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
1096 next_mode = LUT_RAM_B;
1097 else
1098 next_mode = LUT_RAM_A;
1099
1100 dpp3_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A ? true:false);
1101
1102 if (next_mode == LUT_RAM_A)
1103 dpp3_program_shaper_luta_settings(dpp_base, params);
1104 else
1105 dpp3_program_shaper_lutb_settings(dpp_base, params);
1106
1107 dpp3_program_shaper_lut(
1108 dpp_base, params->rgb_resulted, params->hw_points_num);
1109
1110 REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);
1111
1112 return true;
1113
1114}
1115
1116static enum dc_lut_mode get3dlut_config(
1117 struct dpp *dpp_base,
1118 bool *is_17x17x17,
1119 bool *is_12bits_color_channel)
1120{
1121 uint32_t i_mode, i_enable_10bits, lut_size;
1122 enum dc_lut_mode mode;
1123 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1124
1125 REG_GET(CM_3DLUT_READ_WRITE_CONTROL,
1126 CM_3DLUT_30BIT_EN, &i_enable_10bits);
1127 REG_GET(CM_3DLUT_MODE,
1128 CM_3DLUT_MODE_CURRENT, &i_mode);
1129
1130 switch (i_mode) {
1131 case 0:
1132 mode = LUT_BYPASS;
1133 break;
1134 case 1:
1135 mode = LUT_RAM_A;
1136 break;
1137 case 2:
1138 mode = LUT_RAM_B;
1139 break;
1140 default:
1141 mode = LUT_BYPASS;
1142 break;
1143 }
1144 if (i_enable_10bits > 0)
1145 *is_12bits_color_channel = false;
1146 else
1147 *is_12bits_color_channel = true;
1148
1149 REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &lut_size);
1150
1151 if (lut_size == 0)
1152 *is_17x17x17 = true;
1153 else
1154 *is_17x17x17 = false;
1155
1156 return mode;
1157}
1158/*
1159 * select ramA or ramB, or bypass
1160 * select color channel size 10 or 12 bits
1161 * select 3dlut size 17x17x17 or 9x9x9
1162 */
1163static void dpp3_set_3dlut_mode(
1164 struct dpp *dpp_base,
1165 enum dc_lut_mode mode,
1166 bool is_color_channel_12bits,
1167 bool is_lut_size17x17x17)
1168{
1169 uint32_t lut_mode;
1170 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1171
1172 if (mode == LUT_BYPASS)
1173 lut_mode = 0;
1174 else if (mode == LUT_RAM_A)
1175 lut_mode = 1;
1176 else
1177 lut_mode = 2;
1178
1179 REG_UPDATE_2(CM_3DLUT_MODE,
1180 CM_3DLUT_MODE, lut_mode,
1181 CM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1);
1182}
1183
1184static void dpp3_select_3dlut_ram(
1185 struct dpp *dpp_base,
1186 enum dc_lut_mode mode,
1187 bool is_color_channel_12bits)
1188{
1189 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1190
1191 REG_UPDATE_2(CM_3DLUT_READ_WRITE_CONTROL,
1192 CM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,
1193 CM_3DLUT_30BIT_EN,
1194 is_color_channel_12bits == true ? 0:1);
1195}
1196
1197
1198
1199static void dpp3_set3dlut_ram12(
1200 struct dpp *dpp_base,
1201 const struct dc_rgb *lut,
1202 uint32_t entries)
1203{
1204 uint32_t i, red, green, blue, red1, green1, blue1;
1205 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1206
1207 for (i = 0 ; i < entries; i += 2) {
1208 red = lut[i].red<<4;
1209 green = lut[i].green<<4;
1210 blue = lut[i].blue<<4;
1211 red1 = lut[i+1].red<<4;
1212 green1 = lut[i+1].green<<4;
1213 blue1 = lut[i+1].blue<<4;
1214
1215 REG_SET_2(CM_3DLUT_DATA, 0,
1216 CM_3DLUT_DATA0, red,
1217 CM_3DLUT_DATA1, red1);
1218
1219 REG_SET_2(CM_3DLUT_DATA, 0,
1220 CM_3DLUT_DATA0, green,
1221 CM_3DLUT_DATA1, green1);
1222
1223 REG_SET_2(CM_3DLUT_DATA, 0,
1224 CM_3DLUT_DATA0, blue,
1225 CM_3DLUT_DATA1, blue1);
1226
1227 }
1228}
1229
1230/*
1231 * load selected lut with 10 bits color channels
1232 */
1233static void dpp3_set3dlut_ram10(
1234 struct dpp *dpp_base,
1235 const struct dc_rgb *lut,
1236 uint32_t entries)
1237{
1238 uint32_t i, red, green, blue, value;
1239 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1240
1241 for (i = 0; i < entries; i++) {
1242 red = lut[i].red;
1243 green = lut[i].green;
1244 blue = lut[i].blue;
1245
1246 value = (red<<20) | (green<<10) | blue;
1247
1248 REG_SET(CM_3DLUT_DATA_30BIT, 0, CM_3DLUT_DATA_30BIT, value);
1249 }
1250
1251}
1252
1253
1254static void dpp3_select_3dlut_ram_mask(
1255 struct dpp *dpp_base,
1256 uint32_t ram_selection_mask)
1257{
1258 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1259
1260 REG_UPDATE(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK,
1261 ram_selection_mask);
1262 REG_SET(CM_3DLUT_INDEX, 0, CM_3DLUT_INDEX, 0);
1263}
1264
1265bool dpp3_program_3dlut(
1266 struct dpp *dpp_base,
1267 struct tetrahedral_params *params)
1268{
1269 enum dc_lut_mode mode;
1270 bool is_17x17x17;
1271 bool is_12bits_color_channel;
1272 struct dc_rgb *lut0;
1273 struct dc_rgb *lut1;
1274 struct dc_rgb *lut2;
1275 struct dc_rgb *lut3;
1276 int lut_size0;
1277 int lut_size;
1278
1279 if (params == NULL) {
1280 dpp3_set_3dlut_mode(dpp_base, LUT_BYPASS, false, false);
1281 return false;
1282 }
1283 mode = get3dlut_config(dpp_base, &is_17x17x17, &is_12bits_color_channel);
1284
1285 if (mode == LUT_BYPASS || mode == LUT_RAM_B)
1286 mode = LUT_RAM_A;
1287 else
1288 mode = LUT_RAM_B;
1289
1290 is_17x17x17 = !params->use_tetrahedral_9;
1291 is_12bits_color_channel = params->use_12bits;
1292 if (is_17x17x17) {
1293 lut0 = params->tetrahedral_17.lut0;
1294 lut1 = params->tetrahedral_17.lut1;
1295 lut2 = params->tetrahedral_17.lut2;
1296 lut3 = params->tetrahedral_17.lut3;
1297 lut_size0 = sizeof(params->tetrahedral_17.lut0)/
1298 sizeof(params->tetrahedral_17.lut0[0]);
1299 lut_size = sizeof(params->tetrahedral_17.lut1)/
1300 sizeof(params->tetrahedral_17.lut1[0]);
1301 } else {
1302 lut0 = params->tetrahedral_9.lut0;
1303 lut1 = params->tetrahedral_9.lut1;
1304 lut2 = params->tetrahedral_9.lut2;
1305 lut3 = params->tetrahedral_9.lut3;
1306 lut_size0 = sizeof(params->tetrahedral_9.lut0)/
1307 sizeof(params->tetrahedral_9.lut0[0]);
1308 lut_size = sizeof(params->tetrahedral_9.lut1)/
1309 sizeof(params->tetrahedral_9.lut1[0]);
1310 }
1311
1312 dpp3_select_3dlut_ram(dpp_base, mode,
1313 is_12bits_color_channel);
1314 dpp3_select_3dlut_ram_mask(dpp_base, 0x1);
1315 if (is_12bits_color_channel)
1316 dpp3_set3dlut_ram12(dpp_base, lut0, lut_size0);
1317 else
1318 dpp3_set3dlut_ram10(dpp_base, lut0, lut_size0);
1319
1320 dpp3_select_3dlut_ram_mask(dpp_base, 0x2);
1321 if (is_12bits_color_channel)
1322 dpp3_set3dlut_ram12(dpp_base, lut1, lut_size);
1323 else
1324 dpp3_set3dlut_ram10(dpp_base, lut1, lut_size);
1325
1326 dpp3_select_3dlut_ram_mask(dpp_base, 0x4);
1327 if (is_12bits_color_channel)
1328 dpp3_set3dlut_ram12(dpp_base, lut2, lut_size);
1329 else
1330 dpp3_set3dlut_ram10(dpp_base, lut2, lut_size);
1331
1332 dpp3_select_3dlut_ram_mask(dpp_base, 0x8);
1333 if (is_12bits_color_channel)
1334 dpp3_set3dlut_ram12(dpp_base, lut3, lut_size);
1335 else
1336 dpp3_set3dlut_ram10(dpp_base, lut3, lut_size);
1337
1338
1339 dpp3_set_3dlut_mode(dpp_base, mode, is_12bits_color_channel,
1340 is_17x17x17);
1341
1342 return true;
1343}
1344static struct dpp_funcs dcn30_dpp_funcs = {
1345 .dpp_program_gamcor_lut = dpp3_program_gamcor_lut,
1346 .dpp_read_state = dpp30_read_state,
1347 .dpp_reset = dpp_reset,
1348 .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
1349 .dpp_get_optimal_number_of_taps = dpp3_get_optimal_number_of_taps,
1350 .dpp_set_gamut_remap = dpp3_cm_set_gamut_remap,
1351 .dpp_set_csc_adjustment = NULL,
1352 .dpp_set_csc_default = NULL,
1353 .dpp_program_regamma_pwl = NULL,
1354 .dpp_set_pre_degam = dpp3_set_pre_degam,
1355 .dpp_program_input_lut = NULL,
1356 .dpp_full_bypass = dpp1_full_bypass,
1357 .dpp_setup = dpp3_cnv_setup,
1358 .dpp_program_degamma_pwl = NULL,
1359 .dpp_program_cm_dealpha = dpp3_program_cm_dealpha,
1360 .dpp_program_cm_bias = dpp3_program_cm_bias,
1361#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
1362 .dpp_program_blnd_lut = dpp3_program_blnd_lut,
1363 .dpp_program_shaper_lut = dpp3_program_shaper,
1364 .dpp_program_3dlut = dpp3_program_3dlut,
1365#else
1366 .dpp_program_blnd_lut = NULL,
1367 .dpp_program_shaper_lut = NULL,
1368 .dpp_program_3dlut = NULL,
1369#endif
1370
1371 .dpp_program_bias_and_scale = NULL,
1372 .dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer,
1373 .set_cursor_attributes = dpp3_set_cursor_attributes,
1374 .set_cursor_position = dpp1_set_cursor_position,
1375 .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
1376 .dpp_dppclk_control = dpp1_dppclk_control,
1377 .dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier,
1378};
1379
1380
1381static struct dpp_caps dcn30_dpp_cap = {
1382 .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT,
1383 .dscl_calc_lb_num_partitions = dscl2_calc_lb_num_partitions,
1384};
1385
1386bool dpp3_construct(
1387 struct dcn3_dpp *dpp,
1388 struct dc_context *ctx,
1389 uint32_t inst,
1390 const struct dcn3_dpp_registers *tf_regs,
1391 const struct dcn3_dpp_shift *tf_shift,
1392 const struct dcn3_dpp_mask *tf_mask)
1393{
1394 dpp->base.ctx = ctx;
1395
1396 dpp->base.inst = inst;
1397 dpp->base.funcs = &dcn30_dpp_funcs;
1398 dpp->base.caps = &dcn30_dpp_cap;
1399
1400 dpp->tf_regs = tf_regs;
1401 dpp->tf_shift = tf_shift;
1402 dpp->tf_mask = tf_mask;
1403
1404 dpp->lb_pixel_depth_supported =
1405 LB_PIXEL_DEPTH_18BPP |
1406 LB_PIXEL_DEPTH_24BPP |
1407 LB_PIXEL_DEPTH_30BPP;
1408
1409 dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;
1410 dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
1411
1412 return true;
1413}
1414
Linux 6.x block layer and io_uring tree(s)