projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/amd/display: Access patches from stream for ignore MSA monitor patch
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / dc / dcn21 / dcn21_resource.c
CommitLineData
6f4e6361
BL		 1/*
2* Copyright 2018 Advanced Micro Devices, Inc.
6ca3928d 3 * Copyright 2019 Raptor Engineering, LLC
6f4e6361
BL		 4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
aec43402
AB		 27#include <linux/slab.h>
28
6f4e6361
BL		 29#include "dm_services.h"
30#include "dc.h"
31
78c77382
AK		 32#include "dcn21_init.h"
33
6f4e6361
BL		 34#include "resource.h"
35#include "include/irq_service_interface.h"
36#include "dcn20/dcn20_resource.h"
37
38#include "clk_mgr.h"
39#include "dcn10/dcn10_hubp.h"
40#include "dcn10/dcn10_ipp.h"
41#include "dcn20/dcn20_hubbub.h"
42#include "dcn20/dcn20_mpc.h"
43#include "dcn20/dcn20_hubp.h"
44#include "dcn21_hubp.h"
45#include "irq/dcn21/irq_service_dcn21.h"
46#include "dcn20/dcn20_dpp.h"
47#include "dcn20/dcn20_optc.h"
c0fb59a4 48#include "dcn21/dcn21_hwseq.h"
6f4e6361
BL		 49#include "dce110/dce110_hw_sequencer.h"
50#include "dcn20/dcn20_opp.h"
51#include "dcn20/dcn20_dsc.h"
91c665bd 52#include "dcn21/dcn21_link_encoder.h"
6f4e6361
BL		 53#include "dcn20/dcn20_stream_encoder.h"
54#include "dce/dce_clock_source.h"
55#include "dce/dce_audio.h"
56#include "dce/dce_hwseq.h"
57#include "virtual/virtual_stream_encoder.h"
58#include "dce110/dce110_resource.h"
59#include "dml/display_mode_vba.h"
60#include "dcn20/dcn20_dccg.h"
61#include "dcn21_hubbub.h"
62#include "dcn10/dcn10_resource.h"
15add0c2 63#include "dce110/dce110_resource.h"
6f4e6361
BL		 64
65#include "dcn20/dcn20_dwb.h"
66#include "dcn20/dcn20_mmhubbub.h"
a771ded8
RL		 67#include "dpcs/dpcs_2_1_0_offset.h"
68#include "dpcs/dpcs_2_1_0_sh_mask.h"
6f4e6361
BL		 69
70#include "renoir_ip_offset.h"
71#include "dcn/dcn_2_1_0_offset.h"
72#include "dcn/dcn_2_1_0_sh_mask.h"
73
74#include "nbio/nbio_7_0_offset.h"
75
76#include "mmhub/mmhub_2_0_0_offset.h"
77#include "mmhub/mmhub_2_0_0_sh_mask.h"
78
79#include "reg_helper.h"
80#include "dce/dce_abm.h"
81#include "dce/dce_dmcu.h"
82#include "dce/dce_aux.h"
83#include "dce/dce_i2c.h"
84#include "dcn21_resource.h"
85#include "vm_helper.h"
86#include "dcn20/dcn20_vmid.h"
9dac88d8 87#include "dce/dmub_psr.h"
6f4e6361
BL		 88
89#define SOC_BOUNDING_BOX_VALID false
90#define DC_LOGGER_INIT(logger)
91
92
93struct _vcs_dpi_ip_params_st dcn2_1_ip = {
652651ff 94 .odm_capable = 1,
8c357309
YS		 95 .gpuvm_enable = 1,
96 .hostvm_enable = 1,
6f4e6361
BL		 97 .gpuvm_max_page_table_levels = 1,
98 .hostvm_max_page_table_levels = 4,
99 .hostvm_cached_page_table_levels = 2,
6f4e6361 100 .num_dsc = 3,
6f4e6361
BL		 101 .rob_buffer_size_kbytes = 168,
102 .det_buffer_size_kbytes = 164,
103 .dpte_buffer_size_in_pte_reqs_luma = 44,
104 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
105 .dpp_output_buffer_pixels = 2560,
106 .opp_output_buffer_lines = 1,
107 .pixel_chunk_size_kbytes = 8,
108 .pte_enable = 1,
109 .max_page_table_levels = 4,
110 .pte_chunk_size_kbytes = 2,
111 .meta_chunk_size_kbytes = 2,
112 .writeback_chunk_size_kbytes = 2,
113 .line_buffer_size_bits = 789504,
114 .is_line_buffer_bpp_fixed = 0,
115 .line_buffer_fixed_bpp = 0,
116 .dcc_supported = true,
117 .max_line_buffer_lines = 12,
118 .writeback_luma_buffer_size_kbytes = 12,
119 .writeback_chroma_buffer_size_kbytes = 8,
120 .writeback_chroma_line_buffer_width_pixels = 4,
121 .writeback_max_hscl_ratio = 1,
122 .writeback_max_vscl_ratio = 1,
123 .writeback_min_hscl_ratio = 1,
124 .writeback_min_vscl_ratio = 1,
125 .writeback_max_hscl_taps = 12,
126 .writeback_max_vscl_taps = 12,
127 .writeback_line_buffer_luma_buffer_size = 0,
128 .writeback_line_buffer_chroma_buffer_size = 14643,
129 .cursor_buffer_size = 8,
130 .cursor_chunk_size = 2,
131 .max_num_otg = 4,
132 .max_num_dpp = 4,
133 .max_num_wb = 1,
134 .max_dchub_pscl_bw_pix_per_clk = 4,
135 .max_pscl_lb_bw_pix_per_clk = 2,
136 .max_lb_vscl_bw_pix_per_clk = 4,
137 .max_vscl_hscl_bw_pix_per_clk = 4,
138 .max_hscl_ratio = 4,
139 .max_vscl_ratio = 4,
140 .hscl_mults = 4,
141 .vscl_mults = 4,
142 .max_hscl_taps = 8,
143 .max_vscl_taps = 8,
144 .dispclk_ramp_margin_percent = 1,
145 .underscan_factor = 1.10,
146 .min_vblank_lines = 32, //
147 .dppclk_delay_subtotal = 77, //
148 .dppclk_delay_scl_lb_only = 16,
149 .dppclk_delay_scl = 50,
150 .dppclk_delay_cnvc_formatter = 8,
151 .dppclk_delay_cnvc_cursor = 6,
152 .dispclk_delay_subtotal = 87, //
153 .dcfclk_cstate_latency = 10, // SRExitTime
154 .max_inter_dcn_tile_repeaters = 8,
155
156 .xfc_supported = false,
157 .xfc_fill_bw_overhead_percent = 10.0,
158 .xfc_fill_constant_bytes = 0,
159 .ptoi_supported = 0
160};
161
162struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
163 .clock_limits = {
164 {
165 .state = 0,
a39a5816
EY		 166 .dcfclk_mhz = 400.0,
167 .fabricclk_mhz = 400.0,
168 .dispclk_mhz = 600.0,
169 .dppclk_mhz = 400.00,
6f4e6361
BL		 170 .phyclk_mhz = 600.0,
171 .socclk_mhz = 278.0,
172 .dscclk_mhz = 205.67,
173 .dram_speed_mts = 1600.0,
174 },
175 {
176 .state = 1,
a39a5816
EY		 177 .dcfclk_mhz = 464.52,
178 .fabricclk_mhz = 800.0,
179 .dispclk_mhz = 654.55,
180 .dppclk_mhz = 626.09,
6f4e6361
BL		 181 .phyclk_mhz = 600.0,
182 .socclk_mhz = 278.0,
183 .dscclk_mhz = 205.67,
184 .dram_speed_mts = 1600.0,
185 },
186 {
187 .state = 2,
a39a5816
EY		 188 .dcfclk_mhz = 514.29,
189 .fabricclk_mhz = 933.0,
190 .dispclk_mhz = 757.89,
191 .dppclk_mhz = 685.71,
192 .phyclk_mhz = 600.0,
6f4e6361
BL		 193 .socclk_mhz = 278.0,
194 .dscclk_mhz = 287.67,
a39a5816 195 .dram_speed_mts = 1866.0,
6f4e6361
BL		 196 },
197 {
198 .state = 3,
a39a5816
EY		 199 .dcfclk_mhz = 576.00,
200 .fabricclk_mhz = 1067.0,
201 .dispclk_mhz = 847.06,
202 .dppclk_mhz = 757.89,
203 .phyclk_mhz = 600.0,
6f4e6361
BL		 204 .socclk_mhz = 715.0,
205 .dscclk_mhz = 318.334,
a39a5816 206 .dram_speed_mts = 2134.0,
6f4e6361
BL		 207 },
208 {
209 .state = 4,
a39a5816
EY		 210 .dcfclk_mhz = 626.09,
211 .fabricclk_mhz = 1200.0,
212 .dispclk_mhz = 900.00,
213 .dppclk_mhz = 847.06,
214 .phyclk_mhz = 810.0,
215 .socclk_mhz = 953.0,
216 .dscclk_mhz = 489.0,
217 .dram_speed_mts = 2400.0,
218 },
219 {
220 .state = 5,
221 .dcfclk_mhz = 685.71,
222 .fabricclk_mhz = 1333.0,
223 .dispclk_mhz = 1028.57,
224 .dppclk_mhz = 960.00,
225 .phyclk_mhz = 810.0,
226 .socclk_mhz = 278.0,
227 .dscclk_mhz = 287.67,
228 .dram_speed_mts = 2666.0,
229 },
230 {
231 .state = 6,
232 .dcfclk_mhz = 757.89,
233 .fabricclk_mhz = 1467.0,
234 .dispclk_mhz = 1107.69,
235 .dppclk_mhz = 1028.57,
236 .phyclk_mhz = 810.0,
237 .socclk_mhz = 715.0,
238 .dscclk_mhz = 318.334,
239 .dram_speed_mts = 3200.0,
240 },
241 {
242 .state = 7,
243 .dcfclk_mhz = 847.06,
6f4e6361 244 .fabricclk_mhz = 1600.0,
652651ff 245 .dispclk_mhz = 1395.0,
a39a5816 246 .dppclk_mhz = 1285.00,
652651ff 247 .phyclk_mhz = 1325.0,
6f4e6361 248 .socclk_mhz = 953.0,
652651ff 249 .dscclk_mhz = 489.0,
6f4e6361
BL		 250 .dram_speed_mts = 4266.0,
251 },
252 /*Extra state, no dispclk ramping*/
253 {
a39a5816
EY		 254 .state = 8,
255 .dcfclk_mhz = 847.06,
6f4e6361 256 .fabricclk_mhz = 1600.0,
652651ff
BL		 257 .dispclk_mhz = 1395.0,
258 .dppclk_mhz = 1285.0,
259 .phyclk_mhz = 1325.0,
6f4e6361 260 .socclk_mhz = 953.0,
652651ff 261 .dscclk_mhz = 489.0,
6f4e6361
BL		 262 .dram_speed_mts = 4266.0,
263 },
264
265 },
266
652651ff
BL		 267 .sr_exit_time_us = 12.5,
268 .sr_enter_plus_exit_time_us = 17.0,
6f4e6361
BL		 269 .urgent_latency_us = 4.0,
270 .urgent_latency_pixel_data_only_us = 4.0,
271 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
272 .urgent_latency_vm_data_only_us = 4.0,
273 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
274 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
275 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
276 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
277 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
278 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
279 .max_avg_sdp_bw_use_normal_percent = 60.0,
280 .max_avg_dram_bw_use_normal_percent = 100.0,
281 .writeback_latency_us = 12.0,
282 .max_request_size_bytes = 256,
283 .dram_channel_width_bytes = 4,
284 .fabric_datapath_to_dcn_data_return_bytes = 32,
285 .dcn_downspread_percent = 0.5,
286 .downspread_percent = 0.5,
287 .dram_page_open_time_ns = 50.0,
288 .dram_rw_turnaround_time_ns = 17.5,
289 .dram_return_buffer_per_channel_bytes = 8192,
290 .round_trip_ping_latency_dcfclk_cycles = 128,
291 .urgent_out_of_order_return_per_channel_bytes = 4096,
292 .channel_interleave_bytes = 256,
293 .num_banks = 8,
294 .num_chans = 4,
295 .vmm_page_size_bytes = 4096,
296 .dram_clock_change_latency_us = 23.84,
297 .return_bus_width_bytes = 64,
0beb5403 298 .dispclk_dppclk_vco_speed_mhz = 3600,
6f4e6361
BL		 299 .xfc_bus_transport_time_us = 4,
300 .xfc_xbuf_latency_tolerance_us = 4,
301 .use_urgent_burst_bw = 1,
a39a5816 302 .num_states = 9
6f4e6361
BL		 303};
304
305#ifndef MAX
306#define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
307#endif
308#ifndef MIN
309#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
310#endif
311
312/* begin *********************
313 * macros to expend register list macro defined in HW object header file */
314
315/* DCN */
316/* TODO awful hack. fixup dcn20_dwb.h */
317#undef BASE_INNER
318#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
319
320#define BASE(seg) BASE_INNER(seg)
321
322#define SR(reg_name)\
323 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
324 mm ## reg_name
325
326#define SRI(reg_name, block, id)\
327 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
328 mm ## block ## id ## _ ## reg_name
329
330#define SRIR(var_name, reg_name, block, id)\
331 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
332 mm ## block ## id ## _ ## reg_name
333
334#define SRII(reg_name, block, id)\
335 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
336 mm ## block ## id ## _ ## reg_name
337
338#define DCCG_SRII(reg_name, block, id)\
339 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
340 mm ## block ## id ## _ ## reg_name
341
342/* NBIO */
343#define NBIO_BASE_INNER(seg) \
344 NBIF0_BASE__INST0_SEG ## seg
345
346#define NBIO_BASE(seg) \
347 NBIO_BASE_INNER(seg)
348
349#define NBIO_SR(reg_name)\
350 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
351 mm ## reg_name
352
353/* MMHUB */
354#define MMHUB_BASE_INNER(seg) \
355 MMHUB_BASE__INST0_SEG ## seg
356
357#define MMHUB_BASE(seg) \
358 MMHUB_BASE_INNER(seg)
359
360#define MMHUB_SR(reg_name)\
361 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
362 mmMM ## reg_name
363
364#define clk_src_regs(index, pllid)\
365[index] = {\
366 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
367}
368
369static const struct dce110_clk_src_regs clk_src_regs[] = {
370 clk_src_regs(0, A),
371 clk_src_regs(1, B),
372 clk_src_regs(2, C),
373 clk_src_regs(3, D),
374 clk_src_regs(4, E),
375};
376
377static const struct dce110_clk_src_shift cs_shift = {
378 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
379};
380
381static const struct dce110_clk_src_mask cs_mask = {
382 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
383};
384
385static const struct bios_registers bios_regs = {
386 NBIO_SR(BIOS_SCRATCH_3),
387 NBIO_SR(BIOS_SCRATCH_6)
388};
389
c0fb59a4 390static const struct dce_dmcu_registers dmcu_regs = {
a7e3658e 391 DMCU_DCN20_REG_LIST()
c0fb59a4
BL		 392};
393
394static const struct dce_dmcu_shift dmcu_shift = {
395 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
396};
397
398static const struct dce_dmcu_mask dmcu_mask = {
399 DMCU_MASK_SH_LIST_DCN10(_MASK)
400};
401
402static const struct dce_abm_registers abm_regs = {
403 ABM_DCN20_REG_LIST()
404};
405
406static const struct dce_abm_shift abm_shift = {
407 ABM_MASK_SH_LIST_DCN20(__SHIFT)
408};
409
410static const struct dce_abm_mask abm_mask = {
411 ABM_MASK_SH_LIST_DCN20(_MASK)
412};
413
6f4e6361
BL		 414#define audio_regs(id)\
415[id] = {\
416 AUD_COMMON_REG_LIST(id)\
417}
418
419static const struct dce_audio_registers audio_regs[] = {
420 audio_regs(0),
421 audio_regs(1),
422 audio_regs(2),
423 audio_regs(3),
424 audio_regs(4),
425 audio_regs(5),
426};
427
428#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
429 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
430 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
431 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
432
433static const struct dce_audio_shift audio_shift = {
434 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
435};
436
437static const struct dce_audio_mask audio_mask = {
438 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
439};
440
441static const struct dccg_registers dccg_regs = {
442 DCCG_COMMON_REG_LIST_DCN_BASE()
443};
444
445static const struct dccg_shift dccg_shift = {
446 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
447};
448
449static const struct dccg_mask dccg_mask = {
450 DCCG_MASK_SH_LIST_DCN2(_MASK)
451};
452
453#define opp_regs(id)\
454[id] = {\
455 OPP_REG_LIST_DCN20(id),\
456}
457
458static const struct dcn20_opp_registers opp_regs[] = {
459 opp_regs(0),
460 opp_regs(1),
461 opp_regs(2),
462 opp_regs(3),
463 opp_regs(4),
464 opp_regs(5),
465};
466
467static const struct dcn20_opp_shift opp_shift = {
468 OPP_MASK_SH_LIST_DCN20(__SHIFT)
469};
470
471static const struct dcn20_opp_mask opp_mask = {
472 OPP_MASK_SH_LIST_DCN20(_MASK)
473};
474
475#define tg_regs(id)\
476[id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
477
478static const struct dcn_optc_registers tg_regs[] = {
479 tg_regs(0),
480 tg_regs(1),
481 tg_regs(2),
482 tg_regs(3)
483};
484
485static const struct dcn_optc_shift tg_shift = {
486 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
487};
488
489static const struct dcn_optc_mask tg_mask = {
490 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
491};
492
493static const struct dcn20_mpc_registers mpc_regs = {
494 MPC_REG_LIST_DCN2_0(0),
495 MPC_REG_LIST_DCN2_0(1),
496 MPC_REG_LIST_DCN2_0(2),
497 MPC_REG_LIST_DCN2_0(3),
498 MPC_REG_LIST_DCN2_0(4),
499 MPC_REG_LIST_DCN2_0(5),
500 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
501 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
502 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
e8027e08
NA		 503 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
504 MPC_DBG_REG_LIST_DCN2_0()
6f4e6361
BL		 505};
506
507static const struct dcn20_mpc_shift mpc_shift = {
c1e34175
NA		 508 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
509 MPC_DEBUG_REG_LIST_SH_DCN20
6f4e6361
BL		 510};
511
512static const struct dcn20_mpc_mask mpc_mask = {
c1e34175
NA		 513 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
514 MPC_DEBUG_REG_LIST_MASK_DCN20
6f4e6361
BL		 515};
516
517#define hubp_regs(id)\
518[id] = {\
519 HUBP_REG_LIST_DCN21(id)\
520}
521
522static const struct dcn_hubp2_registers hubp_regs[] = {
523 hubp_regs(0),
524 hubp_regs(1),
525 hubp_regs(2),
526 hubp_regs(3)
527};
528
529static const struct dcn_hubp2_shift hubp_shift = {
530 HUBP_MASK_SH_LIST_DCN21(__SHIFT)
531};
532
533static const struct dcn_hubp2_mask hubp_mask = {
534 HUBP_MASK_SH_LIST_DCN21(_MASK)
535};
536
537static const struct dcn_hubbub_registers hubbub_reg = {
538 HUBBUB_REG_LIST_DCN21()
539};
540
541static const struct dcn_hubbub_shift hubbub_shift = {
542 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
543};
544
545static const struct dcn_hubbub_mask hubbub_mask = {
546 HUBBUB_MASK_SH_LIST_DCN21(_MASK)
547};
548
549
550#define vmid_regs(id)\
551[id] = {\
552 DCN20_VMID_REG_LIST(id)\
553}
554
555static const struct dcn_vmid_registers vmid_regs[] = {
556 vmid_regs(0),
557 vmid_regs(1),
558 vmid_regs(2),
559 vmid_regs(3),
560 vmid_regs(4),
561 vmid_regs(5),
562 vmid_regs(6),
563 vmid_regs(7),
564 vmid_regs(8),
565 vmid_regs(9),
566 vmid_regs(10),
567 vmid_regs(11),
568 vmid_regs(12),
569 vmid_regs(13),
570 vmid_regs(14),
571 vmid_regs(15)
572};
573
574static const struct dcn20_vmid_shift vmid_shifts = {
575 DCN20_VMID_MASK_SH_LIST(__SHIFT)
576};
577
578static const struct dcn20_vmid_mask vmid_masks = {
579 DCN20_VMID_MASK_SH_LIST(_MASK)
580};
581
6f4e6361
BL		 582#define dsc_regsDCN20(id)\
583[id] = {\
584 DSC_REG_LIST_DCN20(id)\
585}
586
587static const struct dcn20_dsc_registers dsc_regs[] = {
588 dsc_regsDCN20(0),
589 dsc_regsDCN20(1),
590 dsc_regsDCN20(2),
591 dsc_regsDCN20(3),
592 dsc_regsDCN20(4),
593 dsc_regsDCN20(5)
594};
595
596static const struct dcn20_dsc_shift dsc_shift = {
597 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
598};
599
600static const struct dcn20_dsc_mask dsc_mask = {
601 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
602};
6f4e6361
BL		 603
604#define ipp_regs(id)\
605[id] = {\
606 IPP_REG_LIST_DCN20(id),\
607}
608
609static const struct dcn10_ipp_registers ipp_regs[] = {
610 ipp_regs(0),
611 ipp_regs(1),
612 ipp_regs(2),
613 ipp_regs(3),
614};
615
616static const struct dcn10_ipp_shift ipp_shift = {
617 IPP_MASK_SH_LIST_DCN20(__SHIFT)
618};
619
620static const struct dcn10_ipp_mask ipp_mask = {
621 IPP_MASK_SH_LIST_DCN20(_MASK),
622};
623
624#define opp_regs(id)\
625[id] = {\
626 OPP_REG_LIST_DCN20(id),\
627}
628
629
630#define aux_engine_regs(id)\
631[id] = {\
632 AUX_COMMON_REG_LIST0(id), \
633 .AUXN_IMPCAL = 0, \
634 .AUXP_IMPCAL = 0, \
635 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
636}
637
638static const struct dce110_aux_registers aux_engine_regs[] = {
639 aux_engine_regs(0),
640 aux_engine_regs(1),
641 aux_engine_regs(2),
642 aux_engine_regs(3),
643 aux_engine_regs(4),
644};
645
646#define tf_regs(id)\
647[id] = {\
648 TF_REG_LIST_DCN20(id),\
d9eb70ae 649 TF_REG_LIST_DCN20_COMMON_APPEND(id),\
6f4e6361
BL		 650}
651
652static const struct dcn2_dpp_registers tf_regs[] = {
653 tf_regs(0),
654 tf_regs(1),
655 tf_regs(2),
656 tf_regs(3),
657};
658
659static const struct dcn2_dpp_shift tf_shift = {
d9eb70ae 660 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
c1e34175 661 TF_DEBUG_REG_LIST_SH_DCN20
6f4e6361
BL		 662};
663
664static const struct dcn2_dpp_mask tf_mask = {
d9eb70ae 665 TF_REG_LIST_SH_MASK_DCN20(_MASK),
c1e34175 666 TF_DEBUG_REG_LIST_MASK_DCN20
6f4e6361
BL		 667};
668
669#define stream_enc_regs(id)\
670[id] = {\
671 SE_DCN2_REG_LIST(id)\
672}
673
674static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
675 stream_enc_regs(0),
676 stream_enc_regs(1),
677 stream_enc_regs(2),
678 stream_enc_regs(3),
679 stream_enc_regs(4),
680};
681
8276dd87 682static const struct dce110_aux_registers_shift aux_shift = {
683 DCN_AUX_MASK_SH_LIST(__SHIFT)
684};
685
686static const struct dce110_aux_registers_mask aux_mask = {
687 DCN_AUX_MASK_SH_LIST(_MASK)
688};
689
6f4e6361
BL		 690static const struct dcn10_stream_encoder_shift se_shift = {
691 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
692};
693
694static const struct dcn10_stream_encoder_mask se_mask = {
695 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
696};
697
44e149bb
AD		 698static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
699
8c357309 700static int dcn21_populate_dml_pipes_from_context(
2f488884 701 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes);
8c357309 702
6f4e6361
BL		 703static struct input_pixel_processor *dcn21_ipp_create(
704 struct dc_context *ctx, uint32_t inst)
705{
706 struct dcn10_ipp *ipp =
707 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
708
709 if (!ipp) {
710 BREAK_TO_DEBUGGER();
711 return NULL;
712 }
713
714 dcn20_ipp_construct(ipp, ctx, inst,
715 &ipp_regs[inst], &ipp_shift, &ipp_mask);
716 return &ipp->base;
717}
718
719static struct dpp *dcn21_dpp_create(
720 struct dc_context *ctx,
721 uint32_t inst)
722{
723 struct dcn20_dpp *dpp =
724 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
725
726 if (!dpp)
727 return NULL;
728
729 if (dpp2_construct(dpp, ctx, inst,
730 &tf_regs[inst], &tf_shift, &tf_mask))
731 return &dpp->base;
732
733 BREAK_TO_DEBUGGER();
734 kfree(dpp);
735 return NULL;
736}
737
738static struct dce_aux *dcn21_aux_engine_create(
739 struct dc_context *ctx,
740 uint32_t inst)
741{
742 struct aux_engine_dce110 *aux_engine =
743 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
744
745 if (!aux_engine)
746 return NULL;
747
748 dce110_aux_engine_construct(aux_engine, ctx, inst,
749 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
8276dd87 750 &aux_engine_regs[inst],
751 &aux_mask,
f6040a43 752 &aux_shift,
753 ctx->dc->caps.extended_aux_timeout_support);
6f4e6361
BL		 754
755 return &aux_engine->base;
756}
757
758#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
759
760static const struct dce_i2c_registers i2c_hw_regs[] = {
761 i2c_inst_regs(1),
762 i2c_inst_regs(2),
763 i2c_inst_regs(3),
764 i2c_inst_regs(4),
765 i2c_inst_regs(5),
766};
767
768static const struct dce_i2c_shift i2c_shifts = {
769 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
770};
771
772static const struct dce_i2c_mask i2c_masks = {
773 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
774};
775
776struct dce_i2c_hw *dcn21_i2c_hw_create(
777 struct dc_context *ctx,
778 uint32_t inst)
779{
780 struct dce_i2c_hw *dce_i2c_hw =
781 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
782
783 if (!dce_i2c_hw)
784 return NULL;
785
786 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
787 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
788
789 return dce_i2c_hw;
790}
791
792static const struct resource_caps res_cap_rn = {
793 .num_timing_generator = 4,
794 .num_opp = 4,
795 .num_video_plane = 4,
b356843e 796 .num_audio = 4, // 4 audio endpoints. 4 audio streams
6f4e6361
BL		 797 .num_stream_encoder = 5,
798 .num_pll = 5, // maybe 3 because the last two used for USB-c
799 .num_dwb = 1,
800 .num_ddc = 5,
652651ff 801 .num_vmid = 1,
6f4e6361 802 .num_dsc = 3,
6f4e6361
BL		 803};
804
805#ifdef DIAGS_BUILD
806static const struct resource_caps res_cap_rn_FPGA_4pipe = {
807 .num_timing_generator = 4,
808 .num_opp = 4,
809 .num_video_plane = 4,
810 .num_audio = 7,
811 .num_stream_encoder = 4,
812 .num_pll = 4,
813 .num_dwb = 1,
814 .num_ddc = 4,
815 .num_dsc = 0,
816};
817
818static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
819 .num_timing_generator = 2,
820 .num_opp = 2,
821 .num_video_plane = 2,
822 .num_audio = 7,
823 .num_stream_encoder = 2,
824 .num_pll = 4,
825 .num_dwb = 1,
826 .num_ddc = 4,
6f4e6361 827 .num_dsc = 2,
6f4e6361
BL		 828};
829#endif
830
831static const struct dc_plane_cap plane_cap = {
832 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
833 .blends_with_above = true,
834 .blends_with_below = true,
835 .per_pixel_alpha = true,
836
837 .pixel_format_support = {
838 .argb8888 = true,
839 .nv12 = true,
840 .fp16 = true
841 },
842
843 .max_upscale_factor = {
844 .argb8888 = 16000,
845 .nv12 = 16000,
846 .fp16 = 16000
847 },
848
849 .max_downscale_factor = {
850 .argb8888 = 250,
851 .nv12 = 250,
852 .fp16 = 250
853 }
854};
855
856static const struct dc_debug_options debug_defaults_drv = {
857 .disable_dmcu = true,
858 .force_abm_enable = false,
859 .timing_trace = false,
860 .clock_trace = true,
861 .disable_pplib_clock_request = true,
862 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
4d25a0d5 863 .force_single_disp_pipe_split = false,
6f4e6361
BL		 864 .disable_dcc = DCC_ENABLE,
865 .vsr_support = true,
866 .performance_trace = false,
947daab2 867 .max_downscale_src_width = 4096,
6f4e6361
BL		 868 .disable_pplib_wm_range = false,
869 .scl_reset_length10 = true,
870 .sanity_checks = true,
57133a28 871 .disable_48mhz_pwrdwn = false,
ee765924
GS		 872 .nv12_iflip_vm_wa = true,
873 .usbc_combo_phy_reset_wa = true
6f4e6361
BL		 874};
875
876static const struct dc_debug_options debug_defaults_diags = {
877 .disable_dmcu = true,
878 .force_abm_enable = false,
879 .timing_trace = true,
880 .clock_trace = true,
881 .disable_dpp_power_gate = true,
882 .disable_hubp_power_gate = true,
883 .disable_clock_gate = true,
884 .disable_pplib_clock_request = true,
885 .disable_pplib_wm_range = true,
886 .disable_stutter = true,
887 .disable_48mhz_pwrdwn = true,
888};
889
890enum dcn20_clk_src_array_id {
891 DCN20_CLK_SRC_PLL0,
892 DCN20_CLK_SRC_PLL1,
15add0c2 893 DCN20_CLK_SRC_PLL2,
6f4e6361
BL		 894 DCN20_CLK_SRC_TOTAL_DCN21
895};
896
d9e32672 897static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
6f4e6361
BL		 898{
899 unsigned int i;
900
901 for (i = 0; i < pool->base.stream_enc_count; i++) {
902 if (pool->base.stream_enc[i] != NULL) {
903 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
904 pool->base.stream_enc[i] = NULL;
905 }
906 }
907
6f4e6361
BL		 908 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
909 if (pool->base.dscs[i] != NULL)
910 dcn20_dsc_destroy(&pool->base.dscs[i]);
911 }
6f4e6361
BL		 912
913 if (pool->base.mpc != NULL) {
914 kfree(TO_DCN20_MPC(pool->base.mpc));
915 pool->base.mpc = NULL;
916 }
917 if (pool->base.hubbub != NULL) {
918 kfree(pool->base.hubbub);
919 pool->base.hubbub = NULL;
920 }
921 for (i = 0; i < pool->base.pipe_count; i++) {
922 if (pool->base.dpps[i] != NULL)
923 dcn20_dpp_destroy(&pool->base.dpps[i]);
924
925 if (pool->base.ipps[i] != NULL)
926 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
927
928 if (pool->base.hubps[i] != NULL) {
929 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
930 pool->base.hubps[i] = NULL;
931 }
932
933 if (pool->base.irqs != NULL) {
934 dal_irq_service_destroy(&pool->base.irqs);
935 }
936 }
937
938 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
939 if (pool->base.engines[i] != NULL)
940 dce110_engine_destroy(&pool->base.engines[i]);
941 if (pool->base.hw_i2cs[i] != NULL) {
942 kfree(pool->base.hw_i2cs[i]);
943 pool->base.hw_i2cs[i] = NULL;
944 }
945 if (pool->base.sw_i2cs[i] != NULL) {
946 kfree(pool->base.sw_i2cs[i]);
947 pool->base.sw_i2cs[i] = NULL;
948 }
949 }
950
951 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
952 if (pool->base.opps[i] != NULL)
953 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
954 }
955
956 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
957 if (pool->base.timing_generators[i] != NULL) {
958 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
959 pool->base.timing_generators[i] = NULL;
960 }
961 }
962
963 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
964 if (pool->base.dwbc[i] != NULL) {
965 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
966 pool->base.dwbc[i] = NULL;
967 }
968 if (pool->base.mcif_wb[i] != NULL) {
969 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
970 pool->base.mcif_wb[i] = NULL;
971 }
972 }
973
974 for (i = 0; i < pool->base.audio_count; i++) {
975 if (pool->base.audios[i])
976 dce_aud_destroy(&pool->base.audios[i]);
977 }
978
979 for (i = 0; i < pool->base.clk_src_count; i++) {
980 if (pool->base.clock_sources[i] != NULL) {
981 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
982 pool->base.clock_sources[i] = NULL;
983 }
984 }
985
986 if (pool->base.dp_clock_source != NULL) {
987 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
988 pool->base.dp_clock_source = NULL;
989 }
990
991
992 if (pool->base.abm != NULL)
993 dce_abm_destroy(&pool->base.abm);
994
995 if (pool->base.dmcu != NULL)
996 dce_dmcu_destroy(&pool->base.dmcu);
997
9dac88d8
WW		 998 if (pool->base.psr != NULL)
999 dmub_psr_destroy(&pool->base.psr);
1000
6f4e6361
BL		 1001 if (pool->base.dccg != NULL)
1002 dcn_dccg_destroy(&pool->base.dccg);
1003
1004 if (pool->base.pp_smu != NULL)
44e149bb 1005 dcn21_pp_smu_destroy(&pool->base.pp_smu);
6f4e6361
BL		 1006}
1007
1008
1009static void calculate_wm_set_for_vlevel(
1010 int vlevel,
1011 struct wm_range_table_entry *table_entry,
1012 struct dcn_watermarks *wm_set,
1013 struct display_mode_lib *dml,
1014 display_e2e_pipe_params_st *pipes,
1015 int pipe_cnt)
1016{
1017 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
1018
1019 ASSERT(vlevel < dml->soc.num_states);
1020 /* only pipe 0 is read for voltage and dcf/soc clocks */
1021 pipes[0].clks_cfg.voltage = vlevel;
1022 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
1023 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
1024
1025 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
d3511fd0
EY		 1026 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
1027 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
6f4e6361
BL		 1028
1029 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
1030 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
1031 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
1032 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1033 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
6f4e6361
BL		 1034 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
1035 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
b617b265 1036 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
6f4e6361
BL		 1037 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
1038
1039}
1040
15fdbcc5
LH		 1041static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
1042{
d3511fd0
EY		 1043 int i;
1044
6ca3928d
TP		 1045 DC_FP_START();
1046
15fdbcc5 1047 if (dc->bb_overrides.sr_exit_time_ns) {
d3511fd0
EY		 1048 for (i = 0; i < WM_SET_COUNT; i++) {
1049 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
1050 dc->bb_overrides.sr_exit_time_ns / 1000.0;
1051 }
15fdbcc5
LH		 1052 }
1053
1054 if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
d3511fd0
EY		 1055 for (i = 0; i < WM_SET_COUNT; i++) {
1056 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
1057 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
1058 }
15fdbcc5
LH		 1059 }
1060
1061 if (dc->bb_overrides.urgent_latency_ns) {
1062 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
1063 }
1064
1065 if (dc->bb_overrides.dram_clock_change_latency_ns) {
580c8be2
JG		 1066 for (i = 0; i < WM_SET_COUNT; i++) {
1067 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
15fdbcc5 1068 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
580c8be2 1069 }
15fdbcc5 1070 }
580c8be2 1071
6ca3928d 1072 DC_FP_END();
15fdbcc5
LH		 1073}
1074
6f4e6361
BL		 1075void dcn21_calculate_wm(
1076 struct dc *dc, struct dc_state *context,
1077 display_e2e_pipe_params_st *pipes,
1078 int *out_pipe_cnt,
1079 int *pipe_split_from,
1080 int vlevel_req)
1081{
1082 int pipe_cnt, i, pipe_idx;
1083 int vlevel, vlevel_max;
1084 struct wm_range_table_entry *table_entry;
1085 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
1086
1087 ASSERT(bw_params);
1088
15fdbcc5
LH		 1089 patch_bounding_box(dc, &context->bw_ctx.dml.soc);
1090
6f4e6361
BL		 1091 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1092 if (!context->res_ctx.pipe_ctx[i].stream)
1093 continue;
1094
1095 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1096 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
1097
1098 if (pipe_split_from[i] < 0) {
1099 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1100 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1101 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1102 pipes[pipe_cnt].pipe.dest.odm_combine =
1103 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
1104 else
1105 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1106 pipe_idx++;
1107 } else {
1108 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1109 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1110 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1111 pipes[pipe_cnt].pipe.dest.odm_combine =
1112 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];
1113 else
1114 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1115 }
1116 pipe_cnt++;
1117 }
1118
1119 if (pipe_cnt != pipe_idx) {
1120 if (dc->res_pool->funcs->populate_dml_pipes)
1121 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2f488884 1122 context, pipes);
6f4e6361 1123 else
8c357309 1124 pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
2f488884 1125 context, pipes);
6f4e6361
BL		 1126 }
1127
1128 *out_pipe_cnt = pipe_cnt;
1129
1130 vlevel_max = bw_params->clk_table.num_entries - 1;
1131
1132
1133 /* WM Set D */
1134 table_entry = &bw_params->wm_table.entries[WM_D];
1135 if (table_entry->wm_type == WM_TYPE_RETRAINING)
1136 vlevel = 0;
1137 else
1138 vlevel = vlevel_max;
1139 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
1140 &context->bw_ctx.dml, pipes, pipe_cnt);
1141 /* WM Set C */
1142 table_entry = &bw_params->wm_table.entries[WM_C];
1143 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
1144 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
1145 &context->bw_ctx.dml, pipes, pipe_cnt);
1146 /* WM Set B */
1147 table_entry = &bw_params->wm_table.entries[WM_B];
1148 vlevel = MIN(MAX(vlevel_req, 1), vlevel_max);
1149 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
1150 &context->bw_ctx.dml, pipes, pipe_cnt);
1151
1152 /* WM Set A */
1153 table_entry = &bw_params->wm_table.entries[WM_A];
1154 vlevel = MIN(vlevel_req, vlevel_max);
1155 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
1156 &context->bw_ctx.dml, pipes, pipe_cnt);
1157}
1158
1159
1160bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
1161 bool fast_validate)
1162{
1163 bool out = false;
1164
1165 BW_VAL_TRACE_SETUP();
1166
1167 int vlevel = 0;
1168 int pipe_split_from[MAX_PIPES];
1169 int pipe_cnt = 0;
1170 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1171 DC_LOGGER_INIT(dc->ctx->logger);
1172
1173 BW_VAL_TRACE_COUNT();
1174
1175 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
1176
1177 if (pipe_cnt == 0)
1178 goto validate_out;
1179
1180 if (!out)
1181 goto validate_fail;
1182
1183 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1184
1185 if (fast_validate) {
1186 BW_VAL_TRACE_SKIP(fast);
1187 goto validate_out;
1188 }
1189
1190 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
1191 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1192
1193 BW_VAL_TRACE_END_WATERMARKS();
1194
1195 goto validate_out;
1196
1197validate_fail:
1198 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1199 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1200
1201 BW_VAL_TRACE_SKIP(fail);
1202 out = false;
1203
1204validate_out:
1205 kfree(pipes);
1206
1207 BW_VAL_TRACE_FINISH();
1208
1209 return out;
1210}
1211static void dcn21_destroy_resource_pool(struct resource_pool **pool)
1212{
1213 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
1214
d9e32672 1215 dcn21_resource_destruct(dcn21_pool);
6f4e6361
BL		 1216 kfree(dcn21_pool);
1217 *pool = NULL;
1218}
1219
1220static struct clock_source *dcn21_clock_source_create(
1221 struct dc_context *ctx,
1222 struct dc_bios *bios,
1223 enum clock_source_id id,
1224 const struct dce110_clk_src_regs *regs,
1225 bool dp_clk_src)
1226{
1227 struct dce110_clk_src *clk_src =
1228 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1229
1230 if (!clk_src)
1231 return NULL;
1232
1233 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1234 regs, &cs_shift, &cs_mask)) {
1235 clk_src->base.dp_clk_src = dp_clk_src;
1236 return &clk_src->base;
1237 }
1238
1239 BREAK_TO_DEBUGGER();
1240 return NULL;
1241}
1242
1243static struct hubp *dcn21_hubp_create(
1244 struct dc_context *ctx,
1245 uint32_t inst)
1246{
1247 struct dcn21_hubp *hubp21 =
1248 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);
1249
1250 if (!hubp21)
1251 return NULL;
1252
1253 if (hubp21_construct(hubp21, ctx, inst,
1254 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1255 return &hubp21->base;
1256
1257 BREAK_TO_DEBUGGER();
1258 kfree(hubp21);
1259 return NULL;
1260}
1261
1262static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
1263{
1264 int i;
1265
1266 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1267 GFP_KERNEL);
1268
1269 if (!hubbub)
1270 return NULL;
1271
1272 hubbub21_construct(hubbub, ctx,
1273 &hubbub_reg,
1274 &hubbub_shift,
1275 &hubbub_mask);
1276
1277 for (i = 0; i < res_cap_rn.num_vmid; i++) {
1278 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1279
1280 vmid->ctx = ctx;
1281
1282 vmid->regs = &vmid_regs[i];
1283 vmid->shifts = &vmid_shifts;
1284 vmid->masks = &vmid_masks;
1285 }
1286
1287 return &hubbub->base;
1288}
1289
1290struct output_pixel_processor *dcn21_opp_create(
1291 struct dc_context *ctx, uint32_t inst)
1292{
1293 struct dcn20_opp *opp =
1294 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1295
1296 if (!opp) {
1297 BREAK_TO_DEBUGGER();
1298 return NULL;
1299 }
1300
1301 dcn20_opp_construct(opp, ctx, inst,
1302 &opp_regs[inst], &opp_shift, &opp_mask);
1303 return &opp->base;
1304}
1305
1306struct timing_generator *dcn21_timing_generator_create(
1307 struct dc_context *ctx,
1308 uint32_t instance)
1309{
1310 struct optc *tgn10 =
1311 kzalloc(sizeof(struct optc), GFP_KERNEL);
1312
1313 if (!tgn10)
1314 return NULL;
1315
1316 tgn10->base.inst = instance;
1317 tgn10->base.ctx = ctx;
1318
1319 tgn10->tg_regs = &tg_regs[instance];
1320 tgn10->tg_shift = &tg_shift;
1321 tgn10->tg_mask = &tg_mask;
1322
1323 dcn20_timing_generator_init(tgn10);
1324
1325 return &tgn10->base;
1326}
1327
1328struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1329{
1330 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1331 GFP_KERNEL);
1332
1333 if (!mpc20)
1334 return NULL;
1335
1336 dcn20_mpc_construct(mpc20, ctx,
1337 &mpc_regs,
1338 &mpc_shift,
1339 &mpc_mask,
1340 6);
1341
1342 return &mpc20->base;
1343}
1344
1345static void read_dce_straps(
1346 struct dc_context *ctx,
1347 struct resource_straps *straps)
1348{
1349 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1350 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1351
1352}
1353
6f4e6361
BL		 1354
1355struct display_stream_compressor *dcn21_dsc_create(
1356 struct dc_context *ctx, uint32_t inst)
1357{
1358 struct dcn20_dsc *dsc =
1359 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1360
1361 if (!dsc) {
1362 BREAK_TO_DEBUGGER();
1363 return NULL;
1364 }
1365
1366 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1367 return &dsc->base;
1368}
6f4e6361
BL		 1369
1370static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1371{
1372 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
1373 struct clk_limit_table *clk_table = &bw_params->clk_table;
a39a5816
EY		 1374 unsigned int i, j, k;
1375 int closest_clk_lvl;
1376
1377 // diags does not retrieve proper values from SMU
1378 // cap states to 5 and make state 5 the max state
1379 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) || IS_DIAG_DC(dc->ctx->dce_environment)) {
1380 dcn2_1_soc.num_states = 5;
1381
1382 dcn2_1_soc.clock_limits[5].state = 5;
1383 dcn2_1_soc.clock_limits[5].dcfclk_mhz = 810.0;
1384 dcn2_1_soc.clock_limits[5].fabricclk_mhz = 1600.0;
1385 dcn2_1_soc.clock_limits[5].dispclk_mhz = 1395.0;
1386 dcn2_1_soc.clock_limits[5].dppclk_mhz = 1285.0;
1387 dcn2_1_soc.clock_limits[5].phyclk_mhz = 1325.0;
1388 dcn2_1_soc.clock_limits[5].socclk_mhz = 953.0;
1389 dcn2_1_soc.clock_limits[5].dscclk_mhz = 489.0;
1390 dcn2_1_soc.clock_limits[5].dram_speed_mts = 4266.0;
1391 } else {
1392 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1393 dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
1394 dcn2_1_soc.num_chans = bw_params->num_channels;
1395
1396 /* Vmin: leave lowest DCN clocks, override with dcfclk, fclk, memclk from fuse */
1397 dcn2_1_soc.clock_limits[0].state = 0;
1398 dcn2_1_soc.clock_limits[0].dcfclk_mhz = clk_table->entries[0].dcfclk_mhz;
1399 dcn2_1_soc.clock_limits[0].fabricclk_mhz = clk_table->entries[0].fclk_mhz;
1400 dcn2_1_soc.clock_limits[0].socclk_mhz = clk_table->entries[0].socclk_mhz;
1401 dcn2_1_soc.clock_limits[0].dram_speed_mts = clk_table->entries[0].memclk_mhz * 2;
1402
1403 /*
1404 * Other levels: find cloest DCN clocks that fit the given clock limit using dcfclk
1405 * as indicater
1406 */
1407
1408 closest_clk_lvl = -1;
1409 /* index currently being filled */
1410 k = 1;
1411 for (i = 1; i < clk_table->num_entries; i++) {
1412 /* loop backwards, skip duplicate state, +1 because SMU has precision issue */
1413 for (j = dcn2_1_soc.num_states - 2; j >= k; j--) {
1414 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
1415 closest_clk_lvl = j;
1416 break;
1417 }
1418 }
6f4e6361 1419
a39a5816
EY		 1420 /* if found a lvl that fits, use the DCN clks from it, if not, go to next clk limit*/
1421 if (closest_clk_lvl != -1) {
1422 dcn2_1_soc.clock_limits[k].state = i;
1423 dcn2_1_soc.clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
1424 dcn2_1_soc.clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
1425 dcn2_1_soc.clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
1426 dcn2_1_soc.clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
1427
1428 dcn2_1_soc.clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
1429 dcn2_1_soc.clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
1430 dcn2_1_soc.clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
1431 dcn2_1_soc.clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
1432 dcn2_1_soc.clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
1433 dcn2_1_soc.clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
1434 dcn2_1_soc.clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
1435 k++;
1436 }
1437 }
6f4e6361 1438
a39a5816
EY		 1439 /* duplicate last level */
1440 dcn2_1_soc.clock_limits[k] = dcn2_1_soc.clock_limits[k - 1];
1441 dcn2_1_soc.clock_limits[k].state = k;
1442 dcn2_1_soc.num_states = k + 1;
6f4e6361 1443 }
08f6c859 1444
a39a5816 1445 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
6f4e6361
BL		 1446}
1447
1448/* Temporary Place holder until we can get them from fuse */
1449static struct dpm_clocks dummy_clocks = {
1450 .DcfClocks = {
1451 {.Freq = 400, .Vol = 1},
1452 {.Freq = 483, .Vol = 1},
1453 {.Freq = 602, .Vol = 1},
1454 {.Freq = 738, .Vol = 1} },
1455 .SocClocks = {
1456 {.Freq = 300, .Vol = 1},
1457 {.Freq = 400, .Vol = 1},
1458 {.Freq = 400, .Vol = 1},
1459 {.Freq = 400, .Vol = 1} },
1460 .FClocks = {
1461 {.Freq = 400, .Vol = 1},
1462 {.Freq = 800, .Vol = 1},
1463 {.Freq = 1067, .Vol = 1},
1464 {.Freq = 1600, .Vol = 1} },
1465 .MemClocks = {
1466 {.Freq = 800, .Vol = 1},
1467 {.Freq = 1600, .Vol = 1},
1468 {.Freq = 1067, .Vol = 1},
1469 {.Freq = 1600, .Vol = 1} },
1470
1471};
1472
976035dd 1473static enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp,
6f4e6361
BL		 1474 struct pp_smu_wm_range_sets *ranges)
1475{
1476 return PP_SMU_RESULT_OK;
1477}
1478
976035dd 1479static enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp,
6f4e6361
BL		 1480 struct dpm_clocks *clock_table)
1481{
1482 *clock_table = dummy_clocks;
1483 return PP_SMU_RESULT_OK;
1484}
1485
976035dd 1486static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
6f4e6361
BL		 1487{
1488 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
1489
a51894f0
EY		 1490 if (!pp_smu)
1491 return pp_smu;
6f4e6361 1492
3794943c 1493 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment) || IS_DIAG_DC(ctx->dce_environment)) {
a51894f0
EY		 1494 pp_smu->ctx.ver = PP_SMU_VER_RN;
1495 pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table;
1496 pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges;
1497 } else {
1498
1499 dm_pp_get_funcs(ctx, pp_smu);
1500
1501 if (pp_smu->ctx.ver != PP_SMU_VER_RN)
1502 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
1503 }
6f4e6361
BL		 1504
1505 return pp_smu;
1506}
1507
976035dd 1508static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
6f4e6361
BL		 1509{
1510 if (pp_smu && *pp_smu) {
1511 kfree(*pp_smu);
1512 *pp_smu = NULL;
1513 }
1514}
1515
1516static struct audio *dcn21_create_audio(
1517 struct dc_context *ctx, unsigned int inst)
1518{
1519 return dce_audio_create(ctx, inst,
1520 &audio_regs[inst], &audio_shift, &audio_mask);
1521}
1522
1523static struct dc_cap_funcs cap_funcs = {
1524 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1525};
1526
1527struct stream_encoder *dcn21_stream_encoder_create(
1528 enum engine_id eng_id,
1529 struct dc_context *ctx)
1530{
1531 struct dcn10_stream_encoder *enc1 =
1532 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1533
1534 if (!enc1)
1535 return NULL;
1536
1537 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1538 &stream_enc_regs[eng_id],
1539 &se_shift, &se_mask);
1540
1541 return &enc1->base;
1542}
1543
1544static const struct dce_hwseq_registers hwseq_reg = {
1545 HWSEQ_DCN21_REG_LIST()
1546};
1547
1548static const struct dce_hwseq_shift hwseq_shift = {
1549 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
1550};
1551
1552static const struct dce_hwseq_mask hwseq_mask = {
1553 HWSEQ_DCN21_MASK_SH_LIST(_MASK)
1554};
1555
1556static struct dce_hwseq *dcn21_hwseq_create(
1557 struct dc_context *ctx)
1558{
1559 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1560
1561 if (hws) {
1562 hws->ctx = ctx;
1563 hws->regs = &hwseq_reg;
1564 hws->shifts = &hwseq_shift;
1565 hws->masks = &hwseq_mask;
f93e29f0 1566 hws->wa.DEGVIDCN21 = true;
d9758768 1567 hws->wa.disallow_self_refresh_during_multi_plane_transition = true;
6f4e6361
BL		 1568 }
1569 return hws;
1570}
1571
1572static const struct resource_create_funcs res_create_funcs = {
1573 .read_dce_straps = read_dce_straps,
1574 .create_audio = dcn21_create_audio,
1575 .create_stream_encoder = dcn21_stream_encoder_create,
1576 .create_hwseq = dcn21_hwseq_create,
1577};
1578
1579static const struct resource_create_funcs res_create_maximus_funcs = {
1580 .read_dce_straps = NULL,
1581 .create_audio = NULL,
1582 .create_stream_encoder = NULL,
1583 .create_hwseq = dcn21_hwseq_create,
1584};
1585
91c665bd
BL		 1586static const struct encoder_feature_support link_enc_feature = {
1587 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1588 .max_hdmi_pixel_clock = 600000,
1589 .hdmi_ycbcr420_supported = true,
1590 .dp_ycbcr420_supported = true,
1591 .flags.bits.IS_HBR2_CAPABLE = true,
1592 .flags.bits.IS_HBR3_CAPABLE = true,
1593 .flags.bits.IS_TPS3_CAPABLE = true,
1594 .flags.bits.IS_TPS4_CAPABLE = true
1595};
1596
1597
1598#define link_regs(id, phyid)\
1599[id] = {\
a771ded8 1600 LE_DCN2_REG_LIST(id), \
91c665bd 1601 UNIPHY_DCN2_REG_LIST(phyid), \
a771ded8 1602 DPCS_DCN21_REG_LIST(id), \
91c665bd
BL		 1603 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
1604}
1605
1606static const struct dcn10_link_enc_registers link_enc_regs[] = {
1607 link_regs(0, A),
1608 link_regs(1, B),
1609 link_regs(2, C),
1610 link_regs(3, D),
1611 link_regs(4, E),
1612};
1613
1614#define aux_regs(id)\
1615[id] = {\
1616 DCN2_AUX_REG_LIST(id)\
1617}
1618
1619static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1620 aux_regs(0),
1621 aux_regs(1),
1622 aux_regs(2),
1623 aux_regs(3),
1624 aux_regs(4)
1625};
1626
1627#define hpd_regs(id)\
1628[id] = {\
1629 HPD_REG_LIST(id)\
1630}
1631
1632static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1633 hpd_regs(0),
1634 hpd_regs(1),
1635 hpd_regs(2),
1636 hpd_regs(3),
1637 hpd_regs(4)
1638};
1639
1640static const struct dcn10_link_enc_shift le_shift = {
a771ded8
RL		 1641 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
1642 DPCS_DCN21_MASK_SH_LIST(__SHIFT)
91c665bd
BL		 1643};
1644
1645static const struct dcn10_link_enc_mask le_mask = {
a771ded8
RL		 1646 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
1647 DPCS_DCN21_MASK_SH_LIST(_MASK)
91c665bd
BL		 1648};
1649
bf7f5ac3
YMM		 1650static int map_transmitter_id_to_phy_instance(
1651 enum transmitter transmitter)
1652{
1653 switch (transmitter) {
1654 case TRANSMITTER_UNIPHY_A:
1655 return 0;
1656 break;
1657 case TRANSMITTER_UNIPHY_B:
1658 return 1;
1659 break;
1660 case TRANSMITTER_UNIPHY_C:
1661 return 2;
1662 break;
1663 case TRANSMITTER_UNIPHY_D:
1664 return 3;
1665 break;
1666 case TRANSMITTER_UNIPHY_E:
1667 return 4;
1668 break;
1669 default:
1670 ASSERT(0);
1671 return 0;
1672 }
1673}
1674
91c665bd
BL		 1675static struct link_encoder *dcn21_link_encoder_create(
1676 const struct encoder_init_data *enc_init_data)
1677{
1678 struct dcn21_link_encoder *enc21 =
1679 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
bf7f5ac3 1680 int link_regs_id;
91c665bd
BL		 1681
1682 if (!enc21)
1683 return NULL;
1684
bf7f5ac3
YMM		 1685 link_regs_id =
1686 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1687
91c665bd
BL		 1688 dcn21_link_encoder_construct(enc21,
1689 enc_init_data,
1690 &link_enc_feature,
bf7f5ac3 1691 &link_enc_regs[link_regs_id],
91c665bd
BL		 1692 &link_enc_aux_regs[enc_init_data->channel - 1],
1693 &link_enc_hpd_regs[enc_init_data->hpd_source],
1694 &le_shift,
1695 &le_mask);
1696
1697 return &enc21->enc10.base;
1698}
c0fb59a4
BL		 1699#define CTX ctx
1700
1701#define REG(reg_name) \
1702 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1703
1704static uint32_t read_pipe_fuses(struct dc_context *ctx)
1705{
1706 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1707 /* RV1 support max 4 pipes */
1708 value = value & 0xf;
1709 return value;
1710}
1711
8c357309 1712static int dcn21_populate_dml_pipes_from_context(
2f488884 1713 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)
8c357309 1714{
2f488884 1715 uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes);
8c357309 1716 int i;
2f488884 1717 struct resource_context *res_ctx = &context->res_ctx;
8c357309
YS		 1718
1719 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1720
1721 if (!res_ctx->pipe_ctx[i].stream)
1722 continue;
1723
1724 pipes[i].pipe.src.hostvm = 1;
1725 pipes[i].pipe.src.gpuvm = 1;
1726 }
1727
1728 return pipe_cnt;
1729}
1730
6f4e6361
BL		 1731static struct resource_funcs dcn21_res_pool_funcs = {
1732 .destroy = dcn21_destroy_resource_pool,
91c665bd 1733 .link_enc_create = dcn21_link_encoder_create,
6f4e6361 1734 .validate_bandwidth = dcn21_validate_bandwidth,
8c357309 1735 .populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
6f4e6361
BL		 1736 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
1737 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1738 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1739 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
1740 .get_default_swizzle_mode = dcn20_get_default_swizzle_mode,
1741 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1742 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1743 .update_bw_bounding_box = update_bw_bounding_box
1744};
1745
d9e32672 1746static bool dcn21_resource_construct(
6f4e6361
BL		 1747 uint8_t num_virtual_links,
1748 struct dc *dc,
1749 struct dcn21_resource_pool *pool)
1750{
c0fb59a4 1751 int i, j;
6f4e6361
BL		 1752 struct dc_context *ctx = dc->ctx;
1753 struct irq_service_init_data init_data;
c0fb59a4 1754 uint32_t pipe_fuses = read_pipe_fuses(ctx);
ff86391e 1755 uint32_t num_pipes;
6f4e6361
BL		 1756
1757 ctx->dc_bios->regs = &bios_regs;
1758
1759 pool->base.res_cap = &res_cap_rn;
1760#ifdef DIAGS_BUILD
1761 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1762 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc;
1763 pool->base.res_cap = &res_cap_rn_FPGA_4pipe;
1764#endif
1765
1766 pool->base.funcs = &dcn21_res_pool_funcs;
1767
1768 /*************************************************
1769 * Resource + asic cap harcoding *
1770 *************************************************/
1771 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1772
c0fb59a4
BL		 1773 /* max pipe num for ASIC before check pipe fuses */
1774 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1775
6f4e6361
BL		 1776 dc->caps.max_downscale_ratio = 200;
1777 dc->caps.i2c_speed_in_khz = 100;
1778 dc->caps.max_cursor_size = 256;
1779 dc->caps.dmdata_alloc_size = 2048;
1780 dc->caps.hw_3d_lut = true;
1781
1782 dc->caps.max_slave_planes = 1;
1783 dc->caps.post_blend_color_processing = true;
1784 dc->caps.force_dp_tps4_for_cp2520 = true;
ca4f844e 1785 dc->caps.extended_aux_timeout_support = true;
3a1627b0 1786 dc->caps.dmcub_support = true;
6f4e6361
BL		 1787
1788 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1789 dc->debug = debug_defaults_drv;
1790 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1791 pool->base.pipe_count = 4;
1792 dc->debug = debug_defaults_diags;
1793 } else
1794 dc->debug = debug_defaults_diags;
1795
1796 // Init the vm_helper
1797 if (dc->vm_helper)
1798 vm_helper_init(dc->vm_helper, 16);
1799
1800 /*************************************************
1801 * Create resources *
1802 *************************************************/
1803
1804 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1805 dcn21_clock_source_create(ctx, ctx->dc_bios,
1806 CLOCK_SOURCE_COMBO_PHY_PLL0,
1807 &clk_src_regs[0], false);
1808 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1809 dcn21_clock_source_create(ctx, ctx->dc_bios,
1810 CLOCK_SOURCE_COMBO_PHY_PLL1,
1811 &clk_src_regs[1], false);
15add0c2
IZ		 1812 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
1813 dcn21_clock_source_create(ctx, ctx->dc_bios,
1814 CLOCK_SOURCE_COMBO_PHY_PLL2,
1815 &clk_src_regs[2], false);
6f4e6361
BL		 1816
1817 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
1818
1819 /* todo: not reuse phy_pll registers */
1820 pool->base.dp_clock_source =
1821 dcn21_clock_source_create(ctx, ctx->dc_bios,
1822 CLOCK_SOURCE_ID_DP_DTO,
1823 &clk_src_regs[0], true);
1824
1825 for (i = 0; i < pool->base.clk_src_count; i++) {
1826 if (pool->base.clock_sources[i] == NULL) {
1827 dm_error("DC: failed to create clock sources!\n");
1828 BREAK_TO_DEBUGGER();
1829 goto create_fail;
1830 }
1831 }
1832
1833 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1834 if (pool->base.dccg == NULL) {
1835 dm_error("DC: failed to create dccg!\n");
1836 BREAK_TO_DEBUGGER();
1837 goto create_fail;
1838 }
1839
a7e3658e 1840 pool->base.dmcu = dcn21_dmcu_create(ctx,
c0fb59a4
BL		 1841 &dmcu_regs,
1842 &dmcu_shift,
1843 &dmcu_mask);
1844 if (pool->base.dmcu == NULL) {
1845 dm_error("DC: failed to create dmcu!\n");
1846 BREAK_TO_DEBUGGER();
1847 goto create_fail;
1848 }
1849
9dac88d8
WW		 1850 if (dc->debug.psr_on_dmub) {
1851 pool->base.psr = dmub_psr_create(ctx);
1852
1853 if (pool->base.psr == NULL) {
1854 dm_error("DC: failed to create psr obj!\n");
1855 BREAK_TO_DEBUGGER();
1856 goto create_fail;
1857 }
1858 }
4c1a1335 1859
c0fb59a4
BL		 1860 pool->base.abm = dce_abm_create(ctx,
1861 &abm_regs,
1862 &abm_shift,
1863 &abm_mask);
1864 if (pool->base.abm == NULL) {
1865 dm_error("DC: failed to create abm!\n");
1866 BREAK_TO_DEBUGGER();
1867 goto create_fail;
1868 }
1869
6f4e6361
BL		 1870 pool->base.pp_smu = dcn21_pp_smu_create(ctx);
1871
ff86391e
MS		 1872 num_pipes = dcn2_1_ip.max_num_dpp;
1873
1874 for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
1875 if (pipe_fuses & 1 << i)
1876 num_pipes--;
1877 dcn2_1_ip.max_num_dpp = num_pipes;
1878 dcn2_1_ip.max_num_otg = num_pipes;
1879
6f4e6361
BL		 1880 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1881
1882 init_data.ctx = dc->ctx;
1883 pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
1884 if (!pool->base.irqs)
1885 goto create_fail;
1886
c0fb59a4 1887 j = 0;
6f4e6361
BL		 1888 /* mem input -> ipp -> dpp -> opp -> TG */
1889 for (i = 0; i < pool->base.pipe_count; i++) {
c0fb59a4
BL		 1890 /* if pipe is disabled, skip instance of HW pipe,
1891 * i.e, skip ASIC register instance
1892 */
1893 if ((pipe_fuses & (1 << i)) != 0)
1894 continue;
1895
b9f1246d
NA		 1896 pool->base.hubps[j] = dcn21_hubp_create(ctx, i);
1897 if (pool->base.hubps[j] == NULL) {
6f4e6361
BL		 1898 BREAK_TO_DEBUGGER();
1899 dm_error(
1900 "DC: failed to create memory input!\n");
1901 goto create_fail;
1902 }
1903
b9f1246d
NA		 1904 pool->base.ipps[j] = dcn21_ipp_create(ctx, i);
1905 if (pool->base.ipps[j] == NULL) {
6f4e6361
BL		 1906 BREAK_TO_DEBUGGER();
1907 dm_error(
1908 "DC: failed to create input pixel processor!\n");
1909 goto create_fail;
1910 }
1911
b9f1246d
NA		 1912 pool->base.dpps[j] = dcn21_dpp_create(ctx, i);
1913 if (pool->base.dpps[j] == NULL) {
6f4e6361
BL		 1914 BREAK_TO_DEBUGGER();
1915 dm_error(
1916 "DC: failed to create dpps!\n");
1917 goto create_fail;
1918 }
c0fb59a4 1919
b9f1246d
NA		 1920 pool->base.opps[j] = dcn21_opp_create(ctx, i);
1921 if (pool->base.opps[j] == NULL) {
c0fb59a4
BL		 1922 BREAK_TO_DEBUGGER();
1923 dm_error(
1924 "DC: failed to create output pixel processor!\n");
1925 goto create_fail;
1926 }
1927
b9f1246d 1928 pool->base.timing_generators[j] = dcn21_timing_generator_create(
c0fb59a4 1929 ctx, i);
b9f1246d 1930 if (pool->base.timing_generators[j] == NULL) {
c0fb59a4
BL		 1931 BREAK_TO_DEBUGGER();
1932 dm_error("DC: failed to create tg!\n");
1933 goto create_fail;
1934 }
1935 j++;
6f4e6361
BL		 1936 }
1937
1938 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1939 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
1940 if (pool->base.engines[i] == NULL) {
1941 BREAK_TO_DEBUGGER();
1942 dm_error(
1943 "DC:failed to create aux engine!!\n");
1944 goto create_fail;
1945 }
1946 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
1947 if (pool->base.hw_i2cs[i] == NULL) {
1948 BREAK_TO_DEBUGGER();
1949 dm_error(
1950 "DC:failed to create hw i2c!!\n");
1951 goto create_fail;
1952 }
1953 pool->base.sw_i2cs[i] = NULL;
1954 }
1955
c0fb59a4
BL		 1956 pool->base.timing_generator_count = j;
1957 pool->base.pipe_count = j;
1958 pool->base.mpcc_count = j;
6f4e6361
BL		 1959
1960 pool->base.mpc = dcn21_mpc_create(ctx);
1961 if (pool->base.mpc == NULL) {
1962 BREAK_TO_DEBUGGER();
1963 dm_error("DC: failed to create mpc!\n");
1964 goto create_fail;
1965 }
1966
1967 pool->base.hubbub = dcn21_hubbub_create(ctx);
1968 if (pool->base.hubbub == NULL) {
1969 BREAK_TO_DEBUGGER();
1970 dm_error("DC: failed to create hubbub!\n");
1971 goto create_fail;
1972 }
1973
6f4e6361
BL		 1974 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1975 pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
1976 if (pool->base.dscs[i] == NULL) {
1977 BREAK_TO_DEBUGGER();
1978 dm_error("DC: failed to create display stream compressor %d!\n", i);
1979 goto create_fail;
1980 }
1981 }
6f4e6361
BL		 1982
1983 if (!dcn20_dwbc_create(ctx, &pool->base)) {
1984 BREAK_TO_DEBUGGER();
1985 dm_error("DC: failed to create dwbc!\n");
1986 goto create_fail;
1987 }
1988 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
1989 BREAK_TO_DEBUGGER();
1990 dm_error("DC: failed to create mcif_wb!\n");
1991 goto create_fail;
1992 }
1993
1994 if (!resource_construct(num_virtual_links, dc, &pool->base,
1995 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1996 &res_create_funcs : &res_create_maximus_funcs)))
1997 goto create_fail;
1998
c0fb59a4 1999 dcn21_hw_sequencer_construct(dc);
6f4e6361
BL		 2000
2001 dc->caps.max_planes = pool->base.pipe_count;
2002
2003 for (i = 0; i < dc->caps.max_planes; ++i)
2004 dc->caps.planes[i] = plane_cap;
2005
2006 dc->cap_funcs = cap_funcs;
2007
2008 return true;
2009
2010create_fail:
2011
d9e32672 2012 dcn21_resource_destruct(pool);
6f4e6361
BL		 2013
2014 return false;
2015}
2016
2017struct resource_pool *dcn21_create_resource_pool(
2018 const struct dc_init_data *init_data,
2019 struct dc *dc)
2020{
2021 struct dcn21_resource_pool *pool =
2022 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);
2023
2024 if (!pool)
2025 return NULL;
2026
d9e32672 2027 if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
6f4e6361
BL		 2028 return &pool->base;
2029
2030 BREAK_TO_DEBUGGER();
2031 kfree(pool);
2032 return NULL;
2033}
Linux 6.x block layer and io_uring tree(s)