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drm/amd/display: rename dsc extended caps as dsc branch decoder caps
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / dc / dcn21 / dcn21_resource.c
CommitLineData
6f4e6361
BL		 1/*
2* Copyright 2018 Advanced Micro Devices, Inc.
6ca3928d 3 * Copyright 2019 Raptor Engineering, LLC
6f4e6361
BL		 4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
aec43402
AB		 27#include <linux/slab.h>
28
6f4e6361
BL		 29#include "dm_services.h"
30#include "dc.h"
31
78c77382
AK		 32#include "dcn21_init.h"
33
6f4e6361
BL		 34#include "resource.h"
35#include "include/irq_service_interface.h"
36#include "dcn20/dcn20_resource.h"
37
38#include "clk_mgr.h"
39#include "dcn10/dcn10_hubp.h"
40#include "dcn10/dcn10_ipp.h"
41#include "dcn20/dcn20_hubbub.h"
42#include "dcn20/dcn20_mpc.h"
43#include "dcn20/dcn20_hubp.h"
44#include "dcn21_hubp.h"
45#include "irq/dcn21/irq_service_dcn21.h"
46#include "dcn20/dcn20_dpp.h"
47#include "dcn20/dcn20_optc.h"
c0fb59a4 48#include "dcn21/dcn21_hwseq.h"
6f4e6361
BL		 49#include "dce110/dce110_hw_sequencer.h"
50#include "dcn20/dcn20_opp.h"
51#include "dcn20/dcn20_dsc.h"
91c665bd 52#include "dcn21/dcn21_link_encoder.h"
6f4e6361
BL		 53#include "dcn20/dcn20_stream_encoder.h"
54#include "dce/dce_clock_source.h"
55#include "dce/dce_audio.h"
56#include "dce/dce_hwseq.h"
57#include "virtual/virtual_stream_encoder.h"
58#include "dce110/dce110_resource.h"
59#include "dml/display_mode_vba.h"
60#include "dcn20/dcn20_dccg.h"
61#include "dcn21_hubbub.h"
62#include "dcn10/dcn10_resource.h"
15add0c2 63#include "dce110/dce110_resource.h"
d4caa72e 64#include "dce/dce_panel_cntl.h"
6f4e6361
BL		 65
66#include "dcn20/dcn20_dwb.h"
67#include "dcn20/dcn20_mmhubbub.h"
a771ded8
RL		 68#include "dpcs/dpcs_2_1_0_offset.h"
69#include "dpcs/dpcs_2_1_0_sh_mask.h"
6f4e6361
BL		 70
71#include "renoir_ip_offset.h"
72#include "dcn/dcn_2_1_0_offset.h"
73#include "dcn/dcn_2_1_0_sh_mask.h"
74
75#include "nbio/nbio_7_0_offset.h"
76
77#include "mmhub/mmhub_2_0_0_offset.h"
78#include "mmhub/mmhub_2_0_0_sh_mask.h"
79
80#include "reg_helper.h"
81#include "dce/dce_abm.h"
82#include "dce/dce_dmcu.h"
83#include "dce/dce_aux.h"
84#include "dce/dce_i2c.h"
85#include "dcn21_resource.h"
86#include "vm_helper.h"
87#include "dcn20/dcn20_vmid.h"
9dac88d8 88#include "dce/dmub_psr.h"
16012806 89#include "dce/dmub_abm.h"
6f4e6361 90
6f4e6361
BL		 91#define DC_LOGGER_INIT(logger)
92
93
94struct _vcs_dpi_ip_params_st dcn2_1_ip = {
652651ff 95 .odm_capable = 1,
8c357309
YS		 96 .gpuvm_enable = 1,
97 .hostvm_enable = 1,
6f4e6361
BL		 98 .gpuvm_max_page_table_levels = 1,
99 .hostvm_max_page_table_levels = 4,
100 .hostvm_cached_page_table_levels = 2,
6f4e6361 101 .num_dsc = 3,
6f4e6361
BL		 102 .rob_buffer_size_kbytes = 168,
103 .det_buffer_size_kbytes = 164,
104 .dpte_buffer_size_in_pte_reqs_luma = 44,
105 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
106 .dpp_output_buffer_pixels = 2560,
107 .opp_output_buffer_lines = 1,
108 .pixel_chunk_size_kbytes = 8,
109 .pte_enable = 1,
110 .max_page_table_levels = 4,
111 .pte_chunk_size_kbytes = 2,
112 .meta_chunk_size_kbytes = 2,
113 .writeback_chunk_size_kbytes = 2,
114 .line_buffer_size_bits = 789504,
115 .is_line_buffer_bpp_fixed = 0,
116 .line_buffer_fixed_bpp = 0,
117 .dcc_supported = true,
118 .max_line_buffer_lines = 12,
119 .writeback_luma_buffer_size_kbytes = 12,
120 .writeback_chroma_buffer_size_kbytes = 8,
121 .writeback_chroma_line_buffer_width_pixels = 4,
122 .writeback_max_hscl_ratio = 1,
123 .writeback_max_vscl_ratio = 1,
124 .writeback_min_hscl_ratio = 1,
125 .writeback_min_vscl_ratio = 1,
126 .writeback_max_hscl_taps = 12,
127 .writeback_max_vscl_taps = 12,
128 .writeback_line_buffer_luma_buffer_size = 0,
129 .writeback_line_buffer_chroma_buffer_size = 14643,
130 .cursor_buffer_size = 8,
131 .cursor_chunk_size = 2,
132 .max_num_otg = 4,
133 .max_num_dpp = 4,
134 .max_num_wb = 1,
135 .max_dchub_pscl_bw_pix_per_clk = 4,
136 .max_pscl_lb_bw_pix_per_clk = 2,
137 .max_lb_vscl_bw_pix_per_clk = 4,
138 .max_vscl_hscl_bw_pix_per_clk = 4,
139 .max_hscl_ratio = 4,
140 .max_vscl_ratio = 4,
141 .hscl_mults = 4,
142 .vscl_mults = 4,
143 .max_hscl_taps = 8,
144 .max_vscl_taps = 8,
145 .dispclk_ramp_margin_percent = 1,
146 .underscan_factor = 1.10,
147 .min_vblank_lines = 32, //
148 .dppclk_delay_subtotal = 77, //
149 .dppclk_delay_scl_lb_only = 16,
150 .dppclk_delay_scl = 50,
151 .dppclk_delay_cnvc_formatter = 8,
152 .dppclk_delay_cnvc_cursor = 6,
153 .dispclk_delay_subtotal = 87, //
154 .dcfclk_cstate_latency = 10, // SRExitTime
155 .max_inter_dcn_tile_repeaters = 8,
156
157 .xfc_supported = false,
158 .xfc_fill_bw_overhead_percent = 10.0,
159 .xfc_fill_constant_bytes = 0,
8f174fdb
YS		 160 .ptoi_supported = 0,
161 .number_of_cursors = 1,
6f4e6361
BL		 162};
163
164struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
165 .clock_limits = {
166 {
167 .state = 0,
a39a5816
EY		 168 .dcfclk_mhz = 400.0,
169 .fabricclk_mhz = 400.0,
170 .dispclk_mhz = 600.0,
171 .dppclk_mhz = 400.00,
6f4e6361
BL		 172 .phyclk_mhz = 600.0,
173 .socclk_mhz = 278.0,
174 .dscclk_mhz = 205.67,
175 .dram_speed_mts = 1600.0,
176 },
177 {
178 .state = 1,
a39a5816
EY		 179 .dcfclk_mhz = 464.52,
180 .fabricclk_mhz = 800.0,
181 .dispclk_mhz = 654.55,
182 .dppclk_mhz = 626.09,
6f4e6361
BL		 183 .phyclk_mhz = 600.0,
184 .socclk_mhz = 278.0,
185 .dscclk_mhz = 205.67,
186 .dram_speed_mts = 1600.0,
187 },
188 {
189 .state = 2,
a39a5816
EY		 190 .dcfclk_mhz = 514.29,
191 .fabricclk_mhz = 933.0,
192 .dispclk_mhz = 757.89,
193 .dppclk_mhz = 685.71,
194 .phyclk_mhz = 600.0,
6f4e6361
BL		 195 .socclk_mhz = 278.0,
196 .dscclk_mhz = 287.67,
a39a5816 197 .dram_speed_mts = 1866.0,
6f4e6361
BL		 198 },
199 {
200 .state = 3,
a39a5816
EY		 201 .dcfclk_mhz = 576.00,
202 .fabricclk_mhz = 1067.0,
203 .dispclk_mhz = 847.06,
204 .dppclk_mhz = 757.89,
205 .phyclk_mhz = 600.0,
6f4e6361
BL		 206 .socclk_mhz = 715.0,
207 .dscclk_mhz = 318.334,
a39a5816 208 .dram_speed_mts = 2134.0,
6f4e6361
BL		 209 },
210 {
211 .state = 4,
a39a5816
EY		 212 .dcfclk_mhz = 626.09,
213 .fabricclk_mhz = 1200.0,
214 .dispclk_mhz = 900.00,
215 .dppclk_mhz = 847.06,
216 .phyclk_mhz = 810.0,
217 .socclk_mhz = 953.0,
218 .dscclk_mhz = 489.0,
219 .dram_speed_mts = 2400.0,
220 },
221 {
222 .state = 5,
223 .dcfclk_mhz = 685.71,
224 .fabricclk_mhz = 1333.0,
225 .dispclk_mhz = 1028.57,
226 .dppclk_mhz = 960.00,
227 .phyclk_mhz = 810.0,
228 .socclk_mhz = 278.0,
229 .dscclk_mhz = 287.67,
230 .dram_speed_mts = 2666.0,
231 },
232 {
233 .state = 6,
234 .dcfclk_mhz = 757.89,
235 .fabricclk_mhz = 1467.0,
236 .dispclk_mhz = 1107.69,
237 .dppclk_mhz = 1028.57,
238 .phyclk_mhz = 810.0,
239 .socclk_mhz = 715.0,
240 .dscclk_mhz = 318.334,
241 .dram_speed_mts = 3200.0,
242 },
243 {
244 .state = 7,
245 .dcfclk_mhz = 847.06,
6f4e6361 246 .fabricclk_mhz = 1600.0,
652651ff 247 .dispclk_mhz = 1395.0,
a39a5816 248 .dppclk_mhz = 1285.00,
652651ff 249 .phyclk_mhz = 1325.0,
6f4e6361 250 .socclk_mhz = 953.0,
652651ff 251 .dscclk_mhz = 489.0,
6f4e6361
BL		 252 .dram_speed_mts = 4266.0,
253 },
254 /*Extra state, no dispclk ramping*/
255 {
a39a5816
EY		 256 .state = 8,
257 .dcfclk_mhz = 847.06,
6f4e6361 258 .fabricclk_mhz = 1600.0,
652651ff
BL		 259 .dispclk_mhz = 1395.0,
260 .dppclk_mhz = 1285.0,
261 .phyclk_mhz = 1325.0,
6f4e6361 262 .socclk_mhz = 953.0,
652651ff 263 .dscclk_mhz = 489.0,
6f4e6361
BL		 264 .dram_speed_mts = 4266.0,
265 },
266
267 },
268
652651ff
BL		 269 .sr_exit_time_us = 12.5,
270 .sr_enter_plus_exit_time_us = 17.0,
6f4e6361
BL		 271 .urgent_latency_us = 4.0,
272 .urgent_latency_pixel_data_only_us = 4.0,
273 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
274 .urgent_latency_vm_data_only_us = 4.0,
275 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
276 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
277 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
278 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
279 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
280 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
281 .max_avg_sdp_bw_use_normal_percent = 60.0,
282 .max_avg_dram_bw_use_normal_percent = 100.0,
283 .writeback_latency_us = 12.0,
284 .max_request_size_bytes = 256,
285 .dram_channel_width_bytes = 4,
286 .fabric_datapath_to_dcn_data_return_bytes = 32,
287 .dcn_downspread_percent = 0.5,
77ef333e 288 .downspread_percent = 0.38,
6f4e6361
BL		 289 .dram_page_open_time_ns = 50.0,
290 .dram_rw_turnaround_time_ns = 17.5,
291 .dram_return_buffer_per_channel_bytes = 8192,
292 .round_trip_ping_latency_dcfclk_cycles = 128,
293 .urgent_out_of_order_return_per_channel_bytes = 4096,
294 .channel_interleave_bytes = 256,
295 .num_banks = 8,
296 .num_chans = 4,
297 .vmm_page_size_bytes = 4096,
298 .dram_clock_change_latency_us = 23.84,
299 .return_bus_width_bytes = 64,
0beb5403 300 .dispclk_dppclk_vco_speed_mhz = 3600,
6f4e6361
BL		 301 .xfc_bus_transport_time_us = 4,
302 .xfc_xbuf_latency_tolerance_us = 4,
303 .use_urgent_burst_bw = 1,
c42656f8 304 .num_states = 8
6f4e6361
BL		 305};
306
307#ifndef MAX
308#define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
309#endif
310#ifndef MIN
311#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
312#endif
313
314/* begin *********************
315 * macros to expend register list macro defined in HW object header file */
316
317/* DCN */
318/* TODO awful hack. fixup dcn20_dwb.h */
319#undef BASE_INNER
320#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
321
322#define BASE(seg) BASE_INNER(seg)
323
324#define SR(reg_name)\
325 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
326 mm ## reg_name
327
328#define SRI(reg_name, block, id)\
329 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
330 mm ## block ## id ## _ ## reg_name
331
332#define SRIR(var_name, reg_name, block, id)\
333 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
334 mm ## block ## id ## _ ## reg_name
335
336#define SRII(reg_name, block, id)\
337 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
338 mm ## block ## id ## _ ## reg_name
339
340#define DCCG_SRII(reg_name, block, id)\
341 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
342 mm ## block ## id ## _ ## reg_name
343
1e461c37
AC		 344#define VUPDATE_SRII(reg_name, block, id)\
345 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
346 mm ## reg_name ## _ ## block ## id
347
6f4e6361
BL		 348/* NBIO */
349#define NBIO_BASE_INNER(seg) \
350 NBIF0_BASE__INST0_SEG ## seg
351
352#define NBIO_BASE(seg) \
353 NBIO_BASE_INNER(seg)
354
355#define NBIO_SR(reg_name)\
356 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
357 mm ## reg_name
358
359/* MMHUB */
360#define MMHUB_BASE_INNER(seg) \
361 MMHUB_BASE__INST0_SEG ## seg
362
363#define MMHUB_BASE(seg) \
364 MMHUB_BASE_INNER(seg)
365
366#define MMHUB_SR(reg_name)\
367 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
368 mmMM ## reg_name
369
370#define clk_src_regs(index, pllid)\
371[index] = {\
372 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
373}
374
375static const struct dce110_clk_src_regs clk_src_regs[] = {
376 clk_src_regs(0, A),
377 clk_src_regs(1, B),
378 clk_src_regs(2, C),
379 clk_src_regs(3, D),
380 clk_src_regs(4, E),
381};
382
383static const struct dce110_clk_src_shift cs_shift = {
384 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
385};
386
387static const struct dce110_clk_src_mask cs_mask = {
388 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
389};
390
391static const struct bios_registers bios_regs = {
392 NBIO_SR(BIOS_SCRATCH_3),
393 NBIO_SR(BIOS_SCRATCH_6)
394};
395
c0fb59a4 396static const struct dce_dmcu_registers dmcu_regs = {
a7e3658e 397 DMCU_DCN20_REG_LIST()
c0fb59a4
BL		 398};
399
400static const struct dce_dmcu_shift dmcu_shift = {
401 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
402};
403
404static const struct dce_dmcu_mask dmcu_mask = {
405 DMCU_MASK_SH_LIST_DCN10(_MASK)
406};
407
408static const struct dce_abm_registers abm_regs = {
409 ABM_DCN20_REG_LIST()
410};
411
412static const struct dce_abm_shift abm_shift = {
413 ABM_MASK_SH_LIST_DCN20(__SHIFT)
414};
415
416static const struct dce_abm_mask abm_mask = {
417 ABM_MASK_SH_LIST_DCN20(_MASK)
418};
419
6f4e6361
BL		 420#define audio_regs(id)\
421[id] = {\
422 AUD_COMMON_REG_LIST(id)\
423}
424
425static const struct dce_audio_registers audio_regs[] = {
426 audio_regs(0),
427 audio_regs(1),
428 audio_regs(2),
429 audio_regs(3),
430 audio_regs(4),
431 audio_regs(5),
432};
433
434#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
435 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
436 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
437 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
438
439static const struct dce_audio_shift audio_shift = {
440 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
441};
442
443static const struct dce_audio_mask audio_mask = {
444 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
445};
446
447static const struct dccg_registers dccg_regs = {
448 DCCG_COMMON_REG_LIST_DCN_BASE()
449};
450
451static const struct dccg_shift dccg_shift = {
452 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
453};
454
455static const struct dccg_mask dccg_mask = {
456 DCCG_MASK_SH_LIST_DCN2(_MASK)
457};
458
459#define opp_regs(id)\
460[id] = {\
461 OPP_REG_LIST_DCN20(id),\
462}
463
464static const struct dcn20_opp_registers opp_regs[] = {
465 opp_regs(0),
466 opp_regs(1),
467 opp_regs(2),
468 opp_regs(3),
469 opp_regs(4),
470 opp_regs(5),
471};
472
473static const struct dcn20_opp_shift opp_shift = {
474 OPP_MASK_SH_LIST_DCN20(__SHIFT)
475};
476
477static const struct dcn20_opp_mask opp_mask = {
478 OPP_MASK_SH_LIST_DCN20(_MASK)
479};
480
481#define tg_regs(id)\
482[id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
483
484static const struct dcn_optc_registers tg_regs[] = {
485 tg_regs(0),
486 tg_regs(1),
487 tg_regs(2),
488 tg_regs(3)
489};
490
491static const struct dcn_optc_shift tg_shift = {
492 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
493};
494
495static const struct dcn_optc_mask tg_mask = {
496 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
497};
498
499static const struct dcn20_mpc_registers mpc_regs = {
500 MPC_REG_LIST_DCN2_0(0),
501 MPC_REG_LIST_DCN2_0(1),
502 MPC_REG_LIST_DCN2_0(2),
503 MPC_REG_LIST_DCN2_0(3),
504 MPC_REG_LIST_DCN2_0(4),
505 MPC_REG_LIST_DCN2_0(5),
506 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
507 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
508 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
e8027e08
NA		 509 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
510 MPC_DBG_REG_LIST_DCN2_0()
6f4e6361
BL		 511};
512
513static const struct dcn20_mpc_shift mpc_shift = {
c1e34175
NA		 514 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
515 MPC_DEBUG_REG_LIST_SH_DCN20
6f4e6361
BL		 516};
517
518static const struct dcn20_mpc_mask mpc_mask = {
c1e34175
NA		 519 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
520 MPC_DEBUG_REG_LIST_MASK_DCN20
6f4e6361
BL		 521};
522
523#define hubp_regs(id)\
524[id] = {\
525 HUBP_REG_LIST_DCN21(id)\
526}
527
528static const struct dcn_hubp2_registers hubp_regs[] = {
529 hubp_regs(0),
530 hubp_regs(1),
531 hubp_regs(2),
532 hubp_regs(3)
533};
534
535static const struct dcn_hubp2_shift hubp_shift = {
536 HUBP_MASK_SH_LIST_DCN21(__SHIFT)
537};
538
539static const struct dcn_hubp2_mask hubp_mask = {
540 HUBP_MASK_SH_LIST_DCN21(_MASK)
541};
542
543static const struct dcn_hubbub_registers hubbub_reg = {
544 HUBBUB_REG_LIST_DCN21()
545};
546
547static const struct dcn_hubbub_shift hubbub_shift = {
548 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
549};
550
551static const struct dcn_hubbub_mask hubbub_mask = {
552 HUBBUB_MASK_SH_LIST_DCN21(_MASK)
553};
554
555
556#define vmid_regs(id)\
557[id] = {\
558 DCN20_VMID_REG_LIST(id)\
559}
560
561static const struct dcn_vmid_registers vmid_regs[] = {
562 vmid_regs(0),
563 vmid_regs(1),
564 vmid_regs(2),
565 vmid_regs(3),
566 vmid_regs(4),
567 vmid_regs(5),
568 vmid_regs(6),
569 vmid_regs(7),
570 vmid_regs(8),
571 vmid_regs(9),
572 vmid_regs(10),
573 vmid_regs(11),
574 vmid_regs(12),
575 vmid_regs(13),
576 vmid_regs(14),
577 vmid_regs(15)
578};
579
580static const struct dcn20_vmid_shift vmid_shifts = {
581 DCN20_VMID_MASK_SH_LIST(__SHIFT)
582};
583
584static const struct dcn20_vmid_mask vmid_masks = {
585 DCN20_VMID_MASK_SH_LIST(_MASK)
586};
587
6f4e6361
BL		 588#define dsc_regsDCN20(id)\
589[id] = {\
590 DSC_REG_LIST_DCN20(id)\
591}
592
593static const struct dcn20_dsc_registers dsc_regs[] = {
594 dsc_regsDCN20(0),
595 dsc_regsDCN20(1),
596 dsc_regsDCN20(2),
597 dsc_regsDCN20(3),
598 dsc_regsDCN20(4),
599 dsc_regsDCN20(5)
600};
601
602static const struct dcn20_dsc_shift dsc_shift = {
603 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
604};
605
606static const struct dcn20_dsc_mask dsc_mask = {
607 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
608};
6f4e6361
BL		 609
610#define ipp_regs(id)\
611[id] = {\
612 IPP_REG_LIST_DCN20(id),\
613}
614
615static const struct dcn10_ipp_registers ipp_regs[] = {
616 ipp_regs(0),
617 ipp_regs(1),
618 ipp_regs(2),
619 ipp_regs(3),
620};
621
622static const struct dcn10_ipp_shift ipp_shift = {
623 IPP_MASK_SH_LIST_DCN20(__SHIFT)
624};
625
626static const struct dcn10_ipp_mask ipp_mask = {
627 IPP_MASK_SH_LIST_DCN20(_MASK),
628};
629
630#define opp_regs(id)\
631[id] = {\
632 OPP_REG_LIST_DCN20(id),\
633}
634
635
636#define aux_engine_regs(id)\
637[id] = {\
638 AUX_COMMON_REG_LIST0(id), \
639 .AUXN_IMPCAL = 0, \
640 .AUXP_IMPCAL = 0, \
641 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
642}
643
644static const struct dce110_aux_registers aux_engine_regs[] = {
645 aux_engine_regs(0),
646 aux_engine_regs(1),
647 aux_engine_regs(2),
648 aux_engine_regs(3),
649 aux_engine_regs(4),
650};
651
652#define tf_regs(id)\
653[id] = {\
654 TF_REG_LIST_DCN20(id),\
d9eb70ae 655 TF_REG_LIST_DCN20_COMMON_APPEND(id),\
6f4e6361
BL		 656}
657
658static const struct dcn2_dpp_registers tf_regs[] = {
659 tf_regs(0),
660 tf_regs(1),
661 tf_regs(2),
662 tf_regs(3),
663};
664
665static const struct dcn2_dpp_shift tf_shift = {
d9eb70ae 666 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
c1e34175 667 TF_DEBUG_REG_LIST_SH_DCN20
6f4e6361
BL		 668};
669
670static const struct dcn2_dpp_mask tf_mask = {
d9eb70ae 671 TF_REG_LIST_SH_MASK_DCN20(_MASK),
c1e34175 672 TF_DEBUG_REG_LIST_MASK_DCN20
6f4e6361
BL		 673};
674
675#define stream_enc_regs(id)\
676[id] = {\
677 SE_DCN2_REG_LIST(id)\
678}
679
680static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
681 stream_enc_regs(0),
682 stream_enc_regs(1),
683 stream_enc_regs(2),
684 stream_enc_regs(3),
685 stream_enc_regs(4),
686};
687
8276dd87 688static const struct dce110_aux_registers_shift aux_shift = {
689 DCN_AUX_MASK_SH_LIST(__SHIFT)
690};
691
692static const struct dce110_aux_registers_mask aux_mask = {
693 DCN_AUX_MASK_SH_LIST(_MASK)
694};
695
6f4e6361
BL		 696static const struct dcn10_stream_encoder_shift se_shift = {
697 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
698};
699
700static const struct dcn10_stream_encoder_mask se_mask = {
701 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
702};
703
44e149bb
AD		 704static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
705
8c357309 706static int dcn21_populate_dml_pipes_from_context(
2f488884 707 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes);
8c357309 708
6f4e6361
BL		 709static struct input_pixel_processor *dcn21_ipp_create(
710 struct dc_context *ctx, uint32_t inst)
711{
712 struct dcn10_ipp *ipp =
713 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
714
715 if (!ipp) {
716 BREAK_TO_DEBUGGER();
717 return NULL;
718 }
719
720 dcn20_ipp_construct(ipp, ctx, inst,
721 &ipp_regs[inst], &ipp_shift, &ipp_mask);
722 return &ipp->base;
723}
724
725static struct dpp *dcn21_dpp_create(
726 struct dc_context *ctx,
727 uint32_t inst)
728{
729 struct dcn20_dpp *dpp =
730 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
731
732 if (!dpp)
733 return NULL;
734
735 if (dpp2_construct(dpp, ctx, inst,
736 &tf_regs[inst], &tf_shift, &tf_mask))
737 return &dpp->base;
738
739 BREAK_TO_DEBUGGER();
740 kfree(dpp);
741 return NULL;
742}
743
744static struct dce_aux *dcn21_aux_engine_create(
745 struct dc_context *ctx,
746 uint32_t inst)
747{
748 struct aux_engine_dce110 *aux_engine =
749 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
750
751 if (!aux_engine)
752 return NULL;
753
754 dce110_aux_engine_construct(aux_engine, ctx, inst,
755 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
8276dd87 756 &aux_engine_regs[inst],
757 &aux_mask,
f6040a43 758 &aux_shift,
759 ctx->dc->caps.extended_aux_timeout_support);
6f4e6361
BL		 760
761 return &aux_engine->base;
762}
763
764#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
765
766static const struct dce_i2c_registers i2c_hw_regs[] = {
767 i2c_inst_regs(1),
768 i2c_inst_regs(2),
769 i2c_inst_regs(3),
770 i2c_inst_regs(4),
771 i2c_inst_regs(5),
772};
773
774static const struct dce_i2c_shift i2c_shifts = {
775 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
776};
777
778static const struct dce_i2c_mask i2c_masks = {
779 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
780};
781
782struct dce_i2c_hw *dcn21_i2c_hw_create(
783 struct dc_context *ctx,
784 uint32_t inst)
785{
786 struct dce_i2c_hw *dce_i2c_hw =
787 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
788
789 if (!dce_i2c_hw)
790 return NULL;
791
792 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
793 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
794
795 return dce_i2c_hw;
796}
797
798static const struct resource_caps res_cap_rn = {
799 .num_timing_generator = 4,
800 .num_opp = 4,
801 .num_video_plane = 4,
b356843e 802 .num_audio = 4, // 4 audio endpoints. 4 audio streams
6f4e6361
BL		 803 .num_stream_encoder = 5,
804 .num_pll = 5, // maybe 3 because the last two used for USB-c
805 .num_dwb = 1,
806 .num_ddc = 5,
fdcf62fb 807 .num_vmid = 16,
6f4e6361 808 .num_dsc = 3,
6f4e6361
BL		 809};
810
811#ifdef DIAGS_BUILD
812static const struct resource_caps res_cap_rn_FPGA_4pipe = {
813 .num_timing_generator = 4,
814 .num_opp = 4,
815 .num_video_plane = 4,
816 .num_audio = 7,
817 .num_stream_encoder = 4,
818 .num_pll = 4,
819 .num_dwb = 1,
820 .num_ddc = 4,
821 .num_dsc = 0,
822};
823
824static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
825 .num_timing_generator = 2,
826 .num_opp = 2,
827 .num_video_plane = 2,
828 .num_audio = 7,
829 .num_stream_encoder = 2,
830 .num_pll = 4,
831 .num_dwb = 1,
832 .num_ddc = 4,
6f4e6361 833 .num_dsc = 2,
6f4e6361
BL		 834};
835#endif
836
837static const struct dc_plane_cap plane_cap = {
838 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
839 .blends_with_above = true,
840 .blends_with_below = true,
841 .per_pixel_alpha = true,
842
843 .pixel_format_support = {
844 .argb8888 = true,
845 .nv12 = true,
cbec6477
SW		 846 .fp16 = true,
847 .p010 = true
6f4e6361
BL		 848 },
849
850 .max_upscale_factor = {
851 .argb8888 = 16000,
852 .nv12 = 16000,
853 .fp16 = 16000
854 },
855
856 .max_downscale_factor = {
857 .argb8888 = 250,
858 .nv12 = 250,
859 .fp16 = 250
860 }
861};
862
863static const struct dc_debug_options debug_defaults_drv = {
f0a574c9 864 .disable_dmcu = false,
6f4e6361
BL		 865 .force_abm_enable = false,
866 .timing_trace = false,
867 .clock_trace = true,
868 .disable_pplib_clock_request = true,
cab5dec4 869 .min_disp_clk_khz = 100000,
6f4e6361 870 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
4d25a0d5 871 .force_single_disp_pipe_split = false,
6f4e6361
BL		 872 .disable_dcc = DCC_ENABLE,
873 .vsr_support = true,
874 .performance_trace = false,
947daab2 875 .max_downscale_src_width = 4096,
6f4e6361
BL		 876 .disable_pplib_wm_range = false,
877 .scl_reset_length10 = true,
878 .sanity_checks = true,
57133a28 879 .disable_48mhz_pwrdwn = false,
ee765924 880 .usbc_combo_phy_reset_wa = true
6f4e6361
BL		 881};
882
883static const struct dc_debug_options debug_defaults_diags = {
f0a574c9 884 .disable_dmcu = false,
6f4e6361
BL		 885 .force_abm_enable = false,
886 .timing_trace = true,
887 .clock_trace = true,
888 .disable_dpp_power_gate = true,
889 .disable_hubp_power_gate = true,
890 .disable_clock_gate = true,
891 .disable_pplib_clock_request = true,
892 .disable_pplib_wm_range = true,
893 .disable_stutter = true,
894 .disable_48mhz_pwrdwn = true,
895};
896
897enum dcn20_clk_src_array_id {
898 DCN20_CLK_SRC_PLL0,
899 DCN20_CLK_SRC_PLL1,
15add0c2 900 DCN20_CLK_SRC_PLL2,
6f4e6361
BL		 901 DCN20_CLK_SRC_TOTAL_DCN21
902};
903
d9e32672 904static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
6f4e6361
BL		 905{
906 unsigned int i;
907
908 for (i = 0; i < pool->base.stream_enc_count; i++) {
909 if (pool->base.stream_enc[i] != NULL) {
910 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
911 pool->base.stream_enc[i] = NULL;
912 }
913 }
914
6f4e6361
BL		 915 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
916 if (pool->base.dscs[i] != NULL)
917 dcn20_dsc_destroy(&pool->base.dscs[i]);
918 }
6f4e6361
BL		 919
920 if (pool->base.mpc != NULL) {
921 kfree(TO_DCN20_MPC(pool->base.mpc));
922 pool->base.mpc = NULL;
923 }
924 if (pool->base.hubbub != NULL) {
925 kfree(pool->base.hubbub);
926 pool->base.hubbub = NULL;
927 }
928 for (i = 0; i < pool->base.pipe_count; i++) {
929 if (pool->base.dpps[i] != NULL)
930 dcn20_dpp_destroy(&pool->base.dpps[i]);
931
932 if (pool->base.ipps[i] != NULL)
933 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
934
935 if (pool->base.hubps[i] != NULL) {
936 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
937 pool->base.hubps[i] = NULL;
938 }
939
940 if (pool->base.irqs != NULL) {
941 dal_irq_service_destroy(&pool->base.irqs);
942 }
943 }
944
945 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
946 if (pool->base.engines[i] != NULL)
947 dce110_engine_destroy(&pool->base.engines[i]);
948 if (pool->base.hw_i2cs[i] != NULL) {
949 kfree(pool->base.hw_i2cs[i]);
950 pool->base.hw_i2cs[i] = NULL;
951 }
952 if (pool->base.sw_i2cs[i] != NULL) {
953 kfree(pool->base.sw_i2cs[i]);
954 pool->base.sw_i2cs[i] = NULL;
955 }
956 }
957
958 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
959 if (pool->base.opps[i] != NULL)
960 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
961 }
962
963 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
964 if (pool->base.timing_generators[i] != NULL) {
965 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
966 pool->base.timing_generators[i] = NULL;
967 }
968 }
969
970 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
971 if (pool->base.dwbc[i] != NULL) {
972 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
973 pool->base.dwbc[i] = NULL;
974 }
975 if (pool->base.mcif_wb[i] != NULL) {
976 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
977 pool->base.mcif_wb[i] = NULL;
978 }
979 }
980
981 for (i = 0; i < pool->base.audio_count; i++) {
982 if (pool->base.audios[i])
983 dce_aud_destroy(&pool->base.audios[i]);
984 }
985
986 for (i = 0; i < pool->base.clk_src_count; i++) {
987 if (pool->base.clock_sources[i] != NULL) {
988 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
989 pool->base.clock_sources[i] = NULL;
990 }
991 }
992
993 if (pool->base.dp_clock_source != NULL) {
994 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
995 pool->base.dp_clock_source = NULL;
996 }
997
16012806 998 if (pool->base.abm != NULL) {
501b4026 999 if (pool->base.abm->ctx->dc->config.disable_dmcu)
16012806
WW		 1000 dmub_abm_destroy(&pool->base.abm);
1001 else
1002 dce_abm_destroy(&pool->base.abm);
1003 }
6f4e6361
BL		 1004
1005 if (pool->base.dmcu != NULL)
1006 dce_dmcu_destroy(&pool->base.dmcu);
1007
9dac88d8
WW		 1008 if (pool->base.psr != NULL)
1009 dmub_psr_destroy(&pool->base.psr);
1010
6f4e6361
BL		 1011 if (pool->base.dccg != NULL)
1012 dcn_dccg_destroy(&pool->base.dccg);
1013
1014 if (pool->base.pp_smu != NULL)
44e149bb 1015 dcn21_pp_smu_destroy(&pool->base.pp_smu);
6f4e6361
BL		 1016}
1017
1018
1019static void calculate_wm_set_for_vlevel(
1020 int vlevel,
1021 struct wm_range_table_entry *table_entry,
1022 struct dcn_watermarks *wm_set,
1023 struct display_mode_lib *dml,
1024 display_e2e_pipe_params_st *pipes,
1025 int pipe_cnt)
1026{
1027 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
1028
1029 ASSERT(vlevel < dml->soc.num_states);
1030 /* only pipe 0 is read for voltage and dcf/soc clocks */
1031 pipes[0].clks_cfg.voltage = vlevel;
1032 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
1033 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
1034
1035 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
d3511fd0
EY		 1036 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
1037 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
6f4e6361
BL		 1038
1039 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
1040 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
1041 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
1042 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1043 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
6f4e6361
BL		 1044 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
1045 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
b617b265 1046 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
6f4e6361
BL		 1047 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
1048
1049}
1050
15fdbcc5
LH		 1051static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
1052{
d3511fd0
EY		 1053 int i;
1054
6ca3928d
TP		 1055 DC_FP_START();
1056
15fdbcc5 1057 if (dc->bb_overrides.sr_exit_time_ns) {
d3511fd0
EY		 1058 for (i = 0; i < WM_SET_COUNT; i++) {
1059 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
1060 dc->bb_overrides.sr_exit_time_ns / 1000.0;
1061 }
15fdbcc5
LH		 1062 }
1063
1064 if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
d3511fd0
EY		 1065 for (i = 0; i < WM_SET_COUNT; i++) {
1066 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
1067 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
1068 }
15fdbcc5
LH		 1069 }
1070
1071 if (dc->bb_overrides.urgent_latency_ns) {
1072 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
1073 }
1074
1075 if (dc->bb_overrides.dram_clock_change_latency_ns) {
580c8be2
JG		 1076 for (i = 0; i < WM_SET_COUNT; i++) {
1077 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
15fdbcc5 1078 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
580c8be2 1079 }
15fdbcc5 1080 }
580c8be2 1081
6ca3928d 1082 DC_FP_END();
15fdbcc5
LH		 1083}
1084
6f4e6361
BL		 1085void dcn21_calculate_wm(
1086 struct dc *dc, struct dc_state *context,
1087 display_e2e_pipe_params_st *pipes,
1088 int *out_pipe_cnt,
1089 int *pipe_split_from,
1090 int vlevel_req)
1091{
1092 int pipe_cnt, i, pipe_idx;
1093 int vlevel, vlevel_max;
1094 struct wm_range_table_entry *table_entry;
1095 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
1096
1097 ASSERT(bw_params);
1098
15fdbcc5
LH		 1099 patch_bounding_box(dc, &context->bw_ctx.dml.soc);
1100
6f4e6361
BL		 1101 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1102 if (!context->res_ctx.pipe_ctx[i].stream)
1103 continue;
1104
1105 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1106 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
1107
1108 if (pipe_split_from[i] < 0) {
1109 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1110 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1111 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1112 pipes[pipe_cnt].pipe.dest.odm_combine =
1113 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
1114 else
1115 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1116 pipe_idx++;
1117 } else {
1118 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1119 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1120 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1121 pipes[pipe_cnt].pipe.dest.odm_combine =
1122 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];
1123 else
1124 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1125 }
1126 pipe_cnt++;
1127 }
1128
1129 if (pipe_cnt != pipe_idx) {
1130 if (dc->res_pool->funcs->populate_dml_pipes)
1131 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2f488884 1132 context, pipes);
6f4e6361 1133 else
8c357309 1134 pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
2f488884 1135 context, pipes);
6f4e6361
BL		 1136 }
1137
1138 *out_pipe_cnt = pipe_cnt;
1139
1140 vlevel_max = bw_params->clk_table.num_entries - 1;
1141
1142
1143 /* WM Set D */
1144 table_entry = &bw_params->wm_table.entries[WM_D];
1145 if (table_entry->wm_type == WM_TYPE_RETRAINING)
1146 vlevel = 0;
1147 else
1148 vlevel = vlevel_max;
1149 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
1150 &context->bw_ctx.dml, pipes, pipe_cnt);
1151 /* WM Set C */
1152 table_entry = &bw_params->wm_table.entries[WM_C];
1153 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
1154 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
1155 &context->bw_ctx.dml, pipes, pipe_cnt);
1156 /* WM Set B */
1157 table_entry = &bw_params->wm_table.entries[WM_B];
1158 vlevel = MIN(MAX(vlevel_req, 1), vlevel_max);
1159 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
1160 &context->bw_ctx.dml, pipes, pipe_cnt);
1161
1162 /* WM Set A */
1163 table_entry = &bw_params->wm_table.entries[WM_A];
1164 vlevel = MIN(vlevel_req, vlevel_max);
1165 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
1166 &context->bw_ctx.dml, pipes, pipe_cnt);
1167}
1168
1169
1170bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
1171 bool fast_validate)
1172{
1173 bool out = false;
1174
1175 BW_VAL_TRACE_SETUP();
1176
1177 int vlevel = 0;
1178 int pipe_split_from[MAX_PIPES];
1179 int pipe_cnt = 0;
1180 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1181 DC_LOGGER_INIT(dc->ctx->logger);
1182
1183 BW_VAL_TRACE_COUNT();
1184
1185 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
1186
1187 if (pipe_cnt == 0)
1188 goto validate_out;
1189
1190 if (!out)
1191 goto validate_fail;
1192
1193 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1194
1195 if (fast_validate) {
1196 BW_VAL_TRACE_SKIP(fast);
1197 goto validate_out;
1198 }
1199
1200 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
1201 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1202
1203 BW_VAL_TRACE_END_WATERMARKS();
1204
1205 goto validate_out;
1206
1207validate_fail:
1208 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1209 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1210
1211 BW_VAL_TRACE_SKIP(fail);
1212 out = false;
1213
1214validate_out:
1215 kfree(pipes);
1216
1217 BW_VAL_TRACE_FINISH();
1218
1219 return out;
1220}
1221static void dcn21_destroy_resource_pool(struct resource_pool **pool)
1222{
1223 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
1224
d9e32672 1225 dcn21_resource_destruct(dcn21_pool);
6f4e6361
BL		 1226 kfree(dcn21_pool);
1227 *pool = NULL;
1228}
1229
1230static struct clock_source *dcn21_clock_source_create(
1231 struct dc_context *ctx,
1232 struct dc_bios *bios,
1233 enum clock_source_id id,
1234 const struct dce110_clk_src_regs *regs,
1235 bool dp_clk_src)
1236{
1237 struct dce110_clk_src *clk_src =
1238 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1239
1240 if (!clk_src)
1241 return NULL;
1242
1243 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1244 regs, &cs_shift, &cs_mask)) {
1245 clk_src->base.dp_clk_src = dp_clk_src;
1246 return &clk_src->base;
1247 }
1248
1249 BREAK_TO_DEBUGGER();
1250 return NULL;
1251}
1252
1253static struct hubp *dcn21_hubp_create(
1254 struct dc_context *ctx,
1255 uint32_t inst)
1256{
1257 struct dcn21_hubp *hubp21 =
1258 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);
1259
1260 if (!hubp21)
1261 return NULL;
1262
1263 if (hubp21_construct(hubp21, ctx, inst,
1264 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1265 return &hubp21->base;
1266
1267 BREAK_TO_DEBUGGER();
1268 kfree(hubp21);
1269 return NULL;
1270}
1271
1272static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
1273{
1274 int i;
1275
1276 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1277 GFP_KERNEL);
1278
1279 if (!hubbub)
1280 return NULL;
1281
1282 hubbub21_construct(hubbub, ctx,
1283 &hubbub_reg,
1284 &hubbub_shift,
1285 &hubbub_mask);
1286
1287 for (i = 0; i < res_cap_rn.num_vmid; i++) {
1288 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1289
1290 vmid->ctx = ctx;
1291
1292 vmid->regs = &vmid_regs[i];
1293 vmid->shifts = &vmid_shifts;
1294 vmid->masks = &vmid_masks;
1295 }
fdcf62fb 1296 hubbub->num_vmid = res_cap_rn.num_vmid;
6f4e6361
BL		 1297
1298 return &hubbub->base;
1299}
1300
1301struct output_pixel_processor *dcn21_opp_create(
1302 struct dc_context *ctx, uint32_t inst)
1303{
1304 struct dcn20_opp *opp =
1305 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1306
1307 if (!opp) {
1308 BREAK_TO_DEBUGGER();
1309 return NULL;
1310 }
1311
1312 dcn20_opp_construct(opp, ctx, inst,
1313 &opp_regs[inst], &opp_shift, &opp_mask);
1314 return &opp->base;
1315}
1316
1317struct timing_generator *dcn21_timing_generator_create(
1318 struct dc_context *ctx,
1319 uint32_t instance)
1320{
1321 struct optc *tgn10 =
1322 kzalloc(sizeof(struct optc), GFP_KERNEL);
1323
1324 if (!tgn10)
1325 return NULL;
1326
1327 tgn10->base.inst = instance;
1328 tgn10->base.ctx = ctx;
1329
1330 tgn10->tg_regs = &tg_regs[instance];
1331 tgn10->tg_shift = &tg_shift;
1332 tgn10->tg_mask = &tg_mask;
1333
1334 dcn20_timing_generator_init(tgn10);
1335
1336 return &tgn10->base;
1337}
1338
1339struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1340{
1341 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1342 GFP_KERNEL);
1343
1344 if (!mpc20)
1345 return NULL;
1346
1347 dcn20_mpc_construct(mpc20, ctx,
1348 &mpc_regs,
1349 &mpc_shift,
1350 &mpc_mask,
1351 6);
1352
1353 return &mpc20->base;
1354}
1355
1356static void read_dce_straps(
1357 struct dc_context *ctx,
1358 struct resource_straps *straps)
1359{
1360 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1361 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1362
1363}
1364
6f4e6361
BL		 1365
1366struct display_stream_compressor *dcn21_dsc_create(
1367 struct dc_context *ctx, uint32_t inst)
1368{
1369 struct dcn20_dsc *dsc =
1370 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1371
1372 if (!dsc) {
1373 BREAK_TO_DEBUGGER();
1374 return NULL;
1375 }
1376
1377 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1378 return &dsc->base;
1379}
6f4e6361
BL		 1380
1381static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1382{
1383 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
1384 struct clk_limit_table *clk_table = &bw_params->clk_table;
23838777 1385 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
6de1601e
ZW		 1386 unsigned int i, closest_clk_lvl;
1387 int j;
a39a5816 1388
c42656f8 1389 // Default clock levels are used for diags, which may lead to overclocking.
23838777 1390 if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
a39a5816
EY		 1391 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1392 dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
1393 dcn2_1_soc.num_chans = bw_params->num_channels;
1394
23838777
DL		 1395 ASSERT(clk_table->num_entries);
1396 for (i = 0; i < clk_table->num_entries; i++) {
1397 /* loop backwards*/
1398 for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) {
a39a5816
EY		 1399 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
1400 closest_clk_lvl = j;
1401 break;
1402 }
1403 }
6f4e6361 1404
23838777
DL		 1405 clock_limits[i].state = i;
1406 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
1407 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
1408 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
1409 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
1410
1411 clock_limits[i].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
1412 clock_limits[i].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
1413 clock_limits[i].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
1414 clock_limits[i].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
1415 clock_limits[i].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
1416 clock_limits[i].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
1417 clock_limits[i].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
1418 }
1419 for (i = 0; i < clk_table->num_entries; i++)
1420 dcn2_1_soc.clock_limits[i] = clock_limits[i];
1421 if (clk_table->num_entries) {
1422 dcn2_1_soc.num_states = clk_table->num_entries;
1423 /* duplicate last level */
1424 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
1425 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;
a39a5816 1426 }
6f4e6361 1427 }
08f6c859 1428
a39a5816 1429 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
6f4e6361
BL		 1430}
1431
1432/* Temporary Place holder until we can get them from fuse */
1433static struct dpm_clocks dummy_clocks = {
1434 .DcfClocks = {
1435 {.Freq = 400, .Vol = 1},
1436 {.Freq = 483, .Vol = 1},
1437 {.Freq = 602, .Vol = 1},
1438 {.Freq = 738, .Vol = 1} },
1439 .SocClocks = {
1440 {.Freq = 300, .Vol = 1},
1441 {.Freq = 400, .Vol = 1},
1442 {.Freq = 400, .Vol = 1},
1443 {.Freq = 400, .Vol = 1} },
1444 .FClocks = {
1445 {.Freq = 400, .Vol = 1},
1446 {.Freq = 800, .Vol = 1},
1447 {.Freq = 1067, .Vol = 1},
1448 {.Freq = 1600, .Vol = 1} },
1449 .MemClocks = {
1450 {.Freq = 800, .Vol = 1},
1451 {.Freq = 1600, .Vol = 1},
1452 {.Freq = 1067, .Vol = 1},
1453 {.Freq = 1600, .Vol = 1} },
1454
1455};
1456
976035dd 1457static enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp,
6f4e6361
BL		 1458 struct pp_smu_wm_range_sets *ranges)
1459{
1460 return PP_SMU_RESULT_OK;
1461}
1462
976035dd 1463static enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp,
6f4e6361
BL		 1464 struct dpm_clocks *clock_table)
1465{
1466 *clock_table = dummy_clocks;
1467 return PP_SMU_RESULT_OK;
1468}
1469
976035dd 1470static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
6f4e6361
BL		 1471{
1472 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
1473
a51894f0
EY		 1474 if (!pp_smu)
1475 return pp_smu;
6f4e6361 1476
3794943c 1477 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment) || IS_DIAG_DC(ctx->dce_environment)) {
a51894f0
EY		 1478 pp_smu->ctx.ver = PP_SMU_VER_RN;
1479 pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table;
1480 pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges;
1481 } else {
1482
1483 dm_pp_get_funcs(ctx, pp_smu);
1484
1485 if (pp_smu->ctx.ver != PP_SMU_VER_RN)
1486 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
1487 }
6f4e6361
BL		 1488
1489 return pp_smu;
1490}
1491
976035dd 1492static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
6f4e6361
BL		 1493{
1494 if (pp_smu && *pp_smu) {
1495 kfree(*pp_smu);
1496 *pp_smu = NULL;
1497 }
1498}
1499
1500static struct audio *dcn21_create_audio(
1501 struct dc_context *ctx, unsigned int inst)
1502{
1503 return dce_audio_create(ctx, inst,
1504 &audio_regs[inst], &audio_shift, &audio_mask);
1505}
1506
1507static struct dc_cap_funcs cap_funcs = {
1508 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1509};
1510
1511struct stream_encoder *dcn21_stream_encoder_create(
1512 enum engine_id eng_id,
1513 struct dc_context *ctx)
1514{
1515 struct dcn10_stream_encoder *enc1 =
1516 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1517
1518 if (!enc1)
1519 return NULL;
1520
1521 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1522 &stream_enc_regs[eng_id],
1523 &se_shift, &se_mask);
1524
1525 return &enc1->base;
1526}
1527
1528static const struct dce_hwseq_registers hwseq_reg = {
1529 HWSEQ_DCN21_REG_LIST()
1530};
1531
1532static const struct dce_hwseq_shift hwseq_shift = {
1533 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
1534};
1535
1536static const struct dce_hwseq_mask hwseq_mask = {
1537 HWSEQ_DCN21_MASK_SH_LIST(_MASK)
1538};
1539
1540static struct dce_hwseq *dcn21_hwseq_create(
1541 struct dc_context *ctx)
1542{
1543 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1544
1545 if (hws) {
1546 hws->ctx = ctx;
1547 hws->regs = &hwseq_reg;
1548 hws->shifts = &hwseq_shift;
1549 hws->masks = &hwseq_mask;
f93e29f0 1550 hws->wa.DEGVIDCN21 = true;
d9758768 1551 hws->wa.disallow_self_refresh_during_multi_plane_transition = true;
6f4e6361
BL		 1552 }
1553 return hws;
1554}
1555
1556static const struct resource_create_funcs res_create_funcs = {
1557 .read_dce_straps = read_dce_straps,
1558 .create_audio = dcn21_create_audio,
1559 .create_stream_encoder = dcn21_stream_encoder_create,
1560 .create_hwseq = dcn21_hwseq_create,
1561};
1562
1563static const struct resource_create_funcs res_create_maximus_funcs = {
1564 .read_dce_straps = NULL,
1565 .create_audio = NULL,
1566 .create_stream_encoder = NULL,
1567 .create_hwseq = dcn21_hwseq_create,
1568};
1569
91c665bd
BL		 1570static const struct encoder_feature_support link_enc_feature = {
1571 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1572 .max_hdmi_pixel_clock = 600000,
1573 .hdmi_ycbcr420_supported = true,
1574 .dp_ycbcr420_supported = true,
c14b726e 1575 .fec_supported = true,
91c665bd
BL		 1576 .flags.bits.IS_HBR2_CAPABLE = true,
1577 .flags.bits.IS_HBR3_CAPABLE = true,
1578 .flags.bits.IS_TPS3_CAPABLE = true,
1579 .flags.bits.IS_TPS4_CAPABLE = true
1580};
1581
1582
1583#define link_regs(id, phyid)\
1584[id] = {\
a771ded8 1585 LE_DCN2_REG_LIST(id), \
91c665bd 1586 UNIPHY_DCN2_REG_LIST(phyid), \
a771ded8 1587 DPCS_DCN21_REG_LIST(id), \
91c665bd
BL		 1588 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
1589}
1590
1591static const struct dcn10_link_enc_registers link_enc_regs[] = {
1592 link_regs(0, A),
1593 link_regs(1, B),
1594 link_regs(2, C),
1595 link_regs(3, D),
1596 link_regs(4, E),
1597};
1598
d4caa72e
AK		 1599static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
1600 { DCN_PANEL_CNTL_REG_LIST() }
904fb6e0
AK		 1601};
1602
d4caa72e
AK		 1603static const struct dce_panel_cntl_shift panel_cntl_shift = {
1604 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
904fb6e0
AK		 1605};
1606
d4caa72e
AK		 1607static const struct dce_panel_cntl_mask panel_cntl_mask = {
1608 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
904fb6e0
AK		 1609};
1610
91c665bd
BL		 1611#define aux_regs(id)\
1612[id] = {\
1613 DCN2_AUX_REG_LIST(id)\
1614}
1615
1616static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1617 aux_regs(0),
1618 aux_regs(1),
1619 aux_regs(2),
1620 aux_regs(3),
1621 aux_regs(4)
1622};
1623
1624#define hpd_regs(id)\
1625[id] = {\
1626 HPD_REG_LIST(id)\
1627}
1628
1629static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1630 hpd_regs(0),
1631 hpd_regs(1),
1632 hpd_regs(2),
1633 hpd_regs(3),
1634 hpd_regs(4)
1635};
1636
1637static const struct dcn10_link_enc_shift le_shift = {
a771ded8
RL		 1638 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
1639 DPCS_DCN21_MASK_SH_LIST(__SHIFT)
91c665bd
BL		 1640};
1641
1642static const struct dcn10_link_enc_mask le_mask = {
a771ded8
RL		 1643 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
1644 DPCS_DCN21_MASK_SH_LIST(_MASK)
91c665bd
BL		 1645};
1646
bf7f5ac3
YMM		 1647static int map_transmitter_id_to_phy_instance(
1648 enum transmitter transmitter)
1649{
1650 switch (transmitter) {
1651 case TRANSMITTER_UNIPHY_A:
1652 return 0;
1653 break;
1654 case TRANSMITTER_UNIPHY_B:
1655 return 1;
1656 break;
1657 case TRANSMITTER_UNIPHY_C:
1658 return 2;
1659 break;
1660 case TRANSMITTER_UNIPHY_D:
1661 return 3;
1662 break;
1663 case TRANSMITTER_UNIPHY_E:
1664 return 4;
1665 break;
1666 default:
1667 ASSERT(0);
1668 return 0;
1669 }
1670}
1671
91c665bd
BL		 1672static struct link_encoder *dcn21_link_encoder_create(
1673 const struct encoder_init_data *enc_init_data)
1674{
1675 struct dcn21_link_encoder *enc21 =
1676 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
bf7f5ac3 1677 int link_regs_id;
91c665bd
BL		 1678
1679 if (!enc21)
1680 return NULL;
1681
bf7f5ac3
YMM		 1682 link_regs_id =
1683 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1684
91c665bd
BL		 1685 dcn21_link_encoder_construct(enc21,
1686 enc_init_data,
1687 &link_enc_feature,
bf7f5ac3 1688 &link_enc_regs[link_regs_id],
91c665bd
BL		 1689 &link_enc_aux_regs[enc_init_data->channel - 1],
1690 &link_enc_hpd_regs[enc_init_data->hpd_source],
1691 &le_shift,
1692 &le_mask);
1693
1694 return &enc21->enc10.base;
1695}
904fb6e0 1696
d4caa72e 1697static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_data *init_data)
904fb6e0 1698{
d4caa72e
AK		 1699 struct dce_panel_cntl *panel_cntl =
1700 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
904fb6e0 1701
d4caa72e 1702 if (!panel_cntl)
904fb6e0
AK		 1703 return NULL;
1704
d4caa72e 1705 dce_panel_cntl_construct(panel_cntl,
904fb6e0 1706 init_data,
d4caa72e
AK		 1707 &panel_cntl_regs[init_data->inst],
1708 &panel_cntl_shift,
1709 &panel_cntl_mask);
904fb6e0 1710
d4caa72e 1711 return &panel_cntl->base;
904fb6e0
AK		 1712}
1713
c0fb59a4
BL		 1714#define CTX ctx
1715
1716#define REG(reg_name) \
1717 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1718
1719static uint32_t read_pipe_fuses(struct dc_context *ctx)
1720{
1721 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1722 /* RV1 support max 4 pipes */
1723 value = value & 0xf;
1724 return value;
1725}
1726
8c357309 1727static int dcn21_populate_dml_pipes_from_context(
2f488884 1728 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)
8c357309 1729{
2f488884 1730 uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes);
8c357309
YS		 1731 int i;
1732
2a28fe92 1733 for (i = 0; i < pipe_cnt; i++) {
8c357309
YS		 1734
1735 pipes[i].pipe.src.hostvm = 1;
1736 pipes[i].pipe.src.gpuvm = 1;
1737 }
1738
1739 return pipe_cnt;
1740}
1741
8d8c82b6
JG		 1742enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1743{
1744 enum dc_status result = DC_OK;
1745
1746 if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {
1747 plane_state->dcc.enable = 1;
1748 /* align to our worst case block width */
1749 plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024;
1750 }
1751 result = dcn20_patch_unknown_plane_state(plane_state);
1752 return result;
1753}
1754
6f4e6361
BL		 1755static struct resource_funcs dcn21_res_pool_funcs = {
1756 .destroy = dcn21_destroy_resource_pool,
91c665bd 1757 .link_enc_create = dcn21_link_encoder_create,
d4caa72e 1758 .panel_cntl_create = dcn21_panel_cntl_create,
6f4e6361 1759 .validate_bandwidth = dcn21_validate_bandwidth,
8c357309 1760 .populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
6f4e6361
BL		 1761 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
1762 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1763 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1764 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
8d8c82b6 1765 .patch_unknown_plane_state = dcn21_patch_unknown_plane_state,
6f4e6361
BL		 1766 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1767 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1768 .update_bw_bounding_box = update_bw_bounding_box
1769};
1770
d9e32672 1771static bool dcn21_resource_construct(
6f4e6361
BL		 1772 uint8_t num_virtual_links,
1773 struct dc *dc,
1774 struct dcn21_resource_pool *pool)
1775{
c0fb59a4 1776 int i, j;
6f4e6361
BL		 1777 struct dc_context *ctx = dc->ctx;
1778 struct irq_service_init_data init_data;
c0fb59a4 1779 uint32_t pipe_fuses = read_pipe_fuses(ctx);
ff86391e 1780 uint32_t num_pipes;
6f4e6361
BL		 1781
1782 ctx->dc_bios->regs = &bios_regs;
1783
1784 pool->base.res_cap = &res_cap_rn;
1785#ifdef DIAGS_BUILD
1786 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1787 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc;
1788 pool->base.res_cap = &res_cap_rn_FPGA_4pipe;
1789#endif
1790
1791 pool->base.funcs = &dcn21_res_pool_funcs;
1792
1793 /*************************************************
1794 * Resource + asic cap harcoding *
1795 *************************************************/
1796 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1797
c0fb59a4
BL		 1798 /* max pipe num for ASIC before check pipe fuses */
1799 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1800
6f4e6361
BL		 1801 dc->caps.max_downscale_ratio = 200;
1802 dc->caps.i2c_speed_in_khz = 100;
1803 dc->caps.max_cursor_size = 256;
1804 dc->caps.dmdata_alloc_size = 2048;
6f4e6361
BL		 1805
1806 dc->caps.max_slave_planes = 1;
1807 dc->caps.post_blend_color_processing = true;
1808 dc->caps.force_dp_tps4_for_cp2520 = true;
c797ede0 1809 dc->caps.extended_aux_timeout_support = true;
3a1627b0 1810 dc->caps.dmcub_support = true;
3cfe9fb6 1811 dc->caps.is_apu = true;
6f4e6361 1812
a8bf7164
KK		 1813 /* Color pipeline capabilities */
1814 dc->caps.color.dpp.dcn_arch = 1;
1815 dc->caps.color.dpp.input_lut_shared = 0;
1816 dc->caps.color.dpp.icsc = 1;
1817 dc->caps.color.dpp.dgam_ram = 1;
1818 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1819 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1820 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1821 dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1822 dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1823 dc->caps.color.dpp.post_csc = 0;
1824 dc->caps.color.dpp.gamma_corr = 0;
1825
1826 dc->caps.color.dpp.hw_3d_lut = 1;
1827 dc->caps.color.dpp.ogam_ram = 1;
1828 // no OGAM ROM on DCN2
1829 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1830 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1831 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1832 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1833 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1834 dc->caps.color.dpp.ocsc = 0;
1835
1836 dc->caps.color.mpc.gamut_remap = 0;
1837 dc->caps.color.mpc.num_3dluts = 0;
1838 dc->caps.color.mpc.shared_3d_lut = 0;
1839 dc->caps.color.mpc.ogam_ram = 1;
1840 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1841 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1842 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1843 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1844 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1845 dc->caps.color.mpc.ocsc = 1;
1846
6f4e6361
BL		 1847 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1848 dc->debug = debug_defaults_drv;
1849 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1850 pool->base.pipe_count = 4;
1851 dc->debug = debug_defaults_diags;
1852 } else
1853 dc->debug = debug_defaults_diags;
1854
1855 // Init the vm_helper
1856 if (dc->vm_helper)
1857 vm_helper_init(dc->vm_helper, 16);
1858
1859 /*************************************************
1860 * Create resources *
1861 *************************************************/
1862
1863 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1864 dcn21_clock_source_create(ctx, ctx->dc_bios,
1865 CLOCK_SOURCE_COMBO_PHY_PLL0,
1866 &clk_src_regs[0], false);
1867 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1868 dcn21_clock_source_create(ctx, ctx->dc_bios,
1869 CLOCK_SOURCE_COMBO_PHY_PLL1,
1870 &clk_src_regs[1], false);
15add0c2
IZ		 1871 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
1872 dcn21_clock_source_create(ctx, ctx->dc_bios,
1873 CLOCK_SOURCE_COMBO_PHY_PLL2,
1874 &clk_src_regs[2], false);
6f4e6361
BL		 1875
1876 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
1877
1878 /* todo: not reuse phy_pll registers */
1879 pool->base.dp_clock_source =
1880 dcn21_clock_source_create(ctx, ctx->dc_bios,
1881 CLOCK_SOURCE_ID_DP_DTO,
1882 &clk_src_regs[0], true);
1883
1884 for (i = 0; i < pool->base.clk_src_count; i++) {
1885 if (pool->base.clock_sources[i] == NULL) {
1886 dm_error("DC: failed to create clock sources!\n");
1887 BREAK_TO_DEBUGGER();
1888 goto create_fail;
1889 }
1890 }
1891
1892 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1893 if (pool->base.dccg == NULL) {
1894 dm_error("DC: failed to create dccg!\n");
1895 BREAK_TO_DEBUGGER();
1896 goto create_fail;
1897 }
1898
501b4026 1899 if (!dc->config.disable_dmcu) {
16012806
WW		 1900 pool->base.dmcu = dcn21_dmcu_create(ctx,
1901 &dmcu_regs,
1902 &dmcu_shift,
1903 &dmcu_mask);
1904 if (pool->base.dmcu == NULL) {
1905 dm_error("DC: failed to create dmcu!\n");
1906 BREAK_TO_DEBUGGER();
1907 goto create_fail;
1908 }
a96562b0
AP		 1909
1910 dc->debug.dmub_command_table = false;
c0fb59a4
BL		 1911 }
1912
501b4026 1913 if (dc->config.disable_dmcu) {
9dac88d8
WW		 1914 pool->base.psr = dmub_psr_create(ctx);
1915
1916 if (pool->base.psr == NULL) {
1917 dm_error("DC: failed to create psr obj!\n");
1918 BREAK_TO_DEBUGGER();
1919 goto create_fail;
1920 }
1921 }
4c1a1335 1922
501b4026 1923 if (dc->config.disable_dmcu)
16012806
WW		 1924 pool->base.abm = dmub_abm_create(ctx,
1925 &abm_regs,
1926 &abm_shift,
1927 &abm_mask);
1928 else
1929 pool->base.abm = dce_abm_create(ctx,
c0fb59a4
BL		 1930 &abm_regs,
1931 &abm_shift,
1932 &abm_mask);
c0fb59a4 1933
6f4e6361
BL		 1934 pool->base.pp_smu = dcn21_pp_smu_create(ctx);
1935
ff86391e
MS		 1936 num_pipes = dcn2_1_ip.max_num_dpp;
1937
1938 for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
1939 if (pipe_fuses & 1 << i)
1940 num_pipes--;
1941 dcn2_1_ip.max_num_dpp = num_pipes;
1942 dcn2_1_ip.max_num_otg = num_pipes;
1943
6f4e6361
BL		 1944 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1945
1946 init_data.ctx = dc->ctx;
1947 pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
1948 if (!pool->base.irqs)
1949 goto create_fail;
1950
c0fb59a4 1951 j = 0;
6f4e6361
BL		 1952 /* mem input -> ipp -> dpp -> opp -> TG */
1953 for (i = 0; i < pool->base.pipe_count; i++) {
c0fb59a4
BL		 1954 /* if pipe is disabled, skip instance of HW pipe,
1955 * i.e, skip ASIC register instance
1956 */
1957 if ((pipe_fuses & (1 << i)) != 0)
1958 continue;
1959
b9f1246d
NA		 1960 pool->base.hubps[j] = dcn21_hubp_create(ctx, i);
1961 if (pool->base.hubps[j] == NULL) {
6f4e6361
BL		 1962 BREAK_TO_DEBUGGER();
1963 dm_error(
1964 "DC: failed to create memory input!\n");
1965 goto create_fail;
1966 }
1967
b9f1246d
NA		 1968 pool->base.ipps[j] = dcn21_ipp_create(ctx, i);
1969 if (pool->base.ipps[j] == NULL) {
6f4e6361
BL		 1970 BREAK_TO_DEBUGGER();
1971 dm_error(
1972 "DC: failed to create input pixel processor!\n");
1973 goto create_fail;
1974 }
1975
b9f1246d
NA		 1976 pool->base.dpps[j] = dcn21_dpp_create(ctx, i);
1977 if (pool->base.dpps[j] == NULL) {
6f4e6361
BL		 1978 BREAK_TO_DEBUGGER();
1979 dm_error(
1980 "DC: failed to create dpps!\n");
1981 goto create_fail;
1982 }
c0fb59a4 1983
b9f1246d
NA		 1984 pool->base.opps[j] = dcn21_opp_create(ctx, i);
1985 if (pool->base.opps[j] == NULL) {
c0fb59a4
BL		 1986 BREAK_TO_DEBUGGER();
1987 dm_error(
1988 "DC: failed to create output pixel processor!\n");
1989 goto create_fail;
1990 }
1991
b9f1246d 1992 pool->base.timing_generators[j] = dcn21_timing_generator_create(
c0fb59a4 1993 ctx, i);
b9f1246d 1994 if (pool->base.timing_generators[j] == NULL) {
c0fb59a4
BL		 1995 BREAK_TO_DEBUGGER();
1996 dm_error("DC: failed to create tg!\n");
1997 goto create_fail;
1998 }
1999 j++;
6f4e6361
BL		 2000 }
2001
2002 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2003 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
2004 if (pool->base.engines[i] == NULL) {
2005 BREAK_TO_DEBUGGER();
2006 dm_error(
2007 "DC:failed to create aux engine!!\n");
2008 goto create_fail;
2009 }
2010 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
2011 if (pool->base.hw_i2cs[i] == NULL) {
2012 BREAK_TO_DEBUGGER();
2013 dm_error(
2014 "DC:failed to create hw i2c!!\n");
2015 goto create_fail;
2016 }
2017 pool->base.sw_i2cs[i] = NULL;
2018 }
2019
c0fb59a4
BL		 2020 pool->base.timing_generator_count = j;
2021 pool->base.pipe_count = j;
2022 pool->base.mpcc_count = j;
6f4e6361
BL		 2023
2024 pool->base.mpc = dcn21_mpc_create(ctx);
2025 if (pool->base.mpc == NULL) {
2026 BREAK_TO_DEBUGGER();
2027 dm_error("DC: failed to create mpc!\n");
2028 goto create_fail;
2029 }
2030
2031 pool->base.hubbub = dcn21_hubbub_create(ctx);
2032 if (pool->base.hubbub == NULL) {
2033 BREAK_TO_DEBUGGER();
2034 dm_error("DC: failed to create hubbub!\n");
2035 goto create_fail;
2036 }
2037
6f4e6361
BL		 2038 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2039 pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
2040 if (pool->base.dscs[i] == NULL) {
2041 BREAK_TO_DEBUGGER();
2042 dm_error("DC: failed to create display stream compressor %d!\n", i);
2043 goto create_fail;
2044 }
2045 }
6f4e6361
BL		 2046
2047 if (!dcn20_dwbc_create(ctx, &pool->base)) {
2048 BREAK_TO_DEBUGGER();
2049 dm_error("DC: failed to create dwbc!\n");
2050 goto create_fail;
2051 }
2052 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
2053 BREAK_TO_DEBUGGER();
2054 dm_error("DC: failed to create mcif_wb!\n");
2055 goto create_fail;
2056 }
2057
2058 if (!resource_construct(num_virtual_links, dc, &pool->base,
2059 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2060 &res_create_funcs : &res_create_maximus_funcs)))
2061 goto create_fail;
2062
c0fb59a4 2063 dcn21_hw_sequencer_construct(dc);
6f4e6361
BL		 2064
2065 dc->caps.max_planes = pool->base.pipe_count;
2066
2067 for (i = 0; i < dc->caps.max_planes; ++i)
2068 dc->caps.planes[i] = plane_cap;
2069
2070 dc->cap_funcs = cap_funcs;
2071
2072 return true;
2073
2074create_fail:
2075
d9e32672 2076 dcn21_resource_destruct(pool);
6f4e6361
BL		 2077
2078 return false;
2079}
2080
2081struct resource_pool *dcn21_create_resource_pool(
2082 const struct dc_init_data *init_data,
2083 struct dc *dc)
2084{
2085 struct dcn21_resource_pool *pool =
2086 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);
2087
2088 if (!pool)
2089 return NULL;
2090
d9e32672 2091 if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
6f4e6361
BL		 2092 return &pool->base;
2093
2094 BREAK_TO_DEBUGGER();
2095 kfree(pool);
2096 return NULL;
2097}
Linux 6.x block layer and io_uring tree(s)