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drm/amd/display: Block ABM in case of eDP ODM
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / dc / dcn21 / dcn21_resource.c
CommitLineData
6f4e6361
BL		 1/*
2* Copyright 2018 Advanced Micro Devices, Inc.
6ca3928d 3 * Copyright 2019 Raptor Engineering, LLC
6f4e6361
BL		 4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
aec43402
AB		 27#include <linux/slab.h>
28
6f4e6361
BL		 29#include "dm_services.h"
30#include "dc.h"
31
78c77382
AK		 32#include "dcn21_init.h"
33
6f4e6361
BL		 34#include "resource.h"
35#include "include/irq_service_interface.h"
36#include "dcn20/dcn20_resource.h"
37
38#include "clk_mgr.h"
39#include "dcn10/dcn10_hubp.h"
40#include "dcn10/dcn10_ipp.h"
41#include "dcn20/dcn20_hubbub.h"
42#include "dcn20/dcn20_mpc.h"
43#include "dcn20/dcn20_hubp.h"
44#include "dcn21_hubp.h"
45#include "irq/dcn21/irq_service_dcn21.h"
46#include "dcn20/dcn20_dpp.h"
47#include "dcn20/dcn20_optc.h"
c0fb59a4 48#include "dcn21/dcn21_hwseq.h"
6f4e6361
BL		 49#include "dce110/dce110_hw_sequencer.h"
50#include "dcn20/dcn20_opp.h"
51#include "dcn20/dcn20_dsc.h"
91c665bd 52#include "dcn21/dcn21_link_encoder.h"
6f4e6361
BL		 53#include "dcn20/dcn20_stream_encoder.h"
54#include "dce/dce_clock_source.h"
55#include "dce/dce_audio.h"
56#include "dce/dce_hwseq.h"
57#include "virtual/virtual_stream_encoder.h"
58#include "dce110/dce110_resource.h"
59#include "dml/display_mode_vba.h"
60#include "dcn20/dcn20_dccg.h"
61#include "dcn21_hubbub.h"
62#include "dcn10/dcn10_resource.h"
15add0c2 63#include "dce110/dce110_resource.h"
d4caa72e 64#include "dce/dce_panel_cntl.h"
6f4e6361
BL		 65
66#include "dcn20/dcn20_dwb.h"
67#include "dcn20/dcn20_mmhubbub.h"
a771ded8
RL		 68#include "dpcs/dpcs_2_1_0_offset.h"
69#include "dpcs/dpcs_2_1_0_sh_mask.h"
6f4e6361
BL		 70
71#include "renoir_ip_offset.h"
72#include "dcn/dcn_2_1_0_offset.h"
73#include "dcn/dcn_2_1_0_sh_mask.h"
74
75#include "nbio/nbio_7_0_offset.h"
76
77#include "mmhub/mmhub_2_0_0_offset.h"
78#include "mmhub/mmhub_2_0_0_sh_mask.h"
79
80#include "reg_helper.h"
81#include "dce/dce_abm.h"
82#include "dce/dce_dmcu.h"
83#include "dce/dce_aux.h"
84#include "dce/dce_i2c.h"
85#include "dcn21_resource.h"
86#include "vm_helper.h"
87#include "dcn20/dcn20_vmid.h"
9dac88d8 88#include "dce/dmub_psr.h"
16012806 89#include "dce/dmub_abm.h"
6f4e6361 90
6f4e6361
BL		 91#define DC_LOGGER_INIT(logger)
92
93
94struct _vcs_dpi_ip_params_st dcn2_1_ip = {
652651ff 95 .odm_capable = 1,
8c357309
YS		 96 .gpuvm_enable = 1,
97 .hostvm_enable = 1,
6f4e6361
BL		 98 .gpuvm_max_page_table_levels = 1,
99 .hostvm_max_page_table_levels = 4,
100 .hostvm_cached_page_table_levels = 2,
6f4e6361 101 .num_dsc = 3,
6f4e6361
BL		 102 .rob_buffer_size_kbytes = 168,
103 .det_buffer_size_kbytes = 164,
104 .dpte_buffer_size_in_pte_reqs_luma = 44,
105 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
106 .dpp_output_buffer_pixels = 2560,
107 .opp_output_buffer_lines = 1,
108 .pixel_chunk_size_kbytes = 8,
109 .pte_enable = 1,
110 .max_page_table_levels = 4,
111 .pte_chunk_size_kbytes = 2,
112 .meta_chunk_size_kbytes = 2,
113 .writeback_chunk_size_kbytes = 2,
114 .line_buffer_size_bits = 789504,
115 .is_line_buffer_bpp_fixed = 0,
116 .line_buffer_fixed_bpp = 0,
117 .dcc_supported = true,
118 .max_line_buffer_lines = 12,
119 .writeback_luma_buffer_size_kbytes = 12,
120 .writeback_chroma_buffer_size_kbytes = 8,
121 .writeback_chroma_line_buffer_width_pixels = 4,
122 .writeback_max_hscl_ratio = 1,
123 .writeback_max_vscl_ratio = 1,
124 .writeback_min_hscl_ratio = 1,
125 .writeback_min_vscl_ratio = 1,
126 .writeback_max_hscl_taps = 12,
127 .writeback_max_vscl_taps = 12,
128 .writeback_line_buffer_luma_buffer_size = 0,
129 .writeback_line_buffer_chroma_buffer_size = 14643,
130 .cursor_buffer_size = 8,
131 .cursor_chunk_size = 2,
132 .max_num_otg = 4,
133 .max_num_dpp = 4,
134 .max_num_wb = 1,
135 .max_dchub_pscl_bw_pix_per_clk = 4,
136 .max_pscl_lb_bw_pix_per_clk = 2,
137 .max_lb_vscl_bw_pix_per_clk = 4,
138 .max_vscl_hscl_bw_pix_per_clk = 4,
139 .max_hscl_ratio = 4,
140 .max_vscl_ratio = 4,
141 .hscl_mults = 4,
142 .vscl_mults = 4,
143 .max_hscl_taps = 8,
144 .max_vscl_taps = 8,
145 .dispclk_ramp_margin_percent = 1,
146 .underscan_factor = 1.10,
147 .min_vblank_lines = 32, //
148 .dppclk_delay_subtotal = 77, //
149 .dppclk_delay_scl_lb_only = 16,
150 .dppclk_delay_scl = 50,
151 .dppclk_delay_cnvc_formatter = 8,
152 .dppclk_delay_cnvc_cursor = 6,
153 .dispclk_delay_subtotal = 87, //
154 .dcfclk_cstate_latency = 10, // SRExitTime
155 .max_inter_dcn_tile_repeaters = 8,
156
157 .xfc_supported = false,
158 .xfc_fill_bw_overhead_percent = 10.0,
159 .xfc_fill_constant_bytes = 0,
8f174fdb
YS		 160 .ptoi_supported = 0,
161 .number_of_cursors = 1,
6f4e6361
BL		 162};
163
164struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
165 .clock_limits = {
166 {
167 .state = 0,
a39a5816
EY		 168 .dcfclk_mhz = 400.0,
169 .fabricclk_mhz = 400.0,
170 .dispclk_mhz = 600.0,
171 .dppclk_mhz = 400.00,
6f4e6361
BL		 172 .phyclk_mhz = 600.0,
173 .socclk_mhz = 278.0,
174 .dscclk_mhz = 205.67,
175 .dram_speed_mts = 1600.0,
176 },
177 {
178 .state = 1,
a39a5816
EY		 179 .dcfclk_mhz = 464.52,
180 .fabricclk_mhz = 800.0,
181 .dispclk_mhz = 654.55,
182 .dppclk_mhz = 626.09,
6f4e6361
BL		 183 .phyclk_mhz = 600.0,
184 .socclk_mhz = 278.0,
185 .dscclk_mhz = 205.67,
186 .dram_speed_mts = 1600.0,
187 },
188 {
189 .state = 2,
a39a5816
EY		 190 .dcfclk_mhz = 514.29,
191 .fabricclk_mhz = 933.0,
192 .dispclk_mhz = 757.89,
193 .dppclk_mhz = 685.71,
194 .phyclk_mhz = 600.0,
6f4e6361
BL		 195 .socclk_mhz = 278.0,
196 .dscclk_mhz = 287.67,
a39a5816 197 .dram_speed_mts = 1866.0,
6f4e6361
BL		 198 },
199 {
200 .state = 3,
a39a5816
EY		 201 .dcfclk_mhz = 576.00,
202 .fabricclk_mhz = 1067.0,
203 .dispclk_mhz = 847.06,
204 .dppclk_mhz = 757.89,
205 .phyclk_mhz = 600.0,
6f4e6361
BL		 206 .socclk_mhz = 715.0,
207 .dscclk_mhz = 318.334,
a39a5816 208 .dram_speed_mts = 2134.0,
6f4e6361
BL		 209 },
210 {
211 .state = 4,
a39a5816
EY		 212 .dcfclk_mhz = 626.09,
213 .fabricclk_mhz = 1200.0,
214 .dispclk_mhz = 900.00,
215 .dppclk_mhz = 847.06,
216 .phyclk_mhz = 810.0,
217 .socclk_mhz = 953.0,
218 .dscclk_mhz = 489.0,
219 .dram_speed_mts = 2400.0,
220 },
221 {
222 .state = 5,
223 .dcfclk_mhz = 685.71,
224 .fabricclk_mhz = 1333.0,
225 .dispclk_mhz = 1028.57,
226 .dppclk_mhz = 960.00,
227 .phyclk_mhz = 810.0,
228 .socclk_mhz = 278.0,
229 .dscclk_mhz = 287.67,
230 .dram_speed_mts = 2666.0,
231 },
232 {
233 .state = 6,
234 .dcfclk_mhz = 757.89,
235 .fabricclk_mhz = 1467.0,
236 .dispclk_mhz = 1107.69,
237 .dppclk_mhz = 1028.57,
238 .phyclk_mhz = 810.0,
239 .socclk_mhz = 715.0,
240 .dscclk_mhz = 318.334,
241 .dram_speed_mts = 3200.0,
242 },
243 {
244 .state = 7,
245 .dcfclk_mhz = 847.06,
6f4e6361 246 .fabricclk_mhz = 1600.0,
652651ff 247 .dispclk_mhz = 1395.0,
a39a5816 248 .dppclk_mhz = 1285.00,
652651ff 249 .phyclk_mhz = 1325.0,
6f4e6361 250 .socclk_mhz = 953.0,
652651ff 251 .dscclk_mhz = 489.0,
6f4e6361
BL		 252 .dram_speed_mts = 4266.0,
253 },
254 /*Extra state, no dispclk ramping*/
255 {
a39a5816
EY		 256 .state = 8,
257 .dcfclk_mhz = 847.06,
6f4e6361 258 .fabricclk_mhz = 1600.0,
652651ff
BL		 259 .dispclk_mhz = 1395.0,
260 .dppclk_mhz = 1285.0,
261 .phyclk_mhz = 1325.0,
6f4e6361 262 .socclk_mhz = 953.0,
652651ff 263 .dscclk_mhz = 489.0,
6f4e6361
BL		 264 .dram_speed_mts = 4266.0,
265 },
266
267 },
268
652651ff
BL		 269 .sr_exit_time_us = 12.5,
270 .sr_enter_plus_exit_time_us = 17.0,
6f4e6361
BL		 271 .urgent_latency_us = 4.0,
272 .urgent_latency_pixel_data_only_us = 4.0,
273 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
274 .urgent_latency_vm_data_only_us = 4.0,
275 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
276 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
277 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
278 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
279 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
280 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
281 .max_avg_sdp_bw_use_normal_percent = 60.0,
282 .max_avg_dram_bw_use_normal_percent = 100.0,
283 .writeback_latency_us = 12.0,
284 .max_request_size_bytes = 256,
285 .dram_channel_width_bytes = 4,
286 .fabric_datapath_to_dcn_data_return_bytes = 32,
287 .dcn_downspread_percent = 0.5,
77ef333e 288 .downspread_percent = 0.38,
6f4e6361
BL		 289 .dram_page_open_time_ns = 50.0,
290 .dram_rw_turnaround_time_ns = 17.5,
291 .dram_return_buffer_per_channel_bytes = 8192,
292 .round_trip_ping_latency_dcfclk_cycles = 128,
293 .urgent_out_of_order_return_per_channel_bytes = 4096,
294 .channel_interleave_bytes = 256,
295 .num_banks = 8,
296 .num_chans = 4,
297 .vmm_page_size_bytes = 4096,
298 .dram_clock_change_latency_us = 23.84,
299 .return_bus_width_bytes = 64,
0beb5403 300 .dispclk_dppclk_vco_speed_mhz = 3600,
6f4e6361
BL		 301 .xfc_bus_transport_time_us = 4,
302 .xfc_xbuf_latency_tolerance_us = 4,
303 .use_urgent_burst_bw = 1,
c42656f8 304 .num_states = 8
6f4e6361
BL		 305};
306
307#ifndef MAX
308#define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
309#endif
310#ifndef MIN
311#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
312#endif
313
314/* begin *********************
315 * macros to expend register list macro defined in HW object header file */
316
317/* DCN */
318/* TODO awful hack. fixup dcn20_dwb.h */
319#undef BASE_INNER
320#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
321
322#define BASE(seg) BASE_INNER(seg)
323
324#define SR(reg_name)\
325 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
326 mm ## reg_name
327
328#define SRI(reg_name, block, id)\
329 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
330 mm ## block ## id ## _ ## reg_name
331
332#define SRIR(var_name, reg_name, block, id)\
333 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
334 mm ## block ## id ## _ ## reg_name
335
336#define SRII(reg_name, block, id)\
337 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
338 mm ## block ## id ## _ ## reg_name
339
340#define DCCG_SRII(reg_name, block, id)\
341 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
342 mm ## block ## id ## _ ## reg_name
343
1e461c37
AC		 344#define VUPDATE_SRII(reg_name, block, id)\
345 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
346 mm ## reg_name ## _ ## block ## id
347
6f4e6361
BL		 348/* NBIO */
349#define NBIO_BASE_INNER(seg) \
350 NBIF0_BASE__INST0_SEG ## seg
351
352#define NBIO_BASE(seg) \
353 NBIO_BASE_INNER(seg)
354
355#define NBIO_SR(reg_name)\
356 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
357 mm ## reg_name
358
359/* MMHUB */
360#define MMHUB_BASE_INNER(seg) \
361 MMHUB_BASE__INST0_SEG ## seg
362
363#define MMHUB_BASE(seg) \
364 MMHUB_BASE_INNER(seg)
365
366#define MMHUB_SR(reg_name)\
367 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
368 mmMM ## reg_name
369
370#define clk_src_regs(index, pllid)\
371[index] = {\
372 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
373}
374
375static const struct dce110_clk_src_regs clk_src_regs[] = {
376 clk_src_regs(0, A),
377 clk_src_regs(1, B),
378 clk_src_regs(2, C),
379 clk_src_regs(3, D),
380 clk_src_regs(4, E),
381};
382
383static const struct dce110_clk_src_shift cs_shift = {
384 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
385};
386
387static const struct dce110_clk_src_mask cs_mask = {
388 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
389};
390
391static const struct bios_registers bios_regs = {
392 NBIO_SR(BIOS_SCRATCH_3),
393 NBIO_SR(BIOS_SCRATCH_6)
394};
395
c0fb59a4 396static const struct dce_dmcu_registers dmcu_regs = {
a7e3658e 397 DMCU_DCN20_REG_LIST()
c0fb59a4
BL		 398};
399
400static const struct dce_dmcu_shift dmcu_shift = {
401 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
402};
403
404static const struct dce_dmcu_mask dmcu_mask = {
405 DMCU_MASK_SH_LIST_DCN10(_MASK)
406};
407
408static const struct dce_abm_registers abm_regs = {
409 ABM_DCN20_REG_LIST()
410};
411
412static const struct dce_abm_shift abm_shift = {
413 ABM_MASK_SH_LIST_DCN20(__SHIFT)
414};
415
416static const struct dce_abm_mask abm_mask = {
417 ABM_MASK_SH_LIST_DCN20(_MASK)
418};
419
6f4e6361
BL		 420#define audio_regs(id)\
421[id] = {\
422 AUD_COMMON_REG_LIST(id)\
423}
424
425static const struct dce_audio_registers audio_regs[] = {
426 audio_regs(0),
427 audio_regs(1),
428 audio_regs(2),
429 audio_regs(3),
430 audio_regs(4),
431 audio_regs(5),
432};
433
434#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
435 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
436 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
437 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
438
439static const struct dce_audio_shift audio_shift = {
440 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
441};
442
443static const struct dce_audio_mask audio_mask = {
444 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
445};
446
447static const struct dccg_registers dccg_regs = {
448 DCCG_COMMON_REG_LIST_DCN_BASE()
449};
450
451static const struct dccg_shift dccg_shift = {
452 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
453};
454
455static const struct dccg_mask dccg_mask = {
456 DCCG_MASK_SH_LIST_DCN2(_MASK)
457};
458
459#define opp_regs(id)\
460[id] = {\
461 OPP_REG_LIST_DCN20(id),\
462}
463
464static const struct dcn20_opp_registers opp_regs[] = {
465 opp_regs(0),
466 opp_regs(1),
467 opp_regs(2),
468 opp_regs(3),
469 opp_regs(4),
470 opp_regs(5),
471};
472
473static const struct dcn20_opp_shift opp_shift = {
474 OPP_MASK_SH_LIST_DCN20(__SHIFT)
475};
476
477static const struct dcn20_opp_mask opp_mask = {
478 OPP_MASK_SH_LIST_DCN20(_MASK)
479};
480
481#define tg_regs(id)\
482[id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
483
484static const struct dcn_optc_registers tg_regs[] = {
485 tg_regs(0),
486 tg_regs(1),
487 tg_regs(2),
488 tg_regs(3)
489};
490
491static const struct dcn_optc_shift tg_shift = {
492 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
493};
494
495static const struct dcn_optc_mask tg_mask = {
496 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
497};
498
499static const struct dcn20_mpc_registers mpc_regs = {
500 MPC_REG_LIST_DCN2_0(0),
501 MPC_REG_LIST_DCN2_0(1),
502 MPC_REG_LIST_DCN2_0(2),
503 MPC_REG_LIST_DCN2_0(3),
504 MPC_REG_LIST_DCN2_0(4),
505 MPC_REG_LIST_DCN2_0(5),
506 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
507 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
508 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
e8027e08
NA		 509 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
510 MPC_DBG_REG_LIST_DCN2_0()
6f4e6361
BL		 511};
512
513static const struct dcn20_mpc_shift mpc_shift = {
c1e34175
NA		 514 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
515 MPC_DEBUG_REG_LIST_SH_DCN20
6f4e6361
BL		 516};
517
518static const struct dcn20_mpc_mask mpc_mask = {
c1e34175
NA		 519 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
520 MPC_DEBUG_REG_LIST_MASK_DCN20
6f4e6361
BL		 521};
522
523#define hubp_regs(id)\
524[id] = {\
525 HUBP_REG_LIST_DCN21(id)\
526}
527
528static const struct dcn_hubp2_registers hubp_regs[] = {
529 hubp_regs(0),
530 hubp_regs(1),
531 hubp_regs(2),
532 hubp_regs(3)
533};
534
535static const struct dcn_hubp2_shift hubp_shift = {
536 HUBP_MASK_SH_LIST_DCN21(__SHIFT)
537};
538
539static const struct dcn_hubp2_mask hubp_mask = {
540 HUBP_MASK_SH_LIST_DCN21(_MASK)
541};
542
543static const struct dcn_hubbub_registers hubbub_reg = {
544 HUBBUB_REG_LIST_DCN21()
545};
546
547static const struct dcn_hubbub_shift hubbub_shift = {
548 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
549};
550
551static const struct dcn_hubbub_mask hubbub_mask = {
552 HUBBUB_MASK_SH_LIST_DCN21(_MASK)
553};
554
555
556#define vmid_regs(id)\
557[id] = {\
558 DCN20_VMID_REG_LIST(id)\
559}
560
561static const struct dcn_vmid_registers vmid_regs[] = {
562 vmid_regs(0),
563 vmid_regs(1),
564 vmid_regs(2),
565 vmid_regs(3),
566 vmid_regs(4),
567 vmid_regs(5),
568 vmid_regs(6),
569 vmid_regs(7),
570 vmid_regs(8),
571 vmid_regs(9),
572 vmid_regs(10),
573 vmid_regs(11),
574 vmid_regs(12),
575 vmid_regs(13),
576 vmid_regs(14),
577 vmid_regs(15)
578};
579
580static const struct dcn20_vmid_shift vmid_shifts = {
581 DCN20_VMID_MASK_SH_LIST(__SHIFT)
582};
583
584static const struct dcn20_vmid_mask vmid_masks = {
585 DCN20_VMID_MASK_SH_LIST(_MASK)
586};
587
6f4e6361
BL		 588#define dsc_regsDCN20(id)\
589[id] = {\
590 DSC_REG_LIST_DCN20(id)\
591}
592
593static const struct dcn20_dsc_registers dsc_regs[] = {
594 dsc_regsDCN20(0),
595 dsc_regsDCN20(1),
596 dsc_regsDCN20(2),
597 dsc_regsDCN20(3),
598 dsc_regsDCN20(4),
599 dsc_regsDCN20(5)
600};
601
602static const struct dcn20_dsc_shift dsc_shift = {
603 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
604};
605
606static const struct dcn20_dsc_mask dsc_mask = {
607 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
608};
6f4e6361
BL		 609
610#define ipp_regs(id)\
611[id] = {\
612 IPP_REG_LIST_DCN20(id),\
613}
614
615static const struct dcn10_ipp_registers ipp_regs[] = {
616 ipp_regs(0),
617 ipp_regs(1),
618 ipp_regs(2),
619 ipp_regs(3),
620};
621
622static const struct dcn10_ipp_shift ipp_shift = {
623 IPP_MASK_SH_LIST_DCN20(__SHIFT)
624};
625
626static const struct dcn10_ipp_mask ipp_mask = {
627 IPP_MASK_SH_LIST_DCN20(_MASK),
628};
629
630#define opp_regs(id)\
631[id] = {\
632 OPP_REG_LIST_DCN20(id),\
633}
634
635
636#define aux_engine_regs(id)\
637[id] = {\
638 AUX_COMMON_REG_LIST0(id), \
639 .AUXN_IMPCAL = 0, \
640 .AUXP_IMPCAL = 0, \
641 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
642}
643
644static const struct dce110_aux_registers aux_engine_regs[] = {
645 aux_engine_regs(0),
646 aux_engine_regs(1),
647 aux_engine_regs(2),
648 aux_engine_regs(3),
649 aux_engine_regs(4),
650};
651
652#define tf_regs(id)\
653[id] = {\
654 TF_REG_LIST_DCN20(id),\
d9eb70ae 655 TF_REG_LIST_DCN20_COMMON_APPEND(id),\
6f4e6361
BL		 656}
657
658static const struct dcn2_dpp_registers tf_regs[] = {
659 tf_regs(0),
660 tf_regs(1),
661 tf_regs(2),
662 tf_regs(3),
663};
664
665static const struct dcn2_dpp_shift tf_shift = {
d9eb70ae 666 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
c1e34175 667 TF_DEBUG_REG_LIST_SH_DCN20
6f4e6361
BL		 668};
669
670static const struct dcn2_dpp_mask tf_mask = {
d9eb70ae 671 TF_REG_LIST_SH_MASK_DCN20(_MASK),
c1e34175 672 TF_DEBUG_REG_LIST_MASK_DCN20
6f4e6361
BL		 673};
674
675#define stream_enc_regs(id)\
676[id] = {\
677 SE_DCN2_REG_LIST(id)\
678}
679
680static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
681 stream_enc_regs(0),
682 stream_enc_regs(1),
683 stream_enc_regs(2),
684 stream_enc_regs(3),
685 stream_enc_regs(4),
686};
687
8276dd87 688static const struct dce110_aux_registers_shift aux_shift = {
689 DCN_AUX_MASK_SH_LIST(__SHIFT)
690};
691
692static const struct dce110_aux_registers_mask aux_mask = {
693 DCN_AUX_MASK_SH_LIST(_MASK)
694};
695
6f4e6361
BL		 696static const struct dcn10_stream_encoder_shift se_shift = {
697 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
698};
699
700static const struct dcn10_stream_encoder_mask se_mask = {
701 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
702};
703
44e149bb
AD		 704static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
705
8c357309 706static int dcn21_populate_dml_pipes_from_context(
2f488884 707 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes);
8c357309 708
6f4e6361
BL		 709static struct input_pixel_processor *dcn21_ipp_create(
710 struct dc_context *ctx, uint32_t inst)
711{
712 struct dcn10_ipp *ipp =
713 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
714
715 if (!ipp) {
716 BREAK_TO_DEBUGGER();
717 return NULL;
718 }
719
720 dcn20_ipp_construct(ipp, ctx, inst,
721 &ipp_regs[inst], &ipp_shift, &ipp_mask);
722 return &ipp->base;
723}
724
725static struct dpp *dcn21_dpp_create(
726 struct dc_context *ctx,
727 uint32_t inst)
728{
729 struct dcn20_dpp *dpp =
730 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
731
732 if (!dpp)
733 return NULL;
734
735 if (dpp2_construct(dpp, ctx, inst,
736 &tf_regs[inst], &tf_shift, &tf_mask))
737 return &dpp->base;
738
739 BREAK_TO_DEBUGGER();
740 kfree(dpp);
741 return NULL;
742}
743
744static struct dce_aux *dcn21_aux_engine_create(
745 struct dc_context *ctx,
746 uint32_t inst)
747{
748 struct aux_engine_dce110 *aux_engine =
749 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
750
751 if (!aux_engine)
752 return NULL;
753
754 dce110_aux_engine_construct(aux_engine, ctx, inst,
755 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
8276dd87 756 &aux_engine_regs[inst],
757 &aux_mask,
f6040a43 758 &aux_shift,
759 ctx->dc->caps.extended_aux_timeout_support);
6f4e6361
BL		 760
761 return &aux_engine->base;
762}
763
764#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
765
766static const struct dce_i2c_registers i2c_hw_regs[] = {
767 i2c_inst_regs(1),
768 i2c_inst_regs(2),
769 i2c_inst_regs(3),
770 i2c_inst_regs(4),
771 i2c_inst_regs(5),
772};
773
774static const struct dce_i2c_shift i2c_shifts = {
775 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
776};
777
778static const struct dce_i2c_mask i2c_masks = {
779 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
780};
781
782struct dce_i2c_hw *dcn21_i2c_hw_create(
783 struct dc_context *ctx,
784 uint32_t inst)
785{
786 struct dce_i2c_hw *dce_i2c_hw =
787 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
788
789 if (!dce_i2c_hw)
790 return NULL;
791
792 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
793 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
794
795 return dce_i2c_hw;
796}
797
798static const struct resource_caps res_cap_rn = {
799 .num_timing_generator = 4,
800 .num_opp = 4,
801 .num_video_plane = 4,
b356843e 802 .num_audio = 4, // 4 audio endpoints. 4 audio streams
6f4e6361
BL		 803 .num_stream_encoder = 5,
804 .num_pll = 5, // maybe 3 because the last two used for USB-c
805 .num_dwb = 1,
806 .num_ddc = 5,
fdcf62fb 807 .num_vmid = 16,
6f4e6361 808 .num_dsc = 3,
6f4e6361
BL		 809};
810
811#ifdef DIAGS_BUILD
812static const struct resource_caps res_cap_rn_FPGA_4pipe = {
813 .num_timing_generator = 4,
814 .num_opp = 4,
815 .num_video_plane = 4,
816 .num_audio = 7,
817 .num_stream_encoder = 4,
818 .num_pll = 4,
819 .num_dwb = 1,
820 .num_ddc = 4,
821 .num_dsc = 0,
822};
823
824static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
825 .num_timing_generator = 2,
826 .num_opp = 2,
827 .num_video_plane = 2,
828 .num_audio = 7,
829 .num_stream_encoder = 2,
830 .num_pll = 4,
831 .num_dwb = 1,
832 .num_ddc = 4,
6f4e6361 833 .num_dsc = 2,
6f4e6361
BL		 834};
835#endif
836
837static const struct dc_plane_cap plane_cap = {
838 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
839 .blends_with_above = true,
840 .blends_with_below = true,
841 .per_pixel_alpha = true,
842
843 .pixel_format_support = {
844 .argb8888 = true,
845 .nv12 = true,
cbec6477
SW		 846 .fp16 = true,
847 .p010 = true
6f4e6361
BL		 848 },
849
850 .max_upscale_factor = {
851 .argb8888 = 16000,
852 .nv12 = 16000,
853 .fp16 = 16000
854 },
855
856 .max_downscale_factor = {
857 .argb8888 = 250,
858 .nv12 = 250,
859 .fp16 = 250
3b26ca2d
IK		 860 },
861 64,
862 64
6f4e6361
BL		 863};
864
865static const struct dc_debug_options debug_defaults_drv = {
f0a574c9 866 .disable_dmcu = false,
6f4e6361
BL		 867 .force_abm_enable = false,
868 .timing_trace = false,
869 .clock_trace = true,
870 .disable_pplib_clock_request = true,
cab5dec4 871 .min_disp_clk_khz = 100000,
6f4e6361 872 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
4d25a0d5 873 .force_single_disp_pipe_split = false,
6f4e6361
BL		 874 .disable_dcc = DCC_ENABLE,
875 .vsr_support = true,
876 .performance_trace = false,
947daab2 877 .max_downscale_src_width = 4096,
6f4e6361
BL		 878 .disable_pplib_wm_range = false,
879 .scl_reset_length10 = true,
880 .sanity_checks = true,
57133a28 881 .disable_48mhz_pwrdwn = false,
ee765924 882 .usbc_combo_phy_reset_wa = true
6f4e6361
BL		 883};
884
885static const struct dc_debug_options debug_defaults_diags = {
f0a574c9 886 .disable_dmcu = false,
6f4e6361
BL		 887 .force_abm_enable = false,
888 .timing_trace = true,
889 .clock_trace = true,
890 .disable_dpp_power_gate = true,
891 .disable_hubp_power_gate = true,
892 .disable_clock_gate = true,
893 .disable_pplib_clock_request = true,
894 .disable_pplib_wm_range = true,
895 .disable_stutter = true,
896 .disable_48mhz_pwrdwn = true,
091018a5
AC		 897 .disable_psr = true,
898 .enable_tri_buf = true
6f4e6361
BL		 899};
900
901enum dcn20_clk_src_array_id {
902 DCN20_CLK_SRC_PLL0,
903 DCN20_CLK_SRC_PLL1,
15add0c2 904 DCN20_CLK_SRC_PLL2,
6f4e6361
BL		 905 DCN20_CLK_SRC_TOTAL_DCN21
906};
907
d9e32672 908static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
6f4e6361
BL		 909{
910 unsigned int i;
911
912 for (i = 0; i < pool->base.stream_enc_count; i++) {
913 if (pool->base.stream_enc[i] != NULL) {
914 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
915 pool->base.stream_enc[i] = NULL;
916 }
917 }
918
6f4e6361
BL		 919 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
920 if (pool->base.dscs[i] != NULL)
921 dcn20_dsc_destroy(&pool->base.dscs[i]);
922 }
6f4e6361
BL		 923
924 if (pool->base.mpc != NULL) {
925 kfree(TO_DCN20_MPC(pool->base.mpc));
926 pool->base.mpc = NULL;
927 }
928 if (pool->base.hubbub != NULL) {
929 kfree(pool->base.hubbub);
930 pool->base.hubbub = NULL;
931 }
932 for (i = 0; i < pool->base.pipe_count; i++) {
933 if (pool->base.dpps[i] != NULL)
934 dcn20_dpp_destroy(&pool->base.dpps[i]);
935
936 if (pool->base.ipps[i] != NULL)
937 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
938
939 if (pool->base.hubps[i] != NULL) {
940 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
941 pool->base.hubps[i] = NULL;
942 }
943
944 if (pool->base.irqs != NULL) {
945 dal_irq_service_destroy(&pool->base.irqs);
946 }
947 }
948
949 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
950 if (pool->base.engines[i] != NULL)
951 dce110_engine_destroy(&pool->base.engines[i]);
952 if (pool->base.hw_i2cs[i] != NULL) {
953 kfree(pool->base.hw_i2cs[i]);
954 pool->base.hw_i2cs[i] = NULL;
955 }
956 if (pool->base.sw_i2cs[i] != NULL) {
957 kfree(pool->base.sw_i2cs[i]);
958 pool->base.sw_i2cs[i] = NULL;
959 }
960 }
961
962 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
963 if (pool->base.opps[i] != NULL)
964 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
965 }
966
967 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
968 if (pool->base.timing_generators[i] != NULL) {
969 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
970 pool->base.timing_generators[i] = NULL;
971 }
972 }
973
974 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
975 if (pool->base.dwbc[i] != NULL) {
976 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
977 pool->base.dwbc[i] = NULL;
978 }
979 if (pool->base.mcif_wb[i] != NULL) {
980 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
981 pool->base.mcif_wb[i] = NULL;
982 }
983 }
984
985 for (i = 0; i < pool->base.audio_count; i++) {
986 if (pool->base.audios[i])
987 dce_aud_destroy(&pool->base.audios[i]);
988 }
989
990 for (i = 0; i < pool->base.clk_src_count; i++) {
991 if (pool->base.clock_sources[i] != NULL) {
992 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
993 pool->base.clock_sources[i] = NULL;
994 }
995 }
996
997 if (pool->base.dp_clock_source != NULL) {
998 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
999 pool->base.dp_clock_source = NULL;
1000 }
1001
16012806 1002 if (pool->base.abm != NULL) {
501b4026 1003 if (pool->base.abm->ctx->dc->config.disable_dmcu)
16012806
WW		 1004 dmub_abm_destroy(&pool->base.abm);
1005 else
1006 dce_abm_destroy(&pool->base.abm);
1007 }
6f4e6361
BL		 1008
1009 if (pool->base.dmcu != NULL)
1010 dce_dmcu_destroy(&pool->base.dmcu);
1011
9dac88d8
WW		 1012 if (pool->base.psr != NULL)
1013 dmub_psr_destroy(&pool->base.psr);
1014
6f4e6361
BL		 1015 if (pool->base.dccg != NULL)
1016 dcn_dccg_destroy(&pool->base.dccg);
1017
1018 if (pool->base.pp_smu != NULL)
44e149bb 1019 dcn21_pp_smu_destroy(&pool->base.pp_smu);
6f4e6361
BL		 1020}
1021
1022
1023static void calculate_wm_set_for_vlevel(
1024 int vlevel,
1025 struct wm_range_table_entry *table_entry,
1026 struct dcn_watermarks *wm_set,
1027 struct display_mode_lib *dml,
1028 display_e2e_pipe_params_st *pipes,
1029 int pipe_cnt)
1030{
1031 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
1032
1033 ASSERT(vlevel < dml->soc.num_states);
1034 /* only pipe 0 is read for voltage and dcf/soc clocks */
1035 pipes[0].clks_cfg.voltage = vlevel;
1036 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
1037 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
1038
1039 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
d3511fd0
EY		 1040 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
1041 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
6f4e6361
BL		 1042
1043 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
1044 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
1045 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
1046 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1047 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
6f4e6361
BL		 1048 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
1049 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
b617b265 1050 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
6f4e6361
BL		 1051 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
1052
1053}
1054
15fdbcc5
LH		 1055static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
1056{
d3511fd0
EY		 1057 int i;
1058
6ca3928d
TP		 1059 DC_FP_START();
1060
15fdbcc5 1061 if (dc->bb_overrides.sr_exit_time_ns) {
d3511fd0
EY		 1062 for (i = 0; i < WM_SET_COUNT; i++) {
1063 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
1064 dc->bb_overrides.sr_exit_time_ns / 1000.0;
1065 }
15fdbcc5
LH		 1066 }
1067
1068 if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
d3511fd0
EY		 1069 for (i = 0; i < WM_SET_COUNT; i++) {
1070 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
1071 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
1072 }
15fdbcc5
LH		 1073 }
1074
1075 if (dc->bb_overrides.urgent_latency_ns) {
1076 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
1077 }
1078
1079 if (dc->bb_overrides.dram_clock_change_latency_ns) {
580c8be2
JG		 1080 for (i = 0; i < WM_SET_COUNT; i++) {
1081 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
15fdbcc5 1082 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
580c8be2 1083 }
15fdbcc5 1084 }
580c8be2 1085
6ca3928d 1086 DC_FP_END();
15fdbcc5
LH		 1087}
1088
6f4e6361
BL		 1089void dcn21_calculate_wm(
1090 struct dc *dc, struct dc_state *context,
1091 display_e2e_pipe_params_st *pipes,
1092 int *out_pipe_cnt,
1093 int *pipe_split_from,
1094 int vlevel_req)
1095{
1096 int pipe_cnt, i, pipe_idx;
1097 int vlevel, vlevel_max;
1098 struct wm_range_table_entry *table_entry;
1099 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
1100
1101 ASSERT(bw_params);
1102
15fdbcc5
LH		 1103 patch_bounding_box(dc, &context->bw_ctx.dml.soc);
1104
6f4e6361
BL		 1105 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1106 if (!context->res_ctx.pipe_ctx[i].stream)
1107 continue;
1108
1109 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1110 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
1111
1112 if (pipe_split_from[i] < 0) {
1113 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1114 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1115 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1116 pipes[pipe_cnt].pipe.dest.odm_combine =
1117 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
1118 else
1119 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1120 pipe_idx++;
1121 } else {
1122 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1123 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1124 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1125 pipes[pipe_cnt].pipe.dest.odm_combine =
1126 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];
1127 else
1128 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1129 }
1130 pipe_cnt++;
1131 }
1132
1133 if (pipe_cnt != pipe_idx) {
1134 if (dc->res_pool->funcs->populate_dml_pipes)
1135 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2f488884 1136 context, pipes);
6f4e6361 1137 else
8c357309 1138 pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
2f488884 1139 context, pipes);
6f4e6361
BL		 1140 }
1141
1142 *out_pipe_cnt = pipe_cnt;
1143
1144 vlevel_max = bw_params->clk_table.num_entries - 1;
1145
1146
1147 /* WM Set D */
1148 table_entry = &bw_params->wm_table.entries[WM_D];
1149 if (table_entry->wm_type == WM_TYPE_RETRAINING)
1150 vlevel = 0;
1151 else
1152 vlevel = vlevel_max;
1153 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
1154 &context->bw_ctx.dml, pipes, pipe_cnt);
1155 /* WM Set C */
1156 table_entry = &bw_params->wm_table.entries[WM_C];
1157 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
1158 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
1159 &context->bw_ctx.dml, pipes, pipe_cnt);
1160 /* WM Set B */
1161 table_entry = &bw_params->wm_table.entries[WM_B];
1162 vlevel = MIN(MAX(vlevel_req, 1), vlevel_max);
1163 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
1164 &context->bw_ctx.dml, pipes, pipe_cnt);
1165
1166 /* WM Set A */
1167 table_entry = &bw_params->wm_table.entries[WM_A];
1168 vlevel = MIN(vlevel_req, vlevel_max);
1169 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
1170 &context->bw_ctx.dml, pipes, pipe_cnt);
1171}
1172
1173
1174bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
1175 bool fast_validate)
1176{
1177 bool out = false;
1178
1179 BW_VAL_TRACE_SETUP();
1180
1181 int vlevel = 0;
1182 int pipe_split_from[MAX_PIPES];
1183 int pipe_cnt = 0;
1184 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1185 DC_LOGGER_INIT(dc->ctx->logger);
1186
1187 BW_VAL_TRACE_COUNT();
1188
ce271b40
QZ		 1189 /*Unsafe due to current pipe merge and split logic*/
1190 ASSERT(context != dc->current_state);
1191
6f4e6361
BL		 1192 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
1193
1194 if (pipe_cnt == 0)
1195 goto validate_out;
1196
1197 if (!out)
1198 goto validate_fail;
1199
1200 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1201
1202 if (fast_validate) {
1203 BW_VAL_TRACE_SKIP(fast);
1204 goto validate_out;
1205 }
1206
1207 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
1208 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1209
1210 BW_VAL_TRACE_END_WATERMARKS();
1211
1212 goto validate_out;
1213
1214validate_fail:
1215 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1216 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1217
1218 BW_VAL_TRACE_SKIP(fail);
1219 out = false;
1220
1221validate_out:
1222 kfree(pipes);
1223
1224 BW_VAL_TRACE_FINISH();
1225
1226 return out;
1227}
1228static void dcn21_destroy_resource_pool(struct resource_pool **pool)
1229{
1230 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
1231
d9e32672 1232 dcn21_resource_destruct(dcn21_pool);
6f4e6361
BL		 1233 kfree(dcn21_pool);
1234 *pool = NULL;
1235}
1236
1237static struct clock_source *dcn21_clock_source_create(
1238 struct dc_context *ctx,
1239 struct dc_bios *bios,
1240 enum clock_source_id id,
1241 const struct dce110_clk_src_regs *regs,
1242 bool dp_clk_src)
1243{
1244 struct dce110_clk_src *clk_src =
1245 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1246
1247 if (!clk_src)
1248 return NULL;
1249
1250 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1251 regs, &cs_shift, &cs_mask)) {
1252 clk_src->base.dp_clk_src = dp_clk_src;
1253 return &clk_src->base;
1254 }
1255
1256 BREAK_TO_DEBUGGER();
1257 return NULL;
1258}
1259
1260static struct hubp *dcn21_hubp_create(
1261 struct dc_context *ctx,
1262 uint32_t inst)
1263{
1264 struct dcn21_hubp *hubp21 =
1265 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);
1266
1267 if (!hubp21)
1268 return NULL;
1269
1270 if (hubp21_construct(hubp21, ctx, inst,
1271 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1272 return &hubp21->base;
1273
1274 BREAK_TO_DEBUGGER();
1275 kfree(hubp21);
1276 return NULL;
1277}
1278
1279static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
1280{
1281 int i;
1282
1283 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1284 GFP_KERNEL);
1285
1286 if (!hubbub)
1287 return NULL;
1288
1289 hubbub21_construct(hubbub, ctx,
1290 &hubbub_reg,
1291 &hubbub_shift,
1292 &hubbub_mask);
1293
1294 for (i = 0; i < res_cap_rn.num_vmid; i++) {
1295 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1296
1297 vmid->ctx = ctx;
1298
1299 vmid->regs = &vmid_regs[i];
1300 vmid->shifts = &vmid_shifts;
1301 vmid->masks = &vmid_masks;
1302 }
fdcf62fb 1303 hubbub->num_vmid = res_cap_rn.num_vmid;
6f4e6361
BL		 1304
1305 return &hubbub->base;
1306}
1307
1308struct output_pixel_processor *dcn21_opp_create(
1309 struct dc_context *ctx, uint32_t inst)
1310{
1311 struct dcn20_opp *opp =
1312 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1313
1314 if (!opp) {
1315 BREAK_TO_DEBUGGER();
1316 return NULL;
1317 }
1318
1319 dcn20_opp_construct(opp, ctx, inst,
1320 &opp_regs[inst], &opp_shift, &opp_mask);
1321 return &opp->base;
1322}
1323
1324struct timing_generator *dcn21_timing_generator_create(
1325 struct dc_context *ctx,
1326 uint32_t instance)
1327{
1328 struct optc *tgn10 =
1329 kzalloc(sizeof(struct optc), GFP_KERNEL);
1330
1331 if (!tgn10)
1332 return NULL;
1333
1334 tgn10->base.inst = instance;
1335 tgn10->base.ctx = ctx;
1336
1337 tgn10->tg_regs = &tg_regs[instance];
1338 tgn10->tg_shift = &tg_shift;
1339 tgn10->tg_mask = &tg_mask;
1340
1341 dcn20_timing_generator_init(tgn10);
1342
1343 return &tgn10->base;
1344}
1345
1346struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1347{
1348 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1349 GFP_KERNEL);
1350
1351 if (!mpc20)
1352 return NULL;
1353
1354 dcn20_mpc_construct(mpc20, ctx,
1355 &mpc_regs,
1356 &mpc_shift,
1357 &mpc_mask,
1358 6);
1359
1360 return &mpc20->base;
1361}
1362
1363static void read_dce_straps(
1364 struct dc_context *ctx,
1365 struct resource_straps *straps)
1366{
1367 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1368 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1369
1370}
1371
6f4e6361
BL		 1372
1373struct display_stream_compressor *dcn21_dsc_create(
1374 struct dc_context *ctx, uint32_t inst)
1375{
1376 struct dcn20_dsc *dsc =
1377 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1378
1379 if (!dsc) {
1380 BREAK_TO_DEBUGGER();
1381 return NULL;
1382 }
1383
1384 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1385 return &dsc->base;
1386}
6f4e6361
BL		 1387
1388static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1389{
1390 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
1391 struct clk_limit_table *clk_table = &bw_params->clk_table;
23838777 1392 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
6de1601e
ZW		 1393 unsigned int i, closest_clk_lvl;
1394 int j;
a39a5816 1395
c42656f8 1396 // Default clock levels are used for diags, which may lead to overclocking.
23838777 1397 if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
a39a5816
EY		 1398 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1399 dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
1400 dcn2_1_soc.num_chans = bw_params->num_channels;
1401
23838777
DL		 1402 ASSERT(clk_table->num_entries);
1403 for (i = 0; i < clk_table->num_entries; i++) {
1404 /* loop backwards*/
1405 for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) {
a39a5816
EY		 1406 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
1407 closest_clk_lvl = j;
1408 break;
1409 }
1410 }
6f4e6361 1411
23838777
DL		 1412 clock_limits[i].state = i;
1413 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
1414 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
1415 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
1416 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
1417
1418 clock_limits[i].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
1419 clock_limits[i].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
1420 clock_limits[i].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
1421 clock_limits[i].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
1422 clock_limits[i].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
1423 clock_limits[i].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
1424 clock_limits[i].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
1425 }
1426 for (i = 0; i < clk_table->num_entries; i++)
1427 dcn2_1_soc.clock_limits[i] = clock_limits[i];
1428 if (clk_table->num_entries) {
1429 dcn2_1_soc.num_states = clk_table->num_entries;
1430 /* duplicate last level */
1431 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
1432 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;
a39a5816 1433 }
6f4e6361 1434 }
08f6c859 1435
a39a5816 1436 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
6f4e6361
BL		 1437}
1438
1439/* Temporary Place holder until we can get them from fuse */
1440static struct dpm_clocks dummy_clocks = {
1441 .DcfClocks = {
1442 {.Freq = 400, .Vol = 1},
1443 {.Freq = 483, .Vol = 1},
1444 {.Freq = 602, .Vol = 1},
1445 {.Freq = 738, .Vol = 1} },
1446 .SocClocks = {
1447 {.Freq = 300, .Vol = 1},
1448 {.Freq = 400, .Vol = 1},
1449 {.Freq = 400, .Vol = 1},
1450 {.Freq = 400, .Vol = 1} },
1451 .FClocks = {
1452 {.Freq = 400, .Vol = 1},
1453 {.Freq = 800, .Vol = 1},
1454 {.Freq = 1067, .Vol = 1},
1455 {.Freq = 1600, .Vol = 1} },
1456 .MemClocks = {
1457 {.Freq = 800, .Vol = 1},
1458 {.Freq = 1600, .Vol = 1},
1459 {.Freq = 1067, .Vol = 1},
1460 {.Freq = 1600, .Vol = 1} },
1461
1462};
1463
976035dd 1464static enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp,
6f4e6361
BL		 1465 struct pp_smu_wm_range_sets *ranges)
1466{
1467 return PP_SMU_RESULT_OK;
1468}
1469
976035dd 1470static enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp,
6f4e6361
BL		 1471 struct dpm_clocks *clock_table)
1472{
1473 *clock_table = dummy_clocks;
1474 return PP_SMU_RESULT_OK;
1475}
1476
976035dd 1477static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
6f4e6361
BL		 1478{
1479 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
1480
a51894f0
EY		 1481 if (!pp_smu)
1482 return pp_smu;
6f4e6361 1483
3794943c 1484 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment) || IS_DIAG_DC(ctx->dce_environment)) {
a51894f0
EY		 1485 pp_smu->ctx.ver = PP_SMU_VER_RN;
1486 pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table;
1487 pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges;
1488 } else {
1489
1490 dm_pp_get_funcs(ctx, pp_smu);
1491
1492 if (pp_smu->ctx.ver != PP_SMU_VER_RN)
1493 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
1494 }
6f4e6361
BL		 1495
1496 return pp_smu;
1497}
1498
976035dd 1499static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
6f4e6361
BL		 1500{
1501 if (pp_smu && *pp_smu) {
1502 kfree(*pp_smu);
1503 *pp_smu = NULL;
1504 }
1505}
1506
1507static struct audio *dcn21_create_audio(
1508 struct dc_context *ctx, unsigned int inst)
1509{
1510 return dce_audio_create(ctx, inst,
1511 &audio_regs[inst], &audio_shift, &audio_mask);
1512}
1513
1514static struct dc_cap_funcs cap_funcs = {
1515 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1516};
1517
1518struct stream_encoder *dcn21_stream_encoder_create(
1519 enum engine_id eng_id,
1520 struct dc_context *ctx)
1521{
1522 struct dcn10_stream_encoder *enc1 =
1523 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1524
1525 if (!enc1)
1526 return NULL;
1527
1528 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1529 &stream_enc_regs[eng_id],
1530 &se_shift, &se_mask);
1531
1532 return &enc1->base;
1533}
1534
1535static const struct dce_hwseq_registers hwseq_reg = {
1536 HWSEQ_DCN21_REG_LIST()
1537};
1538
1539static const struct dce_hwseq_shift hwseq_shift = {
1540 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
1541};
1542
1543static const struct dce_hwseq_mask hwseq_mask = {
1544 HWSEQ_DCN21_MASK_SH_LIST(_MASK)
1545};
1546
1547static struct dce_hwseq *dcn21_hwseq_create(
1548 struct dc_context *ctx)
1549{
1550 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1551
1552 if (hws) {
1553 hws->ctx = ctx;
1554 hws->regs = &hwseq_reg;
1555 hws->shifts = &hwseq_shift;
1556 hws->masks = &hwseq_mask;
f93e29f0 1557 hws->wa.DEGVIDCN21 = true;
d9758768 1558 hws->wa.disallow_self_refresh_during_multi_plane_transition = true;
6f4e6361
BL		 1559 }
1560 return hws;
1561}
1562
1563static const struct resource_create_funcs res_create_funcs = {
1564 .read_dce_straps = read_dce_straps,
1565 .create_audio = dcn21_create_audio,
1566 .create_stream_encoder = dcn21_stream_encoder_create,
1567 .create_hwseq = dcn21_hwseq_create,
1568};
1569
1570static const struct resource_create_funcs res_create_maximus_funcs = {
1571 .read_dce_straps = NULL,
1572 .create_audio = NULL,
1573 .create_stream_encoder = NULL,
1574 .create_hwseq = dcn21_hwseq_create,
1575};
1576
91c665bd
BL		 1577static const struct encoder_feature_support link_enc_feature = {
1578 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1579 .max_hdmi_pixel_clock = 600000,
1580 .hdmi_ycbcr420_supported = true,
1581 .dp_ycbcr420_supported = true,
c14b726e 1582 .fec_supported = true,
91c665bd
BL		 1583 .flags.bits.IS_HBR2_CAPABLE = true,
1584 .flags.bits.IS_HBR3_CAPABLE = true,
1585 .flags.bits.IS_TPS3_CAPABLE = true,
1586 .flags.bits.IS_TPS4_CAPABLE = true
1587};
1588
1589
1590#define link_regs(id, phyid)\
1591[id] = {\
a771ded8 1592 LE_DCN2_REG_LIST(id), \
91c665bd 1593 UNIPHY_DCN2_REG_LIST(phyid), \
a771ded8 1594 DPCS_DCN21_REG_LIST(id), \
91c665bd
BL		 1595 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
1596}
1597
1598static const struct dcn10_link_enc_registers link_enc_regs[] = {
1599 link_regs(0, A),
1600 link_regs(1, B),
1601 link_regs(2, C),
1602 link_regs(3, D),
1603 link_regs(4, E),
1604};
1605
d4caa72e
AK		 1606static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
1607 { DCN_PANEL_CNTL_REG_LIST() }
904fb6e0
AK		 1608};
1609
d4caa72e
AK		 1610static const struct dce_panel_cntl_shift panel_cntl_shift = {
1611 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
904fb6e0
AK		 1612};
1613
d4caa72e
AK		 1614static const struct dce_panel_cntl_mask panel_cntl_mask = {
1615 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
904fb6e0
AK		 1616};
1617
91c665bd
BL		 1618#define aux_regs(id)\
1619[id] = {\
1620 DCN2_AUX_REG_LIST(id)\
1621}
1622
1623static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1624 aux_regs(0),
1625 aux_regs(1),
1626 aux_regs(2),
1627 aux_regs(3),
1628 aux_regs(4)
1629};
1630
1631#define hpd_regs(id)\
1632[id] = {\
1633 HPD_REG_LIST(id)\
1634}
1635
1636static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1637 hpd_regs(0),
1638 hpd_regs(1),
1639 hpd_regs(2),
1640 hpd_regs(3),
1641 hpd_regs(4)
1642};
1643
1644static const struct dcn10_link_enc_shift le_shift = {
a771ded8
RL		 1645 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
1646 DPCS_DCN21_MASK_SH_LIST(__SHIFT)
91c665bd
BL		 1647};
1648
1649static const struct dcn10_link_enc_mask le_mask = {
a771ded8
RL		 1650 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
1651 DPCS_DCN21_MASK_SH_LIST(_MASK)
91c665bd
BL		 1652};
1653
bf7f5ac3
YMM		 1654static int map_transmitter_id_to_phy_instance(
1655 enum transmitter transmitter)
1656{
1657 switch (transmitter) {
1658 case TRANSMITTER_UNIPHY_A:
1659 return 0;
1660 break;
1661 case TRANSMITTER_UNIPHY_B:
1662 return 1;
1663 break;
1664 case TRANSMITTER_UNIPHY_C:
1665 return 2;
1666 break;
1667 case TRANSMITTER_UNIPHY_D:
1668 return 3;
1669 break;
1670 case TRANSMITTER_UNIPHY_E:
1671 return 4;
1672 break;
1673 default:
1674 ASSERT(0);
1675 return 0;
1676 }
1677}
1678
91c665bd
BL		 1679static struct link_encoder *dcn21_link_encoder_create(
1680 const struct encoder_init_data *enc_init_data)
1681{
1682 struct dcn21_link_encoder *enc21 =
1683 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
bf7f5ac3 1684 int link_regs_id;
91c665bd
BL		 1685
1686 if (!enc21)
1687 return NULL;
1688
bf7f5ac3
YMM		 1689 link_regs_id =
1690 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1691
91c665bd
BL		 1692 dcn21_link_encoder_construct(enc21,
1693 enc_init_data,
1694 &link_enc_feature,
bf7f5ac3 1695 &link_enc_regs[link_regs_id],
91c665bd
BL		 1696 &link_enc_aux_regs[enc_init_data->channel - 1],
1697 &link_enc_hpd_regs[enc_init_data->hpd_source],
1698 &le_shift,
1699 &le_mask);
1700
1701 return &enc21->enc10.base;
1702}
904fb6e0 1703
d4caa72e 1704static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_data *init_data)
904fb6e0 1705{
d4caa72e
AK		 1706 struct dce_panel_cntl *panel_cntl =
1707 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
904fb6e0 1708
d4caa72e 1709 if (!panel_cntl)
904fb6e0
AK		 1710 return NULL;
1711
d4caa72e 1712 dce_panel_cntl_construct(panel_cntl,
904fb6e0 1713 init_data,
d4caa72e
AK		 1714 &panel_cntl_regs[init_data->inst],
1715 &panel_cntl_shift,
1716 &panel_cntl_mask);
904fb6e0 1717
d4caa72e 1718 return &panel_cntl->base;
904fb6e0
AK		 1719}
1720
c0fb59a4
BL		 1721#define CTX ctx
1722
1723#define REG(reg_name) \
1724 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1725
1726static uint32_t read_pipe_fuses(struct dc_context *ctx)
1727{
1728 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1729 /* RV1 support max 4 pipes */
1730 value = value & 0xf;
1731 return value;
1732}
1733
8c357309 1734static int dcn21_populate_dml_pipes_from_context(
2f488884 1735 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)
8c357309 1736{
2f488884 1737 uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes);
8c357309
YS		 1738 int i;
1739
2a28fe92 1740 for (i = 0; i < pipe_cnt; i++) {
8c357309
YS		 1741
1742 pipes[i].pipe.src.hostvm = 1;
1743 pipes[i].pipe.src.gpuvm = 1;
1744 }
1745
1746 return pipe_cnt;
1747}
1748
8d8c82b6
JG		 1749enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1750{
1751 enum dc_status result = DC_OK;
1752
1753 if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {
1754 plane_state->dcc.enable = 1;
1755 /* align to our worst case block width */
1756 plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024;
1757 }
1758 result = dcn20_patch_unknown_plane_state(plane_state);
1759 return result;
1760}
1761
ea22cc33 1762static const struct resource_funcs dcn21_res_pool_funcs = {
6f4e6361 1763 .destroy = dcn21_destroy_resource_pool,
91c665bd 1764 .link_enc_create = dcn21_link_encoder_create,
d4caa72e 1765 .panel_cntl_create = dcn21_panel_cntl_create,
6f4e6361 1766 .validate_bandwidth = dcn21_validate_bandwidth,
8c357309 1767 .populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
6f4e6361 1768 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
b4f71c8c 1769 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
6f4e6361
BL		 1770 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1771 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1772 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
8d8c82b6 1773 .patch_unknown_plane_state = dcn21_patch_unknown_plane_state,
6f4e6361
BL		 1774 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1775 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1776 .update_bw_bounding_box = update_bw_bounding_box
1777};
1778
d9e32672 1779static bool dcn21_resource_construct(
6f4e6361
BL		 1780 uint8_t num_virtual_links,
1781 struct dc *dc,
1782 struct dcn21_resource_pool *pool)
1783{
c0fb59a4 1784 int i, j;
6f4e6361
BL		 1785 struct dc_context *ctx = dc->ctx;
1786 struct irq_service_init_data init_data;
c0fb59a4 1787 uint32_t pipe_fuses = read_pipe_fuses(ctx);
ff86391e 1788 uint32_t num_pipes;
6f4e6361
BL		 1789
1790 ctx->dc_bios->regs = &bios_regs;
1791
1792 pool->base.res_cap = &res_cap_rn;
1793#ifdef DIAGS_BUILD
1794 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1795 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc;
1796 pool->base.res_cap = &res_cap_rn_FPGA_4pipe;
1797#endif
1798
1799 pool->base.funcs = &dcn21_res_pool_funcs;
1800
1801 /*************************************************
1802 * Resource + asic cap harcoding *
1803 *************************************************/
1804 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1805
c0fb59a4
BL		 1806 /* max pipe num for ASIC before check pipe fuses */
1807 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1808
6f4e6361
BL		 1809 dc->caps.max_downscale_ratio = 200;
1810 dc->caps.i2c_speed_in_khz = 100;
1811 dc->caps.max_cursor_size = 256;
1812 dc->caps.dmdata_alloc_size = 2048;
6f4e6361
BL		 1813
1814 dc->caps.max_slave_planes = 1;
1815 dc->caps.post_blend_color_processing = true;
1816 dc->caps.force_dp_tps4_for_cp2520 = true;
c797ede0 1817 dc->caps.extended_aux_timeout_support = true;
3a1627b0 1818 dc->caps.dmcub_support = true;
3cfe9fb6 1819 dc->caps.is_apu = true;
6f4e6361 1820
a8bf7164
KK		 1821 /* Color pipeline capabilities */
1822 dc->caps.color.dpp.dcn_arch = 1;
1823 dc->caps.color.dpp.input_lut_shared = 0;
1824 dc->caps.color.dpp.icsc = 1;
1825 dc->caps.color.dpp.dgam_ram = 1;
1826 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1827 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1828 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1829 dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1830 dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1831 dc->caps.color.dpp.post_csc = 0;
1832 dc->caps.color.dpp.gamma_corr = 0;
1833
1834 dc->caps.color.dpp.hw_3d_lut = 1;
1835 dc->caps.color.dpp.ogam_ram = 1;
1836 // no OGAM ROM on DCN2
1837 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1838 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1839 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1840 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1841 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1842 dc->caps.color.dpp.ocsc = 0;
1843
1844 dc->caps.color.mpc.gamut_remap = 0;
1845 dc->caps.color.mpc.num_3dluts = 0;
1846 dc->caps.color.mpc.shared_3d_lut = 0;
1847 dc->caps.color.mpc.ogam_ram = 1;
1848 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1849 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1850 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1851 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1852 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1853 dc->caps.color.mpc.ocsc = 1;
1854
6f4e6361
BL		 1855 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1856 dc->debug = debug_defaults_drv;
1857 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1858 pool->base.pipe_count = 4;
1859 dc->debug = debug_defaults_diags;
1860 } else
1861 dc->debug = debug_defaults_diags;
1862
1863 // Init the vm_helper
1864 if (dc->vm_helper)
1865 vm_helper_init(dc->vm_helper, 16);
1866
1867 /*************************************************
1868 * Create resources *
1869 *************************************************/
1870
1871 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1872 dcn21_clock_source_create(ctx, ctx->dc_bios,
1873 CLOCK_SOURCE_COMBO_PHY_PLL0,
1874 &clk_src_regs[0], false);
1875 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1876 dcn21_clock_source_create(ctx, ctx->dc_bios,
1877 CLOCK_SOURCE_COMBO_PHY_PLL1,
1878 &clk_src_regs[1], false);
15add0c2
IZ		 1879 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
1880 dcn21_clock_source_create(ctx, ctx->dc_bios,
1881 CLOCK_SOURCE_COMBO_PHY_PLL2,
1882 &clk_src_regs[2], false);
6f4e6361
BL		 1883
1884 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
1885
1886 /* todo: not reuse phy_pll registers */
1887 pool->base.dp_clock_source =
1888 dcn21_clock_source_create(ctx, ctx->dc_bios,
1889 CLOCK_SOURCE_ID_DP_DTO,
1890 &clk_src_regs[0], true);
1891
1892 for (i = 0; i < pool->base.clk_src_count; i++) {
1893 if (pool->base.clock_sources[i] == NULL) {
1894 dm_error("DC: failed to create clock sources!\n");
1895 BREAK_TO_DEBUGGER();
1896 goto create_fail;
1897 }
1898 }
1899
1900 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1901 if (pool->base.dccg == NULL) {
1902 dm_error("DC: failed to create dccg!\n");
1903 BREAK_TO_DEBUGGER();
1904 goto create_fail;
1905 }
1906
501b4026 1907 if (!dc->config.disable_dmcu) {
16012806
WW		 1908 pool->base.dmcu = dcn21_dmcu_create(ctx,
1909 &dmcu_regs,
1910 &dmcu_shift,
1911 &dmcu_mask);
1912 if (pool->base.dmcu == NULL) {
1913 dm_error("DC: failed to create dmcu!\n");
1914 BREAK_TO_DEBUGGER();
1915 goto create_fail;
1916 }
a96562b0
AP		 1917
1918 dc->debug.dmub_command_table = false;
c0fb59a4
BL		 1919 }
1920
501b4026 1921 if (dc->config.disable_dmcu) {
9dac88d8
WW		 1922 pool->base.psr = dmub_psr_create(ctx);
1923
1924 if (pool->base.psr == NULL) {
1925 dm_error("DC: failed to create psr obj!\n");
1926 BREAK_TO_DEBUGGER();
1927 goto create_fail;
1928 }
1929 }
4c1a1335 1930
501b4026 1931 if (dc->config.disable_dmcu)
16012806
WW		 1932 pool->base.abm = dmub_abm_create(ctx,
1933 &abm_regs,
1934 &abm_shift,
1935 &abm_mask);
1936 else
1937 pool->base.abm = dce_abm_create(ctx,
c0fb59a4
BL		 1938 &abm_regs,
1939 &abm_shift,
1940 &abm_mask);
c0fb59a4 1941
6f4e6361
BL		 1942 pool->base.pp_smu = dcn21_pp_smu_create(ctx);
1943
ff86391e
MS		 1944 num_pipes = dcn2_1_ip.max_num_dpp;
1945
1946 for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
1947 if (pipe_fuses & 1 << i)
1948 num_pipes--;
1949 dcn2_1_ip.max_num_dpp = num_pipes;
1950 dcn2_1_ip.max_num_otg = num_pipes;
1951
6f4e6361
BL		 1952 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1953
1954 init_data.ctx = dc->ctx;
1955 pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
1956 if (!pool->base.irqs)
1957 goto create_fail;
1958
c0fb59a4 1959 j = 0;
6f4e6361
BL		 1960 /* mem input -> ipp -> dpp -> opp -> TG */
1961 for (i = 0; i < pool->base.pipe_count; i++) {
c0fb59a4
BL		 1962 /* if pipe is disabled, skip instance of HW pipe,
1963 * i.e, skip ASIC register instance
1964 */
1965 if ((pipe_fuses & (1 << i)) != 0)
1966 continue;
1967
b9f1246d
NA		 1968 pool->base.hubps[j] = dcn21_hubp_create(ctx, i);
1969 if (pool->base.hubps[j] == NULL) {
6f4e6361
BL		 1970 BREAK_TO_DEBUGGER();
1971 dm_error(
1972 "DC: failed to create memory input!\n");
1973 goto create_fail;
1974 }
1975
b9f1246d
NA		 1976 pool->base.ipps[j] = dcn21_ipp_create(ctx, i);
1977 if (pool->base.ipps[j] == NULL) {
6f4e6361
BL		 1978 BREAK_TO_DEBUGGER();
1979 dm_error(
1980 "DC: failed to create input pixel processor!\n");
1981 goto create_fail;
1982 }
1983
b9f1246d
NA		 1984 pool->base.dpps[j] = dcn21_dpp_create(ctx, i);
1985 if (pool->base.dpps[j] == NULL) {
6f4e6361
BL		 1986 BREAK_TO_DEBUGGER();
1987 dm_error(
1988 "DC: failed to create dpps!\n");
1989 goto create_fail;
1990 }
c0fb59a4 1991
b9f1246d
NA		 1992 pool->base.opps[j] = dcn21_opp_create(ctx, i);
1993 if (pool->base.opps[j] == NULL) {
c0fb59a4
BL		 1994 BREAK_TO_DEBUGGER();
1995 dm_error(
1996 "DC: failed to create output pixel processor!\n");
1997 goto create_fail;
1998 }
1999
b9f1246d 2000 pool->base.timing_generators[j] = dcn21_timing_generator_create(
c0fb59a4 2001 ctx, i);
b9f1246d 2002 if (pool->base.timing_generators[j] == NULL) {
c0fb59a4
BL		 2003 BREAK_TO_DEBUGGER();
2004 dm_error("DC: failed to create tg!\n");
2005 goto create_fail;
2006 }
2007 j++;
6f4e6361
BL		 2008 }
2009
2010 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2011 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
2012 if (pool->base.engines[i] == NULL) {
2013 BREAK_TO_DEBUGGER();
2014 dm_error(
2015 "DC:failed to create aux engine!!\n");
2016 goto create_fail;
2017 }
2018 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
2019 if (pool->base.hw_i2cs[i] == NULL) {
2020 BREAK_TO_DEBUGGER();
2021 dm_error(
2022 "DC:failed to create hw i2c!!\n");
2023 goto create_fail;
2024 }
2025 pool->base.sw_i2cs[i] = NULL;
2026 }
2027
c0fb59a4
BL		 2028 pool->base.timing_generator_count = j;
2029 pool->base.pipe_count = j;
2030 pool->base.mpcc_count = j;
6f4e6361
BL		 2031
2032 pool->base.mpc = dcn21_mpc_create(ctx);
2033 if (pool->base.mpc == NULL) {
2034 BREAK_TO_DEBUGGER();
2035 dm_error("DC: failed to create mpc!\n");
2036 goto create_fail;
2037 }
2038
2039 pool->base.hubbub = dcn21_hubbub_create(ctx);
2040 if (pool->base.hubbub == NULL) {
2041 BREAK_TO_DEBUGGER();
2042 dm_error("DC: failed to create hubbub!\n");
2043 goto create_fail;
2044 }
2045
6f4e6361
BL		 2046 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2047 pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
2048 if (pool->base.dscs[i] == NULL) {
2049 BREAK_TO_DEBUGGER();
2050 dm_error("DC: failed to create display stream compressor %d!\n", i);
2051 goto create_fail;
2052 }
2053 }
6f4e6361
BL		 2054
2055 if (!dcn20_dwbc_create(ctx, &pool->base)) {
2056 BREAK_TO_DEBUGGER();
2057 dm_error("DC: failed to create dwbc!\n");
2058 goto create_fail;
2059 }
2060 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
2061 BREAK_TO_DEBUGGER();
2062 dm_error("DC: failed to create mcif_wb!\n");
2063 goto create_fail;
2064 }
2065
2066 if (!resource_construct(num_virtual_links, dc, &pool->base,
2067 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2068 &res_create_funcs : &res_create_maximus_funcs)))
2069 goto create_fail;
2070
c0fb59a4 2071 dcn21_hw_sequencer_construct(dc);
6f4e6361
BL		 2072
2073 dc->caps.max_planes = pool->base.pipe_count;
2074
2075 for (i = 0; i < dc->caps.max_planes; ++i)
2076 dc->caps.planes[i] = plane_cap;
2077
2078 dc->cap_funcs = cap_funcs;
2079
2080 return true;
2081
2082create_fail:
2083
d9e32672 2084 dcn21_resource_destruct(pool);
6f4e6361
BL		 2085
2086 return false;
2087}
2088
2089struct resource_pool *dcn21_create_resource_pool(
2090 const struct dc_init_data *init_data,
2091 struct dc *dc)
2092{
2093 struct dcn21_resource_pool *pool =
2094 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);
2095
2096 if (!pool)
2097 return NULL;
2098
d9e32672 2099 if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
6f4e6361
BL		 2100 return &pool->base;
2101
2102 BREAK_TO_DEBUGGER();
2103 kfree(pool);
2104 return NULL;
2105}
Linux 6.x block layer and io_uring tree(s)