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drm/amd/display: check if REFCLK_CNTL register is present
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / dc / dcn21 / dcn21_resource.c
CommitLineData
6f4e6361
BL		 1/*
2* Copyright 2018 Advanced Micro Devices, Inc.
6ca3928d 3 * Copyright 2019 Raptor Engineering, LLC
6f4e6361
BL		 4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
aec43402
AB		 27#include <linux/slab.h>
28
6f4e6361
BL		 29#include "dm_services.h"
30#include "dc.h"
31
78c77382
AK		 32#include "dcn21_init.h"
33
6f4e6361
BL		 34#include "resource.h"
35#include "include/irq_service_interface.h"
36#include "dcn20/dcn20_resource.h"
37
38#include "clk_mgr.h"
39#include "dcn10/dcn10_hubp.h"
40#include "dcn10/dcn10_ipp.h"
41#include "dcn20/dcn20_hubbub.h"
42#include "dcn20/dcn20_mpc.h"
43#include "dcn20/dcn20_hubp.h"
44#include "dcn21_hubp.h"
45#include "irq/dcn21/irq_service_dcn21.h"
46#include "dcn20/dcn20_dpp.h"
47#include "dcn20/dcn20_optc.h"
c0fb59a4 48#include "dcn21/dcn21_hwseq.h"
6f4e6361
BL		 49#include "dce110/dce110_hw_sequencer.h"
50#include "dcn20/dcn20_opp.h"
51#include "dcn20/dcn20_dsc.h"
91c665bd 52#include "dcn21/dcn21_link_encoder.h"
6f4e6361
BL		 53#include "dcn20/dcn20_stream_encoder.h"
54#include "dce/dce_clock_source.h"
55#include "dce/dce_audio.h"
56#include "dce/dce_hwseq.h"
57#include "virtual/virtual_stream_encoder.h"
58#include "dce110/dce110_resource.h"
59#include "dml/display_mode_vba.h"
60#include "dcn20/dcn20_dccg.h"
61#include "dcn21_hubbub.h"
62#include "dcn10/dcn10_resource.h"
15add0c2 63#include "dce110/dce110_resource.h"
d4caa72e 64#include "dce/dce_panel_cntl.h"
6f4e6361
BL		 65
66#include "dcn20/dcn20_dwb.h"
67#include "dcn20/dcn20_mmhubbub.h"
a771ded8
RL		 68#include "dpcs/dpcs_2_1_0_offset.h"
69#include "dpcs/dpcs_2_1_0_sh_mask.h"
6f4e6361
BL		 70
71#include "renoir_ip_offset.h"
72#include "dcn/dcn_2_1_0_offset.h"
73#include "dcn/dcn_2_1_0_sh_mask.h"
74
75#include "nbio/nbio_7_0_offset.h"
76
77#include "mmhub/mmhub_2_0_0_offset.h"
78#include "mmhub/mmhub_2_0_0_sh_mask.h"
79
80#include "reg_helper.h"
81#include "dce/dce_abm.h"
82#include "dce/dce_dmcu.h"
83#include "dce/dce_aux.h"
84#include "dce/dce_i2c.h"
85#include "dcn21_resource.h"
86#include "vm_helper.h"
87#include "dcn20/dcn20_vmid.h"
9dac88d8 88#include "dce/dmub_psr.h"
16012806 89#include "dce/dmub_abm.h"
6f4e6361
BL		 90
91#define SOC_BOUNDING_BOX_VALID false
92#define DC_LOGGER_INIT(logger)
93
94
95struct _vcs_dpi_ip_params_st dcn2_1_ip = {
652651ff 96 .odm_capable = 1,
8c357309
YS		 97 .gpuvm_enable = 1,
98 .hostvm_enable = 1,
6f4e6361
BL		 99 .gpuvm_max_page_table_levels = 1,
100 .hostvm_max_page_table_levels = 4,
101 .hostvm_cached_page_table_levels = 2,
6f4e6361 102 .num_dsc = 3,
6f4e6361
BL		 103 .rob_buffer_size_kbytes = 168,
104 .det_buffer_size_kbytes = 164,
105 .dpte_buffer_size_in_pte_reqs_luma = 44,
106 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
107 .dpp_output_buffer_pixels = 2560,
108 .opp_output_buffer_lines = 1,
109 .pixel_chunk_size_kbytes = 8,
110 .pte_enable = 1,
111 .max_page_table_levels = 4,
112 .pte_chunk_size_kbytes = 2,
113 .meta_chunk_size_kbytes = 2,
114 .writeback_chunk_size_kbytes = 2,
115 .line_buffer_size_bits = 789504,
116 .is_line_buffer_bpp_fixed = 0,
117 .line_buffer_fixed_bpp = 0,
118 .dcc_supported = true,
119 .max_line_buffer_lines = 12,
120 .writeback_luma_buffer_size_kbytes = 12,
121 .writeback_chroma_buffer_size_kbytes = 8,
122 .writeback_chroma_line_buffer_width_pixels = 4,
123 .writeback_max_hscl_ratio = 1,
124 .writeback_max_vscl_ratio = 1,
125 .writeback_min_hscl_ratio = 1,
126 .writeback_min_vscl_ratio = 1,
127 .writeback_max_hscl_taps = 12,
128 .writeback_max_vscl_taps = 12,
129 .writeback_line_buffer_luma_buffer_size = 0,
130 .writeback_line_buffer_chroma_buffer_size = 14643,
131 .cursor_buffer_size = 8,
132 .cursor_chunk_size = 2,
133 .max_num_otg = 4,
134 .max_num_dpp = 4,
135 .max_num_wb = 1,
136 .max_dchub_pscl_bw_pix_per_clk = 4,
137 .max_pscl_lb_bw_pix_per_clk = 2,
138 .max_lb_vscl_bw_pix_per_clk = 4,
139 .max_vscl_hscl_bw_pix_per_clk = 4,
140 .max_hscl_ratio = 4,
141 .max_vscl_ratio = 4,
142 .hscl_mults = 4,
143 .vscl_mults = 4,
144 .max_hscl_taps = 8,
145 .max_vscl_taps = 8,
146 .dispclk_ramp_margin_percent = 1,
147 .underscan_factor = 1.10,
148 .min_vblank_lines = 32, //
149 .dppclk_delay_subtotal = 77, //
150 .dppclk_delay_scl_lb_only = 16,
151 .dppclk_delay_scl = 50,
152 .dppclk_delay_cnvc_formatter = 8,
153 .dppclk_delay_cnvc_cursor = 6,
154 .dispclk_delay_subtotal = 87, //
155 .dcfclk_cstate_latency = 10, // SRExitTime
156 .max_inter_dcn_tile_repeaters = 8,
157
158 .xfc_supported = false,
159 .xfc_fill_bw_overhead_percent = 10.0,
160 .xfc_fill_constant_bytes = 0,
8f174fdb
YS		 161 .ptoi_supported = 0,
162 .number_of_cursors = 1,
6f4e6361
BL		 163};
164
165struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
166 .clock_limits = {
167 {
168 .state = 0,
a39a5816
EY		 169 .dcfclk_mhz = 400.0,
170 .fabricclk_mhz = 400.0,
171 .dispclk_mhz = 600.0,
172 .dppclk_mhz = 400.00,
6f4e6361
BL		 173 .phyclk_mhz = 600.0,
174 .socclk_mhz = 278.0,
175 .dscclk_mhz = 205.67,
176 .dram_speed_mts = 1600.0,
177 },
178 {
179 .state = 1,
a39a5816
EY		 180 .dcfclk_mhz = 464.52,
181 .fabricclk_mhz = 800.0,
182 .dispclk_mhz = 654.55,
183 .dppclk_mhz = 626.09,
6f4e6361
BL		 184 .phyclk_mhz = 600.0,
185 .socclk_mhz = 278.0,
186 .dscclk_mhz = 205.67,
187 .dram_speed_mts = 1600.0,
188 },
189 {
190 .state = 2,
a39a5816
EY		 191 .dcfclk_mhz = 514.29,
192 .fabricclk_mhz = 933.0,
193 .dispclk_mhz = 757.89,
194 .dppclk_mhz = 685.71,
195 .phyclk_mhz = 600.0,
6f4e6361
BL		 196 .socclk_mhz = 278.0,
197 .dscclk_mhz = 287.67,
a39a5816 198 .dram_speed_mts = 1866.0,
6f4e6361
BL		 199 },
200 {
201 .state = 3,
a39a5816
EY		 202 .dcfclk_mhz = 576.00,
203 .fabricclk_mhz = 1067.0,
204 .dispclk_mhz = 847.06,
205 .dppclk_mhz = 757.89,
206 .phyclk_mhz = 600.0,
6f4e6361
BL		 207 .socclk_mhz = 715.0,
208 .dscclk_mhz = 318.334,
a39a5816 209 .dram_speed_mts = 2134.0,
6f4e6361
BL		 210 },
211 {
212 .state = 4,
a39a5816
EY		 213 .dcfclk_mhz = 626.09,
214 .fabricclk_mhz = 1200.0,
215 .dispclk_mhz = 900.00,
216 .dppclk_mhz = 847.06,
217 .phyclk_mhz = 810.0,
218 .socclk_mhz = 953.0,
219 .dscclk_mhz = 489.0,
220 .dram_speed_mts = 2400.0,
221 },
222 {
223 .state = 5,
224 .dcfclk_mhz = 685.71,
225 .fabricclk_mhz = 1333.0,
226 .dispclk_mhz = 1028.57,
227 .dppclk_mhz = 960.00,
228 .phyclk_mhz = 810.0,
229 .socclk_mhz = 278.0,
230 .dscclk_mhz = 287.67,
231 .dram_speed_mts = 2666.0,
232 },
233 {
234 .state = 6,
235 .dcfclk_mhz = 757.89,
236 .fabricclk_mhz = 1467.0,
237 .dispclk_mhz = 1107.69,
238 .dppclk_mhz = 1028.57,
239 .phyclk_mhz = 810.0,
240 .socclk_mhz = 715.0,
241 .dscclk_mhz = 318.334,
242 .dram_speed_mts = 3200.0,
243 },
244 {
245 .state = 7,
246 .dcfclk_mhz = 847.06,
6f4e6361 247 .fabricclk_mhz = 1600.0,
652651ff 248 .dispclk_mhz = 1395.0,
a39a5816 249 .dppclk_mhz = 1285.00,
652651ff 250 .phyclk_mhz = 1325.0,
6f4e6361 251 .socclk_mhz = 953.0,
652651ff 252 .dscclk_mhz = 489.0,
6f4e6361
BL		 253 .dram_speed_mts = 4266.0,
254 },
255 /*Extra state, no dispclk ramping*/
256 {
a39a5816
EY		 257 .state = 8,
258 .dcfclk_mhz = 847.06,
6f4e6361 259 .fabricclk_mhz = 1600.0,
652651ff
BL		 260 .dispclk_mhz = 1395.0,
261 .dppclk_mhz = 1285.0,
262 .phyclk_mhz = 1325.0,
6f4e6361 263 .socclk_mhz = 953.0,
652651ff 264 .dscclk_mhz = 489.0,
6f4e6361
BL		 265 .dram_speed_mts = 4266.0,
266 },
267
268 },
269
652651ff
BL		 270 .sr_exit_time_us = 12.5,
271 .sr_enter_plus_exit_time_us = 17.0,
6f4e6361
BL		 272 .urgent_latency_us = 4.0,
273 .urgent_latency_pixel_data_only_us = 4.0,
274 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
275 .urgent_latency_vm_data_only_us = 4.0,
276 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
277 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
278 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
279 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
280 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
281 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
282 .max_avg_sdp_bw_use_normal_percent = 60.0,
283 .max_avg_dram_bw_use_normal_percent = 100.0,
284 .writeback_latency_us = 12.0,
285 .max_request_size_bytes = 256,
286 .dram_channel_width_bytes = 4,
287 .fabric_datapath_to_dcn_data_return_bytes = 32,
288 .dcn_downspread_percent = 0.5,
289 .downspread_percent = 0.5,
290 .dram_page_open_time_ns = 50.0,
291 .dram_rw_turnaround_time_ns = 17.5,
292 .dram_return_buffer_per_channel_bytes = 8192,
293 .round_trip_ping_latency_dcfclk_cycles = 128,
294 .urgent_out_of_order_return_per_channel_bytes = 4096,
295 .channel_interleave_bytes = 256,
296 .num_banks = 8,
297 .num_chans = 4,
298 .vmm_page_size_bytes = 4096,
299 .dram_clock_change_latency_us = 23.84,
300 .return_bus_width_bytes = 64,
0beb5403 301 .dispclk_dppclk_vco_speed_mhz = 3600,
6f4e6361
BL		 302 .xfc_bus_transport_time_us = 4,
303 .xfc_xbuf_latency_tolerance_us = 4,
304 .use_urgent_burst_bw = 1,
c42656f8 305 .num_states = 8
6f4e6361
BL		 306};
307
308#ifndef MAX
309#define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
310#endif
311#ifndef MIN
312#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
313#endif
314
315/* begin *********************
316 * macros to expend register list macro defined in HW object header file */
317
318/* DCN */
319/* TODO awful hack. fixup dcn20_dwb.h */
320#undef BASE_INNER
321#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
322
323#define BASE(seg) BASE_INNER(seg)
324
325#define SR(reg_name)\
326 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
327 mm ## reg_name
328
329#define SRI(reg_name, block, id)\
330 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
331 mm ## block ## id ## _ ## reg_name
332
333#define SRIR(var_name, reg_name, block, id)\
334 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
335 mm ## block ## id ## _ ## reg_name
336
337#define SRII(reg_name, block, id)\
338 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
339 mm ## block ## id ## _ ## reg_name
340
341#define DCCG_SRII(reg_name, block, id)\
342 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
343 mm ## block ## id ## _ ## reg_name
344
345/* NBIO */
346#define NBIO_BASE_INNER(seg) \
347 NBIF0_BASE__INST0_SEG ## seg
348
349#define NBIO_BASE(seg) \
350 NBIO_BASE_INNER(seg)
351
352#define NBIO_SR(reg_name)\
353 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
354 mm ## reg_name
355
356/* MMHUB */
357#define MMHUB_BASE_INNER(seg) \
358 MMHUB_BASE__INST0_SEG ## seg
359
360#define MMHUB_BASE(seg) \
361 MMHUB_BASE_INNER(seg)
362
363#define MMHUB_SR(reg_name)\
364 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
365 mmMM ## reg_name
366
367#define clk_src_regs(index, pllid)\
368[index] = {\
369 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
370}
371
372static const struct dce110_clk_src_regs clk_src_regs[] = {
373 clk_src_regs(0, A),
374 clk_src_regs(1, B),
375 clk_src_regs(2, C),
376 clk_src_regs(3, D),
377 clk_src_regs(4, E),
378};
379
380static const struct dce110_clk_src_shift cs_shift = {
381 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
382};
383
384static const struct dce110_clk_src_mask cs_mask = {
385 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
386};
387
388static const struct bios_registers bios_regs = {
389 NBIO_SR(BIOS_SCRATCH_3),
390 NBIO_SR(BIOS_SCRATCH_6)
391};
392
c0fb59a4 393static const struct dce_dmcu_registers dmcu_regs = {
a7e3658e 394 DMCU_DCN20_REG_LIST()
c0fb59a4
BL		 395};
396
397static const struct dce_dmcu_shift dmcu_shift = {
398 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
399};
400
401static const struct dce_dmcu_mask dmcu_mask = {
402 DMCU_MASK_SH_LIST_DCN10(_MASK)
403};
404
405static const struct dce_abm_registers abm_regs = {
406 ABM_DCN20_REG_LIST()
407};
408
409static const struct dce_abm_shift abm_shift = {
410 ABM_MASK_SH_LIST_DCN20(__SHIFT)
411};
412
413static const struct dce_abm_mask abm_mask = {
414 ABM_MASK_SH_LIST_DCN20(_MASK)
415};
416
6f4e6361
BL		 417#define audio_regs(id)\
418[id] = {\
419 AUD_COMMON_REG_LIST(id)\
420}
421
422static const struct dce_audio_registers audio_regs[] = {
423 audio_regs(0),
424 audio_regs(1),
425 audio_regs(2),
426 audio_regs(3),
427 audio_regs(4),
428 audio_regs(5),
429};
430
431#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
432 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
433 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
434 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
435
436static const struct dce_audio_shift audio_shift = {
437 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
438};
439
440static const struct dce_audio_mask audio_mask = {
441 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
442};
443
444static const struct dccg_registers dccg_regs = {
445 DCCG_COMMON_REG_LIST_DCN_BASE()
446};
447
448static const struct dccg_shift dccg_shift = {
449 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
450};
451
452static const struct dccg_mask dccg_mask = {
453 DCCG_MASK_SH_LIST_DCN2(_MASK)
454};
455
456#define opp_regs(id)\
457[id] = {\
458 OPP_REG_LIST_DCN20(id),\
459}
460
461static const struct dcn20_opp_registers opp_regs[] = {
462 opp_regs(0),
463 opp_regs(1),
464 opp_regs(2),
465 opp_regs(3),
466 opp_regs(4),
467 opp_regs(5),
468};
469
470static const struct dcn20_opp_shift opp_shift = {
471 OPP_MASK_SH_LIST_DCN20(__SHIFT)
472};
473
474static const struct dcn20_opp_mask opp_mask = {
475 OPP_MASK_SH_LIST_DCN20(_MASK)
476};
477
478#define tg_regs(id)\
479[id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
480
481static const struct dcn_optc_registers tg_regs[] = {
482 tg_regs(0),
483 tg_regs(1),
484 tg_regs(2),
485 tg_regs(3)
486};
487
488static const struct dcn_optc_shift tg_shift = {
489 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
490};
491
492static const struct dcn_optc_mask tg_mask = {
493 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
494};
495
496static const struct dcn20_mpc_registers mpc_regs = {
497 MPC_REG_LIST_DCN2_0(0),
498 MPC_REG_LIST_DCN2_0(1),
499 MPC_REG_LIST_DCN2_0(2),
500 MPC_REG_LIST_DCN2_0(3),
501 MPC_REG_LIST_DCN2_0(4),
502 MPC_REG_LIST_DCN2_0(5),
503 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
504 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
505 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
e8027e08
NA		 506 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
507 MPC_DBG_REG_LIST_DCN2_0()
6f4e6361
BL		 508};
509
510static const struct dcn20_mpc_shift mpc_shift = {
c1e34175
NA		 511 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
512 MPC_DEBUG_REG_LIST_SH_DCN20
6f4e6361
BL		 513};
514
515static const struct dcn20_mpc_mask mpc_mask = {
c1e34175
NA		 516 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
517 MPC_DEBUG_REG_LIST_MASK_DCN20
6f4e6361
BL		 518};
519
520#define hubp_regs(id)\
521[id] = {\
522 HUBP_REG_LIST_DCN21(id)\
523}
524
525static const struct dcn_hubp2_registers hubp_regs[] = {
526 hubp_regs(0),
527 hubp_regs(1),
528 hubp_regs(2),
529 hubp_regs(3)
530};
531
532static const struct dcn_hubp2_shift hubp_shift = {
533 HUBP_MASK_SH_LIST_DCN21(__SHIFT)
534};
535
536static const struct dcn_hubp2_mask hubp_mask = {
537 HUBP_MASK_SH_LIST_DCN21(_MASK)
538};
539
540static const struct dcn_hubbub_registers hubbub_reg = {
541 HUBBUB_REG_LIST_DCN21()
542};
543
544static const struct dcn_hubbub_shift hubbub_shift = {
545 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
546};
547
548static const struct dcn_hubbub_mask hubbub_mask = {
549 HUBBUB_MASK_SH_LIST_DCN21(_MASK)
550};
551
552
553#define vmid_regs(id)\
554[id] = {\
555 DCN20_VMID_REG_LIST(id)\
556}
557
558static const struct dcn_vmid_registers vmid_regs[] = {
559 vmid_regs(0),
560 vmid_regs(1),
561 vmid_regs(2),
562 vmid_regs(3),
563 vmid_regs(4),
564 vmid_regs(5),
565 vmid_regs(6),
566 vmid_regs(7),
567 vmid_regs(8),
568 vmid_regs(9),
569 vmid_regs(10),
570 vmid_regs(11),
571 vmid_regs(12),
572 vmid_regs(13),
573 vmid_regs(14),
574 vmid_regs(15)
575};
576
577static const struct dcn20_vmid_shift vmid_shifts = {
578 DCN20_VMID_MASK_SH_LIST(__SHIFT)
579};
580
581static const struct dcn20_vmid_mask vmid_masks = {
582 DCN20_VMID_MASK_SH_LIST(_MASK)
583};
584
6f4e6361
BL		 585#define dsc_regsDCN20(id)\
586[id] = {\
587 DSC_REG_LIST_DCN20(id)\
588}
589
590static const struct dcn20_dsc_registers dsc_regs[] = {
591 dsc_regsDCN20(0),
592 dsc_regsDCN20(1),
593 dsc_regsDCN20(2),
594 dsc_regsDCN20(3),
595 dsc_regsDCN20(4),
596 dsc_regsDCN20(5)
597};
598
599static const struct dcn20_dsc_shift dsc_shift = {
600 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
601};
602
603static const struct dcn20_dsc_mask dsc_mask = {
604 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
605};
6f4e6361
BL		 606
607#define ipp_regs(id)\
608[id] = {\
609 IPP_REG_LIST_DCN20(id),\
610}
611
612static const struct dcn10_ipp_registers ipp_regs[] = {
613 ipp_regs(0),
614 ipp_regs(1),
615 ipp_regs(2),
616 ipp_regs(3),
617};
618
619static const struct dcn10_ipp_shift ipp_shift = {
620 IPP_MASK_SH_LIST_DCN20(__SHIFT)
621};
622
623static const struct dcn10_ipp_mask ipp_mask = {
624 IPP_MASK_SH_LIST_DCN20(_MASK),
625};
626
627#define opp_regs(id)\
628[id] = {\
629 OPP_REG_LIST_DCN20(id),\
630}
631
632
633#define aux_engine_regs(id)\
634[id] = {\
635 AUX_COMMON_REG_LIST0(id), \
636 .AUXN_IMPCAL = 0, \
637 .AUXP_IMPCAL = 0, \
638 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
639}
640
641static const struct dce110_aux_registers aux_engine_regs[] = {
642 aux_engine_regs(0),
643 aux_engine_regs(1),
644 aux_engine_regs(2),
645 aux_engine_regs(3),
646 aux_engine_regs(4),
647};
648
649#define tf_regs(id)\
650[id] = {\
651 TF_REG_LIST_DCN20(id),\
d9eb70ae 652 TF_REG_LIST_DCN20_COMMON_APPEND(id),\
6f4e6361
BL		 653}
654
655static const struct dcn2_dpp_registers tf_regs[] = {
656 tf_regs(0),
657 tf_regs(1),
658 tf_regs(2),
659 tf_regs(3),
660};
661
662static const struct dcn2_dpp_shift tf_shift = {
d9eb70ae 663 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
c1e34175 664 TF_DEBUG_REG_LIST_SH_DCN20
6f4e6361
BL		 665};
666
667static const struct dcn2_dpp_mask tf_mask = {
d9eb70ae 668 TF_REG_LIST_SH_MASK_DCN20(_MASK),
c1e34175 669 TF_DEBUG_REG_LIST_MASK_DCN20
6f4e6361
BL		 670};
671
672#define stream_enc_regs(id)\
673[id] = {\
674 SE_DCN2_REG_LIST(id)\
675}
676
677static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
678 stream_enc_regs(0),
679 stream_enc_regs(1),
680 stream_enc_regs(2),
681 stream_enc_regs(3),
682 stream_enc_regs(4),
683};
684
8276dd87 685static const struct dce110_aux_registers_shift aux_shift = {
686 DCN_AUX_MASK_SH_LIST(__SHIFT)
687};
688
689static const struct dce110_aux_registers_mask aux_mask = {
690 DCN_AUX_MASK_SH_LIST(_MASK)
691};
692
6f4e6361
BL		 693static const struct dcn10_stream_encoder_shift se_shift = {
694 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
695};
696
697static const struct dcn10_stream_encoder_mask se_mask = {
698 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
699};
700
44e149bb
AD		 701static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
702
8c357309 703static int dcn21_populate_dml_pipes_from_context(
2f488884 704 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes);
8c357309 705
6f4e6361
BL		 706static struct input_pixel_processor *dcn21_ipp_create(
707 struct dc_context *ctx, uint32_t inst)
708{
709 struct dcn10_ipp *ipp =
710 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
711
712 if (!ipp) {
713 BREAK_TO_DEBUGGER();
714 return NULL;
715 }
716
717 dcn20_ipp_construct(ipp, ctx, inst,
718 &ipp_regs[inst], &ipp_shift, &ipp_mask);
719 return &ipp->base;
720}
721
722static struct dpp *dcn21_dpp_create(
723 struct dc_context *ctx,
724 uint32_t inst)
725{
726 struct dcn20_dpp *dpp =
727 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
728
729 if (!dpp)
730 return NULL;
731
732 if (dpp2_construct(dpp, ctx, inst,
733 &tf_regs[inst], &tf_shift, &tf_mask))
734 return &dpp->base;
735
736 BREAK_TO_DEBUGGER();
737 kfree(dpp);
738 return NULL;
739}
740
741static struct dce_aux *dcn21_aux_engine_create(
742 struct dc_context *ctx,
743 uint32_t inst)
744{
745 struct aux_engine_dce110 *aux_engine =
746 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
747
748 if (!aux_engine)
749 return NULL;
750
751 dce110_aux_engine_construct(aux_engine, ctx, inst,
752 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
8276dd87 753 &aux_engine_regs[inst],
754 &aux_mask,
f6040a43 755 &aux_shift,
756 ctx->dc->caps.extended_aux_timeout_support);
6f4e6361
BL		 757
758 return &aux_engine->base;
759}
760
761#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
762
763static const struct dce_i2c_registers i2c_hw_regs[] = {
764 i2c_inst_regs(1),
765 i2c_inst_regs(2),
766 i2c_inst_regs(3),
767 i2c_inst_regs(4),
768 i2c_inst_regs(5),
769};
770
771static const struct dce_i2c_shift i2c_shifts = {
772 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
773};
774
775static const struct dce_i2c_mask i2c_masks = {
776 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
777};
778
779struct dce_i2c_hw *dcn21_i2c_hw_create(
780 struct dc_context *ctx,
781 uint32_t inst)
782{
783 struct dce_i2c_hw *dce_i2c_hw =
784 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
785
786 if (!dce_i2c_hw)
787 return NULL;
788
789 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
790 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
791
792 return dce_i2c_hw;
793}
794
795static const struct resource_caps res_cap_rn = {
796 .num_timing_generator = 4,
797 .num_opp = 4,
798 .num_video_plane = 4,
b356843e 799 .num_audio = 4, // 4 audio endpoints. 4 audio streams
6f4e6361
BL		 800 .num_stream_encoder = 5,
801 .num_pll = 5, // maybe 3 because the last two used for USB-c
802 .num_dwb = 1,
803 .num_ddc = 5,
652651ff 804 .num_vmid = 1,
6f4e6361 805 .num_dsc = 3,
6f4e6361
BL		 806};
807
808#ifdef DIAGS_BUILD
809static const struct resource_caps res_cap_rn_FPGA_4pipe = {
810 .num_timing_generator = 4,
811 .num_opp = 4,
812 .num_video_plane = 4,
813 .num_audio = 7,
814 .num_stream_encoder = 4,
815 .num_pll = 4,
816 .num_dwb = 1,
817 .num_ddc = 4,
818 .num_dsc = 0,
819};
820
821static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
822 .num_timing_generator = 2,
823 .num_opp = 2,
824 .num_video_plane = 2,
825 .num_audio = 7,
826 .num_stream_encoder = 2,
827 .num_pll = 4,
828 .num_dwb = 1,
829 .num_ddc = 4,
6f4e6361 830 .num_dsc = 2,
6f4e6361
BL		 831};
832#endif
833
834static const struct dc_plane_cap plane_cap = {
835 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
836 .blends_with_above = true,
837 .blends_with_below = true,
838 .per_pixel_alpha = true,
839
840 .pixel_format_support = {
841 .argb8888 = true,
842 .nv12 = true,
cbec6477
SW		 843 .fp16 = true,
844 .p010 = true
6f4e6361
BL		 845 },
846
847 .max_upscale_factor = {
848 .argb8888 = 16000,
849 .nv12 = 16000,
850 .fp16 = 16000
851 },
852
853 .max_downscale_factor = {
854 .argb8888 = 250,
855 .nv12 = 250,
856 .fp16 = 250
857 }
858};
859
860static const struct dc_debug_options debug_defaults_drv = {
f0a574c9 861 .disable_dmcu = false,
6f4e6361
BL		 862 .force_abm_enable = false,
863 .timing_trace = false,
864 .clock_trace = true,
865 .disable_pplib_clock_request = true,
cab5dec4 866 .min_disp_clk_khz = 100000,
6f4e6361 867 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
4d25a0d5 868 .force_single_disp_pipe_split = false,
6f4e6361
BL		 869 .disable_dcc = DCC_ENABLE,
870 .vsr_support = true,
871 .performance_trace = false,
947daab2 872 .max_downscale_src_width = 4096,
6f4e6361
BL		 873 .disable_pplib_wm_range = false,
874 .scl_reset_length10 = true,
875 .sanity_checks = true,
57133a28 876 .disable_48mhz_pwrdwn = false,
ee765924
GS		 877 .nv12_iflip_vm_wa = true,
878 .usbc_combo_phy_reset_wa = true
6f4e6361
BL		 879};
880
881static const struct dc_debug_options debug_defaults_diags = {
f0a574c9 882 .disable_dmcu = false,
6f4e6361
BL		 883 .force_abm_enable = false,
884 .timing_trace = true,
885 .clock_trace = true,
886 .disable_dpp_power_gate = true,
887 .disable_hubp_power_gate = true,
888 .disable_clock_gate = true,
889 .disable_pplib_clock_request = true,
890 .disable_pplib_wm_range = true,
891 .disable_stutter = true,
892 .disable_48mhz_pwrdwn = true,
893};
894
895enum dcn20_clk_src_array_id {
896 DCN20_CLK_SRC_PLL0,
897 DCN20_CLK_SRC_PLL1,
15add0c2 898 DCN20_CLK_SRC_PLL2,
6f4e6361
BL		 899 DCN20_CLK_SRC_TOTAL_DCN21
900};
901
d9e32672 902static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
6f4e6361
BL		 903{
904 unsigned int i;
905
906 for (i = 0; i < pool->base.stream_enc_count; i++) {
907 if (pool->base.stream_enc[i] != NULL) {
908 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
909 pool->base.stream_enc[i] = NULL;
910 }
911 }
912
6f4e6361
BL		 913 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
914 if (pool->base.dscs[i] != NULL)
915 dcn20_dsc_destroy(&pool->base.dscs[i]);
916 }
6f4e6361
BL		 917
918 if (pool->base.mpc != NULL) {
919 kfree(TO_DCN20_MPC(pool->base.mpc));
920 pool->base.mpc = NULL;
921 }
922 if (pool->base.hubbub != NULL) {
923 kfree(pool->base.hubbub);
924 pool->base.hubbub = NULL;
925 }
926 for (i = 0; i < pool->base.pipe_count; i++) {
927 if (pool->base.dpps[i] != NULL)
928 dcn20_dpp_destroy(&pool->base.dpps[i]);
929
930 if (pool->base.ipps[i] != NULL)
931 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
932
933 if (pool->base.hubps[i] != NULL) {
934 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
935 pool->base.hubps[i] = NULL;
936 }
937
938 if (pool->base.irqs != NULL) {
939 dal_irq_service_destroy(&pool->base.irqs);
940 }
941 }
942
943 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
944 if (pool->base.engines[i] != NULL)
945 dce110_engine_destroy(&pool->base.engines[i]);
946 if (pool->base.hw_i2cs[i] != NULL) {
947 kfree(pool->base.hw_i2cs[i]);
948 pool->base.hw_i2cs[i] = NULL;
949 }
950 if (pool->base.sw_i2cs[i] != NULL) {
951 kfree(pool->base.sw_i2cs[i]);
952 pool->base.sw_i2cs[i] = NULL;
953 }
954 }
955
956 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
957 if (pool->base.opps[i] != NULL)
958 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
959 }
960
961 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
962 if (pool->base.timing_generators[i] != NULL) {
963 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
964 pool->base.timing_generators[i] = NULL;
965 }
966 }
967
968 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
969 if (pool->base.dwbc[i] != NULL) {
970 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
971 pool->base.dwbc[i] = NULL;
972 }
973 if (pool->base.mcif_wb[i] != NULL) {
974 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
975 pool->base.mcif_wb[i] = NULL;
976 }
977 }
978
979 for (i = 0; i < pool->base.audio_count; i++) {
980 if (pool->base.audios[i])
981 dce_aud_destroy(&pool->base.audios[i]);
982 }
983
984 for (i = 0; i < pool->base.clk_src_count; i++) {
985 if (pool->base.clock_sources[i] != NULL) {
986 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
987 pool->base.clock_sources[i] = NULL;
988 }
989 }
990
991 if (pool->base.dp_clock_source != NULL) {
992 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
993 pool->base.dp_clock_source = NULL;
994 }
995
16012806 996 if (pool->base.abm != NULL) {
501b4026 997 if (pool->base.abm->ctx->dc->config.disable_dmcu)
16012806
WW		 998 dmub_abm_destroy(&pool->base.abm);
999 else
1000 dce_abm_destroy(&pool->base.abm);
1001 }
6f4e6361
BL		 1002
1003 if (pool->base.dmcu != NULL)
1004 dce_dmcu_destroy(&pool->base.dmcu);
1005
9dac88d8
WW		 1006 if (pool->base.psr != NULL)
1007 dmub_psr_destroy(&pool->base.psr);
1008
6f4e6361
BL		 1009 if (pool->base.dccg != NULL)
1010 dcn_dccg_destroy(&pool->base.dccg);
1011
1012 if (pool->base.pp_smu != NULL)
44e149bb 1013 dcn21_pp_smu_destroy(&pool->base.pp_smu);
6f4e6361
BL		 1014}
1015
1016
1017static void calculate_wm_set_for_vlevel(
1018 int vlevel,
1019 struct wm_range_table_entry *table_entry,
1020 struct dcn_watermarks *wm_set,
1021 struct display_mode_lib *dml,
1022 display_e2e_pipe_params_st *pipes,
1023 int pipe_cnt)
1024{
1025 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
1026
1027 ASSERT(vlevel < dml->soc.num_states);
1028 /* only pipe 0 is read for voltage and dcf/soc clocks */
1029 pipes[0].clks_cfg.voltage = vlevel;
1030 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
1031 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
1032
1033 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
d3511fd0
EY		 1034 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
1035 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
6f4e6361
BL		 1036
1037 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
1038 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
1039 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
1040 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1041 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
6f4e6361
BL		 1042 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
1043 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
b617b265 1044 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
6f4e6361
BL		 1045 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
1046
1047}
1048
15fdbcc5
LH		 1049static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
1050{
d3511fd0
EY		 1051 int i;
1052
6ca3928d
TP		 1053 DC_FP_START();
1054
15fdbcc5 1055 if (dc->bb_overrides.sr_exit_time_ns) {
d3511fd0
EY		 1056 for (i = 0; i < WM_SET_COUNT; i++) {
1057 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
1058 dc->bb_overrides.sr_exit_time_ns / 1000.0;
1059 }
15fdbcc5
LH		 1060 }
1061
1062 if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
d3511fd0
EY		 1063 for (i = 0; i < WM_SET_COUNT; i++) {
1064 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
1065 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
1066 }
15fdbcc5
LH		 1067 }
1068
1069 if (dc->bb_overrides.urgent_latency_ns) {
1070 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
1071 }
1072
1073 if (dc->bb_overrides.dram_clock_change_latency_ns) {
580c8be2
JG		 1074 for (i = 0; i < WM_SET_COUNT; i++) {
1075 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
15fdbcc5 1076 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
580c8be2 1077 }
15fdbcc5 1078 }
580c8be2 1079
6ca3928d 1080 DC_FP_END();
15fdbcc5
LH		 1081}
1082
6f4e6361
BL		 1083void dcn21_calculate_wm(
1084 struct dc *dc, struct dc_state *context,
1085 display_e2e_pipe_params_st *pipes,
1086 int *out_pipe_cnt,
1087 int *pipe_split_from,
1088 int vlevel_req)
1089{
1090 int pipe_cnt, i, pipe_idx;
1091 int vlevel, vlevel_max;
1092 struct wm_range_table_entry *table_entry;
1093 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
1094
1095 ASSERT(bw_params);
1096
15fdbcc5
LH		 1097 patch_bounding_box(dc, &context->bw_ctx.dml.soc);
1098
6f4e6361
BL		 1099 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1100 if (!context->res_ctx.pipe_ctx[i].stream)
1101 continue;
1102
1103 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1104 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
1105
1106 if (pipe_split_from[i] < 0) {
1107 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1108 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1109 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1110 pipes[pipe_cnt].pipe.dest.odm_combine =
1111 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
1112 else
1113 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1114 pipe_idx++;
1115 } else {
1116 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1117 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1118 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1119 pipes[pipe_cnt].pipe.dest.odm_combine =
1120 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];
1121 else
1122 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1123 }
1124 pipe_cnt++;
1125 }
1126
1127 if (pipe_cnt != pipe_idx) {
1128 if (dc->res_pool->funcs->populate_dml_pipes)
1129 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2f488884 1130 context, pipes);
6f4e6361 1131 else
8c357309 1132 pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
2f488884 1133 context, pipes);
6f4e6361
BL		 1134 }
1135
1136 *out_pipe_cnt = pipe_cnt;
1137
1138 vlevel_max = bw_params->clk_table.num_entries - 1;
1139
1140
1141 /* WM Set D */
1142 table_entry = &bw_params->wm_table.entries[WM_D];
1143 if (table_entry->wm_type == WM_TYPE_RETRAINING)
1144 vlevel = 0;
1145 else
1146 vlevel = vlevel_max;
1147 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
1148 &context->bw_ctx.dml, pipes, pipe_cnt);
1149 /* WM Set C */
1150 table_entry = &bw_params->wm_table.entries[WM_C];
1151 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
1152 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
1153 &context->bw_ctx.dml, pipes, pipe_cnt);
1154 /* WM Set B */
1155 table_entry = &bw_params->wm_table.entries[WM_B];
1156 vlevel = MIN(MAX(vlevel_req, 1), vlevel_max);
1157 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
1158 &context->bw_ctx.dml, pipes, pipe_cnt);
1159
1160 /* WM Set A */
1161 table_entry = &bw_params->wm_table.entries[WM_A];
1162 vlevel = MIN(vlevel_req, vlevel_max);
1163 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
1164 &context->bw_ctx.dml, pipes, pipe_cnt);
1165}
1166
1167
1168bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
1169 bool fast_validate)
1170{
1171 bool out = false;
1172
1173 BW_VAL_TRACE_SETUP();
1174
1175 int vlevel = 0;
1176 int pipe_split_from[MAX_PIPES];
1177 int pipe_cnt = 0;
1178 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1179 DC_LOGGER_INIT(dc->ctx->logger);
1180
1181 BW_VAL_TRACE_COUNT();
1182
1183 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
1184
1185 if (pipe_cnt == 0)
1186 goto validate_out;
1187
1188 if (!out)
1189 goto validate_fail;
1190
1191 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1192
1193 if (fast_validate) {
1194 BW_VAL_TRACE_SKIP(fast);
1195 goto validate_out;
1196 }
1197
1198 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
1199 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1200
1201 BW_VAL_TRACE_END_WATERMARKS();
1202
1203 goto validate_out;
1204
1205validate_fail:
1206 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1207 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1208
1209 BW_VAL_TRACE_SKIP(fail);
1210 out = false;
1211
1212validate_out:
1213 kfree(pipes);
1214
1215 BW_VAL_TRACE_FINISH();
1216
1217 return out;
1218}
1219static void dcn21_destroy_resource_pool(struct resource_pool **pool)
1220{
1221 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
1222
d9e32672 1223 dcn21_resource_destruct(dcn21_pool);
6f4e6361
BL		 1224 kfree(dcn21_pool);
1225 *pool = NULL;
1226}
1227
1228static struct clock_source *dcn21_clock_source_create(
1229 struct dc_context *ctx,
1230 struct dc_bios *bios,
1231 enum clock_source_id id,
1232 const struct dce110_clk_src_regs *regs,
1233 bool dp_clk_src)
1234{
1235 struct dce110_clk_src *clk_src =
1236 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1237
1238 if (!clk_src)
1239 return NULL;
1240
1241 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1242 regs, &cs_shift, &cs_mask)) {
1243 clk_src->base.dp_clk_src = dp_clk_src;
1244 return &clk_src->base;
1245 }
1246
1247 BREAK_TO_DEBUGGER();
1248 return NULL;
1249}
1250
1251static struct hubp *dcn21_hubp_create(
1252 struct dc_context *ctx,
1253 uint32_t inst)
1254{
1255 struct dcn21_hubp *hubp21 =
1256 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);
1257
1258 if (!hubp21)
1259 return NULL;
1260
1261 if (hubp21_construct(hubp21, ctx, inst,
1262 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1263 return &hubp21->base;
1264
1265 BREAK_TO_DEBUGGER();
1266 kfree(hubp21);
1267 return NULL;
1268}
1269
1270static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
1271{
1272 int i;
1273
1274 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1275 GFP_KERNEL);
1276
1277 if (!hubbub)
1278 return NULL;
1279
1280 hubbub21_construct(hubbub, ctx,
1281 &hubbub_reg,
1282 &hubbub_shift,
1283 &hubbub_mask);
1284
1285 for (i = 0; i < res_cap_rn.num_vmid; i++) {
1286 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1287
1288 vmid->ctx = ctx;
1289
1290 vmid->regs = &vmid_regs[i];
1291 vmid->shifts = &vmid_shifts;
1292 vmid->masks = &vmid_masks;
1293 }
1294
1295 return &hubbub->base;
1296}
1297
1298struct output_pixel_processor *dcn21_opp_create(
1299 struct dc_context *ctx, uint32_t inst)
1300{
1301 struct dcn20_opp *opp =
1302 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1303
1304 if (!opp) {
1305 BREAK_TO_DEBUGGER();
1306 return NULL;
1307 }
1308
1309 dcn20_opp_construct(opp, ctx, inst,
1310 &opp_regs[inst], &opp_shift, &opp_mask);
1311 return &opp->base;
1312}
1313
1314struct timing_generator *dcn21_timing_generator_create(
1315 struct dc_context *ctx,
1316 uint32_t instance)
1317{
1318 struct optc *tgn10 =
1319 kzalloc(sizeof(struct optc), GFP_KERNEL);
1320
1321 if (!tgn10)
1322 return NULL;
1323
1324 tgn10->base.inst = instance;
1325 tgn10->base.ctx = ctx;
1326
1327 tgn10->tg_regs = &tg_regs[instance];
1328 tgn10->tg_shift = &tg_shift;
1329 tgn10->tg_mask = &tg_mask;
1330
1331 dcn20_timing_generator_init(tgn10);
1332
1333 return &tgn10->base;
1334}
1335
1336struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1337{
1338 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1339 GFP_KERNEL);
1340
1341 if (!mpc20)
1342 return NULL;
1343
1344 dcn20_mpc_construct(mpc20, ctx,
1345 &mpc_regs,
1346 &mpc_shift,
1347 &mpc_mask,
1348 6);
1349
1350 return &mpc20->base;
1351}
1352
1353static void read_dce_straps(
1354 struct dc_context *ctx,
1355 struct resource_straps *straps)
1356{
1357 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1358 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1359
1360}
1361
6f4e6361
BL		 1362
1363struct display_stream_compressor *dcn21_dsc_create(
1364 struct dc_context *ctx, uint32_t inst)
1365{
1366 struct dcn20_dsc *dsc =
1367 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1368
1369 if (!dsc) {
1370 BREAK_TO_DEBUGGER();
1371 return NULL;
1372 }
1373
1374 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1375 return &dsc->base;
1376}
6f4e6361
BL		 1377
1378static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1379{
1380 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
1381 struct clk_limit_table *clk_table = &bw_params->clk_table;
a39a5816
EY		 1382 unsigned int i, j, k;
1383 int closest_clk_lvl;
1384
c42656f8
DL		 1385 // Default clock levels are used for diags, which may lead to overclocking.
1386 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) && !IS_DIAG_DC(dc->ctx->dce_environment)) {
a39a5816
EY		 1387 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1388 dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
1389 dcn2_1_soc.num_chans = bw_params->num_channels;
1390
1391 /* Vmin: leave lowest DCN clocks, override with dcfclk, fclk, memclk from fuse */
1392 dcn2_1_soc.clock_limits[0].state = 0;
1393 dcn2_1_soc.clock_limits[0].dcfclk_mhz = clk_table->entries[0].dcfclk_mhz;
1394 dcn2_1_soc.clock_limits[0].fabricclk_mhz = clk_table->entries[0].fclk_mhz;
1395 dcn2_1_soc.clock_limits[0].socclk_mhz = clk_table->entries[0].socclk_mhz;
1396 dcn2_1_soc.clock_limits[0].dram_speed_mts = clk_table->entries[0].memclk_mhz * 2;
1397
1398 /*
c42656f8
DL		 1399 * Other levels: find closest DCN clocks that fit the given clock limit using dcfclk
1400 * as indicator
a39a5816
EY		 1401 */
1402
1403 closest_clk_lvl = -1;
1404 /* index currently being filled */
1405 k = 1;
1406 for (i = 1; i < clk_table->num_entries; i++) {
c42656f8
DL		 1407 /* loop backwards, skip duplicate state*/
1408 for (j = dcn2_1_soc.num_states - 1; j >= k; j--) {
a39a5816
EY		 1409 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
1410 closest_clk_lvl = j;
1411 break;
1412 }
1413 }
6f4e6361 1414
a39a5816
EY		 1415 /* if found a lvl that fits, use the DCN clks from it, if not, go to next clk limit*/
1416 if (closest_clk_lvl != -1) {
1417 dcn2_1_soc.clock_limits[k].state = i;
1418 dcn2_1_soc.clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
1419 dcn2_1_soc.clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
1420 dcn2_1_soc.clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
1421 dcn2_1_soc.clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
1422
1423 dcn2_1_soc.clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
1424 dcn2_1_soc.clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
1425 dcn2_1_soc.clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
1426 dcn2_1_soc.clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
1427 dcn2_1_soc.clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
1428 dcn2_1_soc.clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
1429 dcn2_1_soc.clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
1430 k++;
1431 }
1432 }
c42656f8 1433 dcn2_1_soc.num_states = k;
6f4e6361 1434 }
08f6c859 1435
c42656f8
DL		 1436 /* duplicate last level */
1437 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
1438 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;
1439
a39a5816 1440 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
6f4e6361
BL		 1441}
1442
1443/* Temporary Place holder until we can get them from fuse */
1444static struct dpm_clocks dummy_clocks = {
1445 .DcfClocks = {
1446 {.Freq = 400, .Vol = 1},
1447 {.Freq = 483, .Vol = 1},
1448 {.Freq = 602, .Vol = 1},
1449 {.Freq = 738, .Vol = 1} },
1450 .SocClocks = {
1451 {.Freq = 300, .Vol = 1},
1452 {.Freq = 400, .Vol = 1},
1453 {.Freq = 400, .Vol = 1},
1454 {.Freq = 400, .Vol = 1} },
1455 .FClocks = {
1456 {.Freq = 400, .Vol = 1},
1457 {.Freq = 800, .Vol = 1},
1458 {.Freq = 1067, .Vol = 1},
1459 {.Freq = 1600, .Vol = 1} },
1460 .MemClocks = {
1461 {.Freq = 800, .Vol = 1},
1462 {.Freq = 1600, .Vol = 1},
1463 {.Freq = 1067, .Vol = 1},
1464 {.Freq = 1600, .Vol = 1} },
1465
1466};
1467
976035dd 1468static enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp,
6f4e6361
BL		 1469 struct pp_smu_wm_range_sets *ranges)
1470{
1471 return PP_SMU_RESULT_OK;
1472}
1473
976035dd 1474static enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp,
6f4e6361
BL		 1475 struct dpm_clocks *clock_table)
1476{
1477 *clock_table = dummy_clocks;
1478 return PP_SMU_RESULT_OK;
1479}
1480
976035dd 1481static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
6f4e6361
BL		 1482{
1483 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
1484
a51894f0
EY		 1485 if (!pp_smu)
1486 return pp_smu;
6f4e6361 1487
3794943c 1488 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment) || IS_DIAG_DC(ctx->dce_environment)) {
a51894f0
EY		 1489 pp_smu->ctx.ver = PP_SMU_VER_RN;
1490 pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table;
1491 pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges;
1492 } else {
1493
1494 dm_pp_get_funcs(ctx, pp_smu);
1495
1496 if (pp_smu->ctx.ver != PP_SMU_VER_RN)
1497 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
1498 }
6f4e6361
BL		 1499
1500 return pp_smu;
1501}
1502
976035dd 1503static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
6f4e6361
BL		 1504{
1505 if (pp_smu && *pp_smu) {
1506 kfree(*pp_smu);
1507 *pp_smu = NULL;
1508 }
1509}
1510
1511static struct audio *dcn21_create_audio(
1512 struct dc_context *ctx, unsigned int inst)
1513{
1514 return dce_audio_create(ctx, inst,
1515 &audio_regs[inst], &audio_shift, &audio_mask);
1516}
1517
1518static struct dc_cap_funcs cap_funcs = {
1519 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1520};
1521
1522struct stream_encoder *dcn21_stream_encoder_create(
1523 enum engine_id eng_id,
1524 struct dc_context *ctx)
1525{
1526 struct dcn10_stream_encoder *enc1 =
1527 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1528
1529 if (!enc1)
1530 return NULL;
1531
1532 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1533 &stream_enc_regs[eng_id],
1534 &se_shift, &se_mask);
1535
1536 return &enc1->base;
1537}
1538
1539static const struct dce_hwseq_registers hwseq_reg = {
1540 HWSEQ_DCN21_REG_LIST()
1541};
1542
1543static const struct dce_hwseq_shift hwseq_shift = {
1544 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
1545};
1546
1547static const struct dce_hwseq_mask hwseq_mask = {
1548 HWSEQ_DCN21_MASK_SH_LIST(_MASK)
1549};
1550
1551static struct dce_hwseq *dcn21_hwseq_create(
1552 struct dc_context *ctx)
1553{
1554 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1555
1556 if (hws) {
1557 hws->ctx = ctx;
1558 hws->regs = &hwseq_reg;
1559 hws->shifts = &hwseq_shift;
1560 hws->masks = &hwseq_mask;
f93e29f0 1561 hws->wa.DEGVIDCN21 = true;
d9758768 1562 hws->wa.disallow_self_refresh_during_multi_plane_transition = true;
6f4e6361
BL		 1563 }
1564 return hws;
1565}
1566
1567static const struct resource_create_funcs res_create_funcs = {
1568 .read_dce_straps = read_dce_straps,
1569 .create_audio = dcn21_create_audio,
1570 .create_stream_encoder = dcn21_stream_encoder_create,
1571 .create_hwseq = dcn21_hwseq_create,
1572};
1573
1574static const struct resource_create_funcs res_create_maximus_funcs = {
1575 .read_dce_straps = NULL,
1576 .create_audio = NULL,
1577 .create_stream_encoder = NULL,
1578 .create_hwseq = dcn21_hwseq_create,
1579};
1580
91c665bd
BL		 1581static const struct encoder_feature_support link_enc_feature = {
1582 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1583 .max_hdmi_pixel_clock = 600000,
1584 .hdmi_ycbcr420_supported = true,
1585 .dp_ycbcr420_supported = true,
c14b726e 1586 .fec_supported = true,
91c665bd
BL		 1587 .flags.bits.IS_HBR2_CAPABLE = true,
1588 .flags.bits.IS_HBR3_CAPABLE = true,
1589 .flags.bits.IS_TPS3_CAPABLE = true,
1590 .flags.bits.IS_TPS4_CAPABLE = true
1591};
1592
1593
1594#define link_regs(id, phyid)\
1595[id] = {\
a771ded8 1596 LE_DCN2_REG_LIST(id), \
91c665bd 1597 UNIPHY_DCN2_REG_LIST(phyid), \
a771ded8 1598 DPCS_DCN21_REG_LIST(id), \
91c665bd
BL		 1599 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
1600}
1601
1602static const struct dcn10_link_enc_registers link_enc_regs[] = {
1603 link_regs(0, A),
1604 link_regs(1, B),
1605 link_regs(2, C),
1606 link_regs(3, D),
1607 link_regs(4, E),
1608};
1609
d4caa72e
AK		 1610static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
1611 { DCN_PANEL_CNTL_REG_LIST() }
904fb6e0
AK		 1612};
1613
d4caa72e
AK		 1614static const struct dce_panel_cntl_shift panel_cntl_shift = {
1615 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
904fb6e0
AK		 1616};
1617
d4caa72e
AK		 1618static const struct dce_panel_cntl_mask panel_cntl_mask = {
1619 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
904fb6e0
AK		 1620};
1621
91c665bd
BL		 1622#define aux_regs(id)\
1623[id] = {\
1624 DCN2_AUX_REG_LIST(id)\
1625}
1626
1627static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1628 aux_regs(0),
1629 aux_regs(1),
1630 aux_regs(2),
1631 aux_regs(3),
1632 aux_regs(4)
1633};
1634
1635#define hpd_regs(id)\
1636[id] = {\
1637 HPD_REG_LIST(id)\
1638}
1639
1640static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1641 hpd_regs(0),
1642 hpd_regs(1),
1643 hpd_regs(2),
1644 hpd_regs(3),
1645 hpd_regs(4)
1646};
1647
1648static const struct dcn10_link_enc_shift le_shift = {
a771ded8
RL		 1649 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
1650 DPCS_DCN21_MASK_SH_LIST(__SHIFT)
91c665bd
BL		 1651};
1652
1653static const struct dcn10_link_enc_mask le_mask = {
a771ded8
RL		 1654 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
1655 DPCS_DCN21_MASK_SH_LIST(_MASK)
91c665bd
BL		 1656};
1657
bf7f5ac3
YMM		 1658static int map_transmitter_id_to_phy_instance(
1659 enum transmitter transmitter)
1660{
1661 switch (transmitter) {
1662 case TRANSMITTER_UNIPHY_A:
1663 return 0;
1664 break;
1665 case TRANSMITTER_UNIPHY_B:
1666 return 1;
1667 break;
1668 case TRANSMITTER_UNIPHY_C:
1669 return 2;
1670 break;
1671 case TRANSMITTER_UNIPHY_D:
1672 return 3;
1673 break;
1674 case TRANSMITTER_UNIPHY_E:
1675 return 4;
1676 break;
1677 default:
1678 ASSERT(0);
1679 return 0;
1680 }
1681}
1682
91c665bd
BL		 1683static struct link_encoder *dcn21_link_encoder_create(
1684 const struct encoder_init_data *enc_init_data)
1685{
1686 struct dcn21_link_encoder *enc21 =
1687 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
bf7f5ac3 1688 int link_regs_id;
91c665bd
BL		 1689
1690 if (!enc21)
1691 return NULL;
1692
bf7f5ac3
YMM		 1693 link_regs_id =
1694 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1695
91c665bd
BL		 1696 dcn21_link_encoder_construct(enc21,
1697 enc_init_data,
1698 &link_enc_feature,
bf7f5ac3 1699 &link_enc_regs[link_regs_id],
91c665bd
BL		 1700 &link_enc_aux_regs[enc_init_data->channel - 1],
1701 &link_enc_hpd_regs[enc_init_data->hpd_source],
1702 &le_shift,
1703 &le_mask);
1704
1705 return &enc21->enc10.base;
1706}
904fb6e0 1707
d4caa72e 1708static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_data *init_data)
904fb6e0 1709{
d4caa72e
AK		 1710 struct dce_panel_cntl *panel_cntl =
1711 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
904fb6e0 1712
d4caa72e 1713 if (!panel_cntl)
904fb6e0
AK		 1714 return NULL;
1715
d4caa72e 1716 dce_panel_cntl_construct(panel_cntl,
904fb6e0 1717 init_data,
d4caa72e
AK		 1718 &panel_cntl_regs[init_data->inst],
1719 &panel_cntl_shift,
1720 &panel_cntl_mask);
904fb6e0 1721
d4caa72e 1722 return &panel_cntl->base;
904fb6e0
AK		 1723}
1724
c0fb59a4
BL		 1725#define CTX ctx
1726
1727#define REG(reg_name) \
1728 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1729
1730static uint32_t read_pipe_fuses(struct dc_context *ctx)
1731{
1732 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1733 /* RV1 support max 4 pipes */
1734 value = value & 0xf;
1735 return value;
1736}
1737
8c357309 1738static int dcn21_populate_dml_pipes_from_context(
2f488884 1739 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)
8c357309 1740{
2f488884 1741 uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes);
8c357309
YS		 1742 int i;
1743
2a28fe92 1744 for (i = 0; i < pipe_cnt; i++) {
8c357309
YS		 1745
1746 pipes[i].pipe.src.hostvm = 1;
1747 pipes[i].pipe.src.gpuvm = 1;
1748 }
1749
1750 return pipe_cnt;
1751}
1752
8d8c82b6
JG		 1753enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1754{
1755 enum dc_status result = DC_OK;
1756
1757 if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {
1758 plane_state->dcc.enable = 1;
1759 /* align to our worst case block width */
1760 plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024;
1761 }
1762 result = dcn20_patch_unknown_plane_state(plane_state);
1763 return result;
1764}
1765
6f4e6361
BL		 1766static struct resource_funcs dcn21_res_pool_funcs = {
1767 .destroy = dcn21_destroy_resource_pool,
91c665bd 1768 .link_enc_create = dcn21_link_encoder_create,
d4caa72e 1769 .panel_cntl_create = dcn21_panel_cntl_create,
6f4e6361 1770 .validate_bandwidth = dcn21_validate_bandwidth,
8c357309 1771 .populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
6f4e6361
BL		 1772 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
1773 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1774 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1775 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
8d8c82b6 1776 .patch_unknown_plane_state = dcn21_patch_unknown_plane_state,
6f4e6361
BL		 1777 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1778 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1779 .update_bw_bounding_box = update_bw_bounding_box
1780};
1781
d9e32672 1782static bool dcn21_resource_construct(
6f4e6361
BL		 1783 uint8_t num_virtual_links,
1784 struct dc *dc,
1785 struct dcn21_resource_pool *pool)
1786{
c0fb59a4 1787 int i, j;
6f4e6361
BL		 1788 struct dc_context *ctx = dc->ctx;
1789 struct irq_service_init_data init_data;
c0fb59a4 1790 uint32_t pipe_fuses = read_pipe_fuses(ctx);
ff86391e 1791 uint32_t num_pipes;
6f4e6361
BL		 1792
1793 ctx->dc_bios->regs = &bios_regs;
1794
1795 pool->base.res_cap = &res_cap_rn;
1796#ifdef DIAGS_BUILD
1797 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1798 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc;
1799 pool->base.res_cap = &res_cap_rn_FPGA_4pipe;
1800#endif
1801
1802 pool->base.funcs = &dcn21_res_pool_funcs;
1803
1804 /*************************************************
1805 * Resource + asic cap harcoding *
1806 *************************************************/
1807 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1808
c0fb59a4
BL		 1809 /* max pipe num for ASIC before check pipe fuses */
1810 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1811
6f4e6361
BL		 1812 dc->caps.max_downscale_ratio = 200;
1813 dc->caps.i2c_speed_in_khz = 100;
1814 dc->caps.max_cursor_size = 256;
1815 dc->caps.dmdata_alloc_size = 2048;
1816 dc->caps.hw_3d_lut = true;
1817
1818 dc->caps.max_slave_planes = 1;
1819 dc->caps.post_blend_color_processing = true;
1820 dc->caps.force_dp_tps4_for_cp2520 = true;
ca4f844e 1821 dc->caps.extended_aux_timeout_support = true;
3a1627b0 1822 dc->caps.dmcub_support = true;
3cfe9fb6 1823 dc->caps.is_apu = true;
6f4e6361
BL		 1824
1825 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1826 dc->debug = debug_defaults_drv;
1827 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1828 pool->base.pipe_count = 4;
1829 dc->debug = debug_defaults_diags;
1830 } else
1831 dc->debug = debug_defaults_diags;
1832
1833 // Init the vm_helper
1834 if (dc->vm_helper)
1835 vm_helper_init(dc->vm_helper, 16);
1836
1837 /*************************************************
1838 * Create resources *
1839 *************************************************/
1840
1841 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1842 dcn21_clock_source_create(ctx, ctx->dc_bios,
1843 CLOCK_SOURCE_COMBO_PHY_PLL0,
1844 &clk_src_regs[0], false);
1845 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1846 dcn21_clock_source_create(ctx, ctx->dc_bios,
1847 CLOCK_SOURCE_COMBO_PHY_PLL1,
1848 &clk_src_regs[1], false);
15add0c2
IZ		 1849 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
1850 dcn21_clock_source_create(ctx, ctx->dc_bios,
1851 CLOCK_SOURCE_COMBO_PHY_PLL2,
1852 &clk_src_regs[2], false);
6f4e6361
BL		 1853
1854 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
1855
1856 /* todo: not reuse phy_pll registers */
1857 pool->base.dp_clock_source =
1858 dcn21_clock_source_create(ctx, ctx->dc_bios,
1859 CLOCK_SOURCE_ID_DP_DTO,
1860 &clk_src_regs[0], true);
1861
1862 for (i = 0; i < pool->base.clk_src_count; i++) {
1863 if (pool->base.clock_sources[i] == NULL) {
1864 dm_error("DC: failed to create clock sources!\n");
1865 BREAK_TO_DEBUGGER();
1866 goto create_fail;
1867 }
1868 }
1869
1870 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1871 if (pool->base.dccg == NULL) {
1872 dm_error("DC: failed to create dccg!\n");
1873 BREAK_TO_DEBUGGER();
1874 goto create_fail;
1875 }
1876
501b4026 1877 if (!dc->config.disable_dmcu) {
16012806
WW		 1878 pool->base.dmcu = dcn21_dmcu_create(ctx,
1879 &dmcu_regs,
1880 &dmcu_shift,
1881 &dmcu_mask);
1882 if (pool->base.dmcu == NULL) {
1883 dm_error("DC: failed to create dmcu!\n");
1884 BREAK_TO_DEBUGGER();
1885 goto create_fail;
1886 }
c0fb59a4
BL		 1887 }
1888
501b4026 1889 if (dc->config.disable_dmcu) {
9dac88d8
WW		 1890 pool->base.psr = dmub_psr_create(ctx);
1891
1892 if (pool->base.psr == NULL) {
1893 dm_error("DC: failed to create psr obj!\n");
1894 BREAK_TO_DEBUGGER();
1895 goto create_fail;
1896 }
1897 }
4c1a1335 1898
501b4026 1899 if (dc->config.disable_dmcu)
16012806
WW		 1900 pool->base.abm = dmub_abm_create(ctx,
1901 &abm_regs,
1902 &abm_shift,
1903 &abm_mask);
1904 else
1905 pool->base.abm = dce_abm_create(ctx,
c0fb59a4
BL		 1906 &abm_regs,
1907 &abm_shift,
1908 &abm_mask);
c0fb59a4 1909
6f4e6361
BL		 1910 pool->base.pp_smu = dcn21_pp_smu_create(ctx);
1911
ff86391e
MS		 1912 num_pipes = dcn2_1_ip.max_num_dpp;
1913
1914 for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
1915 if (pipe_fuses & 1 << i)
1916 num_pipes--;
1917 dcn2_1_ip.max_num_dpp = num_pipes;
1918 dcn2_1_ip.max_num_otg = num_pipes;
1919
6f4e6361
BL		 1920 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1921
1922 init_data.ctx = dc->ctx;
1923 pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
1924 if (!pool->base.irqs)
1925 goto create_fail;
1926
c0fb59a4 1927 j = 0;
6f4e6361
BL		 1928 /* mem input -> ipp -> dpp -> opp -> TG */
1929 for (i = 0; i < pool->base.pipe_count; i++) {
c0fb59a4
BL		 1930 /* if pipe is disabled, skip instance of HW pipe,
1931 * i.e, skip ASIC register instance
1932 */
1933 if ((pipe_fuses & (1 << i)) != 0)
1934 continue;
1935
b9f1246d
NA		 1936 pool->base.hubps[j] = dcn21_hubp_create(ctx, i);
1937 if (pool->base.hubps[j] == NULL) {
6f4e6361
BL		 1938 BREAK_TO_DEBUGGER();
1939 dm_error(
1940 "DC: failed to create memory input!\n");
1941 goto create_fail;
1942 }
1943
b9f1246d
NA		 1944 pool->base.ipps[j] = dcn21_ipp_create(ctx, i);
1945 if (pool->base.ipps[j] == NULL) {
6f4e6361
BL		 1946 BREAK_TO_DEBUGGER();
1947 dm_error(
1948 "DC: failed to create input pixel processor!\n");
1949 goto create_fail;
1950 }
1951
b9f1246d
NA		 1952 pool->base.dpps[j] = dcn21_dpp_create(ctx, i);
1953 if (pool->base.dpps[j] == NULL) {
6f4e6361
BL		 1954 BREAK_TO_DEBUGGER();
1955 dm_error(
1956 "DC: failed to create dpps!\n");
1957 goto create_fail;
1958 }
c0fb59a4 1959
b9f1246d
NA		 1960 pool->base.opps[j] = dcn21_opp_create(ctx, i);
1961 if (pool->base.opps[j] == NULL) {
c0fb59a4
BL		 1962 BREAK_TO_DEBUGGER();
1963 dm_error(
1964 "DC: failed to create output pixel processor!\n");
1965 goto create_fail;
1966 }
1967
b9f1246d 1968 pool->base.timing_generators[j] = dcn21_timing_generator_create(
c0fb59a4 1969 ctx, i);
b9f1246d 1970 if (pool->base.timing_generators[j] == NULL) {
c0fb59a4
BL		 1971 BREAK_TO_DEBUGGER();
1972 dm_error("DC: failed to create tg!\n");
1973 goto create_fail;
1974 }
1975 j++;
6f4e6361
BL		 1976 }
1977
1978 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1979 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
1980 if (pool->base.engines[i] == NULL) {
1981 BREAK_TO_DEBUGGER();
1982 dm_error(
1983 "DC:failed to create aux engine!!\n");
1984 goto create_fail;
1985 }
1986 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
1987 if (pool->base.hw_i2cs[i] == NULL) {
1988 BREAK_TO_DEBUGGER();
1989 dm_error(
1990 "DC:failed to create hw i2c!!\n");
1991 goto create_fail;
1992 }
1993 pool->base.sw_i2cs[i] = NULL;
1994 }
1995
c0fb59a4
BL		 1996 pool->base.timing_generator_count = j;
1997 pool->base.pipe_count = j;
1998 pool->base.mpcc_count = j;
6f4e6361
BL		 1999
2000 pool->base.mpc = dcn21_mpc_create(ctx);
2001 if (pool->base.mpc == NULL) {
2002 BREAK_TO_DEBUGGER();
2003 dm_error("DC: failed to create mpc!\n");
2004 goto create_fail;
2005 }
2006
2007 pool->base.hubbub = dcn21_hubbub_create(ctx);
2008 if (pool->base.hubbub == NULL) {
2009 BREAK_TO_DEBUGGER();
2010 dm_error("DC: failed to create hubbub!\n");
2011 goto create_fail;
2012 }
2013
6f4e6361
BL		 2014 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2015 pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
2016 if (pool->base.dscs[i] == NULL) {
2017 BREAK_TO_DEBUGGER();
2018 dm_error("DC: failed to create display stream compressor %d!\n", i);
2019 goto create_fail;
2020 }
2021 }
6f4e6361
BL		 2022
2023 if (!dcn20_dwbc_create(ctx, &pool->base)) {
2024 BREAK_TO_DEBUGGER();
2025 dm_error("DC: failed to create dwbc!\n");
2026 goto create_fail;
2027 }
2028 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
2029 BREAK_TO_DEBUGGER();
2030 dm_error("DC: failed to create mcif_wb!\n");
2031 goto create_fail;
2032 }
2033
2034 if (!resource_construct(num_virtual_links, dc, &pool->base,
2035 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2036 &res_create_funcs : &res_create_maximus_funcs)))
2037 goto create_fail;
2038
c0fb59a4 2039 dcn21_hw_sequencer_construct(dc);
6f4e6361
BL		 2040
2041 dc->caps.max_planes = pool->base.pipe_count;
2042
2043 for (i = 0; i < dc->caps.max_planes; ++i)
2044 dc->caps.planes[i] = plane_cap;
2045
2046 dc->cap_funcs = cap_funcs;
2047
2048 return true;
2049
2050create_fail:
2051
d9e32672 2052 dcn21_resource_destruct(pool);
6f4e6361
BL		 2053
2054 return false;
2055}
2056
2057struct resource_pool *dcn21_create_resource_pool(
2058 const struct dc_init_data *init_data,
2059 struct dc *dc)
2060{
2061 struct dcn21_resource_pool *pool =
2062 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);
2063
2064 if (!pool)
2065 return NULL;
2066
d9e32672 2067 if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
6f4e6361
BL		 2068 return &pool->base;
2069
2070 BREAK_TO_DEBUGGER();
2071 kfree(pool);
2072 return NULL;
2073}
Linux 6.x block layer and io_uring tree(s)