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Merge tag 'devprop-5.12-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael...
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / dc / dcn21 / dcn21_resource.c
CommitLineData
6f4e6361
BL		 1/*
2* Copyright 2018 Advanced Micro Devices, Inc.
6ca3928d 3 * Copyright 2019 Raptor Engineering, LLC
6f4e6361
BL		 4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
aec43402
AB		 27#include <linux/slab.h>
28
6f4e6361
BL		 29#include "dm_services.h"
30#include "dc.h"
31
78c77382
AK		 32#include "dcn21_init.h"
33
6f4e6361
BL		 34#include "resource.h"
35#include "include/irq_service_interface.h"
36#include "dcn20/dcn20_resource.h"
37
38#include "clk_mgr.h"
39#include "dcn10/dcn10_hubp.h"
40#include "dcn10/dcn10_ipp.h"
41#include "dcn20/dcn20_hubbub.h"
42#include "dcn20/dcn20_mpc.h"
43#include "dcn20/dcn20_hubp.h"
44#include "dcn21_hubp.h"
45#include "irq/dcn21/irq_service_dcn21.h"
46#include "dcn20/dcn20_dpp.h"
47#include "dcn20/dcn20_optc.h"
c0fb59a4 48#include "dcn21/dcn21_hwseq.h"
6f4e6361
BL		 49#include "dce110/dce110_hw_sequencer.h"
50#include "dcn20/dcn20_opp.h"
51#include "dcn20/dcn20_dsc.h"
91c665bd 52#include "dcn21/dcn21_link_encoder.h"
6f4e6361
BL		 53#include "dcn20/dcn20_stream_encoder.h"
54#include "dce/dce_clock_source.h"
55#include "dce/dce_audio.h"
56#include "dce/dce_hwseq.h"
57#include "virtual/virtual_stream_encoder.h"
58#include "dce110/dce110_resource.h"
59#include "dml/display_mode_vba.h"
60#include "dcn20/dcn20_dccg.h"
c07cbc1f 61#include "dcn21/dcn21_dccg.h"
6f4e6361
BL		 62#include "dcn21_hubbub.h"
63#include "dcn10/dcn10_resource.h"
15add0c2 64#include "dce110/dce110_resource.h"
d4caa72e 65#include "dce/dce_panel_cntl.h"
6f4e6361
BL		 66
67#include "dcn20/dcn20_dwb.h"
68#include "dcn20/dcn20_mmhubbub.h"
a771ded8
RL		 69#include "dpcs/dpcs_2_1_0_offset.h"
70#include "dpcs/dpcs_2_1_0_sh_mask.h"
6f4e6361
BL		 71
72#include "renoir_ip_offset.h"
73#include "dcn/dcn_2_1_0_offset.h"
74#include "dcn/dcn_2_1_0_sh_mask.h"
75
76#include "nbio/nbio_7_0_offset.h"
77
78#include "mmhub/mmhub_2_0_0_offset.h"
79#include "mmhub/mmhub_2_0_0_sh_mask.h"
80
81#include "reg_helper.h"
82#include "dce/dce_abm.h"
83#include "dce/dce_dmcu.h"
84#include "dce/dce_aux.h"
85#include "dce/dce_i2c.h"
86#include "dcn21_resource.h"
87#include "vm_helper.h"
88#include "dcn20/dcn20_vmid.h"
9dac88d8 89#include "dce/dmub_psr.h"
16012806 90#include "dce/dmub_abm.h"
6f4e6361 91
6f4e6361
BL		 92#define DC_LOGGER_INIT(logger)
93
94
95struct _vcs_dpi_ip_params_st dcn2_1_ip = {
652651ff 96 .odm_capable = 1,
8c357309
YS		 97 .gpuvm_enable = 1,
98 .hostvm_enable = 1,
6f4e6361
BL		 99 .gpuvm_max_page_table_levels = 1,
100 .hostvm_max_page_table_levels = 4,
101 .hostvm_cached_page_table_levels = 2,
6f4e6361 102 .num_dsc = 3,
6f4e6361
BL		 103 .rob_buffer_size_kbytes = 168,
104 .det_buffer_size_kbytes = 164,
105 .dpte_buffer_size_in_pte_reqs_luma = 44,
106 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
107 .dpp_output_buffer_pixels = 2560,
108 .opp_output_buffer_lines = 1,
109 .pixel_chunk_size_kbytes = 8,
110 .pte_enable = 1,
111 .max_page_table_levels = 4,
112 .pte_chunk_size_kbytes = 2,
113 .meta_chunk_size_kbytes = 2,
114 .writeback_chunk_size_kbytes = 2,
115 .line_buffer_size_bits = 789504,
116 .is_line_buffer_bpp_fixed = 0,
117 .line_buffer_fixed_bpp = 0,
118 .dcc_supported = true,
119 .max_line_buffer_lines = 12,
120 .writeback_luma_buffer_size_kbytes = 12,
121 .writeback_chroma_buffer_size_kbytes = 8,
122 .writeback_chroma_line_buffer_width_pixels = 4,
123 .writeback_max_hscl_ratio = 1,
124 .writeback_max_vscl_ratio = 1,
125 .writeback_min_hscl_ratio = 1,
126 .writeback_min_vscl_ratio = 1,
127 .writeback_max_hscl_taps = 12,
128 .writeback_max_vscl_taps = 12,
129 .writeback_line_buffer_luma_buffer_size = 0,
130 .writeback_line_buffer_chroma_buffer_size = 14643,
131 .cursor_buffer_size = 8,
132 .cursor_chunk_size = 2,
133 .max_num_otg = 4,
134 .max_num_dpp = 4,
135 .max_num_wb = 1,
136 .max_dchub_pscl_bw_pix_per_clk = 4,
137 .max_pscl_lb_bw_pix_per_clk = 2,
138 .max_lb_vscl_bw_pix_per_clk = 4,
139 .max_vscl_hscl_bw_pix_per_clk = 4,
140 .max_hscl_ratio = 4,
141 .max_vscl_ratio = 4,
142 .hscl_mults = 4,
143 .vscl_mults = 4,
144 .max_hscl_taps = 8,
145 .max_vscl_taps = 8,
146 .dispclk_ramp_margin_percent = 1,
147 .underscan_factor = 1.10,
148 .min_vblank_lines = 32, //
149 .dppclk_delay_subtotal = 77, //
150 .dppclk_delay_scl_lb_only = 16,
151 .dppclk_delay_scl = 50,
152 .dppclk_delay_cnvc_formatter = 8,
153 .dppclk_delay_cnvc_cursor = 6,
154 .dispclk_delay_subtotal = 87, //
155 .dcfclk_cstate_latency = 10, // SRExitTime
156 .max_inter_dcn_tile_repeaters = 8,
157
158 .xfc_supported = false,
159 .xfc_fill_bw_overhead_percent = 10.0,
160 .xfc_fill_constant_bytes = 0,
8f174fdb
YS		 161 .ptoi_supported = 0,
162 .number_of_cursors = 1,
6f4e6361
BL		 163};
164
165struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
166 .clock_limits = {
167 {
168 .state = 0,
a39a5816
EY		 169 .dcfclk_mhz = 400.0,
170 .fabricclk_mhz = 400.0,
171 .dispclk_mhz = 600.0,
172 .dppclk_mhz = 400.00,
6f4e6361
BL		 173 .phyclk_mhz = 600.0,
174 .socclk_mhz = 278.0,
175 .dscclk_mhz = 205.67,
176 .dram_speed_mts = 1600.0,
177 },
178 {
179 .state = 1,
a39a5816
EY		 180 .dcfclk_mhz = 464.52,
181 .fabricclk_mhz = 800.0,
182 .dispclk_mhz = 654.55,
183 .dppclk_mhz = 626.09,
6f4e6361
BL		 184 .phyclk_mhz = 600.0,
185 .socclk_mhz = 278.0,
186 .dscclk_mhz = 205.67,
187 .dram_speed_mts = 1600.0,
188 },
189 {
190 .state = 2,
a39a5816
EY		 191 .dcfclk_mhz = 514.29,
192 .fabricclk_mhz = 933.0,
193 .dispclk_mhz = 757.89,
194 .dppclk_mhz = 685.71,
195 .phyclk_mhz = 600.0,
6f4e6361
BL		 196 .socclk_mhz = 278.0,
197 .dscclk_mhz = 287.67,
a39a5816 198 .dram_speed_mts = 1866.0,
6f4e6361
BL		 199 },
200 {
201 .state = 3,
a39a5816
EY		 202 .dcfclk_mhz = 576.00,
203 .fabricclk_mhz = 1067.0,
204 .dispclk_mhz = 847.06,
205 .dppclk_mhz = 757.89,
206 .phyclk_mhz = 600.0,
6f4e6361
BL		 207 .socclk_mhz = 715.0,
208 .dscclk_mhz = 318.334,
a39a5816 209 .dram_speed_mts = 2134.0,
6f4e6361
BL		 210 },
211 {
212 .state = 4,
a39a5816
EY		 213 .dcfclk_mhz = 626.09,
214 .fabricclk_mhz = 1200.0,
215 .dispclk_mhz = 900.00,
216 .dppclk_mhz = 847.06,
217 .phyclk_mhz = 810.0,
218 .socclk_mhz = 953.0,
219 .dscclk_mhz = 489.0,
220 .dram_speed_mts = 2400.0,
221 },
222 {
223 .state = 5,
224 .dcfclk_mhz = 685.71,
225 .fabricclk_mhz = 1333.0,
226 .dispclk_mhz = 1028.57,
227 .dppclk_mhz = 960.00,
228 .phyclk_mhz = 810.0,
229 .socclk_mhz = 278.0,
230 .dscclk_mhz = 287.67,
231 .dram_speed_mts = 2666.0,
232 },
233 {
234 .state = 6,
235 .dcfclk_mhz = 757.89,
236 .fabricclk_mhz = 1467.0,
237 .dispclk_mhz = 1107.69,
238 .dppclk_mhz = 1028.57,
239 .phyclk_mhz = 810.0,
240 .socclk_mhz = 715.0,
241 .dscclk_mhz = 318.334,
242 .dram_speed_mts = 3200.0,
243 },
244 {
245 .state = 7,
246 .dcfclk_mhz = 847.06,
6f4e6361 247 .fabricclk_mhz = 1600.0,
652651ff 248 .dispclk_mhz = 1395.0,
a39a5816 249 .dppclk_mhz = 1285.00,
652651ff 250 .phyclk_mhz = 1325.0,
6f4e6361 251 .socclk_mhz = 953.0,
652651ff 252 .dscclk_mhz = 489.0,
6f4e6361
BL		 253 .dram_speed_mts = 4266.0,
254 },
255 /*Extra state, no dispclk ramping*/
256 {
a39a5816
EY		 257 .state = 8,
258 .dcfclk_mhz = 847.06,
6f4e6361 259 .fabricclk_mhz = 1600.0,
652651ff
BL		 260 .dispclk_mhz = 1395.0,
261 .dppclk_mhz = 1285.0,
262 .phyclk_mhz = 1325.0,
6f4e6361 263 .socclk_mhz = 953.0,
652651ff 264 .dscclk_mhz = 489.0,
6f4e6361
BL		 265 .dram_speed_mts = 4266.0,
266 },
267
268 },
269
652651ff
BL		 270 .sr_exit_time_us = 12.5,
271 .sr_enter_plus_exit_time_us = 17.0,
6f4e6361
BL		 272 .urgent_latency_us = 4.0,
273 .urgent_latency_pixel_data_only_us = 4.0,
274 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
275 .urgent_latency_vm_data_only_us = 4.0,
276 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
277 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
278 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
279 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
280 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
281 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
282 .max_avg_sdp_bw_use_normal_percent = 60.0,
283 .max_avg_dram_bw_use_normal_percent = 100.0,
284 .writeback_latency_us = 12.0,
285 .max_request_size_bytes = 256,
286 .dram_channel_width_bytes = 4,
287 .fabric_datapath_to_dcn_data_return_bytes = 32,
288 .dcn_downspread_percent = 0.5,
77ef333e 289 .downspread_percent = 0.38,
6f4e6361
BL		 290 .dram_page_open_time_ns = 50.0,
291 .dram_rw_turnaround_time_ns = 17.5,
292 .dram_return_buffer_per_channel_bytes = 8192,
293 .round_trip_ping_latency_dcfclk_cycles = 128,
294 .urgent_out_of_order_return_per_channel_bytes = 4096,
295 .channel_interleave_bytes = 256,
296 .num_banks = 8,
297 .num_chans = 4,
298 .vmm_page_size_bytes = 4096,
b0075d11 299 .dram_clock_change_latency_us = 23.84,
6f4e6361 300 .return_bus_width_bytes = 64,
0beb5403 301 .dispclk_dppclk_vco_speed_mhz = 3600,
6f4e6361
BL		 302 .xfc_bus_transport_time_us = 4,
303 .xfc_xbuf_latency_tolerance_us = 4,
304 .use_urgent_burst_bw = 1,
103cd0b1 305 .num_states = 8
6f4e6361
BL		 306};
307
308#ifndef MAX
309#define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
310#endif
311#ifndef MIN
312#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
313#endif
314
315/* begin *********************
316 * macros to expend register list macro defined in HW object header file */
317
318/* DCN */
319/* TODO awful hack. fixup dcn20_dwb.h */
320#undef BASE_INNER
321#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
322
323#define BASE(seg) BASE_INNER(seg)
324
325#define SR(reg_name)\
326 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
327 mm ## reg_name
328
329#define SRI(reg_name, block, id)\
330 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
331 mm ## block ## id ## _ ## reg_name
332
333#define SRIR(var_name, reg_name, block, id)\
334 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
335 mm ## block ## id ## _ ## reg_name
336
337#define SRII(reg_name, block, id)\
338 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
339 mm ## block ## id ## _ ## reg_name
340
341#define DCCG_SRII(reg_name, block, id)\
342 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
343 mm ## block ## id ## _ ## reg_name
344
1e461c37
AC		 345#define VUPDATE_SRII(reg_name, block, id)\
346 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
347 mm ## reg_name ## _ ## block ## id
348
6f4e6361
BL		 349/* NBIO */
350#define NBIO_BASE_INNER(seg) \
351 NBIF0_BASE__INST0_SEG ## seg
352
353#define NBIO_BASE(seg) \
354 NBIO_BASE_INNER(seg)
355
356#define NBIO_SR(reg_name)\
357 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
358 mm ## reg_name
359
360/* MMHUB */
361#define MMHUB_BASE_INNER(seg) \
362 MMHUB_BASE__INST0_SEG ## seg
363
364#define MMHUB_BASE(seg) \
365 MMHUB_BASE_INNER(seg)
366
367#define MMHUB_SR(reg_name)\
368 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
369 mmMM ## reg_name
370
371#define clk_src_regs(index, pllid)\
372[index] = {\
373 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
374}
375
376static const struct dce110_clk_src_regs clk_src_regs[] = {
377 clk_src_regs(0, A),
378 clk_src_regs(1, B),
379 clk_src_regs(2, C),
380 clk_src_regs(3, D),
381 clk_src_regs(4, E),
382};
383
384static const struct dce110_clk_src_shift cs_shift = {
385 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
386};
387
388static const struct dce110_clk_src_mask cs_mask = {
389 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
390};
391
392static const struct bios_registers bios_regs = {
393 NBIO_SR(BIOS_SCRATCH_3),
394 NBIO_SR(BIOS_SCRATCH_6)
395};
396
c0fb59a4 397static const struct dce_dmcu_registers dmcu_regs = {
a7e3658e 398 DMCU_DCN20_REG_LIST()
c0fb59a4
BL		 399};
400
401static const struct dce_dmcu_shift dmcu_shift = {
402 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
403};
404
405static const struct dce_dmcu_mask dmcu_mask = {
406 DMCU_MASK_SH_LIST_DCN10(_MASK)
407};
408
409static const struct dce_abm_registers abm_regs = {
410 ABM_DCN20_REG_LIST()
411};
412
413static const struct dce_abm_shift abm_shift = {
414 ABM_MASK_SH_LIST_DCN20(__SHIFT)
415};
416
417static const struct dce_abm_mask abm_mask = {
418 ABM_MASK_SH_LIST_DCN20(_MASK)
419};
420
6f4e6361
BL		 421#define audio_regs(id)\
422[id] = {\
423 AUD_COMMON_REG_LIST(id)\
424}
425
426static const struct dce_audio_registers audio_regs[] = {
427 audio_regs(0),
428 audio_regs(1),
429 audio_regs(2),
430 audio_regs(3),
431 audio_regs(4),
432 audio_regs(5),
433};
434
435#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
436 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
437 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
438 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
439
440static const struct dce_audio_shift audio_shift = {
441 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
442};
443
444static const struct dce_audio_mask audio_mask = {
445 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
446};
447
448static const struct dccg_registers dccg_regs = {
449 DCCG_COMMON_REG_LIST_DCN_BASE()
450};
451
452static const struct dccg_shift dccg_shift = {
453 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
454};
455
456static const struct dccg_mask dccg_mask = {
457 DCCG_MASK_SH_LIST_DCN2(_MASK)
458};
459
460#define opp_regs(id)\
461[id] = {\
462 OPP_REG_LIST_DCN20(id),\
463}
464
465static const struct dcn20_opp_registers opp_regs[] = {
466 opp_regs(0),
467 opp_regs(1),
468 opp_regs(2),
469 opp_regs(3),
470 opp_regs(4),
471 opp_regs(5),
472};
473
474static const struct dcn20_opp_shift opp_shift = {
475 OPP_MASK_SH_LIST_DCN20(__SHIFT)
476};
477
478static const struct dcn20_opp_mask opp_mask = {
479 OPP_MASK_SH_LIST_DCN20(_MASK)
480};
481
482#define tg_regs(id)\
483[id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
484
485static const struct dcn_optc_registers tg_regs[] = {
486 tg_regs(0),
487 tg_regs(1),
488 tg_regs(2),
489 tg_regs(3)
490};
491
492static const struct dcn_optc_shift tg_shift = {
493 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
494};
495
496static const struct dcn_optc_mask tg_mask = {
497 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
498};
499
500static const struct dcn20_mpc_registers mpc_regs = {
501 MPC_REG_LIST_DCN2_0(0),
502 MPC_REG_LIST_DCN2_0(1),
503 MPC_REG_LIST_DCN2_0(2),
504 MPC_REG_LIST_DCN2_0(3),
505 MPC_REG_LIST_DCN2_0(4),
506 MPC_REG_LIST_DCN2_0(5),
507 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
508 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
509 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
e8027e08
NA		 510 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
511 MPC_DBG_REG_LIST_DCN2_0()
6f4e6361
BL		 512};
513
514static const struct dcn20_mpc_shift mpc_shift = {
c1e34175
NA		 515 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
516 MPC_DEBUG_REG_LIST_SH_DCN20
6f4e6361
BL		 517};
518
519static const struct dcn20_mpc_mask mpc_mask = {
c1e34175
NA		 520 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
521 MPC_DEBUG_REG_LIST_MASK_DCN20
6f4e6361
BL		 522};
523
524#define hubp_regs(id)\
525[id] = {\
526 HUBP_REG_LIST_DCN21(id)\
527}
528
529static const struct dcn_hubp2_registers hubp_regs[] = {
530 hubp_regs(0),
531 hubp_regs(1),
532 hubp_regs(2),
533 hubp_regs(3)
534};
535
536static const struct dcn_hubp2_shift hubp_shift = {
537 HUBP_MASK_SH_LIST_DCN21(__SHIFT)
538};
539
540static const struct dcn_hubp2_mask hubp_mask = {
541 HUBP_MASK_SH_LIST_DCN21(_MASK)
542};
543
544static const struct dcn_hubbub_registers hubbub_reg = {
545 HUBBUB_REG_LIST_DCN21()
546};
547
548static const struct dcn_hubbub_shift hubbub_shift = {
549 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
550};
551
552static const struct dcn_hubbub_mask hubbub_mask = {
553 HUBBUB_MASK_SH_LIST_DCN21(_MASK)
554};
555
556
557#define vmid_regs(id)\
558[id] = {\
559 DCN20_VMID_REG_LIST(id)\
560}
561
562static const struct dcn_vmid_registers vmid_regs[] = {
563 vmid_regs(0),
564 vmid_regs(1),
565 vmid_regs(2),
566 vmid_regs(3),
567 vmid_regs(4),
568 vmid_regs(5),
569 vmid_regs(6),
570 vmid_regs(7),
571 vmid_regs(8),
572 vmid_regs(9),
573 vmid_regs(10),
574 vmid_regs(11),
575 vmid_regs(12),
576 vmid_regs(13),
577 vmid_regs(14),
578 vmid_regs(15)
579};
580
581static const struct dcn20_vmid_shift vmid_shifts = {
582 DCN20_VMID_MASK_SH_LIST(__SHIFT)
583};
584
585static const struct dcn20_vmid_mask vmid_masks = {
586 DCN20_VMID_MASK_SH_LIST(_MASK)
587};
588
6f4e6361
BL		 589#define dsc_regsDCN20(id)\
590[id] = {\
591 DSC_REG_LIST_DCN20(id)\
592}
593
594static const struct dcn20_dsc_registers dsc_regs[] = {
595 dsc_regsDCN20(0),
596 dsc_regsDCN20(1),
597 dsc_regsDCN20(2),
598 dsc_regsDCN20(3),
599 dsc_regsDCN20(4),
600 dsc_regsDCN20(5)
601};
602
603static const struct dcn20_dsc_shift dsc_shift = {
604 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
605};
606
607static const struct dcn20_dsc_mask dsc_mask = {
608 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
609};
6f4e6361
BL		 610
611#define ipp_regs(id)\
612[id] = {\
613 IPP_REG_LIST_DCN20(id),\
614}
615
616static const struct dcn10_ipp_registers ipp_regs[] = {
617 ipp_regs(0),
618 ipp_regs(1),
619 ipp_regs(2),
620 ipp_regs(3),
621};
622
623static const struct dcn10_ipp_shift ipp_shift = {
624 IPP_MASK_SH_LIST_DCN20(__SHIFT)
625};
626
627static const struct dcn10_ipp_mask ipp_mask = {
628 IPP_MASK_SH_LIST_DCN20(_MASK),
629};
630
631#define opp_regs(id)\
632[id] = {\
633 OPP_REG_LIST_DCN20(id),\
634}
635
636
637#define aux_engine_regs(id)\
638[id] = {\
639 AUX_COMMON_REG_LIST0(id), \
640 .AUXN_IMPCAL = 0, \
641 .AUXP_IMPCAL = 0, \
642 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
643}
644
645static const struct dce110_aux_registers aux_engine_regs[] = {
646 aux_engine_regs(0),
647 aux_engine_regs(1),
648 aux_engine_regs(2),
649 aux_engine_regs(3),
650 aux_engine_regs(4),
651};
652
653#define tf_regs(id)\
654[id] = {\
655 TF_REG_LIST_DCN20(id),\
d9eb70ae 656 TF_REG_LIST_DCN20_COMMON_APPEND(id),\
6f4e6361
BL		 657}
658
659static const struct dcn2_dpp_registers tf_regs[] = {
660 tf_regs(0),
661 tf_regs(1),
662 tf_regs(2),
663 tf_regs(3),
664};
665
666static const struct dcn2_dpp_shift tf_shift = {
d9eb70ae 667 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
c1e34175 668 TF_DEBUG_REG_LIST_SH_DCN20
6f4e6361
BL		 669};
670
671static const struct dcn2_dpp_mask tf_mask = {
d9eb70ae 672 TF_REG_LIST_SH_MASK_DCN20(_MASK),
c1e34175 673 TF_DEBUG_REG_LIST_MASK_DCN20
6f4e6361
BL		 674};
675
676#define stream_enc_regs(id)\
677[id] = {\
678 SE_DCN2_REG_LIST(id)\
679}
680
681static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
682 stream_enc_regs(0),
683 stream_enc_regs(1),
684 stream_enc_regs(2),
685 stream_enc_regs(3),
686 stream_enc_regs(4),
687};
688
8276dd87 689static const struct dce110_aux_registers_shift aux_shift = {
690 DCN_AUX_MASK_SH_LIST(__SHIFT)
691};
692
693static const struct dce110_aux_registers_mask aux_mask = {
694 DCN_AUX_MASK_SH_LIST(_MASK)
695};
696
6f4e6361
BL		 697static const struct dcn10_stream_encoder_shift se_shift = {
698 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
699};
700
701static const struct dcn10_stream_encoder_mask se_mask = {
702 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
703};
704
44e149bb
AD		 705static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
706
8c357309 707static int dcn21_populate_dml_pipes_from_context(
fa896813
IZ		 708 struct dc *dc,
709 struct dc_state *context,
710 display_e2e_pipe_params_st *pipes,
711 bool fast_validate);
8c357309 712
6f4e6361
BL		 713static struct input_pixel_processor *dcn21_ipp_create(
714 struct dc_context *ctx, uint32_t inst)
715{
716 struct dcn10_ipp *ipp =
717 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
718
719 if (!ipp) {
720 BREAK_TO_DEBUGGER();
721 return NULL;
722 }
723
724 dcn20_ipp_construct(ipp, ctx, inst,
725 &ipp_regs[inst], &ipp_shift, &ipp_mask);
726 return &ipp->base;
727}
728
729static struct dpp *dcn21_dpp_create(
730 struct dc_context *ctx,
731 uint32_t inst)
732{
733 struct dcn20_dpp *dpp =
734 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
735
736 if (!dpp)
737 return NULL;
738
739 if (dpp2_construct(dpp, ctx, inst,
740 &tf_regs[inst], &tf_shift, &tf_mask))
741 return &dpp->base;
742
743 BREAK_TO_DEBUGGER();
744 kfree(dpp);
745 return NULL;
746}
747
748static struct dce_aux *dcn21_aux_engine_create(
749 struct dc_context *ctx,
750 uint32_t inst)
751{
752 struct aux_engine_dce110 *aux_engine =
753 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
754
755 if (!aux_engine)
756 return NULL;
757
758 dce110_aux_engine_construct(aux_engine, ctx, inst,
759 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
8276dd87 760 &aux_engine_regs[inst],
761 &aux_mask,
f6040a43 762 &aux_shift,
763 ctx->dc->caps.extended_aux_timeout_support);
6f4e6361
BL		 764
765 return &aux_engine->base;
766}
767
768#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
769
770static const struct dce_i2c_registers i2c_hw_regs[] = {
771 i2c_inst_regs(1),
772 i2c_inst_regs(2),
773 i2c_inst_regs(3),
774 i2c_inst_regs(4),
775 i2c_inst_regs(5),
776};
777
778static const struct dce_i2c_shift i2c_shifts = {
779 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
780};
781
782static const struct dce_i2c_mask i2c_masks = {
783 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
784};
785
786struct dce_i2c_hw *dcn21_i2c_hw_create(
787 struct dc_context *ctx,
788 uint32_t inst)
789{
790 struct dce_i2c_hw *dce_i2c_hw =
791 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
792
793 if (!dce_i2c_hw)
794 return NULL;
795
796 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
797 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
798
799 return dce_i2c_hw;
800}
801
802static const struct resource_caps res_cap_rn = {
803 .num_timing_generator = 4,
804 .num_opp = 4,
805 .num_video_plane = 4,
b356843e 806 .num_audio = 4, // 4 audio endpoints. 4 audio streams
6f4e6361
BL		 807 .num_stream_encoder = 5,
808 .num_pll = 5, // maybe 3 because the last two used for USB-c
809 .num_dwb = 1,
810 .num_ddc = 5,
fdcf62fb 811 .num_vmid = 16,
6f4e6361 812 .num_dsc = 3,
6f4e6361
BL		 813};
814
815#ifdef DIAGS_BUILD
816static const struct resource_caps res_cap_rn_FPGA_4pipe = {
817 .num_timing_generator = 4,
818 .num_opp = 4,
819 .num_video_plane = 4,
820 .num_audio = 7,
821 .num_stream_encoder = 4,
822 .num_pll = 4,
823 .num_dwb = 1,
824 .num_ddc = 4,
825 .num_dsc = 0,
826};
827
828static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
829 .num_timing_generator = 2,
830 .num_opp = 2,
831 .num_video_plane = 2,
832 .num_audio = 7,
833 .num_stream_encoder = 2,
834 .num_pll = 4,
835 .num_dwb = 1,
836 .num_ddc = 4,
6f4e6361 837 .num_dsc = 2,
6f4e6361
BL		 838};
839#endif
840
841static const struct dc_plane_cap plane_cap = {
842 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
843 .blends_with_above = true,
844 .blends_with_below = true,
845 .per_pixel_alpha = true,
846
847 .pixel_format_support = {
848 .argb8888 = true,
849 .nv12 = true,
cbec6477
SW		 850 .fp16 = true,
851 .p010 = true
6f4e6361
BL		 852 },
853
854 .max_upscale_factor = {
855 .argb8888 = 16000,
856 .nv12 = 16000,
857 .fp16 = 16000
858 },
859
860 .max_downscale_factor = {
861 .argb8888 = 250,
862 .nv12 = 250,
863 .fp16 = 250
3b26ca2d
IK		 864 },
865 64,
866 64
6f4e6361
BL		 867};
868
869static const struct dc_debug_options debug_defaults_drv = {
f0a574c9 870 .disable_dmcu = false,
6f4e6361
BL		 871 .force_abm_enable = false,
872 .timing_trace = false,
873 .clock_trace = true,
874 .disable_pplib_clock_request = true,
cab5dec4 875 .min_disp_clk_khz = 100000,
6f4e6361 876 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
4d25a0d5 877 .force_single_disp_pipe_split = false,
6f4e6361
BL		 878 .disable_dcc = DCC_ENABLE,
879 .vsr_support = true,
880 .performance_trace = false,
947daab2 881 .max_downscale_src_width = 4096,
6f4e6361
BL		 882 .disable_pplib_wm_range = false,
883 .scl_reset_length10 = true,
884 .sanity_checks = true,
57133a28 885 .disable_48mhz_pwrdwn = false,
ee765924 886 .usbc_combo_phy_reset_wa = true
6f4e6361
BL		 887};
888
889static const struct dc_debug_options debug_defaults_diags = {
f0a574c9 890 .disable_dmcu = false,
6f4e6361
BL		 891 .force_abm_enable = false,
892 .timing_trace = true,
893 .clock_trace = true,
894 .disable_dpp_power_gate = true,
895 .disable_hubp_power_gate = true,
896 .disable_clock_gate = true,
897 .disable_pplib_clock_request = true,
898 .disable_pplib_wm_range = true,
899 .disable_stutter = true,
900 .disable_48mhz_pwrdwn = true,
091018a5
AC		 901 .disable_psr = true,
902 .enable_tri_buf = true
6f4e6361
BL		 903};
904
905enum dcn20_clk_src_array_id {
906 DCN20_CLK_SRC_PLL0,
907 DCN20_CLK_SRC_PLL1,
15add0c2 908 DCN20_CLK_SRC_PLL2,
fc13b701
SL		 909 DCN20_CLK_SRC_PLL3,
910 DCN20_CLK_SRC_PLL4,
6f4e6361
BL		 911 DCN20_CLK_SRC_TOTAL_DCN21
912};
913
d9e32672 914static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
6f4e6361
BL		 915{
916 unsigned int i;
917
918 for (i = 0; i < pool->base.stream_enc_count; i++) {
919 if (pool->base.stream_enc[i] != NULL) {
920 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
921 pool->base.stream_enc[i] = NULL;
922 }
923 }
924
6f4e6361
BL		 925 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
926 if (pool->base.dscs[i] != NULL)
927 dcn20_dsc_destroy(&pool->base.dscs[i]);
928 }
6f4e6361
BL		 929
930 if (pool->base.mpc != NULL) {
931 kfree(TO_DCN20_MPC(pool->base.mpc));
932 pool->base.mpc = NULL;
933 }
934 if (pool->base.hubbub != NULL) {
935 kfree(pool->base.hubbub);
936 pool->base.hubbub = NULL;
937 }
938 for (i = 0; i < pool->base.pipe_count; i++) {
939 if (pool->base.dpps[i] != NULL)
940 dcn20_dpp_destroy(&pool->base.dpps[i]);
941
942 if (pool->base.ipps[i] != NULL)
943 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
944
945 if (pool->base.hubps[i] != NULL) {
946 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
947 pool->base.hubps[i] = NULL;
948 }
949
950 if (pool->base.irqs != NULL) {
951 dal_irq_service_destroy(&pool->base.irqs);
952 }
953 }
954
955 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
956 if (pool->base.engines[i] != NULL)
957 dce110_engine_destroy(&pool->base.engines[i]);
958 if (pool->base.hw_i2cs[i] != NULL) {
959 kfree(pool->base.hw_i2cs[i]);
960 pool->base.hw_i2cs[i] = NULL;
961 }
962 if (pool->base.sw_i2cs[i] != NULL) {
963 kfree(pool->base.sw_i2cs[i]);
964 pool->base.sw_i2cs[i] = NULL;
965 }
966 }
967
968 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
969 if (pool->base.opps[i] != NULL)
970 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
971 }
972
973 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
974 if (pool->base.timing_generators[i] != NULL) {
975 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
976 pool->base.timing_generators[i] = NULL;
977 }
978 }
979
980 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
981 if (pool->base.dwbc[i] != NULL) {
982 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
983 pool->base.dwbc[i] = NULL;
984 }
985 if (pool->base.mcif_wb[i] != NULL) {
986 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
987 pool->base.mcif_wb[i] = NULL;
988 }
989 }
990
991 for (i = 0; i < pool->base.audio_count; i++) {
992 if (pool->base.audios[i])
993 dce_aud_destroy(&pool->base.audios[i]);
994 }
995
996 for (i = 0; i < pool->base.clk_src_count; i++) {
997 if (pool->base.clock_sources[i] != NULL) {
998 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
999 pool->base.clock_sources[i] = NULL;
1000 }
1001 }
1002
1003 if (pool->base.dp_clock_source != NULL) {
1004 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1005 pool->base.dp_clock_source = NULL;
1006 }
1007
16012806 1008 if (pool->base.abm != NULL) {
501b4026 1009 if (pool->base.abm->ctx->dc->config.disable_dmcu)
16012806
WW		 1010 dmub_abm_destroy(&pool->base.abm);
1011 else
1012 dce_abm_destroy(&pool->base.abm);
1013 }
6f4e6361
BL		 1014
1015 if (pool->base.dmcu != NULL)
1016 dce_dmcu_destroy(&pool->base.dmcu);
1017
9dac88d8
WW		 1018 if (pool->base.psr != NULL)
1019 dmub_psr_destroy(&pool->base.psr);
1020
6f4e6361
BL		 1021 if (pool->base.dccg != NULL)
1022 dcn_dccg_destroy(&pool->base.dccg);
1023
1024 if (pool->base.pp_smu != NULL)
44e149bb 1025 dcn21_pp_smu_destroy(&pool->base.pp_smu);
6f4e6361
BL		 1026}
1027
1028
1029static void calculate_wm_set_for_vlevel(
1030 int vlevel,
1031 struct wm_range_table_entry *table_entry,
1032 struct dcn_watermarks *wm_set,
1033 struct display_mode_lib *dml,
1034 display_e2e_pipe_params_st *pipes,
1035 int pipe_cnt)
1036{
1037 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
1038
1039 ASSERT(vlevel < dml->soc.num_states);
1040 /* only pipe 0 is read for voltage and dcf/soc clocks */
1041 pipes[0].clks_cfg.voltage = vlevel;
1042 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
1043 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
1044
1045 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
d3511fd0
EY		 1046 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
1047 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
6f4e6361
BL		 1048
1049 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
1050 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
1051 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
1052 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1053 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
6f4e6361
BL		 1054 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
1055 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
b617b265 1056 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
6f4e6361
BL		 1057 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
1058
1059}
1060
15fdbcc5
LH		 1061static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
1062{
d3511fd0
EY		 1063 int i;
1064
15fdbcc5 1065 if (dc->bb_overrides.sr_exit_time_ns) {
d3511fd0
EY		 1066 for (i = 0; i < WM_SET_COUNT; i++) {
1067 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
1068 dc->bb_overrides.sr_exit_time_ns / 1000.0;
1069 }
15fdbcc5
LH		 1070 }
1071
1072 if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
d3511fd0
EY		 1073 for (i = 0; i < WM_SET_COUNT; i++) {
1074 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
1075 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
1076 }
15fdbcc5
LH		 1077 }
1078
1079 if (dc->bb_overrides.urgent_latency_ns) {
1080 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
1081 }
1082
1083 if (dc->bb_overrides.dram_clock_change_latency_ns) {
580c8be2
JG		 1084 for (i = 0; i < WM_SET_COUNT; i++) {
1085 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
15fdbcc5 1086 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
580c8be2 1087 }
15fdbcc5 1088 }
15fdbcc5
LH		 1089}
1090
6f4e6361
BL		 1091void dcn21_calculate_wm(
1092 struct dc *dc, struct dc_state *context,
1093 display_e2e_pipe_params_st *pipes,
1094 int *out_pipe_cnt,
1095 int *pipe_split_from,
fa896813
IZ		 1096 int vlevel_req,
1097 bool fast_validate)
6f4e6361
BL		 1098{
1099 int pipe_cnt, i, pipe_idx;
1100 int vlevel, vlevel_max;
1101 struct wm_range_table_entry *table_entry;
1102 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
1103
1104 ASSERT(bw_params);
1105
15fdbcc5
LH		 1106 patch_bounding_box(dc, &context->bw_ctx.dml.soc);
1107
6f4e6361
BL		 1108 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1109 if (!context->res_ctx.pipe_ctx[i].stream)
1110 continue;
1111
1112 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1113 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
1114
1115 if (pipe_split_from[i] < 0) {
1116 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1117 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1118 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1119 pipes[pipe_cnt].pipe.dest.odm_combine =
1120 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
1121 else
1122 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1123 pipe_idx++;
1124 } else {
1125 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1126 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1127 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1128 pipes[pipe_cnt].pipe.dest.odm_combine =
1129 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];
1130 else
1131 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1132 }
1133 pipe_cnt++;
1134 }
1135
1136 if (pipe_cnt != pipe_idx) {
1137 if (dc->res_pool->funcs->populate_dml_pipes)
1138 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
fa896813 1139 context, pipes, fast_validate);
6f4e6361 1140 else
8c357309 1141 pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
fa896813 1142 context, pipes, fast_validate);
6f4e6361
BL		 1143 }
1144
1145 *out_pipe_cnt = pipe_cnt;
1146
1147 vlevel_max = bw_params->clk_table.num_entries - 1;
1148
1149
1150 /* WM Set D */
1151 table_entry = &bw_params->wm_table.entries[WM_D];
1152 if (table_entry->wm_type == WM_TYPE_RETRAINING)
1153 vlevel = 0;
1154 else
1155 vlevel = vlevel_max;
1156 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
1157 &context->bw_ctx.dml, pipes, pipe_cnt);
1158 /* WM Set C */
1159 table_entry = &bw_params->wm_table.entries[WM_C];
f2459c52 1160 vlevel = MIN(MAX(vlevel_req, 3), vlevel_max);
6f4e6361
BL		 1161 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
1162 &context->bw_ctx.dml, pipes, pipe_cnt);
1163 /* WM Set B */
1164 table_entry = &bw_params->wm_table.entries[WM_B];
f2459c52 1165 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
6f4e6361
BL		 1166 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
1167 &context->bw_ctx.dml, pipes, pipe_cnt);
1168
1169 /* WM Set A */
1170 table_entry = &bw_params->wm_table.entries[WM_A];
1171 vlevel = MIN(vlevel_req, vlevel_max);
1172 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
1173 &context->bw_ctx.dml, pipes, pipe_cnt);
1174}
1175
1176
ea817dd5
DL		 1177static bool dcn21_fast_validate_bw(
1178 struct dc *dc,
1179 struct dc_state *context,
1180 display_e2e_pipe_params_st *pipes,
1181 int *pipe_cnt_out,
1182 int *pipe_split_from,
fa896813
IZ		 1183 int *vlevel_out,
1184 bool fast_validate)
ea817dd5
DL		 1185{
1186 bool out = false;
1187 int split[MAX_PIPES] = { 0 };
1188 int pipe_cnt, i, pipe_idx, vlevel;
1189
1190 ASSERT(pipes);
1191 if (!pipes)
1192 return false;
1193
1194 dcn20_merge_pipes_for_validate(dc, context);
1195
fa896813 1196 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
ea817dd5
DL		 1197
1198 *pipe_cnt_out = pipe_cnt;
1199
1200 if (!pipe_cnt) {
1201 out = true;
1202 goto validate_out;
1203 }
103cd0b1
IZ		 1204 /*
1205 * DML favors voltage over p-state, but we're more interested in
1206 * supporting p-state over voltage. We can't support p-state in
1207 * prefetch mode > 0 so try capping the prefetch mode to start.
1208 */
1209 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1210 dm_allow_self_refresh_and_mclk_switch;
ea817dd5
DL		 1211 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1212
103cd0b1
IZ		 1213 if (vlevel > context->bw_ctx.dml.soc.num_states) {
1214 /*
1215 * If mode is unsupported or there's still no p-state support then
1216 * fall back to favoring voltage.
1217 *
1218 * We don't actually support prefetch mode 2, so require that we
1219 * at least support prefetch mode 1.
1220 */
1221 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1222 dm_allow_self_refresh;
1223 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1224 if (vlevel > context->bw_ctx.dml.soc.num_states)
1225 goto validate_fail;
1226 }
ea817dd5
DL		 1227
1228 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);
1229
2e7b43e6
DL		 1230 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1231 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1232 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
1233 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1234
1235 if (!pipe->stream)
1236 continue;
1237
1238 /* We only support full screen mpo with ODM */
1239 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
1240 && pipe->plane_state && mpo_pipe
1241 && memcmp(&mpo_pipe->plane_res.scl_data.recout,
1242 &pipe->plane_res.scl_data.recout,
1243 sizeof(struct rect)) != 0) {
1244 ASSERT(mpo_pipe->plane_state != pipe->plane_state);
1245 goto validate_fail;
1246 }
1247 pipe_idx++;
1248 }
1249
ea817dd5
DL		 1250 /*initialize pipe_just_split_from to invalid idx*/
1251 for (i = 0; i < MAX_PIPES; i++)
1252 pipe_split_from[i] = -1;
1253
1254 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
1255 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1256 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
1257
1258 if (!pipe->stream || pipe_split_from[i] >= 0)
1259 continue;
1260
1261 pipe_idx++;
1262
1263 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
1264 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
1265 ASSERT(hsplit_pipe);
1266 if (!dcn20_split_stream_for_odm(
1267 dc, &context->res_ctx,
1268 pipe, hsplit_pipe))
1269 goto validate_fail;
1270 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
1271 dcn20_build_mapped_resource(dc, context, pipe->stream);
1272 }
1273
1274 if (!pipe->plane_state)
1275 continue;
1276 /* Skip 2nd half of already split pipe */
1277 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
1278 continue;
1279
ea817dd5
DL		 1280 if (split[i] == 2) {
1281 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
1282 /* pipe not split previously needs split */
1283 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
1284 ASSERT(hsplit_pipe);
1285 if (!hsplit_pipe) {
1286 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2;
1287 continue;
1288 }
1289 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
1290 if (!dcn20_split_stream_for_odm(
1291 dc, &context->res_ctx,
1292 pipe, hsplit_pipe))
1293 goto validate_fail;
1294 dcn20_build_mapped_resource(dc, context, pipe->stream);
1295 } else {
1296 dcn20_split_stream_for_mpc(
1297 &context->res_ctx, dc->res_pool,
1298 pipe, hsplit_pipe);
1299 resource_build_scaling_params(pipe);
1300 resource_build_scaling_params(hsplit_pipe);
1301 }
1302 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
1303 }
1304 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
1305 /* merge should already have been done */
1306 ASSERT(0);
1307 }
1308 }
1309 /* Actual dsc count per stream dsc validation*/
1310 if (!dcn20_validate_dsc(dc, context)) {
1311 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
1312 DML_FAIL_DSC_VALIDATION_FAILURE;
1313 goto validate_fail;
1314 }
1315
1316 *vlevel_out = vlevel;
1317
1318 out = true;
1319 goto validate_out;
1320
1321validate_fail:
1322 out = false;
1323
1324validate_out:
1325 return out;
1326}
1327
41401ac6
JK		 1328static noinline bool dcn21_validate_bandwidth_fp(struct dc *dc,
1329 struct dc_state *context, bool fast_validate)
6f4e6361
BL		 1330{
1331 bool out = false;
1332
1333 BW_VAL_TRACE_SETUP();
1334
1335 int vlevel = 0;
1336 int pipe_split_from[MAX_PIPES];
1337 int pipe_cnt = 0;
680174cf 1338 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
6f4e6361
BL		 1339 DC_LOGGER_INIT(dc->ctx->logger);
1340
1341 BW_VAL_TRACE_COUNT();
1342
ce271b40
QZ		 1343 /*Unsafe due to current pipe merge and split logic*/
1344 ASSERT(context != dc->current_state);
1345
fa896813 1346 out = dcn21_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
6f4e6361
BL		 1347
1348 if (pipe_cnt == 0)
1349 goto validate_out;
1350
1351 if (!out)
1352 goto validate_fail;
1353
1354 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1355
1356 if (fast_validate) {
1357 BW_VAL_TRACE_SKIP(fast);
1358 goto validate_out;
1359 }
1360
fa896813 1361 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
6f4e6361
BL		 1362 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1363
1364 BW_VAL_TRACE_END_WATERMARKS();
1365
1366 goto validate_out;
1367
1368validate_fail:
1369 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1370 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1371
1372 BW_VAL_TRACE_SKIP(fail);
1373 out = false;
1374
1375validate_out:
1376 kfree(pipes);
1377
1378 BW_VAL_TRACE_FINISH();
1379
1380 return out;
1381}
41401ac6
JK		 1382
1383/*
1384 * Some of the functions further below use the FPU, so we need to wrap this
1385 * with DC_FP_START()/DC_FP_END(). Use the same approach as for
1386 * dcn20_validate_bandwidth in dcn20_resource.c.
1387 */
1388bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
1389 bool fast_validate)
1390{
1391 bool voltage_supported;
1392 DC_FP_START();
1393 voltage_supported = dcn21_validate_bandwidth_fp(dc, context, fast_validate);
1394 DC_FP_END();
1395 return voltage_supported;
1396}
1397
6f4e6361
BL		 1398static void dcn21_destroy_resource_pool(struct resource_pool **pool)
1399{
1400 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
1401
d9e32672 1402 dcn21_resource_destruct(dcn21_pool);
6f4e6361
BL		 1403 kfree(dcn21_pool);
1404 *pool = NULL;
1405}
1406
1407static struct clock_source *dcn21_clock_source_create(
1408 struct dc_context *ctx,
1409 struct dc_bios *bios,
1410 enum clock_source_id id,
1411 const struct dce110_clk_src_regs *regs,
1412 bool dp_clk_src)
1413{
1414 struct dce110_clk_src *clk_src =
1415 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1416
1417 if (!clk_src)
1418 return NULL;
1419
1420 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1421 regs, &cs_shift, &cs_mask)) {
1422 clk_src->base.dp_clk_src = dp_clk_src;
1423 return &clk_src->base;
1424 }
1425
1426 BREAK_TO_DEBUGGER();
1427 return NULL;
1428}
1429
1430static struct hubp *dcn21_hubp_create(
1431 struct dc_context *ctx,
1432 uint32_t inst)
1433{
1434 struct dcn21_hubp *hubp21 =
1435 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);
1436
1437 if (!hubp21)
1438 return NULL;
1439
1440 if (hubp21_construct(hubp21, ctx, inst,
1441 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1442 return &hubp21->base;
1443
1444 BREAK_TO_DEBUGGER();
1445 kfree(hubp21);
1446 return NULL;
1447}
1448
1449static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
1450{
1451 int i;
1452
1453 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1454 GFP_KERNEL);
1455
1456 if (!hubbub)
1457 return NULL;
1458
1459 hubbub21_construct(hubbub, ctx,
1460 &hubbub_reg,
1461 &hubbub_shift,
1462 &hubbub_mask);
1463
1464 for (i = 0; i < res_cap_rn.num_vmid; i++) {
1465 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1466
1467 vmid->ctx = ctx;
1468
1469 vmid->regs = &vmid_regs[i];
1470 vmid->shifts = &vmid_shifts;
1471 vmid->masks = &vmid_masks;
1472 }
fdcf62fb 1473 hubbub->num_vmid = res_cap_rn.num_vmid;
6f4e6361
BL		 1474
1475 return &hubbub->base;
1476}
1477
1478struct output_pixel_processor *dcn21_opp_create(
1479 struct dc_context *ctx, uint32_t inst)
1480{
1481 struct dcn20_opp *opp =
1482 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1483
1484 if (!opp) {
1485 BREAK_TO_DEBUGGER();
1486 return NULL;
1487 }
1488
1489 dcn20_opp_construct(opp, ctx, inst,
1490 &opp_regs[inst], &opp_shift, &opp_mask);
1491 return &opp->base;
1492}
1493
1494struct timing_generator *dcn21_timing_generator_create(
1495 struct dc_context *ctx,
1496 uint32_t instance)
1497{
1498 struct optc *tgn10 =
1499 kzalloc(sizeof(struct optc), GFP_KERNEL);
1500
1501 if (!tgn10)
1502 return NULL;
1503
1504 tgn10->base.inst = instance;
1505 tgn10->base.ctx = ctx;
1506
1507 tgn10->tg_regs = &tg_regs[instance];
1508 tgn10->tg_shift = &tg_shift;
1509 tgn10->tg_mask = &tg_mask;
1510
1511 dcn20_timing_generator_init(tgn10);
1512
1513 return &tgn10->base;
1514}
1515
1516struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1517{
1518 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1519 GFP_KERNEL);
1520
1521 if (!mpc20)
1522 return NULL;
1523
1524 dcn20_mpc_construct(mpc20, ctx,
1525 &mpc_regs,
1526 &mpc_shift,
1527 &mpc_mask,
1528 6);
1529
1530 return &mpc20->base;
1531}
1532
1533static void read_dce_straps(
1534 struct dc_context *ctx,
1535 struct resource_straps *straps)
1536{
1537 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1538 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1539
1540}
1541
6f4e6361
BL		 1542
1543struct display_stream_compressor *dcn21_dsc_create(
1544 struct dc_context *ctx, uint32_t inst)
1545{
1546 struct dcn20_dsc *dsc =
1547 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1548
1549 if (!dsc) {
1550 BREAK_TO_DEBUGGER();
1551 return NULL;
1552 }
1553
1554 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1555 return &dsc->base;
1556}
6f4e6361 1557
f2459c52
SL		 1558static struct _vcs_dpi_voltage_scaling_st construct_low_pstate_lvl(struct clk_limit_table *clk_table, unsigned int high_voltage_lvl)
1559{
1560 struct _vcs_dpi_voltage_scaling_st low_pstate_lvl;
1561 int i;
1562
1563 low_pstate_lvl.state = 1;
1564 low_pstate_lvl.dcfclk_mhz = clk_table->entries[0].dcfclk_mhz;
1565 low_pstate_lvl.fabricclk_mhz = clk_table->entries[0].fclk_mhz;
1566 low_pstate_lvl.socclk_mhz = clk_table->entries[0].socclk_mhz;
1567 low_pstate_lvl.dram_speed_mts = clk_table->entries[0].memclk_mhz * 2;
1568
1569 low_pstate_lvl.dispclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dispclk_mhz;
1570 low_pstate_lvl.dppclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dppclk_mhz;
1571 low_pstate_lvl.dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[high_voltage_lvl].dram_bw_per_chan_gbps;
1572 low_pstate_lvl.dscclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dscclk_mhz;
1573 low_pstate_lvl.dtbclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dtbclk_mhz;
1574 low_pstate_lvl.phyclk_d18_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_d18_mhz;
1575 low_pstate_lvl.phyclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_mhz;
1576
1577 for (i = clk_table->num_entries; i > 1; i--)
1578 clk_table->entries[i] = clk_table->entries[i-1];
1579 clk_table->entries[1] = clk_table->entries[0];
1580 clk_table->num_entries++;
1581
1582 return low_pstate_lvl;
1583}
1584
6f4e6361
BL		 1585static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1586{
1587 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
1588 struct clk_limit_table *clk_table = &bw_params->clk_table;
23838777 1589 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
f2459c52 1590 unsigned int i, closest_clk_lvl = 0, k = 0;
6de1601e 1591 int j;
a39a5816 1592
b98ab70e
SL		 1593 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1594 dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
1595 dcn2_1_soc.num_chans = bw_params->num_channels;
1596
1597 ASSERT(clk_table->num_entries);
1598 for (i = 0; i < clk_table->num_entries; i++) {
1599 /* loop backwards*/
1600 for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) {
1601 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
1602 closest_clk_lvl = j;
1603 break;
a39a5816 1604 }
a39a5816 1605 }
b98ab70e 1606
f2459c52
SL		 1607 /* clk_table[1] is reserved for min DF PState. skip here to fill in later. */
1608 if (i == 1)
1609 k++;
1610
1611 clock_limits[k].state = k;
1612 clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
1613 clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
1614 clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
1615 clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
1616
1617 clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
1618 clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
1619 clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
1620 clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
1621 clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
1622 clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
1623 clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
1624
1625 k++;
b98ab70e 1626 }
f2459c52 1627 for (i = 0; i < clk_table->num_entries + 1; i++)
b98ab70e
SL		 1628 dcn2_1_soc.clock_limits[i] = clock_limits[i];
1629 if (clk_table->num_entries) {
f2459c52 1630 dcn2_1_soc.num_states = clk_table->num_entries + 1;
b98ab70e
SL		 1631 /* duplicate last level */
1632 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
1633 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;
f2459c52
SL		 1634 /* fill in min DF PState */
1635 dcn2_1_soc.clock_limits[1] = construct_low_pstate_lvl(clk_table, closest_clk_lvl);
6f4e6361 1636 }
08f6c859 1637
a39a5816 1638 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
6f4e6361
BL		 1639}
1640
976035dd 1641static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
6f4e6361
BL		 1642{
1643 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
1644
a51894f0
EY		 1645 if (!pp_smu)
1646 return pp_smu;
6f4e6361 1647
b98ab70e 1648 dm_pp_get_funcs(ctx, pp_smu);
a51894f0 1649
b98ab70e
SL		 1650 if (pp_smu->ctx.ver != PP_SMU_VER_RN)
1651 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
a51894f0 1652
6f4e6361
BL		 1653
1654 return pp_smu;
1655}
1656
976035dd 1657static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
6f4e6361
BL		 1658{
1659 if (pp_smu && *pp_smu) {
1660 kfree(*pp_smu);
1661 *pp_smu = NULL;
1662 }
1663}
1664
1665static struct audio *dcn21_create_audio(
1666 struct dc_context *ctx, unsigned int inst)
1667{
1668 return dce_audio_create(ctx, inst,
1669 &audio_regs[inst], &audio_shift, &audio_mask);
1670}
1671
1672static struct dc_cap_funcs cap_funcs = {
1673 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1674};
1675
1676struct stream_encoder *dcn21_stream_encoder_create(
1677 enum engine_id eng_id,
1678 struct dc_context *ctx)
1679{
1680 struct dcn10_stream_encoder *enc1 =
1681 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1682
1683 if (!enc1)
1684 return NULL;
1685
1686 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1687 &stream_enc_regs[eng_id],
1688 &se_shift, &se_mask);
1689
1690 return &enc1->base;
1691}
1692
1693static const struct dce_hwseq_registers hwseq_reg = {
1694 HWSEQ_DCN21_REG_LIST()
1695};
1696
1697static const struct dce_hwseq_shift hwseq_shift = {
1698 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
1699};
1700
1701static const struct dce_hwseq_mask hwseq_mask = {
1702 HWSEQ_DCN21_MASK_SH_LIST(_MASK)
1703};
1704
1705static struct dce_hwseq *dcn21_hwseq_create(
1706 struct dc_context *ctx)
1707{
1708 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1709
1710 if (hws) {
1711 hws->ctx = ctx;
1712 hws->regs = &hwseq_reg;
1713 hws->shifts = &hwseq_shift;
1714 hws->masks = &hwseq_mask;
f93e29f0 1715 hws->wa.DEGVIDCN21 = true;
d9758768 1716 hws->wa.disallow_self_refresh_during_multi_plane_transition = true;
6f4e6361
BL		 1717 }
1718 return hws;
1719}
1720
1721static const struct resource_create_funcs res_create_funcs = {
1722 .read_dce_straps = read_dce_straps,
1723 .create_audio = dcn21_create_audio,
1724 .create_stream_encoder = dcn21_stream_encoder_create,
1725 .create_hwseq = dcn21_hwseq_create,
1726};
1727
1728static const struct resource_create_funcs res_create_maximus_funcs = {
1729 .read_dce_straps = NULL,
1730 .create_audio = NULL,
1731 .create_stream_encoder = NULL,
1732 .create_hwseq = dcn21_hwseq_create,
1733};
1734
91c665bd
BL		 1735static const struct encoder_feature_support link_enc_feature = {
1736 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1737 .max_hdmi_pixel_clock = 600000,
1738 .hdmi_ycbcr420_supported = true,
1739 .dp_ycbcr420_supported = true,
c14b726e 1740 .fec_supported = true,
91c665bd
BL		 1741 .flags.bits.IS_HBR2_CAPABLE = true,
1742 .flags.bits.IS_HBR3_CAPABLE = true,
1743 .flags.bits.IS_TPS3_CAPABLE = true,
1744 .flags.bits.IS_TPS4_CAPABLE = true
1745};
1746
1747
1748#define link_regs(id, phyid)\
1749[id] = {\
a771ded8 1750 LE_DCN2_REG_LIST(id), \
91c665bd 1751 UNIPHY_DCN2_REG_LIST(phyid), \
a771ded8 1752 DPCS_DCN21_REG_LIST(id), \
91c665bd
BL		 1753 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
1754}
1755
1756static const struct dcn10_link_enc_registers link_enc_regs[] = {
1757 link_regs(0, A),
1758 link_regs(1, B),
1759 link_regs(2, C),
1760 link_regs(3, D),
1761 link_regs(4, E),
1762};
1763
d4caa72e
AK		 1764static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
1765 { DCN_PANEL_CNTL_REG_LIST() }
904fb6e0
AK		 1766};
1767
d4caa72e
AK		 1768static const struct dce_panel_cntl_shift panel_cntl_shift = {
1769 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
904fb6e0
AK		 1770};
1771
d4caa72e
AK		 1772static const struct dce_panel_cntl_mask panel_cntl_mask = {
1773 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
904fb6e0
AK		 1774};
1775
91c665bd
BL		 1776#define aux_regs(id)\
1777[id] = {\
1778 DCN2_AUX_REG_LIST(id)\
1779}
1780
1781static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1782 aux_regs(0),
1783 aux_regs(1),
1784 aux_regs(2),
1785 aux_regs(3),
1786 aux_regs(4)
1787};
1788
1789#define hpd_regs(id)\
1790[id] = {\
1791 HPD_REG_LIST(id)\
1792}
1793
1794static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1795 hpd_regs(0),
1796 hpd_regs(1),
1797 hpd_regs(2),
1798 hpd_regs(3),
1799 hpd_regs(4)
1800};
1801
1802static const struct dcn10_link_enc_shift le_shift = {
a771ded8
RL		 1803 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
1804 DPCS_DCN21_MASK_SH_LIST(__SHIFT)
91c665bd
BL		 1805};
1806
1807static const struct dcn10_link_enc_mask le_mask = {
a771ded8
RL		 1808 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
1809 DPCS_DCN21_MASK_SH_LIST(_MASK)
91c665bd
BL		 1810};
1811
bf7f5ac3
YMM		 1812static int map_transmitter_id_to_phy_instance(
1813 enum transmitter transmitter)
1814{
1815 switch (transmitter) {
1816 case TRANSMITTER_UNIPHY_A:
1817 return 0;
1818 break;
1819 case TRANSMITTER_UNIPHY_B:
1820 return 1;
1821 break;
1822 case TRANSMITTER_UNIPHY_C:
1823 return 2;
1824 break;
1825 case TRANSMITTER_UNIPHY_D:
1826 return 3;
1827 break;
1828 case TRANSMITTER_UNIPHY_E:
1829 return 4;
1830 break;
1831 default:
1832 ASSERT(0);
1833 return 0;
1834 }
1835}
1836
91c665bd
BL		 1837static struct link_encoder *dcn21_link_encoder_create(
1838 const struct encoder_init_data *enc_init_data)
1839{
1840 struct dcn21_link_encoder *enc21 =
1841 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
bf7f5ac3 1842 int link_regs_id;
91c665bd
BL		 1843
1844 if (!enc21)
1845 return NULL;
1846
bf7f5ac3
YMM		 1847 link_regs_id =
1848 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1849
91c665bd
BL		 1850 dcn21_link_encoder_construct(enc21,
1851 enc_init_data,
1852 &link_enc_feature,
bf7f5ac3 1853 &link_enc_regs[link_regs_id],
91c665bd
BL		 1854 &link_enc_aux_regs[enc_init_data->channel - 1],
1855 &link_enc_hpd_regs[enc_init_data->hpd_source],
1856 &le_shift,
1857 &le_mask);
1858
1859 return &enc21->enc10.base;
1860}
904fb6e0 1861
d4caa72e 1862static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_data *init_data)
904fb6e0 1863{
d4caa72e
AK		 1864 struct dce_panel_cntl *panel_cntl =
1865 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
904fb6e0 1866
d4caa72e 1867 if (!panel_cntl)
904fb6e0
AK		 1868 return NULL;
1869
d4caa72e 1870 dce_panel_cntl_construct(panel_cntl,
904fb6e0 1871 init_data,
d4caa72e
AK		 1872 &panel_cntl_regs[init_data->inst],
1873 &panel_cntl_shift,
1874 &panel_cntl_mask);
904fb6e0 1875
d4caa72e 1876 return &panel_cntl->base;
904fb6e0
AK		 1877}
1878
c0fb59a4
BL		 1879#define CTX ctx
1880
1881#define REG(reg_name) \
1882 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1883
1884static uint32_t read_pipe_fuses(struct dc_context *ctx)
1885{
1886 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1887 /* RV1 support max 4 pipes */
1888 value = value & 0xf;
1889 return value;
1890}
1891
8c357309 1892static int dcn21_populate_dml_pipes_from_context(
fa896813
IZ		 1893 struct dc *dc,
1894 struct dc_state *context,
1895 display_e2e_pipe_params_st *pipes,
1896 bool fast_validate)
8c357309 1897{
fa896813 1898 uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
8c357309
YS		 1899 int i;
1900
2a28fe92 1901 for (i = 0; i < pipe_cnt; i++) {
8c357309 1902
82df77ae 1903 pipes[i].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
8c357309
YS		 1904 pipes[i].pipe.src.gpuvm = 1;
1905 }
1906
1907 return pipe_cnt;
1908}
1909
8d8c82b6
JG		 1910enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1911{
1912 enum dc_status result = DC_OK;
1913
1914 if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {
1915 plane_state->dcc.enable = 1;
1916 /* align to our worst case block width */
1917 plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024;
1918 }
1919 result = dcn20_patch_unknown_plane_state(plane_state);
1920 return result;
1921}
1922
ea22cc33 1923static const struct resource_funcs dcn21_res_pool_funcs = {
6f4e6361 1924 .destroy = dcn21_destroy_resource_pool,
91c665bd 1925 .link_enc_create = dcn21_link_encoder_create,
d4caa72e 1926 .panel_cntl_create = dcn21_panel_cntl_create,
6f4e6361 1927 .validate_bandwidth = dcn21_validate_bandwidth,
8c357309 1928 .populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
6f4e6361 1929 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
b4f71c8c 1930 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
6f4e6361
BL		 1931 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1932 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1933 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
8d8c82b6 1934 .patch_unknown_plane_state = dcn21_patch_unknown_plane_state,
6f4e6361
BL		 1935 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1936 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1937 .update_bw_bounding_box = update_bw_bounding_box
1938};
1939
d9e32672 1940static bool dcn21_resource_construct(
6f4e6361
BL		 1941 uint8_t num_virtual_links,
1942 struct dc *dc,
1943 struct dcn21_resource_pool *pool)
1944{
c0fb59a4 1945 int i, j;
6f4e6361
BL		 1946 struct dc_context *ctx = dc->ctx;
1947 struct irq_service_init_data init_data;
c0fb59a4 1948 uint32_t pipe_fuses = read_pipe_fuses(ctx);
ff86391e 1949 uint32_t num_pipes;
6f4e6361
BL		 1950
1951 ctx->dc_bios->regs = &bios_regs;
1952
1953 pool->base.res_cap = &res_cap_rn;
1954#ifdef DIAGS_BUILD
1955 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1956 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc;
1957 pool->base.res_cap = &res_cap_rn_FPGA_4pipe;
1958#endif
1959
1960 pool->base.funcs = &dcn21_res_pool_funcs;
1961
1962 /*************************************************
1963 * Resource + asic cap harcoding *
1964 *************************************************/
1965 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1966
c0fb59a4
BL		 1967 /* max pipe num for ASIC before check pipe fuses */
1968 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1969
6f4e6361
BL		 1970 dc->caps.max_downscale_ratio = 200;
1971 dc->caps.i2c_speed_in_khz = 100;
b15cde19 1972 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
6f4e6361 1973 dc->caps.max_cursor_size = 256;
9248681f 1974 dc->caps.min_horizontal_blanking_period = 80;
6f4e6361 1975 dc->caps.dmdata_alloc_size = 2048;
6f4e6361
BL		 1976
1977 dc->caps.max_slave_planes = 1;
1978 dc->caps.post_blend_color_processing = true;
1979 dc->caps.force_dp_tps4_for_cp2520 = true;
c797ede0 1980 dc->caps.extended_aux_timeout_support = true;
3a1627b0 1981 dc->caps.dmcub_support = true;
3cfe9fb6 1982 dc->caps.is_apu = true;
6f4e6361 1983
a8bf7164
KK		 1984 /* Color pipeline capabilities */
1985 dc->caps.color.dpp.dcn_arch = 1;
1986 dc->caps.color.dpp.input_lut_shared = 0;
1987 dc->caps.color.dpp.icsc = 1;
1988 dc->caps.color.dpp.dgam_ram = 1;
1989 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1990 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1991 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1992 dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1993 dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1994 dc->caps.color.dpp.post_csc = 0;
1995 dc->caps.color.dpp.gamma_corr = 0;
c6160900 1996 dc->caps.color.dpp.dgam_rom_for_yuv = 1;
a8bf7164
KK		 1997
1998 dc->caps.color.dpp.hw_3d_lut = 1;
1999 dc->caps.color.dpp.ogam_ram = 1;
2000 // no OGAM ROM on DCN2
2001 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2002 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2003 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2004 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2005 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2006 dc->caps.color.dpp.ocsc = 0;
2007
2008 dc->caps.color.mpc.gamut_remap = 0;
2009 dc->caps.color.mpc.num_3dluts = 0;
2010 dc->caps.color.mpc.shared_3d_lut = 0;
2011 dc->caps.color.mpc.ogam_ram = 1;
2012 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2013 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2014 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2015 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2016 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2017 dc->caps.color.mpc.ocsc = 1;
2018
6f4e6361
BL		 2019 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2020 dc->debug = debug_defaults_drv;
2021 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2022 pool->base.pipe_count = 4;
2023 dc->debug = debug_defaults_diags;
2024 } else
2025 dc->debug = debug_defaults_diags;
2026
2027 // Init the vm_helper
2028 if (dc->vm_helper)
2029 vm_helper_init(dc->vm_helper, 16);
2030
2031 /*************************************************
2032 * Create resources *
2033 *************************************************/
2034
2035 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
2036 dcn21_clock_source_create(ctx, ctx->dc_bios,
2037 CLOCK_SOURCE_COMBO_PHY_PLL0,
2038 &clk_src_regs[0], false);
2039 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
2040 dcn21_clock_source_create(ctx, ctx->dc_bios,
2041 CLOCK_SOURCE_COMBO_PHY_PLL1,
2042 &clk_src_regs[1], false);
15add0c2
IZ		 2043 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
2044 dcn21_clock_source_create(ctx, ctx->dc_bios,
2045 CLOCK_SOURCE_COMBO_PHY_PLL2,
2046 &clk_src_regs[2], false);
fc13b701
SL		 2047 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
2048 dcn21_clock_source_create(ctx, ctx->dc_bios,
2049 CLOCK_SOURCE_COMBO_PHY_PLL3,
2050 &clk_src_regs[3], false);
2051 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
2052 dcn21_clock_source_create(ctx, ctx->dc_bios,
2053 CLOCK_SOURCE_COMBO_PHY_PLL4,
2054 &clk_src_regs[4], false);
6f4e6361
BL		 2055
2056 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
2057
2058 /* todo: not reuse phy_pll registers */
2059 pool->base.dp_clock_source =
2060 dcn21_clock_source_create(ctx, ctx->dc_bios,
2061 CLOCK_SOURCE_ID_DP_DTO,
2062 &clk_src_regs[0], true);
2063
2064 for (i = 0; i < pool->base.clk_src_count; i++) {
2065 if (pool->base.clock_sources[i] == NULL) {
2066 dm_error("DC: failed to create clock sources!\n");
2067 BREAK_TO_DEBUGGER();
2068 goto create_fail;
2069 }
2070 }
2071
c07cbc1f 2072 pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
6f4e6361
BL		 2073 if (pool->base.dccg == NULL) {
2074 dm_error("DC: failed to create dccg!\n");
2075 BREAK_TO_DEBUGGER();
2076 goto create_fail;
2077 }
2078
501b4026 2079 if (!dc->config.disable_dmcu) {
16012806
WW		 2080 pool->base.dmcu = dcn21_dmcu_create(ctx,
2081 &dmcu_regs,
2082 &dmcu_shift,
2083 &dmcu_mask);
2084 if (pool->base.dmcu == NULL) {
2085 dm_error("DC: failed to create dmcu!\n");
2086 BREAK_TO_DEBUGGER();
2087 goto create_fail;
2088 }
a96562b0
AP		 2089
2090 dc->debug.dmub_command_table = false;
c0fb59a4
BL		 2091 }
2092
501b4026 2093 if (dc->config.disable_dmcu) {
9dac88d8
WW		 2094 pool->base.psr = dmub_psr_create(ctx);
2095
2096 if (pool->base.psr == NULL) {
2097 dm_error("DC: failed to create psr obj!\n");
2098 BREAK_TO_DEBUGGER();
2099 goto create_fail;
2100 }
2101 }
4c1a1335 2102
501b4026 2103 if (dc->config.disable_dmcu)
16012806
WW		 2104 pool->base.abm = dmub_abm_create(ctx,
2105 &abm_regs,
2106 &abm_shift,
2107 &abm_mask);
2108 else
2109 pool->base.abm = dce_abm_create(ctx,
c0fb59a4
BL		 2110 &abm_regs,
2111 &abm_shift,
2112 &abm_mask);
c0fb59a4 2113
6f4e6361
BL		 2114 pool->base.pp_smu = dcn21_pp_smu_create(ctx);
2115
ff86391e
MS		 2116 num_pipes = dcn2_1_ip.max_num_dpp;
2117
2118 for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
2119 if (pipe_fuses & 1 << i)
2120 num_pipes--;
2121 dcn2_1_ip.max_num_dpp = num_pipes;
2122 dcn2_1_ip.max_num_otg = num_pipes;
2123
6f4e6361
BL		 2124 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
2125
2126 init_data.ctx = dc->ctx;
2127 pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
2128 if (!pool->base.irqs)
2129 goto create_fail;
2130
c0fb59a4 2131 j = 0;
6f4e6361
BL		 2132 /* mem input -> ipp -> dpp -> opp -> TG */
2133 for (i = 0; i < pool->base.pipe_count; i++) {
c0fb59a4
BL		 2134 /* if pipe is disabled, skip instance of HW pipe,
2135 * i.e, skip ASIC register instance
2136 */
2137 if ((pipe_fuses & (1 << i)) != 0)
2138 continue;
2139
b9f1246d
NA		 2140 pool->base.hubps[j] = dcn21_hubp_create(ctx, i);
2141 if (pool->base.hubps[j] == NULL) {
6f4e6361
BL		 2142 BREAK_TO_DEBUGGER();
2143 dm_error(
2144 "DC: failed to create memory input!\n");
2145 goto create_fail;
2146 }
2147
b9f1246d
NA		 2148 pool->base.ipps[j] = dcn21_ipp_create(ctx, i);
2149 if (pool->base.ipps[j] == NULL) {
6f4e6361
BL		 2150 BREAK_TO_DEBUGGER();
2151 dm_error(
2152 "DC: failed to create input pixel processor!\n");
2153 goto create_fail;
2154 }
2155
b9f1246d
NA		 2156 pool->base.dpps[j] = dcn21_dpp_create(ctx, i);
2157 if (pool->base.dpps[j] == NULL) {
6f4e6361
BL		 2158 BREAK_TO_DEBUGGER();
2159 dm_error(
2160 "DC: failed to create dpps!\n");
2161 goto create_fail;
2162 }
c0fb59a4 2163
b9f1246d
NA		 2164 pool->base.opps[j] = dcn21_opp_create(ctx, i);
2165 if (pool->base.opps[j] == NULL) {
c0fb59a4
BL		 2166 BREAK_TO_DEBUGGER();
2167 dm_error(
2168 "DC: failed to create output pixel processor!\n");
2169 goto create_fail;
2170 }
2171
b9f1246d 2172 pool->base.timing_generators[j] = dcn21_timing_generator_create(
c0fb59a4 2173 ctx, i);
b9f1246d 2174 if (pool->base.timing_generators[j] == NULL) {
c0fb59a4
BL		 2175 BREAK_TO_DEBUGGER();
2176 dm_error("DC: failed to create tg!\n");
2177 goto create_fail;
2178 }
2179 j++;
6f4e6361
BL		 2180 }
2181
2182 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2183 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
2184 if (pool->base.engines[i] == NULL) {
2185 BREAK_TO_DEBUGGER();
2186 dm_error(
2187 "DC:failed to create aux engine!!\n");
2188 goto create_fail;
2189 }
2190 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
2191 if (pool->base.hw_i2cs[i] == NULL) {
2192 BREAK_TO_DEBUGGER();
2193 dm_error(
2194 "DC:failed to create hw i2c!!\n");
2195 goto create_fail;
2196 }
2197 pool->base.sw_i2cs[i] = NULL;
2198 }
2199
c0fb59a4
BL		 2200 pool->base.timing_generator_count = j;
2201 pool->base.pipe_count = j;
2202 pool->base.mpcc_count = j;
6f4e6361
BL		 2203
2204 pool->base.mpc = dcn21_mpc_create(ctx);
2205 if (pool->base.mpc == NULL) {
2206 BREAK_TO_DEBUGGER();
2207 dm_error("DC: failed to create mpc!\n");
2208 goto create_fail;
2209 }
2210
2211 pool->base.hubbub = dcn21_hubbub_create(ctx);
2212 if (pool->base.hubbub == NULL) {
2213 BREAK_TO_DEBUGGER();
2214 dm_error("DC: failed to create hubbub!\n");
2215 goto create_fail;
2216 }
2217
6f4e6361
BL		 2218 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2219 pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
2220 if (pool->base.dscs[i] == NULL) {
2221 BREAK_TO_DEBUGGER();
2222 dm_error("DC: failed to create display stream compressor %d!\n", i);
2223 goto create_fail;
2224 }
2225 }
6f4e6361
BL		 2226
2227 if (!dcn20_dwbc_create(ctx, &pool->base)) {
2228 BREAK_TO_DEBUGGER();
2229 dm_error("DC: failed to create dwbc!\n");
2230 goto create_fail;
2231 }
2232 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
2233 BREAK_TO_DEBUGGER();
2234 dm_error("DC: failed to create mcif_wb!\n");
2235 goto create_fail;
2236 }
2237
2238 if (!resource_construct(num_virtual_links, dc, &pool->base,
2239 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2240 &res_create_funcs : &res_create_maximus_funcs)))
2241 goto create_fail;
2242
c0fb59a4 2243 dcn21_hw_sequencer_construct(dc);
6f4e6361
BL		 2244
2245 dc->caps.max_planes = pool->base.pipe_count;
2246
2247 for (i = 0; i < dc->caps.max_planes; ++i)
2248 dc->caps.planes[i] = plane_cap;
2249
2250 dc->cap_funcs = cap_funcs;
2251
2252 return true;
2253
2254create_fail:
2255
d9e32672 2256 dcn21_resource_destruct(pool);
6f4e6361
BL		 2257
2258 return false;
2259}
2260
2261struct resource_pool *dcn21_create_resource_pool(
2262 const struct dc_init_data *init_data,
2263 struct dc *dc)
2264{
2265 struct dcn21_resource_pool *pool =
2266 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);
2267
2268 if (!pool)
2269 return NULL;
2270
d9e32672 2271 if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
6f4e6361
BL		 2272 return &pool->base;
2273
2274 BREAK_TO_DEBUGGER();
2275 kfree(pool);
2276 return NULL;
2277}
Linux 6.x block layer and io_uring tree(s)