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drm/amd/display: add null checks and set update flags for DCN2
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / dc / dcn20 / dcn20_resource.c
CommitLineData
7ed4e635
HW		 1/*
2* Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services.h"
27#include "dc.h"
28
29#include "resource.h"
30#include "include/irq_service_interface.h"
31#include "dcn20/dcn20_resource.h"
32
33#include "dcn10/dcn10_hubp.h"
34#include "dcn10/dcn10_ipp.h"
35#include "dcn20_hubbub.h"
36#include "dcn20_mpc.h"
37#include "dcn20_hubp.h"
38#include "irq/dcn20/irq_service_dcn20.h"
39#include "dcn20_dpp.h"
40#include "dcn20_optc.h"
41#include "dcn20_hwseq.h"
42#include "dce110/dce110_hw_sequencer.h"
43#include "dcn20_opp.h"
44
97bda032
HW		 45#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
46#include "dcn20_dsc.h"
47#endif
48
7ed4e635
HW		 49#include "dcn20_link_encoder.h"
50#include "dcn20_stream_encoder.h"
51#include "dce/dce_clock_source.h"
52#include "dce/dce_audio.h"
53#include "dce/dce_hwseq.h"
54#include "virtual/virtual_stream_encoder.h"
55#include "dce110/dce110_resource.h"
56#include "dml/display_mode_vba.h"
57#include "dcn20_dccg.h"
58#include "dcn20_vmid.h"
59
60#include "navi10_ip_offset.h"
61
62#include "dcn/dcn_2_0_0_offset.h"
63#include "dcn/dcn_2_0_0_sh_mask.h"
64
65#include "nbio/nbio_2_3_offset.h"
66
bb21290f
CL		 67#include "dcn20/dcn20_dwb.h"
68#include "dcn20/dcn20_mmhubbub.h"
69
7ed4e635
HW		 70#include "mmhub/mmhub_2_0_0_offset.h"
71#include "mmhub/mmhub_2_0_0_sh_mask.h"
72
73#include "reg_helper.h"
74#include "dce/dce_abm.h"
75#include "dce/dce_dmcu.h"
76#include "dce/dce_aux.h"
77#include "dce/dce_i2c.h"
78#include "vm_helper.h"
79
80#include "amdgpu_socbb.h"
81
82#define SOC_BOUNDING_BOX_VALID false
83#define DC_LOGGER_INIT(logger)
84
85struct _vcs_dpi_ip_params_st dcn2_0_ip = {
86 .odm_capable = 1,
87 .gpuvm_enable = 0,
88 .hostvm_enable = 0,
89 .gpuvm_max_page_table_levels = 4,
90 .hostvm_max_page_table_levels = 4,
91 .hostvm_cached_page_table_levels = 0,
92 .pte_group_size_bytes = 2048,
97bda032
HW		 93#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
94 .num_dsc = 6,
95#else
7ed4e635 96 .num_dsc = 0,
97bda032 97#endif
7ed4e635
HW		 98 .rob_buffer_size_kbytes = 168,
99 .det_buffer_size_kbytes = 164,
100 .dpte_buffer_size_in_pte_reqs_luma = 84,
101 .pde_proc_buffer_size_64k_reqs = 48,
102 .dpp_output_buffer_pixels = 2560,
103 .opp_output_buffer_lines = 1,
104 .pixel_chunk_size_kbytes = 8,
105 .pte_chunk_size_kbytes = 2,
106 .meta_chunk_size_kbytes = 2,
107 .writeback_chunk_size_kbytes = 2,
108 .line_buffer_size_bits = 789504,
109 .is_line_buffer_bpp_fixed = 0,
110 .line_buffer_fixed_bpp = 0,
111 .dcc_supported = true,
112 .max_line_buffer_lines = 12,
113 .writeback_luma_buffer_size_kbytes = 12,
114 .writeback_chroma_buffer_size_kbytes = 8,
115 .writeback_chroma_line_buffer_width_pixels = 4,
116 .writeback_max_hscl_ratio = 1,
117 .writeback_max_vscl_ratio = 1,
118 .writeback_min_hscl_ratio = 1,
119 .writeback_min_vscl_ratio = 1,
120 .writeback_max_hscl_taps = 12,
121 .writeback_max_vscl_taps = 12,
122 .writeback_line_buffer_luma_buffer_size = 0,
123 .writeback_line_buffer_chroma_buffer_size = 14643,
124 .cursor_buffer_size = 8,
125 .cursor_chunk_size = 2,
126 .max_num_otg = 6,
127 .max_num_dpp = 6,
128 .max_num_wb = 1,
129 .max_dchub_pscl_bw_pix_per_clk = 4,
130 .max_pscl_lb_bw_pix_per_clk = 2,
131 .max_lb_vscl_bw_pix_per_clk = 4,
132 .max_vscl_hscl_bw_pix_per_clk = 4,
133 .max_hscl_ratio = 8,
134 .max_vscl_ratio = 8,
135 .hscl_mults = 4,
136 .vscl_mults = 4,
137 .max_hscl_taps = 8,
138 .max_vscl_taps = 8,
139 .dispclk_ramp_margin_percent = 1,
140 .underscan_factor = 1.10,
141 .min_vblank_lines = 32, //
142 .dppclk_delay_subtotal = 77, //
143 .dppclk_delay_scl_lb_only = 16,
144 .dppclk_delay_scl = 50,
145 .dppclk_delay_cnvc_formatter = 8,
146 .dppclk_delay_cnvc_cursor = 6,
147 .dispclk_delay_subtotal = 87, //
148 .dcfclk_cstate_latency = 10, // SRExitTime
149 .max_inter_dcn_tile_repeaters = 8,
150
151 .xfc_supported = true,
152 .xfc_fill_bw_overhead_percent = 10.0,
153 .xfc_fill_constant_bytes = 0,
154};
155
156struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = { 0 };
157
158
159#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
160 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
161 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
162 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
163 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
164 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
165 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
166 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
167 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
168 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
169 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
170 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
171 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
172 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
173 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
174#endif
175
176
177enum dcn20_clk_src_array_id {
178 DCN20_CLK_SRC_PLL0,
179 DCN20_CLK_SRC_PLL1,
180 DCN20_CLK_SRC_PLL2,
181 DCN20_CLK_SRC_PLL3,
182 DCN20_CLK_SRC_PLL4,
183 DCN20_CLK_SRC_PLL5,
184 DCN20_CLK_SRC_TOTAL
185};
186
187/* begin *********************
188 * macros to expend register list macro defined in HW object header file */
189
190/* DCN */
191/* TODO awful hack. fixup dcn20_dwb.h */
192#undef BASE_INNER
193#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
194
195#define BASE(seg) BASE_INNER(seg)
196
197#define SR(reg_name)\
198 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
199 mm ## reg_name
200
201#define SRI(reg_name, block, id)\
202 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
203 mm ## block ## id ## _ ## reg_name
204
205#define SRIR(var_name, reg_name, block, id)\
206 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
207 mm ## block ## id ## _ ## reg_name
208
209#define SRII(reg_name, block, id)\
210 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
211 mm ## block ## id ## _ ## reg_name
212
213#define DCCG_SRII(reg_name, block, id)\
214 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
215 mm ## block ## id ## _ ## reg_name
216
217/* NBIO */
218#define NBIO_BASE_INNER(seg) \
219 NBIO_BASE__INST0_SEG ## seg
220
221#define NBIO_BASE(seg) \
222 NBIO_BASE_INNER(seg)
223
224#define NBIO_SR(reg_name)\
225 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
226 mm ## reg_name
227
228/* MMHUB */
229#define MMHUB_BASE_INNER(seg) \
230 MMHUB_BASE__INST0_SEG ## seg
231
232#define MMHUB_BASE(seg) \
233 MMHUB_BASE_INNER(seg)
234
235#define MMHUB_SR(reg_name)\
236 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
237 mmMM ## reg_name
238
239static const struct bios_registers bios_regs = {
240 NBIO_SR(BIOS_SCRATCH_3),
241 NBIO_SR(BIOS_SCRATCH_6)
242};
243
244#define clk_src_regs(index, pllid)\
245[index] = {\
246 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
247}
248
249static const struct dce110_clk_src_regs clk_src_regs[] = {
250 clk_src_regs(0, A),
251 clk_src_regs(1, B),
252 clk_src_regs(2, C),
253 clk_src_regs(3, D),
254 clk_src_regs(4, E),
255 clk_src_regs(5, F)
256};
257
258static const struct dce110_clk_src_shift cs_shift = {
259 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
260};
261
262static const struct dce110_clk_src_mask cs_mask = {
263 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
264};
265
266static const struct dce_dmcu_registers dmcu_regs = {
267 DMCU_DCN10_REG_LIST()
268};
269
270static const struct dce_dmcu_shift dmcu_shift = {
271 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
272};
273
274static const struct dce_dmcu_mask dmcu_mask = {
275 DMCU_MASK_SH_LIST_DCN10(_MASK)
276};
d7c29549 277
7ed4e635 278static const struct dce_abm_registers abm_regs = {
d7c29549 279 ABM_DCN20_REG_LIST()
7ed4e635
HW		 280};
281
282static const struct dce_abm_shift abm_shift = {
d7c29549 283 ABM_MASK_SH_LIST_DCN20(__SHIFT)
7ed4e635
HW		 284};
285
286static const struct dce_abm_mask abm_mask = {
d7c29549 287 ABM_MASK_SH_LIST_DCN20(_MASK)
7ed4e635 288};
d7c29549 289
7ed4e635
HW		 290#define audio_regs(id)\
291[id] = {\
292 AUD_COMMON_REG_LIST(id)\
293}
294
295static const struct dce_audio_registers audio_regs[] = {
296 audio_regs(0),
297 audio_regs(1),
298 audio_regs(2),
299 audio_regs(3),
300 audio_regs(4),
301 audio_regs(5),
302 audio_regs(6),
303};
304
305#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
306 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
307 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
308 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
309
310static const struct dce_audio_shift audio_shift = {
311 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
312};
313
314static const struct dce_aduio_mask audio_mask = {
315 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
316};
317
318#define stream_enc_regs(id)\
319[id] = {\
320 SE_DCN2_REG_LIST(id)\
321}
322
323static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
324 stream_enc_regs(0),
325 stream_enc_regs(1),
326 stream_enc_regs(2),
327 stream_enc_regs(3),
328 stream_enc_regs(4),
329 stream_enc_regs(5),
330};
331
332static const struct dcn10_stream_encoder_shift se_shift = {
333 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
334};
335
336static const struct dcn10_stream_encoder_mask se_mask = {
337 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
338};
339
340
341#define aux_regs(id)\
342[id] = {\
343 DCN2_AUX_REG_LIST(id)\
344}
345
346static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
347 aux_regs(0),
348 aux_regs(1),
349 aux_regs(2),
350 aux_regs(3),
351 aux_regs(4),
352 aux_regs(5)
353};
354
355#define hpd_regs(id)\
356[id] = {\
357 HPD_REG_LIST(id)\
358}
359
360static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
361 hpd_regs(0),
362 hpd_regs(1),
363 hpd_regs(2),
364 hpd_regs(3),
365 hpd_regs(4),
366 hpd_regs(5)
367};
368
369#define link_regs(id, phyid)\
370[id] = {\
371 LE_DCN10_REG_LIST(id), \
372 UNIPHY_DCN2_REG_LIST(phyid), \
373 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
374}
375
376static const struct dcn10_link_enc_registers link_enc_regs[] = {
377 link_regs(0, A),
378 link_regs(1, B),
379 link_regs(2, C),
380 link_regs(3, D),
381 link_regs(4, E),
382 link_regs(5, F)
383};
384
385static const struct dcn10_link_enc_shift le_shift = {
386 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT)
387};
388
389static const struct dcn10_link_enc_mask le_mask = {
390 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK)
391};
392
393#define ipp_regs(id)\
394[id] = {\
395 IPP_REG_LIST_DCN20(id),\
396}
397
398static const struct dcn10_ipp_registers ipp_regs[] = {
399 ipp_regs(0),
400 ipp_regs(1),
401 ipp_regs(2),
402 ipp_regs(3),
403 ipp_regs(4),
404 ipp_regs(5),
405};
406
407static const struct dcn10_ipp_shift ipp_shift = {
408 IPP_MASK_SH_LIST_DCN20(__SHIFT)
409};
410
411static const struct dcn10_ipp_mask ipp_mask = {
412 IPP_MASK_SH_LIST_DCN20(_MASK),
413};
414
415#define opp_regs(id)\
416[id] = {\
417 OPP_REG_LIST_DCN20(id),\
418}
419
420static const struct dcn20_opp_registers opp_regs[] = {
421 opp_regs(0),
422 opp_regs(1),
423 opp_regs(2),
424 opp_regs(3),
425 opp_regs(4),
426 opp_regs(5),
427};
428
429static const struct dcn20_opp_shift opp_shift = {
430 OPP_MASK_SH_LIST_DCN20(__SHIFT)
431};
432
433static const struct dcn20_opp_mask opp_mask = {
434 OPP_MASK_SH_LIST_DCN20(_MASK)
435};
436
437#define aux_engine_regs(id)\
438[id] = {\
439 AUX_COMMON_REG_LIST0(id), \
440 .AUXN_IMPCAL = 0, \
441 .AUXP_IMPCAL = 0, \
442 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
443}
444
445static const struct dce110_aux_registers aux_engine_regs[] = {
446 aux_engine_regs(0),
447 aux_engine_regs(1),
448 aux_engine_regs(2),
449 aux_engine_regs(3),
450 aux_engine_regs(4),
451 aux_engine_regs(5)
452};
453
454#define tf_regs(id)\
455[id] = {\
456 TF_REG_LIST_DCN20(id),\
457}
458
459static const struct dcn2_dpp_registers tf_regs[] = {
460 tf_regs(0),
461 tf_regs(1),
462 tf_regs(2),
463 tf_regs(3),
464 tf_regs(4),
465 tf_regs(5),
466};
467
468static const struct dcn2_dpp_shift tf_shift = {
469 TF_REG_LIST_SH_MASK_DCN20(__SHIFT)
470};
471
472static const struct dcn2_dpp_mask tf_mask = {
473 TF_REG_LIST_SH_MASK_DCN20(_MASK)
474};
475
bb21290f
CL		 476#define dwbc_regs_dcn2(id)\
477[id] = {\
478 DWBC_COMMON_REG_LIST_DCN2_0(id),\
479 }
480
481static const struct dcn20_dwbc_registers dwbc20_regs[] = {
482 dwbc_regs_dcn2(0),
483};
484
485static const struct dcn20_dwbc_shift dwbc20_shift = {
486 DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
487};
488
489static const struct dcn20_dwbc_mask dwbc20_mask = {
490 DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
491};
492
493#define mcif_wb_regs_dcn2(id)\
494[id] = {\
495 MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\
496 }
497
498static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {
499 mcif_wb_regs_dcn2(0),
500};
501
502static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {
503 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
504};
505
506static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {
507 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
508};
509
7ed4e635
HW		 510static const struct dcn20_mpc_registers mpc_regs = {
511 MPC_REG_LIST_DCN2_0(0),
512 MPC_REG_LIST_DCN2_0(1),
513 MPC_REG_LIST_DCN2_0(2),
514 MPC_REG_LIST_DCN2_0(3),
515 MPC_REG_LIST_DCN2_0(4),
516 MPC_REG_LIST_DCN2_0(5),
517 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
518 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
519 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
520 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
521 MPC_OUT_MUX_REG_LIST_DCN2_0(4),
522 MPC_OUT_MUX_REG_LIST_DCN2_0(5),
523};
524
525static const struct dcn20_mpc_shift mpc_shift = {
526 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
527};
528
529static const struct dcn20_mpc_mask mpc_mask = {
530 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
531};
532
533#define tg_regs(id)\
534[id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
535
536
537static const struct dcn_optc_registers tg_regs[] = {
538 tg_regs(0),
539 tg_regs(1),
540 tg_regs(2),
541 tg_regs(3),
542 tg_regs(4),
543 tg_regs(5)
544};
545
546static const struct dcn_optc_shift tg_shift = {
547 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
548};
549
550static const struct dcn_optc_mask tg_mask = {
551 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
552};
553
554#define hubp_regs(id)\
555[id] = {\
556 HUBP_REG_LIST_DCN20(id)\
557}
558
559static const struct dcn_hubp2_registers hubp_regs[] = {
560 hubp_regs(0),
561 hubp_regs(1),
562 hubp_regs(2),
563 hubp_regs(3),
564 hubp_regs(4),
565 hubp_regs(5)
566};
567
568static const struct dcn_hubp2_shift hubp_shift = {
569 HUBP_MASK_SH_LIST_DCN20(__SHIFT)
570};
571
572static const struct dcn_hubp2_mask hubp_mask = {
573 HUBP_MASK_SH_LIST_DCN20(_MASK)
574};
575
576static const struct dcn_hubbub_registers hubbub_reg = {
577 HUBBUB_REG_LIST_DCN20(0)
578};
579
580static const struct dcn_hubbub_shift hubbub_shift = {
581 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT)
582};
583
584static const struct dcn_hubbub_mask hubbub_mask = {
585 HUBBUB_MASK_SH_LIST_DCN20(_MASK)
586};
587
588#define vmid_regs(id)\
589[id] = {\
590 DCN20_VMID_REG_LIST(id)\
591}
592
593static const struct dcn_vmid_registers vmid_regs[] = {
594 vmid_regs(0),
595 vmid_regs(1),
596 vmid_regs(2),
597 vmid_regs(3),
598 vmid_regs(4),
599 vmid_regs(5),
600 vmid_regs(6),
601 vmid_regs(7),
602 vmid_regs(8),
603 vmid_regs(9),
604 vmid_regs(10),
605 vmid_regs(11),
606 vmid_regs(12),
607 vmid_regs(13),
608 vmid_regs(14),
609 vmid_regs(15)
610};
611
612static const struct dcn20_vmid_shift vmid_shifts = {
613 DCN20_VMID_MASK_SH_LIST(__SHIFT)
614};
615
616static const struct dcn20_vmid_mask vmid_masks = {
617 DCN20_VMID_MASK_SH_LIST(_MASK)
618};
619
97bda032
HW		 620#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
621#define dsc_regsDCN20(id)\
622[id] = {\
623 DSC_REG_LIST_DCN20(id)\
624}
625
626static const struct dcn20_dsc_registers dsc_regs[] = {
627 dsc_regsDCN20(0),
628 dsc_regsDCN20(1),
629 dsc_regsDCN20(2),
630 dsc_regsDCN20(3),
631 dsc_regsDCN20(4),
632 dsc_regsDCN20(5)
633};
634
635static const struct dcn20_dsc_shift dsc_shift = {
636 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
637};
638
639static const struct dcn20_dsc_mask dsc_mask = {
640 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
641};
642#endif
7ed4e635
HW		 643
644static const struct dccg_registers dccg_regs = {
645 DCCG_REG_LIST_DCN2()
646};
647
648static const struct dccg_shift dccg_shift = {
649 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
650};
651
652static const struct dccg_mask dccg_mask = {
653 DCCG_MASK_SH_LIST_DCN2(_MASK)
654};
655
656static const struct resource_caps res_cap_nv10 = {
657 .num_timing_generator = 6,
658 .num_opp = 6,
659 .num_video_plane = 6,
660 .num_audio = 7,
661 .num_stream_encoder = 6,
662 .num_pll = 6,
0d7bd17c 663 .num_dwb = 0,
7ed4e635
HW		 664 .num_ddc = 6,
665 .num_vmid = 16,
97bda032
HW		 666#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
667 .num_dsc = 6,
668#endif
7ed4e635
HW		 669};
670
671static const struct dc_plane_cap plane_cap = {
672 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
673 .blends_with_above = true,
674 .blends_with_below = true,
7ed4e635 675 .per_pixel_alpha = true,
5b1b2f20
AD		 676
677 .pixel_format_support = {
678 .argb8888 = true,
679 .nv12 = true,
680 .fp16 = true
681 },
682
683 .max_upscale_factor = {
684 .argb8888 = 16000,
685 .nv12 = 16000,
686 .fp16 = 1
687 },
688
689 .max_downscale_factor = {
690 .argb8888 = 250,
691 .nv12 = 250,
692 .fp16 = 1
693 }
7ed4e635
HW		 694};
695
696static const struct dc_debug_options debug_defaults_drv = {
697 .disable_dmcu = true,
698 .force_abm_enable = false,
699 .timing_trace = false,
700 .clock_trace = true,
701 .disable_pplib_clock_request = true,
702 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
703 .force_single_disp_pipe_split = true,
704 .disable_dcc = DCC_ENABLE,
705 .vsr_support = true,
706 .performance_trace = false,
707 .max_downscale_src_width = 5120,/*upto 5K*/
708 .disable_pplib_wm_range = false,
709 .scl_reset_length10 = true,
9e14d4f1 710 .sanity_checks = false,
7ed4e635
HW		 711 .disable_tri_buf = true,
712};
713
714static const struct dc_debug_options debug_defaults_diags = {
715 .disable_dmcu = true,
716 .force_abm_enable = false,
717 .timing_trace = true,
718 .clock_trace = true,
719 .disable_dpp_power_gate = true,
720 .disable_hubp_power_gate = true,
721 .disable_clock_gate = true,
722 .disable_pplib_clock_request = true,
723 .disable_pplib_wm_range = true,
724 .disable_stutter = true,
725 .scl_reset_length10 = true,
726};
727
728void dcn20_dpp_destroy(struct dpp **dpp)
729{
730 kfree(TO_DCN20_DPP(*dpp));
731 *dpp = NULL;
732}
733
734struct dpp *dcn20_dpp_create(
735 struct dc_context *ctx,
736 uint32_t inst)
737{
738 struct dcn20_dpp *dpp =
739 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
740
741 if (!dpp)
742 return NULL;
743
744 if (dpp2_construct(dpp, ctx, inst,
745 &tf_regs[inst], &tf_shift, &tf_mask))
746 return &dpp->base;
747
748 BREAK_TO_DEBUGGER();
749 kfree(dpp);
750 return NULL;
751}
752
753struct input_pixel_processor *dcn20_ipp_create(
754 struct dc_context *ctx, uint32_t inst)
755{
756 struct dcn10_ipp *ipp =
757 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
758
759 if (!ipp) {
760 BREAK_TO_DEBUGGER();
761 return NULL;
762 }
763
764 dcn20_ipp_construct(ipp, ctx, inst,
765 &ipp_regs[inst], &ipp_shift, &ipp_mask);
766 return &ipp->base;
767}
768
769
770struct output_pixel_processor *dcn20_opp_create(
771 struct dc_context *ctx, uint32_t inst)
772{
773 struct dcn20_opp *opp =
774 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
775
776 if (!opp) {
777 BREAK_TO_DEBUGGER();
778 return NULL;
779 }
780
781 dcn20_opp_construct(opp, ctx, inst,
782 &opp_regs[inst], &opp_shift, &opp_mask);
783 return &opp->base;
784}
785
786struct dce_aux *dcn20_aux_engine_create(
787 struct dc_context *ctx,
788 uint32_t inst)
789{
790 struct aux_engine_dce110 *aux_engine =
791 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
792
793 if (!aux_engine)
794 return NULL;
795
796 dce110_aux_engine_construct(aux_engine, ctx, inst,
797 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
798 &aux_engine_regs[inst]);
799
800 return &aux_engine->base;
801}
802#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
803
804static const struct dce_i2c_registers i2c_hw_regs[] = {
805 i2c_inst_regs(1),
806 i2c_inst_regs(2),
807 i2c_inst_regs(3),
808 i2c_inst_regs(4),
809 i2c_inst_regs(5),
810 i2c_inst_regs(6),
811};
812
813static const struct dce_i2c_shift i2c_shifts = {
814 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
815};
816
817static const struct dce_i2c_mask i2c_masks = {
818 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
819};
820
821struct dce_i2c_hw *dcn20_i2c_hw_create(
822 struct dc_context *ctx,
823 uint32_t inst)
824{
825 struct dce_i2c_hw *dce_i2c_hw =
826 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
827
828 if (!dce_i2c_hw)
829 return NULL;
830
831 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
832 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
833
834 return dce_i2c_hw;
835}
836struct mpc *dcn20_mpc_create(struct dc_context *ctx)
837{
838 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
839 GFP_KERNEL);
840
841 if (!mpc20)
842 return NULL;
843
844 dcn20_mpc_construct(mpc20, ctx,
845 &mpc_regs,
846 &mpc_shift,
847 &mpc_mask,
848 6);
849
850 return &mpc20->base;
851}
852
853struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)
854{
855 int i;
856 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
857 GFP_KERNEL);
858
859 if (!hubbub)
860 return NULL;
861
862 hubbub2_construct(hubbub, ctx,
863 &hubbub_reg,
864 &hubbub_shift,
865 &hubbub_mask);
866
867 for (i = 0; i < res_cap_nv10.num_vmid; i++) {
868 struct dcn20_vmid *vmid = &hubbub->vmid[i];
869
870 vmid->ctx = ctx;
871
872 vmid->regs = &vmid_regs[i];
873 vmid->shifts = &vmid_shifts;
874 vmid->masks = &vmid_masks;
875 }
876
877 return &hubbub->base;
878}
879
880struct timing_generator *dcn20_timing_generator_create(
881 struct dc_context *ctx,
882 uint32_t instance)
883{
884 struct optc *tgn10 =
885 kzalloc(sizeof(struct optc), GFP_KERNEL);
886
887 if (!tgn10)
888 return NULL;
889
890 tgn10->base.inst = instance;
891 tgn10->base.ctx = ctx;
892
893 tgn10->tg_regs = &tg_regs[instance];
894 tgn10->tg_shift = &tg_shift;
895 tgn10->tg_mask = &tg_mask;
896
897 dcn20_timing_generator_init(tgn10);
898
899 return &tgn10->base;
900}
901
902static const struct encoder_feature_support link_enc_feature = {
903 .max_hdmi_deep_color = COLOR_DEPTH_121212,
904 .max_hdmi_pixel_clock = 600000,
905 .hdmi_ycbcr420_supported = true,
906 .dp_ycbcr420_supported = true,
907 .flags.bits.IS_HBR2_CAPABLE = true,
908 .flags.bits.IS_HBR3_CAPABLE = true,
909 .flags.bits.IS_TPS3_CAPABLE = true,
910 .flags.bits.IS_TPS4_CAPABLE = true
911};
912
913struct link_encoder *dcn20_link_encoder_create(
914 const struct encoder_init_data *enc_init_data)
915{
916 struct dcn20_link_encoder *enc20 =
917 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
918
919 if (!enc20)
920 return NULL;
921
922 dcn20_link_encoder_construct(enc20,
923 enc_init_data,
924 &link_enc_feature,
925 &link_enc_regs[enc_init_data->transmitter],
926 &link_enc_aux_regs[enc_init_data->channel - 1],
927 &link_enc_hpd_regs[enc_init_data->hpd_source],
928 &le_shift,
929 &le_mask);
930
931 return &enc20->enc10.base;
932}
933
934struct clock_source *dcn20_clock_source_create(
935 struct dc_context *ctx,
936 struct dc_bios *bios,
937 enum clock_source_id id,
938 const struct dce110_clk_src_regs *regs,
939 bool dp_clk_src)
940{
941 struct dce110_clk_src *clk_src =
942 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
943
944 if (!clk_src)
945 return NULL;
946
947 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
948 regs, &cs_shift, &cs_mask)) {
949 clk_src->base.dp_clk_src = dp_clk_src;
950 return &clk_src->base;
951 }
952
953 BREAK_TO_DEBUGGER();
954 return NULL;
955}
956
957static void read_dce_straps(
958 struct dc_context *ctx,
959 struct resource_straps *straps)
960{
961 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
962 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
963}
964
965static struct audio *dcn20_create_audio(
966 struct dc_context *ctx, unsigned int inst)
967{
968 return dce_audio_create(ctx, inst,
969 &audio_regs[inst], &audio_shift, &audio_mask);
970}
971
972struct stream_encoder *dcn20_stream_encoder_create(
973 enum engine_id eng_id,
974 struct dc_context *ctx)
975{
976 struct dcn10_stream_encoder *enc1 =
977 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
978
979 if (!enc1)
980 return NULL;
981
982 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
983 &stream_enc_regs[eng_id],
984 &se_shift, &se_mask);
985
986 return &enc1->base;
987}
988
989static const struct dce_hwseq_registers hwseq_reg = {
990 HWSEQ_DCN2_REG_LIST()
991};
992
993static const struct dce_hwseq_shift hwseq_shift = {
994 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT)
995};
996
997static const struct dce_hwseq_mask hwseq_mask = {
998 HWSEQ_DCN2_MASK_SH_LIST(_MASK)
999};
1000
1001struct dce_hwseq *dcn20_hwseq_create(
1002 struct dc_context *ctx)
1003{
1004 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1005
1006 if (hws) {
1007 hws->ctx = ctx;
1008 hws->regs = &hwseq_reg;
1009 hws->shifts = &hwseq_shift;
1010 hws->masks = &hwseq_mask;
1011 }
1012 return hws;
1013}
1014
1015static const struct resource_create_funcs res_create_funcs = {
1016 .read_dce_straps = read_dce_straps,
1017 .create_audio = dcn20_create_audio,
1018 .create_stream_encoder = dcn20_stream_encoder_create,
1019 .create_hwseq = dcn20_hwseq_create,
1020};
1021
1022static const struct resource_create_funcs res_create_maximus_funcs = {
1023 .read_dce_straps = NULL,
1024 .create_audio = NULL,
1025 .create_stream_encoder = NULL,
1026 .create_hwseq = dcn20_hwseq_create,
1027};
1028
1029void dcn20_clock_source_destroy(struct clock_source **clk_src)
1030{
1031 kfree(TO_DCE110_CLK_SRC(*clk_src));
1032 *clk_src = NULL;
1033}
1034
97bda032
HW		 1035#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1036
1037struct display_stream_compressor *dcn20_dsc_create(
1038 struct dc_context *ctx, uint32_t inst)
1039{
1040 struct dcn20_dsc *dsc =
1041 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1042
1043 if (!dsc) {
1044 BREAK_TO_DEBUGGER();
1045 return NULL;
1046 }
1047
1048 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1049 return &dsc->base;
1050}
1051
1052void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
1053{
1054 kfree(container_of(*dsc, struct dcn20_dsc, base));
1055 *dsc = NULL;
1056}
1057
1058#endif
7ed4e635
HW		 1059
1060static void destruct(struct dcn20_resource_pool *pool)
1061{
1062 unsigned int i;
1063
1064 for (i = 0; i < pool->base.stream_enc_count; i++) {
1065 if (pool->base.stream_enc[i] != NULL) {
1066 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1067 pool->base.stream_enc[i] = NULL;
1068 }
1069 }
1070
97bda032
HW		 1071#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1072 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1073 if (pool->base.dscs[i] != NULL)
1074 dcn20_dsc_destroy(&pool->base.dscs[i]);
1075 }
1076#endif
7ed4e635
HW		 1077
1078 if (pool->base.mpc != NULL) {
1079 kfree(TO_DCN20_MPC(pool->base.mpc));
1080 pool->base.mpc = NULL;
1081 }
1082 if (pool->base.hubbub != NULL) {
1083 kfree(pool->base.hubbub);
1084 pool->base.hubbub = NULL;
1085 }
1086 for (i = 0; i < pool->base.pipe_count; i++) {
1087 if (pool->base.dpps[i] != NULL)
1088 dcn20_dpp_destroy(&pool->base.dpps[i]);
1089
1090 if (pool->base.ipps[i] != NULL)
1091 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1092
1093 if (pool->base.hubps[i] != NULL) {
1094 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1095 pool->base.hubps[i] = NULL;
1096 }
1097
1098 if (pool->base.irqs != NULL) {
1099 dal_irq_service_destroy(&pool->base.irqs);
1100 }
1101 }
1102
1103 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1104 if (pool->base.engines[i] != NULL)
1105 dce110_engine_destroy(&pool->base.engines[i]);
1106 if (pool->base.hw_i2cs[i] != NULL) {
1107 kfree(pool->base.hw_i2cs[i]);
1108 pool->base.hw_i2cs[i] = NULL;
1109 }
1110 if (pool->base.sw_i2cs[i] != NULL) {
1111 kfree(pool->base.sw_i2cs[i]);
1112 pool->base.sw_i2cs[i] = NULL;
1113 }
1114 }
1115
1116 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1117 if (pool->base.opps[i] != NULL)
1118 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1119 }
1120
1121 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1122 if (pool->base.timing_generators[i] != NULL) {
1123 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1124 pool->base.timing_generators[i] = NULL;
1125 }
1126 }
1127
bb21290f
CL		 1128 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1129 if (pool->base.dwbc[i] != NULL) {
1130 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
1131 pool->base.dwbc[i] = NULL;
1132 }
1133 if (pool->base.mcif_wb[i] != NULL) {
1134 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
1135 pool->base.mcif_wb[i] = NULL;
1136 }
1137 }
1138
7ed4e635
HW		 1139 for (i = 0; i < pool->base.audio_count; i++) {
1140 if (pool->base.audios[i])
1141 dce_aud_destroy(&pool->base.audios[i]);
1142 }
1143
1144 for (i = 0; i < pool->base.clk_src_count; i++) {
1145 if (pool->base.clock_sources[i] != NULL) {
1146 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1147 pool->base.clock_sources[i] = NULL;
1148 }
1149 }
1150
1151 if (pool->base.dp_clock_source != NULL) {
1152 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1153 pool->base.dp_clock_source = NULL;
1154 }
1155
1156
1157 if (pool->base.abm != NULL)
1158 dce_abm_destroy(&pool->base.abm);
1159
1160 if (pool->base.dmcu != NULL)
1161 dce_dmcu_destroy(&pool->base.dmcu);
1162
1163 if (pool->base.dccg != NULL)
1164 dcn_dccg_destroy(&pool->base.dccg);
1165
1166 if (pool->base.pp_smu != NULL)
1167 dcn20_pp_smu_destroy(&pool->base.pp_smu);
1168
1169}
1170
1171struct hubp *dcn20_hubp_create(
1172 struct dc_context *ctx,
1173 uint32_t inst)
1174{
1175 struct dcn20_hubp *hubp2 =
1176 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1177
1178 if (!hubp2)
1179 return NULL;
1180
1181 if (hubp2_construct(hubp2, ctx, inst,
1182 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1183 return &hubp2->base;
1184
1185 BREAK_TO_DEBUGGER();
1186 kfree(hubp2);
1187 return NULL;
1188}
1189
1190static void get_pixel_clock_parameters(
1191 struct pipe_ctx *pipe_ctx,
1192 struct pixel_clk_params *pixel_clk_params)
1193{
1194 const struct dc_stream_state *stream = pipe_ctx->stream;
1195 bool odm_combine = dc_res_get_odm_bottom_pipe(pipe_ctx) != NULL;
1196
1197 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1198 pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1199 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1200 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1201 /* TODO: un-hardcode*/
1202 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1203 LINK_RATE_REF_FREQ_IN_KHZ;
1204 pixel_clk_params->flags.ENABLE_SS = 0;
1205 pixel_clk_params->color_depth =
1206 stream->timing.display_color_depth;
1207 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1208 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1209
1210 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1211 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1212
1213 if (optc1_is_two_pixels_per_containter(&stream->timing) || odm_combine)
1214 pixel_clk_params->requested_pix_clk_100hz /= 2;
1215
1216 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1217 pixel_clk_params->requested_pix_clk_100hz *= 2;
1218
1219}
1220
1221static void build_clamping_params(struct dc_stream_state *stream)
1222{
1223 stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1224 stream->clamping.c_depth = stream->timing.display_color_depth;
1225 stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1226}
1227
1228static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1229{
1230
1231 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1232
1233 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1234 pipe_ctx->clock_source,
1235 &pipe_ctx->stream_res.pix_clk_params,
1236 &pipe_ctx->pll_settings);
1237
1238 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1239
1240 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1241 &pipe_ctx->stream->bit_depth_params);
1242 build_clamping_params(pipe_ctx->stream);
1243
1244 return DC_OK;
1245}
1246
1247enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
1248{
1249 enum dc_status status = DC_OK;
1250 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1251
1252 /*TODO Seems unneeded anymore */
1253 /* if (old_context && resource_is_stream_unchanged(old_context, stream)) {
1254 if (stream != NULL && old_context->streams[i] != NULL) {
1255 todo: shouldn't have to copy missing parameter here
1256 resource_build_bit_depth_reduction_params(stream,
1257 &stream->bit_depth_params);
1258 stream->clamping.pixel_encoding =
1259 stream->timing.pixel_encoding;
1260
1261 resource_build_bit_depth_reduction_params(stream,
1262 &stream->bit_depth_params);
1263 build_clamping_params(stream);
1264
1265 continue;
1266 }
1267 }
1268 */
1269
1270 if (!pipe_ctx)
1271 return DC_ERROR_UNEXPECTED;
1272
1273
1274 status = build_pipe_hw_param(pipe_ctx);
1275
1276 return status;
1277}
1278
97bda032
HW		 1279#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1280
c9ae6e16
NC		 1281static void acquire_dsc(struct resource_context *res_ctx,
1282 const struct resource_pool *pool,
1283 struct display_stream_compressor **dsc)
97bda032
HW		 1284{
1285 int i;
c9ae6e16
NC		 1286
1287 ASSERT(*dsc == NULL);
1288 *dsc = NULL;
97bda032
HW		 1289
1290 /* Find first free DSC */
1291 for (i = 0; i < pool->res_cap->num_dsc; i++)
1292 if (!res_ctx->is_dsc_acquired[i]) {
c9ae6e16 1293 *dsc = pool->dscs[i];
97bda032
HW		 1294 res_ctx->is_dsc_acquired[i] = true;
1295 break;
1296 }
97bda032
HW		 1297}
1298
1299static void release_dsc(struct resource_context *res_ctx,
1300 const struct resource_pool *pool,
c9ae6e16 1301 struct display_stream_compressor **dsc)
97bda032
HW		 1302{
1303 int i;
1304
1305 for (i = 0; i < pool->res_cap->num_dsc; i++)
c9ae6e16 1306 if (pool->dscs[i] == *dsc) {
97bda032 1307 res_ctx->is_dsc_acquired[i] = false;
c9ae6e16 1308 *dsc = NULL;
97bda032
HW		 1309 break;
1310 }
1311}
1312
1313#endif
7ed4e635 1314
7ed4e635 1315
97bda032 1316#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
c9ae6e16
NC		 1317enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc,
1318 struct dc_state *dc_ctx,
1319 struct dc_stream_state *dc_stream)
1320{
1321 enum dc_status result = DC_OK;
1322 int i;
1323 const struct resource_pool *pool = dc->res_pool;
97bda032 1324
c9ae6e16
NC		 1325 /* Get a DSC if required and available */
1326 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1327 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];
97bda032 1328
c9ae6e16
NC		 1329 if (pipe_ctx->stream != dc_stream)
1330 continue;
97bda032 1331
c9ae6e16 1332 acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc);
97bda032 1333
c9ae6e16
NC		 1334 /* The number of DSCs can be less than the number of pipes */
1335 if (!pipe_ctx->stream_res.dsc) {
1336 dm_output_to_console("No DSCs available\n");
1337 result = DC_NO_DSC_RESOURCE;
97bda032 1338 }
7ed4e635 1339
c9ae6e16
NC		 1340 break;
1341 }
7ed4e635
HW		 1342
1343 return result;
1344}
1345
1346
c9ae6e16
NC		 1347enum dc_status dcn20_remove_dsc_from_stream_resource(struct dc *dc,
1348 struct dc_state *new_ctx,
1349 struct dc_stream_state *dc_stream)
7ed4e635
HW		 1350{
1351 struct pipe_ctx *pipe_ctx = NULL;
1352 int i;
1353
7ed4e635
HW		 1354 for (i = 0; i < MAX_PIPES; i++) {
1355 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1356 pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1357 break;
1358 }
1359 }
1360
1361 if (!pipe_ctx)
1362 return DC_ERROR_UNEXPECTED;
1363
97bda032
HW		 1364 if (pipe_ctx->stream_res.dsc) {
1365 struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
1366
c9ae6e16
NC		 1367 release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
1368 if (odm_pipe)
1369 release_dsc(&new_ctx->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
97bda032 1370 }
7ed4e635
HW		 1371
1372 return DC_OK;
1373}
c9ae6e16
NC		 1374#endif
1375
1376
1377enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1378{
1379 enum dc_status result = DC_ERROR_UNEXPECTED;
1380
1381 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1382
1383 if (result == DC_OK)
1384 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1385
1386#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1387 /* Get a DSC if required and available */
1388 if (result == DC_OK && dc_stream->timing.flags.DSC)
1389 result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
1390#endif
1391
1392 if (result == DC_OK)
1393 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
1394
1395 return result;
1396}
1397
1398
1399enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1400{
1401 enum dc_status result = DC_OK;
1402
1403#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1404 result = dcn20_remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
1405#endif
1406
1407 return result;
1408}
7ed4e635
HW		 1409
1410
1411static void swizzle_to_dml_params(
1412 enum swizzle_mode_values swizzle,
1413 unsigned int *sw_mode)
1414{
1415 switch (swizzle) {
1416 case DC_SW_LINEAR:
1417 *sw_mode = dm_sw_linear;
1418 break;
1419 case DC_SW_4KB_S:
1420 *sw_mode = dm_sw_4kb_s;
1421 break;
1422 case DC_SW_4KB_S_X:
1423 *sw_mode = dm_sw_4kb_s_x;
1424 break;
1425 case DC_SW_4KB_D:
1426 *sw_mode = dm_sw_4kb_d;
1427 break;
1428 case DC_SW_4KB_D_X:
1429 *sw_mode = dm_sw_4kb_d_x;
1430 break;
1431 case DC_SW_64KB_S:
1432 *sw_mode = dm_sw_64kb_s;
1433 break;
1434 case DC_SW_64KB_S_X:
1435 *sw_mode = dm_sw_64kb_s_x;
1436 break;
1437 case DC_SW_64KB_S_T:
1438 *sw_mode = dm_sw_64kb_s_t;
1439 break;
1440 case DC_SW_64KB_D:
1441 *sw_mode = dm_sw_64kb_d;
1442 break;
1443 case DC_SW_64KB_D_X:
1444 *sw_mode = dm_sw_64kb_d_x;
1445 break;
1446 case DC_SW_64KB_D_T:
1447 *sw_mode = dm_sw_64kb_d_t;
1448 break;
1449 case DC_SW_64KB_R_X:
1450 *sw_mode = dm_sw_64kb_r_x;
1451 break;
1452 case DC_SW_VAR_S:
1453 *sw_mode = dm_sw_var_s;
1454 break;
1455 case DC_SW_VAR_S_X:
1456 *sw_mode = dm_sw_var_s_x;
1457 break;
1458 case DC_SW_VAR_D:
1459 *sw_mode = dm_sw_var_d;
1460 break;
1461 case DC_SW_VAR_D_X:
1462 *sw_mode = dm_sw_var_d_x;
1463 break;
1464
1465 default:
1466 ASSERT(0); /* Not supported */
1467 break;
1468 }
1469}
1470
1471static bool dcn20_split_stream_for_combine(
1472 struct resource_context *res_ctx,
1473 const struct resource_pool *pool,
1474 struct pipe_ctx *primary_pipe,
1475 struct pipe_ctx *secondary_pipe,
1476 bool is_odm_combine)
1477{
1478 int pipe_idx = secondary_pipe->pipe_idx;
1479 struct scaler_data *sd = &primary_pipe->plane_res.scl_data;
1480 struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
1481 int new_width;
1482
1483 *secondary_pipe = *primary_pipe;
1484 secondary_pipe->bottom_pipe = sec_bot_pipe;
1485
1486 secondary_pipe->pipe_idx = pipe_idx;
1487 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
1488 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
1489 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
1490 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
1491 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
1492 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
c92b4c46
NC		 1493#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1494 secondary_pipe->stream_res.dsc = NULL;
1495#endif
7ed4e635
HW		 1496 if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
1497 ASSERT(!secondary_pipe->bottom_pipe);
1498 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
1499 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
1500 }
1501 primary_pipe->bottom_pipe = secondary_pipe;
1502 secondary_pipe->top_pipe = primary_pipe;
1503
1504 if (is_odm_combine) {
7ed4e635
HW		 1505 if (primary_pipe->plane_state) {
1506 /* HACTIVE halved for odm combine */
1507 sd->h_active /= 2;
1508 /* Copy scl_data to secondary pipe */
1509 secondary_pipe->plane_res.scl_data = *sd;
1510
1511 /* Calculate new vp and recout for left pipe */
1512 /* Need at least 16 pixels width per side */
1513 if (sd->recout.x + 16 >= sd->h_active)
1514 return false;
1515 new_width = sd->h_active - sd->recout.x;
1516 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1517 sd->ratios.horz, sd->recout.width - new_width));
1518 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1519 sd->ratios.horz_c, sd->recout.width - new_width));
1520 sd->recout.width = new_width;
1521
1522 /* Calculate new vp and recout for right pipe */
1523 sd = &secondary_pipe->plane_res.scl_data;
1524 new_width = sd->recout.width + sd->recout.x - sd->h_active;
1525 /* Need at least 16 pixels width per side */
1526 if (new_width <= 16)
1527 return false;
1528 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1529 sd->ratios.horz, sd->recout.width - new_width));
1530 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1531 sd->ratios.horz_c, sd->recout.width - new_width));
1532 sd->recout.width = new_width;
1533 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
1534 sd->ratios.horz, sd->h_active - sd->recout.x));
1535 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
1536 sd->ratios.horz_c, sd->h_active - sd->recout.x));
1537 sd->recout.x = 0;
1538 }
1539 secondary_pipe->stream_res.opp = pool->opps[secondary_pipe->pipe_idx];
97bda032 1540#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
c9ae6e16
NC		 1541 if (secondary_pipe->stream->timing.flags.DSC == 1) {
1542 acquire_dsc(res_ctx, pool, &secondary_pipe->stream_res.dsc);
97bda032
HW		 1543 ASSERT(secondary_pipe->stream_res.dsc);
1544 if (secondary_pipe->stream_res.dsc == NULL)
1545 return false;
1546 }
1547#endif
7ed4e635
HW		 1548 } else {
1549 ASSERT(primary_pipe->plane_state);
1550 resource_build_scaling_params(primary_pipe);
1551 resource_build_scaling_params(secondary_pipe);
1552 }
1553
1554 return true;
1555}
1556
1557void dcn20_populate_dml_writeback_from_context(
1558 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1559{
1560 int pipe_cnt, i;
1561
1562 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1563 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];
1564
1565 if (!res_ctx->pipe_ctx[i].stream)
1566 continue;
1567
1568 /* Set writeback information */
1569 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
1570 pipes[pipe_cnt].dout.num_active_wb++;
1571 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
1572 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
1573 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
1574 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
1575 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
1576 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1;
1577 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
1578 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
1579 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0;
1580 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0;
1581 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
1582 if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
1583 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
1584 else
1585 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
1586 } else
1587 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
1588
1589 pipe_cnt++;
1590 }
1591
1592}
1593
1594int dcn20_populate_dml_pipes_from_context(
1595 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1596{
1597 int pipe_cnt, i;
1598 bool synchronized_vblank = true;
1599
1600 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
1601 if (!res_ctx->pipe_ctx[i].stream)
1602 continue;
1603
1604 if (pipe_cnt < 0) {
1605 pipe_cnt = i;
1606 continue;
1607 }
1608 if (!resource_are_streams_timing_synchronizable(
1609 res_ctx->pipe_ctx[pipe_cnt].stream,
1610 res_ctx->pipe_ctx[i].stream)) {
1611 synchronized_vblank = false;
1612 break;
1613 }
1614 }
1615
1616 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1617 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
1618 struct dc_link *link;
1619
1620 if (!res_ctx->pipe_ctx[i].stream)
1621 continue;
1622 /* todo:
1623 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
1624 pipes[pipe_cnt].pipe.src.dcc = 0;
1625 pipes[pipe_cnt].pipe.src.vm = 0;*/
1626
97bda032
HW		 1627#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1628 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
1629 /* todo: rotation?*/
1630 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
1631#endif
7ed4e635
HW		 1632 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
1633 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
1634 /* 1/2 vblank */
1635 pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
1636 (timing->v_total - timing->v_addressable
1637 - timing->v_border_top - timing->v_border_bottom) / 2;
1638 /* 36 bytes dp, 32 hdmi */
1639 pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
1640 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
1641 }
1642 pipes[pipe_cnt].pipe.src.dcc = false;
1643 pipes[pipe_cnt].pipe.src.dcc_rate = 1;
1644 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
1645 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
1646 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
1647 - timing->h_addressable
1648 - timing->h_border_left
1649 - timing->h_border_right;
1650 pipes[pipe_cnt].pipe.dest.vblank_start = timing->v_total - timing->v_front_porch;
1651 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
1652 - timing->v_addressable
1653 - timing->v_border_top
1654 - timing->v_border_bottom;
1655 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
1656 pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total;
1657 pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable;
1658 pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable;
1659 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
1660 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
1661 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1662 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
1663 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
1664
1665 link = res_ctx->pipe_ctx[i].stream->link;
1666 if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) {
1667 pipes[pipe_cnt].dout.dp_lanes = link->cur_link_settings.lane_count;
1668 } else if (link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN) {
1669 pipes[pipe_cnt].dout.dp_lanes = link->verified_link_cap.lane_count;
1670 } else {
1671 /* Unknown link capabilities, so assume max */
1672 pipes[pipe_cnt].dout.dp_lanes = 4;
1673 }
8bb3d7e7
CL		 1674 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
1675 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
7ed4e635
HW		 1676
1677 pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.display_color_depth;
1678 switch (res_ctx->pipe_ctx[i].stream->signal) {
1679 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1680 case SIGNAL_TYPE_DISPLAY_PORT:
1681 pipes[pipe_cnt].dout.output_type = dm_dp;
1682 break;
1683 case SIGNAL_TYPE_EDP:
1684 pipes[pipe_cnt].dout.output_type = dm_edp;
1685 break;
1686 case SIGNAL_TYPE_HDMI_TYPE_A:
1687 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1688 case SIGNAL_TYPE_DVI_DUAL_LINK:
1689 pipes[pipe_cnt].dout.output_type = dm_hdmi;
1690 break;
1691 default:
1692 /* In case there is no signal, set dp with 4 lanes to allow max config */
1693 pipes[pipe_cnt].dout.output_type = dm_dp;
1694 pipes[pipe_cnt].dout.dp_lanes = 4;
1695 }
1696 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
1697 case PIXEL_ENCODING_RGB:
1698 case PIXEL_ENCODING_YCBCR444:
1699 pipes[pipe_cnt].dout.output_format = dm_444;
1700 break;
1701 case PIXEL_ENCODING_YCBCR420:
1702 pipes[pipe_cnt].dout.output_format = dm_420;
1703 break;
1704 case PIXEL_ENCODING_YCBCR422:
1705 if (true) /* todo */
1706 pipes[pipe_cnt].dout.output_format = dm_s422;
1707 else
1708 pipes[pipe_cnt].dout.output_format = dm_n422;
1709 break;
1710 default:
1711 pipes[pipe_cnt].dout.output_format = dm_444;
1712 }
1713 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1714 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
1715 == res_ctx->pipe_ctx[i].plane_state)
1716 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
1717
1718 /* todo: default max for now, until there is logic reflecting this in dc*/
1719 pipes[pipe_cnt].dout.output_bpc = 12;
1720 /*
1721 * Use max cursor settings for calculations to minimize
1722 * bw calculations due to cursor on/off
1723 */
1724 pipes[pipe_cnt].pipe.src.num_cursors = 2;
ed07237c
IB		 1725 pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
1726 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
1727 pipes[pipe_cnt].pipe.src.cur1_src_width = 256;
1728 pipes[pipe_cnt].pipe.src.cur1_bpp = dm_cur_32bit;
7ed4e635
HW		 1729
1730 if (!res_ctx->pipe_ctx[i].plane_state) {
1731 pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
1732 pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear;
1733 pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
1734 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
1735 if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
1736 pipes[pipe_cnt].pipe.src.viewport_width = 1920;
1737 pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
1738 if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
1739 pipes[pipe_cnt].pipe.src.viewport_height = 1080;
1740 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */
1741 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
1742 pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
1743 pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/
1744 pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_hsplit != 1*/
1745 pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/
1746 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
1747 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
1748 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
1749 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
1750 pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
1751 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
1752 pipes[pipe_cnt].pipe.src.is_hsplit = 0;
1753 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
8bb3d7e7
CL		 1754 pipes[pipe_cnt].pipe.dest.vtotal_min = timing->v_total;
1755 pipes[pipe_cnt].pipe.dest.vtotal_max = timing->v_total;
7ed4e635
HW		 1756 } else {
1757 struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
1758 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
1759
7ed4e635
HW		 1760 pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
1761 pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe
1762 && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
1763 || (res_ctx->pipe_ctx[i].top_pipe
1764 && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln);
1765 pipes[pipe_cnt].pipe.dest.odm_combine = (res_ctx->pipe_ctx[i].bottom_pipe
1766 && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln
1767 && res_ctx->pipe_ctx[i].bottom_pipe->stream_res.opp
1768 != res_ctx->pipe_ctx[i].stream_res.opp)
1769 || (res_ctx->pipe_ctx[i].top_pipe
1770 && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln
1771 && res_ctx->pipe_ctx[i].top_pipe->stream_res.opp
1772 != res_ctx->pipe_ctx[i].stream_res.opp);
1773 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
1774 || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
1775 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
1776 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
1777 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
1778 pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
1779 pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
1780 pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
1781 if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1782 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.video.luma_pitch;
1783 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.video.chroma_pitch;
1784 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.video.meta_pitch_l;
1785 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.video.meta_pitch_c;
1786 } else {
1787 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.grph.surface_pitch;
1788 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.grph.meta_pitch;
1789 }
1790 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
1791 pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
1792 pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
1793 pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
1794 pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
1795 if (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) {
1796 pipes[pipe_cnt].pipe.dest.full_recout_width +=
1797 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.width;
1798 pipes[pipe_cnt].pipe.dest.full_recout_height +=
1799 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.height;
1800 } else if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) {
1801 pipes[pipe_cnt].pipe.dest.full_recout_width +=
1802 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.width;
1803 pipes[pipe_cnt].pipe.dest.full_recout_height +=
1804 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.height;
1805 }
1806
ed07237c 1807 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
7ed4e635
HW		 1808 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
1809 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
1810 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
1811 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
1812 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
1813 scl->ratios.vert.value != dc_fixpt_one.value
1814 || scl->ratios.horz.value != dc_fixpt_one.value
1815 || scl->ratios.vert_c.value != dc_fixpt_one.value
1816 || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/
1817 || dc->debug.always_scale; /*support always scale*/
1818 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
1819 pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
1820 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
1821 pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
1822
b964e790
DL		 1823 pipes[pipe_cnt].pipe.src.macro_tile_size =
1824 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
7ed4e635
HW		 1825 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
1826 &pipes[pipe_cnt].pipe.src.sw_mode);
1827
1828 switch (pln->format) {
1829 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
1830 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
1831 pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
1832 break;
1833 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
1834 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
1835 pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
1836 break;
1837 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1838 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1839 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1840 pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
1841 break;
1842 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
1843 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
1844 pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
1845 break;
1846 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
1847 pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
1848 break;
1849 default:
1850 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
1851 break;
1852 }
1853 }
1854
1855 pipe_cnt++;
1856 }
1857
1858 /* populate writeback information */
1859 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
1860
1861 return pipe_cnt;
1862}
1863
1864unsigned int dcn20_calc_max_scaled_time(
1865 unsigned int time_per_pixel,
1866 enum mmhubbub_wbif_mode mode,
1867 unsigned int urgent_watermark)
1868{
1869 unsigned int time_per_byte = 0;
1870 unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */
1871 unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */
1872 unsigned int small_free_entry, max_free_entry;
1873 unsigned int buf_lh_capability;
1874 unsigned int max_scaled_time;
1875
1876 if (mode == PACKED_444) /* packed mode */
1877 time_per_byte = time_per_pixel/4;
1878 else if (mode == PLANAR_420_8BPC)
1879 time_per_byte = time_per_pixel;
1880 else if (mode == PLANAR_420_10BPC) /* p010 */
1881 time_per_byte = time_per_pixel * 819/1024;
1882
1883 if (time_per_byte == 0)
1884 time_per_byte = 1;
1885
1886 small_free_entry = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry;
1887 max_free_entry = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;
1888 buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */
1889 max_scaled_time = buf_lh_capability - urgent_watermark;
1890 return max_scaled_time;
1891}
1892
1893void dcn20_set_mcif_arb_params(
1894 struct dc *dc,
1895 struct dc_state *context,
1896 display_e2e_pipe_params_st *pipes,
1897 int pipe_cnt)
1898{
1899 enum mmhubbub_wbif_mode wbif_mode;
1900 struct mcif_arb_params *wb_arb_params;
1901 int i, j, k, dwb_pipe;
1902
1903 /* Writeback MCIF_WB arbitration parameters */
1904 dwb_pipe = 0;
1905 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1906
1907 if (!context->res_ctx.pipe_ctx[i].stream)
1908 continue;
1909
1910 for (j = 0; j < MAX_DWB_PIPES; j++) {
1911 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)
1912 continue;
1913
1914 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
1915 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
1916
1917 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {
1918 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
1919 wbif_mode = PLANAR_420_8BPC;
1920 else
1921 wbif_mode = PLANAR_420_10BPC;
1922 } else
1923 wbif_mode = PACKED_444;
1924
1925 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
1926 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1927 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1928 }
1929 wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* 4 bit fraction, ms */
1930 wb_arb_params->slice_lines = 32;
1931 wb_arb_params->arbitration_slice = 2;
1932 wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
1933 wbif_mode,
1934 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
1935
1936 dwb_pipe++;
1937
1938 if (dwb_pipe >= MAX_DWB_PIPES)
1939 return;
1940 }
1941 if (dwb_pipe >= MAX_DWB_PIPES)
1942 return;
1943 }
1944}
1945
0ba37b20
DL		 1946#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1947static bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
1948{
1949 int i;
1950
1951 /* Validate DSC config, dsc count validation is already done */
1952 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1953 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1954 struct dc_stream_state *stream = pipe_ctx->stream;
1955 struct dsc_config dsc_cfg;
1956
1957 /* Only need to validate top pipe */
1958 if (pipe_ctx->top_pipe || !stream || !stream->timing.flags.DSC)
1959 continue;
1960
1961 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left
1962 + stream->timing.h_border_right;
1963 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
1964 + stream->timing.v_border_bottom;
1965 if (dc_res_get_odm_bottom_pipe(pipe_ctx))
1966 dsc_cfg.pic_width /= 2;
1967 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
1968 dsc_cfg.color_depth = stream->timing.display_color_depth;
1969 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
1970
1971 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
1972 return false;
1973 }
1974 return true;
1975}
1976#endif
1977
254eb07c
JA		 1978bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
1979 bool fast_validate)
7ed4e635 1980{
254eb07c
JA		 1981 bool out = false;
1982
42351c66
JA		 1983 BW_VAL_TRACE_SETUP();
1984
7ed4e635
HW		 1985 int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit;
1986 int pipe_split_from[MAX_PIPES];
1987 bool odm_capable = context->bw_ctx.dml.ip.odm_capable;
1988 bool force_split = false;
0ba37b20
DL		 1989#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1990 bool failed_non_odm_dsc = false;
1991#endif
7ed4e635
HW		 1992 int split_threshold = dc->res_pool->pipe_count / 2;
1993 bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
1994 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
00999d99 1995 DC_LOGGER_INIT(dc->ctx->logger);
7ed4e635 1996
42351c66
JA		 1997 BW_VAL_TRACE_COUNT();
1998
7ed4e635
HW		 1999 ASSERT(pipes);
2000 if (!pipes)
2001 return false;
2002
2003 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2004 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2005 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2006
2007 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
2008 continue;
2009
2010 /* merge previously split pipe since mode support needs to make the decision */
2011 pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
2012 if (hsplit_pipe->bottom_pipe)
2013 hsplit_pipe->bottom_pipe->top_pipe = pipe;
2014 hsplit_pipe->plane_state = NULL;
2015 hsplit_pipe->stream = NULL;
2016 hsplit_pipe->top_pipe = NULL;
2017 hsplit_pipe->bottom_pipe = NULL;
97bda032
HW		 2018#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2019 if (hsplit_pipe->stream_res.dsc && hsplit_pipe->stream_res.dsc != pipe->stream_res.dsc)
c9ae6e16 2020 release_dsc(&context->res_ctx, dc->res_pool, &hsplit_pipe->stream_res.dsc);
97bda032 2021#endif
7ed4e635
HW		 2022 /* Clear plane_res and stream_res */
2023 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
2024 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
2025 if (pipe->plane_state)
2026 resource_build_scaling_params(pipe);
2027 }
2028
ed07237c
IB		 2029 if (dc->res_pool->funcs->populate_dml_pipes)
2030 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2031 &context->res_ctx, pipes);
2032 else
2033 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
2034 &context->res_ctx, pipes);
254eb07c
JA		 2035
2036 if (!pipe_cnt) {
42351c66 2037 BW_VAL_TRACE_SKIP(pass);
254eb07c
JA		 2038 out = true;
2039 goto validate_out;
2040 }
7ed4e635
HW		 2041
2042 context->bw_ctx.dml.ip.odm_capable = 0;
254eb07c 2043
7ed4e635 2044 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
254eb07c 2045
7ed4e635
HW		 2046 context->bw_ctx.dml.ip.odm_capable = odm_capable;
2047
0ba37b20
DL		 2048#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2049 /* 1 dsc per stream dsc validation */
2050 if (vlevel <= context->bw_ctx.dml.soc.num_states)
2051 if (!dcn20_validate_dsc(dc, context)) {
2052 failed_non_odm_dsc = true;
2053 vlevel = context->bw_ctx.dml.soc.num_states + 1;
2054 }
2055#endif
2056
7ed4e635
HW		 2057 if (vlevel > context->bw_ctx.dml.soc.num_states && odm_capable)
2058 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2059
2060 if (vlevel > context->bw_ctx.dml.soc.num_states)
2061 goto validate_fail;
2062
2063 if ((context->stream_count > split_threshold && dc->current_state->stream_count <= split_threshold)
2064 || (context->stream_count <= split_threshold && dc->current_state->stream_count > split_threshold))
2065 context->commit_hints.full_update_needed = true;
2066
2067 /*initialize pipe_just_split_from to invalid idx*/
2068 for (i = 0; i < MAX_PIPES; i++)
2069 pipe_split_from[i] = -1;
2070
2071 /* Single display only conditionals get set here */
2072 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2073 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2074 bool exit_loop = false;
2075
2076 if (!pipe->stream || pipe->top_pipe)
2077 continue;
2078
2079 if (dc->debug.force_single_disp_pipe_split) {
2080 if (!force_split)
2081 force_split = true;
2082 else {
2083 force_split = false;
2084 exit_loop = true;
2085 }
2086 }
2087 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP) {
2088 if (avoid_split)
2089 avoid_split = false;
2090 else {
2091 avoid_split = true;
2092 exit_loop = true;
2093 }
2094 }
2095 if (exit_loop)
2096 break;
2097 }
2098
2099 if (context->stream_count > split_threshold)
2100 avoid_split = true;
2101
2102 vlevel_unsplit = vlevel;
2103 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2104 if (!context->res_ctx.pipe_ctx[i].stream)
2105 continue;
2106 for (; vlevel_unsplit <= context->bw_ctx.dml.soc.num_states; vlevel_unsplit++)
2107 if (context->bw_ctx.dml.vba.NoOfDPP[vlevel_unsplit][0][pipe_idx] == 1)
2108 break;
2109 pipe_idx++;
2110 }
2111
2112 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2113 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2114 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2115 bool need_split = true;
2116 bool need_split3d;
2117
2118 if (!pipe->stream || pipe_split_from[i] >= 0)
2119 continue;
2120
2121 pipe_idx++;
2122
2123 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
2124 force_split = true;
2125 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx] = true;
2126 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = true;
2127 }
2128 if (force_split && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)
2129 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
2130
2131 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2132 hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, dc->res_pool, pipe);
2133 ASSERT(hsplit_pipe);
2134 if (!dcn20_split_stream_for_combine(
2135 &context->res_ctx, dc->res_pool,
2136 pipe, hsplit_pipe,
2137 true))
2138 goto validate_fail;
2139 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2140 dcn20_build_mapped_resource(dc, context, pipe->stream);
2141 }
2142
2143 if (!pipe->plane_state)
2144 continue;
2145 /* Skip 2nd half of already split pipe */
2146 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
2147 continue;
2148
2149 need_split3d = ((pipe->stream->view_format ==
2150 VIEW_3D_FORMAT_SIDE_BY_SIDE ||
2151 pipe->stream->view_format ==
2152 VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
2153 (pipe->stream->timing.timing_3d_format ==
2154 TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
2155 pipe->stream->timing.timing_3d_format ==
2156 TIMING_3D_FORMAT_SIDE_BY_SIDE));
2157
2158 if (avoid_split && vlevel_unsplit <= context->bw_ctx.dml.soc.num_states && !force_split && !need_split3d) {
2159 need_split = false;
2160 vlevel = vlevel_unsplit;
2161 context->bw_ctx.dml.vba.maxMpcComb = 0;
2162 } else
be67de35 2163 need_split = context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 2;
7ed4e635 2164
02ce5a79
DL		 2165 /* We do not support mpo + odm at the moment */
2166 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
2167 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
2168 goto validate_fail;
2169
7ed4e635
HW		 2170 if (need_split3d || need_split || force_split) {
2171 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
2172 /* pipe not split previously needs split */
2173 hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, dc->res_pool, pipe);
2174 ASSERT(hsplit_pipe || force_split);
2175 if (!hsplit_pipe)
2176 continue;
2177
2178 if (!dcn20_split_stream_for_combine(
2179 &context->res_ctx, dc->res_pool,
2180 pipe, hsplit_pipe,
2181 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]))
2182 goto validate_fail;
2183 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2184 }
02ce5a79 2185 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
7ed4e635
HW		 2186 /* merge should already have been done */
2187 ASSERT(0);
2188 }
2189 }
0ba37b20
DL		 2190#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2191 /* Actual dsc count per stream dsc validation*/
2192 if (failed_non_odm_dsc && !dcn20_validate_dsc(dc, context)) {
2193 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2194 DML_FAIL_DSC_VALIDATION_FAILURE;
2195 goto validate_fail;
2196 }
2197#endif
7ed4e635 2198
42351c66
JA		 2199 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2200
254eb07c 2201 if (fast_validate) {
42351c66 2202 BW_VAL_TRACE_SKIP(fast);
254eb07c
JA		 2203 out = true;
2204 goto validate_out;
2205 }
2206
7ed4e635
HW		 2207 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2208 if (!context->res_ctx.pipe_ctx[i].stream)
2209 continue;
2210
2211 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2212 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2213
2214 if (pipe_split_from[i] < 0) {
2215 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2216 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
2217 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
2218 pipes[pipe_cnt].pipe.dest.odm_combine =
2219 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
2220 else
2221 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2222 pipe_idx++;
2223 } else {
2224 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2225 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
2226 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
2227 pipes[pipe_cnt].pipe.dest.odm_combine =
2228 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_split_from[i]];
2229 else
2230 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2231 }
2232 pipe_cnt++;
2233 }
2234
ed07237c
IB		 2235 if (pipe_cnt != pipe_idx) {
2236 if (dc->res_pool->funcs->populate_dml_pipes)
2237 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2238 &context->res_ctx, pipes);
2239 else
2240 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
2241 &context->res_ctx, pipes);
2242 }
7ed4e635 2243
8e27a2d4
IB		 2244 pipes[0].clks_cfg.voltage = vlevel;
2245 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2246 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2247
7ed4e635
HW		 2248 /* only pipe 0 is read for voltage and dcf/soc clocks */
2249 if (vlevel < 1) {
2250 pipes[0].clks_cfg.voltage = 1;
2251 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
2252 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
2253 }
2254 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2255 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2256 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2257 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2258 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2259
2260 if (vlevel < 2) {
2261 pipes[0].clks_cfg.voltage = 2;
2262 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2263 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2264 }
2265 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2266 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2267 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2268 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2269 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2270
2271 if (vlevel < 3) {
2272 pipes[0].clks_cfg.voltage = 3;
2273 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2274 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2275 }
2276 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2277 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2278 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2279 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2280 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2281
2282 pipes[0].clks_cfg.voltage = vlevel;
2283 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2284 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2285 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2286 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2287 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2288 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2289 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2290 /* Writeback MCIF_WB arbitration parameters */
2291 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
2292
2293 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
2294 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
2295 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
173932de 2296 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
7ed4e635
HW		 2297 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
2298 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
2299 context->bw_ctx.bw.dcn.clk.p_state_change_support =
2300 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
2301 != dm_dram_clock_change_unsupported;
2302 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
2303
42351c66
JA		 2304 BW_VAL_TRACE_END_WATERMARKS();
2305
7ed4e635
HW		 2306 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2307 if (!context->res_ctx.pipe_ctx[i].stream)
2308 continue;
2309 pipes[pipe_idx].pipe.dest.vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx];
2310 pipes[pipe_idx].pipe.dest.vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx];
2311 pipes[pipe_idx].pipe.dest.vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx];
2312 pipes[pipe_idx].pipe.dest.vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx];
2313 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2314 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
2315 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
2316 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
97bda032 2317#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
b7d39c58 2318 context->res_ctx.pipe_ctx[i].stream_res.dscclk_khz =
97bda032
HW		 2319 context->bw_ctx.dml.vba.DSCCLK_calculated[pipe_idx] * 1000;
2320#endif
7ed4e635
HW		 2321 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
2322 pipe_idx++;
2323 }
2324
2325 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2326 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
2327
2328 if (!context->res_ctx.pipe_ctx[i].stream)
2329 continue;
2330
2331 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
2332 &context->res_ctx.pipe_ctx[i].dlg_regs,
2333 &context->res_ctx.pipe_ctx[i].ttu_regs,
2334 pipes,
2335 pipe_cnt,
2336 pipe_idx,
2337 cstate_en,
2338 context->bw_ctx.bw.dcn.clk.p_state_change_support);
254eb07c 2339
7ed4e635
HW		 2340 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
2341 &context->res_ctx.pipe_ctx[i].rq_regs,
2342 pipes[pipe_idx].pipe);
2343 pipe_idx++;
2344 }
2345
254eb07c
JA		 2346 out = true;
2347 goto validate_out;
7ed4e635
HW		 2348
2349validate_fail:
00999d99
DL		 2350 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2351 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
254eb07c 2352
42351c66 2353 BW_VAL_TRACE_SKIP(fail);
254eb07c
JA		 2354 out = false;
2355
2356validate_out:
7ed4e635 2357 kfree(pipes);
254eb07c 2358
42351c66
JA		 2359 BW_VAL_TRACE_FINISH();
2360
254eb07c 2361 return out;
7ed4e635
HW		 2362}
2363
7ed4e635
HW		 2364struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
2365 struct dc_state *state,
2366 const struct resource_pool *pool,
2367 struct dc_stream_state *stream)
2368{
2369 struct resource_context *res_ctx = &state->res_ctx;
2370 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
2371 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
2372
2373 if (!head_pipe)
2374 ASSERT(0);
2375
2376 if (!idle_pipe)
2377 return false;
2378
2379 idle_pipe->stream = head_pipe->stream;
2380 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
2381 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
2382
2383 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
2384 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
2385 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
2386 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
2387
2388 return idle_pipe;
2389}
2390
2391bool dcn20_get_dcc_compression_cap(const struct dc *dc,
2392 const struct dc_dcc_surface_param *input,
2393 struct dc_surface_dcc_cap *output)
2394{
2395 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
2396 dc->res_pool->hubbub,
2397 input,
2398 output);
2399}
2400
2401static void dcn20_destroy_resource_pool(struct resource_pool **pool)
2402{
2403 struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);
2404
2405 destruct(dcn20_pool);
2406 kfree(dcn20_pool);
2407 *pool = NULL;
2408}
2409
2410
2411static struct dc_cap_funcs cap_funcs = {
2412 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
2413};
2414
2415
2416enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state)
2417{
2418 enum dc_status result = DC_OK;
2419
2420 enum surface_pixel_format surf_pix_format = plane_state->format;
2421 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
2422
2423 enum swizzle_mode_values swizzle = DC_SW_LINEAR;
2424
2425 if (bpp == 64)
2426 swizzle = DC_SW_64KB_D;
2427 else
2428 swizzle = DC_SW_64KB_S;
2429
2430 plane_state->tiling_info.gfx9.swizzle = swizzle;
2431 return result;
2432}
2433
2434static struct resource_funcs dcn20_res_pool_funcs = {
2435 .destroy = dcn20_destroy_resource_pool,
2436 .link_enc_create = dcn20_link_encoder_create,
2437 .validate_bandwidth = dcn20_validate_bandwidth,
7ed4e635
HW		 2438 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
2439 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
2440 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2441 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
2442 .get_default_swizzle_mode = dcn20_get_default_swizzle_mode,
c9ae6e16
NC		 2443 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
2444#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2445 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2446 .remove_dsc_from_stream_resource = dcn20_remove_dsc_from_stream_resource
2447#endif
7ed4e635
HW		 2448};
2449
bb21290f
CL		 2450bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
2451{
2452 int i;
2453 uint32_t pipe_count = pool->res_cap->num_dwb;
2454
2455 ASSERT(pipe_count > 0);
2456
2457 for (i = 0; i < pipe_count; i++) {
2458 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
2459 GFP_KERNEL);
2460
2461 if (!dwbc20) {
2462 dm_error("DC: failed to create dwbc20!\n");
2463 return false;
2464 }
2465 dcn20_dwbc_construct(dwbc20, ctx,
2466 &dwbc20_regs[i],
2467 &dwbc20_shift,
2468 &dwbc20_mask,
2469 i);
2470 pool->dwbc[i] = &dwbc20->base;
2471 }
2472 return true;
2473}
2474
2475bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
2476{
2477 int i;
2478 uint32_t pipe_count = pool->res_cap->num_dwb;
2479
2480 ASSERT(pipe_count > 0);
2481
2482 for (i = 0; i < pipe_count; i++) {
2483 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub),
2484 GFP_KERNEL);
2485
2486 if (!mcif_wb20) {
2487 dm_error("DC: failed to create mcif_wb20!\n");
2488 return false;
2489 }
2490
2491 dcn20_mmhubbub_construct(mcif_wb20, ctx,
2492 &mcif_wb20_regs[i],
2493 &mcif_wb20_shift,
2494 &mcif_wb20_mask,
2495 i);
2496
2497 pool->mcif_wb[i] = &mcif_wb20->base;
2498 }
2499 return true;
2500}
2501
7ed4e635
HW		 2502struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
2503{
2504 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
2505
2506 if (!pp_smu)
2507 return pp_smu;
2508
2509 dm_pp_get_funcs(ctx, pp_smu);
2510
2511 if (pp_smu->ctx.ver != PP_SMU_VER_NV)
2512 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
2513
2514 return pp_smu;
2515}
2516
2517void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
2518{
2519 if (pp_smu && *pp_smu) {
2520 kfree(*pp_smu);
2521 *pp_smu = NULL;
2522 }
2523}
2524
2525static void cap_soc_clocks(
2526 struct _vcs_dpi_soc_bounding_box_st *bb,
2527 struct pp_smu_nv_clock_table max_clocks)
2528{
2529 int i;
2530
2531 // First pass - cap all clocks higher than the reported max
2532 for (i = 0; i < bb->num_states; i++) {
2533 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
2534 && max_clocks.dcfClockInKhz != 0)
2535 bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
2536
2537 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
2538 && max_clocks.uClockInKhz != 0)
2539 bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
2540
2541 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
2542 && max_clocks.fabricClockInKhz != 0)
2543 bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
2544
2545 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
2546 && max_clocks.displayClockInKhz != 0)
2547 bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
2548
2549 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
2550 && max_clocks.dppClockInKhz != 0)
2551 bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
2552
2553 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
2554 && max_clocks.phyClockInKhz != 0)
2555 bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
2556
2557 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
2558 && max_clocks.socClockInKhz != 0)
2559 bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
2560
2561 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
2562 && max_clocks.dscClockInKhz != 0)
2563 bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
2564 }
2565
2566 // Second pass - remove all duplicate clock states
2567 for (i = bb->num_states - 1; i > 1; i--) {
2568 bool duplicate = true;
2569
2570 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz)
2571 duplicate = false;
2572 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz)
2573 duplicate = false;
2574 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz)
2575 duplicate = false;
2576 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts)
2577 duplicate = false;
2578 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz)
2579 duplicate = false;
2580 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz)
2581 duplicate = false;
2582 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz)
2583 duplicate = false;
2584 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz)
2585 duplicate = false;
2586
2587 if (duplicate)
2588 bb->num_states--;
2589 }
2590}
2591
2592static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
2593 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
2594{
2595 struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES] = {0};
f18bc4e5 2596 int i;
7ed4e635 2597 int num_calculated_states = 0;
f18bc4e5 2598 int min_dcfclk = 0;
7ed4e635
HW		 2599
2600 if (num_states == 0)
2601 return;
2602
f18bc4e5
JL		 2603 if (dc->bb_overrides.min_dcfclk_mhz > 0)
2604 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
2605
7ed4e635 2606 for (i = 0; i < num_states; i++) {
f18bc4e5
JL		 2607 int min_fclk_required_by_uclk;
2608 calculated_states[i].state = i;
2609 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
7ed4e635 2610
f18bc4e5 2611 min_fclk_required_by_uclk = ((unsigned long long)uclk_states[i]) * 1008 / 1000000;
7ed4e635 2612
f18bc4e5
JL		 2613 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
2614 min_dcfclk : min_fclk_required_by_uclk;
7ed4e635 2615
f18bc4e5
JL		 2616 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
2617 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
7ed4e635 2618
f18bc4e5
JL		 2619 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
2620 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
7ed4e635 2621
f18bc4e5
JL		 2622 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
2623 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
2624 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
7ed4e635 2625
f18bc4e5 2626 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
7ed4e635 2627
f18bc4e5 2628 num_calculated_states++;
7ed4e635
HW		 2629 }
2630
7ed4e635
HW		 2631 memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
2632 bb->num_states = num_calculated_states;
f18bc4e5
JL		 2633
2634 // Duplicate the last state, DML always an extra state identical to max state to work
2635 memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st));
2636 bb->clock_limits[num_calculated_states].state = bb->num_states;
7ed4e635
HW		 2637}
2638
2639static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
2640{
2641 kernel_fpu_begin();
2642 if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
2643 && dc->bb_overrides.sr_exit_time_ns) {
2644 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
2645 }
2646
2647 if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
2648 != dc->bb_overrides.sr_enter_plus_exit_time_ns
2649 && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
2650 bb->sr_enter_plus_exit_time_us =
2651 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
2652 }
2653
2654 if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
2655 && dc->bb_overrides.urgent_latency_ns) {
2656 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
2657 }
2658
2659 if ((int)(bb->dram_clock_change_latency_us * 1000)
2660 != dc->bb_overrides.dram_clock_change_latency_ns
2661 && dc->bb_overrides.dram_clock_change_latency_ns) {
2662 bb->dram_clock_change_latency_us =
2663 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
2664 }
2665 kernel_fpu_end();
2666}
2667
2668#define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
2669#define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
2670
2671static bool init_soc_bounding_box(struct dc *dc,
2672 struct dcn20_resource_pool *pool)
2673{
2674 const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
2675 DC_LOGGER_INIT(dc->ctx->logger);
2676
2677 if (!bb && !SOC_BOUNDING_BOX_VALID) {
2678 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
2679 return false;
2680 }
2681
2682 if (bb && !SOC_BOUNDING_BOX_VALID) {
2683 int i;
2684
2685 dcn2_0_soc.sr_exit_time_us =
2686 fixed16_to_double_to_cpu(bb->sr_exit_time_us);
2687 dcn2_0_soc.sr_enter_plus_exit_time_us =
2688 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us);
2689 dcn2_0_soc.urgent_latency_us =
2690 fixed16_to_double_to_cpu(bb->urgent_latency_us);
2691 dcn2_0_soc.urgent_latency_pixel_data_only_us =
2692 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us);
2693 dcn2_0_soc.urgent_latency_pixel_mixed_with_vm_data_us =
2694 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us);
2695 dcn2_0_soc.urgent_latency_vm_data_only_us =
2696 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us);
2697 dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
2698 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes);
2699 dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
2700 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes);
2701 dcn2_0_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
2702 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes);
2703 dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
2704 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only);
2705 dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
2706 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm);
2707 dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
2708 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only);
2709 dcn2_0_soc.max_avg_sdp_bw_use_normal_percent =
2710 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent);
2711 dcn2_0_soc.max_avg_dram_bw_use_normal_percent =
2712 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent);
2713 dcn2_0_soc.writeback_latency_us =
2714 fixed16_to_double_to_cpu(bb->writeback_latency_us);
2715 dcn2_0_soc.ideal_dram_bw_after_urgent_percent =
2716 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent);
2717 dcn2_0_soc.max_request_size_bytes =
2718 le32_to_cpu(bb->max_request_size_bytes);
2719 dcn2_0_soc.dram_channel_width_bytes =
2720 le32_to_cpu(bb->dram_channel_width_bytes);
2721 dcn2_0_soc.fabric_datapath_to_dcn_data_return_bytes =
2722 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes);
2723 dcn2_0_soc.dcn_downspread_percent =
2724 fixed16_to_double_to_cpu(bb->dcn_downspread_percent);
2725 dcn2_0_soc.downspread_percent =
2726 fixed16_to_double_to_cpu(bb->downspread_percent);
2727 dcn2_0_soc.dram_page_open_time_ns =
2728 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns);
2729 dcn2_0_soc.dram_rw_turnaround_time_ns =
2730 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns);
2731 dcn2_0_soc.dram_return_buffer_per_channel_bytes =
2732 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes);
2733 dcn2_0_soc.round_trip_ping_latency_dcfclk_cycles =
2734 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles);
2735 dcn2_0_soc.urgent_out_of_order_return_per_channel_bytes =
2736 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes);
2737 dcn2_0_soc.channel_interleave_bytes =
2738 le32_to_cpu(bb->channel_interleave_bytes);
2739 dcn2_0_soc.num_banks =
2740 le32_to_cpu(bb->num_banks);
2741 dcn2_0_soc.num_chans =
2742 le32_to_cpu(bb->num_chans);
2743 dcn2_0_soc.vmm_page_size_bytes =
2744 le32_to_cpu(bb->vmm_page_size_bytes);
2745 dcn2_0_soc.dram_clock_change_latency_us =
2746 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
2747 dcn2_0_soc.writeback_dram_clock_change_latency_us =
2748 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
2749 dcn2_0_soc.return_bus_width_bytes =
2750 le32_to_cpu(bb->return_bus_width_bytes);
2751 dcn2_0_soc.dispclk_dppclk_vco_speed_mhz =
2752 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz);
2753 dcn2_0_soc.xfc_bus_transport_time_us =
2754 le32_to_cpu(bb->xfc_bus_transport_time_us);
2755 dcn2_0_soc.xfc_xbuf_latency_tolerance_us =
2756 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us);
2757 dcn2_0_soc.use_urgent_burst_bw =
2758 le32_to_cpu(bb->use_urgent_burst_bw);
2759 dcn2_0_soc.num_states =
2760 le32_to_cpu(bb->num_states);
2761
2762 for (i = 0; i < dcn2_0_soc.num_states; i++) {
2763 dcn2_0_soc.clock_limits[i].state =
2764 le32_to_cpu(bb->clock_limits[i].state);
2765 dcn2_0_soc.clock_limits[i].dcfclk_mhz =
2766 fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz);
2767 dcn2_0_soc.clock_limits[i].fabricclk_mhz =
2768 fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz);
2769 dcn2_0_soc.clock_limits[i].dispclk_mhz =
2770 fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz);
2771 dcn2_0_soc.clock_limits[i].dppclk_mhz =
2772 fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz);
2773 dcn2_0_soc.clock_limits[i].phyclk_mhz =
2774 fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz);
2775 dcn2_0_soc.clock_limits[i].socclk_mhz =
2776 fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz);
2777 dcn2_0_soc.clock_limits[i].dscclk_mhz =
2778 fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz);
2779 dcn2_0_soc.clock_limits[i].dram_speed_mts =
2780 fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
2781 }
2782 }
2783
2784 if (pool->base.pp_smu) {
2785 struct pp_smu_nv_clock_table max_clocks = {0};
2786 unsigned int uclk_states[8] = {0};
2787 unsigned int num_states = 0;
2788 enum pp_smu_status status;
2789 bool clock_limits_available = false;
2790 bool uclk_states_available = false;
2791
2792 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
2793 status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
2794 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
2795
2796 uclk_states_available = (status == PP_SMU_RESULT_OK);
2797 }
2798
2799 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
2800 status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
2801 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
c2ad17c3
AW		 2802 /* SMU cannot set DCF clock to anything equal to or higher than SOC clock
2803 */
2804 if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
2805 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
7ed4e635
HW		 2806 clock_limits_available = (status == PP_SMU_RESULT_OK);
2807 }
2808
c2ad17c3 2809 if (clock_limits_available && uclk_states_available && num_states)
7ed4e635
HW		 2810 update_bounding_box(dc, &dcn2_0_soc, &max_clocks, uclk_states, num_states);
2811 else if (clock_limits_available)
2812 cap_soc_clocks(&dcn2_0_soc, max_clocks);
2813 }
2814
2815 dcn2_0_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
2816 dcn2_0_ip.max_num_dpp = pool->base.pipe_count;
2817 patch_bounding_box(dc, &dcn2_0_soc);
2818
2819 return true;
2820}
2821
2822static bool construct(
2823 uint8_t num_virtual_links,
2824 struct dc *dc,
2825 struct dcn20_resource_pool *pool)
2826{
2827 int i;
2828 struct dc_context *ctx = dc->ctx;
2829 struct irq_service_init_data init_data;
2830
2831 ctx->dc_bios->regs = &bios_regs;
2832
2833 pool->base.res_cap = &res_cap_nv10;
2834 pool->base.funcs = &dcn20_res_pool_funcs;
2835
2836 /*************************************************
2837 * Resource + asic cap harcoding *
2838 *************************************************/
2839 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2840
2841 pool->base.pipe_count = 6;
2842 pool->base.mpcc_count = 6;
2843 dc->caps.max_downscale_ratio = 200;
2844 dc->caps.i2c_speed_in_khz = 100;
2845 dc->caps.max_cursor_size = 256;
2846 dc->caps.dmdata_alloc_size = 2048;
2847
2848 dc->caps.max_slave_planes = 1;
2849 dc->caps.post_blend_color_processing = true;
2850 dc->caps.force_dp_tps4_for_cp2520 = true;
2851 dc->caps.hw_3d_lut = true;
2852
2853 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2854 dc->debug = debug_defaults_drv;
2855 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2856 pool->base.pipe_count = 4;
2857
2858 pool->base.mpcc_count = pool->base.pipe_count;
2859 dc->debug = debug_defaults_diags;
2860 } else
2861 dc->debug = debug_defaults_diags;
2862 //dcn2.0x
2863 dc->work_arounds.dedcn20_305_wa = true;
2864
2865 // Init the vm_helper
2866 if (dc->vm_helper)
2867 init_vm_helper(dc->vm_helper, 16, pool->base.pipe_count);
2868
2869 /*************************************************
2870 * Create resources *
2871 *************************************************/
2872
2873 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
2874 dcn20_clock_source_create(ctx, ctx->dc_bios,
2875 CLOCK_SOURCE_COMBO_PHY_PLL0,
2876 &clk_src_regs[0], false);
2877 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
2878 dcn20_clock_source_create(ctx, ctx->dc_bios,
2879 CLOCK_SOURCE_COMBO_PHY_PLL1,
2880 &clk_src_regs[1], false);
2881 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
2882 dcn20_clock_source_create(ctx, ctx->dc_bios,
2883 CLOCK_SOURCE_COMBO_PHY_PLL2,
2884 &clk_src_regs[2], false);
2885 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
2886 dcn20_clock_source_create(ctx, ctx->dc_bios,
2887 CLOCK_SOURCE_COMBO_PHY_PLL3,
2888 &clk_src_regs[3], false);
2889 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
2890 dcn20_clock_source_create(ctx, ctx->dc_bios,
2891 CLOCK_SOURCE_COMBO_PHY_PLL4,
2892 &clk_src_regs[4], false);
2893 pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =
2894 dcn20_clock_source_create(ctx, ctx->dc_bios,
2895 CLOCK_SOURCE_COMBO_PHY_PLL5,
2896 &clk_src_regs[5], false);
2897 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;
2898 /* todo: not reuse phy_pll registers */
2899 pool->base.dp_clock_source =
2900 dcn20_clock_source_create(ctx, ctx->dc_bios,
2901 CLOCK_SOURCE_ID_DP_DTO,
2902 &clk_src_regs[0], true);
2903
2904 for (i = 0; i < pool->base.clk_src_count; i++) {
2905 if (pool->base.clock_sources[i] == NULL) {
2906 dm_error("DC: failed to create clock sources!\n");
2907 BREAK_TO_DEBUGGER();
2908 goto create_fail;
2909 }
2910 }
2911
2912 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2913 if (pool->base.dccg == NULL) {
2914 dm_error("DC: failed to create dccg!\n");
2915 BREAK_TO_DEBUGGER();
2916 goto create_fail;
2917 }
2918
2919 pool->base.dmcu = dcn20_dmcu_create(ctx,
2920 &dmcu_regs,
2921 &dmcu_shift,
2922 &dmcu_mask);
2923 if (pool->base.dmcu == NULL) {
2924 dm_error("DC: failed to create dmcu!\n");
2925 BREAK_TO_DEBUGGER();
2926 goto create_fail;
2927 }
2928
d7c29549 2929 pool->base.abm = dce_abm_create(ctx,
7ed4e635
HW		 2930 &abm_regs,
2931 &abm_shift,
2932 &abm_mask);
2933 if (pool->base.abm == NULL) {
2934 dm_error("DC: failed to create abm!\n");
2935 BREAK_TO_DEBUGGER();
2936 goto create_fail;
d7c29549 2937 }
7ed4e635
HW		 2938
2939 pool->base.pp_smu = dcn20_pp_smu_create(ctx);
2940
2941
2942 if (!init_soc_bounding_box(dc, pool)) {
2943 dm_error("DC: failed to initialize soc bounding box!\n");
2944 BREAK_TO_DEBUGGER();
2945 goto create_fail;
2946 }
2947
2948 dml_init_instance(&dc->dml, &dcn2_0_soc, &dcn2_0_ip, DML_PROJECT_NAVI10);
2949
2950 if (!dc->debug.disable_pplib_wm_range) {
2951 struct pp_smu_wm_range_sets ranges = {0};
2952 int i = 0;
2953
2954 ranges.num_reader_wm_sets = 0;
2955
2956 if (dcn2_0_soc.num_states == 1) {
2957 ranges.reader_wm_sets[0].wm_inst = i;
2958 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2959 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2960 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2961 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2962
2963 ranges.num_reader_wm_sets = 1;
2964 } else if (dcn2_0_soc.num_states > 1) {
2965 for (i = 0; i < 4 && i < dcn2_0_soc.num_states - 1; i++) {
2966 ranges.reader_wm_sets[i].wm_inst = i;
2967 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2968 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2969 ranges.reader_wm_sets[i].min_fill_clk_mhz = dcn2_0_soc.clock_limits[i].dram_speed_mts / 16;
2970 ranges.reader_wm_sets[i].max_fill_clk_mhz = dcn2_0_soc.clock_limits[i + 1].dram_speed_mts / 16;
2971
2972 ranges.num_reader_wm_sets = i + 1;
2973 }
2974 }
2975
2976 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2977 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2978 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2979 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2980
2981 ranges.num_writer_wm_sets = 1;
2982
2983 ranges.writer_wm_sets[0].wm_inst = 0;
2984 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2985 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2986 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2987 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2988
2989 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
2990 if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
2991 pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);
2992 }
2993
2994 init_data.ctx = dc->ctx;
2995 pool->base.irqs = dal_irq_service_dcn20_create(&init_data);
2996 if (!pool->base.irqs)
2997 goto create_fail;
2998
2999 /* mem input -> ipp -> dpp -> opp -> TG */
3000 for (i = 0; i < pool->base.pipe_count; i++) {
3001 pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
3002 if (pool->base.hubps[i] == NULL) {
3003 BREAK_TO_DEBUGGER();
3004 dm_error(
3005 "DC: failed to create memory input!\n");
3006 goto create_fail;
3007 }
3008
3009 pool->base.ipps[i] = dcn20_ipp_create(ctx, i);
3010 if (pool->base.ipps[i] == NULL) {
3011 BREAK_TO_DEBUGGER();
3012 dm_error(
3013 "DC: failed to create input pixel processor!\n");
3014 goto create_fail;
3015 }
3016
3017 pool->base.dpps[i] = dcn20_dpp_create(ctx, i);
3018 if (pool->base.dpps[i] == NULL) {
3019 BREAK_TO_DEBUGGER();
3020 dm_error(
3021 "DC: failed to create dpps!\n");
3022 goto create_fail;
3023 }
3024 }
3025 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
3026 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i);
3027 if (pool->base.engines[i] == NULL) {
3028 BREAK_TO_DEBUGGER();
3029 dm_error(
3030 "DC:failed to create aux engine!!\n");
3031 goto create_fail;
3032 }
3033 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i);
3034 if (pool->base.hw_i2cs[i] == NULL) {
3035 BREAK_TO_DEBUGGER();
3036 dm_error(
3037 "DC:failed to create hw i2c!!\n");
3038 goto create_fail;
3039 }
3040 pool->base.sw_i2cs[i] = NULL;
3041 }
3042
3043 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
3044 pool->base.opps[i] = dcn20_opp_create(ctx, i);
3045 if (pool->base.opps[i] == NULL) {
3046 BREAK_TO_DEBUGGER();
3047 dm_error(
3048 "DC: failed to create output pixel processor!\n");
3049 goto create_fail;
3050 }
3051 }
3052
3053 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
3054 pool->base.timing_generators[i] = dcn20_timing_generator_create(
3055 ctx, i);
3056 if (pool->base.timing_generators[i] == NULL) {
3057 BREAK_TO_DEBUGGER();
3058 dm_error("DC: failed to create tg!\n");
3059 goto create_fail;
3060 }
3061 }
3062
3063 pool->base.timing_generator_count = i;
3064
3065 pool->base.mpc = dcn20_mpc_create(ctx);
3066 if (pool->base.mpc == NULL) {
3067 BREAK_TO_DEBUGGER();
3068 dm_error("DC: failed to create mpc!\n");
3069 goto create_fail;
3070 }
3071
3072 pool->base.hubbub = dcn20_hubbub_create(ctx);
3073 if (pool->base.hubbub == NULL) {
3074 BREAK_TO_DEBUGGER();
3075 dm_error("DC: failed to create hubbub!\n");
3076 goto create_fail;
3077 }
3078
97bda032
HW		 3079#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3080 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
3081 pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
3082 if (pool->base.dscs[i] == NULL) {
3083 BREAK_TO_DEBUGGER();
3084 dm_error("DC: failed to create display stream compressor %d!\n", i);
3085 goto create_fail;
3086 }
3087 }
3088#endif
7ed4e635 3089
bb21290f
CL		 3090 if (!dcn20_dwbc_create(ctx, &pool->base)) {
3091 BREAK_TO_DEBUGGER();
3092 dm_error("DC: failed to create dwbc!\n");
3093 goto create_fail;
3094 }
3095 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
3096 BREAK_TO_DEBUGGER();
3097 dm_error("DC: failed to create mcif_wb!\n");
3098 goto create_fail;
3099 }
3100
7ed4e635
HW		 3101 if (!resource_construct(num_virtual_links, dc, &pool->base,
3102 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
3103 &res_create_funcs : &res_create_maximus_funcs)))
3104 goto create_fail;
3105
3106 dcn20_hw_sequencer_construct(dc);
3107
3108 dc->caps.max_planes = pool->base.pipe_count;
3109
3110 for (i = 0; i < dc->caps.max_planes; ++i)
3111 dc->caps.planes[i] = plane_cap;
3112
3113 dc->cap_funcs = cap_funcs;
3114
3115 return true;
3116
3117create_fail:
3118
3119 destruct(pool);
3120
3121 return false;
3122}
3123
3124struct resource_pool *dcn20_create_resource_pool(
3125 const struct dc_init_data *init_data,
3126 struct dc *dc)
3127{
3128 struct dcn20_resource_pool *pool =
3129 kzalloc(sizeof(struct dcn20_resource_pool), GFP_KERNEL);
3130
3131 if (!pool)
3132 return NULL;
3133
3134 if (construct(init_data->num_virtual_links, dc, pool))
3135 return &pool->base;
3136
3137 BREAK_TO_DEBUGGER();
3138 kfree(pool);
3139 return NULL;
3140}
Linux 6.x block layer and io_uring tree(s)