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drm/amd/display: Multi-display underflow observed
[linux-block.git] / drivers / gpu / drm / amd / display / dc / dcn20 / dcn20_resource.c
CommitLineData
7ed4e635
HW		 1/*
2* Copyright 2016 Advanced Micro Devices, Inc.
6ca3928d 3 * Copyright 2019 Raptor Engineering, LLC
7ed4e635
HW		 4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
d7929c1e
AD		 27#include <linux/slab.h>
28
7ed4e635
HW		 29#include "dm_services.h"
30#include "dc.h"
31
78c77382
AK		 32#include "dcn20_init.h"
33
7ed4e635
HW		 34#include "resource.h"
35#include "include/irq_service_interface.h"
36#include "dcn20/dcn20_resource.h"
37
38#include "dcn10/dcn10_hubp.h"
39#include "dcn10/dcn10_ipp.h"
40#include "dcn20_hubbub.h"
41#include "dcn20_mpc.h"
42#include "dcn20_hubp.h"
43#include "irq/dcn20/irq_service_dcn20.h"
44#include "dcn20_dpp.h"
45#include "dcn20_optc.h"
46#include "dcn20_hwseq.h"
47#include "dce110/dce110_hw_sequencer.h"
278141f5 48#include "dcn10/dcn10_resource.h"
7ed4e635
HW		 49#include "dcn20_opp.h"
50
97bda032 51#include "dcn20_dsc.h"
97bda032 52
7ed4e635
HW		 53#include "dcn20_link_encoder.h"
54#include "dcn20_stream_encoder.h"
55#include "dce/dce_clock_source.h"
56#include "dce/dce_audio.h"
57#include "dce/dce_hwseq.h"
58#include "virtual/virtual_stream_encoder.h"
59#include "dce110/dce110_resource.h"
60#include "dml/display_mode_vba.h"
61#include "dcn20_dccg.h"
62#include "dcn20_vmid.h"
d9a07577 63#include "dc_link_ddc.h"
d4caa72e 64#include "dce/dce_panel_cntl.h"
7ed4e635
HW		 65
66#include "navi10_ip_offset.h"
67
68#include "dcn/dcn_2_0_0_offset.h"
69#include "dcn/dcn_2_0_0_sh_mask.h"
a771ded8
RL		 70#include "dpcs/dpcs_2_0_0_offset.h"
71#include "dpcs/dpcs_2_0_0_sh_mask.h"
7ed4e635
HW		 72
73#include "nbio/nbio_2_3_offset.h"
74
bb21290f
CL		 75#include "dcn20/dcn20_dwb.h"
76#include "dcn20/dcn20_mmhubbub.h"
77
7ed4e635
HW		 78#include "mmhub/mmhub_2_0_0_offset.h"
79#include "mmhub/mmhub_2_0_0_sh_mask.h"
80
81#include "reg_helper.h"
82#include "dce/dce_abm.h"
83#include "dce/dce_dmcu.h"
84#include "dce/dce_aux.h"
85#include "dce/dce_i2c.h"
86#include "vm_helper.h"
87
88#include "amdgpu_socbb.h"
89
7ed4e635
HW		 90#define DC_LOGGER_INIT(logger)
91
92struct _vcs_dpi_ip_params_st dcn2_0_ip = {
93 .odm_capable = 1,
94 .gpuvm_enable = 0,
95 .hostvm_enable = 0,
96 .gpuvm_max_page_table_levels = 4,
97 .hostvm_max_page_table_levels = 4,
98 .hostvm_cached_page_table_levels = 0,
99 .pte_group_size_bytes = 2048,
97bda032 100 .num_dsc = 6,
7ed4e635
HW		 101 .rob_buffer_size_kbytes = 168,
102 .det_buffer_size_kbytes = 164,
103 .dpte_buffer_size_in_pte_reqs_luma = 84,
104 .pde_proc_buffer_size_64k_reqs = 48,
105 .dpp_output_buffer_pixels = 2560,
106 .opp_output_buffer_lines = 1,
107 .pixel_chunk_size_kbytes = 8,
108 .pte_chunk_size_kbytes = 2,
109 .meta_chunk_size_kbytes = 2,
110 .writeback_chunk_size_kbytes = 2,
111 .line_buffer_size_bits = 789504,
112 .is_line_buffer_bpp_fixed = 0,
113 .line_buffer_fixed_bpp = 0,
114 .dcc_supported = true,
115 .max_line_buffer_lines = 12,
116 .writeback_luma_buffer_size_kbytes = 12,
117 .writeback_chroma_buffer_size_kbytes = 8,
118 .writeback_chroma_line_buffer_width_pixels = 4,
119 .writeback_max_hscl_ratio = 1,
120 .writeback_max_vscl_ratio = 1,
121 .writeback_min_hscl_ratio = 1,
122 .writeback_min_vscl_ratio = 1,
123 .writeback_max_hscl_taps = 12,
124 .writeback_max_vscl_taps = 12,
125 .writeback_line_buffer_luma_buffer_size = 0,
126 .writeback_line_buffer_chroma_buffer_size = 14643,
127 .cursor_buffer_size = 8,
128 .cursor_chunk_size = 2,
129 .max_num_otg = 6,
130 .max_num_dpp = 6,
131 .max_num_wb = 1,
132 .max_dchub_pscl_bw_pix_per_clk = 4,
133 .max_pscl_lb_bw_pix_per_clk = 2,
134 .max_lb_vscl_bw_pix_per_clk = 4,
135 .max_vscl_hscl_bw_pix_per_clk = 4,
136 .max_hscl_ratio = 8,
137 .max_vscl_ratio = 8,
138 .hscl_mults = 4,
139 .vscl_mults = 4,
140 .max_hscl_taps = 8,
141 .max_vscl_taps = 8,
142 .dispclk_ramp_margin_percent = 1,
143 .underscan_factor = 1.10,
144 .min_vblank_lines = 32, //
145 .dppclk_delay_subtotal = 77, //
146 .dppclk_delay_scl_lb_only = 16,
147 .dppclk_delay_scl = 50,
148 .dppclk_delay_cnvc_formatter = 8,
149 .dppclk_delay_cnvc_cursor = 6,
150 .dispclk_delay_subtotal = 87, //
151 .dcfclk_cstate_latency = 10, // SRExitTime
152 .max_inter_dcn_tile_repeaters = 8,
7ed4e635
HW		 153 .xfc_supported = true,
154 .xfc_fill_bw_overhead_percent = 10.0,
155 .xfc_fill_constant_bytes = 0,
8f174fdb 156 .number_of_cursors = 1,
7ed4e635
HW		 157};
158
dfd84d90 159static struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {
a2c63407
Z		 160 .odm_capable = 1,
161 .gpuvm_enable = 0,
162 .hostvm_enable = 0,
163 .gpuvm_max_page_table_levels = 4,
164 .hostvm_max_page_table_levels = 4,
165 .hostvm_cached_page_table_levels = 0,
166 .num_dsc = 5,
167 .rob_buffer_size_kbytes = 168,
168 .det_buffer_size_kbytes = 164,
169 .dpte_buffer_size_in_pte_reqs_luma = 84,
170 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
171 .dpp_output_buffer_pixels = 2560,
172 .opp_output_buffer_lines = 1,
173 .pixel_chunk_size_kbytes = 8,
174 .pte_enable = 1,
175 .max_page_table_levels = 4,
176 .pte_chunk_size_kbytes = 2,
177 .meta_chunk_size_kbytes = 2,
178 .writeback_chunk_size_kbytes = 2,
179 .line_buffer_size_bits = 789504,
180 .is_line_buffer_bpp_fixed = 0,
181 .line_buffer_fixed_bpp = 0,
182 .dcc_supported = true,
183 .max_line_buffer_lines = 12,
184 .writeback_luma_buffer_size_kbytes = 12,
185 .writeback_chroma_buffer_size_kbytes = 8,
186 .writeback_chroma_line_buffer_width_pixels = 4,
187 .writeback_max_hscl_ratio = 1,
188 .writeback_max_vscl_ratio = 1,
189 .writeback_min_hscl_ratio = 1,
190 .writeback_min_vscl_ratio = 1,
191 .writeback_max_hscl_taps = 12,
192 .writeback_max_vscl_taps = 12,
193 .writeback_line_buffer_luma_buffer_size = 0,
194 .writeback_line_buffer_chroma_buffer_size = 14643,
195 .cursor_buffer_size = 8,
196 .cursor_chunk_size = 2,
197 .max_num_otg = 5,
198 .max_num_dpp = 5,
199 .max_num_wb = 1,
200 .max_dchub_pscl_bw_pix_per_clk = 4,
201 .max_pscl_lb_bw_pix_per_clk = 2,
202 .max_lb_vscl_bw_pix_per_clk = 4,
203 .max_vscl_hscl_bw_pix_per_clk = 4,
204 .max_hscl_ratio = 8,
205 .max_vscl_ratio = 8,
206 .hscl_mults = 4,
207 .vscl_mults = 4,
208 .max_hscl_taps = 8,
209 .max_vscl_taps = 8,
210 .dispclk_ramp_margin_percent = 1,
211 .underscan_factor = 1.10,
212 .min_vblank_lines = 32, //
213 .dppclk_delay_subtotal = 77, //
214 .dppclk_delay_scl_lb_only = 16,
215 .dppclk_delay_scl = 50,
216 .dppclk_delay_cnvc_formatter = 8,
217 .dppclk_delay_cnvc_cursor = 6,
218 .dispclk_delay_subtotal = 87, //
219 .dcfclk_cstate_latency = 10, // SRExitTime
220 .max_inter_dcn_tile_repeaters = 8,
221 .xfc_supported = true,
222 .xfc_fill_bw_overhead_percent = 10.0,
223 .xfc_fill_constant_bytes = 0,
8f174fdb
YS		 224 .ptoi_supported = 0,
225 .number_of_cursors = 1,
a2c63407
Z		 226};
227
dfd84d90 228static struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
fb6959ae
NK		 229 /* Defaults that get patched on driver load from firmware. */
230 .clock_limits = {
231 {
232 .state = 0,
233 .dcfclk_mhz = 560.0,
234 .fabricclk_mhz = 560.0,
235 .dispclk_mhz = 513.0,
236 .dppclk_mhz = 513.0,
237 .phyclk_mhz = 540.0,
238 .socclk_mhz = 560.0,
239 .dscclk_mhz = 171.0,
240 .dram_speed_mts = 8960.0,
241 },
242 {
243 .state = 1,
244 .dcfclk_mhz = 694.0,
245 .fabricclk_mhz = 694.0,
246 .dispclk_mhz = 642.0,
247 .dppclk_mhz = 642.0,
248 .phyclk_mhz = 600.0,
249 .socclk_mhz = 694.0,
250 .dscclk_mhz = 214.0,
251 .dram_speed_mts = 11104.0,
252 },
253 {
254 .state = 2,
255 .dcfclk_mhz = 875.0,
256 .fabricclk_mhz = 875.0,
257 .dispclk_mhz = 734.0,
258 .dppclk_mhz = 734.0,
259 .phyclk_mhz = 810.0,
260 .socclk_mhz = 875.0,
261 .dscclk_mhz = 245.0,
262 .dram_speed_mts = 14000.0,
263 },
264 {
265 .state = 3,
266 .dcfclk_mhz = 1000.0,
267 .fabricclk_mhz = 1000.0,
268 .dispclk_mhz = 1100.0,
269 .dppclk_mhz = 1100.0,
270 .phyclk_mhz = 810.0,
271 .socclk_mhz = 1000.0,
272 .dscclk_mhz = 367.0,
273 .dram_speed_mts = 16000.0,
274 },
275 {
276 .state = 4,
277 .dcfclk_mhz = 1200.0,
278 .fabricclk_mhz = 1200.0,
279 .dispclk_mhz = 1284.0,
280 .dppclk_mhz = 1284.0,
281 .phyclk_mhz = 810.0,
282 .socclk_mhz = 1200.0,
283 .dscclk_mhz = 428.0,
284 .dram_speed_mts = 16000.0,
285 },
286 /*Extra state, no dispclk ramping*/
287 {
288 .state = 5,
289 .dcfclk_mhz = 1200.0,
290 .fabricclk_mhz = 1200.0,
291 .dispclk_mhz = 1284.0,
292 .dppclk_mhz = 1284.0,
293 .phyclk_mhz = 810.0,
294 .socclk_mhz = 1200.0,
295 .dscclk_mhz = 428.0,
296 .dram_speed_mts = 16000.0,
297 },
298 },
299 .num_states = 5,
4a3dea89
AL		 300 .sr_exit_time_us = 11.6,
301 .sr_enter_plus_exit_time_us = 13.9,
fb6959ae
NK		 302 .urgent_latency_us = 4.0,
303 .urgent_latency_pixel_data_only_us = 4.0,
304 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
305 .urgent_latency_vm_data_only_us = 4.0,
306 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
307 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
308 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
309 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
310 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
311 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
312 .max_avg_sdp_bw_use_normal_percent = 40.0,
313 .max_avg_dram_bw_use_normal_percent = 40.0,
314 .writeback_latency_us = 12.0,
315 .ideal_dram_bw_after_urgent_percent = 40.0,
316 .max_request_size_bytes = 256,
317 .dram_channel_width_bytes = 2,
318 .fabric_datapath_to_dcn_data_return_bytes = 64,
319 .dcn_downspread_percent = 0.5,
320 .downspread_percent = 0.38,
321 .dram_page_open_time_ns = 50.0,
322 .dram_rw_turnaround_time_ns = 17.5,
323 .dram_return_buffer_per_channel_bytes = 8192,
324 .round_trip_ping_latency_dcfclk_cycles = 131,
325 .urgent_out_of_order_return_per_channel_bytes = 256,
326 .channel_interleave_bytes = 256,
327 .num_banks = 8,
328 .num_chans = 16,
329 .vmm_page_size_bytes = 4096,
330 .dram_clock_change_latency_us = 404.0,
331 .dummy_pstate_latency_us = 5.0,
332 .writeback_dram_clock_change_latency_us = 23.0,
333 .return_bus_width_bytes = 64,
334 .dispclk_dppclk_vco_speed_mhz = 3850,
335 .xfc_bus_transport_time_us = 20,
336 .xfc_xbuf_latency_tolerance_us = 4,
337 .use_urgent_burst_bw = 0
338};
7ed4e635 339
dfd84d90 340static struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = {
e1ab4a91
ML		 341 .clock_limits = {
342 {
343 .state = 0,
344 .dcfclk_mhz = 560.0,
345 .fabricclk_mhz = 560.0,
346 .dispclk_mhz = 513.0,
347 .dppclk_mhz = 513.0,
348 .phyclk_mhz = 540.0,
349 .socclk_mhz = 560.0,
350 .dscclk_mhz = 171.0,
351 .dram_speed_mts = 8960.0,
352 },
353 {
354 .state = 1,
355 .dcfclk_mhz = 694.0,
356 .fabricclk_mhz = 694.0,
357 .dispclk_mhz = 642.0,
358 .dppclk_mhz = 642.0,
359 .phyclk_mhz = 600.0,
360 .socclk_mhz = 694.0,
361 .dscclk_mhz = 214.0,
362 .dram_speed_mts = 11104.0,
363 },
364 {
365 .state = 2,
366 .dcfclk_mhz = 875.0,
367 .fabricclk_mhz = 875.0,
368 .dispclk_mhz = 734.0,
369 .dppclk_mhz = 734.0,
370 .phyclk_mhz = 810.0,
371 .socclk_mhz = 875.0,
372 .dscclk_mhz = 245.0,
373 .dram_speed_mts = 14000.0,
374 },
375 {
376 .state = 3,
377 .dcfclk_mhz = 1000.0,
378 .fabricclk_mhz = 1000.0,
379 .dispclk_mhz = 1100.0,
380 .dppclk_mhz = 1100.0,
381 .phyclk_mhz = 810.0,
382 .socclk_mhz = 1000.0,
383 .dscclk_mhz = 367.0,
384 .dram_speed_mts = 16000.0,
385 },
386 {
387 .state = 4,
388 .dcfclk_mhz = 1200.0,
389 .fabricclk_mhz = 1200.0,
390 .dispclk_mhz = 1284.0,
391 .dppclk_mhz = 1284.0,
392 .phyclk_mhz = 810.0,
393 .socclk_mhz = 1200.0,
394 .dscclk_mhz = 428.0,
395 .dram_speed_mts = 16000.0,
396 },
397 /*Extra state, no dispclk ramping*/
398 {
399 .state = 5,
400 .dcfclk_mhz = 1200.0,
401 .fabricclk_mhz = 1200.0,
402 .dispclk_mhz = 1284.0,
403 .dppclk_mhz = 1284.0,
404 .phyclk_mhz = 810.0,
405 .socclk_mhz = 1200.0,
406 .dscclk_mhz = 428.0,
407 .dram_speed_mts = 16000.0,
408 },
409 },
410 .num_states = 5,
a354b942
JL		 411 .sr_exit_time_us = 11.6,
412 .sr_enter_plus_exit_time_us = 13.9,
e1ab4a91
ML		 413 .urgent_latency_us = 4.0,
414 .urgent_latency_pixel_data_only_us = 4.0,
415 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
416 .urgent_latency_vm_data_only_us = 4.0,
417 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
418 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
419 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
420 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
421 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
422 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
423 .max_avg_sdp_bw_use_normal_percent = 40.0,
424 .max_avg_dram_bw_use_normal_percent = 40.0,
425 .writeback_latency_us = 12.0,
426 .ideal_dram_bw_after_urgent_percent = 40.0,
427 .max_request_size_bytes = 256,
428 .dram_channel_width_bytes = 2,
429 .fabric_datapath_to_dcn_data_return_bytes = 64,
430 .dcn_downspread_percent = 0.5,
431 .downspread_percent = 0.38,
432 .dram_page_open_time_ns = 50.0,
433 .dram_rw_turnaround_time_ns = 17.5,
434 .dram_return_buffer_per_channel_bytes = 8192,
435 .round_trip_ping_latency_dcfclk_cycles = 131,
436 .urgent_out_of_order_return_per_channel_bytes = 256,
437 .channel_interleave_bytes = 256,
438 .num_banks = 8,
439 .num_chans = 8,
440 .vmm_page_size_bytes = 4096,
441 .dram_clock_change_latency_us = 404.0,
442 .dummy_pstate_latency_us = 5.0,
443 .writeback_dram_clock_change_latency_us = 23.0,
444 .return_bus_width_bytes = 64,
445 .dispclk_dppclk_vco_speed_mhz = 3850,
446 .xfc_bus_transport_time_us = 20,
447 .xfc_xbuf_latency_tolerance_us = 4,
448 .use_urgent_burst_bw = 0
449};
450
dfd84d90 451static struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
7ed4e635
HW		 452
453#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
454 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
455 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
456 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
457 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
458 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
459 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
460 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
461 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
462 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
463 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
464 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
465 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
466 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
467 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
468#endif
469
470
471enum dcn20_clk_src_array_id {
472 DCN20_CLK_SRC_PLL0,
473 DCN20_CLK_SRC_PLL1,
474 DCN20_CLK_SRC_PLL2,
475 DCN20_CLK_SRC_PLL3,
476 DCN20_CLK_SRC_PLL4,
477 DCN20_CLK_SRC_PLL5,
478 DCN20_CLK_SRC_TOTAL
479};
480
481/* begin *********************
482 * macros to expend register list macro defined in HW object header file */
483
484/* DCN */
485/* TODO awful hack. fixup dcn20_dwb.h */
486#undef BASE_INNER
487#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
488
489#define BASE(seg) BASE_INNER(seg)
490
491#define SR(reg_name)\
492 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
493 mm ## reg_name
494
495#define SRI(reg_name, block, id)\
496 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
497 mm ## block ## id ## _ ## reg_name
498
499#define SRIR(var_name, reg_name, block, id)\
500 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
501 mm ## block ## id ## _ ## reg_name
502
503#define SRII(reg_name, block, id)\
504 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
505 mm ## block ## id ## _ ## reg_name
506
507#define DCCG_SRII(reg_name, block, id)\
508 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
509 mm ## block ## id ## _ ## reg_name
510
1e461c37
AC		 511#define VUPDATE_SRII(reg_name, block, id)\
512 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
513 mm ## reg_name ## _ ## block ## id
514
7ed4e635
HW		 515/* NBIO */
516#define NBIO_BASE_INNER(seg) \
517 NBIO_BASE__INST0_SEG ## seg
518
519#define NBIO_BASE(seg) \
520 NBIO_BASE_INNER(seg)
521
522#define NBIO_SR(reg_name)\
523 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
524 mm ## reg_name
525
526/* MMHUB */
527#define MMHUB_BASE_INNER(seg) \
528 MMHUB_BASE__INST0_SEG ## seg
529
530#define MMHUB_BASE(seg) \
531 MMHUB_BASE_INNER(seg)
532
533#define MMHUB_SR(reg_name)\
534 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
535 mmMM ## reg_name
536
537static const struct bios_registers bios_regs = {
538 NBIO_SR(BIOS_SCRATCH_3),
539 NBIO_SR(BIOS_SCRATCH_6)
540};
541
542#define clk_src_regs(index, pllid)\
543[index] = {\
544 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
545}
546
547static const struct dce110_clk_src_regs clk_src_regs[] = {
548 clk_src_regs(0, A),
549 clk_src_regs(1, B),
550 clk_src_regs(2, C),
551 clk_src_regs(3, D),
552 clk_src_regs(4, E),
553 clk_src_regs(5, F)
554};
555
556static const struct dce110_clk_src_shift cs_shift = {
557 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
558};
559
560static const struct dce110_clk_src_mask cs_mask = {
561 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
562};
563
564static const struct dce_dmcu_registers dmcu_regs = {
565 DMCU_DCN10_REG_LIST()
566};
567
568static const struct dce_dmcu_shift dmcu_shift = {
569 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
570};
571
572static const struct dce_dmcu_mask dmcu_mask = {
573 DMCU_MASK_SH_LIST_DCN10(_MASK)
574};
d7c29549 575
7ed4e635 576static const struct dce_abm_registers abm_regs = {
d7c29549 577 ABM_DCN20_REG_LIST()
7ed4e635
HW		 578};
579
580static const struct dce_abm_shift abm_shift = {
d7c29549 581 ABM_MASK_SH_LIST_DCN20(__SHIFT)
7ed4e635
HW		 582};
583
584static const struct dce_abm_mask abm_mask = {
d7c29549 585 ABM_MASK_SH_LIST_DCN20(_MASK)
7ed4e635 586};
d7c29549 587
7ed4e635
HW		 588#define audio_regs(id)\
589[id] = {\
590 AUD_COMMON_REG_LIST(id)\
591}
592
593static const struct dce_audio_registers audio_regs[] = {
594 audio_regs(0),
595 audio_regs(1),
596 audio_regs(2),
597 audio_regs(3),
598 audio_regs(4),
599 audio_regs(5),
600 audio_regs(6),
601};
602
603#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
604 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
605 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
606 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
607
608static const struct dce_audio_shift audio_shift = {
609 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
610};
611
54a9bcb0 612static const struct dce_audio_mask audio_mask = {
7ed4e635
HW		 613 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
614};
615
616#define stream_enc_regs(id)\
617[id] = {\
618 SE_DCN2_REG_LIST(id)\
619}
620
621static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
622 stream_enc_regs(0),
623 stream_enc_regs(1),
624 stream_enc_regs(2),
625 stream_enc_regs(3),
626 stream_enc_regs(4),
627 stream_enc_regs(5),
628};
629
630static const struct dcn10_stream_encoder_shift se_shift = {
631 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
632};
633
634static const struct dcn10_stream_encoder_mask se_mask = {
635 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
636};
637
638
639#define aux_regs(id)\
640[id] = {\
641 DCN2_AUX_REG_LIST(id)\
642}
643
644static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
645 aux_regs(0),
646 aux_regs(1),
647 aux_regs(2),
648 aux_regs(3),
649 aux_regs(4),
650 aux_regs(5)
651};
652
653#define hpd_regs(id)\
654[id] = {\
655 HPD_REG_LIST(id)\
656}
657
658static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
659 hpd_regs(0),
660 hpd_regs(1),
661 hpd_regs(2),
662 hpd_regs(3),
663 hpd_regs(4),
664 hpd_regs(5)
665};
666
667#define link_regs(id, phyid)\
668[id] = {\
669 LE_DCN10_REG_LIST(id), \
670 UNIPHY_DCN2_REG_LIST(phyid), \
a771ded8 671 DPCS_DCN2_REG_LIST(id), \
7ed4e635
HW		 672 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
673}
674
675static const struct dcn10_link_enc_registers link_enc_regs[] = {
676 link_regs(0, A),
677 link_regs(1, B),
678 link_regs(2, C),
679 link_regs(3, D),
680 link_regs(4, E),
681 link_regs(5, F)
682};
683
684static const struct dcn10_link_enc_shift le_shift = {
a771ded8
RL		 685 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
686 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
7ed4e635
HW		 687};
688
689static const struct dcn10_link_enc_mask le_mask = {
a771ded8
RL		 690 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
691 DPCS_DCN2_MASK_SH_LIST(_MASK)
7ed4e635
HW		 692};
693
d4caa72e
AK		 694static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
695 { DCN_PANEL_CNTL_REG_LIST() }
904fb6e0
AK		 696};
697
d4caa72e
AK		 698static const struct dce_panel_cntl_shift panel_cntl_shift = {
699 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
904fb6e0
AK		 700};
701
d4caa72e
AK		 702static const struct dce_panel_cntl_mask panel_cntl_mask = {
703 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
904fb6e0
AK		 704};
705
7ed4e635
HW		 706#define ipp_regs(id)\
707[id] = {\
708 IPP_REG_LIST_DCN20(id),\
709}
710
711static const struct dcn10_ipp_registers ipp_regs[] = {
712 ipp_regs(0),
713 ipp_regs(1),
714 ipp_regs(2),
715 ipp_regs(3),
716 ipp_regs(4),
717 ipp_regs(5),
718};
719
720static const struct dcn10_ipp_shift ipp_shift = {
721 IPP_MASK_SH_LIST_DCN20(__SHIFT)
722};
723
724static const struct dcn10_ipp_mask ipp_mask = {
725 IPP_MASK_SH_LIST_DCN20(_MASK),
726};
727
728#define opp_regs(id)\
729[id] = {\
730 OPP_REG_LIST_DCN20(id),\
731}
732
733static const struct dcn20_opp_registers opp_regs[] = {
734 opp_regs(0),
735 opp_regs(1),
736 opp_regs(2),
737 opp_regs(3),
738 opp_regs(4),
739 opp_regs(5),
740};
741
742static const struct dcn20_opp_shift opp_shift = {
743 OPP_MASK_SH_LIST_DCN20(__SHIFT)
744};
745
746static const struct dcn20_opp_mask opp_mask = {
747 OPP_MASK_SH_LIST_DCN20(_MASK)
748};
749
750#define aux_engine_regs(id)\
751[id] = {\
752 AUX_COMMON_REG_LIST0(id), \
753 .AUXN_IMPCAL = 0, \
754 .AUXP_IMPCAL = 0, \
755 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
756}
757
758static const struct dce110_aux_registers aux_engine_regs[] = {
759 aux_engine_regs(0),
760 aux_engine_regs(1),
761 aux_engine_regs(2),
762 aux_engine_regs(3),
763 aux_engine_regs(4),
764 aux_engine_regs(5)
765};
766
767#define tf_regs(id)\
768[id] = {\
769 TF_REG_LIST_DCN20(id),\
d9eb70ae 770 TF_REG_LIST_DCN20_COMMON_APPEND(id),\
7ed4e635
HW		 771}
772
773static const struct dcn2_dpp_registers tf_regs[] = {
774 tf_regs(0),
775 tf_regs(1),
776 tf_regs(2),
777 tf_regs(3),
778 tf_regs(4),
779 tf_regs(5),
780};
781
782static const struct dcn2_dpp_shift tf_shift = {
d56eaa7c 783 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
c1e34175 784 TF_DEBUG_REG_LIST_SH_DCN20
7ed4e635
HW		 785};
786
787static const struct dcn2_dpp_mask tf_mask = {
d56eaa7c 788 TF_REG_LIST_SH_MASK_DCN20(_MASK),
c1e34175 789 TF_DEBUG_REG_LIST_MASK_DCN20
7ed4e635
HW		 790};
791
bb21290f
CL		 792#define dwbc_regs_dcn2(id)\
793[id] = {\
794 DWBC_COMMON_REG_LIST_DCN2_0(id),\
795 }
796
797static const struct dcn20_dwbc_registers dwbc20_regs[] = {
798 dwbc_regs_dcn2(0),
799};
800
801static const struct dcn20_dwbc_shift dwbc20_shift = {
802 DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
803};
804
805static const struct dcn20_dwbc_mask dwbc20_mask = {
806 DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
807};
808
809#define mcif_wb_regs_dcn2(id)\
810[id] = {\
811 MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\
812 }
813
814static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {
815 mcif_wb_regs_dcn2(0),
816};
817
818static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {
819 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
820};
821
822static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {
823 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
824};
825
7ed4e635
HW		 826static const struct dcn20_mpc_registers mpc_regs = {
827 MPC_REG_LIST_DCN2_0(0),
828 MPC_REG_LIST_DCN2_0(1),
829 MPC_REG_LIST_DCN2_0(2),
830 MPC_REG_LIST_DCN2_0(3),
831 MPC_REG_LIST_DCN2_0(4),
832 MPC_REG_LIST_DCN2_0(5),
833 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
834 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
835 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
836 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
837 MPC_OUT_MUX_REG_LIST_DCN2_0(4),
838 MPC_OUT_MUX_REG_LIST_DCN2_0(5),
e8027e08 839 MPC_DBG_REG_LIST_DCN2_0()
7ed4e635
HW		 840};
841
842static const struct dcn20_mpc_shift mpc_shift = {
c1e34175
NA		 843 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
844 MPC_DEBUG_REG_LIST_SH_DCN20
7ed4e635
HW		 845};
846
847static const struct dcn20_mpc_mask mpc_mask = {
c1e34175
NA		 848 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
849 MPC_DEBUG_REG_LIST_MASK_DCN20
7ed4e635
HW		 850};
851
852#define tg_regs(id)\
853[id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
854
855
856static const struct dcn_optc_registers tg_regs[] = {
857 tg_regs(0),
858 tg_regs(1),
859 tg_regs(2),
860 tg_regs(3),
861 tg_regs(4),
862 tg_regs(5)
863};
864
865static const struct dcn_optc_shift tg_shift = {
866 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
867};
868
869static const struct dcn_optc_mask tg_mask = {
870 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
871};
872
873#define hubp_regs(id)\
874[id] = {\
875 HUBP_REG_LIST_DCN20(id)\
876}
877
878static const struct dcn_hubp2_registers hubp_regs[] = {
879 hubp_regs(0),
880 hubp_regs(1),
881 hubp_regs(2),
882 hubp_regs(3),
883 hubp_regs(4),
884 hubp_regs(5)
885};
886
887static const struct dcn_hubp2_shift hubp_shift = {
888 HUBP_MASK_SH_LIST_DCN20(__SHIFT)
889};
890
891static const struct dcn_hubp2_mask hubp_mask = {
892 HUBP_MASK_SH_LIST_DCN20(_MASK)
893};
894
895static const struct dcn_hubbub_registers hubbub_reg = {
896 HUBBUB_REG_LIST_DCN20(0)
897};
898
899static const struct dcn_hubbub_shift hubbub_shift = {
900 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT)
901};
902
903static const struct dcn_hubbub_mask hubbub_mask = {
904 HUBBUB_MASK_SH_LIST_DCN20(_MASK)
905};
906
907#define vmid_regs(id)\
908[id] = {\
909 DCN20_VMID_REG_LIST(id)\
910}
911
912static const struct dcn_vmid_registers vmid_regs[] = {
913 vmid_regs(0),
914 vmid_regs(1),
915 vmid_regs(2),
916 vmid_regs(3),
917 vmid_regs(4),
918 vmid_regs(5),
919 vmid_regs(6),
920 vmid_regs(7),
921 vmid_regs(8),
922 vmid_regs(9),
923 vmid_regs(10),
924 vmid_regs(11),
925 vmid_regs(12),
926 vmid_regs(13),
927 vmid_regs(14),
928 vmid_regs(15)
929};
930
931static const struct dcn20_vmid_shift vmid_shifts = {
932 DCN20_VMID_MASK_SH_LIST(__SHIFT)
933};
934
935static const struct dcn20_vmid_mask vmid_masks = {
936 DCN20_VMID_MASK_SH_LIST(_MASK)
937};
938
8276dd87 939static const struct dce110_aux_registers_shift aux_shift = {
940 DCN_AUX_MASK_SH_LIST(__SHIFT)
941};
942
943static const struct dce110_aux_registers_mask aux_mask = {
944 DCN_AUX_MASK_SH_LIST(_MASK)
945};
946
bf7f5ac3
YMM		 947static int map_transmitter_id_to_phy_instance(
948 enum transmitter transmitter)
949{
950 switch (transmitter) {
951 case TRANSMITTER_UNIPHY_A:
952 return 0;
953 break;
954 case TRANSMITTER_UNIPHY_B:
955 return 1;
956 break;
957 case TRANSMITTER_UNIPHY_C:
958 return 2;
959 break;
960 case TRANSMITTER_UNIPHY_D:
961 return 3;
962 break;
963 case TRANSMITTER_UNIPHY_E:
964 return 4;
965 break;
966 case TRANSMITTER_UNIPHY_F:
967 return 5;
968 break;
969 default:
970 ASSERT(0);
971 return 0;
972 }
973}
8276dd87 974
97bda032
HW		 975#define dsc_regsDCN20(id)\
976[id] = {\
977 DSC_REG_LIST_DCN20(id)\
978}
979
980static const struct dcn20_dsc_registers dsc_regs[] = {
981 dsc_regsDCN20(0),
982 dsc_regsDCN20(1),
983 dsc_regsDCN20(2),
984 dsc_regsDCN20(3),
985 dsc_regsDCN20(4),
986 dsc_regsDCN20(5)
987};
988
989static const struct dcn20_dsc_shift dsc_shift = {
990 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
991};
992
993static const struct dcn20_dsc_mask dsc_mask = {
994 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
995};
7ed4e635
HW		 996
997static const struct dccg_registers dccg_regs = {
998 DCCG_REG_LIST_DCN2()
999};
1000
1001static const struct dccg_shift dccg_shift = {
1002 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
1003};
1004
1005static const struct dccg_mask dccg_mask = {
1006 DCCG_MASK_SH_LIST_DCN2(_MASK)
1007};
1008
1009static const struct resource_caps res_cap_nv10 = {
1010 .num_timing_generator = 6,
1011 .num_opp = 6,
1012 .num_video_plane = 6,
1013 .num_audio = 7,
1014 .num_stream_encoder = 6,
1015 .num_pll = 6,
9cbee6ef 1016 .num_dwb = 1,
7ed4e635
HW		 1017 .num_ddc = 6,
1018 .num_vmid = 16,
97bda032 1019 .num_dsc = 6,
7ed4e635
HW		 1020};
1021
1022static const struct dc_plane_cap plane_cap = {
1023 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
1024 .blends_with_above = true,
1025 .blends_with_below = true,
7ed4e635 1026 .per_pixel_alpha = true,
5b1b2f20
AD		 1027
1028 .pixel_format_support = {
1029 .argb8888 = true,
1030 .nv12 = true,
cbec6477
SW		 1031 .fp16 = true,
1032 .p010 = true
5b1b2f20
AD		 1033 },
1034
1035 .max_upscale_factor = {
1036 .argb8888 = 16000,
1037 .nv12 = 16000,
1038 .fp16 = 1
1039 },
1040
1041 .max_downscale_factor = {
1042 .argb8888 = 250,
1043 .nv12 = 250,
1044 .fp16 = 1
3b26ca2d
IK		 1045 },
1046 16,
1047 16
7ed4e635 1048};
2ebe1773
BL		 1049static const struct resource_caps res_cap_nv14 = {
1050 .num_timing_generator = 5,
1051 .num_opp = 5,
1052 .num_video_plane = 5,
1053 .num_audio = 6,
1054 .num_stream_encoder = 5,
1055 .num_pll = 5,
80df905d 1056 .num_dwb = 1,
2ebe1773 1057 .num_ddc = 5,
6bb27085
ZL		 1058 .num_vmid = 16,
1059 .num_dsc = 5,
2ebe1773 1060};
7ed4e635
HW		 1061
1062static const struct dc_debug_options debug_defaults_drv = {
f0a574c9 1063 .disable_dmcu = false,
7ed4e635
HW		 1064 .force_abm_enable = false,
1065 .timing_trace = false,
1066 .clock_trace = true,
1067 .disable_pplib_clock_request = true,
1068 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
4d25a0d5 1069 .force_single_disp_pipe_split = false,
7ed4e635
HW		 1070 .disable_dcc = DCC_ENABLE,
1071 .vsr_support = true,
1072 .performance_trace = false,
1073 .max_downscale_src_width = 5120,/*upto 5K*/
1074 .disable_pplib_wm_range = false,
1075 .scl_reset_length10 = true,
9e14d4f1 1076 .sanity_checks = false,
1a7d296d 1077 .underflow_assert_delay_us = 0xFFFFFFFF,
7ed4e635
HW		 1078};
1079
1080static const struct dc_debug_options debug_defaults_diags = {
f0a574c9 1081 .disable_dmcu = false,
7ed4e635
HW		 1082 .force_abm_enable = false,
1083 .timing_trace = true,
1084 .clock_trace = true,
1085 .disable_dpp_power_gate = true,
1086 .disable_hubp_power_gate = true,
1087 .disable_clock_gate = true,
1088 .disable_pplib_clock_request = true,
1089 .disable_pplib_wm_range = true,
1090 .disable_stutter = true,
1091 .scl_reset_length10 = true,
1a7d296d 1092 .underflow_assert_delay_us = 0xFFFFFFFF,
091018a5 1093 .enable_tri_buf = true,
7ed4e635
HW		 1094};
1095
1096void dcn20_dpp_destroy(struct dpp **dpp)
1097{
1098 kfree(TO_DCN20_DPP(*dpp));
1099 *dpp = NULL;
1100}
1101
1102struct dpp *dcn20_dpp_create(
1103 struct dc_context *ctx,
1104 uint32_t inst)
1105{
1106 struct dcn20_dpp *dpp =
1107 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
1108
1109 if (!dpp)
1110 return NULL;
1111
1112 if (dpp2_construct(dpp, ctx, inst,
1113 &tf_regs[inst], &tf_shift, &tf_mask))
1114 return &dpp->base;
1115
1116 BREAK_TO_DEBUGGER();
1117 kfree(dpp);
1118 return NULL;
1119}
1120
1121struct input_pixel_processor *dcn20_ipp_create(
1122 struct dc_context *ctx, uint32_t inst)
1123{
1124 struct dcn10_ipp *ipp =
1125 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
1126
1127 if (!ipp) {
1128 BREAK_TO_DEBUGGER();
1129 return NULL;
1130 }
1131
1132 dcn20_ipp_construct(ipp, ctx, inst,
1133 &ipp_regs[inst], &ipp_shift, &ipp_mask);
1134 return &ipp->base;
1135}
1136
1137
1138struct output_pixel_processor *dcn20_opp_create(
1139 struct dc_context *ctx, uint32_t inst)
1140{
1141 struct dcn20_opp *opp =
1142 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1143
1144 if (!opp) {
1145 BREAK_TO_DEBUGGER();
1146 return NULL;
1147 }
1148
1149 dcn20_opp_construct(opp, ctx, inst,
1150 &opp_regs[inst], &opp_shift, &opp_mask);
1151 return &opp->base;
1152}
1153
1154struct dce_aux *dcn20_aux_engine_create(
1155 struct dc_context *ctx,
1156 uint32_t inst)
1157{
1158 struct aux_engine_dce110 *aux_engine =
1159 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
1160
1161 if (!aux_engine)
1162 return NULL;
1163
1164 dce110_aux_engine_construct(aux_engine, ctx, inst,
1165 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
8276dd87 1166 &aux_engine_regs[inst],
1167 &aux_mask,
f6040a43 1168 &aux_shift,
1169 ctx->dc->caps.extended_aux_timeout_support);
7ed4e635
HW		 1170
1171 return &aux_engine->base;
1172}
1173#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
1174
1175static const struct dce_i2c_registers i2c_hw_regs[] = {
1176 i2c_inst_regs(1),
1177 i2c_inst_regs(2),
1178 i2c_inst_regs(3),
1179 i2c_inst_regs(4),
1180 i2c_inst_regs(5),
1181 i2c_inst_regs(6),
1182};
1183
1184static const struct dce_i2c_shift i2c_shifts = {
1185 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
1186};
1187
1188static const struct dce_i2c_mask i2c_masks = {
1189 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
1190};
1191
1192struct dce_i2c_hw *dcn20_i2c_hw_create(
1193 struct dc_context *ctx,
1194 uint32_t inst)
1195{
1196 struct dce_i2c_hw *dce_i2c_hw =
1197 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1198
1199 if (!dce_i2c_hw)
1200 return NULL;
1201
1202 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1203 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1204
1205 return dce_i2c_hw;
1206}
1207struct mpc *dcn20_mpc_create(struct dc_context *ctx)
1208{
1209 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1210 GFP_KERNEL);
1211
1212 if (!mpc20)
1213 return NULL;
1214
1215 dcn20_mpc_construct(mpc20, ctx,
1216 &mpc_regs,
1217 &mpc_shift,
1218 &mpc_mask,
1219 6);
1220
1221 return &mpc20->base;
1222}
1223
1224struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)
1225{
1226 int i;
1227 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1228 GFP_KERNEL);
1229
1230 if (!hubbub)
1231 return NULL;
1232
1233 hubbub2_construct(hubbub, ctx,
1234 &hubbub_reg,
1235 &hubbub_shift,
1236 &hubbub_mask);
1237
1238 for (i = 0; i < res_cap_nv10.num_vmid; i++) {
1239 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1240
1241 vmid->ctx = ctx;
1242
1243 vmid->regs = &vmid_regs[i];
1244 vmid->shifts = &vmid_shifts;
1245 vmid->masks = &vmid_masks;
1246 }
1247
1248 return &hubbub->base;
1249}
1250
1251struct timing_generator *dcn20_timing_generator_create(
1252 struct dc_context *ctx,
1253 uint32_t instance)
1254{
1255 struct optc *tgn10 =
1256 kzalloc(sizeof(struct optc), GFP_KERNEL);
1257
1258 if (!tgn10)
1259 return NULL;
1260
1261 tgn10->base.inst = instance;
1262 tgn10->base.ctx = ctx;
1263
1264 tgn10->tg_regs = &tg_regs[instance];
1265 tgn10->tg_shift = &tg_shift;
1266 tgn10->tg_mask = &tg_mask;
1267
1268 dcn20_timing_generator_init(tgn10);
1269
1270 return &tgn10->base;
1271}
1272
1273static const struct encoder_feature_support link_enc_feature = {
1274 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1275 .max_hdmi_pixel_clock = 600000,
1276 .hdmi_ycbcr420_supported = true,
1277 .dp_ycbcr420_supported = true,
c14b726e 1278 .fec_supported = true,
7ed4e635
HW		 1279 .flags.bits.IS_HBR2_CAPABLE = true,
1280 .flags.bits.IS_HBR3_CAPABLE = true,
1281 .flags.bits.IS_TPS3_CAPABLE = true,
1282 .flags.bits.IS_TPS4_CAPABLE = true
1283};
1284
1285struct link_encoder *dcn20_link_encoder_create(
1286 const struct encoder_init_data *enc_init_data)
1287{
1288 struct dcn20_link_encoder *enc20 =
1289 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
bf7f5ac3 1290 int link_regs_id;
7ed4e635
HW		 1291
1292 if (!enc20)
1293 return NULL;
1294
bf7f5ac3
YMM		 1295 link_regs_id =
1296 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1297
7ed4e635
HW		 1298 dcn20_link_encoder_construct(enc20,
1299 enc_init_data,
1300 &link_enc_feature,
bf7f5ac3 1301 &link_enc_regs[link_regs_id],
7ed4e635
HW		 1302 &link_enc_aux_regs[enc_init_data->channel - 1],
1303 &link_enc_hpd_regs[enc_init_data->hpd_source],
1304 &le_shift,
1305 &le_mask);
1306
1307 return &enc20->enc10.base;
1308}
1309
d4caa72e 1310static struct panel_cntl *dcn20_panel_cntl_create(const struct panel_cntl_init_data *init_data)
904fb6e0 1311{
d4caa72e
AK		 1312 struct dce_panel_cntl *panel_cntl =
1313 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
904fb6e0 1314
d4caa72e 1315 if (!panel_cntl)
904fb6e0
AK		 1316 return NULL;
1317
d4caa72e 1318 dce_panel_cntl_construct(panel_cntl,
904fb6e0 1319 init_data,
d4caa72e
AK		 1320 &panel_cntl_regs[init_data->inst],
1321 &panel_cntl_shift,
1322 &panel_cntl_mask);
904fb6e0 1323
d4caa72e 1324 return &panel_cntl->base;
904fb6e0
AK		 1325}
1326
dfd84d90 1327static struct clock_source *dcn20_clock_source_create(
7ed4e635
HW		 1328 struct dc_context *ctx,
1329 struct dc_bios *bios,
1330 enum clock_source_id id,
1331 const struct dce110_clk_src_regs *regs,
1332 bool dp_clk_src)
1333{
1334 struct dce110_clk_src *clk_src =
1335 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1336
1337 if (!clk_src)
1338 return NULL;
1339
1340 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1341 regs, &cs_shift, &cs_mask)) {
1342 clk_src->base.dp_clk_src = dp_clk_src;
1343 return &clk_src->base;
1344 }
1345
cabe144b 1346 kfree(clk_src);
7ed4e635
HW		 1347 BREAK_TO_DEBUGGER();
1348 return NULL;
1349}
1350
1351static void read_dce_straps(
1352 struct dc_context *ctx,
1353 struct resource_straps *straps)
1354{
1355 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1356 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1357}
1358
1359static struct audio *dcn20_create_audio(
1360 struct dc_context *ctx, unsigned int inst)
1361{
1362 return dce_audio_create(ctx, inst,
1363 &audio_regs[inst], &audio_shift, &audio_mask);
1364}
1365
1366struct stream_encoder *dcn20_stream_encoder_create(
1367 enum engine_id eng_id,
1368 struct dc_context *ctx)
1369{
1370 struct dcn10_stream_encoder *enc1 =
1371 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1372
1373 if (!enc1)
1374 return NULL;
1375
9fd4c2d7
ZL		 1376 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
1377 if (eng_id >= ENGINE_ID_DIGD)
1378 eng_id++;
1379 }
1380
7ed4e635
HW		 1381 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1382 &stream_enc_regs[eng_id],
1383 &se_shift, &se_mask);
1384
1385 return &enc1->base;
1386}
1387
1388static const struct dce_hwseq_registers hwseq_reg = {
1389 HWSEQ_DCN2_REG_LIST()
1390};
1391
1392static const struct dce_hwseq_shift hwseq_shift = {
1393 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT)
1394};
1395
1396static const struct dce_hwseq_mask hwseq_mask = {
1397 HWSEQ_DCN2_MASK_SH_LIST(_MASK)
1398};
1399
1400struct dce_hwseq *dcn20_hwseq_create(
1401 struct dc_context *ctx)
1402{
1403 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1404
1405 if (hws) {
1406 hws->ctx = ctx;
1407 hws->regs = &hwseq_reg;
1408 hws->shifts = &hwseq_shift;
1409 hws->masks = &hwseq_mask;
1410 }
1411 return hws;
1412}
1413
1414static const struct resource_create_funcs res_create_funcs = {
1415 .read_dce_straps = read_dce_straps,
1416 .create_audio = dcn20_create_audio,
1417 .create_stream_encoder = dcn20_stream_encoder_create,
1418 .create_hwseq = dcn20_hwseq_create,
1419};
1420
1421static const struct resource_create_funcs res_create_maximus_funcs = {
1422 .read_dce_straps = NULL,
1423 .create_audio = NULL,
1424 .create_stream_encoder = NULL,
1425 .create_hwseq = dcn20_hwseq_create,
1426};
1427
44e149bb
AD		 1428static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
1429
7ed4e635
HW		 1430void dcn20_clock_source_destroy(struct clock_source **clk_src)
1431{
1432 kfree(TO_DCE110_CLK_SRC(*clk_src));
1433 *clk_src = NULL;
1434}
1435
97bda032
HW		 1436
1437struct display_stream_compressor *dcn20_dsc_create(
1438 struct dc_context *ctx, uint32_t inst)
1439{
1440 struct dcn20_dsc *dsc =
1441 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1442
1443 if (!dsc) {
1444 BREAK_TO_DEBUGGER();
1445 return NULL;
1446 }
1447
1448 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1449 return &dsc->base;
1450}
1451
1452void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
1453{
1454 kfree(container_of(*dsc, struct dcn20_dsc, base));
1455 *dsc = NULL;
1456}
1457
7ed4e635 1458
d9e32672 1459static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)
7ed4e635
HW		 1460{
1461 unsigned int i;
1462
1463 for (i = 0; i < pool->base.stream_enc_count; i++) {
1464 if (pool->base.stream_enc[i] != NULL) {
1465 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1466 pool->base.stream_enc[i] = NULL;
1467 }
1468 }
1469
97bda032
HW		 1470 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1471 if (pool->base.dscs[i] != NULL)
1472 dcn20_dsc_destroy(&pool->base.dscs[i]);
1473 }
7ed4e635
HW		 1474
1475 if (pool->base.mpc != NULL) {
1476 kfree(TO_DCN20_MPC(pool->base.mpc));
1477 pool->base.mpc = NULL;
1478 }
1479 if (pool->base.hubbub != NULL) {
1480 kfree(pool->base.hubbub);
1481 pool->base.hubbub = NULL;
1482 }
1483 for (i = 0; i < pool->base.pipe_count; i++) {
1484 if (pool->base.dpps[i] != NULL)
1485 dcn20_dpp_destroy(&pool->base.dpps[i]);
1486
1487 if (pool->base.ipps[i] != NULL)
1488 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1489
1490 if (pool->base.hubps[i] != NULL) {
1491 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1492 pool->base.hubps[i] = NULL;
1493 }
1494
1495 if (pool->base.irqs != NULL) {
1496 dal_irq_service_destroy(&pool->base.irqs);
1497 }
1498 }
1499
1500 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1501 if (pool->base.engines[i] != NULL)
1502 dce110_engine_destroy(&pool->base.engines[i]);
1503 if (pool->base.hw_i2cs[i] != NULL) {
1504 kfree(pool->base.hw_i2cs[i]);
1505 pool->base.hw_i2cs[i] = NULL;
1506 }
1507 if (pool->base.sw_i2cs[i] != NULL) {
1508 kfree(pool->base.sw_i2cs[i]);
1509 pool->base.sw_i2cs[i] = NULL;
1510 }
1511 }
1512
1513 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1514 if (pool->base.opps[i] != NULL)
1515 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1516 }
1517
1518 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1519 if (pool->base.timing_generators[i] != NULL) {
1520 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1521 pool->base.timing_generators[i] = NULL;
1522 }
1523 }
1524
bb21290f
CL		 1525 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1526 if (pool->base.dwbc[i] != NULL) {
1527 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
1528 pool->base.dwbc[i] = NULL;
1529 }
1530 if (pool->base.mcif_wb[i] != NULL) {
1531 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
1532 pool->base.mcif_wb[i] = NULL;
1533 }
1534 }
1535
7ed4e635
HW		 1536 for (i = 0; i < pool->base.audio_count; i++) {
1537 if (pool->base.audios[i])
1538 dce_aud_destroy(&pool->base.audios[i]);
1539 }
1540
1541 for (i = 0; i < pool->base.clk_src_count; i++) {
1542 if (pool->base.clock_sources[i] != NULL) {
1543 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1544 pool->base.clock_sources[i] = NULL;
1545 }
1546 }
1547
1548 if (pool->base.dp_clock_source != NULL) {
1549 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1550 pool->base.dp_clock_source = NULL;
1551 }
1552
1553
1554 if (pool->base.abm != NULL)
1555 dce_abm_destroy(&pool->base.abm);
1556
1557 if (pool->base.dmcu != NULL)
1558 dce_dmcu_destroy(&pool->base.dmcu);
1559
1560 if (pool->base.dccg != NULL)
1561 dcn_dccg_destroy(&pool->base.dccg);
1562
1563 if (pool->base.pp_smu != NULL)
1564 dcn20_pp_smu_destroy(&pool->base.pp_smu);
1565
d9a07577
JL		 1566 if (pool->base.oem_device != NULL)
1567 dal_ddc_service_destroy(&pool->base.oem_device);
7ed4e635
HW		 1568}
1569
1570struct hubp *dcn20_hubp_create(
1571 struct dc_context *ctx,
1572 uint32_t inst)
1573{
1574 struct dcn20_hubp *hubp2 =
1575 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1576
1577 if (!hubp2)
1578 return NULL;
1579
1580 if (hubp2_construct(hubp2, ctx, inst,
1581 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1582 return &hubp2->base;
1583
1584 BREAK_TO_DEBUGGER();
1585 kfree(hubp2);
1586 return NULL;
1587}
1588
1589static void get_pixel_clock_parameters(
1590 struct pipe_ctx *pipe_ctx,
1591 struct pixel_clk_params *pixel_clk_params)
1592{
1593 const struct dc_stream_state *stream = pipe_ctx->stream;
b1f6d01c
DL		 1594 struct pipe_ctx *odm_pipe;
1595 int opp_cnt = 1;
1596
1597 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1598 opp_cnt++;
7ed4e635
HW		 1599
1600 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1601 pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1602 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1603 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1604 /* TODO: un-hardcode*/
1605 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1606 LINK_RATE_REF_FREQ_IN_KHZ;
1607 pixel_clk_params->flags.ENABLE_SS = 0;
1608 pixel_clk_params->color_depth =
1609 stream->timing.display_color_depth;
1610 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1611 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1612
1613 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1614 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1615
b1f6d01c
DL		 1616 if (opp_cnt == 4)
1617 pixel_clk_params->requested_pix_clk_100hz /= 4;
78c77382 1618 else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2)
7ed4e635
HW		 1619 pixel_clk_params->requested_pix_clk_100hz /= 2;
1620
1621 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1622 pixel_clk_params->requested_pix_clk_100hz *= 2;
1623
1624}
1625
1626static void build_clamping_params(struct dc_stream_state *stream)
1627{
1628 stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1629 stream->clamping.c_depth = stream->timing.display_color_depth;
1630 stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1631}
1632
1633static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1634{
1635
1636 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1637
1638 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1639 pipe_ctx->clock_source,
1640 &pipe_ctx->stream_res.pix_clk_params,
1641 &pipe_ctx->pll_settings);
1642
1643 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1644
1645 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1646 &pipe_ctx->stream->bit_depth_params);
1647 build_clamping_params(pipe_ctx->stream);
1648
1649 return DC_OK;
1650}
1651
1652enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
1653{
1654 enum dc_status status = DC_OK;
1655 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1656
7ed4e635
HW		 1657 if (!pipe_ctx)
1658 return DC_ERROR_UNEXPECTED;
1659
1660
1661 status = build_pipe_hw_param(pipe_ctx);
1662
1663 return status;
1664}
1665
97bda032 1666
570bc18c 1667void dcn20_acquire_dsc(const struct dc *dc,
14e49bb3 1668 struct resource_context *res_ctx,
eab4bb97
NC		 1669 struct display_stream_compressor **dsc,
1670 int pipe_idx)
97bda032
HW		 1671{
1672 int i;
14e49bb3
NC		 1673 const struct resource_pool *pool = dc->res_pool;
1674 struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc;
c9ae6e16 1675
14e49bb3 1676 ASSERT(*dsc == NULL); /* If this ASSERT fails, dsc was not released properly */
c9ae6e16 1677 *dsc = NULL;
97bda032 1678
14e49bb3 1679 /* Always do 1-to-1 mapping when number of DSCs is same as number of pipes */
eab4bb97
NC		 1680 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) {
1681 *dsc = pool->dscs[pipe_idx];
1682 res_ctx->is_dsc_acquired[pipe_idx] = true;
1683 return;
1684 }
1685
14e49bb3
NC		 1686 /* Return old DSC to avoid the need for re-programming */
1687 if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) {
1688 *dsc = dsc_old;
1689 res_ctx->is_dsc_acquired[dsc_old->inst] = true;
1690 return ;
1691 }
1692
97bda032
HW		 1693 /* Find first free DSC */
1694 for (i = 0; i < pool->res_cap->num_dsc; i++)
1695 if (!res_ctx->is_dsc_acquired[i]) {
c9ae6e16 1696 *dsc = pool->dscs[i];
97bda032
HW		 1697 res_ctx->is_dsc_acquired[i] = true;
1698 break;
1699 }
97bda032
HW		 1700}
1701
7287a675 1702void dcn20_release_dsc(struct resource_context *res_ctx,
97bda032 1703 const struct resource_pool *pool,
c9ae6e16 1704 struct display_stream_compressor **dsc)
97bda032
HW		 1705{
1706 int i;
1707
1708 for (i = 0; i < pool->res_cap->num_dsc; i++)
c9ae6e16 1709 if (pool->dscs[i] == *dsc) {
97bda032 1710 res_ctx->is_dsc_acquired[i] = false;
c9ae6e16 1711 *dsc = NULL;
97bda032
HW		 1712 break;
1713 }
1714}
1715
7ed4e635 1716
7ed4e635 1717
8c20a1ed 1718enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc,
c9ae6e16
NC		 1719 struct dc_state *dc_ctx,
1720 struct dc_stream_state *dc_stream)
1721{
1722 enum dc_status result = DC_OK;
1723 int i;
97bda032 1724
c9ae6e16
NC		 1725 /* Get a DSC if required and available */
1726 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1727 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];
97bda032 1728
c9ae6e16
NC		 1729 if (pipe_ctx->stream != dc_stream)
1730 continue;
97bda032 1731
8c20a1ed
DF		 1732 if (pipe_ctx->stream_res.dsc)
1733 continue;
1734
570bc18c 1735 dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i);
97bda032 1736
c9ae6e16
NC		 1737 /* The number of DSCs can be less than the number of pipes */
1738 if (!pipe_ctx->stream_res.dsc) {
c9ae6e16 1739 result = DC_NO_DSC_RESOURCE;
97bda032 1740 }
7ed4e635 1741
c9ae6e16
NC		 1742 break;
1743 }
7ed4e635
HW		 1744
1745 return result;
1746}
1747
1748
ba32c50f 1749static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
c9ae6e16
NC		 1750 struct dc_state *new_ctx,
1751 struct dc_stream_state *dc_stream)
7ed4e635
HW		 1752{
1753 struct pipe_ctx *pipe_ctx = NULL;
1754 int i;
1755
7ed4e635
HW		 1756 for (i = 0; i < MAX_PIPES; i++) {
1757 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1758 pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
b1f6d01c
DL		 1759
1760 if (pipe_ctx->stream_res.dsc)
7287a675 1761 dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
7ed4e635
HW		 1762 }
1763 }
1764
1765 if (!pipe_ctx)
1766 return DC_ERROR_UNEXPECTED;
b1f6d01c
DL		 1767 else
1768 return DC_OK;
7ed4e635 1769}
c9ae6e16
NC		 1770
1771
1772enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1773{
1774 enum dc_status result = DC_ERROR_UNEXPECTED;
1775
1776 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1777
1778 if (result == DC_OK)
1779 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1780
c9ae6e16
NC		 1781 /* Get a DSC if required and available */
1782 if (result == DC_OK && dc_stream->timing.flags.DSC)
8c20a1ed 1783 result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
c9ae6e16
NC		 1784
1785 if (result == DC_OK)
1786 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
1787
1788 return result;
1789}
1790
1791
1792enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1793{
1794 enum dc_status result = DC_OK;
1795
ba32c50f 1796 result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
c9ae6e16
NC		 1797
1798 return result;
1799}
7ed4e635
HW		 1800
1801
1802static void swizzle_to_dml_params(
1803 enum swizzle_mode_values swizzle,
1804 unsigned int *sw_mode)
1805{
1806 switch (swizzle) {
1807 case DC_SW_LINEAR:
1808 *sw_mode = dm_sw_linear;
1809 break;
1810 case DC_SW_4KB_S:
1811 *sw_mode = dm_sw_4kb_s;
1812 break;
1813 case DC_SW_4KB_S_X:
1814 *sw_mode = dm_sw_4kb_s_x;
1815 break;
1816 case DC_SW_4KB_D:
1817 *sw_mode = dm_sw_4kb_d;
1818 break;
1819 case DC_SW_4KB_D_X:
1820 *sw_mode = dm_sw_4kb_d_x;
1821 break;
1822 case DC_SW_64KB_S:
1823 *sw_mode = dm_sw_64kb_s;
1824 break;
1825 case DC_SW_64KB_S_X:
1826 *sw_mode = dm_sw_64kb_s_x;
1827 break;
1828 case DC_SW_64KB_S_T:
1829 *sw_mode = dm_sw_64kb_s_t;
1830 break;
1831 case DC_SW_64KB_D:
1832 *sw_mode = dm_sw_64kb_d;
1833 break;
1834 case DC_SW_64KB_D_X:
1835 *sw_mode = dm_sw_64kb_d_x;
1836 break;
1837 case DC_SW_64KB_D_T:
1838 *sw_mode = dm_sw_64kb_d_t;
1839 break;
1840 case DC_SW_64KB_R_X:
1841 *sw_mode = dm_sw_64kb_r_x;
1842 break;
1843 case DC_SW_VAR_S:
1844 *sw_mode = dm_sw_var_s;
1845 break;
1846 case DC_SW_VAR_S_X:
1847 *sw_mode = dm_sw_var_s_x;
1848 break;
1849 case DC_SW_VAR_D:
1850 *sw_mode = dm_sw_var_d;
1851 break;
1852 case DC_SW_VAR_D_X:
1853 *sw_mode = dm_sw_var_d_x;
1854 break;
1855
1856 default:
1857 ASSERT(0); /* Not supported */
1858 break;
1859 }
1860}
1861
b6bfba6c 1862bool dcn20_split_stream_for_odm(
14e49bb3 1863 const struct dc *dc,
b1f6d01c 1864 struct resource_context *res_ctx,
b1f6d01c
DL		 1865 struct pipe_ctx *prev_odm_pipe,
1866 struct pipe_ctx *next_odm_pipe)
1867{
1868 int pipe_idx = next_odm_pipe->pipe_idx;
14e49bb3 1869 const struct resource_pool *pool = dc->res_pool;
b1f6d01c
DL		 1870
1871 *next_odm_pipe = *prev_odm_pipe;
b1f6d01c
DL		 1872
1873 next_odm_pipe->pipe_idx = pipe_idx;
1874 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
1875 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
1876 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
1877 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
1878 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
1879 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
b1f6d01c 1880 next_odm_pipe->stream_res.dsc = NULL;
b1f6d01c 1881 if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
b1f6d01c
DL		 1882 next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
1883 next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
1884 }
2e7b43e6
DL		 1885 if (prev_odm_pipe->top_pipe && prev_odm_pipe->top_pipe->next_odm_pipe) {
1886 prev_odm_pipe->top_pipe->next_odm_pipe->bottom_pipe = next_odm_pipe;
1887 next_odm_pipe->top_pipe = prev_odm_pipe->top_pipe->next_odm_pipe;
1888 }
1889 if (prev_odm_pipe->bottom_pipe && prev_odm_pipe->bottom_pipe->next_odm_pipe) {
1890 prev_odm_pipe->bottom_pipe->next_odm_pipe->top_pipe = next_odm_pipe;
1891 next_odm_pipe->bottom_pipe = prev_odm_pipe->bottom_pipe->next_odm_pipe;
1892 }
b1f6d01c
DL		 1893 prev_odm_pipe->next_odm_pipe = next_odm_pipe;
1894 next_odm_pipe->prev_odm_pipe = prev_odm_pipe;
b1f6d01c
DL		 1895
1896 if (prev_odm_pipe->plane_state) {
c0358809
DL		 1897 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
1898 int new_width;
1899
b1f6d01c
DL		 1900 /* HACTIVE halved for odm combine */
1901 sd->h_active /= 2;
b1f6d01c
DL		 1902 /* Calculate new vp and recout for left pipe */
1903 /* Need at least 16 pixels width per side */
1904 if (sd->recout.x + 16 >= sd->h_active)
1905 return false;
1906 new_width = sd->h_active - sd->recout.x;
1907 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1908 sd->ratios.horz, sd->recout.width - new_width));
1909 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1910 sd->ratios.horz_c, sd->recout.width - new_width));
1911 sd->recout.width = new_width;
1912
1913 /* Calculate new vp and recout for right pipe */
1914 sd = &next_odm_pipe->plane_res.scl_data;
c0358809
DL		 1915 /* HACTIVE halved for odm combine */
1916 sd->h_active /= 2;
b1f6d01c
DL		 1917 /* Need at least 16 pixels width per side */
1918 if (new_width <= 16)
1919 return false;
c0358809 1920 new_width = sd->recout.width + sd->recout.x - sd->h_active;
b1f6d01c
DL		 1921 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1922 sd->ratios.horz, sd->recout.width - new_width));
1923 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1924 sd->ratios.horz_c, sd->recout.width - new_width));
1925 sd->recout.width = new_width;
1926 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
1927 sd->ratios.horz, sd->h_active - sd->recout.x));
1928 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
1929 sd->ratios.horz_c, sd->h_active - sd->recout.x));
1930 sd->recout.x = 0;
1931 }
2e7b43e6
DL		 1932 if (!next_odm_pipe->top_pipe)
1933 next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
1934 else
1935 next_odm_pipe->stream_res.opp = next_odm_pipe->top_pipe->stream_res.opp;
b1f6d01c 1936 if (next_odm_pipe->stream->timing.flags.DSC == 1) {
570bc18c 1937 dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);
b1f6d01c
DL		 1938 ASSERT(next_odm_pipe->stream_res.dsc);
1939 if (next_odm_pipe->stream_res.dsc == NULL)
1940 return false;
1941 }
b1f6d01c
DL		 1942
1943 return true;
1944}
1945
65d68369 1946void dcn20_split_stream_for_mpc(
7ed4e635
HW		 1947 struct resource_context *res_ctx,
1948 const struct resource_pool *pool,
1949 struct pipe_ctx *primary_pipe,
b1f6d01c 1950 struct pipe_ctx *secondary_pipe)
7ed4e635
HW		 1951{
1952 int pipe_idx = secondary_pipe->pipe_idx;
7ed4e635 1953 struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
7ed4e635
HW		 1954
1955 *secondary_pipe = *primary_pipe;
1956 secondary_pipe->bottom_pipe = sec_bot_pipe;
1957
1958 secondary_pipe->pipe_idx = pipe_idx;
1959 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
1960 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
1961 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
1962 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
1963 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
1964 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
c92b4c46 1965 secondary_pipe->stream_res.dsc = NULL;
7ed4e635
HW		 1966 if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
1967 ASSERT(!secondary_pipe->bottom_pipe);
1968 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
1969 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
1970 }
1971 primary_pipe->bottom_pipe = secondary_pipe;
1972 secondary_pipe->top_pipe = primary_pipe;
1973
b1f6d01c 1974 ASSERT(primary_pipe->plane_state);
7ed4e635
HW		 1975}
1976
1977void dcn20_populate_dml_writeback_from_context(
1978 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1979{
1980 int pipe_cnt, i;
1981
1982 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1983 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];
1984
1985 if (!res_ctx->pipe_ctx[i].stream)
1986 continue;
1987
1988 /* Set writeback information */
1989 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
1990 pipes[pipe_cnt].dout.num_active_wb++;
1991 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
1992 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
1993 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
1994 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
1995 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
1996 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1;
1997 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
1998 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
1999 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0;
2000 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0;
2001 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
2002 if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
2003 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
2004 else
2005 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
2006 } else
2007 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
2008
2009 pipe_cnt++;
2010 }
2011
2012}
2013
2014int dcn20_populate_dml_pipes_from_context(
fa896813
IZ		 2015 struct dc *dc,
2016 struct dc_state *context,
2017 display_e2e_pipe_params_st *pipes,
2018 bool fast_validate)
7ed4e635
HW		 2019{
2020 int pipe_cnt, i;
2021 bool synchronized_vblank = true;
2f488884 2022 struct resource_context *res_ctx = &context->res_ctx;
7ed4e635
HW		 2023
2024 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
2025 if (!res_ctx->pipe_ctx[i].stream)
2026 continue;
2027
2028 if (pipe_cnt < 0) {
2029 pipe_cnt = i;
2030 continue;
2031 }
d294353e
AL		 2032
2033 if (res_ctx->pipe_ctx[pipe_cnt].stream == res_ctx->pipe_ctx[i].stream)
2034 continue;
2035
785908cf 2036 if (dc->debug.disable_timing_sync || !resource_are_streams_timing_synchronizable(
7ed4e635
HW		 2037 res_ctx->pipe_ctx[pipe_cnt].stream,
2038 res_ctx->pipe_ctx[i].stream)) {
2039 synchronized_vblank = false;
2040 break;
2041 }
2042 }
2043
2044 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2045 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
2f488884 2046 unsigned int v_total;
1075735e 2047 unsigned int front_porch;
03fd87db 2048 int output_bpc;
5dba4991 2049 struct audio_check aud_check = {0};
20f2ffe5 2050
7ed4e635
HW		 2051 if (!res_ctx->pipe_ctx[i].stream)
2052 continue;
2f488884
AL		 2053
2054 v_total = timing->v_total;
1075735e 2055 front_porch = timing->v_front_porch;
fa896813 2056
7ed4e635
HW		 2057 /* todo:
2058 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
2059 pipes[pipe_cnt].pipe.src.dcc = 0;
2060 pipes[pipe_cnt].pipe.src.vm = 0;*/
2061
5fc11598
DL		 2062 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2063
97bda032
HW		 2064 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
2065 /* todo: rotation?*/
2066 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
7ed4e635
HW		 2067 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
2068 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
2069 /* 1/2 vblank */
2070 pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
2f488884 2071 (v_total - timing->v_addressable
7ed4e635
HW		 2072 - timing->v_border_top - timing->v_border_bottom) / 2;
2073 /* 36 bytes dp, 32 hdmi */
2074 pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
2075 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
2076 }
2077 pipes[pipe_cnt].pipe.src.dcc = false;
2078 pipes[pipe_cnt].pipe.src.dcc_rate = 1;
2079 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
2080 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
2081 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
2082 - timing->h_addressable
2083 - timing->h_border_left
2084 - timing->h_border_right;
1075735e 2085 pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch;
7ed4e635
HW		 2086 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
2087 - timing->v_addressable
2088 - timing->v_border_top
2089 - timing->v_border_bottom;
2090 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
2f488884 2091 pipes[pipe_cnt].pipe.dest.vtotal = v_total;
7ed4e635
HW		 2092 pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable;
2093 pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable;
2094 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
2095 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
2096 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2097 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
2098 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
1621f4c4 2099 pipes[pipe_cnt].dout.dp_lanes = 4;
8bb3d7e7
CL		 2100 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
2101 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
5bf24270
DL		 2102 switch (get_num_odm_splits(&res_ctx->pipe_ctx[i])) {
2103 case 1:
5fc11598
DL		 2104 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1;
2105 break;
5dba4991
BL		 2106 case 3:
2107 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_4to1;
2108 break;
5fc11598
DL		 2109 default:
2110 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled;
2111 }
c0358809
DL		 2112 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
2113 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
56260cbf
DL		 2114 == res_ctx->pipe_ctx[i].plane_state) {
2115 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe;
4d765d31 2116 int split_idx = 0;
56260cbf
DL		 2117
2118 while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state
4d765d31 2119 == res_ctx->pipe_ctx[i].plane_state) {
56260cbf 2120 first_pipe = first_pipe->top_pipe;
4d765d31
DL		 2121 split_idx++;
2122 }
2123 /* Treat 4to1 mpc combine as an mpo of 2 2-to-1 combines */
2124 if (split_idx == 0)
2125 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
2126 else if (split_idx == 1)
2127 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
2128 else if (split_idx == 2)
2129 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
56260cbf 2130 } else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
c0358809
DL		 2131 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
2132
2133 while (first_pipe->prev_odm_pipe)
2134 first_pipe = first_pipe->prev_odm_pipe;
2135 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
2136 }
7ed4e635 2137
7ed4e635
HW		 2138 switch (res_ctx->pipe_ctx[i].stream->signal) {
2139 case SIGNAL_TYPE_DISPLAY_PORT_MST:
2140 case SIGNAL_TYPE_DISPLAY_PORT:
2141 pipes[pipe_cnt].dout.output_type = dm_dp;
2142 break;
2143 case SIGNAL_TYPE_EDP:
2144 pipes[pipe_cnt].dout.output_type = dm_edp;
2145 break;
2146 case SIGNAL_TYPE_HDMI_TYPE_A:
2147 case SIGNAL_TYPE_DVI_SINGLE_LINK:
2148 case SIGNAL_TYPE_DVI_DUAL_LINK:
2149 pipes[pipe_cnt].dout.output_type = dm_hdmi;
2150 break;
2151 default:
2152 /* In case there is no signal, set dp with 4 lanes to allow max config */
2153 pipes[pipe_cnt].dout.output_type = dm_dp;
2154 pipes[pipe_cnt].dout.dp_lanes = 4;
2155 }
03fd87db
IB		 2156
2157 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
2158 case COLOR_DEPTH_666:
2159 output_bpc = 6;
2160 break;
2161 case COLOR_DEPTH_888:
2162 output_bpc = 8;
2163 break;
2164 case COLOR_DEPTH_101010:
2165 output_bpc = 10;
2166 break;
2167 case COLOR_DEPTH_121212:
2168 output_bpc = 12;
2169 break;
2170 case COLOR_DEPTH_141414:
2171 output_bpc = 14;
2172 break;
2173 case COLOR_DEPTH_161616:
2174 output_bpc = 16;
2175 break;
03fd87db
IB		 2176 case COLOR_DEPTH_999:
2177 output_bpc = 9;
2178 break;
2179 case COLOR_DEPTH_111111:
2180 output_bpc = 11;
2181 break;
03fd87db
IB		 2182 default:
2183 output_bpc = 8;
2184 break;
2185 }
2186
7ed4e635
HW		 2187 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
2188 case PIXEL_ENCODING_RGB:
2189 case PIXEL_ENCODING_YCBCR444:
2190 pipes[pipe_cnt].dout.output_format = dm_444;
03fd87db 2191 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
7ed4e635
HW		 2192 break;
2193 case PIXEL_ENCODING_YCBCR420:
2194 pipes[pipe_cnt].dout.output_format = dm_420;
486cc0ee 2195 pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2;
7ed4e635
HW		 2196 break;
2197 case PIXEL_ENCODING_YCBCR422:
2198 if (true) /* todo */
2199 pipes[pipe_cnt].dout.output_format = dm_s422;
2200 else
2201 pipes[pipe_cnt].dout.output_format = dm_n422;
03fd87db 2202 pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
7ed4e635
HW		 2203 break;
2204 default:
2205 pipes[pipe_cnt].dout.output_format = dm_444;
03fd87db 2206 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
7ed4e635 2207 }
7ed4e635 2208
486cc0ee
NC		 2209 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)
2210 pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
2211
7ed4e635
HW		 2212 /* todo: default max for now, until there is logic reflecting this in dc*/
2213 pipes[pipe_cnt].dout.output_bpc = 12;
dc3de516 2214 /*fill up the audio sample rate (unit in kHz)*/
5dba4991 2215 get_audio_check(&res_ctx->pipe_ctx[i].stream->audio_info, &aud_check);
dc3de516 2216 pipes[pipe_cnt].dout.max_audio_sample_rate = aud_check.max_audiosample_rate / 1000;
7ed4e635 2217 /*
8f174fdb 2218 * For graphic plane, cursor number is 1, nv12 is 0
7ed4e635
HW		 2219 * bw calculations due to cursor on/off
2220 */
8f174fdb
YS		 2221 if (res_ctx->pipe_ctx[i].plane_state &&
2222 res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2223 pipes[pipe_cnt].pipe.src.num_cursors = 0;
2224 else
2225 pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors;
2226
ed07237c
IB		 2227 pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
2228 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
7ed4e635
HW		 2229
2230 if (!res_ctx->pipe_ctx[i].plane_state) {
56260cbf 2231 pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
7ed4e635 2232 pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
0914d115 2233 pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_4kb_s;
7ed4e635
HW		 2234 pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
2235 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
2236 if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
2237 pipes[pipe_cnt].pipe.src.viewport_width = 1920;
2238 pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
2239 if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
2240 pipes[pipe_cnt].pipe.src.viewport_height = 1080;
71e6bd2a 2241 pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height;
5fc11598
DL		 2242 pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width;
2243 pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height;
2244 pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width;
0914d115 2245 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 255) / 256) * 256;
7ed4e635
HW		 2246 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2247 pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
2248 pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/
2249 pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_hsplit != 1*/
2250 pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/
2251 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
2252 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
2253 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
2254 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
2255 pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
2256 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
2f488884
AL		 2257 pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;
2258 pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;
56260cbf
DL		 2259
2260 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) {
2261 pipes[pipe_cnt].pipe.src.viewport_width /= 2;
2262 pipes[pipe_cnt].pipe.dest.recout_width /= 2;
20f2ffe5 2263 } else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) {
5dba4991
BL		 2264 pipes[pipe_cnt].pipe.src.viewport_width /= 4;
2265 pipes[pipe_cnt].pipe.dest.recout_width /= 4;
2266 }
7ed4e635
HW		 2267 } else {
2268 struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
2269 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
2270
7ed4e635 2271 pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
56260cbf
DL		 2272 pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
2273 || (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln)
2274 || pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
d2e0d826 2275
4d765d31 2276 /* stereo is not split */
d2e0d826
NK		 2277 if (pln->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE ||
2278 pln->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) {
2279 pipes[pipe_cnt].pipe.src.is_hsplit = false;
2280 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
2281 }
2282
7ed4e635
HW		 2283 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
2284 || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
fa90219a
DL		 2285 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport_unadjusted.y;
2286 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c_unadjusted.y;
2287 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport_unadjusted.width;
2288 pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c_unadjusted.width;
2289 pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport_unadjusted.height;
2290 pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c_unadjusted.height;
5fc11598 2291 pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width;
71e6bd2a 2292 pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;
5fc11598
DL		 2293 pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width;
2294 pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height;
5dba4991
BL		 2295 if (pln->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA
2296 || pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
12e2b2d4
DL		 2297 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2298 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
2299 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
2300 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
7ed4e635 2301 } else {
12e2b2d4
DL		 2302 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2303 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
7ed4e635
HW		 2304 }
2305 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
2306 pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
2307 pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
7ed4e635 2308 pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
5bf24270
DL		 2309 pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
2310 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1)
2311 pipes[pipe_cnt].pipe.dest.full_recout_width *= 2;
5dba4991
BL		 2312 else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1)
2313 pipes[pipe_cnt].pipe.dest.full_recout_width *= 4;
5bf24270
DL		 2314 else {
2315 struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe;
2316
2317 while (split_pipe && split_pipe->plane_state == pln) {
2318 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
2319 split_pipe = split_pipe->bottom_pipe;
2320 }
2321 split_pipe = res_ctx->pipe_ctx[i].top_pipe;
2322 while (split_pipe && split_pipe->plane_state == pln) {
2323 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
2324 split_pipe = split_pipe->top_pipe;
2325 }
7ed4e635
HW		 2326 }
2327
ed07237c 2328 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
7ed4e635
HW		 2329 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
2330 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
2331 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
2332 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
2333 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
2334 scl->ratios.vert.value != dc_fixpt_one.value
2335 || scl->ratios.horz.value != dc_fixpt_one.value
2336 || scl->ratios.vert_c.value != dc_fixpt_one.value
2337 || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/
2338 || dc->debug.always_scale; /*support always scale*/
2339 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
2340 pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
2341 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
2342 pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
2343
b964e790
DL		 2344 pipes[pipe_cnt].pipe.src.macro_tile_size =
2345 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
7ed4e635
HW		 2346 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
2347 &pipes[pipe_cnt].pipe.src.sw_mode);
2348
2349 switch (pln->format) {
2350 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2351 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2352 pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
2353 break;
2354 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2355 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2356 pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
2357 break;
2358 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2359 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2360 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2361 pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
2362 break;
2363 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2364 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2365 pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
2366 break;
2367 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2368 pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
2369 break;
5dba4991
BL		 2370 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
2371 pipes[pipe_cnt].pipe.src.source_format = dm_rgbe_alpha;
2372 break;
7ed4e635
HW		 2373 default:
2374 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2375 break;
2376 }
2377 }
2378
2379 pipe_cnt++;
2380 }
2381
2382 /* populate writeback information */
2383 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
2384
2385 return pipe_cnt;
2386}
2387
2388unsigned int dcn20_calc_max_scaled_time(
2389 unsigned int time_per_pixel,
2390 enum mmhubbub_wbif_mode mode,
2391 unsigned int urgent_watermark)
2392{
2393 unsigned int time_per_byte = 0;
2394 unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */
2395 unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */
2396 unsigned int small_free_entry, max_free_entry;
2397 unsigned int buf_lh_capability;
2398 unsigned int max_scaled_time;
2399
2400 if (mode == PACKED_444) /* packed mode */
2401 time_per_byte = time_per_pixel/4;
2402 else if (mode == PLANAR_420_8BPC)
2403 time_per_byte = time_per_pixel;
2404 else if (mode == PLANAR_420_10BPC) /* p010 */
2405 time_per_byte = time_per_pixel * 819/1024;
2406
2407 if (time_per_byte == 0)
2408 time_per_byte = 1;
2409
2410 small_free_entry = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry;
2411 max_free_entry = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;
2412 buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */
2413 max_scaled_time = buf_lh_capability - urgent_watermark;
2414 return max_scaled_time;
2415}
2416
2417void dcn20_set_mcif_arb_params(
2418 struct dc *dc,
2419 struct dc_state *context,
2420 display_e2e_pipe_params_st *pipes,
2421 int pipe_cnt)
2422{
2423 enum mmhubbub_wbif_mode wbif_mode;
2424 struct mcif_arb_params *wb_arb_params;
2425 int i, j, k, dwb_pipe;
2426
2427 /* Writeback MCIF_WB arbitration parameters */
2428 dwb_pipe = 0;
2429 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2430
2431 if (!context->res_ctx.pipe_ctx[i].stream)
2432 continue;
2433
2434 for (j = 0; j < MAX_DWB_PIPES; j++) {
2435 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)
2436 continue;
2437
2438 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
2439 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
2440
2441 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {
2442 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
2443 wbif_mode = PLANAR_420_8BPC;
2444 else
2445 wbif_mode = PLANAR_420_10BPC;
2446 } else
2447 wbif_mode = PACKED_444;
2448
2449 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
2450 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2451 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2452 }
2453 wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* 4 bit fraction, ms */
2454 wb_arb_params->slice_lines = 32;
2455 wb_arb_params->arbitration_slice = 2;
2456 wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
2457 wbif_mode,
2458 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
2459
2460 dwb_pipe++;
2461
2462 if (dwb_pipe >= MAX_DWB_PIPES)
2463 return;
2464 }
2465 if (dwb_pipe >= MAX_DWB_PIPES)
2466 return;
2467 }
2468}
2469
b6bfba6c 2470bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
0ba37b20
DL		 2471{
2472 int i;
2473
2474 /* Validate DSC config, dsc count validation is already done */
2475 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2476 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
2477 struct dc_stream_state *stream = pipe_ctx->stream;
2478 struct dsc_config dsc_cfg;
b1f6d01c
DL		 2479 struct pipe_ctx *odm_pipe;
2480 int opp_cnt = 1;
2481
2482 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
2483 opp_cnt++;
0ba37b20
DL		 2484
2485 /* Only need to validate top pipe */
b1f6d01c 2486 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
0ba37b20
DL		 2487 continue;
2488
b1f6d01c
DL		 2489 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
2490 + stream->timing.h_border_right) / opp_cnt;
0ba37b20
DL		 2491 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
2492 + stream->timing.v_border_bottom;
0ba37b20
DL		 2493 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
2494 dsc_cfg.color_depth = stream->timing.display_color_depth;
df8e34ac 2495 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
0ba37b20 2496 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
b1f6d01c 2497 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
0ba37b20
DL		 2498
2499 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
2500 return false;
2501 }
2502 return true;
2503}
0ba37b20 2504
b6bfba6c 2505struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
c681491a
JL		 2506 struct resource_context *res_ctx,
2507 const struct resource_pool *pool,
2508 const struct pipe_ctx *primary_pipe)
2509{
2510 struct pipe_ctx *secondary_pipe = NULL;
2511
2512 if (dc && primary_pipe) {
2513 int j;
2514 int preferred_pipe_idx = 0;
2515
2516 /* first check the prev dc state:
2517 * if this primary pipe has a bottom pipe in prev. state
2518 * and if the bottom pipe is still available (which it should be),
2519 * pick that pipe as secondary
b1f6d01c
DL		 2520 * Same logic applies for ODM pipes. Since mpo is not allowed with odm
2521 * check in else case.
c681491a
JL		 2522 */
2523 if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {
2524 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
2525 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2526 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2527 secondary_pipe->pipe_idx = preferred_pipe_idx;
2528 }
b1f6d01c
DL		 2529 } else if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {
2530 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;
2531 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2532 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2533 secondary_pipe->pipe_idx = preferred_pipe_idx;
2534 }
c681491a
JL		 2535 }
2536
2537 /*
2538 * if this primary pipe does not have a bottom pipe in prev. state
2539 * start backward and find a pipe that did not used to be a bottom pipe in
2540 * prev. dc state. This way we make sure we keep the same assignment as
2541 * last state and will not have to reprogram every pipe
2542 */
2543 if (secondary_pipe == NULL) {
2544 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
8b8eda01
DL		 2545 if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL
2546 && dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) {
c681491a
JL		 2547 preferred_pipe_idx = j;
2548
2549 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2550 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2551 secondary_pipe->pipe_idx = preferred_pipe_idx;
2552 break;
2553 }
2554 }
2555 }
2556 }
2557 /*
2558 * We should never hit this assert unless assignments are shuffled around
2559 * if this happens we will prob. hit a vsync tdr
2560 */
2561 ASSERT(secondary_pipe);
2562 /*
2563 * search backwards for the second pipe to keep pipe
2564 * assignment more consistent
2565 */
2566 if (secondary_pipe == NULL) {
2567 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2568 preferred_pipe_idx = j;
2569
2570 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2571 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2572 secondary_pipe->pipe_idx = preferred_pipe_idx;
2573 break;
2574 }
2575 }
2576 }
2577 }
2578
2579 return secondary_pipe;
2580}
2581
ea817dd5 2582void dcn20_merge_pipes_for_validate(
6de20237 2583 struct dc *dc,
b6bfba6c 2584 struct dc_state *context)
7ed4e635 2585{
b6bfba6c 2586 int i;
7ed4e635 2587
b1f6d01c
DL		 2588 /* merge previously split odm pipes since mode support needs to make the decision */
2589 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2590 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2591 struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;
2592
2593 if (pipe->prev_odm_pipe)
2594 continue;
2595
2596 pipe->next_odm_pipe = NULL;
2597 while (odm_pipe) {
2598 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
2599
2600 odm_pipe->plane_state = NULL;
2601 odm_pipe->stream = NULL;
2602 odm_pipe->top_pipe = NULL;
2603 odm_pipe->bottom_pipe = NULL;
2604 odm_pipe->prev_odm_pipe = NULL;
2605 odm_pipe->next_odm_pipe = NULL;
b1f6d01c 2606 if (odm_pipe->stream_res.dsc)
7287a675 2607 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
b1f6d01c
DL		 2608 /* Clear plane_res and stream_res */
2609 memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));
2610 memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));
2611 odm_pipe = next_odm_pipe;
2612 }
2613 if (pipe->plane_state)
2614 resource_build_scaling_params(pipe);
2615 }
2616
2617 /* merge previously mpc split pipes since mode support needs to make the decision */
7ed4e635
HW		 2618 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2619 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2620 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2621
2622 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
2623 continue;
2624
7ed4e635
HW		 2625 pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
2626 if (hsplit_pipe->bottom_pipe)
2627 hsplit_pipe->bottom_pipe->top_pipe = pipe;
2628 hsplit_pipe->plane_state = NULL;
2629 hsplit_pipe->stream = NULL;
2630 hsplit_pipe->top_pipe = NULL;
2631 hsplit_pipe->bottom_pipe = NULL;
b1f6d01c 2632
7ed4e635
HW		 2633 /* Clear plane_res and stream_res */
2634 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
2635 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
2636 if (pipe->plane_state)
2637 resource_build_scaling_params(pipe);
2638 }
b6bfba6c 2639}
7ed4e635 2640
b6bfba6c
DL		 2641int dcn20_validate_apply_pipe_split_flags(
2642 struct dc *dc,
2643 struct dc_state *context,
2644 int vlevel,
65d68369 2645 int *split,
7287a675 2646 bool *merge)
b6bfba6c 2647{
b745ecdb 2648 int i, pipe_idx, vlevel_split;
cd3e05a7 2649 int plane_count = 0;
b6bfba6c 2650 bool force_split = false;
cd3e05a7 2651 bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID;
570bc18c
DL		 2652 struct vba_vars_st *v = &context->bw_ctx.dml.vba;
2653 int max_mpc_comb = v->maxMpcComb;
7ed4e635 2654
cd3e05a7
DL		 2655 if (context->stream_count > 1) {
2656 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP)
2657 avoid_split = true;
2658 } else if (dc->debug.force_single_disp_pipe_split)
2659 force_split = true;
2660
7ed4e635
HW		 2661 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2662 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
7ed4e635 2663
b6dbb8ff
NK		 2664 /**
2665 * Workaround for avoiding pipe-split in cases where we'd split
2666 * planes that are too small, resulting in splits that aren't
2667 * valid for the scaler.
2668 */
2669 if (pipe->plane_state &&
2670 (pipe->plane_state->dst_rect.width <= 16 ||
2671 pipe->plane_state->dst_rect.height <= 16 ||
2672 pipe->plane_state->src_rect.width <= 16 ||
2673 pipe->plane_state->src_rect.height <= 16))
2674 avoid_split = true;
2675
2676 /* TODO: fix dc bugs and remove this split threshold thing */
cd3e05a7
DL		 2677 if (pipe->stream && !pipe->prev_odm_pipe &&
2678 (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state))
2679 ++plane_count;
7ed4e635 2680 }
cd3e05a7 2681 if (plane_count > dc->res_pool->pipe_count / 2)
7ed4e635
HW		 2682 avoid_split = true;
2683
a0a85ac4
DZ		 2684 /* W/A: Mode timing with borders may not work well with pipe split, avoid for this corner case */
2685 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2686 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2687 struct dc_crtc_timing timing;
2688
2689 if (!pipe->stream)
2690 continue;
2691 else {
2692 timing = pipe->stream->timing;
2693 if (timing.h_border_left + timing.h_border_right
2694 + timing.v_border_top + timing.v_border_bottom > 0) {
2695 avoid_split = true;
2696 break;
2697 }
2698 }
2699 }
2700
b745ecdb 2701 /* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */
b6bfba6c
DL		 2702 if (avoid_split) {
2703 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2704 if (!context->res_ctx.pipe_ctx[i].stream)
2705 continue;
2706
b745ecdb 2707 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
570bc18c
DL		 2708 if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 &&
2709 v->ModeSupport[vlevel][0])
b6bfba6c
DL		 2710 break;
2711 /* Impossible to not split this pipe */
b745ecdb
DL		 2712 if (vlevel > context->bw_ctx.dml.soc.num_states)
2713 vlevel = vlevel_split;
1dfedb39
SL		 2714 else
2715 max_mpc_comb = 0;
b6bfba6c
DL		 2716 pipe_idx++;
2717 }
570bc18c 2718 v->maxMpcComb = max_mpc_comb;
b6bfba6c
DL		 2719 }
2720
b745ecdb 2721 /* Split loop sets which pipe should be split based on dml outputs and dc flags */
7ed4e635 2722 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
b6bfba6c 2723 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
570bc18c
DL		 2724 int pipe_plane = v->pipe_plane[pipe_idx];
2725 bool split4mpc = context->stream_count == 1 && plane_count == 1
2726 && dc->config.enable_4to1MPC && dc->res_pool->pipe_count >= 4;
b6bfba6c 2727
7ed4e635
HW		 2728 if (!context->res_ctx.pipe_ctx[i].stream)
2729 continue;
b6bfba6c 2730
4d765d31
DL		 2731 if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4)
2732 split[i] = 4;
2733 else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2)
65d68369 2734 split[i] = 2;
4d765d31 2735
b6bfba6c
DL		 2736 if ((pipe->stream->view_format ==
2737 VIEW_3D_FORMAT_SIDE_BY_SIDE ||
2738 pipe->stream->view_format ==
2739 VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
2740 (pipe->stream->timing.timing_3d_format ==
2741 TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
2742 pipe->stream->timing.timing_3d_format ==
2743 TIMING_3D_FORMAT_SIDE_BY_SIDE))
65d68369 2744 split[i] = 2;
b6bfba6c 2745 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
65d68369 2746 split[i] = 2;
570bc18c 2747 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1;
b6bfba6c 2748 }
5dba4991
BL		 2749 if (dc->debug.force_odm_combine_4to1 & (1 << pipe->stream_res.tg->inst)) {
2750 split[i] = 4;
2751 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1;
2752 }
5e908012
CP		 2753 /*420 format workaround*/
2754 if (pipe->stream->timing.h_addressable > 7680 &&
2755 pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
2756 split[i] = 4;
2757 }
570bc18c
DL		 2758 v->ODMCombineEnabled[pipe_plane] =
2759 v->ODMCombineEnablePerState[vlevel][pipe_plane];
2760
2761 if (v->ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) {
2762 if (get_num_mpc_splits(pipe) == 1) {
2763 /*If need split for mpc but 2 way split already*/
2764 if (split[i] == 4)
2765 split[i] = 2; /* 2 -> 4 MPC */
2766 else if (split[i] == 2)
2767 split[i] = 0; /* 2 -> 2 MPC */
2768 else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
2769 merge[i] = true; /* 2 -> 1 MPC */
2770 } else if (get_num_mpc_splits(pipe) == 3) {
2771 /*If need split for mpc but 4 way split already*/
2772 if (split[i] == 2 && ((pipe->top_pipe && !pipe->top_pipe->top_pipe)
2773 || !pipe->bottom_pipe)) {
2774 merge[i] = true; /* 4 -> 2 MPC */
2775 } else if (split[i] == 0 && pipe->top_pipe &&
2776 pipe->top_pipe->plane_state == pipe->plane_state)
2777 merge[i] = true; /* 4 -> 1 MPC */
65d68369 2778 split[i] = 0;
570bc18c
DL		 2779 } else if (get_num_odm_splits(pipe)) {
2780 /* ODM -> MPC transition */
2781 ASSERT(0); /* NOT expected yet */
7287a675 2782 if (pipe->prev_odm_pipe) {
570bc18c
DL		 2783 split[i] = 0;
2784 merge[i] = true;
7287a675
DL		 2785 }
2786 }
570bc18c
DL		 2787 } else {
2788 if (get_num_odm_splits(pipe) == 1) {
2789 /*If need split for odm but 2 way split already*/
2790 if (split[i] == 4)
2791 split[i] = 2; /* 2 -> 4 ODM */
2792 else if (split[i] == 2)
2793 split[i] = 0; /* 2 -> 2 ODM */
2794 else if (pipe->prev_odm_pipe) {
2795 ASSERT(0); /* NOT expected yet */
2796 merge[i] = true; /* exit ODM */
2797 }
2798 } else if (get_num_odm_splits(pipe) == 3) {
2799 /*If need split for odm but 4 way split already*/
2800 if (split[i] == 2 && ((pipe->prev_odm_pipe && !pipe->prev_odm_pipe->prev_odm_pipe)
2801 || !pipe->next_odm_pipe)) {
2802 ASSERT(0); /* NOT expected yet */
2803 merge[i] = true; /* 4 -> 2 ODM */
2804 } else if (split[i] == 0 && pipe->prev_odm_pipe) {
2805 ASSERT(0); /* NOT expected yet */
2806 merge[i] = true; /* exit ODM */
2807 }
65d68369 2808 split[i] = 0;
570bc18c
DL		 2809 } else if (get_num_mpc_splits(pipe)) {
2810 /* MPC -> ODM transition */
2811 ASSERT(0); /* NOT expected yet */
2812 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
2813 split[i] = 0;
2814 merge[i] = true;
2815 }
65d68369 2816 }
7287a675
DL		 2817 }
2818
b6bfba6c 2819 /* Adjust dppclk when split is forced, do not bother with dispclk */
570bc18c
DL		 2820 if (split[i] != 0 && v->NoOfDPP[vlevel][max_mpc_comb][pipe_idx] == 1)
2821 v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] /= 2;
7ed4e635
HW		 2822 pipe_idx++;
2823 }
2824
b6bfba6c
DL		 2825 return vlevel;
2826}
2827
2828bool dcn20_fast_validate_bw(
2829 struct dc *dc,
2830 struct dc_state *context,
2831 display_e2e_pipe_params_st *pipes,
2832 int *pipe_cnt_out,
2833 int *pipe_split_from,
fa896813
IZ		 2834 int *vlevel_out,
2835 bool fast_validate)
b6bfba6c
DL		 2836{
2837 bool out = false;
65d68369 2838 int split[MAX_PIPES] = { 0 };
b6bfba6c
DL		 2839 int pipe_cnt, i, pipe_idx, vlevel;
2840
2841 ASSERT(pipes);
2842 if (!pipes)
2843 return false;
2844
2845 dcn20_merge_pipes_for_validate(dc, context);
2846
fa896813 2847 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
b6bfba6c
DL		 2848
2849 *pipe_cnt_out = pipe_cnt;
2850
2851 if (!pipe_cnt) {
2852 out = true;
2853 goto validate_out;
2854 }
2855
2856 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2857
2858 if (vlevel > context->bw_ctx.dml.soc.num_states)
2859 goto validate_fail;
2860
7287a675 2861 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);
b6bfba6c
DL		 2862
2863 /*initialize pipe_just_split_from to invalid idx*/
2864 for (i = 0; i < MAX_PIPES; i++)
2865 pipe_split_from[i] = -1;
2866
7ed4e635
HW		 2867 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2868 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2869 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
7ed4e635
HW		 2870
2871 if (!pipe->stream || pipe_split_from[i] >= 0)
2872 continue;
2873
2874 pipe_idx++;
2875
7ed4e635 2876 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
c681491a 2877 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
7ed4e635 2878 ASSERT(hsplit_pipe);
b1f6d01c 2879 if (!dcn20_split_stream_for_odm(
14e49bb3 2880 dc, &context->res_ctx,
b1f6d01c 2881 pipe, hsplit_pipe))
7ed4e635
HW		 2882 goto validate_fail;
2883 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2884 dcn20_build_mapped_resource(dc, context, pipe->stream);
2885 }
2886
2887 if (!pipe->plane_state)
2888 continue;
2889 /* Skip 2nd half of already split pipe */
2890 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
2891 continue;
2892
02ce5a79
DL		 2893 /* We do not support mpo + odm at the moment */
2894 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
2895 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
2896 goto validate_fail;
2897
65d68369 2898 if (split[i] == 2) {
7ed4e635
HW		 2899 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
2900 /* pipe not split previously needs split */
c681491a 2901 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
b6bfba6c 2902 ASSERT(hsplit_pipe);
ff86391e
MS		 2903 if (!hsplit_pipe) {
2904 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2;
7ed4e635 2905 continue;
ff86391e 2906 }
b1f6d01c
DL		 2907 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2908 if (!dcn20_split_stream_for_odm(
14e49bb3 2909 dc, &context->res_ctx,
b1f6d01c
DL		 2910 pipe, hsplit_pipe))
2911 goto validate_fail;
387596ef 2912 dcn20_build_mapped_resource(dc, context, pipe->stream);
65d68369
IZ		 2913 } else {
2914 dcn20_split_stream_for_mpc(
b8a8d34b 2915 &context->res_ctx, dc->res_pool,
65d68369 2916 pipe, hsplit_pipe);
65f9ace4
SL		 2917 resource_build_scaling_params(pipe);
2918 resource_build_scaling_params(hsplit_pipe);
65d68369 2919 }
7ed4e635
HW		 2920 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2921 }
02ce5a79 2922 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
7ed4e635
HW		 2923 /* merge should already have been done */
2924 ASSERT(0);
2925 }
2926 }
0ba37b20 2927 /* Actual dsc count per stream dsc validation*/
c84ad0d6 2928 if (!dcn20_validate_dsc(dc, context)) {
0ba37b20
DL		 2929 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2930 DML_FAIL_DSC_VALIDATION_FAILURE;
2931 goto validate_fail;
2932 }
7ed4e635 2933
6de20237 2934 *vlevel_out = vlevel;
42351c66 2935
6de20237
EY		 2936 out = true;
2937 goto validate_out;
2938
2939validate_fail:
2940 out = false;
2941
2942validate_out:
2943 return out;
2944}
2945
e2e316d5 2946static void dcn20_calculate_wm(
6de20237
EY		 2947 struct dc *dc, struct dc_state *context,
2948 display_e2e_pipe_params_st *pipes,
2949 int *out_pipe_cnt,
2950 int *pipe_split_from,
fa896813
IZ		 2951 int vlevel,
2952 bool fast_validate)
6de20237
EY		 2953{
2954 int pipe_cnt, i, pipe_idx;
254eb07c 2955
7ed4e635 2956 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
41f03a6d
DL		 2957 if (!context->res_ctx.pipe_ctx[i].stream)
2958 continue;
7ed4e635 2959
41f03a6d
DL		 2960 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2961 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
7ed4e635 2962
41f03a6d
DL		 2963 if (pipe_split_from[i] < 0) {
2964 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2965 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
2966 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
2967 pipes[pipe_cnt].pipe.dest.odm_combine =
b6bfba6c 2968 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx];
41f03a6d
DL		 2969 else
2970 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2971 pipe_idx++;
2972 } else {
2973 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2974 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
2975 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
2976 pipes[pipe_cnt].pipe.dest.odm_combine =
b6bfba6c 2977 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]];
41f03a6d
DL		 2978 else
2979 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
7ed4e635 2980 }
6de20237 2981
41f03a6d
DL		 2982 if (dc->config.forced_clocks) {
2983 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2984 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
a6465d1f 2985 }
41f03a6d
DL		 2986 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
2987 pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2988 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
2989 pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2990
2991 pipe_cnt++;
2992 }
7ed4e635 2993
41f03a6d
DL		 2994 if (pipe_cnt != pipe_idx) {
2995 if (dc->res_pool->funcs->populate_dml_pipes)
2996 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
fa896813 2997 context, pipes, fast_validate);
41f03a6d
DL		 2998 else
2999 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
fa896813 3000 context, pipes, fast_validate);
41f03a6d 3001 }
7ed4e635 3002
41f03a6d 3003 *out_pipe_cnt = pipe_cnt;
6de20237 3004
41f03a6d
DL		 3005 pipes[0].clks_cfg.voltage = vlevel;
3006 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
3007 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
3008
3009 /* only pipe 0 is read for voltage and dcf/soc clocks */
3010 if (vlevel < 1) {
3011 pipes[0].clks_cfg.voltage = 1;
3012 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
3013 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
3014 }
3015 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3016 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3017 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3018 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3019 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
4de094ee
BL		 3020 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3021 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
b617b265 3022 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
41f03a6d
DL		 3023
3024 if (vlevel < 2) {
3025 pipes[0].clks_cfg.voltage = 2;
3026 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
3027 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
3028 }
3029 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3030 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3031 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3032 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3033 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
4de094ee
BL		 3034 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3035 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
41f03a6d
DL		 3036
3037 if (vlevel < 3) {
3038 pipes[0].clks_cfg.voltage = 3;
3039 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
3040 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
3041 }
3042 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3043 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3044 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3045 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3046 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
4de094ee
BL		 3047 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3048 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
41f03a6d
DL		 3049
3050 pipes[0].clks_cfg.voltage = vlevel;
3051 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
3052 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
3053 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3054 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3055 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3056 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3057 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
4de094ee
BL		 3058 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3059 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
6de20237
EY		 3060}
3061
3062void dcn20_calculate_dlg_params(
3063 struct dc *dc, struct dc_state *context,
3064 display_e2e_pipe_params_st *pipes,
3065 int pipe_cnt,
3066 int vlevel)
3067{
a00d8fd4 3068 int i, pipe_idx;
8e27a2d4 3069
7ed4e635
HW		 3070 /* Writeback MCIF_WB arbitration parameters */
3071 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
3072
3073 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
3074 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
3075 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
173932de 3076 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
7ed4e635 3077 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
799c5b9c 3078 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
7ed4e635
HW		 3079 context->bw_ctx.bw.dcn.clk.p_state_change_support =
3080 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
3081 != dm_dram_clock_change_unsupported;
3082 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
3083
cab5dec4
YS		 3084 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
3085 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
3086
7ed4e635
HW		 3087 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3088 if (!context->res_ctx.pipe_ctx[i].stream)
3089 continue;
a00d8fd4
DL		 3090 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3091 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3092 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3093 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
7ed4e635
HW		 3094 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
3095 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
3096 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
3097 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
3098 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
3099 pipe_idx++;
3100 }
925f566c
CL		 3101 /*save a original dppclock copy*/
3102 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
3103 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
41f03a6d
DL		 3104 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
3105 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
7ed4e635
HW		 3106
3107 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3108 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
3109
3110 if (!context->res_ctx.pipe_ctx[i].stream)
3111 continue;
3112
3113 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
3114 &context->res_ctx.pipe_ctx[i].dlg_regs,
3115 &context->res_ctx.pipe_ctx[i].ttu_regs,
3116 pipes,
3117 pipe_cnt,
3118 pipe_idx,
3119 cstate_en,
f82c916c 3120 context->bw_ctx.bw.dcn.clk.p_state_change_support,
c400ecce 3121 false, false, true);
254eb07c 3122
7ed4e635
HW		 3123 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
3124 &context->res_ctx.pipe_ctx[i].rq_regs,
3125 pipes[pipe_idx].pipe);
3126 pipe_idx++;
3127 }
6de20237
EY		 3128}
3129
057fc695 3130static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
6de20237
EY		 3131 bool fast_validate)
3132{
3133 bool out = false;
3134
3135 BW_VAL_TRACE_SETUP();
3136
3137 int vlevel = 0;
3138 int pipe_split_from[MAX_PIPES];
3139 int pipe_cnt = 0;
fbd7cda0 3140 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
6de20237
EY		 3141 DC_LOGGER_INIT(dc->ctx->logger);
3142
3143 BW_VAL_TRACE_COUNT();
3144
fa896813 3145 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
5e335add
EY		 3146
3147 if (pipe_cnt == 0)
3148 goto validate_out;
6de20237
EY		 3149
3150 if (!out)
3151 goto validate_fail;
3152
3153 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
3154
3155 if (fast_validate) {
3156 BW_VAL_TRACE_SKIP(fast);
3157 goto validate_out;
3158 }
3159
fa896813 3160 dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
6de20237
EY		 3161 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
3162
3163 BW_VAL_TRACE_END_WATERMARKS();
7ed4e635 3164
254eb07c 3165 goto validate_out;
7ed4e635
HW		 3166
3167validate_fail:
00999d99
DL		 3168 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
3169 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
254eb07c 3170
42351c66 3171 BW_VAL_TRACE_SKIP(fail);
254eb07c
JA		 3172 out = false;
3173
3174validate_out:
7ed4e635 3175 kfree(pipes);
254eb07c 3176
42351c66
JA		 3177 BW_VAL_TRACE_FINISH();
3178
254eb07c 3179 return out;
7ed4e635
HW		 3180}
3181
8b91fd8b
DK		 3182/*
3183 * This must be noinline to ensure anything that deals with FP registers
3184 * is contained within this call; previously our compiling with hard-float
3185 * would result in fp instructions being emitted outside of the boundaries
3186 * of the DC_FP_START/END macros, which makes sense as the compiler has no
3187 * idea about what is wrapped and what is not
3188 *
3189 * This is largely just a workaround to avoid breakage introduced with 5.6,
3190 * ideally all fp-using code should be moved into its own file, only that
3191 * should be compiled with hard-float, and all code exported from there
3192 * should be strictly wrapped with DC_FP_START/END
3193 */
3194static noinline bool dcn20_validate_bandwidth_fp(struct dc *dc,
3195 struct dc_state *context, bool fast_validate)
057fc695
JL		 3196{
3197 bool voltage_supported = false;
3198 bool full_pstate_supported = false;
3199 bool dummy_pstate_supported = false;
7a8a3430 3200 double p_state_latency_us;
057fc695 3201
7a8a3430
TP		 3202 p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
3203 context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support =
3204 dc->debug.disable_dram_clock_change_vactive_support;
f00889dc
AL		 3205 context->bw_ctx.dml.soc.allow_dram_clock_one_display_vactive =
3206 dc->debug.enable_dram_clock_change_one_display_vactive;
057fc695 3207
ce271b40
QZ		 3208 /*Unsafe due to current pipe merge and split logic*/
3209 ASSERT(context != dc->current_state);
3210
7a8a3430 3211 if (fast_validate) {
8b91fd8b 3212 return dcn20_validate_bandwidth_internal(dc, context, true);
7a8a3430 3213 }
057fc695
JL		 3214
3215 // Best case, we support full UCLK switch latency
3216 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
3217 full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
3218
3219 if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
3220 (voltage_supported && full_pstate_supported)) {
30c9b7a1 3221 context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported;
057fc695
JL		 3222 goto restore_dml_state;
3223 }
3224
b9e8d95a 3225 // Fallback: Try to only support G6 temperature read latency
057fc695
JL		 3226 context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
3227
3228 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
3229 dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
3230
3231 if (voltage_supported && dummy_pstate_supported) {
3232 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
3233 goto restore_dml_state;
3234 }
3235
b9e8d95a 3236 // ERROR: fallback is supposed to always work.
057fc695
JL		 3237 ASSERT(false);
3238
3239restore_dml_state:
057fc695 3240 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
8b91fd8b
DK		 3241 return voltage_supported;
3242}
057fc695 3243
8b91fd8b
DK		 3244bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
3245 bool fast_validate)
3246{
3247 bool voltage_supported = false;
3248 DC_FP_START();
3249 voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate);
7a8a3430 3250 DC_FP_END();
057fc695
JL		 3251 return voltage_supported;
3252}
3253
7ed4e635
HW		 3254struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
3255 struct dc_state *state,
3256 const struct resource_pool *pool,
3257 struct dc_stream_state *stream)
3258{
3259 struct resource_context *res_ctx = &state->res_ctx;
3260 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
3261 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
3262
3263 if (!head_pipe)
3264 ASSERT(0);
3265
3266 if (!idle_pipe)
7a17c8ce 3267 return NULL;
7ed4e635
HW		 3268
3269 idle_pipe->stream = head_pipe->stream;
3270 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
3271 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
3272
3273 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
3274 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
3275 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
3276 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
3277
3278 return idle_pipe;
3279}
3280
3281bool dcn20_get_dcc_compression_cap(const struct dc *dc,
3282 const struct dc_dcc_surface_param *input,
3283 struct dc_surface_dcc_cap *output)
3284{
3285 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
3286 dc->res_pool->hubbub,
3287 input,
3288 output);
3289}
3290
3291static void dcn20_destroy_resource_pool(struct resource_pool **pool)
3292{
3293 struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);
3294
d9e32672 3295 dcn20_resource_destruct(dcn20_pool);
7ed4e635
HW		 3296 kfree(dcn20_pool);
3297 *pool = NULL;
3298}
3299
3300
3301static struct dc_cap_funcs cap_funcs = {
3302 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
3303};
3304
3305
8d8c82b6 3306enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state)
7ed4e635 3307{
7ed4e635
HW		 3308 enum surface_pixel_format surf_pix_format = plane_state->format;
3309 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
3310
3311 enum swizzle_mode_values swizzle = DC_SW_LINEAR;
3312
3313 if (bpp == 64)
3314 swizzle = DC_SW_64KB_D;
3315 else
3316 swizzle = DC_SW_64KB_S;
3317
3318 plane_state->tiling_info.gfx9.swizzle = swizzle;
b1c3b7f1 3319 return DC_OK;
7ed4e635
HW		 3320}
3321
25457a1f 3322static const struct resource_funcs dcn20_res_pool_funcs = {
7ed4e635
HW		 3323 .destroy = dcn20_destroy_resource_pool,
3324 .link_enc_create = dcn20_link_encoder_create,
d4caa72e 3325 .panel_cntl_create = dcn20_panel_cntl_create,
7ed4e635 3326 .validate_bandwidth = dcn20_validate_bandwidth,
7ed4e635
HW		 3327 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
3328 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
b4f71c8c 3329 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
7ed4e635
HW		 3330 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
3331 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
8d8c82b6 3332 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
c9ae6e16 3333 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
b6bfba6c 3334 .populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
278141f5 3335 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
7ed4e635
HW		 3336};
3337
bb21290f
CL		 3338bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
3339{
3340 int i;
3341 uint32_t pipe_count = pool->res_cap->num_dwb;
3342
bb21290f
CL		 3343 for (i = 0; i < pipe_count; i++) {
3344 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
3345 GFP_KERNEL);
3346
3347 if (!dwbc20) {
3348 dm_error("DC: failed to create dwbc20!\n");
3349 return false;
3350 }
3351 dcn20_dwbc_construct(dwbc20, ctx,
3352 &dwbc20_regs[i],
3353 &dwbc20_shift,
3354 &dwbc20_mask,
3355 i);
3356 pool->dwbc[i] = &dwbc20->base;
3357 }
3358 return true;
3359}
3360
3361bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
3362{
3363 int i;
3364 uint32_t pipe_count = pool->res_cap->num_dwb;
3365
3366 ASSERT(pipe_count > 0);
3367
3368 for (i = 0; i < pipe_count; i++) {
3369 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub),
3370 GFP_KERNEL);
3371
3372 if (!mcif_wb20) {
3373 dm_error("DC: failed to create mcif_wb20!\n");
3374 return false;
3375 }
3376
3377 dcn20_mmhubbub_construct(mcif_wb20, ctx,
3378 &mcif_wb20_regs[i],
3379 &mcif_wb20_shift,
3380 &mcif_wb20_mask,
3381 i);
3382
3383 pool->mcif_wb[i] = &mcif_wb20->base;
3384 }
3385 return true;
3386}
3387
44e149bb 3388static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
7ed4e635
HW		 3389{
3390 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
3391
3392 if (!pp_smu)
3393 return pp_smu;
3394
3395 dm_pp_get_funcs(ctx, pp_smu);
3396
3397 if (pp_smu->ctx.ver != PP_SMU_VER_NV)
3398 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
3399
3400 return pp_smu;
3401}
3402
44e149bb 3403static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
7ed4e635
HW		 3404{
3405 if (pp_smu && *pp_smu) {
3406 kfree(*pp_smu);
3407 *pp_smu = NULL;
3408 }
3409}
3410
44ce0cd3 3411void dcn20_cap_soc_clocks(
7ed4e635
HW		 3412 struct _vcs_dpi_soc_bounding_box_st *bb,
3413 struct pp_smu_nv_clock_table max_clocks)
3414{
3415 int i;
3416
3417 // First pass - cap all clocks higher than the reported max
3418 for (i = 0; i < bb->num_states; i++) {
3419 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
3420 && max_clocks.dcfClockInKhz != 0)
3421 bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
3422
3423 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
3424 && max_clocks.uClockInKhz != 0)
3425 bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
3426
3427 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
3428 && max_clocks.fabricClockInKhz != 0)
3429 bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
3430
3431 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
3432 && max_clocks.displayClockInKhz != 0)
3433 bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
3434
3435 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
3436 && max_clocks.dppClockInKhz != 0)
3437 bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
3438
3439 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
3440 && max_clocks.phyClockInKhz != 0)
3441 bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
3442
3443 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
3444 && max_clocks.socClockInKhz != 0)
3445 bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
3446
3447 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
3448 && max_clocks.dscClockInKhz != 0)
3449 bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
3450 }
3451
3452 // Second pass - remove all duplicate clock states
3453 for (i = bb->num_states - 1; i > 1; i--) {
3454 bool duplicate = true;
3455
3456 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz)
3457 duplicate = false;
3458 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz)
3459 duplicate = false;
3460 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz)
3461 duplicate = false;
3462 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts)
3463 duplicate = false;
3464 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz)
3465 duplicate = false;
3466 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz)
3467 duplicate = false;
3468 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz)
3469 duplicate = false;
3470 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz)
3471 duplicate = false;
3472
3473 if (duplicate)
3474 bb->num_states--;
3475 }
3476}
3477
44ce0cd3 3478void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
7ed4e635
HW		 3479 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
3480{
c42656f8 3481 struct _vcs_dpi_voltage_scaling_st calculated_states[DC__VOLTAGE_STATES];
f18bc4e5 3482 int i;
7ed4e635 3483 int num_calculated_states = 0;
f18bc4e5 3484 int min_dcfclk = 0;
7ed4e635
HW		 3485
3486 if (num_states == 0)
3487 return;
3488
960b6f4f
RR		 3489 memset(calculated_states, 0, sizeof(calculated_states));
3490
f18bc4e5
JL		 3491 if (dc->bb_overrides.min_dcfclk_mhz > 0)
3492 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
6ce2427d
AL		 3493 else {
3494 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
3495 min_dcfclk = 310;
3496 else
3497 // Accounting for SOC/DCF relationship, we can go as high as
3498 // 506Mhz in Vmin.
3499 min_dcfclk = 506;
3500 }
f18bc4e5 3501
7ed4e635 3502 for (i = 0; i < num_states; i++) {
f18bc4e5
JL		 3503 int min_fclk_required_by_uclk;
3504 calculated_states[i].state = i;
3505 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
7ed4e635 3506
5d36f783 3507 // FCLK:UCLK ratio is 1.08
5f65ae34 3508 min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32);
7ed4e635 3509
f18bc4e5
JL		 3510 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
3511 min_dcfclk : min_fclk_required_by_uclk;
7ed4e635 3512
f18bc4e5
JL		 3513 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
3514 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
7ed4e635 3515
f18bc4e5
JL		 3516 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
3517 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
7ed4e635 3518
f18bc4e5
JL		 3519 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
3520 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
3521 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
7ed4e635 3522
f18bc4e5 3523 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
7ed4e635 3524
f18bc4e5 3525 num_calculated_states++;
7ed4e635
HW		 3526 }
3527
6da16270
JL		 3528 calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
3529 calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
3530 calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
3531
7ed4e635
HW		 3532 memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
3533 bb->num_states = num_calculated_states;
f18bc4e5
JL		 3534
3535 // Duplicate the last state, DML always an extra state identical to max state to work
3536 memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st));
3537 bb->clock_limits[num_calculated_states].state = bb->num_states;
7ed4e635
HW		 3538}
3539
44ce0cd3 3540void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
7ed4e635 3541{
7ed4e635
HW		 3542 if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
3543 && dc->bb_overrides.sr_exit_time_ns) {
3544 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
3545 }
3546
3547 if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
3548 != dc->bb_overrides.sr_enter_plus_exit_time_ns
3549 && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
3550 bb->sr_enter_plus_exit_time_us =
3551 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
3552 }
3553
3554 if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
3555 && dc->bb_overrides.urgent_latency_ns) {
3556 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
3557 }
3558
3559 if ((int)(bb->dram_clock_change_latency_us * 1000)
3560 != dc->bb_overrides.dram_clock_change_latency_ns
3561 && dc->bb_overrides.dram_clock_change_latency_ns) {
3562 bb->dram_clock_change_latency_us =
3563 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
3564 }
8d829836
JA		 3565
3566 if ((int)(bb->dummy_pstate_latency_us * 1000)
3567 != dc->bb_overrides.dummy_clock_change_latency_ns
3568 && dc->bb_overrides.dummy_clock_change_latency_ns) {
3569 bb->dummy_pstate_latency_us =
3570 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;
3571 }
7ed4e635
HW		 3572}
3573
675a9e38
LL		 3574static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
3575 uint32_t hw_internal_rev)
3576{
e1ab4a91
ML		 3577 if (ASICREV_IS_NAVI14_M(hw_internal_rev))
3578 return &dcn2_0_nv14_soc;
3579
675a9e38
LL		 3580 if (ASICREV_IS_NAVI12_P(hw_internal_rev))
3581 return &dcn2_0_nv12_soc;
3582
3583 return &dcn2_0_soc;
3584}
3585
3586static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(
3587 uint32_t hw_internal_rev)
3588{
72b741af
Z		 3589 /* NV14 */
3590 if (ASICREV_IS_NAVI14_M(hw_internal_rev))
3591 return &dcn2_0_nv14_ip;
3592
675a9e38
LL		 3593 /* NV12 and NV10 */
3594 return &dcn2_0_ip;
3595}
3596
3597static enum dml_project get_dml_project_version(uint32_t hw_internal_rev)
3598{
3599 return DML_PROJECT_NAVI10v2;
3600}
3601
7ed4e635
HW		 3602#define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
3603#define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
3604
3605static bool init_soc_bounding_box(struct dc *dc,
3606 struct dcn20_resource_pool *pool)
3607{
3608 const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
675a9e38
LL		 3609 struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3610 get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);
3611 struct _vcs_dpi_ip_params_st *loaded_ip =
3612 get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);
3613
7ed4e635
HW		 3614 DC_LOGGER_INIT(dc->ctx->logger);
3615
3e0c55f3
ZL		 3616 /* TODO: upstream NV12 bounding box when its launched */
3617 if (!bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
7ed4e635
HW		 3618 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
3619 return false;
3620 }
3621
3e0c55f3 3622 if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
7ed4e635
HW		 3623 int i;
3624
675a9e38 3625 dcn2_0_nv12_soc.sr_exit_time_us =
7ed4e635 3626 fixed16_to_double_to_cpu(bb->sr_exit_time_us);
675a9e38 3627 dcn2_0_nv12_soc.sr_enter_plus_exit_time_us =
7ed4e635 3628 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us);
675a9e38 3629 dcn2_0_nv12_soc.urgent_latency_us =
7ed4e635 3630 fixed16_to_double_to_cpu(bb->urgent_latency_us);
675a9e38 3631 dcn2_0_nv12_soc.urgent_latency_pixel_data_only_us =
7ed4e635 3632 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us);
675a9e38 3633 dcn2_0_nv12_soc.urgent_latency_pixel_mixed_with_vm_data_us =
7ed4e635 3634 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us);
675a9e38 3635 dcn2_0_nv12_soc.urgent_latency_vm_data_only_us =
7ed4e635 3636 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us);
675a9e38 3637 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
7ed4e635 3638 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes);
675a9e38 3639 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
7ed4e635 3640 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes);
675a9e38 3641 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
7ed4e635 3642 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes);
675a9e38 3643 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
7ed4e635 3644 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only);
675a9e38 3645 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
7ed4e635 3646 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm);
675a9e38 3647 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
7ed4e635 3648 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only);
675a9e38 3649 dcn2_0_nv12_soc.max_avg_sdp_bw_use_normal_percent =
7ed4e635 3650 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent);
675a9e38 3651 dcn2_0_nv12_soc.max_avg_dram_bw_use_normal_percent =
7ed4e635 3652 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent);
675a9e38 3653 dcn2_0_nv12_soc.writeback_latency_us =
7ed4e635 3654 fixed16_to_double_to_cpu(bb->writeback_latency_us);
675a9e38 3655 dcn2_0_nv12_soc.ideal_dram_bw_after_urgent_percent =
7ed4e635 3656 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent);
675a9e38 3657 dcn2_0_nv12_soc.max_request_size_bytes =
7ed4e635 3658 le32_to_cpu(bb->max_request_size_bytes);
675a9e38 3659 dcn2_0_nv12_soc.dram_channel_width_bytes =
7ed4e635 3660 le32_to_cpu(bb->dram_channel_width_bytes);
675a9e38 3661 dcn2_0_nv12_soc.fabric_datapath_to_dcn_data_return_bytes =
7ed4e635 3662 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes);
675a9e38 3663 dcn2_0_nv12_soc.dcn_downspread_percent =
7ed4e635 3664 fixed16_to_double_to_cpu(bb->dcn_downspread_percent);
675a9e38 3665 dcn2_0_nv12_soc.downspread_percent =
7ed4e635 3666 fixed16_to_double_to_cpu(bb->downspread_percent);
675a9e38 3667 dcn2_0_nv12_soc.dram_page_open_time_ns =
7ed4e635 3668 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns);
675a9e38 3669 dcn2_0_nv12_soc.dram_rw_turnaround_time_ns =
7ed4e635 3670 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns);
675a9e38 3671 dcn2_0_nv12_soc.dram_return_buffer_per_channel_bytes =
7ed4e635 3672 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes);
675a9e38 3673 dcn2_0_nv12_soc.round_trip_ping_latency_dcfclk_cycles =
7ed4e635 3674 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles);
675a9e38 3675 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_bytes =
7ed4e635 3676 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes);
675a9e38 3677 dcn2_0_nv12_soc.channel_interleave_bytes =
7ed4e635 3678 le32_to_cpu(bb->channel_interleave_bytes);
675a9e38 3679 dcn2_0_nv12_soc.num_banks =
7ed4e635 3680 le32_to_cpu(bb->num_banks);
675a9e38 3681 dcn2_0_nv12_soc.num_chans =
7ed4e635 3682 le32_to_cpu(bb->num_chans);
675a9e38 3683 dcn2_0_nv12_soc.vmm_page_size_bytes =
7ed4e635 3684 le32_to_cpu(bb->vmm_page_size_bytes);
675a9e38 3685 dcn2_0_nv12_soc.dram_clock_change_latency_us =
7ed4e635 3686 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
675a9e38
LL		 3687 // HACK!! Lower uclock latency switch time so we don't switch
3688 dcn2_0_nv12_soc.dram_clock_change_latency_us = 10;
3689 dcn2_0_nv12_soc.writeback_dram_clock_change_latency_us =
7ed4e635 3690 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
675a9e38 3691 dcn2_0_nv12_soc.return_bus_width_bytes =
7ed4e635 3692 le32_to_cpu(bb->return_bus_width_bytes);
675a9e38 3693 dcn2_0_nv12_soc.dispclk_dppclk_vco_speed_mhz =
7ed4e635 3694 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz);
675a9e38 3695 dcn2_0_nv12_soc.xfc_bus_transport_time_us =
7ed4e635 3696 le32_to_cpu(bb->xfc_bus_transport_time_us);
675a9e38 3697 dcn2_0_nv12_soc.xfc_xbuf_latency_tolerance_us =
7ed4e635 3698 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us);
675a9e38 3699 dcn2_0_nv12_soc.use_urgent_burst_bw =
7ed4e635 3700 le32_to_cpu(bb->use_urgent_burst_bw);
675a9e38 3701 dcn2_0_nv12_soc.num_states =
7ed4e635
HW		 3702 le32_to_cpu(bb->num_states);
3703
675a9e38
LL		 3704 for (i = 0; i < dcn2_0_nv12_soc.num_states; i++) {
3705 dcn2_0_nv12_soc.clock_limits[i].state =
7ed4e635 3706 le32_to_cpu(bb->clock_limits[i].state);
675a9e38 3707 dcn2_0_nv12_soc.clock_limits[i].dcfclk_mhz =
7ed4e635 3708 fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz);
675a9e38 3709 dcn2_0_nv12_soc.clock_limits[i].fabricclk_mhz =
7ed4e635 3710 fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz);
675a9e38 3711 dcn2_0_nv12_soc.clock_limits[i].dispclk_mhz =
7ed4e635 3712 fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz);
675a9e38 3713 dcn2_0_nv12_soc.clock_limits[i].dppclk_mhz =
7ed4e635 3714 fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz);
675a9e38 3715 dcn2_0_nv12_soc.clock_limits[i].phyclk_mhz =
7ed4e635 3716 fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz);
675a9e38 3717 dcn2_0_nv12_soc.clock_limits[i].socclk_mhz =
7ed4e635 3718 fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz);
675a9e38 3719 dcn2_0_nv12_soc.clock_limits[i].dscclk_mhz =
7ed4e635 3720 fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz);
675a9e38 3721 dcn2_0_nv12_soc.clock_limits[i].dram_speed_mts =
7ed4e635
HW		 3722 fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
3723 }
3724 }
3725
3726 if (pool->base.pp_smu) {
3727 struct pp_smu_nv_clock_table max_clocks = {0};
3728 unsigned int uclk_states[8] = {0};
3729 unsigned int num_states = 0;
3730 enum pp_smu_status status;
3731 bool clock_limits_available = false;
3732 bool uclk_states_available = false;
3733
3734 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
3735 status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
3736 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
3737
3738 uclk_states_available = (status == PP_SMU_RESULT_OK);
3739 }
3740
3741 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
3742 status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
3743 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
c2ad17c3
AW		 3744 /* SMU cannot set DCF clock to anything equal to or higher than SOC clock
3745 */
3746 if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
3747 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
7ed4e635
HW		 3748 clock_limits_available = (status == PP_SMU_RESULT_OK);
3749 }
3750
c2ad17c3 3751 if (clock_limits_available && uclk_states_available && num_states)
44ce0cd3 3752 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
7ed4e635 3753 else if (clock_limits_available)
44ce0cd3 3754 dcn20_cap_soc_clocks(loaded_bb, max_clocks);
7ed4e635
HW		 3755 }
3756
675a9e38
LL		 3757 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
3758 loaded_ip->max_num_dpp = pool->base.pipe_count;
44ce0cd3 3759 dcn20_patch_bounding_box(dc, loaded_bb);
7ed4e635
HW		 3760
3761 return true;
3762}
3763
d9e32672 3764static bool dcn20_resource_construct(
7ed4e635
HW		 3765 uint8_t num_virtual_links,
3766 struct dc *dc,
3767 struct dcn20_resource_pool *pool)
3768{
3769 int i;
3770 struct dc_context *ctx = dc->ctx;
3771 struct irq_service_init_data init_data;
d9a07577 3772 struct ddc_service_init_data ddc_init_data;
675a9e38
LL		 3773 struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3774 get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);
3775 struct _vcs_dpi_ip_params_st *loaded_ip =
3776 get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev);
3777 enum dml_project dml_project_version =
3778 get_dml_project_version(ctx->asic_id.hw_internal_rev);
7ed4e635 3779
7a8a3430
TP		 3780 DC_FP_START();
3781
7ed4e635 3782 ctx->dc_bios->regs = &bios_regs;
7ed4e635
HW		 3783 pool->base.funcs = &dcn20_res_pool_funcs;
3784
2ebe1773
BL		 3785 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
3786 pool->base.res_cap = &res_cap_nv14;
3787 pool->base.pipe_count = 5;
3788 pool->base.mpcc_count = 5;
3789 } else {
3790 pool->base.res_cap = &res_cap_nv10;
3791 pool->base.pipe_count = 6;
3792 pool->base.mpcc_count = 6;
3793 }
7ed4e635
HW		 3794 /*************************************************
3795 * Resource + asic cap harcoding *
3796 *************************************************/
3797 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
3798
7ed4e635
HW		 3799 dc->caps.max_downscale_ratio = 200;
3800 dc->caps.i2c_speed_in_khz = 100;
b15cde19 3801 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
7ed4e635 3802 dc->caps.max_cursor_size = 256;
9248681f 3803 dc->caps.min_horizontal_blanking_period = 80;
7ed4e635
HW		 3804 dc->caps.dmdata_alloc_size = 2048;
3805
3806 dc->caps.max_slave_planes = 1;
3807 dc->caps.post_blend_color_processing = true;
3808 dc->caps.force_dp_tps4_for_cp2520 = true;
ca4f844e 3809 dc->caps.extended_aux_timeout_support = true;
7ed4e635 3810
a8bf7164
KK		 3811 /* Color pipeline capabilities */
3812 dc->caps.color.dpp.dcn_arch = 1;
3813 dc->caps.color.dpp.input_lut_shared = 0;
3814 dc->caps.color.dpp.icsc = 1;
3815 dc->caps.color.dpp.dgam_ram = 1;
3816 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
3817 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
3818 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
3819 dc->caps.color.dpp.dgam_rom_caps.pq = 0;
3820 dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
3821 dc->caps.color.dpp.post_csc = 0;
3822 dc->caps.color.dpp.gamma_corr = 0;
c6160900 3823 dc->caps.color.dpp.dgam_rom_for_yuv = 1;
a8bf7164
KK		 3824
3825 dc->caps.color.dpp.hw_3d_lut = 1;
3826 dc->caps.color.dpp.ogam_ram = 1;
3827 // no OGAM ROM on DCN2, only MPC ROM
3828 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
3829 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
3830 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
3831 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
3832 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
3833 dc->caps.color.dpp.ocsc = 0;
3834
3835 dc->caps.color.mpc.gamut_remap = 0;
3836 dc->caps.color.mpc.num_3dluts = 0;
3837 dc->caps.color.mpc.shared_3d_lut = 0;
3838 dc->caps.color.mpc.ogam_ram = 1;
3839 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
3840 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
3841 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
3842 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
3843 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
3844 dc->caps.color.mpc.ocsc = 1;
3845
803a1412 3846 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) {
7ed4e635 3847 dc->debug = debug_defaults_drv;
803a1412
ES		 3848 } else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
3849 pool->base.pipe_count = 4;
7ed4e635
HW		 3850 pool->base.mpcc_count = pool->base.pipe_count;
3851 dc->debug = debug_defaults_diags;
803a1412 3852 } else {
7ed4e635 3853 dc->debug = debug_defaults_diags;
803a1412 3854 }
7ed4e635
HW		 3855 //dcn2.0x
3856 dc->work_arounds.dedcn20_305_wa = true;
3857
3858 // Init the vm_helper
3859 if (dc->vm_helper)
bda9afda 3860 vm_helper_init(dc->vm_helper, 16);
7ed4e635
HW		 3861
3862 /*************************************************
3863 * Create resources *
3864 *************************************************/
3865
3866 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
3867 dcn20_clock_source_create(ctx, ctx->dc_bios,
3868 CLOCK_SOURCE_COMBO_PHY_PLL0,
3869 &clk_src_regs[0], false);
3870 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
3871 dcn20_clock_source_create(ctx, ctx->dc_bios,
3872 CLOCK_SOURCE_COMBO_PHY_PLL1,
3873 &clk_src_regs[1], false);
3874 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
3875 dcn20_clock_source_create(ctx, ctx->dc_bios,
3876 CLOCK_SOURCE_COMBO_PHY_PLL2,
3877 &clk_src_regs[2], false);
3878 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
3879 dcn20_clock_source_create(ctx, ctx->dc_bios,
3880 CLOCK_SOURCE_COMBO_PHY_PLL3,
3881 &clk_src_regs[3], false);
3882 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
3883 dcn20_clock_source_create(ctx, ctx->dc_bios,
3884 CLOCK_SOURCE_COMBO_PHY_PLL4,
3885 &clk_src_regs[4], false);
3886 pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =
3887 dcn20_clock_source_create(ctx, ctx->dc_bios,
3888 CLOCK_SOURCE_COMBO_PHY_PLL5,
3889 &clk_src_regs[5], false);
3890 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;
3891 /* todo: not reuse phy_pll registers */
3892 pool->base.dp_clock_source =
3893 dcn20_clock_source_create(ctx, ctx->dc_bios,
3894 CLOCK_SOURCE_ID_DP_DTO,
3895 &clk_src_regs[0], true);
3896
3897 for (i = 0; i < pool->base.clk_src_count; i++) {
3898 if (pool->base.clock_sources[i] == NULL) {
3899 dm_error("DC: failed to create clock sources!\n");
3900 BREAK_TO_DEBUGGER();
3901 goto create_fail;
3902 }
3903 }
3904
3905 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
3906 if (pool->base.dccg == NULL) {
3907 dm_error("DC: failed to create dccg!\n");
3908 BREAK_TO_DEBUGGER();
3909 goto create_fail;
3910 }
3911
3912 pool->base.dmcu = dcn20_dmcu_create(ctx,
3913 &dmcu_regs,
3914 &dmcu_shift,
3915 &dmcu_mask);
3916 if (pool->base.dmcu == NULL) {
3917 dm_error("DC: failed to create dmcu!\n");
3918 BREAK_TO_DEBUGGER();
3919 goto create_fail;
3920 }
3921
d7c29549 3922 pool->base.abm = dce_abm_create(ctx,
7ed4e635
HW		 3923 &abm_regs,
3924 &abm_shift,
3925 &abm_mask);
3926 if (pool->base.abm == NULL) {
3927 dm_error("DC: failed to create abm!\n");
3928 BREAK_TO_DEBUGGER();
3929 goto create_fail;
d7c29549 3930 }
7ed4e635
HW		 3931
3932 pool->base.pp_smu = dcn20_pp_smu_create(ctx);
3933
3934
3935 if (!init_soc_bounding_box(dc, pool)) {
3936 dm_error("DC: failed to initialize soc bounding box!\n");
3937 BREAK_TO_DEBUGGER();
3938 goto create_fail;
3939 }
3940
675a9e38 3941 dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version);
7ed4e635
HW		 3942
3943 if (!dc->debug.disable_pplib_wm_range) {
3944 struct pp_smu_wm_range_sets ranges = {0};
3945 int i = 0;
3946
3947 ranges.num_reader_wm_sets = 0;
3948
675a9e38 3949 if (loaded_bb->num_states == 1) {
7ed4e635
HW		 3950 ranges.reader_wm_sets[0].wm_inst = i;
3951 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3952 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3953 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3954 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3955
3956 ranges.num_reader_wm_sets = 1;
675a9e38
LL		 3957 } else if (loaded_bb->num_states > 1) {
3958 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
7ed4e635
HW		 3959 ranges.reader_wm_sets[i].wm_inst = i;
3960 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3961 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
675a9e38
LL		 3962 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
3963 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
7ed4e635
HW		 3964
3965 ranges.num_reader_wm_sets = i + 1;
3966 }
7ed4e635 3967
5d36f783
JL		 3968 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3969 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3970 }
7ed4e635
HW		 3971
3972 ranges.num_writer_wm_sets = 1;
3973
3974 ranges.writer_wm_sets[0].wm_inst = 0;
3975 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3976 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3977 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3978 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3979
3980 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
3981 if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
3982 pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);
3983 }
3984
3985 init_data.ctx = dc->ctx;
3986 pool->base.irqs = dal_irq_service_dcn20_create(&init_data);
3987 if (!pool->base.irqs)
3988 goto create_fail;
3989
3990 /* mem input -> ipp -> dpp -> opp -> TG */
3991 for (i = 0; i < pool->base.pipe_count; i++) {
3992 pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
3993 if (pool->base.hubps[i] == NULL) {
3994 BREAK_TO_DEBUGGER();
3995 dm_error(
3996 "DC: failed to create memory input!\n");
3997 goto create_fail;
3998 }
3999
4000 pool->base.ipps[i] = dcn20_ipp_create(ctx, i);
4001 if (pool->base.ipps[i] == NULL) {
4002 BREAK_TO_DEBUGGER();
4003 dm_error(
4004 "DC: failed to create input pixel processor!\n");
4005 goto create_fail;
4006 }
4007
4008 pool->base.dpps[i] = dcn20_dpp_create(ctx, i);
4009 if (pool->base.dpps[i] == NULL) {
4010 BREAK_TO_DEBUGGER();
4011 dm_error(
4012 "DC: failed to create dpps!\n");
4013 goto create_fail;
4014 }
4015 }
4016 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
4017 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i);
4018 if (pool->base.engines[i] == NULL) {
4019 BREAK_TO_DEBUGGER();
4020 dm_error(
4021 "DC:failed to create aux engine!!\n");
4022 goto create_fail;
4023 }
4024 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i);
4025 if (pool->base.hw_i2cs[i] == NULL) {
4026 BREAK_TO_DEBUGGER();
4027 dm_error(
4028 "DC:failed to create hw i2c!!\n");
4029 goto create_fail;
4030 }
4031 pool->base.sw_i2cs[i] = NULL;
4032 }
4033
4034 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
4035 pool->base.opps[i] = dcn20_opp_create(ctx, i);
4036 if (pool->base.opps[i] == NULL) {
4037 BREAK_TO_DEBUGGER();
4038 dm_error(
4039 "DC: failed to create output pixel processor!\n");
4040 goto create_fail;
4041 }
4042 }
4043
4044 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
4045 pool->base.timing_generators[i] = dcn20_timing_generator_create(
4046 ctx, i);
4047 if (pool->base.timing_generators[i] == NULL) {
4048 BREAK_TO_DEBUGGER();
4049 dm_error("DC: failed to create tg!\n");
4050 goto create_fail;
4051 }
4052 }
4053
4054 pool->base.timing_generator_count = i;
4055
4056 pool->base.mpc = dcn20_mpc_create(ctx);
4057 if (pool->base.mpc == NULL) {
4058 BREAK_TO_DEBUGGER();
4059 dm_error("DC: failed to create mpc!\n");
4060 goto create_fail;
4061 }
4062
4063 pool->base.hubbub = dcn20_hubbub_create(ctx);
4064 if (pool->base.hubbub == NULL) {
4065 BREAK_TO_DEBUGGER();
4066 dm_error("DC: failed to create hubbub!\n");
4067 goto create_fail;
4068 }
4069
97bda032
HW		 4070 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
4071 pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
4072 if (pool->base.dscs[i] == NULL) {
4073 BREAK_TO_DEBUGGER();
4074 dm_error("DC: failed to create display stream compressor %d!\n", i);
4075 goto create_fail;
4076 }
4077 }
7ed4e635 4078
bb21290f
CL		 4079 if (!dcn20_dwbc_create(ctx, &pool->base)) {
4080 BREAK_TO_DEBUGGER();
4081 dm_error("DC: failed to create dwbc!\n");
4082 goto create_fail;
4083 }
4084 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
4085 BREAK_TO_DEBUGGER();
4086 dm_error("DC: failed to create mcif_wb!\n");
4087 goto create_fail;
4088 }
4089
7ed4e635
HW		 4090 if (!resource_construct(num_virtual_links, dc, &pool->base,
4091 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
4092 &res_create_funcs : &res_create_maximus_funcs)))
4093 goto create_fail;
4094
4095 dcn20_hw_sequencer_construct(dc);
4096
3c9de4da
AL		 4097 // IF NV12, set PG function pointer to NULL. It's not that
4098 // PG isn't supported for NV12, it's that we don't want to
4099 // program the registers because that will cause more power
4100 // to be consumed. We could have created dcn20_init_hw to get
4101 // the same effect by checking ASIC rev, but there was a
4102 // request at some point to not check ASIC rev on hw sequencer.
15ce104c 4103 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
3c9de4da 4104 dc->hwseq->funcs.enable_power_gating_plane = NULL;
15ce104c
AL		 4105 dc->debug.disable_dpp_power_gate = true;
4106 dc->debug.disable_hubp_power_gate = true;
4107 }
4108
3c9de4da 4109
7ed4e635
HW		 4110 dc->caps.max_planes = pool->base.pipe_count;
4111
4112 for (i = 0; i < dc->caps.max_planes; ++i)
4113 dc->caps.planes[i] = plane_cap;
4114
4115 dc->cap_funcs = cap_funcs;
4116
d9a07577
JL		 4117 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
4118 ddc_init_data.ctx = dc->ctx;
4119 ddc_init_data.link = NULL;
4120 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
4121 ddc_init_data.id.enum_id = 0;
4122 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
4123 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
4124 } else {
4125 pool->base.oem_device = NULL;
4126 }
4127
7a8a3430 4128 DC_FP_END();
7ed4e635
HW		 4129 return true;
4130
4131create_fail:
4132
7a8a3430 4133 DC_FP_END();
d9e32672 4134 dcn20_resource_destruct(pool);
7ed4e635
HW		 4135
4136 return false;
4137}
4138
4139struct resource_pool *dcn20_create_resource_pool(
4140 const struct dc_init_data *init_data,
4141 struct dc *dc)
4142{
4143 struct dcn20_resource_pool *pool =
4144 kzalloc(sizeof(struct dcn20_resource_pool), GFP_KERNEL);
4145
4146 if (!pool)
4147 return NULL;
4148
d9e32672 4149 if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool))
7ed4e635
HW		 4150 return &pool->base;
4151
4152 BREAK_TO_DEBUGGER();
4153 kfree(pool);
4154 return NULL;
4155}
Linux 6.x block layer and io_uring tree(s)