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drm/amd/display: Add DP-HDMI FRL PCON SST Support in DM
[linux-block.git] / drivers / gpu / drm / amd / display / dc / dcn20 / dcn20_resource.c
CommitLineData
7ed4e635
HW		 1/*
2* Copyright 2016 Advanced Micro Devices, Inc.
6ca3928d 3 * Copyright 2019 Raptor Engineering, LLC
7ed4e635
HW		 4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
d7929c1e
AD		 27#include <linux/slab.h>
28
7ed4e635
HW		 29#include "dm_services.h"
30#include "dc.h"
31
78c77382
AK		 32#include "dcn20_init.h"
33
7ed4e635
HW		 34#include "resource.h"
35#include "include/irq_service_interface.h"
36#include "dcn20/dcn20_resource.h"
37
ee373411 38#include "dml/dcn20/dcn20_fpu.h"
c8b3538d 39
7ed4e635
HW		 40#include "dcn10/dcn10_hubp.h"
41#include "dcn10/dcn10_ipp.h"
42#include "dcn20_hubbub.h"
43#include "dcn20_mpc.h"
44#include "dcn20_hubp.h"
45#include "irq/dcn20/irq_service_dcn20.h"
46#include "dcn20_dpp.h"
47#include "dcn20_optc.h"
48#include "dcn20_hwseq.h"
49#include "dce110/dce110_hw_sequencer.h"
278141f5 50#include "dcn10/dcn10_resource.h"
7ed4e635
HW		 51#include "dcn20_opp.h"
52
97bda032 53#include "dcn20_dsc.h"
97bda032 54
7ed4e635
HW		 55#include "dcn20_link_encoder.h"
56#include "dcn20_stream_encoder.h"
57#include "dce/dce_clock_source.h"
58#include "dce/dce_audio.h"
59#include "dce/dce_hwseq.h"
60#include "virtual/virtual_stream_encoder.h"
61#include "dce110/dce110_resource.h"
62#include "dml/display_mode_vba.h"
63#include "dcn20_dccg.h"
64#include "dcn20_vmid.h"
d9a07577 65#include "dc_link_ddc.h"
f01ee019 66#include "dc_link_dp.h"
d4caa72e 67#include "dce/dce_panel_cntl.h"
7ed4e635
HW		 68
69#include "navi10_ip_offset.h"
70
71#include "dcn/dcn_2_0_0_offset.h"
72#include "dcn/dcn_2_0_0_sh_mask.h"
a771ded8
RL		 73#include "dpcs/dpcs_2_0_0_offset.h"
74#include "dpcs/dpcs_2_0_0_sh_mask.h"
7ed4e635
HW		 75
76#include "nbio/nbio_2_3_offset.h"
77
bb21290f
CL		 78#include "dcn20/dcn20_dwb.h"
79#include "dcn20/dcn20_mmhubbub.h"
80
7ed4e635
HW		 81#include "mmhub/mmhub_2_0_0_offset.h"
82#include "mmhub/mmhub_2_0_0_sh_mask.h"
83
84#include "reg_helper.h"
85#include "dce/dce_abm.h"
86#include "dce/dce_dmcu.h"
87#include "dce/dce_aux.h"
88#include "dce/dce_i2c.h"
89#include "vm_helper.h"
64d283cb 90#include "link_enc_cfg.h"
7ed4e635
HW		 91
92#include "amdgpu_socbb.h"
93
7ed4e635
HW		 94#define DC_LOGGER_INIT(logger)
95
96struct _vcs_dpi_ip_params_st dcn2_0_ip = {
97 .odm_capable = 1,
98 .gpuvm_enable = 0,
99 .hostvm_enable = 0,
100 .gpuvm_max_page_table_levels = 4,
101 .hostvm_max_page_table_levels = 4,
102 .hostvm_cached_page_table_levels = 0,
103 .pte_group_size_bytes = 2048,
97bda032 104 .num_dsc = 6,
7ed4e635
HW		 105 .rob_buffer_size_kbytes = 168,
106 .det_buffer_size_kbytes = 164,
107 .dpte_buffer_size_in_pte_reqs_luma = 84,
108 .pde_proc_buffer_size_64k_reqs = 48,
109 .dpp_output_buffer_pixels = 2560,
110 .opp_output_buffer_lines = 1,
111 .pixel_chunk_size_kbytes = 8,
112 .pte_chunk_size_kbytes = 2,
113 .meta_chunk_size_kbytes = 2,
114 .writeback_chunk_size_kbytes = 2,
115 .line_buffer_size_bits = 789504,
116 .is_line_buffer_bpp_fixed = 0,
117 .line_buffer_fixed_bpp = 0,
118 .dcc_supported = true,
234cc26f 119 .max_line_buffer_lines = 12,
7ed4e635
HW		 120 .writeback_luma_buffer_size_kbytes = 12,
121 .writeback_chroma_buffer_size_kbytes = 8,
122 .writeback_chroma_line_buffer_width_pixels = 4,
123 .writeback_max_hscl_ratio = 1,
124 .writeback_max_vscl_ratio = 1,
125 .writeback_min_hscl_ratio = 1,
126 .writeback_min_vscl_ratio = 1,
127 .writeback_max_hscl_taps = 12,
128 .writeback_max_vscl_taps = 12,
129 .writeback_line_buffer_luma_buffer_size = 0,
130 .writeback_line_buffer_chroma_buffer_size = 14643,
131 .cursor_buffer_size = 8,
132 .cursor_chunk_size = 2,
133 .max_num_otg = 6,
134 .max_num_dpp = 6,
135 .max_num_wb = 1,
136 .max_dchub_pscl_bw_pix_per_clk = 4,
137 .max_pscl_lb_bw_pix_per_clk = 2,
138 .max_lb_vscl_bw_pix_per_clk = 4,
139 .max_vscl_hscl_bw_pix_per_clk = 4,
140 .max_hscl_ratio = 8,
141 .max_vscl_ratio = 8,
142 .hscl_mults = 4,
143 .vscl_mults = 4,
144 .max_hscl_taps = 8,
145 .max_vscl_taps = 8,
146 .dispclk_ramp_margin_percent = 1,
147 .underscan_factor = 1.10,
148 .min_vblank_lines = 32, //
149 .dppclk_delay_subtotal = 77, //
150 .dppclk_delay_scl_lb_only = 16,
151 .dppclk_delay_scl = 50,
152 .dppclk_delay_cnvc_formatter = 8,
153 .dppclk_delay_cnvc_cursor = 6,
154 .dispclk_delay_subtotal = 87, //
155 .dcfclk_cstate_latency = 10, // SRExitTime
156 .max_inter_dcn_tile_repeaters = 8,
7ed4e635
HW		 157 .xfc_supported = true,
158 .xfc_fill_bw_overhead_percent = 10.0,
159 .xfc_fill_constant_bytes = 0,
8f174fdb 160 .number_of_cursors = 1,
7ed4e635
HW		 161};
162
dfd84d90 163static struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {
a2c63407
Z		 164 .odm_capable = 1,
165 .gpuvm_enable = 0,
166 .hostvm_enable = 0,
167 .gpuvm_max_page_table_levels = 4,
168 .hostvm_max_page_table_levels = 4,
169 .hostvm_cached_page_table_levels = 0,
170 .num_dsc = 5,
171 .rob_buffer_size_kbytes = 168,
172 .det_buffer_size_kbytes = 164,
173 .dpte_buffer_size_in_pte_reqs_luma = 84,
174 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
175 .dpp_output_buffer_pixels = 2560,
176 .opp_output_buffer_lines = 1,
177 .pixel_chunk_size_kbytes = 8,
178 .pte_enable = 1,
179 .max_page_table_levels = 4,
180 .pte_chunk_size_kbytes = 2,
181 .meta_chunk_size_kbytes = 2,
182 .writeback_chunk_size_kbytes = 2,
183 .line_buffer_size_bits = 789504,
184 .is_line_buffer_bpp_fixed = 0,
185 .line_buffer_fixed_bpp = 0,
186 .dcc_supported = true,
234cc26f 187 .max_line_buffer_lines = 12,
a2c63407
Z		 188 .writeback_luma_buffer_size_kbytes = 12,
189 .writeback_chroma_buffer_size_kbytes = 8,
190 .writeback_chroma_line_buffer_width_pixels = 4,
191 .writeback_max_hscl_ratio = 1,
192 .writeback_max_vscl_ratio = 1,
193 .writeback_min_hscl_ratio = 1,
194 .writeback_min_vscl_ratio = 1,
195 .writeback_max_hscl_taps = 12,
196 .writeback_max_vscl_taps = 12,
197 .writeback_line_buffer_luma_buffer_size = 0,
198 .writeback_line_buffer_chroma_buffer_size = 14643,
199 .cursor_buffer_size = 8,
200 .cursor_chunk_size = 2,
201 .max_num_otg = 5,
202 .max_num_dpp = 5,
203 .max_num_wb = 1,
204 .max_dchub_pscl_bw_pix_per_clk = 4,
205 .max_pscl_lb_bw_pix_per_clk = 2,
206 .max_lb_vscl_bw_pix_per_clk = 4,
207 .max_vscl_hscl_bw_pix_per_clk = 4,
208 .max_hscl_ratio = 8,
209 .max_vscl_ratio = 8,
210 .hscl_mults = 4,
211 .vscl_mults = 4,
212 .max_hscl_taps = 8,
213 .max_vscl_taps = 8,
214 .dispclk_ramp_margin_percent = 1,
215 .underscan_factor = 1.10,
216 .min_vblank_lines = 32, //
217 .dppclk_delay_subtotal = 77, //
218 .dppclk_delay_scl_lb_only = 16,
219 .dppclk_delay_scl = 50,
220 .dppclk_delay_cnvc_formatter = 8,
221 .dppclk_delay_cnvc_cursor = 6,
222 .dispclk_delay_subtotal = 87, //
223 .dcfclk_cstate_latency = 10, // SRExitTime
224 .max_inter_dcn_tile_repeaters = 8,
225 .xfc_supported = true,
226 .xfc_fill_bw_overhead_percent = 10.0,
227 .xfc_fill_constant_bytes = 0,
8f174fdb
YS		 228 .ptoi_supported = 0,
229 .number_of_cursors = 1,
a2c63407
Z		 230};
231
dfd84d90 232static struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
fb6959ae
NK		 233 /* Defaults that get patched on driver load from firmware. */
234 .clock_limits = {
235 {
236 .state = 0,
237 .dcfclk_mhz = 560.0,
238 .fabricclk_mhz = 560.0,
239 .dispclk_mhz = 513.0,
240 .dppclk_mhz = 513.0,
241 .phyclk_mhz = 540.0,
242 .socclk_mhz = 560.0,
243 .dscclk_mhz = 171.0,
244 .dram_speed_mts = 8960.0,
245 },
246 {
247 .state = 1,
248 .dcfclk_mhz = 694.0,
249 .fabricclk_mhz = 694.0,
250 .dispclk_mhz = 642.0,
251 .dppclk_mhz = 642.0,
252 .phyclk_mhz = 600.0,
253 .socclk_mhz = 694.0,
254 .dscclk_mhz = 214.0,
255 .dram_speed_mts = 11104.0,
256 },
257 {
258 .state = 2,
259 .dcfclk_mhz = 875.0,
260 .fabricclk_mhz = 875.0,
261 .dispclk_mhz = 734.0,
262 .dppclk_mhz = 734.0,
263 .phyclk_mhz = 810.0,
264 .socclk_mhz = 875.0,
265 .dscclk_mhz = 245.0,
266 .dram_speed_mts = 14000.0,
267 },
268 {
269 .state = 3,
270 .dcfclk_mhz = 1000.0,
271 .fabricclk_mhz = 1000.0,
272 .dispclk_mhz = 1100.0,
273 .dppclk_mhz = 1100.0,
274 .phyclk_mhz = 810.0,
275 .socclk_mhz = 1000.0,
276 .dscclk_mhz = 367.0,
277 .dram_speed_mts = 16000.0,
278 },
279 {
280 .state = 4,
281 .dcfclk_mhz = 1200.0,
282 .fabricclk_mhz = 1200.0,
283 .dispclk_mhz = 1284.0,
284 .dppclk_mhz = 1284.0,
285 .phyclk_mhz = 810.0,
286 .socclk_mhz = 1200.0,
287 .dscclk_mhz = 428.0,
288 .dram_speed_mts = 16000.0,
289 },
290 /*Extra state, no dispclk ramping*/
291 {
292 .state = 5,
293 .dcfclk_mhz = 1200.0,
294 .fabricclk_mhz = 1200.0,
295 .dispclk_mhz = 1284.0,
296 .dppclk_mhz = 1284.0,
297 .phyclk_mhz = 810.0,
298 .socclk_mhz = 1200.0,
299 .dscclk_mhz = 428.0,
300 .dram_speed_mts = 16000.0,
301 },
302 },
303 .num_states = 5,
910f1601
AD		 304 .sr_exit_time_us = 8.6,
305 .sr_enter_plus_exit_time_us = 10.9,
fb6959ae
NK		 306 .urgent_latency_us = 4.0,
307 .urgent_latency_pixel_data_only_us = 4.0,
308 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
309 .urgent_latency_vm_data_only_us = 4.0,
310 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
311 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
312 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
313 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
314 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
315 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
316 .max_avg_sdp_bw_use_normal_percent = 40.0,
317 .max_avg_dram_bw_use_normal_percent = 40.0,
318 .writeback_latency_us = 12.0,
319 .ideal_dram_bw_after_urgent_percent = 40.0,
320 .max_request_size_bytes = 256,
321 .dram_channel_width_bytes = 2,
322 .fabric_datapath_to_dcn_data_return_bytes = 64,
323 .dcn_downspread_percent = 0.5,
324 .downspread_percent = 0.38,
325 .dram_page_open_time_ns = 50.0,
326 .dram_rw_turnaround_time_ns = 17.5,
327 .dram_return_buffer_per_channel_bytes = 8192,
328 .round_trip_ping_latency_dcfclk_cycles = 131,
329 .urgent_out_of_order_return_per_channel_bytes = 256,
330 .channel_interleave_bytes = 256,
331 .num_banks = 8,
332 .num_chans = 16,
333 .vmm_page_size_bytes = 4096,
334 .dram_clock_change_latency_us = 404.0,
335 .dummy_pstate_latency_us = 5.0,
336 .writeback_dram_clock_change_latency_us = 23.0,
337 .return_bus_width_bytes = 64,
338 .dispclk_dppclk_vco_speed_mhz = 3850,
339 .xfc_bus_transport_time_us = 20,
340 .xfc_xbuf_latency_tolerance_us = 4,
341 .use_urgent_burst_bw = 0
342};
7ed4e635 343
dfd84d90 344static struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = {
e1ab4a91
ML		 345 .clock_limits = {
346 {
347 .state = 0,
348 .dcfclk_mhz = 560.0,
349 .fabricclk_mhz = 560.0,
350 .dispclk_mhz = 513.0,
351 .dppclk_mhz = 513.0,
352 .phyclk_mhz = 540.0,
353 .socclk_mhz = 560.0,
354 .dscclk_mhz = 171.0,
355 .dram_speed_mts = 8960.0,
356 },
357 {
358 .state = 1,
359 .dcfclk_mhz = 694.0,
360 .fabricclk_mhz = 694.0,
361 .dispclk_mhz = 642.0,
362 .dppclk_mhz = 642.0,
363 .phyclk_mhz = 600.0,
364 .socclk_mhz = 694.0,
365 .dscclk_mhz = 214.0,
366 .dram_speed_mts = 11104.0,
367 },
368 {
369 .state = 2,
370 .dcfclk_mhz = 875.0,
371 .fabricclk_mhz = 875.0,
372 .dispclk_mhz = 734.0,
373 .dppclk_mhz = 734.0,
374 .phyclk_mhz = 810.0,
375 .socclk_mhz = 875.0,
376 .dscclk_mhz = 245.0,
377 .dram_speed_mts = 14000.0,
378 },
379 {
380 .state = 3,
381 .dcfclk_mhz = 1000.0,
382 .fabricclk_mhz = 1000.0,
383 .dispclk_mhz = 1100.0,
384 .dppclk_mhz = 1100.0,
385 .phyclk_mhz = 810.0,
386 .socclk_mhz = 1000.0,
387 .dscclk_mhz = 367.0,
388 .dram_speed_mts = 16000.0,
389 },
390 {
391 .state = 4,
392 .dcfclk_mhz = 1200.0,
393 .fabricclk_mhz = 1200.0,
394 .dispclk_mhz = 1284.0,
395 .dppclk_mhz = 1284.0,
396 .phyclk_mhz = 810.0,
397 .socclk_mhz = 1200.0,
398 .dscclk_mhz = 428.0,
399 .dram_speed_mts = 16000.0,
400 },
401 /*Extra state, no dispclk ramping*/
402 {
403 .state = 5,
404 .dcfclk_mhz = 1200.0,
405 .fabricclk_mhz = 1200.0,
406 .dispclk_mhz = 1284.0,
407 .dppclk_mhz = 1284.0,
408 .phyclk_mhz = 810.0,
409 .socclk_mhz = 1200.0,
410 .dscclk_mhz = 428.0,
411 .dram_speed_mts = 16000.0,
412 },
413 },
414 .num_states = 5,
a354b942
JL		 415 .sr_exit_time_us = 11.6,
416 .sr_enter_plus_exit_time_us = 13.9,
e1ab4a91
ML		 417 .urgent_latency_us = 4.0,
418 .urgent_latency_pixel_data_only_us = 4.0,
419 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
420 .urgent_latency_vm_data_only_us = 4.0,
421 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
422 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
423 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
424 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
425 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
426 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
427 .max_avg_sdp_bw_use_normal_percent = 40.0,
428 .max_avg_dram_bw_use_normal_percent = 40.0,
429 .writeback_latency_us = 12.0,
430 .ideal_dram_bw_after_urgent_percent = 40.0,
431 .max_request_size_bytes = 256,
432 .dram_channel_width_bytes = 2,
433 .fabric_datapath_to_dcn_data_return_bytes = 64,
434 .dcn_downspread_percent = 0.5,
435 .downspread_percent = 0.38,
436 .dram_page_open_time_ns = 50.0,
437 .dram_rw_turnaround_time_ns = 17.5,
438 .dram_return_buffer_per_channel_bytes = 8192,
439 .round_trip_ping_latency_dcfclk_cycles = 131,
440 .urgent_out_of_order_return_per_channel_bytes = 256,
441 .channel_interleave_bytes = 256,
442 .num_banks = 8,
443 .num_chans = 8,
444 .vmm_page_size_bytes = 4096,
445 .dram_clock_change_latency_us = 404.0,
446 .dummy_pstate_latency_us = 5.0,
447 .writeback_dram_clock_change_latency_us = 23.0,
448 .return_bus_width_bytes = 64,
449 .dispclk_dppclk_vco_speed_mhz = 3850,
450 .xfc_bus_transport_time_us = 20,
451 .xfc_xbuf_latency_tolerance_us = 4,
452 .use_urgent_burst_bw = 0
453};
454
dfd84d90 455static struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
7ed4e635
HW		 456
457#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
458 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
459 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
460 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
461 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
462 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
463 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
464 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
465 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
466 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
467 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
468 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
469 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
470 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
471 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
472#endif
473
474
475enum dcn20_clk_src_array_id {
476 DCN20_CLK_SRC_PLL0,
477 DCN20_CLK_SRC_PLL1,
478 DCN20_CLK_SRC_PLL2,
479 DCN20_CLK_SRC_PLL3,
480 DCN20_CLK_SRC_PLL4,
481 DCN20_CLK_SRC_PLL5,
482 DCN20_CLK_SRC_TOTAL
483};
484
485/* begin *********************
486 * macros to expend register list macro defined in HW object header file */
487
488/* DCN */
489/* TODO awful hack. fixup dcn20_dwb.h */
490#undef BASE_INNER
491#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
492
493#define BASE(seg) BASE_INNER(seg)
494
495#define SR(reg_name)\
496 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
497 mm ## reg_name
498
499#define SRI(reg_name, block, id)\
500 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
501 mm ## block ## id ## _ ## reg_name
502
503#define SRIR(var_name, reg_name, block, id)\
504 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
505 mm ## block ## id ## _ ## reg_name
506
507#define SRII(reg_name, block, id)\
508 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
509 mm ## block ## id ## _ ## reg_name
510
511#define DCCG_SRII(reg_name, block, id)\
512 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
513 mm ## block ## id ## _ ## reg_name
514
1e461c37
AC		 515#define VUPDATE_SRII(reg_name, block, id)\
516 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
517 mm ## reg_name ## _ ## block ## id
518
7ed4e635
HW		 519/* NBIO */
520#define NBIO_BASE_INNER(seg) \
521 NBIO_BASE__INST0_SEG ## seg
522
523#define NBIO_BASE(seg) \
524 NBIO_BASE_INNER(seg)
525
526#define NBIO_SR(reg_name)\
527 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
528 mm ## reg_name
529
530/* MMHUB */
531#define MMHUB_BASE_INNER(seg) \
532 MMHUB_BASE__INST0_SEG ## seg
533
534#define MMHUB_BASE(seg) \
535 MMHUB_BASE_INNER(seg)
536
537#define MMHUB_SR(reg_name)\
538 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
539 mmMM ## reg_name
540
541static const struct bios_registers bios_regs = {
542 NBIO_SR(BIOS_SCRATCH_3),
543 NBIO_SR(BIOS_SCRATCH_6)
544};
545
546#define clk_src_regs(index, pllid)\
547[index] = {\
548 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
549}
550
551static const struct dce110_clk_src_regs clk_src_regs[] = {
552 clk_src_regs(0, A),
553 clk_src_regs(1, B),
554 clk_src_regs(2, C),
555 clk_src_regs(3, D),
556 clk_src_regs(4, E),
557 clk_src_regs(5, F)
558};
559
560static const struct dce110_clk_src_shift cs_shift = {
561 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
562};
563
564static const struct dce110_clk_src_mask cs_mask = {
565 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
566};
567
568static const struct dce_dmcu_registers dmcu_regs = {
569 DMCU_DCN10_REG_LIST()
570};
571
572static const struct dce_dmcu_shift dmcu_shift = {
573 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
574};
575
576static const struct dce_dmcu_mask dmcu_mask = {
577 DMCU_MASK_SH_LIST_DCN10(_MASK)
578};
d7c29549 579
7ed4e635 580static const struct dce_abm_registers abm_regs = {
d7c29549 581 ABM_DCN20_REG_LIST()
7ed4e635
HW		 582};
583
584static const struct dce_abm_shift abm_shift = {
d7c29549 585 ABM_MASK_SH_LIST_DCN20(__SHIFT)
7ed4e635
HW		 586};
587
588static const struct dce_abm_mask abm_mask = {
d7c29549 589 ABM_MASK_SH_LIST_DCN20(_MASK)
7ed4e635 590};
d7c29549 591
7ed4e635
HW		 592#define audio_regs(id)\
593[id] = {\
594 AUD_COMMON_REG_LIST(id)\
595}
596
597static const struct dce_audio_registers audio_regs[] = {
598 audio_regs(0),
599 audio_regs(1),
600 audio_regs(2),
601 audio_regs(3),
602 audio_regs(4),
603 audio_regs(5),
604 audio_regs(6),
605};
606
607#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
608 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
609 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
610 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
611
612static const struct dce_audio_shift audio_shift = {
613 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
614};
615
54a9bcb0 616static const struct dce_audio_mask audio_mask = {
7ed4e635
HW		 617 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
618};
619
620#define stream_enc_regs(id)\
621[id] = {\
622 SE_DCN2_REG_LIST(id)\
623}
624
625static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
626 stream_enc_regs(0),
627 stream_enc_regs(1),
628 stream_enc_regs(2),
629 stream_enc_regs(3),
630 stream_enc_regs(4),
631 stream_enc_regs(5),
632};
633
634static const struct dcn10_stream_encoder_shift se_shift = {
635 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
636};
637
638static const struct dcn10_stream_encoder_mask se_mask = {
639 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
640};
641
642
643#define aux_regs(id)\
644[id] = {\
645 DCN2_AUX_REG_LIST(id)\
646}
647
648static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
649 aux_regs(0),
650 aux_regs(1),
651 aux_regs(2),
652 aux_regs(3),
653 aux_regs(4),
654 aux_regs(5)
655};
656
657#define hpd_regs(id)\
658[id] = {\
659 HPD_REG_LIST(id)\
660}
661
662static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
663 hpd_regs(0),
664 hpd_regs(1),
665 hpd_regs(2),
666 hpd_regs(3),
667 hpd_regs(4),
668 hpd_regs(5)
669};
670
671#define link_regs(id, phyid)\
672[id] = {\
673 LE_DCN10_REG_LIST(id), \
674 UNIPHY_DCN2_REG_LIST(phyid), \
a771ded8 675 DPCS_DCN2_REG_LIST(id), \
7ed4e635
HW		 676 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
677}
678
679static const struct dcn10_link_enc_registers link_enc_regs[] = {
680 link_regs(0, A),
681 link_regs(1, B),
682 link_regs(2, C),
683 link_regs(3, D),
684 link_regs(4, E),
685 link_regs(5, F)
686};
687
688static const struct dcn10_link_enc_shift le_shift = {
a771ded8
RL		 689 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
690 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
7ed4e635
HW		 691};
692
693static const struct dcn10_link_enc_mask le_mask = {
a771ded8
RL		 694 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
695 DPCS_DCN2_MASK_SH_LIST(_MASK)
7ed4e635
HW		 696};
697
d4caa72e
AK		 698static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
699 { DCN_PANEL_CNTL_REG_LIST() }
904fb6e0
AK		 700};
701
d4caa72e
AK		 702static const struct dce_panel_cntl_shift panel_cntl_shift = {
703 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
904fb6e0
AK		 704};
705
d4caa72e
AK		 706static const struct dce_panel_cntl_mask panel_cntl_mask = {
707 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
904fb6e0
AK		 708};
709
7ed4e635
HW		 710#define ipp_regs(id)\
711[id] = {\
712 IPP_REG_LIST_DCN20(id),\
713}
714
715static const struct dcn10_ipp_registers ipp_regs[] = {
716 ipp_regs(0),
717 ipp_regs(1),
718 ipp_regs(2),
719 ipp_regs(3),
720 ipp_regs(4),
721 ipp_regs(5),
722};
723
724static const struct dcn10_ipp_shift ipp_shift = {
725 IPP_MASK_SH_LIST_DCN20(__SHIFT)
726};
727
728static const struct dcn10_ipp_mask ipp_mask = {
729 IPP_MASK_SH_LIST_DCN20(_MASK),
730};
731
732#define opp_regs(id)\
733[id] = {\
734 OPP_REG_LIST_DCN20(id),\
735}
736
737static const struct dcn20_opp_registers opp_regs[] = {
738 opp_regs(0),
739 opp_regs(1),
740 opp_regs(2),
741 opp_regs(3),
742 opp_regs(4),
743 opp_regs(5),
744};
745
746static const struct dcn20_opp_shift opp_shift = {
747 OPP_MASK_SH_LIST_DCN20(__SHIFT)
748};
749
750static const struct dcn20_opp_mask opp_mask = {
751 OPP_MASK_SH_LIST_DCN20(_MASK)
752};
753
754#define aux_engine_regs(id)\
755[id] = {\
756 AUX_COMMON_REG_LIST0(id), \
757 .AUXN_IMPCAL = 0, \
758 .AUXP_IMPCAL = 0, \
759 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
760}
761
762static const struct dce110_aux_registers aux_engine_regs[] = {
763 aux_engine_regs(0),
764 aux_engine_regs(1),
765 aux_engine_regs(2),
766 aux_engine_regs(3),
767 aux_engine_regs(4),
768 aux_engine_regs(5)
769};
770
771#define tf_regs(id)\
772[id] = {\
773 TF_REG_LIST_DCN20(id),\
d9eb70ae 774 TF_REG_LIST_DCN20_COMMON_APPEND(id),\
7ed4e635
HW		 775}
776
777static const struct dcn2_dpp_registers tf_regs[] = {
778 tf_regs(0),
779 tf_regs(1),
780 tf_regs(2),
781 tf_regs(3),
782 tf_regs(4),
783 tf_regs(5),
784};
785
786static const struct dcn2_dpp_shift tf_shift = {
d56eaa7c 787 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
c1e34175 788 TF_DEBUG_REG_LIST_SH_DCN20
7ed4e635
HW		 789};
790
791static const struct dcn2_dpp_mask tf_mask = {
d56eaa7c 792 TF_REG_LIST_SH_MASK_DCN20(_MASK),
c1e34175 793 TF_DEBUG_REG_LIST_MASK_DCN20
7ed4e635
HW		 794};
795
bb21290f
CL		 796#define dwbc_regs_dcn2(id)\
797[id] = {\
798 DWBC_COMMON_REG_LIST_DCN2_0(id),\
799 }
800
801static const struct dcn20_dwbc_registers dwbc20_regs[] = {
802 dwbc_regs_dcn2(0),
803};
804
805static const struct dcn20_dwbc_shift dwbc20_shift = {
806 DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
807};
808
809static const struct dcn20_dwbc_mask dwbc20_mask = {
810 DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
811};
812
813#define mcif_wb_regs_dcn2(id)\
814[id] = {\
815 MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\
816 }
817
818static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {
819 mcif_wb_regs_dcn2(0),
820};
821
822static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {
823 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
824};
825
826static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {
827 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
828};
829
7ed4e635
HW		 830static const struct dcn20_mpc_registers mpc_regs = {
831 MPC_REG_LIST_DCN2_0(0),
832 MPC_REG_LIST_DCN2_0(1),
833 MPC_REG_LIST_DCN2_0(2),
834 MPC_REG_LIST_DCN2_0(3),
835 MPC_REG_LIST_DCN2_0(4),
836 MPC_REG_LIST_DCN2_0(5),
837 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
838 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
839 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
840 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
841 MPC_OUT_MUX_REG_LIST_DCN2_0(4),
842 MPC_OUT_MUX_REG_LIST_DCN2_0(5),
e8027e08 843 MPC_DBG_REG_LIST_DCN2_0()
7ed4e635
HW		 844};
845
846static const struct dcn20_mpc_shift mpc_shift = {
c1e34175
NA		 847 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
848 MPC_DEBUG_REG_LIST_SH_DCN20
7ed4e635
HW		 849};
850
851static const struct dcn20_mpc_mask mpc_mask = {
c1e34175
NA		 852 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
853 MPC_DEBUG_REG_LIST_MASK_DCN20
7ed4e635
HW		 854};
855
856#define tg_regs(id)\
857[id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
858
859
860static const struct dcn_optc_registers tg_regs[] = {
861 tg_regs(0),
862 tg_regs(1),
863 tg_regs(2),
864 tg_regs(3),
865 tg_regs(4),
866 tg_regs(5)
867};
868
869static const struct dcn_optc_shift tg_shift = {
870 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
871};
872
873static const struct dcn_optc_mask tg_mask = {
874 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
875};
876
877#define hubp_regs(id)\
878[id] = {\
879 HUBP_REG_LIST_DCN20(id)\
880}
881
882static const struct dcn_hubp2_registers hubp_regs[] = {
883 hubp_regs(0),
884 hubp_regs(1),
885 hubp_regs(2),
886 hubp_regs(3),
887 hubp_regs(4),
888 hubp_regs(5)
889};
890
891static const struct dcn_hubp2_shift hubp_shift = {
892 HUBP_MASK_SH_LIST_DCN20(__SHIFT)
893};
894
895static const struct dcn_hubp2_mask hubp_mask = {
896 HUBP_MASK_SH_LIST_DCN20(_MASK)
897};
898
899static const struct dcn_hubbub_registers hubbub_reg = {
900 HUBBUB_REG_LIST_DCN20(0)
901};
902
903static const struct dcn_hubbub_shift hubbub_shift = {
904 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT)
905};
906
907static const struct dcn_hubbub_mask hubbub_mask = {
908 HUBBUB_MASK_SH_LIST_DCN20(_MASK)
909};
910
911#define vmid_regs(id)\
912[id] = {\
913 DCN20_VMID_REG_LIST(id)\
914}
915
916static const struct dcn_vmid_registers vmid_regs[] = {
917 vmid_regs(0),
918 vmid_regs(1),
919 vmid_regs(2),
920 vmid_regs(3),
921 vmid_regs(4),
922 vmid_regs(5),
923 vmid_regs(6),
924 vmid_regs(7),
925 vmid_regs(8),
926 vmid_regs(9),
927 vmid_regs(10),
928 vmid_regs(11),
929 vmid_regs(12),
930 vmid_regs(13),
931 vmid_regs(14),
932 vmid_regs(15)
933};
934
935static const struct dcn20_vmid_shift vmid_shifts = {
936 DCN20_VMID_MASK_SH_LIST(__SHIFT)
937};
938
939static const struct dcn20_vmid_mask vmid_masks = {
940 DCN20_VMID_MASK_SH_LIST(_MASK)
941};
942
8276dd87 943static const struct dce110_aux_registers_shift aux_shift = {
944 DCN_AUX_MASK_SH_LIST(__SHIFT)
945};
946
947static const struct dce110_aux_registers_mask aux_mask = {
948 DCN_AUX_MASK_SH_LIST(_MASK)
949};
950
bf7f5ac3
YMM		 951static int map_transmitter_id_to_phy_instance(
952 enum transmitter transmitter)
953{
954 switch (transmitter) {
955 case TRANSMITTER_UNIPHY_A:
956 return 0;
957 break;
958 case TRANSMITTER_UNIPHY_B:
959 return 1;
960 break;
961 case TRANSMITTER_UNIPHY_C:
962 return 2;
963 break;
964 case TRANSMITTER_UNIPHY_D:
965 return 3;
966 break;
967 case TRANSMITTER_UNIPHY_E:
968 return 4;
969 break;
970 case TRANSMITTER_UNIPHY_F:
971 return 5;
972 break;
973 default:
974 ASSERT(0);
975 return 0;
976 }
977}
8276dd87 978
97bda032
HW		 979#define dsc_regsDCN20(id)\
980[id] = {\
981 DSC_REG_LIST_DCN20(id)\
982}
983
984static const struct dcn20_dsc_registers dsc_regs[] = {
985 dsc_regsDCN20(0),
986 dsc_regsDCN20(1),
987 dsc_regsDCN20(2),
988 dsc_regsDCN20(3),
989 dsc_regsDCN20(4),
990 dsc_regsDCN20(5)
991};
992
993static const struct dcn20_dsc_shift dsc_shift = {
994 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
995};
996
997static const struct dcn20_dsc_mask dsc_mask = {
998 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
999};
7ed4e635
HW		 1000
1001static const struct dccg_registers dccg_regs = {
1002 DCCG_REG_LIST_DCN2()
1003};
1004
1005static const struct dccg_shift dccg_shift = {
1006 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
1007};
1008
1009static const struct dccg_mask dccg_mask = {
1010 DCCG_MASK_SH_LIST_DCN2(_MASK)
1011};
1012
1013static const struct resource_caps res_cap_nv10 = {
1014 .num_timing_generator = 6,
1015 .num_opp = 6,
1016 .num_video_plane = 6,
1017 .num_audio = 7,
1018 .num_stream_encoder = 6,
1019 .num_pll = 6,
9cbee6ef 1020 .num_dwb = 1,
7ed4e635
HW		 1021 .num_ddc = 6,
1022 .num_vmid = 16,
97bda032 1023 .num_dsc = 6,
7ed4e635
HW		 1024};
1025
1026static const struct dc_plane_cap plane_cap = {
1027 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
1028 .blends_with_above = true,
1029 .blends_with_below = true,
7ed4e635 1030 .per_pixel_alpha = true,
5b1b2f20
AD		 1031
1032 .pixel_format_support = {
1033 .argb8888 = true,
1034 .nv12 = true,
cbec6477
SW		 1035 .fp16 = true,
1036 .p010 = true
5b1b2f20
AD		 1037 },
1038
1039 .max_upscale_factor = {
1040 .argb8888 = 16000,
1041 .nv12 = 16000,
1042 .fp16 = 1
1043 },
1044
1045 .max_downscale_factor = {
1046 .argb8888 = 250,
1047 .nv12 = 250,
1048 .fp16 = 1
3b26ca2d
IK		 1049 },
1050 16,
1051 16
7ed4e635 1052};
2ebe1773
BL		 1053static const struct resource_caps res_cap_nv14 = {
1054 .num_timing_generator = 5,
1055 .num_opp = 5,
1056 .num_video_plane = 5,
1057 .num_audio = 6,
1058 .num_stream_encoder = 5,
1059 .num_pll = 5,
80df905d 1060 .num_dwb = 1,
2ebe1773 1061 .num_ddc = 5,
6bb27085
ZL		 1062 .num_vmid = 16,
1063 .num_dsc = 5,
2ebe1773 1064};
7ed4e635
HW		 1065
1066static const struct dc_debug_options debug_defaults_drv = {
f0a574c9 1067 .disable_dmcu = false,
7ed4e635
HW		 1068 .force_abm_enable = false,
1069 .timing_trace = false,
1070 .clock_trace = true,
1071 .disable_pplib_clock_request = true,
fd3b2e21 1072 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
4d25a0d5 1073 .force_single_disp_pipe_split = false,
7ed4e635
HW		 1074 .disable_dcc = DCC_ENABLE,
1075 .vsr_support = true,
1076 .performance_trace = false,
1077 .max_downscale_src_width = 5120,/*upto 5K*/
1078 .disable_pplib_wm_range = false,
1079 .scl_reset_length10 = true,
9e14d4f1 1080 .sanity_checks = false,
1a7d296d 1081 .underflow_assert_delay_us = 0xFFFFFFFF,
7ed4e635
HW		 1082};
1083
1084static const struct dc_debug_options debug_defaults_diags = {
f0a574c9 1085 .disable_dmcu = false,
7ed4e635
HW		 1086 .force_abm_enable = false,
1087 .timing_trace = true,
1088 .clock_trace = true,
1089 .disable_dpp_power_gate = true,
1090 .disable_hubp_power_gate = true,
1091 .disable_clock_gate = true,
1092 .disable_pplib_clock_request = true,
1093 .disable_pplib_wm_range = true,
1094 .disable_stutter = true,
1095 .scl_reset_length10 = true,
1a7d296d 1096 .underflow_assert_delay_us = 0xFFFFFFFF,
091018a5 1097 .enable_tri_buf = true,
7ed4e635
HW		 1098};
1099
1100void dcn20_dpp_destroy(struct dpp **dpp)
1101{
1102 kfree(TO_DCN20_DPP(*dpp));
1103 *dpp = NULL;
1104}
1105
1106struct dpp *dcn20_dpp_create(
1107 struct dc_context *ctx,
1108 uint32_t inst)
1109{
1110 struct dcn20_dpp *dpp =
3bb11050 1111 kzalloc(sizeof(struct dcn20_dpp), GFP_ATOMIC);
7ed4e635
HW		 1112
1113 if (!dpp)
1114 return NULL;
1115
1116 if (dpp2_construct(dpp, ctx, inst,
1117 &tf_regs[inst], &tf_shift, &tf_mask))
1118 return &dpp->base;
1119
1120 BREAK_TO_DEBUGGER();
1121 kfree(dpp);
1122 return NULL;
1123}
1124
1125struct input_pixel_processor *dcn20_ipp_create(
1126 struct dc_context *ctx, uint32_t inst)
1127{
1128 struct dcn10_ipp *ipp =
3bb11050 1129 kzalloc(sizeof(struct dcn10_ipp), GFP_ATOMIC);
7ed4e635
HW		 1130
1131 if (!ipp) {
1132 BREAK_TO_DEBUGGER();
1133 return NULL;
1134 }
1135
1136 dcn20_ipp_construct(ipp, ctx, inst,
1137 &ipp_regs[inst], &ipp_shift, &ipp_mask);
1138 return &ipp->base;
1139}
1140
1141
1142struct output_pixel_processor *dcn20_opp_create(
1143 struct dc_context *ctx, uint32_t inst)
1144{
1145 struct dcn20_opp *opp =
3bb11050 1146 kzalloc(sizeof(struct dcn20_opp), GFP_ATOMIC);
7ed4e635
HW		 1147
1148 if (!opp) {
1149 BREAK_TO_DEBUGGER();
1150 return NULL;
1151 }
1152
1153 dcn20_opp_construct(opp, ctx, inst,
1154 &opp_regs[inst], &opp_shift, &opp_mask);
1155 return &opp->base;
1156}
1157
1158struct dce_aux *dcn20_aux_engine_create(
1159 struct dc_context *ctx,
1160 uint32_t inst)
1161{
1162 struct aux_engine_dce110 *aux_engine =
3bb11050 1163 kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC);
7ed4e635
HW		 1164
1165 if (!aux_engine)
1166 return NULL;
1167
1168 dce110_aux_engine_construct(aux_engine, ctx, inst,
1169 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
8276dd87 1170 &aux_engine_regs[inst],
1171 &aux_mask,
f6040a43 1172 &aux_shift,
1173 ctx->dc->caps.extended_aux_timeout_support);
7ed4e635
HW		 1174
1175 return &aux_engine->base;
1176}
1177#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
1178
1179static const struct dce_i2c_registers i2c_hw_regs[] = {
1180 i2c_inst_regs(1),
1181 i2c_inst_regs(2),
1182 i2c_inst_regs(3),
1183 i2c_inst_regs(4),
1184 i2c_inst_regs(5),
1185 i2c_inst_regs(6),
1186};
1187
1188static const struct dce_i2c_shift i2c_shifts = {
1189 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
1190};
1191
1192static const struct dce_i2c_mask i2c_masks = {
1193 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
1194};
1195
1196struct dce_i2c_hw *dcn20_i2c_hw_create(
1197 struct dc_context *ctx,
1198 uint32_t inst)
1199{
1200 struct dce_i2c_hw *dce_i2c_hw =
3bb11050 1201 kzalloc(sizeof(struct dce_i2c_hw), GFP_ATOMIC);
7ed4e635
HW		 1202
1203 if (!dce_i2c_hw)
1204 return NULL;
1205
1206 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1207 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1208
1209 return dce_i2c_hw;
1210}
1211struct mpc *dcn20_mpc_create(struct dc_context *ctx)
1212{
1213 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
3bb11050 1214 GFP_ATOMIC);
7ed4e635
HW		 1215
1216 if (!mpc20)
1217 return NULL;
1218
1219 dcn20_mpc_construct(mpc20, ctx,
1220 &mpc_regs,
1221 &mpc_shift,
1222 &mpc_mask,
1223 6);
1224
1225 return &mpc20->base;
1226}
1227
1228struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)
1229{
1230 int i;
1231 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
3bb11050 1232 GFP_ATOMIC);
7ed4e635
HW		 1233
1234 if (!hubbub)
1235 return NULL;
1236
1237 hubbub2_construct(hubbub, ctx,
1238 &hubbub_reg,
1239 &hubbub_shift,
1240 &hubbub_mask);
1241
1242 for (i = 0; i < res_cap_nv10.num_vmid; i++) {
1243 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1244
1245 vmid->ctx = ctx;
1246
1247 vmid->regs = &vmid_regs[i];
1248 vmid->shifts = &vmid_shifts;
1249 vmid->masks = &vmid_masks;
1250 }
1251
1252 return &hubbub->base;
1253}
1254
1255struct timing_generator *dcn20_timing_generator_create(
1256 struct dc_context *ctx,
1257 uint32_t instance)
1258{
1259 struct optc *tgn10 =
3bb11050 1260 kzalloc(sizeof(struct optc), GFP_ATOMIC);
7ed4e635
HW		 1261
1262 if (!tgn10)
1263 return NULL;
1264
1265 tgn10->base.inst = instance;
1266 tgn10->base.ctx = ctx;
1267
1268 tgn10->tg_regs = &tg_regs[instance];
1269 tgn10->tg_shift = &tg_shift;
1270 tgn10->tg_mask = &tg_mask;
1271
1272 dcn20_timing_generator_init(tgn10);
1273
1274 return &tgn10->base;
1275}
1276
1277static const struct encoder_feature_support link_enc_feature = {
1278 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1279 .max_hdmi_pixel_clock = 600000,
1280 .hdmi_ycbcr420_supported = true,
1281 .dp_ycbcr420_supported = true,
c14b726e 1282 .fec_supported = true,
7ed4e635
HW		 1283 .flags.bits.IS_HBR2_CAPABLE = true,
1284 .flags.bits.IS_HBR3_CAPABLE = true,
1285 .flags.bits.IS_TPS3_CAPABLE = true,
1286 .flags.bits.IS_TPS4_CAPABLE = true
1287};
1288
1289struct link_encoder *dcn20_link_encoder_create(
1290 const struct encoder_init_data *enc_init_data)
1291{
1292 struct dcn20_link_encoder *enc20 =
1293 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
bf7f5ac3 1294 int link_regs_id;
7ed4e635
HW		 1295
1296 if (!enc20)
1297 return NULL;
1298
bf7f5ac3
YMM		 1299 link_regs_id =
1300 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1301
7ed4e635
HW		 1302 dcn20_link_encoder_construct(enc20,
1303 enc_init_data,
1304 &link_enc_feature,
bf7f5ac3 1305 &link_enc_regs[link_regs_id],
7ed4e635
HW		 1306 &link_enc_aux_regs[enc_init_data->channel - 1],
1307 &link_enc_hpd_regs[enc_init_data->hpd_source],
1308 &le_shift,
1309 &le_mask);
1310
1311 return &enc20->enc10.base;
1312}
1313
d4caa72e 1314static struct panel_cntl *dcn20_panel_cntl_create(const struct panel_cntl_init_data *init_data)
904fb6e0 1315{
d4caa72e
AK		 1316 struct dce_panel_cntl *panel_cntl =
1317 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
904fb6e0 1318
d4caa72e 1319 if (!panel_cntl)
904fb6e0
AK		 1320 return NULL;
1321
d4caa72e 1322 dce_panel_cntl_construct(panel_cntl,
904fb6e0 1323 init_data,
d4caa72e
AK		 1324 &panel_cntl_regs[init_data->inst],
1325 &panel_cntl_shift,
1326 &panel_cntl_mask);
904fb6e0 1327
d4caa72e 1328 return &panel_cntl->base;
904fb6e0
AK		 1329}
1330
dfd84d90 1331static struct clock_source *dcn20_clock_source_create(
7ed4e635
HW		 1332 struct dc_context *ctx,
1333 struct dc_bios *bios,
1334 enum clock_source_id id,
1335 const struct dce110_clk_src_regs *regs,
1336 bool dp_clk_src)
1337{
1338 struct dce110_clk_src *clk_src =
3bb11050 1339 kzalloc(sizeof(struct dce110_clk_src), GFP_ATOMIC);
7ed4e635
HW		 1340
1341 if (!clk_src)
1342 return NULL;
1343
1344 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1345 regs, &cs_shift, &cs_mask)) {
1346 clk_src->base.dp_clk_src = dp_clk_src;
1347 return &clk_src->base;
1348 }
1349
cabe144b 1350 kfree(clk_src);
7ed4e635
HW		 1351 BREAK_TO_DEBUGGER();
1352 return NULL;
1353}
1354
1355static void read_dce_straps(
1356 struct dc_context *ctx,
1357 struct resource_straps *straps)
1358{
1359 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1360 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1361}
1362
1363static struct audio *dcn20_create_audio(
1364 struct dc_context *ctx, unsigned int inst)
1365{
1366 return dce_audio_create(ctx, inst,
1367 &audio_regs[inst], &audio_shift, &audio_mask);
1368}
1369
1370struct stream_encoder *dcn20_stream_encoder_create(
1371 enum engine_id eng_id,
1372 struct dc_context *ctx)
1373{
1374 struct dcn10_stream_encoder *enc1 =
1375 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1376
1377 if (!enc1)
1378 return NULL;
1379
9fd4c2d7
ZL		 1380 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
1381 if (eng_id >= ENGINE_ID_DIGD)
1382 eng_id++;
1383 }
1384
7ed4e635
HW		 1385 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1386 &stream_enc_regs[eng_id],
1387 &se_shift, &se_mask);
1388
1389 return &enc1->base;
1390}
1391
1392static const struct dce_hwseq_registers hwseq_reg = {
1393 HWSEQ_DCN2_REG_LIST()
1394};
1395
1396static const struct dce_hwseq_shift hwseq_shift = {
1397 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT)
1398};
1399
1400static const struct dce_hwseq_mask hwseq_mask = {
1401 HWSEQ_DCN2_MASK_SH_LIST(_MASK)
1402};
1403
1404struct dce_hwseq *dcn20_hwseq_create(
1405 struct dc_context *ctx)
1406{
1407 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1408
1409 if (hws) {
1410 hws->ctx = ctx;
1411 hws->regs = &hwseq_reg;
1412 hws->shifts = &hwseq_shift;
1413 hws->masks = &hwseq_mask;
1414 }
1415 return hws;
1416}
1417
1418static const struct resource_create_funcs res_create_funcs = {
1419 .read_dce_straps = read_dce_straps,
1420 .create_audio = dcn20_create_audio,
1421 .create_stream_encoder = dcn20_stream_encoder_create,
1422 .create_hwseq = dcn20_hwseq_create,
1423};
1424
1425static const struct resource_create_funcs res_create_maximus_funcs = {
1426 .read_dce_straps = NULL,
1427 .create_audio = NULL,
1428 .create_stream_encoder = NULL,
1429 .create_hwseq = dcn20_hwseq_create,
1430};
1431
44e149bb
AD		 1432static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
1433
7ed4e635
HW		 1434void dcn20_clock_source_destroy(struct clock_source **clk_src)
1435{
1436 kfree(TO_DCE110_CLK_SRC(*clk_src));
1437 *clk_src = NULL;
1438}
1439
97bda032
HW		 1440
1441struct display_stream_compressor *dcn20_dsc_create(
1442 struct dc_context *ctx, uint32_t inst)
1443{
1444 struct dcn20_dsc *dsc =
3bb11050 1445 kzalloc(sizeof(struct dcn20_dsc), GFP_ATOMIC);
97bda032
HW		 1446
1447 if (!dsc) {
1448 BREAK_TO_DEBUGGER();
1449 return NULL;
1450 }
1451
1452 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1453 return &dsc->base;
1454}
1455
1456void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
1457{
1458 kfree(container_of(*dsc, struct dcn20_dsc, base));
1459 *dsc = NULL;
1460}
1461
7ed4e635 1462
d9e32672 1463static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)
7ed4e635
HW		 1464{
1465 unsigned int i;
1466
1467 for (i = 0; i < pool->base.stream_enc_count; i++) {
1468 if (pool->base.stream_enc[i] != NULL) {
1469 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1470 pool->base.stream_enc[i] = NULL;
1471 }
1472 }
1473
97bda032
HW		 1474 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1475 if (pool->base.dscs[i] != NULL)
1476 dcn20_dsc_destroy(&pool->base.dscs[i]);
1477 }
7ed4e635
HW		 1478
1479 if (pool->base.mpc != NULL) {
1480 kfree(TO_DCN20_MPC(pool->base.mpc));
1481 pool->base.mpc = NULL;
1482 }
1483 if (pool->base.hubbub != NULL) {
1484 kfree(pool->base.hubbub);
1485 pool->base.hubbub = NULL;
1486 }
1487 for (i = 0; i < pool->base.pipe_count; i++) {
1488 if (pool->base.dpps[i] != NULL)
1489 dcn20_dpp_destroy(&pool->base.dpps[i]);
1490
1491 if (pool->base.ipps[i] != NULL)
1492 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1493
1494 if (pool->base.hubps[i] != NULL) {
1495 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1496 pool->base.hubps[i] = NULL;
1497 }
1498
1499 if (pool->base.irqs != NULL) {
1500 dal_irq_service_destroy(&pool->base.irqs);
1501 }
1502 }
1503
1504 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1505 if (pool->base.engines[i] != NULL)
1506 dce110_engine_destroy(&pool->base.engines[i]);
1507 if (pool->base.hw_i2cs[i] != NULL) {
1508 kfree(pool->base.hw_i2cs[i]);
1509 pool->base.hw_i2cs[i] = NULL;
1510 }
1511 if (pool->base.sw_i2cs[i] != NULL) {
1512 kfree(pool->base.sw_i2cs[i]);
1513 pool->base.sw_i2cs[i] = NULL;
1514 }
1515 }
1516
1517 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1518 if (pool->base.opps[i] != NULL)
1519 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1520 }
1521
1522 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1523 if (pool->base.timing_generators[i] != NULL) {
1524 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1525 pool->base.timing_generators[i] = NULL;
1526 }
1527 }
1528
bb21290f
CL		 1529 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1530 if (pool->base.dwbc[i] != NULL) {
1531 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
1532 pool->base.dwbc[i] = NULL;
1533 }
1534 if (pool->base.mcif_wb[i] != NULL) {
1535 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
1536 pool->base.mcif_wb[i] = NULL;
1537 }
1538 }
1539
7ed4e635
HW		 1540 for (i = 0; i < pool->base.audio_count; i++) {
1541 if (pool->base.audios[i])
1542 dce_aud_destroy(&pool->base.audios[i]);
1543 }
1544
1545 for (i = 0; i < pool->base.clk_src_count; i++) {
1546 if (pool->base.clock_sources[i] != NULL) {
1547 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1548 pool->base.clock_sources[i] = NULL;
1549 }
1550 }
1551
1552 if (pool->base.dp_clock_source != NULL) {
1553 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1554 pool->base.dp_clock_source = NULL;
1555 }
1556
1557
1558 if (pool->base.abm != NULL)
1559 dce_abm_destroy(&pool->base.abm);
1560
1561 if (pool->base.dmcu != NULL)
1562 dce_dmcu_destroy(&pool->base.dmcu);
1563
1564 if (pool->base.dccg != NULL)
1565 dcn_dccg_destroy(&pool->base.dccg);
1566
1567 if (pool->base.pp_smu != NULL)
1568 dcn20_pp_smu_destroy(&pool->base.pp_smu);
1569
d9a07577
JL		 1570 if (pool->base.oem_device != NULL)
1571 dal_ddc_service_destroy(&pool->base.oem_device);
7ed4e635
HW		 1572}
1573
1574struct hubp *dcn20_hubp_create(
1575 struct dc_context *ctx,
1576 uint32_t inst)
1577{
1578 struct dcn20_hubp *hubp2 =
3bb11050 1579 kzalloc(sizeof(struct dcn20_hubp), GFP_ATOMIC);
7ed4e635
HW		 1580
1581 if (!hubp2)
1582 return NULL;
1583
1584 if (hubp2_construct(hubp2, ctx, inst,
1585 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1586 return &hubp2->base;
1587
1588 BREAK_TO_DEBUGGER();
1589 kfree(hubp2);
1590 return NULL;
1591}
1592
1593static void get_pixel_clock_parameters(
1594 struct pipe_ctx *pipe_ctx,
1595 struct pixel_clk_params *pixel_clk_params)
1596{
1597 const struct dc_stream_state *stream = pipe_ctx->stream;
b1f6d01c
DL		 1598 struct pipe_ctx *odm_pipe;
1599 int opp_cnt = 1;
64d283cb
JK		 1600 struct dc_link *link = stream->link;
1601 struct link_encoder *link_enc = NULL;
b1f6d01c
DL		 1602
1603 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1604 opp_cnt++;
7ed4e635
HW		 1605
1606 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
64d283cb
JK		 1607
1608 /* Links supporting dynamically assigned link encoder will be assigned next
1609 * available encoder if one not already assigned.
1610 */
1611 if (link->is_dig_mapping_flexible &&
1612 link->dc->res_pool->funcs->link_encs_assign) {
0d4b4253 1613 link_enc = link_enc_cfg_get_link_enc_used_by_stream(stream->ctx->dc, stream);
64d283cb 1614 if (link_enc == NULL)
0d4b4253 1615 link_enc = link_enc_cfg_get_next_avail_link_enc(stream->ctx->dc);
64d283cb
JK		 1616 } else
1617 link_enc = stream->link->link_enc;
1618 ASSERT(link_enc);
1619
1620 if (link_enc)
1621 pixel_clk_params->encoder_object_id = link_enc->id;
7ed4e635
HW		 1622 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1623 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1624 /* TODO: un-hardcode*/
f01ee019 1625 /* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */
7ed4e635
HW		 1626 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1627 LINK_RATE_REF_FREQ_IN_KHZ;
1628 pixel_clk_params->flags.ENABLE_SS = 0;
1629 pixel_clk_params->color_depth =
1630 stream->timing.display_color_depth;
1631 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1632 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1633
1634 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1635 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1636
b1f6d01c
DL		 1637 if (opp_cnt == 4)
1638 pixel_clk_params->requested_pix_clk_100hz /= 4;
78c77382 1639 else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2)
7ed4e635
HW		 1640 pixel_clk_params->requested_pix_clk_100hz /= 2;
1641
1642 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1643 pixel_clk_params->requested_pix_clk_100hz *= 2;
1644
1645}
1646
1647static void build_clamping_params(struct dc_stream_state *stream)
1648{
1649 stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1650 stream->clamping.c_depth = stream->timing.display_color_depth;
1651 stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1652}
1653
1654static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1655{
1656
1657 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1658
1659 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1660 pipe_ctx->clock_source,
1661 &pipe_ctx->stream_res.pix_clk_params,
1662 &pipe_ctx->pll_settings);
1663
1664 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1665
1666 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1667 &pipe_ctx->stream->bit_depth_params);
1668 build_clamping_params(pipe_ctx->stream);
1669
1670 return DC_OK;
1671}
1672
1673enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
1674{
1675 enum dc_status status = DC_OK;
1676 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1677
7ed4e635
HW		 1678 if (!pipe_ctx)
1679 return DC_ERROR_UNEXPECTED;
1680
1681
1682 status = build_pipe_hw_param(pipe_ctx);
1683
1684 return status;
1685}
1686
97bda032 1687
570bc18c 1688void dcn20_acquire_dsc(const struct dc *dc,
14e49bb3 1689 struct resource_context *res_ctx,
eab4bb97
NC		 1690 struct display_stream_compressor **dsc,
1691 int pipe_idx)
97bda032
HW		 1692{
1693 int i;
14e49bb3
NC		 1694 const struct resource_pool *pool = dc->res_pool;
1695 struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc;
c9ae6e16 1696
14e49bb3 1697 ASSERT(*dsc == NULL); /* If this ASSERT fails, dsc was not released properly */
c9ae6e16 1698 *dsc = NULL;
97bda032 1699
14e49bb3 1700 /* Always do 1-to-1 mapping when number of DSCs is same as number of pipes */
eab4bb97
NC		 1701 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) {
1702 *dsc = pool->dscs[pipe_idx];
1703 res_ctx->is_dsc_acquired[pipe_idx] = true;
1704 return;
1705 }
1706
14e49bb3
NC		 1707 /* Return old DSC to avoid the need for re-programming */
1708 if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) {
1709 *dsc = dsc_old;
1710 res_ctx->is_dsc_acquired[dsc_old->inst] = true;
1711 return ;
1712 }
1713
97bda032
HW		 1714 /* Find first free DSC */
1715 for (i = 0; i < pool->res_cap->num_dsc; i++)
1716 if (!res_ctx->is_dsc_acquired[i]) {
c9ae6e16 1717 *dsc = pool->dscs[i];
97bda032
HW		 1718 res_ctx->is_dsc_acquired[i] = true;
1719 break;
1720 }
97bda032
HW		 1721}
1722
7287a675 1723void dcn20_release_dsc(struct resource_context *res_ctx,
97bda032 1724 const struct resource_pool *pool,
c9ae6e16 1725 struct display_stream_compressor **dsc)
97bda032
HW		 1726{
1727 int i;
1728
1729 for (i = 0; i < pool->res_cap->num_dsc; i++)
c9ae6e16 1730 if (pool->dscs[i] == *dsc) {
97bda032 1731 res_ctx->is_dsc_acquired[i] = false;
c9ae6e16 1732 *dsc = NULL;
97bda032
HW		 1733 break;
1734 }
1735}
1736
7ed4e635 1737
7ed4e635 1738
8c20a1ed 1739enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc,
c9ae6e16
NC		 1740 struct dc_state *dc_ctx,
1741 struct dc_stream_state *dc_stream)
1742{
1743 enum dc_status result = DC_OK;
1744 int i;
97bda032 1745
c9ae6e16
NC		 1746 /* Get a DSC if required and available */
1747 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1748 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];
97bda032 1749
c9ae6e16
NC		 1750 if (pipe_ctx->stream != dc_stream)
1751 continue;
97bda032 1752
8c20a1ed
DF		 1753 if (pipe_ctx->stream_res.dsc)
1754 continue;
1755
570bc18c 1756 dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i);
97bda032 1757
c9ae6e16
NC		 1758 /* The number of DSCs can be less than the number of pipes */
1759 if (!pipe_ctx->stream_res.dsc) {
c9ae6e16 1760 result = DC_NO_DSC_RESOURCE;
97bda032 1761 }
7ed4e635 1762
c9ae6e16
NC		 1763 break;
1764 }
7ed4e635
HW		 1765
1766 return result;
1767}
1768
1769
ba32c50f 1770static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
c9ae6e16
NC		 1771 struct dc_state *new_ctx,
1772 struct dc_stream_state *dc_stream)
7ed4e635
HW		 1773{
1774 struct pipe_ctx *pipe_ctx = NULL;
1775 int i;
1776
7ed4e635
HW		 1777 for (i = 0; i < MAX_PIPES; i++) {
1778 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1779 pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
b1f6d01c
DL		 1780
1781 if (pipe_ctx->stream_res.dsc)
7287a675 1782 dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
7ed4e635
HW		 1783 }
1784 }
1785
1786 if (!pipe_ctx)
1787 return DC_ERROR_UNEXPECTED;
b1f6d01c
DL		 1788 else
1789 return DC_OK;
7ed4e635 1790}
c9ae6e16
NC		 1791
1792
1793enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1794{
1795 enum dc_status result = DC_ERROR_UNEXPECTED;
1796
1797 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1798
1799 if (result == DC_OK)
1800 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1801
c9ae6e16
NC		 1802 /* Get a DSC if required and available */
1803 if (result == DC_OK && dc_stream->timing.flags.DSC)
8c20a1ed 1804 result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
c9ae6e16
NC		 1805
1806 if (result == DC_OK)
1807 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
1808
1809 return result;
1810}
1811
1812
1813enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1814{
1815 enum dc_status result = DC_OK;
1816
ba32c50f 1817 result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
c9ae6e16
NC		 1818
1819 return result;
1820}
7ed4e635
HW		 1821
1822
1823static void swizzle_to_dml_params(
1824 enum swizzle_mode_values swizzle,
1825 unsigned int *sw_mode)
1826{
1827 switch (swizzle) {
1828 case DC_SW_LINEAR:
1829 *sw_mode = dm_sw_linear;
1830 break;
1831 case DC_SW_4KB_S:
1832 *sw_mode = dm_sw_4kb_s;
1833 break;
1834 case DC_SW_4KB_S_X:
1835 *sw_mode = dm_sw_4kb_s_x;
1836 break;
1837 case DC_SW_4KB_D:
1838 *sw_mode = dm_sw_4kb_d;
1839 break;
1840 case DC_SW_4KB_D_X:
1841 *sw_mode = dm_sw_4kb_d_x;
1842 break;
1843 case DC_SW_64KB_S:
1844 *sw_mode = dm_sw_64kb_s;
1845 break;
1846 case DC_SW_64KB_S_X:
1847 *sw_mode = dm_sw_64kb_s_x;
1848 break;
1849 case DC_SW_64KB_S_T:
1850 *sw_mode = dm_sw_64kb_s_t;
1851 break;
1852 case DC_SW_64KB_D:
1853 *sw_mode = dm_sw_64kb_d;
1854 break;
1855 case DC_SW_64KB_D_X:
1856 *sw_mode = dm_sw_64kb_d_x;
1857 break;
1858 case DC_SW_64KB_D_T:
1859 *sw_mode = dm_sw_64kb_d_t;
1860 break;
1861 case DC_SW_64KB_R_X:
1862 *sw_mode = dm_sw_64kb_r_x;
1863 break;
1864 case DC_SW_VAR_S:
1865 *sw_mode = dm_sw_var_s;
1866 break;
1867 case DC_SW_VAR_S_X:
1868 *sw_mode = dm_sw_var_s_x;
1869 break;
1870 case DC_SW_VAR_D:
1871 *sw_mode = dm_sw_var_d;
1872 break;
1873 case DC_SW_VAR_D_X:
1874 *sw_mode = dm_sw_var_d_x;
1875 break;
58065a1e
AL		 1876 case DC_SW_VAR_R_X:
1877 *sw_mode = dm_sw_var_r_x;
1878 break;
7ed4e635
HW		 1879 default:
1880 ASSERT(0); /* Not supported */
1881 break;
1882 }
1883}
1884
b6bfba6c 1885bool dcn20_split_stream_for_odm(
14e49bb3 1886 const struct dc *dc,
b1f6d01c 1887 struct resource_context *res_ctx,
b1f6d01c
DL		 1888 struct pipe_ctx *prev_odm_pipe,
1889 struct pipe_ctx *next_odm_pipe)
1890{
1891 int pipe_idx = next_odm_pipe->pipe_idx;
14e49bb3 1892 const struct resource_pool *pool = dc->res_pool;
b1f6d01c
DL		 1893
1894 *next_odm_pipe = *prev_odm_pipe;
b1f6d01c
DL		 1895
1896 next_odm_pipe->pipe_idx = pipe_idx;
1897 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
1898 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
1899 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
1900 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
1901 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
1902 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
b1f6d01c 1903 next_odm_pipe->stream_res.dsc = NULL;
b1f6d01c 1904 if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
b1f6d01c
DL		 1905 next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
1906 next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
1907 }
2e7b43e6
DL		 1908 if (prev_odm_pipe->top_pipe && prev_odm_pipe->top_pipe->next_odm_pipe) {
1909 prev_odm_pipe->top_pipe->next_odm_pipe->bottom_pipe = next_odm_pipe;
1910 next_odm_pipe->top_pipe = prev_odm_pipe->top_pipe->next_odm_pipe;
1911 }
1912 if (prev_odm_pipe->bottom_pipe && prev_odm_pipe->bottom_pipe->next_odm_pipe) {
1913 prev_odm_pipe->bottom_pipe->next_odm_pipe->top_pipe = next_odm_pipe;
1914 next_odm_pipe->bottom_pipe = prev_odm_pipe->bottom_pipe->next_odm_pipe;
1915 }
b1f6d01c
DL		 1916 prev_odm_pipe->next_odm_pipe = next_odm_pipe;
1917 next_odm_pipe->prev_odm_pipe = prev_odm_pipe;
b1f6d01c
DL		 1918
1919 if (prev_odm_pipe->plane_state) {
c0358809
DL		 1920 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
1921 int new_width;
1922
b1f6d01c
DL		 1923 /* HACTIVE halved for odm combine */
1924 sd->h_active /= 2;
b1f6d01c
DL		 1925 /* Calculate new vp and recout for left pipe */
1926 /* Need at least 16 pixels width per side */
1927 if (sd->recout.x + 16 >= sd->h_active)
1928 return false;
1929 new_width = sd->h_active - sd->recout.x;
1930 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1931 sd->ratios.horz, sd->recout.width - new_width));
1932 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1933 sd->ratios.horz_c, sd->recout.width - new_width));
1934 sd->recout.width = new_width;
1935
1936 /* Calculate new vp and recout for right pipe */
1937 sd = &next_odm_pipe->plane_res.scl_data;
c0358809
DL		 1938 /* HACTIVE halved for odm combine */
1939 sd->h_active /= 2;
b1f6d01c
DL		 1940 /* Need at least 16 pixels width per side */
1941 if (new_width <= 16)
1942 return false;
c0358809 1943 new_width = sd->recout.width + sd->recout.x - sd->h_active;
b1f6d01c
DL		 1944 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1945 sd->ratios.horz, sd->recout.width - new_width));
1946 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1947 sd->ratios.horz_c, sd->recout.width - new_width));
1948 sd->recout.width = new_width;
1949 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
1950 sd->ratios.horz, sd->h_active - sd->recout.x));
1951 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
1952 sd->ratios.horz_c, sd->h_active - sd->recout.x));
1953 sd->recout.x = 0;
1954 }
2e7b43e6
DL		 1955 if (!next_odm_pipe->top_pipe)
1956 next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
1957 else
1958 next_odm_pipe->stream_res.opp = next_odm_pipe->top_pipe->stream_res.opp;
73d48f08 1959 if (next_odm_pipe->stream->timing.flags.DSC == 1 && !next_odm_pipe->top_pipe) {
570bc18c 1960 dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);
b1f6d01c
DL		 1961 ASSERT(next_odm_pipe->stream_res.dsc);
1962 if (next_odm_pipe->stream_res.dsc == NULL)
1963 return false;
1964 }
b1f6d01c
DL		 1965
1966 return true;
1967}
1968
65d68369 1969void dcn20_split_stream_for_mpc(
7ed4e635
HW		 1970 struct resource_context *res_ctx,
1971 const struct resource_pool *pool,
1972 struct pipe_ctx *primary_pipe,
b1f6d01c 1973 struct pipe_ctx *secondary_pipe)
7ed4e635
HW		 1974{
1975 int pipe_idx = secondary_pipe->pipe_idx;
7ed4e635 1976 struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
7ed4e635
HW		 1977
1978 *secondary_pipe = *primary_pipe;
1979 secondary_pipe->bottom_pipe = sec_bot_pipe;
1980
1981 secondary_pipe->pipe_idx = pipe_idx;
1982 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
1983 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
1984 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
1985 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
1986 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
1987 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
c92b4c46 1988 secondary_pipe->stream_res.dsc = NULL;
7ed4e635
HW		 1989 if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
1990 ASSERT(!secondary_pipe->bottom_pipe);
1991 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
1992 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
1993 }
1994 primary_pipe->bottom_pipe = secondary_pipe;
1995 secondary_pipe->top_pipe = primary_pipe;
1996
b1f6d01c 1997 ASSERT(primary_pipe->plane_state);
7ed4e635
HW		 1998}
1999
7ed4e635 2000int dcn20_populate_dml_pipes_from_context(
fa896813
IZ		 2001 struct dc *dc,
2002 struct dc_state *context,
2003 display_e2e_pipe_params_st *pipes,
2004 bool fast_validate)
7ed4e635
HW		 2005{
2006 int pipe_cnt, i;
2007 bool synchronized_vblank = true;
2f488884 2008 struct resource_context *res_ctx = &context->res_ctx;
7ed4e635
HW		 2009
2010 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
2011 if (!res_ctx->pipe_ctx[i].stream)
2012 continue;
2013
2014 if (pipe_cnt < 0) {
2015 pipe_cnt = i;
2016 continue;
2017 }
d294353e
AL		 2018
2019 if (res_ctx->pipe_ctx[pipe_cnt].stream == res_ctx->pipe_ctx[i].stream)
2020 continue;
2021
77a2b726
VS		 2022 if (dc->debug.disable_timing_sync ||
2023 (!resource_are_streams_timing_synchronizable(
7ed4e635 2024 res_ctx->pipe_ctx[pipe_cnt].stream,
77a2b726
VS		 2025 res_ctx->pipe_ctx[i].stream) &&
2026 !resource_are_vblanks_synchronizable(
2027 res_ctx->pipe_ctx[pipe_cnt].stream,
2028 res_ctx->pipe_ctx[i].stream))) {
7ed4e635
HW		 2029 synchronized_vblank = false;
2030 break;
2031 }
2032 }
2033
2034 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2035 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
2f488884 2036 unsigned int v_total;
1075735e 2037 unsigned int front_porch;
03fd87db 2038 int output_bpc;
5dba4991 2039 struct audio_check aud_check = {0};
20f2ffe5 2040
7ed4e635
HW		 2041 if (!res_ctx->pipe_ctx[i].stream)
2042 continue;
2f488884
AL		 2043
2044 v_total = timing->v_total;
1075735e 2045 front_porch = timing->v_front_porch;
fa896813 2046
7ed4e635
HW		 2047 /* todo:
2048 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
2049 pipes[pipe_cnt].pipe.src.dcc = 0;
2050 pipes[pipe_cnt].pipe.src.vm = 0;*/
2051
5fc11598
DL		 2052 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2053
97bda032
HW		 2054 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
2055 /* todo: rotation?*/
2056 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
7ed4e635
HW		 2057 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
2058 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
2059 /* 1/2 vblank */
2060 pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
2f488884 2061 (v_total - timing->v_addressable
7ed4e635
HW		 2062 - timing->v_border_top - timing->v_border_bottom) / 2;
2063 /* 36 bytes dp, 32 hdmi */
2064 pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
2065 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
2066 }
2067 pipes[pipe_cnt].pipe.src.dcc = false;
2068 pipes[pipe_cnt].pipe.src.dcc_rate = 1;
2069 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
2070 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
2071 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
2072 - timing->h_addressable
2073 - timing->h_border_left
2074 - timing->h_border_right;
1075735e 2075 pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch;
7ed4e635
HW		 2076 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
2077 - timing->v_addressable
2078 - timing->v_border_top
2079 - timing->v_border_bottom;
2080 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
2f488884 2081 pipes[pipe_cnt].pipe.dest.vtotal = v_total;
2e63f406
NK		 2082 pipes[pipe_cnt].pipe.dest.hactive =
2083 timing->h_addressable + timing->h_border_left + timing->h_border_right;
2084 pipes[pipe_cnt].pipe.dest.vactive =
2085 timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
7ed4e635
HW		 2086 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
2087 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
2088 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2089 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
2090 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
1621f4c4 2091 pipes[pipe_cnt].dout.dp_lanes = 4;
91a51fbf 2092 pipes[pipe_cnt].dout.is_virtual = 0;
8bb3d7e7
CL		 2093 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
2094 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
5bf24270
DL		 2095 switch (get_num_odm_splits(&res_ctx->pipe_ctx[i])) {
2096 case 1:
5fc11598
DL		 2097 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1;
2098 break;
5dba4991
BL		 2099 case 3:
2100 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_4to1;
2101 break;
5fc11598
DL		 2102 default:
2103 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled;
2104 }
c0358809
DL		 2105 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
2106 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
56260cbf
DL		 2107 == res_ctx->pipe_ctx[i].plane_state) {
2108 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe;
4d765d31 2109 int split_idx = 0;
56260cbf
DL		 2110
2111 while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state
4d765d31 2112 == res_ctx->pipe_ctx[i].plane_state) {
56260cbf 2113 first_pipe = first_pipe->top_pipe;
4d765d31
DL		 2114 split_idx++;
2115 }
2116 /* Treat 4to1 mpc combine as an mpo of 2 2-to-1 combines */
2117 if (split_idx == 0)
2118 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
2119 else if (split_idx == 1)
2120 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
2121 else if (split_idx == 2)
2122 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
56260cbf 2123 } else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
c0358809
DL		 2124 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
2125
2126 while (first_pipe->prev_odm_pipe)
2127 first_pipe = first_pipe->prev_odm_pipe;
2128 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
2129 }
7ed4e635 2130
7ed4e635
HW		 2131 switch (res_ctx->pipe_ctx[i].stream->signal) {
2132 case SIGNAL_TYPE_DISPLAY_PORT_MST:
2133 case SIGNAL_TYPE_DISPLAY_PORT:
2134 pipes[pipe_cnt].dout.output_type = dm_dp;
2135 break;
2136 case SIGNAL_TYPE_EDP:
2137 pipes[pipe_cnt].dout.output_type = dm_edp;
2138 break;
2139 case SIGNAL_TYPE_HDMI_TYPE_A:
2140 case SIGNAL_TYPE_DVI_SINGLE_LINK:
2141 case SIGNAL_TYPE_DVI_DUAL_LINK:
2142 pipes[pipe_cnt].dout.output_type = dm_hdmi;
2143 break;
2144 default:
2145 /* In case there is no signal, set dp with 4 lanes to allow max config */
91a51fbf 2146 pipes[pipe_cnt].dout.is_virtual = 1;
7ed4e635
HW		 2147 pipes[pipe_cnt].dout.output_type = dm_dp;
2148 pipes[pipe_cnt].dout.dp_lanes = 4;
2149 }
03fd87db
IB		 2150
2151 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
2152 case COLOR_DEPTH_666:
2153 output_bpc = 6;
2154 break;
2155 case COLOR_DEPTH_888:
2156 output_bpc = 8;
2157 break;
2158 case COLOR_DEPTH_101010:
2159 output_bpc = 10;
2160 break;
2161 case COLOR_DEPTH_121212:
2162 output_bpc = 12;
2163 break;
2164 case COLOR_DEPTH_141414:
2165 output_bpc = 14;
2166 break;
2167 case COLOR_DEPTH_161616:
2168 output_bpc = 16;
2169 break;
03fd87db
IB		 2170 case COLOR_DEPTH_999:
2171 output_bpc = 9;
2172 break;
2173 case COLOR_DEPTH_111111:
2174 output_bpc = 11;
2175 break;
03fd87db
IB		 2176 default:
2177 output_bpc = 8;
2178 break;
2179 }
2180
7ed4e635
HW		 2181 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
2182 case PIXEL_ENCODING_RGB:
2183 case PIXEL_ENCODING_YCBCR444:
2184 pipes[pipe_cnt].dout.output_format = dm_444;
03fd87db 2185 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
7ed4e635
HW		 2186 break;
2187 case PIXEL_ENCODING_YCBCR420:
2188 pipes[pipe_cnt].dout.output_format = dm_420;
486cc0ee 2189 pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2;
7ed4e635
HW		 2190 break;
2191 case PIXEL_ENCODING_YCBCR422:
b0f34382
NK		 2192 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC &&
2193 !res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.ycbcr422_simple)
7ed4e635 2194 pipes[pipe_cnt].dout.output_format = dm_n422;
b0f34382
NK		 2195 else
2196 pipes[pipe_cnt].dout.output_format = dm_s422;
03fd87db 2197 pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
7ed4e635
HW		 2198 break;
2199 default:
2200 pipes[pipe_cnt].dout.output_format = dm_444;
03fd87db 2201 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
7ed4e635 2202 }
7ed4e635 2203
486cc0ee
NC		 2204 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)
2205 pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
2206
7ed4e635 2207 /* todo: default max for now, until there is logic reflecting this in dc*/
091e3131 2208 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
dc3de516 2209 /*fill up the audio sample rate (unit in kHz)*/
5dba4991 2210 get_audio_check(&res_ctx->pipe_ctx[i].stream->audio_info, &aud_check);
dc3de516 2211 pipes[pipe_cnt].dout.max_audio_sample_rate = aud_check.max_audiosample_rate / 1000;
7ed4e635 2212 /*
8f174fdb 2213 * For graphic plane, cursor number is 1, nv12 is 0
7ed4e635
HW		 2214 * bw calculations due to cursor on/off
2215 */
8f174fdb
YS		 2216 if (res_ctx->pipe_ctx[i].plane_state &&
2217 res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2218 pipes[pipe_cnt].pipe.src.num_cursors = 0;
2219 else
2220 pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors;
2221
ed07237c
IB		 2222 pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
2223 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
7ed4e635
HW		 2224
2225 if (!res_ctx->pipe_ctx[i].plane_state) {
56260cbf 2226 pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
7ed4e635 2227 pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
0914d115 2228 pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_4kb_s;
7ed4e635
HW		 2229 pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
2230 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
2231 if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
2232 pipes[pipe_cnt].pipe.src.viewport_width = 1920;
2233 pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
2234 if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
2235 pipes[pipe_cnt].pipe.src.viewport_height = 1080;
71e6bd2a 2236 pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height;
5fc11598
DL		 2237 pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width;
2238 pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height;
2239 pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width;
0914d115 2240 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 255) / 256) * 256;
7ed4e635
HW		 2241 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2242 pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
2243 pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/
2244 pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_hsplit != 1*/
2245 pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/
2246 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
2247 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
2248 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
2249 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
2250 pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
2251 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
2f488884
AL		 2252 pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;
2253 pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;
56260cbf
DL		 2254
2255 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) {
2256 pipes[pipe_cnt].pipe.src.viewport_width /= 2;
2257 pipes[pipe_cnt].pipe.dest.recout_width /= 2;
20f2ffe5 2258 } else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) {
5dba4991
BL		 2259 pipes[pipe_cnt].pipe.src.viewport_width /= 4;
2260 pipes[pipe_cnt].pipe.dest.recout_width /= 4;
2261 }
7ed4e635
HW		 2262 } else {
2263 struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
2264 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
2265
7ed4e635 2266 pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
56260cbf
DL		 2267 pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
2268 || (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln)
2269 || pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
d2e0d826 2270
4d765d31 2271 /* stereo is not split */
d2e0d826
NK		 2272 if (pln->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE ||
2273 pln->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) {
2274 pipes[pipe_cnt].pipe.src.is_hsplit = false;
2275 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
2276 }
2277
7ed4e635
HW		 2278 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
2279 || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
6566cae7
DL		 2280 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
2281 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
2282 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
2283 pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
2284 pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
2285 pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
2286 pipes[pipe_cnt].pipe.src.viewport_width_max = pln->src_rect.width;
2287 pipes[pipe_cnt].pipe.src.viewport_height_max = pln->src_rect.height;
5fc11598 2288 pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width;
71e6bd2a 2289 pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;
5fc11598
DL		 2290 pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width;
2291 pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height;
5dba4991
BL		 2292 if (pln->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA
2293 || pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
12e2b2d4
DL		 2294 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2295 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
2296 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
2297 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
7ed4e635 2298 } else {
12e2b2d4
DL		 2299 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2300 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
7ed4e635
HW		 2301 }
2302 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
2303 pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
2304 pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
7ed4e635 2305 pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
5bf24270
DL		 2306 pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
2307 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1)
2308 pipes[pipe_cnt].pipe.dest.full_recout_width *= 2;
5dba4991
BL		 2309 else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1)
2310 pipes[pipe_cnt].pipe.dest.full_recout_width *= 4;
5bf24270
DL		 2311 else {
2312 struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe;
2313
2314 while (split_pipe && split_pipe->plane_state == pln) {
2315 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
2316 split_pipe = split_pipe->bottom_pipe;
2317 }
2318 split_pipe = res_ctx->pipe_ctx[i].top_pipe;
2319 while (split_pipe && split_pipe->plane_state == pln) {
2320 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
2321 split_pipe = split_pipe->top_pipe;
2322 }
7ed4e635
HW		 2323 }
2324
ed07237c 2325 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
7ed4e635
HW		 2326 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
2327 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
2328 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
2329 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
2330 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
2331 scl->ratios.vert.value != dc_fixpt_one.value
2332 || scl->ratios.horz.value != dc_fixpt_one.value
2333 || scl->ratios.vert_c.value != dc_fixpt_one.value
2334 || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/
2335 || dc->debug.always_scale; /*support always scale*/
2336 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
2337 pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
2338 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
2339 pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
2340
b964e790
DL		 2341 pipes[pipe_cnt].pipe.src.macro_tile_size =
2342 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
7ed4e635
HW		 2343 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
2344 &pipes[pipe_cnt].pipe.src.sw_mode);
2345
2346 switch (pln->format) {
2347 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2348 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2349 pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
2350 break;
2351 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2352 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2353 pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
2354 break;
2355 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
050cd3d6 2356 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
7ed4e635
HW		 2357 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2358 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2359 pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
2360 break;
2361 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2362 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2363 pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
2364 break;
2365 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2366 pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
2367 break;
5dba4991
BL		 2368 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
2369 pipes[pipe_cnt].pipe.src.source_format = dm_rgbe_alpha;
2370 break;
7ed4e635
HW		 2371 default:
2372 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2373 break;
2374 }
2375 }
2376
2377 pipe_cnt++;
2378 }
2379
2380 /* populate writeback information */
0ea7ee82 2381 DC_FP_START();
7ed4e635 2382 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
0ea7ee82 2383 DC_FP_END();
7ed4e635
HW		 2384
2385 return pipe_cnt;
2386}
2387
2388unsigned int dcn20_calc_max_scaled_time(
2389 unsigned int time_per_pixel,
2390 enum mmhubbub_wbif_mode mode,
2391 unsigned int urgent_watermark)
2392{
2393 unsigned int time_per_byte = 0;
2394 unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */
2395 unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */
2396 unsigned int small_free_entry, max_free_entry;
2397 unsigned int buf_lh_capability;
2398 unsigned int max_scaled_time;
2399
2400 if (mode == PACKED_444) /* packed mode */
2401 time_per_byte = time_per_pixel/4;
2402 else if (mode == PLANAR_420_8BPC)
2403 time_per_byte = time_per_pixel;
2404 else if (mode == PLANAR_420_10BPC) /* p010 */
2405 time_per_byte = time_per_pixel * 819/1024;
2406
2407 if (time_per_byte == 0)
2408 time_per_byte = 1;
2409
2410 small_free_entry = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry;
2411 max_free_entry = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;
2412 buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */
2413 max_scaled_time = buf_lh_capability - urgent_watermark;
2414 return max_scaled_time;
2415}
2416
2417void dcn20_set_mcif_arb_params(
2418 struct dc *dc,
2419 struct dc_state *context,
2420 display_e2e_pipe_params_st *pipes,
2421 int pipe_cnt)
2422{
2423 enum mmhubbub_wbif_mode wbif_mode;
2424 struct mcif_arb_params *wb_arb_params;
2425 int i, j, k, dwb_pipe;
2426
2427 /* Writeback MCIF_WB arbitration parameters */
2428 dwb_pipe = 0;
2429 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2430
2431 if (!context->res_ctx.pipe_ctx[i].stream)
2432 continue;
2433
2434 for (j = 0; j < MAX_DWB_PIPES; j++) {
2435 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)
2436 continue;
2437
2438 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
2439 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
2440
2441 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {
2442 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
2443 wbif_mode = PLANAR_420_8BPC;
2444 else
2445 wbif_mode = PLANAR_420_10BPC;
2446 } else
2447 wbif_mode = PACKED_444;
2448
2449 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
2450 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2451 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2452 }
23e55639 2453 wb_arb_params->time_per_pixel = 16.0 * 1000 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000); /* 4 bit fraction, ms */
7ed4e635
HW		 2454 wb_arb_params->slice_lines = 32;
2455 wb_arb_params->arbitration_slice = 2;
2456 wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
2457 wbif_mode,
2458 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
2459
2460 dwb_pipe++;
2461
2462 if (dwb_pipe >= MAX_DWB_PIPES)
2463 return;
2464 }
2465 if (dwb_pipe >= MAX_DWB_PIPES)
2466 return;
2467 }
2468}
2469
b6bfba6c 2470bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
0ba37b20
DL		 2471{
2472 int i;
2473
2474 /* Validate DSC config, dsc count validation is already done */
2475 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2476 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
2477 struct dc_stream_state *stream = pipe_ctx->stream;
2478 struct dsc_config dsc_cfg;
b1f6d01c
DL		 2479 struct pipe_ctx *odm_pipe;
2480 int opp_cnt = 1;
2481
2482 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
2483 opp_cnt++;
0ba37b20
DL		 2484
2485 /* Only need to validate top pipe */
b1f6d01c 2486 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
0ba37b20
DL		 2487 continue;
2488
b1f6d01c
DL		 2489 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
2490 + stream->timing.h_border_right) / opp_cnt;
0ba37b20
DL		 2491 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
2492 + stream->timing.v_border_bottom;
0ba37b20
DL		 2493 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
2494 dsc_cfg.color_depth = stream->timing.display_color_depth;
df8e34ac 2495 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
0ba37b20 2496 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
b1f6d01c 2497 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
0ba37b20
DL		 2498
2499 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
2500 return false;
2501 }
2502 return true;
2503}
0ba37b20 2504
b6bfba6c 2505struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
c681491a
JL		 2506 struct resource_context *res_ctx,
2507 const struct resource_pool *pool,
2508 const struct pipe_ctx *primary_pipe)
2509{
2510 struct pipe_ctx *secondary_pipe = NULL;
2511
2512 if (dc && primary_pipe) {
2513 int j;
2514 int preferred_pipe_idx = 0;
2515
2516 /* first check the prev dc state:
2517 * if this primary pipe has a bottom pipe in prev. state
2518 * and if the bottom pipe is still available (which it should be),
2519 * pick that pipe as secondary
7a214cd8 2520 * Same logic applies for ODM pipes
c681491a 2521 */
324b1fcb 2522 if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {
2523 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;
c681491a
JL		 2524 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2525 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2526 secondary_pipe->pipe_idx = preferred_pipe_idx;
2527 }
7a214cd8
SL		 2528 }
2529 if (secondary_pipe == NULL &&
324b1fcb 2530 dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {
2531 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
b1f6d01c
DL		 2532 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2533 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2534 secondary_pipe->pipe_idx = preferred_pipe_idx;
2535 }
c681491a
JL		 2536 }
2537
2538 /*
2539 * if this primary pipe does not have a bottom pipe in prev. state
2540 * start backward and find a pipe that did not used to be a bottom pipe in
2541 * prev. dc state. This way we make sure we keep the same assignment as
2542 * last state and will not have to reprogram every pipe
2543 */
2544 if (secondary_pipe == NULL) {
2545 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
8b8eda01
DL		 2546 if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL
2547 && dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) {
c681491a
JL		 2548 preferred_pipe_idx = j;
2549
2550 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2551 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2552 secondary_pipe->pipe_idx = preferred_pipe_idx;
2553 break;
2554 }
2555 }
2556 }
2557 }
2558 /*
2559 * We should never hit this assert unless assignments are shuffled around
2560 * if this happens we will prob. hit a vsync tdr
2561 */
2562 ASSERT(secondary_pipe);
2563 /*
2564 * search backwards for the second pipe to keep pipe
2565 * assignment more consistent
2566 */
2567 if (secondary_pipe == NULL) {
2568 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2569 preferred_pipe_idx = j;
2570
2571 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2572 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2573 secondary_pipe->pipe_idx = preferred_pipe_idx;
2574 break;
2575 }
2576 }
2577 }
2578 }
2579
2580 return secondary_pipe;
2581}
2582
ea817dd5 2583void dcn20_merge_pipes_for_validate(
6de20237 2584 struct dc *dc,
b6bfba6c 2585 struct dc_state *context)
7ed4e635 2586{
b6bfba6c 2587 int i;
7ed4e635 2588
b1f6d01c
DL		 2589 /* merge previously split odm pipes since mode support needs to make the decision */
2590 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2591 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2592 struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;
2593
2594 if (pipe->prev_odm_pipe)
2595 continue;
2596
2597 pipe->next_odm_pipe = NULL;
2598 while (odm_pipe) {
2599 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
2600
2601 odm_pipe->plane_state = NULL;
2602 odm_pipe->stream = NULL;
2603 odm_pipe->top_pipe = NULL;
2604 odm_pipe->bottom_pipe = NULL;
2605 odm_pipe->prev_odm_pipe = NULL;
2606 odm_pipe->next_odm_pipe = NULL;
b1f6d01c 2607 if (odm_pipe->stream_res.dsc)
7287a675 2608 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
b1f6d01c
DL		 2609 /* Clear plane_res and stream_res */
2610 memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));
2611 memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));
2612 odm_pipe = next_odm_pipe;
2613 }
2614 if (pipe->plane_state)
2615 resource_build_scaling_params(pipe);
2616 }
2617
2618 /* merge previously mpc split pipes since mode support needs to make the decision */
7ed4e635
HW		 2619 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2620 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2621 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2622
2623 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
2624 continue;
2625
7ed4e635
HW		 2626 pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
2627 if (hsplit_pipe->bottom_pipe)
2628 hsplit_pipe->bottom_pipe->top_pipe = pipe;
2629 hsplit_pipe->plane_state = NULL;
2630 hsplit_pipe->stream = NULL;
2631 hsplit_pipe->top_pipe = NULL;
2632 hsplit_pipe->bottom_pipe = NULL;
b1f6d01c 2633
7ed4e635
HW		 2634 /* Clear plane_res and stream_res */
2635 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
2636 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
2637 if (pipe->plane_state)
2638 resource_build_scaling_params(pipe);
2639 }
b6bfba6c 2640}
7ed4e635 2641
b6bfba6c
DL		 2642int dcn20_validate_apply_pipe_split_flags(
2643 struct dc *dc,
2644 struct dc_state *context,
2645 int vlevel,
65d68369 2646 int *split,
7287a675 2647 bool *merge)
b6bfba6c 2648{
b745ecdb 2649 int i, pipe_idx, vlevel_split;
cd3e05a7 2650 int plane_count = 0;
b6bfba6c 2651 bool force_split = false;
cd3e05a7 2652 bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID;
570bc18c
DL		 2653 struct vba_vars_st *v = &context->bw_ctx.dml.vba;
2654 int max_mpc_comb = v->maxMpcComb;
7ed4e635 2655
cd3e05a7
DL		 2656 if (context->stream_count > 1) {
2657 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP)
2658 avoid_split = true;
2659 } else if (dc->debug.force_single_disp_pipe_split)
2660 force_split = true;
2661
7ed4e635
HW		 2662 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2663 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
7ed4e635 2664
b6dbb8ff
NK		 2665 /**
2666 * Workaround for avoiding pipe-split in cases where we'd split
2667 * planes that are too small, resulting in splits that aren't
2668 * valid for the scaler.
2669 */
2670 if (pipe->plane_state &&
2671 (pipe->plane_state->dst_rect.width <= 16 ||
2672 pipe->plane_state->dst_rect.height <= 16 ||
2673 pipe->plane_state->src_rect.width <= 16 ||
2674 pipe->plane_state->src_rect.height <= 16))
2675 avoid_split = true;
2676
2677 /* TODO: fix dc bugs and remove this split threshold thing */
cd3e05a7
DL		 2678 if (pipe->stream && !pipe->prev_odm_pipe &&
2679 (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state))
2680 ++plane_count;
7ed4e635 2681 }
cd3e05a7 2682 if (plane_count > dc->res_pool->pipe_count / 2)
7ed4e635
HW		 2683 avoid_split = true;
2684
a0a85ac4
DZ		 2685 /* W/A: Mode timing with borders may not work well with pipe split, avoid for this corner case */
2686 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2687 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2688 struct dc_crtc_timing timing;
2689
2690 if (!pipe->stream)
2691 continue;
2692 else {
2693 timing = pipe->stream->timing;
2694 if (timing.h_border_left + timing.h_border_right
2695 + timing.v_border_top + timing.v_border_bottom > 0) {
2696 avoid_split = true;
2697 break;
2698 }
2699 }
2700 }
2701
b745ecdb 2702 /* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */
b6bfba6c
DL		 2703 if (avoid_split) {
2704 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2705 if (!context->res_ctx.pipe_ctx[i].stream)
2706 continue;
2707
b745ecdb 2708 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
570bc18c
DL		 2709 if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 &&
2710 v->ModeSupport[vlevel][0])
b6bfba6c
DL		 2711 break;
2712 /* Impossible to not split this pipe */
b745ecdb
DL		 2713 if (vlevel > context->bw_ctx.dml.soc.num_states)
2714 vlevel = vlevel_split;
1dfedb39
SL		 2715 else
2716 max_mpc_comb = 0;
b6bfba6c
DL		 2717 pipe_idx++;
2718 }
570bc18c 2719 v->maxMpcComb = max_mpc_comb;
b6bfba6c
DL		 2720 }
2721
b745ecdb 2722 /* Split loop sets which pipe should be split based on dml outputs and dc flags */
7ed4e635 2723 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
b6bfba6c 2724 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
570bc18c
DL		 2725 int pipe_plane = v->pipe_plane[pipe_idx];
2726 bool split4mpc = context->stream_count == 1 && plane_count == 1
2727 && dc->config.enable_4to1MPC && dc->res_pool->pipe_count >= 4;
b6bfba6c 2728
7ed4e635
HW		 2729 if (!context->res_ctx.pipe_ctx[i].stream)
2730 continue;
b6bfba6c 2731
4d765d31
DL		 2732 if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4)
2733 split[i] = 4;
2734 else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2)
65d68369 2735 split[i] = 2;
4d765d31 2736
b6bfba6c
DL		 2737 if ((pipe->stream->view_format ==
2738 VIEW_3D_FORMAT_SIDE_BY_SIDE ||
2739 pipe->stream->view_format ==
2740 VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
2741 (pipe->stream->timing.timing_3d_format ==
2742 TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
2743 pipe->stream->timing.timing_3d_format ==
2744 TIMING_3D_FORMAT_SIDE_BY_SIDE))
65d68369 2745 split[i] = 2;
b6bfba6c 2746 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
65d68369 2747 split[i] = 2;
570bc18c 2748 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1;
b6bfba6c 2749 }
5dba4991
BL		 2750 if (dc->debug.force_odm_combine_4to1 & (1 << pipe->stream_res.tg->inst)) {
2751 split[i] = 4;
2752 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1;
2753 }
5e908012
CP		 2754 /*420 format workaround*/
2755 if (pipe->stream->timing.h_addressable > 7680 &&
2756 pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
2757 split[i] = 4;
2758 }
570bc18c
DL		 2759 v->ODMCombineEnabled[pipe_plane] =
2760 v->ODMCombineEnablePerState[vlevel][pipe_plane];
2761
2762 if (v->ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) {
2763 if (get_num_mpc_splits(pipe) == 1) {
2764 /*If need split for mpc but 2 way split already*/
2765 if (split[i] == 4)
2766 split[i] = 2; /* 2 -> 4 MPC */
2767 else if (split[i] == 2)
2768 split[i] = 0; /* 2 -> 2 MPC */
2769 else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
2770 merge[i] = true; /* 2 -> 1 MPC */
2771 } else if (get_num_mpc_splits(pipe) == 3) {
2772 /*If need split for mpc but 4 way split already*/
2773 if (split[i] == 2 && ((pipe->top_pipe && !pipe->top_pipe->top_pipe)
2774 || !pipe->bottom_pipe)) {
2775 merge[i] = true; /* 4 -> 2 MPC */
2776 } else if (split[i] == 0 && pipe->top_pipe &&
2777 pipe->top_pipe->plane_state == pipe->plane_state)
2778 merge[i] = true; /* 4 -> 1 MPC */
65d68369 2779 split[i] = 0;
570bc18c
DL		 2780 } else if (get_num_odm_splits(pipe)) {
2781 /* ODM -> MPC transition */
7287a675 2782 if (pipe->prev_odm_pipe) {
570bc18c
DL		 2783 split[i] = 0;
2784 merge[i] = true;
7287a675
DL		 2785 }
2786 }
570bc18c
DL		 2787 } else {
2788 if (get_num_odm_splits(pipe) == 1) {
2789 /*If need split for odm but 2 way split already*/
2790 if (split[i] == 4)
2791 split[i] = 2; /* 2 -> 4 ODM */
2792 else if (split[i] == 2)
2793 split[i] = 0; /* 2 -> 2 ODM */
2794 else if (pipe->prev_odm_pipe) {
2795 ASSERT(0); /* NOT expected yet */
2796 merge[i] = true; /* exit ODM */
2797 }
2798 } else if (get_num_odm_splits(pipe) == 3) {
2799 /*If need split for odm but 4 way split already*/
2800 if (split[i] == 2 && ((pipe->prev_odm_pipe && !pipe->prev_odm_pipe->prev_odm_pipe)
2801 || !pipe->next_odm_pipe)) {
2802 ASSERT(0); /* NOT expected yet */
2803 merge[i] = true; /* 4 -> 2 ODM */
2804 } else if (split[i] == 0 && pipe->prev_odm_pipe) {
2805 ASSERT(0); /* NOT expected yet */
2806 merge[i] = true; /* exit ODM */
2807 }
65d68369 2808 split[i] = 0;
570bc18c
DL		 2809 } else if (get_num_mpc_splits(pipe)) {
2810 /* MPC -> ODM transition */
2811 ASSERT(0); /* NOT expected yet */
2812 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
2813 split[i] = 0;
2814 merge[i] = true;
2815 }
65d68369 2816 }
7287a675
DL		 2817 }
2818
b6bfba6c 2819 /* Adjust dppclk when split is forced, do not bother with dispclk */
570bc18c
DL		 2820 if (split[i] != 0 && v->NoOfDPP[vlevel][max_mpc_comb][pipe_idx] == 1)
2821 v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] /= 2;
7ed4e635
HW		 2822 pipe_idx++;
2823 }
2824
b6bfba6c
DL		 2825 return vlevel;
2826}
2827
2828bool dcn20_fast_validate_bw(
2829 struct dc *dc,
2830 struct dc_state *context,
2831 display_e2e_pipe_params_st *pipes,
2832 int *pipe_cnt_out,
2833 int *pipe_split_from,
fa896813
IZ		 2834 int *vlevel_out,
2835 bool fast_validate)
b6bfba6c
DL		 2836{
2837 bool out = false;
65d68369 2838 int split[MAX_PIPES] = { 0 };
b6bfba6c
DL		 2839 int pipe_cnt, i, pipe_idx, vlevel;
2840
2841 ASSERT(pipes);
2842 if (!pipes)
2843 return false;
2844
2845 dcn20_merge_pipes_for_validate(dc, context);
2846
fa896813 2847 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
b6bfba6c
DL		 2848
2849 *pipe_cnt_out = pipe_cnt;
2850
2851 if (!pipe_cnt) {
2852 out = true;
2853 goto validate_out;
2854 }
2855
2856 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2857
2858 if (vlevel > context->bw_ctx.dml.soc.num_states)
2859 goto validate_fail;
2860
7287a675 2861 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);
b6bfba6c
DL		 2862
2863 /*initialize pipe_just_split_from to invalid idx*/
2864 for (i = 0; i < MAX_PIPES; i++)
2865 pipe_split_from[i] = -1;
2866
7ed4e635
HW		 2867 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2868 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2869 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
7ed4e635
HW		 2870
2871 if (!pipe->stream || pipe_split_from[i] >= 0)
2872 continue;
2873
2874 pipe_idx++;
2875
7ed4e635 2876 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
c681491a 2877 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
7ed4e635 2878 ASSERT(hsplit_pipe);
b1f6d01c 2879 if (!dcn20_split_stream_for_odm(
14e49bb3 2880 dc, &context->res_ctx,
b1f6d01c 2881 pipe, hsplit_pipe))
7ed4e635
HW		 2882 goto validate_fail;
2883 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2884 dcn20_build_mapped_resource(dc, context, pipe->stream);
2885 }
2886
2887 if (!pipe->plane_state)
2888 continue;
2889 /* Skip 2nd half of already split pipe */
2890 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
2891 continue;
2892
02ce5a79
DL		 2893 /* We do not support mpo + odm at the moment */
2894 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
2895 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
2896 goto validate_fail;
2897
65d68369 2898 if (split[i] == 2) {
7ed4e635
HW		 2899 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
2900 /* pipe not split previously needs split */
c681491a 2901 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
b6bfba6c 2902 ASSERT(hsplit_pipe);
ff86391e
MS		 2903 if (!hsplit_pipe) {
2904 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2;
7ed4e635 2905 continue;
ff86391e 2906 }
b1f6d01c
DL		 2907 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2908 if (!dcn20_split_stream_for_odm(
14e49bb3 2909 dc, &context->res_ctx,
b1f6d01c
DL		 2910 pipe, hsplit_pipe))
2911 goto validate_fail;
387596ef 2912 dcn20_build_mapped_resource(dc, context, pipe->stream);
65d68369
IZ		 2913 } else {
2914 dcn20_split_stream_for_mpc(
b8a8d34b 2915 &context->res_ctx, dc->res_pool,
65d68369 2916 pipe, hsplit_pipe);
65f9ace4
SL		 2917 resource_build_scaling_params(pipe);
2918 resource_build_scaling_params(hsplit_pipe);
65d68369 2919 }
7ed4e635
HW		 2920 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2921 }
02ce5a79 2922 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
7ed4e635
HW		 2923 /* merge should already have been done */
2924 ASSERT(0);
2925 }
2926 }
0ba37b20 2927 /* Actual dsc count per stream dsc validation*/
c84ad0d6 2928 if (!dcn20_validate_dsc(dc, context)) {
0ba37b20
DL		 2929 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2930 DML_FAIL_DSC_VALIDATION_FAILURE;
2931 goto validate_fail;
2932 }
7ed4e635 2933
6de20237 2934 *vlevel_out = vlevel;
42351c66 2935
6de20237
EY		 2936 out = true;
2937 goto validate_out;
2938
2939validate_fail:
2940 out = false;
2941
2942validate_out:
2943 return out;
2944}
2945
e2e316d5 2946static void dcn20_calculate_wm(
6de20237
EY		 2947 struct dc *dc, struct dc_state *context,
2948 display_e2e_pipe_params_st *pipes,
2949 int *out_pipe_cnt,
2950 int *pipe_split_from,
fa896813
IZ		 2951 int vlevel,
2952 bool fast_validate)
6de20237
EY		 2953{
2954 int pipe_cnt, i, pipe_idx;
254eb07c 2955
7ed4e635 2956 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
41f03a6d
DL		 2957 if (!context->res_ctx.pipe_ctx[i].stream)
2958 continue;
7ed4e635 2959
41f03a6d
DL		 2960 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2961 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
7ed4e635 2962
41f03a6d
DL		 2963 if (pipe_split_from[i] < 0) {
2964 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2965 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
2966 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
2967 pipes[pipe_cnt].pipe.dest.odm_combine =
b6bfba6c 2968 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx];
41f03a6d
DL		 2969 else
2970 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2971 pipe_idx++;
2972 } else {
2973 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2974 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
2975 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
2976 pipes[pipe_cnt].pipe.dest.odm_combine =
b6bfba6c 2977 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]];
41f03a6d
DL		 2978 else
2979 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
7ed4e635 2980 }
6de20237 2981
41f03a6d
DL		 2982 if (dc->config.forced_clocks) {
2983 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2984 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
a6465d1f 2985 }
41f03a6d
DL		 2986 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
2987 pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2988 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
2989 pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2990
2991 pipe_cnt++;
2992 }
7ed4e635 2993
41f03a6d
DL		 2994 if (pipe_cnt != pipe_idx) {
2995 if (dc->res_pool->funcs->populate_dml_pipes)
2996 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
fa896813 2997 context, pipes, fast_validate);
41f03a6d
DL		 2998 else
2999 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
fa896813 3000 context, pipes, fast_validate);
41f03a6d 3001 }
7ed4e635 3002
41f03a6d 3003 *out_pipe_cnt = pipe_cnt;
6de20237 3004
41f03a6d
DL		 3005 pipes[0].clks_cfg.voltage = vlevel;
3006 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
3007 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
3008
3009 /* only pipe 0 is read for voltage and dcf/soc clocks */
3010 if (vlevel < 1) {
3011 pipes[0].clks_cfg.voltage = 1;
3012 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
3013 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
3014 }
3015 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3016 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3017 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3018 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3019 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
4de094ee
BL		 3020 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3021 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
b617b265 3022 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
41f03a6d
DL		 3023
3024 if (vlevel < 2) {
3025 pipes[0].clks_cfg.voltage = 2;
3026 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
3027 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
3028 }
3029 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3030 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3031 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3032 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3033 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
4de094ee
BL		 3034 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3035 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
41f03a6d
DL		 3036
3037 if (vlevel < 3) {
3038 pipes[0].clks_cfg.voltage = 3;
3039 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
3040 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
3041 }
3042 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3043 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3044 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3045 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3046 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
4de094ee
BL		 3047 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3048 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
41f03a6d
DL		 3049
3050 pipes[0].clks_cfg.voltage = vlevel;
3051 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
3052 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
3053 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3054 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3055 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3056 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3057 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
4de094ee
BL		 3058 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3059 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
6de20237
EY		 3060}
3061
74458c08
NK		 3062static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
3063{
3064 int i;
3065 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3066 if (!context->res_ctx.pipe_ctx[i].stream)
3067 continue;
f01ee019
FZ		 3068 if (is_dp_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))
3069 return true;
74458c08
NK		 3070 }
3071 return false;
3072}
74458c08 3073
550ff7ad
EY		 3074static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struct dc_state *context)
3075{
3076 int plane_count;
3077 int i;
3078
3079 plane_count = 0;
3080 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3081 if (context->res_ctx.pipe_ctx[i].plane_state)
3082 plane_count++;
3083 }
3084
3085 /*
3086 * Zstate is allowed in following scenarios:
3087 * 1. Single eDP with PSR enabled
3088 * 2. 0 planes (No memory requests)
3089 * 3. Single eDP without PSR but > 5ms stutter period
3090 */
3091 if (plane_count == 0)
3092 return DCN_ZSTATE_SUPPORT_ALLOW;
3093 else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) {
3094 struct dc_link *link = context->streams[0]->sink->link;
3095
3096 if ((link->link_index == 0 && link->psr_settings.psr_feature_enabled)
3097 || context->bw_ctx.dml.vba.StutterPeriod > 5000.0)
3098 return DCN_ZSTATE_SUPPORT_ALLOW;
3099 else
3100 return DCN_ZSTATE_SUPPORT_DISALLOW;
3101 } else
3102 return DCN_ZSTATE_SUPPORT_DISALLOW;
3103}
3104
6de20237
EY		 3105void dcn20_calculate_dlg_params(
3106 struct dc *dc, struct dc_state *context,
3107 display_e2e_pipe_params_st *pipes,
3108 int pipe_cnt,
3109 int vlevel)
3110{
a00d8fd4 3111 int i, pipe_idx;
8e27a2d4 3112
7ed4e635
HW		 3113 /* Writeback MCIF_WB arbitration parameters */
3114 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
3115
3116 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
3117 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
3118 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
173932de 3119 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
ba9012fc
DG		 3120
3121 if (dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz)
3122 context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz;
3123
7ed4e635 3124 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
799c5b9c 3125 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
7ed4e635
HW		 3126 context->bw_ctx.bw.dcn.clk.p_state_change_support =
3127 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
3128 != dm_dram_clock_change_unsupported;
3129 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
8fe44c08 3130
550ff7ad 3131 context->bw_ctx.bw.dcn.clk.zstate_support = decide_zstate_support(dc, context);
74458c08
NK		 3132
3133 context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
7ed4e635 3134
cab5dec4
YS		 3135 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
3136 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
3137
7ed4e635
HW		 3138 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3139 if (!context->res_ctx.pipe_ctx[i].stream)
3140 continue;
a00d8fd4
DL		 3141 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3142 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3143 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3144 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
8fe44c08
AD		 3145 context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes;
3146 context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;
3147
7ed4e635
HW		 3148 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
3149 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
3150 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
3151 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
3152 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
3153 pipe_idx++;
3154 }
925f566c
CL		 3155 /*save a original dppclock copy*/
3156 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
3157 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
41f03a6d
DL		 3158 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
3159 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
7ed4e635 3160
74458c08
NK		 3161 context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes
3162 - context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx;
74458c08 3163
7ed4e635
HW		 3164 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3165 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
3166
3167 if (!context->res_ctx.pipe_ctx[i].stream)
3168 continue;
3169
3f68c01b
ZL		 3170 if (dc->ctx->dce_version == DCN_VERSION_2_01)
3171 cstate_en = false;
3172
7ed4e635
HW		 3173 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
3174 &context->res_ctx.pipe_ctx[i].dlg_regs,
3175 &context->res_ctx.pipe_ctx[i].ttu_regs,
3176 pipes,
3177 pipe_cnt,
3178 pipe_idx,
3179 cstate_en,
f82c916c 3180 context->bw_ctx.bw.dcn.clk.p_state_change_support,
c400ecce 3181 false, false, true);
254eb07c 3182
7ed4e635
HW		 3183 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
3184 &context->res_ctx.pipe_ctx[i].rq_regs,
22667e6e 3185 &pipes[pipe_idx].pipe);
7ed4e635
HW		 3186 pipe_idx++;
3187 }
6de20237
EY		 3188}
3189
057fc695 3190static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
6de20237
EY		 3191 bool fast_validate)
3192{
3193 bool out = false;
3194
3195 BW_VAL_TRACE_SETUP();
3196
3197 int vlevel = 0;
3198 int pipe_split_from[MAX_PIPES];
3199 int pipe_cnt = 0;
fbd7cda0 3200 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
6de20237
EY		 3201 DC_LOGGER_INIT(dc->ctx->logger);
3202
3203 BW_VAL_TRACE_COUNT();
3204
fa896813 3205 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
5e335add
EY		 3206
3207 if (pipe_cnt == 0)
3208 goto validate_out;
6de20237
EY		 3209
3210 if (!out)
3211 goto validate_fail;
3212
3213 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
3214
3215 if (fast_validate) {
3216 BW_VAL_TRACE_SKIP(fast);
3217 goto validate_out;
3218 }
3219
fa896813 3220 dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
6de20237
EY		 3221 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
3222
3223 BW_VAL_TRACE_END_WATERMARKS();
7ed4e635 3224
254eb07c 3225 goto validate_out;
7ed4e635
HW		 3226
3227validate_fail:
00999d99
DL		 3228 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
3229 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
254eb07c 3230
42351c66 3231 BW_VAL_TRACE_SKIP(fail);
254eb07c
JA		 3232 out = false;
3233
3234validate_out:
7ed4e635 3235 kfree(pipes);
254eb07c 3236
42351c66
JA		 3237 BW_VAL_TRACE_FINISH();
3238
254eb07c 3239 return out;
7ed4e635
HW		 3240}
3241
8b91fd8b
DK		 3242/*
3243 * This must be noinline to ensure anything that deals with FP registers
3244 * is contained within this call; previously our compiling with hard-float
3245 * would result in fp instructions being emitted outside of the boundaries
3246 * of the DC_FP_START/END macros, which makes sense as the compiler has no
3247 * idea about what is wrapped and what is not
3248 *
3249 * This is largely just a workaround to avoid breakage introduced with 5.6,
3250 * ideally all fp-using code should be moved into its own file, only that
3251 * should be compiled with hard-float, and all code exported from there
3252 * should be strictly wrapped with DC_FP_START/END
3253 */
3254static noinline bool dcn20_validate_bandwidth_fp(struct dc *dc,
3255 struct dc_state *context, bool fast_validate)
057fc695
JL		 3256{
3257 bool voltage_supported = false;
3258 bool full_pstate_supported = false;
3259 bool dummy_pstate_supported = false;
7a8a3430 3260 double p_state_latency_us;
057fc695 3261
7a8a3430
TP		 3262 p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
3263 context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support =
3264 dc->debug.disable_dram_clock_change_vactive_support;
f00889dc
AL		 3265 context->bw_ctx.dml.soc.allow_dram_clock_one_display_vactive =
3266 dc->debug.enable_dram_clock_change_one_display_vactive;
057fc695 3267
ce271b40
QZ		 3268 /*Unsafe due to current pipe merge and split logic*/
3269 ASSERT(context != dc->current_state);
3270
7a8a3430 3271 if (fast_validate) {
8b91fd8b 3272 return dcn20_validate_bandwidth_internal(dc, context, true);
7a8a3430 3273 }
057fc695
JL		 3274
3275 // Best case, we support full UCLK switch latency
3276 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
3277 full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
3278
3279 if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
3280 (voltage_supported && full_pstate_supported)) {
30c9b7a1 3281 context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported;
057fc695
JL		 3282 goto restore_dml_state;
3283 }
3284
b9e8d95a 3285 // Fallback: Try to only support G6 temperature read latency
057fc695
JL		 3286 context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
3287
3288 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
3289 dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
3290
6abb3f43 3291 if (voltage_supported && (dummy_pstate_supported || !(context->stream_count))) {
057fc695
JL		 3292 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
3293 goto restore_dml_state;
3294 }
3295
b9e8d95a 3296 // ERROR: fallback is supposed to always work.
057fc695
JL		 3297 ASSERT(false);
3298
3299restore_dml_state:
057fc695 3300 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
8b91fd8b
DK		 3301 return voltage_supported;
3302}
057fc695 3303
8b91fd8b
DK		 3304bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
3305 bool fast_validate)
3306{
41401ac6 3307 bool voltage_supported;
8b91fd8b
DK		 3308 DC_FP_START();
3309 voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate);
7a8a3430 3310 DC_FP_END();
057fc695
JL		 3311 return voltage_supported;
3312}
3313
7ed4e635
HW		 3314struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
3315 struct dc_state *state,
3316 const struct resource_pool *pool,
3317 struct dc_stream_state *stream)
3318{
3319 struct resource_context *res_ctx = &state->res_ctx;
3320 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
3321 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
3322
3323 if (!head_pipe)
3324 ASSERT(0);
3325
3326 if (!idle_pipe)
7a17c8ce 3327 return NULL;
7ed4e635
HW		 3328
3329 idle_pipe->stream = head_pipe->stream;
3330 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
3331 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
3332
3333 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
3334 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
3335 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
3336 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
3337
3338 return idle_pipe;
3339}
3340
3341bool dcn20_get_dcc_compression_cap(const struct dc *dc,
3342 const struct dc_dcc_surface_param *input,
3343 struct dc_surface_dcc_cap *output)
3344{
3345 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
3346 dc->res_pool->hubbub,
3347 input,
3348 output);
3349}
3350
3351static void dcn20_destroy_resource_pool(struct resource_pool **pool)
3352{
3353 struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);
3354
d9e32672 3355 dcn20_resource_destruct(dcn20_pool);
7ed4e635
HW		 3356 kfree(dcn20_pool);
3357 *pool = NULL;
3358}
3359
3360
3361static struct dc_cap_funcs cap_funcs = {
3362 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
3363};
3364
3365
8d8c82b6 3366enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state)
7ed4e635 3367{
7ed4e635
HW		 3368 enum surface_pixel_format surf_pix_format = plane_state->format;
3369 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
3370
3371 enum swizzle_mode_values swizzle = DC_SW_LINEAR;
3372
3373 if (bpp == 64)
3374 swizzle = DC_SW_64KB_D;
3375 else
3376 swizzle = DC_SW_64KB_S;
3377
3378 plane_state->tiling_info.gfx9.swizzle = swizzle;
b1c3b7f1 3379 return DC_OK;
7ed4e635
HW		 3380}
3381
25457a1f 3382static const struct resource_funcs dcn20_res_pool_funcs = {
7ed4e635
HW		 3383 .destroy = dcn20_destroy_resource_pool,
3384 .link_enc_create = dcn20_link_encoder_create,
d4caa72e 3385 .panel_cntl_create = dcn20_panel_cntl_create,
7ed4e635 3386 .validate_bandwidth = dcn20_validate_bandwidth,
7ed4e635
HW		 3387 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
3388 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
b4f71c8c 3389 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
7ed4e635
HW		 3390 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
3391 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
8d8c82b6 3392 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
c9ae6e16 3393 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
b6bfba6c 3394 .populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
278141f5 3395 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
7ed4e635
HW		 3396};
3397
bb21290f
CL		 3398bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
3399{
3400 int i;
3401 uint32_t pipe_count = pool->res_cap->num_dwb;
3402
bb21290f
CL		 3403 for (i = 0; i < pipe_count; i++) {
3404 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
3405 GFP_KERNEL);
3406
3407 if (!dwbc20) {
3408 dm_error("DC: failed to create dwbc20!\n");
3409 return false;
3410 }
3411 dcn20_dwbc_construct(dwbc20, ctx,
3412 &dwbc20_regs[i],
3413 &dwbc20_shift,
3414 &dwbc20_mask,
3415 i);
3416 pool->dwbc[i] = &dwbc20->base;
3417 }
3418 return true;
3419}
3420
3421bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
3422{
3423 int i;
3424 uint32_t pipe_count = pool->res_cap->num_dwb;
3425
3426 ASSERT(pipe_count > 0);
3427
3428 for (i = 0; i < pipe_count; i++) {
3429 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub),
3430 GFP_KERNEL);
3431
3432 if (!mcif_wb20) {
3433 dm_error("DC: failed to create mcif_wb20!\n");
3434 return false;
3435 }
3436
3437 dcn20_mmhubbub_construct(mcif_wb20, ctx,
3438 &mcif_wb20_regs[i],
3439 &mcif_wb20_shift,
3440 &mcif_wb20_mask,
3441 i);
3442
3443 pool->mcif_wb[i] = &mcif_wb20->base;
3444 }
3445 return true;
3446}
3447
44e149bb 3448static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
7ed4e635 3449{
3bb11050 3450 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_ATOMIC);
7ed4e635
HW		 3451
3452 if (!pp_smu)
3453 return pp_smu;
3454
3455 dm_pp_get_funcs(ctx, pp_smu);
3456
3457 if (pp_smu->ctx.ver != PP_SMU_VER_NV)
3458 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
3459
3460 return pp_smu;
3461}
3462
44e149bb 3463static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
7ed4e635
HW		 3464{
3465 if (pp_smu && *pp_smu) {
3466 kfree(*pp_smu);
3467 *pp_smu = NULL;
3468 }
3469}
3470
44ce0cd3 3471void dcn20_cap_soc_clocks(
7ed4e635
HW		 3472 struct _vcs_dpi_soc_bounding_box_st *bb,
3473 struct pp_smu_nv_clock_table max_clocks)
3474{
3475 int i;
3476
3477 // First pass - cap all clocks higher than the reported max
3478 for (i = 0; i < bb->num_states; i++) {
3479 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
3480 && max_clocks.dcfClockInKhz != 0)
3481 bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
3482
3483 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
3484 && max_clocks.uClockInKhz != 0)
3485 bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
3486
3487 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
3488 && max_clocks.fabricClockInKhz != 0)
3489 bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
3490
3491 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
3492 && max_clocks.displayClockInKhz != 0)
3493 bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
3494
3495 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
3496 && max_clocks.dppClockInKhz != 0)
3497 bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
3498
3499 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
3500 && max_clocks.phyClockInKhz != 0)
3501 bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
3502
3503 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
3504 && max_clocks.socClockInKhz != 0)
3505 bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
3506
3507 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
3508 && max_clocks.dscClockInKhz != 0)
3509 bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
3510 }
3511
3512 // Second pass - remove all duplicate clock states
3513 for (i = bb->num_states - 1; i > 1; i--) {
3514 bool duplicate = true;
3515
3516 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz)
3517 duplicate = false;
3518 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz)
3519 duplicate = false;
3520 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz)
3521 duplicate = false;
3522 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts)
3523 duplicate = false;
3524 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz)
3525 duplicate = false;
3526 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz)
3527 duplicate = false;
3528 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz)
3529 duplicate = false;
3530 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz)
3531 duplicate = false;
3532
3533 if (duplicate)
3534 bb->num_states--;
3535 }
3536}
3537
44ce0cd3 3538void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
7ed4e635
HW		 3539 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
3540{
c42656f8 3541 struct _vcs_dpi_voltage_scaling_st calculated_states[DC__VOLTAGE_STATES];
f18bc4e5 3542 int i;
7ed4e635 3543 int num_calculated_states = 0;
f18bc4e5 3544 int min_dcfclk = 0;
7ed4e635
HW		 3545
3546 if (num_states == 0)
3547 return;
3548
960b6f4f
RR		 3549 memset(calculated_states, 0, sizeof(calculated_states));
3550
f18bc4e5
JL		 3551 if (dc->bb_overrides.min_dcfclk_mhz > 0)
3552 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
6ce2427d
AL		 3553 else {
3554 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
3555 min_dcfclk = 310;
3556 else
3557 // Accounting for SOC/DCF relationship, we can go as high as
3558 // 506Mhz in Vmin.
3559 min_dcfclk = 506;
3560 }
f18bc4e5 3561
7ed4e635 3562 for (i = 0; i < num_states; i++) {
f18bc4e5
JL		 3563 int min_fclk_required_by_uclk;
3564 calculated_states[i].state = i;
3565 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
7ed4e635 3566
5d36f783 3567 // FCLK:UCLK ratio is 1.08
7a03fdf6
LY		 3568 min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080,
3569 1000000);
7ed4e635 3570
f18bc4e5
JL		 3571 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
3572 min_dcfclk : min_fclk_required_by_uclk;
7ed4e635 3573
f18bc4e5
JL		 3574 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
3575 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
7ed4e635 3576
f18bc4e5
JL		 3577 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
3578 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
7ed4e635 3579
f18bc4e5
JL		 3580 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
3581 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
3582 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
7ed4e635 3583
f18bc4e5 3584 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
7ed4e635 3585
f18bc4e5 3586 num_calculated_states++;
7ed4e635
HW		 3587 }
3588
6da16270
JL		 3589 calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
3590 calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
3591 calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
3592
7ed4e635
HW		 3593 memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
3594 bb->num_states = num_calculated_states;
f18bc4e5
JL		 3595
3596 // Duplicate the last state, DML always an extra state identical to max state to work
3597 memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st));
3598 bb->clock_limits[num_calculated_states].state = bb->num_states;
7ed4e635
HW		 3599}
3600
44ce0cd3 3601void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
7ed4e635 3602{
7ed4e635
HW		 3603 if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
3604 && dc->bb_overrides.sr_exit_time_ns) {
3605 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
3606 }
3607
3608 if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
3609 != dc->bb_overrides.sr_enter_plus_exit_time_ns
3610 && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
3611 bb->sr_enter_plus_exit_time_us =
3612 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
3613 }
3614
3615 if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
3616 && dc->bb_overrides.urgent_latency_ns) {
3617 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
3618 }
3619
3620 if ((int)(bb->dram_clock_change_latency_us * 1000)
3621 != dc->bb_overrides.dram_clock_change_latency_ns
3622 && dc->bb_overrides.dram_clock_change_latency_ns) {
3623 bb->dram_clock_change_latency_us =
3624 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
3625 }
8d829836
JA		 3626
3627 if ((int)(bb->dummy_pstate_latency_us * 1000)
3628 != dc->bb_overrides.dummy_clock_change_latency_ns
3629 && dc->bb_overrides.dummy_clock_change_latency_ns) {
3630 bb->dummy_pstate_latency_us =
3631 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;
3632 }
7ed4e635
HW		 3633}
3634
675a9e38
LL		 3635static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
3636 uint32_t hw_internal_rev)
3637{
e1ab4a91
ML		 3638 if (ASICREV_IS_NAVI14_M(hw_internal_rev))
3639 return &dcn2_0_nv14_soc;
3640
675a9e38
LL		 3641 if (ASICREV_IS_NAVI12_P(hw_internal_rev))
3642 return &dcn2_0_nv12_soc;
3643
3644 return &dcn2_0_soc;
3645}
3646
3647static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(
3648 uint32_t hw_internal_rev)
3649{
72b741af
Z		 3650 /* NV14 */
3651 if (ASICREV_IS_NAVI14_M(hw_internal_rev))
3652 return &dcn2_0_nv14_ip;
3653
675a9e38
LL		 3654 /* NV12 and NV10 */
3655 return &dcn2_0_ip;
3656}
3657
3658static enum dml_project get_dml_project_version(uint32_t hw_internal_rev)
3659{
3660 return DML_PROJECT_NAVI10v2;
3661}
3662
7ed4e635
HW		 3663static bool init_soc_bounding_box(struct dc *dc,
3664 struct dcn20_resource_pool *pool)
3665{
675a9e38
LL		 3666 struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3667 get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);
3668 struct _vcs_dpi_ip_params_st *loaded_ip =
3669 get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);
3670
7ed4e635
HW		 3671 DC_LOGGER_INIT(dc->ctx->logger);
3672
7ed4e635
HW		 3673 if (pool->base.pp_smu) {
3674 struct pp_smu_nv_clock_table max_clocks = {0};
3675 unsigned int uclk_states[8] = {0};
3676 unsigned int num_states = 0;
3677 enum pp_smu_status status;
3678 bool clock_limits_available = false;
3679 bool uclk_states_available = false;
3680
3681 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
3682 status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
3683 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
3684
3685 uclk_states_available = (status == PP_SMU_RESULT_OK);
3686 }
3687
3688 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
3689 status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
3690 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
c2ad17c3
AW		 3691 /* SMU cannot set DCF clock to anything equal to or higher than SOC clock
3692 */
3693 if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
3694 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
7ed4e635
HW		 3695 clock_limits_available = (status == PP_SMU_RESULT_OK);
3696 }
3697
bc39a69a
AJ		 3698 if (clock_limits_available && uclk_states_available && num_states) {
3699 DC_FP_START();
44ce0cd3 3700 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
bc39a69a
AJ		 3701 DC_FP_END();
3702 } else if (clock_limits_available) {
3703 DC_FP_START();
44ce0cd3 3704 dcn20_cap_soc_clocks(loaded_bb, max_clocks);
bc39a69a
AJ		 3705 DC_FP_END();
3706 }
7ed4e635
HW		 3707 }
3708
675a9e38
LL		 3709 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
3710 loaded_ip->max_num_dpp = pool->base.pipe_count;
bc39a69a 3711 DC_FP_START();
44ce0cd3 3712 dcn20_patch_bounding_box(dc, loaded_bb);
bc39a69a 3713 DC_FP_END();
7ed4e635
HW		 3714 return true;
3715}
3716
d9e32672 3717static bool dcn20_resource_construct(
7ed4e635
HW		 3718 uint8_t num_virtual_links,
3719 struct dc *dc,
3720 struct dcn20_resource_pool *pool)
3721{
3722 int i;
3723 struct dc_context *ctx = dc->ctx;
3724 struct irq_service_init_data init_data;
130ac6d8 3725 struct ddc_service_init_data ddc_init_data = {0};
675a9e38
LL		 3726 struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3727 get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);
3728 struct _vcs_dpi_ip_params_st *loaded_ip =
3729 get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev);
3730 enum dml_project dml_project_version =
3731 get_dml_project_version(ctx->asic_id.hw_internal_rev);
7ed4e635
HW		 3732
3733 ctx->dc_bios->regs = &bios_regs;
7ed4e635
HW		 3734 pool->base.funcs = &dcn20_res_pool_funcs;
3735
2ebe1773
BL		 3736 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
3737 pool->base.res_cap = &res_cap_nv14;
3738 pool->base.pipe_count = 5;
3739 pool->base.mpcc_count = 5;
3740 } else {
3741 pool->base.res_cap = &res_cap_nv10;
3742 pool->base.pipe_count = 6;
3743 pool->base.mpcc_count = 6;
3744 }
7ed4e635
HW		 3745 /*************************************************
3746 * Resource + asic cap harcoding *
3747 *************************************************/
3748 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
3749
7ed4e635
HW		 3750 dc->caps.max_downscale_ratio = 200;
3751 dc->caps.i2c_speed_in_khz = 100;
b15cde19 3752 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
7ed4e635 3753 dc->caps.max_cursor_size = 256;
9248681f 3754 dc->caps.min_horizontal_blanking_period = 80;
7ed4e635
HW		 3755 dc->caps.dmdata_alloc_size = 2048;
3756
3757 dc->caps.max_slave_planes = 1;
ae030570
AK		 3758 dc->caps.max_slave_yuv_planes = 1;
3759 dc->caps.max_slave_rgb_planes = 1;
7ed4e635
HW		 3760 dc->caps.post_blend_color_processing = true;
3761 dc->caps.force_dp_tps4_for_cp2520 = true;
ca4f844e 3762 dc->caps.extended_aux_timeout_support = true;
7ed4e635 3763
a8bf7164
KK		 3764 /* Color pipeline capabilities */
3765 dc->caps.color.dpp.dcn_arch = 1;
3766 dc->caps.color.dpp.input_lut_shared = 0;
3767 dc->caps.color.dpp.icsc = 1;
3768 dc->caps.color.dpp.dgam_ram = 1;
3769 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
3770 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
3771 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
3772 dc->caps.color.dpp.dgam_rom_caps.pq = 0;
3773 dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
3774 dc->caps.color.dpp.post_csc = 0;
3775 dc->caps.color.dpp.gamma_corr = 0;
c6160900 3776 dc->caps.color.dpp.dgam_rom_for_yuv = 1;
a8bf7164
KK		 3777
3778 dc->caps.color.dpp.hw_3d_lut = 1;
3779 dc->caps.color.dpp.ogam_ram = 1;
3780 // no OGAM ROM on DCN2, only MPC ROM
3781 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
3782 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
3783 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
3784 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
3785 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
3786 dc->caps.color.dpp.ocsc = 0;
3787
3788 dc->caps.color.mpc.gamut_remap = 0;
3789 dc->caps.color.mpc.num_3dluts = 0;
3790 dc->caps.color.mpc.shared_3d_lut = 0;
3791 dc->caps.color.mpc.ogam_ram = 1;
3792 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
3793 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
3794 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
3795 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
3796 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
3797 dc->caps.color.mpc.ocsc = 1;
3798
803a1412 3799 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) {
7ed4e635 3800 dc->debug = debug_defaults_drv;
803a1412
ES		 3801 } else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
3802 pool->base.pipe_count = 4;
7ed4e635
HW		 3803 pool->base.mpcc_count = pool->base.pipe_count;
3804 dc->debug = debug_defaults_diags;
803a1412 3805 } else {
7ed4e635 3806 dc->debug = debug_defaults_diags;
803a1412 3807 }
7ed4e635
HW		 3808 //dcn2.0x
3809 dc->work_arounds.dedcn20_305_wa = true;
3810
3811 // Init the vm_helper
3812 if (dc->vm_helper)
bda9afda 3813 vm_helper_init(dc->vm_helper, 16);
7ed4e635
HW		 3814
3815 /*************************************************
3816 * Create resources *
3817 *************************************************/
3818
3819 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
3820 dcn20_clock_source_create(ctx, ctx->dc_bios,
3821 CLOCK_SOURCE_COMBO_PHY_PLL0,
3822 &clk_src_regs[0], false);
3823 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
3824 dcn20_clock_source_create(ctx, ctx->dc_bios,
3825 CLOCK_SOURCE_COMBO_PHY_PLL1,
3826 &clk_src_regs[1], false);
3827 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
3828 dcn20_clock_source_create(ctx, ctx->dc_bios,
3829 CLOCK_SOURCE_COMBO_PHY_PLL2,
3830 &clk_src_regs[2], false);
3831 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
3832 dcn20_clock_source_create(ctx, ctx->dc_bios,
3833 CLOCK_SOURCE_COMBO_PHY_PLL3,
3834 &clk_src_regs[3], false);
3835 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
3836 dcn20_clock_source_create(ctx, ctx->dc_bios,
3837 CLOCK_SOURCE_COMBO_PHY_PLL4,
3838 &clk_src_regs[4], false);
3839 pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =
3840 dcn20_clock_source_create(ctx, ctx->dc_bios,
3841 CLOCK_SOURCE_COMBO_PHY_PLL5,
3842 &clk_src_regs[5], false);
3843 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;
3844 /* todo: not reuse phy_pll registers */
3845 pool->base.dp_clock_source =
3846 dcn20_clock_source_create(ctx, ctx->dc_bios,
3847 CLOCK_SOURCE_ID_DP_DTO,
3848 &clk_src_regs[0], true);
3849
3850 for (i = 0; i < pool->base.clk_src_count; i++) {
3851 if (pool->base.clock_sources[i] == NULL) {
3852 dm_error("DC: failed to create clock sources!\n");
3853 BREAK_TO_DEBUGGER();
3854 goto create_fail;
3855 }
3856 }
3857
3858 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
3859 if (pool->base.dccg == NULL) {
3860 dm_error("DC: failed to create dccg!\n");
3861 BREAK_TO_DEBUGGER();
3862 goto create_fail;
3863 }
3864
3865 pool->base.dmcu = dcn20_dmcu_create(ctx,
3866 &dmcu_regs,
3867 &dmcu_shift,
3868 &dmcu_mask);
3869 if (pool->base.dmcu == NULL) {
3870 dm_error("DC: failed to create dmcu!\n");
3871 BREAK_TO_DEBUGGER();
3872 goto create_fail;
3873 }
3874
d7c29549 3875 pool->base.abm = dce_abm_create(ctx,
7ed4e635
HW		 3876 &abm_regs,
3877 &abm_shift,
3878 &abm_mask);
3879 if (pool->base.abm == NULL) {
3880 dm_error("DC: failed to create abm!\n");
3881 BREAK_TO_DEBUGGER();
3882 goto create_fail;
d7c29549 3883 }
7ed4e635
HW		 3884
3885 pool->base.pp_smu = dcn20_pp_smu_create(ctx);
3886
3887
3888 if (!init_soc_bounding_box(dc, pool)) {
3889 dm_error("DC: failed to initialize soc bounding box!\n");
3890 BREAK_TO_DEBUGGER();
3891 goto create_fail;
3892 }
3893
675a9e38 3894 dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version);
7ed4e635
HW		 3895
3896 if (!dc->debug.disable_pplib_wm_range) {
3897 struct pp_smu_wm_range_sets ranges = {0};
3898 int i = 0;
3899
3900 ranges.num_reader_wm_sets = 0;
3901
675a9e38 3902 if (loaded_bb->num_states == 1) {
7ed4e635
HW		 3903 ranges.reader_wm_sets[0].wm_inst = i;
3904 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3905 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3906 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3907 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3908
3909 ranges.num_reader_wm_sets = 1;
675a9e38
LL		 3910 } else if (loaded_bb->num_states > 1) {
3911 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
7ed4e635
HW		 3912 ranges.reader_wm_sets[i].wm_inst = i;
3913 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3914 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
675a9e38
LL		 3915 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
3916 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
7ed4e635
HW		 3917
3918 ranges.num_reader_wm_sets = i + 1;
3919 }
7ed4e635 3920
5d36f783
JL		 3921 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3922 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3923 }
7ed4e635
HW		 3924
3925 ranges.num_writer_wm_sets = 1;
3926
3927 ranges.writer_wm_sets[0].wm_inst = 0;
3928 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3929 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3930 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3931 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3932
3933 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
3934 if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
3935 pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);
3936 }
3937
3938 init_data.ctx = dc->ctx;
3939 pool->base.irqs = dal_irq_service_dcn20_create(&init_data);
3940 if (!pool->base.irqs)
3941 goto create_fail;
3942
3943 /* mem input -> ipp -> dpp -> opp -> TG */
3944 for (i = 0; i < pool->base.pipe_count; i++) {
3945 pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
3946 if (pool->base.hubps[i] == NULL) {
3947 BREAK_TO_DEBUGGER();
3948 dm_error(
3949 "DC: failed to create memory input!\n");
3950 goto create_fail;
3951 }
3952
3953 pool->base.ipps[i] = dcn20_ipp_create(ctx, i);
3954 if (pool->base.ipps[i] == NULL) {
3955 BREAK_TO_DEBUGGER();
3956 dm_error(
3957 "DC: failed to create input pixel processor!\n");
3958 goto create_fail;
3959 }
3960
3961 pool->base.dpps[i] = dcn20_dpp_create(ctx, i);
3962 if (pool->base.dpps[i] == NULL) {
3963 BREAK_TO_DEBUGGER();
3964 dm_error(
3965 "DC: failed to create dpps!\n");
3966 goto create_fail;
3967 }
3968 }
3969 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
3970 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i);
3971 if (pool->base.engines[i] == NULL) {
3972 BREAK_TO_DEBUGGER();
3973 dm_error(
3974 "DC:failed to create aux engine!!\n");
3975 goto create_fail;
3976 }
3977 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i);
3978 if (pool->base.hw_i2cs[i] == NULL) {
3979 BREAK_TO_DEBUGGER();
3980 dm_error(
3981 "DC:failed to create hw i2c!!\n");
3982 goto create_fail;
3983 }
3984 pool->base.sw_i2cs[i] = NULL;
3985 }
3986
3987 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
3988 pool->base.opps[i] = dcn20_opp_create(ctx, i);
3989 if (pool->base.opps[i] == NULL) {
3990 BREAK_TO_DEBUGGER();
3991 dm_error(
3992 "DC: failed to create output pixel processor!\n");
3993 goto create_fail;
3994 }
3995 }
3996
3997 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
3998 pool->base.timing_generators[i] = dcn20_timing_generator_create(
3999 ctx, i);
4000 if (pool->base.timing_generators[i] == NULL) {
4001 BREAK_TO_DEBUGGER();
4002 dm_error("DC: failed to create tg!\n");
4003 goto create_fail;
4004 }
4005 }
4006
4007 pool->base.timing_generator_count = i;
4008
4009 pool->base.mpc = dcn20_mpc_create(ctx);
4010 if (pool->base.mpc == NULL) {
4011 BREAK_TO_DEBUGGER();
4012 dm_error("DC: failed to create mpc!\n");
4013 goto create_fail;
4014 }
4015
4016 pool->base.hubbub = dcn20_hubbub_create(ctx);
4017 if (pool->base.hubbub == NULL) {
4018 BREAK_TO_DEBUGGER();
4019 dm_error("DC: failed to create hubbub!\n");
4020 goto create_fail;
4021 }
4022
97bda032
HW		 4023 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
4024 pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
4025 if (pool->base.dscs[i] == NULL) {
4026 BREAK_TO_DEBUGGER();
4027 dm_error("DC: failed to create display stream compressor %d!\n", i);
4028 goto create_fail;
4029 }
4030 }
7ed4e635 4031
bb21290f
CL		 4032 if (!dcn20_dwbc_create(ctx, &pool->base)) {
4033 BREAK_TO_DEBUGGER();
4034 dm_error("DC: failed to create dwbc!\n");
4035 goto create_fail;
4036 }
4037 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
4038 BREAK_TO_DEBUGGER();
4039 dm_error("DC: failed to create mcif_wb!\n");
4040 goto create_fail;
4041 }
4042
7ed4e635
HW		 4043 if (!resource_construct(num_virtual_links, dc, &pool->base,
4044 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
4045 &res_create_funcs : &res_create_maximus_funcs)))
4046 goto create_fail;
4047
4048 dcn20_hw_sequencer_construct(dc);
4049
3c9de4da
AL		 4050 // IF NV12, set PG function pointer to NULL. It's not that
4051 // PG isn't supported for NV12, it's that we don't want to
4052 // program the registers because that will cause more power
4053 // to be consumed. We could have created dcn20_init_hw to get
4054 // the same effect by checking ASIC rev, but there was a
4055 // request at some point to not check ASIC rev on hw sequencer.
15ce104c 4056 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
3c9de4da 4057 dc->hwseq->funcs.enable_power_gating_plane = NULL;
15ce104c
AL		 4058 dc->debug.disable_dpp_power_gate = true;
4059 dc->debug.disable_hubp_power_gate = true;
4060 }
4061
3c9de4da 4062
7ed4e635
HW		 4063 dc->caps.max_planes = pool->base.pipe_count;
4064
4065 for (i = 0; i < dc->caps.max_planes; ++i)
4066 dc->caps.planes[i] = plane_cap;
4067
4068 dc->cap_funcs = cap_funcs;
4069
d9a07577
JL		 4070 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
4071 ddc_init_data.ctx = dc->ctx;
4072 ddc_init_data.link = NULL;
4073 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
4074 ddc_init_data.id.enum_id = 0;
4075 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
4076 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
4077 } else {
4078 pool->base.oem_device = NULL;
4079 }
4080
7ed4e635
HW		 4081 return true;
4082
4083create_fail:
4084
d9e32672 4085 dcn20_resource_destruct(pool);
7ed4e635
HW		 4086
4087 return false;
4088}
4089
4090struct resource_pool *dcn20_create_resource_pool(
4091 const struct dc_init_data *init_data,
4092 struct dc *dc)
4093{
4094 struct dcn20_resource_pool *pool =
3bb11050 4095 kzalloc(sizeof(struct dcn20_resource_pool), GFP_ATOMIC);
7ed4e635
HW		 4096
4097 if (!pool)
4098 return NULL;
4099
d9e32672 4100 if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool))
7ed4e635
HW		 4101 return &pool->base;
4102
4103 BREAK_TO_DEBUGGER();
4104 kfree(pool);
4105 return NULL;
4106}
Linux 6.x block layer and io_uring tree(s)