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7ed4e635 HW |
1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. | |
6ca3928d | 3 | * Copyright 2019 Raptor Engineering, LLC |
7ed4e635 HW |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: AMD | |
24 | * | |
25 | */ | |
26 | ||
d7929c1e AD |
27 | #include <linux/slab.h> |
28 | ||
7ed4e635 HW |
29 | #include "dm_services.h" |
30 | #include "dc.h" | |
31 | ||
78c77382 AK |
32 | #include "dcn20_init.h" |
33 | ||
7ed4e635 HW |
34 | #include "resource.h" |
35 | #include "include/irq_service_interface.h" | |
36 | #include "dcn20/dcn20_resource.h" | |
37 | ||
ee373411 | 38 | #include "dml/dcn20/dcn20_fpu.h" |
c8b3538d | 39 | |
7ed4e635 HW |
40 | #include "dcn10/dcn10_hubp.h" |
41 | #include "dcn10/dcn10_ipp.h" | |
42 | #include "dcn20_hubbub.h" | |
43 | #include "dcn20_mpc.h" | |
44 | #include "dcn20_hubp.h" | |
45 | #include "irq/dcn20/irq_service_dcn20.h" | |
46 | #include "dcn20_dpp.h" | |
47 | #include "dcn20_optc.h" | |
48 | #include "dcn20_hwseq.h" | |
49 | #include "dce110/dce110_hw_sequencer.h" | |
278141f5 | 50 | #include "dcn10/dcn10_resource.h" |
7ed4e635 HW |
51 | #include "dcn20_opp.h" |
52 | ||
97bda032 | 53 | #include "dcn20_dsc.h" |
97bda032 | 54 | |
7ed4e635 HW |
55 | #include "dcn20_link_encoder.h" |
56 | #include "dcn20_stream_encoder.h" | |
57 | #include "dce/dce_clock_source.h" | |
58 | #include "dce/dce_audio.h" | |
59 | #include "dce/dce_hwseq.h" | |
60 | #include "virtual/virtual_stream_encoder.h" | |
61 | #include "dce110/dce110_resource.h" | |
62 | #include "dml/display_mode_vba.h" | |
63 | #include "dcn20_dccg.h" | |
64 | #include "dcn20_vmid.h" | |
d9a07577 | 65 | #include "dc_link_ddc.h" |
d4caa72e | 66 | #include "dce/dce_panel_cntl.h" |
7ed4e635 HW |
67 | |
68 | #include "navi10_ip_offset.h" | |
69 | ||
70 | #include "dcn/dcn_2_0_0_offset.h" | |
71 | #include "dcn/dcn_2_0_0_sh_mask.h" | |
a771ded8 RL |
72 | #include "dpcs/dpcs_2_0_0_offset.h" |
73 | #include "dpcs/dpcs_2_0_0_sh_mask.h" | |
7ed4e635 HW |
74 | |
75 | #include "nbio/nbio_2_3_offset.h" | |
76 | ||
bb21290f CL |
77 | #include "dcn20/dcn20_dwb.h" |
78 | #include "dcn20/dcn20_mmhubbub.h" | |
79 | ||
7ed4e635 HW |
80 | #include "mmhub/mmhub_2_0_0_offset.h" |
81 | #include "mmhub/mmhub_2_0_0_sh_mask.h" | |
82 | ||
83 | #include "reg_helper.h" | |
84 | #include "dce/dce_abm.h" | |
85 | #include "dce/dce_dmcu.h" | |
86 | #include "dce/dce_aux.h" | |
87 | #include "dce/dce_i2c.h" | |
88 | #include "vm_helper.h" | |
64d283cb | 89 | #include "link_enc_cfg.h" |
7ed4e635 HW |
90 | |
91 | #include "amdgpu_socbb.h" | |
92 | ||
7ed4e635 HW |
93 | #define DC_LOGGER_INIT(logger) |
94 | ||
7ed4e635 HW |
95 | #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL |
96 | #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f | |
97 | #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
98 | #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f | |
99 | #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
100 | #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f | |
101 | #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
102 | #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f | |
103 | #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
104 | #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f | |
105 | #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
106 | #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f | |
107 | #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
108 | #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f | |
109 | #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 | |
110 | #endif | |
111 | ||
112 | ||
113 | enum dcn20_clk_src_array_id { | |
114 | DCN20_CLK_SRC_PLL0, | |
115 | DCN20_CLK_SRC_PLL1, | |
116 | DCN20_CLK_SRC_PLL2, | |
117 | DCN20_CLK_SRC_PLL3, | |
118 | DCN20_CLK_SRC_PLL4, | |
119 | DCN20_CLK_SRC_PLL5, | |
120 | DCN20_CLK_SRC_TOTAL | |
121 | }; | |
122 | ||
123 | /* begin ********************* | |
124 | * macros to expend register list macro defined in HW object header file */ | |
125 | ||
126 | /* DCN */ | |
7ed4e635 HW |
127 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg |
128 | ||
129 | #define BASE(seg) BASE_INNER(seg) | |
130 | ||
131 | #define SR(reg_name)\ | |
132 | .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ | |
133 | mm ## reg_name | |
134 | ||
135 | #define SRI(reg_name, block, id)\ | |
136 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | |
137 | mm ## block ## id ## _ ## reg_name | |
138 | ||
158858bf AP |
139 | #define SRI2_DWB(reg_name, block, id)\ |
140 | .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ | |
141 | mm ## reg_name | |
142 | #define SF_DWB(reg_name, field_name, post_fix)\ | |
143 | .field_name = reg_name ## __ ## field_name ## post_fix | |
144 | ||
145 | #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ | |
146 | .field_name = reg_name ## __ ## field_name ## post_fix | |
147 | ||
7ed4e635 HW |
148 | #define SRIR(var_name, reg_name, block, id)\ |
149 | .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | |
150 | mm ## block ## id ## _ ## reg_name | |
151 | ||
152 | #define SRII(reg_name, block, id)\ | |
153 | .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | |
154 | mm ## block ## id ## _ ## reg_name | |
155 | ||
156 | #define DCCG_SRII(reg_name, block, id)\ | |
157 | .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | |
158 | mm ## block ## id ## _ ## reg_name | |
159 | ||
1e461c37 AC |
160 | #define VUPDATE_SRII(reg_name, block, id)\ |
161 | .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ | |
162 | mm ## reg_name ## _ ## block ## id | |
163 | ||
7ed4e635 HW |
164 | /* NBIO */ |
165 | #define NBIO_BASE_INNER(seg) \ | |
166 | NBIO_BASE__INST0_SEG ## seg | |
167 | ||
168 | #define NBIO_BASE(seg) \ | |
169 | NBIO_BASE_INNER(seg) | |
170 | ||
171 | #define NBIO_SR(reg_name)\ | |
172 | .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ | |
173 | mm ## reg_name | |
174 | ||
175 | /* MMHUB */ | |
176 | #define MMHUB_BASE_INNER(seg) \ | |
177 | MMHUB_BASE__INST0_SEG ## seg | |
178 | ||
179 | #define MMHUB_BASE(seg) \ | |
180 | MMHUB_BASE_INNER(seg) | |
181 | ||
182 | #define MMHUB_SR(reg_name)\ | |
183 | .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ | |
184 | mmMM ## reg_name | |
185 | ||
186 | static const struct bios_registers bios_regs = { | |
187 | NBIO_SR(BIOS_SCRATCH_3), | |
188 | NBIO_SR(BIOS_SCRATCH_6) | |
189 | }; | |
190 | ||
191 | #define clk_src_regs(index, pllid)\ | |
192 | [index] = {\ | |
193 | CS_COMMON_REG_LIST_DCN2_0(index, pllid),\ | |
194 | } | |
195 | ||
196 | static const struct dce110_clk_src_regs clk_src_regs[] = { | |
197 | clk_src_regs(0, A), | |
198 | clk_src_regs(1, B), | |
199 | clk_src_regs(2, C), | |
200 | clk_src_regs(3, D), | |
201 | clk_src_regs(4, E), | |
202 | clk_src_regs(5, F) | |
203 | }; | |
204 | ||
205 | static const struct dce110_clk_src_shift cs_shift = { | |
206 | CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) | |
207 | }; | |
208 | ||
209 | static const struct dce110_clk_src_mask cs_mask = { | |
210 | CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) | |
211 | }; | |
212 | ||
213 | static const struct dce_dmcu_registers dmcu_regs = { | |
214 | DMCU_DCN10_REG_LIST() | |
215 | }; | |
216 | ||
217 | static const struct dce_dmcu_shift dmcu_shift = { | |
218 | DMCU_MASK_SH_LIST_DCN10(__SHIFT) | |
219 | }; | |
220 | ||
221 | static const struct dce_dmcu_mask dmcu_mask = { | |
222 | DMCU_MASK_SH_LIST_DCN10(_MASK) | |
223 | }; | |
d7c29549 | 224 | |
7ed4e635 | 225 | static const struct dce_abm_registers abm_regs = { |
d7c29549 | 226 | ABM_DCN20_REG_LIST() |
7ed4e635 HW |
227 | }; |
228 | ||
229 | static const struct dce_abm_shift abm_shift = { | |
d7c29549 | 230 | ABM_MASK_SH_LIST_DCN20(__SHIFT) |
7ed4e635 HW |
231 | }; |
232 | ||
233 | static const struct dce_abm_mask abm_mask = { | |
d7c29549 | 234 | ABM_MASK_SH_LIST_DCN20(_MASK) |
7ed4e635 | 235 | }; |
d7c29549 | 236 | |
7ed4e635 HW |
237 | #define audio_regs(id)\ |
238 | [id] = {\ | |
239 | AUD_COMMON_REG_LIST(id)\ | |
240 | } | |
241 | ||
242 | static const struct dce_audio_registers audio_regs[] = { | |
243 | audio_regs(0), | |
244 | audio_regs(1), | |
245 | audio_regs(2), | |
246 | audio_regs(3), | |
247 | audio_regs(4), | |
248 | audio_regs(5), | |
249 | audio_regs(6), | |
250 | }; | |
251 | ||
252 | #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ | |
253 | SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ | |
254 | SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ | |
255 | AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) | |
256 | ||
257 | static const struct dce_audio_shift audio_shift = { | |
258 | DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) | |
259 | }; | |
260 | ||
54a9bcb0 | 261 | static const struct dce_audio_mask audio_mask = { |
7ed4e635 HW |
262 | DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) |
263 | }; | |
264 | ||
265 | #define stream_enc_regs(id)\ | |
266 | [id] = {\ | |
267 | SE_DCN2_REG_LIST(id)\ | |
268 | } | |
269 | ||
270 | static const struct dcn10_stream_enc_registers stream_enc_regs[] = { | |
271 | stream_enc_regs(0), | |
272 | stream_enc_regs(1), | |
273 | stream_enc_regs(2), | |
274 | stream_enc_regs(3), | |
275 | stream_enc_regs(4), | |
276 | stream_enc_regs(5), | |
277 | }; | |
278 | ||
279 | static const struct dcn10_stream_encoder_shift se_shift = { | |
280 | SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) | |
281 | }; | |
282 | ||
283 | static const struct dcn10_stream_encoder_mask se_mask = { | |
284 | SE_COMMON_MASK_SH_LIST_DCN20(_MASK) | |
285 | }; | |
286 | ||
287 | ||
288 | #define aux_regs(id)\ | |
289 | [id] = {\ | |
290 | DCN2_AUX_REG_LIST(id)\ | |
291 | } | |
292 | ||
293 | static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { | |
294 | aux_regs(0), | |
295 | aux_regs(1), | |
296 | aux_regs(2), | |
297 | aux_regs(3), | |
298 | aux_regs(4), | |
299 | aux_regs(5) | |
300 | }; | |
301 | ||
302 | #define hpd_regs(id)\ | |
303 | [id] = {\ | |
304 | HPD_REG_LIST(id)\ | |
305 | } | |
306 | ||
307 | static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { | |
308 | hpd_regs(0), | |
309 | hpd_regs(1), | |
310 | hpd_regs(2), | |
311 | hpd_regs(3), | |
312 | hpd_regs(4), | |
313 | hpd_regs(5) | |
314 | }; | |
315 | ||
316 | #define link_regs(id, phyid)\ | |
317 | [id] = {\ | |
318 | LE_DCN10_REG_LIST(id), \ | |
319 | UNIPHY_DCN2_REG_LIST(phyid), \ | |
a771ded8 | 320 | DPCS_DCN2_REG_LIST(id), \ |
7ed4e635 HW |
321 | SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ |
322 | } | |
323 | ||
324 | static const struct dcn10_link_enc_registers link_enc_regs[] = { | |
325 | link_regs(0, A), | |
326 | link_regs(1, B), | |
327 | link_regs(2, C), | |
328 | link_regs(3, D), | |
329 | link_regs(4, E), | |
330 | link_regs(5, F) | |
331 | }; | |
332 | ||
333 | static const struct dcn10_link_enc_shift le_shift = { | |
a771ded8 RL |
334 | LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\ |
335 | DPCS_DCN2_MASK_SH_LIST(__SHIFT) | |
7ed4e635 HW |
336 | }; |
337 | ||
338 | static const struct dcn10_link_enc_mask le_mask = { | |
a771ded8 RL |
339 | LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\ |
340 | DPCS_DCN2_MASK_SH_LIST(_MASK) | |
7ed4e635 HW |
341 | }; |
342 | ||
d4caa72e AK |
343 | static const struct dce_panel_cntl_registers panel_cntl_regs[] = { |
344 | { DCN_PANEL_CNTL_REG_LIST() } | |
904fb6e0 AK |
345 | }; |
346 | ||
d4caa72e AK |
347 | static const struct dce_panel_cntl_shift panel_cntl_shift = { |
348 | DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) | |
904fb6e0 AK |
349 | }; |
350 | ||
d4caa72e AK |
351 | static const struct dce_panel_cntl_mask panel_cntl_mask = { |
352 | DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) | |
904fb6e0 AK |
353 | }; |
354 | ||
7ed4e635 HW |
355 | #define ipp_regs(id)\ |
356 | [id] = {\ | |
357 | IPP_REG_LIST_DCN20(id),\ | |
358 | } | |
359 | ||
360 | static const struct dcn10_ipp_registers ipp_regs[] = { | |
361 | ipp_regs(0), | |
362 | ipp_regs(1), | |
363 | ipp_regs(2), | |
364 | ipp_regs(3), | |
365 | ipp_regs(4), | |
366 | ipp_regs(5), | |
367 | }; | |
368 | ||
369 | static const struct dcn10_ipp_shift ipp_shift = { | |
370 | IPP_MASK_SH_LIST_DCN20(__SHIFT) | |
371 | }; | |
372 | ||
373 | static const struct dcn10_ipp_mask ipp_mask = { | |
374 | IPP_MASK_SH_LIST_DCN20(_MASK), | |
375 | }; | |
376 | ||
377 | #define opp_regs(id)\ | |
378 | [id] = {\ | |
379 | OPP_REG_LIST_DCN20(id),\ | |
380 | } | |
381 | ||
382 | static const struct dcn20_opp_registers opp_regs[] = { | |
383 | opp_regs(0), | |
384 | opp_regs(1), | |
385 | opp_regs(2), | |
386 | opp_regs(3), | |
387 | opp_regs(4), | |
388 | opp_regs(5), | |
389 | }; | |
390 | ||
391 | static const struct dcn20_opp_shift opp_shift = { | |
392 | OPP_MASK_SH_LIST_DCN20(__SHIFT) | |
393 | }; | |
394 | ||
395 | static const struct dcn20_opp_mask opp_mask = { | |
396 | OPP_MASK_SH_LIST_DCN20(_MASK) | |
397 | }; | |
398 | ||
399 | #define aux_engine_regs(id)\ | |
400 | [id] = {\ | |
401 | AUX_COMMON_REG_LIST0(id), \ | |
402 | .AUXN_IMPCAL = 0, \ | |
403 | .AUXP_IMPCAL = 0, \ | |
404 | .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ | |
405 | } | |
406 | ||
407 | static const struct dce110_aux_registers aux_engine_regs[] = { | |
408 | aux_engine_regs(0), | |
409 | aux_engine_regs(1), | |
410 | aux_engine_regs(2), | |
411 | aux_engine_regs(3), | |
412 | aux_engine_regs(4), | |
413 | aux_engine_regs(5) | |
414 | }; | |
415 | ||
416 | #define tf_regs(id)\ | |
417 | [id] = {\ | |
418 | TF_REG_LIST_DCN20(id),\ | |
d9eb70ae | 419 | TF_REG_LIST_DCN20_COMMON_APPEND(id),\ |
7ed4e635 HW |
420 | } |
421 | ||
422 | static const struct dcn2_dpp_registers tf_regs[] = { | |
423 | tf_regs(0), | |
424 | tf_regs(1), | |
425 | tf_regs(2), | |
426 | tf_regs(3), | |
427 | tf_regs(4), | |
428 | tf_regs(5), | |
429 | }; | |
430 | ||
431 | static const struct dcn2_dpp_shift tf_shift = { | |
d56eaa7c | 432 | TF_REG_LIST_SH_MASK_DCN20(__SHIFT), |
c1e34175 | 433 | TF_DEBUG_REG_LIST_SH_DCN20 |
7ed4e635 HW |
434 | }; |
435 | ||
436 | static const struct dcn2_dpp_mask tf_mask = { | |
d56eaa7c | 437 | TF_REG_LIST_SH_MASK_DCN20(_MASK), |
c1e34175 | 438 | TF_DEBUG_REG_LIST_MASK_DCN20 |
7ed4e635 HW |
439 | }; |
440 | ||
bb21290f CL |
441 | #define dwbc_regs_dcn2(id)\ |
442 | [id] = {\ | |
443 | DWBC_COMMON_REG_LIST_DCN2_0(id),\ | |
444 | } | |
445 | ||
446 | static const struct dcn20_dwbc_registers dwbc20_regs[] = { | |
447 | dwbc_regs_dcn2(0), | |
448 | }; | |
449 | ||
450 | static const struct dcn20_dwbc_shift dwbc20_shift = { | |
451 | DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) | |
452 | }; | |
453 | ||
454 | static const struct dcn20_dwbc_mask dwbc20_mask = { | |
455 | DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK) | |
456 | }; | |
457 | ||
458 | #define mcif_wb_regs_dcn2(id)\ | |
459 | [id] = {\ | |
460 | MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\ | |
461 | } | |
462 | ||
463 | static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = { | |
464 | mcif_wb_regs_dcn2(0), | |
465 | }; | |
466 | ||
467 | static const struct dcn20_mmhubbub_shift mcif_wb20_shift = { | |
468 | MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) | |
469 | }; | |
470 | ||
471 | static const struct dcn20_mmhubbub_mask mcif_wb20_mask = { | |
472 | MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK) | |
473 | }; | |
474 | ||
7ed4e635 HW |
475 | static const struct dcn20_mpc_registers mpc_regs = { |
476 | MPC_REG_LIST_DCN2_0(0), | |
477 | MPC_REG_LIST_DCN2_0(1), | |
478 | MPC_REG_LIST_DCN2_0(2), | |
479 | MPC_REG_LIST_DCN2_0(3), | |
480 | MPC_REG_LIST_DCN2_0(4), | |
481 | MPC_REG_LIST_DCN2_0(5), | |
482 | MPC_OUT_MUX_REG_LIST_DCN2_0(0), | |
483 | MPC_OUT_MUX_REG_LIST_DCN2_0(1), | |
484 | MPC_OUT_MUX_REG_LIST_DCN2_0(2), | |
485 | MPC_OUT_MUX_REG_LIST_DCN2_0(3), | |
486 | MPC_OUT_MUX_REG_LIST_DCN2_0(4), | |
487 | MPC_OUT_MUX_REG_LIST_DCN2_0(5), | |
e8027e08 | 488 | MPC_DBG_REG_LIST_DCN2_0() |
7ed4e635 HW |
489 | }; |
490 | ||
491 | static const struct dcn20_mpc_shift mpc_shift = { | |
c1e34175 NA |
492 | MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT), |
493 | MPC_DEBUG_REG_LIST_SH_DCN20 | |
7ed4e635 HW |
494 | }; |
495 | ||
496 | static const struct dcn20_mpc_mask mpc_mask = { | |
c1e34175 NA |
497 | MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK), |
498 | MPC_DEBUG_REG_LIST_MASK_DCN20 | |
7ed4e635 HW |
499 | }; |
500 | ||
501 | #define tg_regs(id)\ | |
502 | [id] = {TG_COMMON_REG_LIST_DCN2_0(id)} | |
503 | ||
504 | ||
505 | static const struct dcn_optc_registers tg_regs[] = { | |
506 | tg_regs(0), | |
507 | tg_regs(1), | |
508 | tg_regs(2), | |
509 | tg_regs(3), | |
510 | tg_regs(4), | |
511 | tg_regs(5) | |
512 | }; | |
513 | ||
514 | static const struct dcn_optc_shift tg_shift = { | |
515 | TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) | |
516 | }; | |
517 | ||
518 | static const struct dcn_optc_mask tg_mask = { | |
519 | TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) | |
520 | }; | |
521 | ||
522 | #define hubp_regs(id)\ | |
523 | [id] = {\ | |
524 | HUBP_REG_LIST_DCN20(id)\ | |
525 | } | |
526 | ||
527 | static const struct dcn_hubp2_registers hubp_regs[] = { | |
528 | hubp_regs(0), | |
529 | hubp_regs(1), | |
530 | hubp_regs(2), | |
531 | hubp_regs(3), | |
532 | hubp_regs(4), | |
533 | hubp_regs(5) | |
534 | }; | |
535 | ||
536 | static const struct dcn_hubp2_shift hubp_shift = { | |
537 | HUBP_MASK_SH_LIST_DCN20(__SHIFT) | |
538 | }; | |
539 | ||
540 | static const struct dcn_hubp2_mask hubp_mask = { | |
541 | HUBP_MASK_SH_LIST_DCN20(_MASK) | |
542 | }; | |
543 | ||
544 | static const struct dcn_hubbub_registers hubbub_reg = { | |
545 | HUBBUB_REG_LIST_DCN20(0) | |
546 | }; | |
547 | ||
548 | static const struct dcn_hubbub_shift hubbub_shift = { | |
549 | HUBBUB_MASK_SH_LIST_DCN20(__SHIFT) | |
550 | }; | |
551 | ||
552 | static const struct dcn_hubbub_mask hubbub_mask = { | |
553 | HUBBUB_MASK_SH_LIST_DCN20(_MASK) | |
554 | }; | |
555 | ||
556 | #define vmid_regs(id)\ | |
557 | [id] = {\ | |
558 | DCN20_VMID_REG_LIST(id)\ | |
559 | } | |
560 | ||
561 | static const struct dcn_vmid_registers vmid_regs[] = { | |
562 | vmid_regs(0), | |
563 | vmid_regs(1), | |
564 | vmid_regs(2), | |
565 | vmid_regs(3), | |
566 | vmid_regs(4), | |
567 | vmid_regs(5), | |
568 | vmid_regs(6), | |
569 | vmid_regs(7), | |
570 | vmid_regs(8), | |
571 | vmid_regs(9), | |
572 | vmid_regs(10), | |
573 | vmid_regs(11), | |
574 | vmid_regs(12), | |
575 | vmid_regs(13), | |
576 | vmid_regs(14), | |
577 | vmid_regs(15) | |
578 | }; | |
579 | ||
580 | static const struct dcn20_vmid_shift vmid_shifts = { | |
581 | DCN20_VMID_MASK_SH_LIST(__SHIFT) | |
582 | }; | |
583 | ||
584 | static const struct dcn20_vmid_mask vmid_masks = { | |
585 | DCN20_VMID_MASK_SH_LIST(_MASK) | |
586 | }; | |
587 | ||
8276dd87 | 588 | static const struct dce110_aux_registers_shift aux_shift = { |
589 | DCN_AUX_MASK_SH_LIST(__SHIFT) | |
590 | }; | |
591 | ||
592 | static const struct dce110_aux_registers_mask aux_mask = { | |
593 | DCN_AUX_MASK_SH_LIST(_MASK) | |
594 | }; | |
595 | ||
bf7f5ac3 YMM |
596 | static int map_transmitter_id_to_phy_instance( |
597 | enum transmitter transmitter) | |
598 | { | |
599 | switch (transmitter) { | |
600 | case TRANSMITTER_UNIPHY_A: | |
601 | return 0; | |
602 | break; | |
603 | case TRANSMITTER_UNIPHY_B: | |
604 | return 1; | |
605 | break; | |
606 | case TRANSMITTER_UNIPHY_C: | |
607 | return 2; | |
608 | break; | |
609 | case TRANSMITTER_UNIPHY_D: | |
610 | return 3; | |
611 | break; | |
612 | case TRANSMITTER_UNIPHY_E: | |
613 | return 4; | |
614 | break; | |
615 | case TRANSMITTER_UNIPHY_F: | |
616 | return 5; | |
617 | break; | |
618 | default: | |
619 | ASSERT(0); | |
620 | return 0; | |
621 | } | |
622 | } | |
8276dd87 | 623 | |
97bda032 HW |
624 | #define dsc_regsDCN20(id)\ |
625 | [id] = {\ | |
626 | DSC_REG_LIST_DCN20(id)\ | |
627 | } | |
628 | ||
629 | static const struct dcn20_dsc_registers dsc_regs[] = { | |
630 | dsc_regsDCN20(0), | |
631 | dsc_regsDCN20(1), | |
632 | dsc_regsDCN20(2), | |
633 | dsc_regsDCN20(3), | |
634 | dsc_regsDCN20(4), | |
635 | dsc_regsDCN20(5) | |
636 | }; | |
637 | ||
638 | static const struct dcn20_dsc_shift dsc_shift = { | |
639 | DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) | |
640 | }; | |
641 | ||
642 | static const struct dcn20_dsc_mask dsc_mask = { | |
643 | DSC_REG_LIST_SH_MASK_DCN20(_MASK) | |
644 | }; | |
7ed4e635 HW |
645 | |
646 | static const struct dccg_registers dccg_regs = { | |
647 | DCCG_REG_LIST_DCN2() | |
648 | }; | |
649 | ||
650 | static const struct dccg_shift dccg_shift = { | |
651 | DCCG_MASK_SH_LIST_DCN2(__SHIFT) | |
652 | }; | |
653 | ||
654 | static const struct dccg_mask dccg_mask = { | |
655 | DCCG_MASK_SH_LIST_DCN2(_MASK) | |
656 | }; | |
657 | ||
658 | static const struct resource_caps res_cap_nv10 = { | |
659 | .num_timing_generator = 6, | |
660 | .num_opp = 6, | |
661 | .num_video_plane = 6, | |
662 | .num_audio = 7, | |
663 | .num_stream_encoder = 6, | |
664 | .num_pll = 6, | |
9cbee6ef | 665 | .num_dwb = 1, |
7ed4e635 HW |
666 | .num_ddc = 6, |
667 | .num_vmid = 16, | |
97bda032 | 668 | .num_dsc = 6, |
7ed4e635 HW |
669 | }; |
670 | ||
671 | static const struct dc_plane_cap plane_cap = { | |
672 | .type = DC_PLANE_TYPE_DCN_UNIVERSAL, | |
673 | .blends_with_above = true, | |
674 | .blends_with_below = true, | |
7ed4e635 | 675 | .per_pixel_alpha = true, |
5b1b2f20 AD |
676 | |
677 | .pixel_format_support = { | |
678 | .argb8888 = true, | |
679 | .nv12 = true, | |
cbec6477 SW |
680 | .fp16 = true, |
681 | .p010 = true | |
5b1b2f20 AD |
682 | }, |
683 | ||
684 | .max_upscale_factor = { | |
685 | .argb8888 = 16000, | |
686 | .nv12 = 16000, | |
687 | .fp16 = 1 | |
688 | }, | |
689 | ||
690 | .max_downscale_factor = { | |
691 | .argb8888 = 250, | |
692 | .nv12 = 250, | |
693 | .fp16 = 1 | |
3b26ca2d IK |
694 | }, |
695 | 16, | |
696 | 16 | |
7ed4e635 | 697 | }; |
2ebe1773 BL |
698 | static const struct resource_caps res_cap_nv14 = { |
699 | .num_timing_generator = 5, | |
700 | .num_opp = 5, | |
701 | .num_video_plane = 5, | |
702 | .num_audio = 6, | |
703 | .num_stream_encoder = 5, | |
704 | .num_pll = 5, | |
80df905d | 705 | .num_dwb = 1, |
2ebe1773 | 706 | .num_ddc = 5, |
6bb27085 ZL |
707 | .num_vmid = 16, |
708 | .num_dsc = 5, | |
2ebe1773 | 709 | }; |
7ed4e635 HW |
710 | |
711 | static const struct dc_debug_options debug_defaults_drv = { | |
f0a574c9 | 712 | .disable_dmcu = false, |
7ed4e635 HW |
713 | .force_abm_enable = false, |
714 | .timing_trace = false, | |
715 | .clock_trace = true, | |
716 | .disable_pplib_clock_request = true, | |
bcfab8e3 | 717 | .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, |
4d25a0d5 | 718 | .force_single_disp_pipe_split = false, |
7ed4e635 HW |
719 | .disable_dcc = DCC_ENABLE, |
720 | .vsr_support = true, | |
721 | .performance_trace = false, | |
722 | .max_downscale_src_width = 5120,/*upto 5K*/ | |
723 | .disable_pplib_wm_range = false, | |
724 | .scl_reset_length10 = true, | |
9e14d4f1 | 725 | .sanity_checks = false, |
1a7d296d | 726 | .underflow_assert_delay_us = 0xFFFFFFFF, |
7ed4e635 HW |
727 | }; |
728 | ||
729 | static const struct dc_debug_options debug_defaults_diags = { | |
f0a574c9 | 730 | .disable_dmcu = false, |
7ed4e635 HW |
731 | .force_abm_enable = false, |
732 | .timing_trace = true, | |
733 | .clock_trace = true, | |
734 | .disable_dpp_power_gate = true, | |
735 | .disable_hubp_power_gate = true, | |
736 | .disable_clock_gate = true, | |
737 | .disable_pplib_clock_request = true, | |
738 | .disable_pplib_wm_range = true, | |
739 | .disable_stutter = true, | |
740 | .scl_reset_length10 = true, | |
1a7d296d | 741 | .underflow_assert_delay_us = 0xFFFFFFFF, |
091018a5 | 742 | .enable_tri_buf = true, |
7ed4e635 HW |
743 | }; |
744 | ||
745 | void dcn20_dpp_destroy(struct dpp **dpp) | |
746 | { | |
747 | kfree(TO_DCN20_DPP(*dpp)); | |
748 | *dpp = NULL; | |
749 | } | |
750 | ||
751 | struct dpp *dcn20_dpp_create( | |
752 | struct dc_context *ctx, | |
753 | uint32_t inst) | |
754 | { | |
755 | struct dcn20_dpp *dpp = | |
3bb11050 | 756 | kzalloc(sizeof(struct dcn20_dpp), GFP_ATOMIC); |
7ed4e635 HW |
757 | |
758 | if (!dpp) | |
759 | return NULL; | |
760 | ||
761 | if (dpp2_construct(dpp, ctx, inst, | |
762 | &tf_regs[inst], &tf_shift, &tf_mask)) | |
763 | return &dpp->base; | |
764 | ||
765 | BREAK_TO_DEBUGGER(); | |
766 | kfree(dpp); | |
767 | return NULL; | |
768 | } | |
769 | ||
770 | struct input_pixel_processor *dcn20_ipp_create( | |
771 | struct dc_context *ctx, uint32_t inst) | |
772 | { | |
773 | struct dcn10_ipp *ipp = | |
3bb11050 | 774 | kzalloc(sizeof(struct dcn10_ipp), GFP_ATOMIC); |
7ed4e635 HW |
775 | |
776 | if (!ipp) { | |
777 | BREAK_TO_DEBUGGER(); | |
778 | return NULL; | |
779 | } | |
780 | ||
781 | dcn20_ipp_construct(ipp, ctx, inst, | |
782 | &ipp_regs[inst], &ipp_shift, &ipp_mask); | |
783 | return &ipp->base; | |
784 | } | |
785 | ||
786 | ||
787 | struct output_pixel_processor *dcn20_opp_create( | |
788 | struct dc_context *ctx, uint32_t inst) | |
789 | { | |
790 | struct dcn20_opp *opp = | |
3bb11050 | 791 | kzalloc(sizeof(struct dcn20_opp), GFP_ATOMIC); |
7ed4e635 HW |
792 | |
793 | if (!opp) { | |
794 | BREAK_TO_DEBUGGER(); | |
795 | return NULL; | |
796 | } | |
797 | ||
798 | dcn20_opp_construct(opp, ctx, inst, | |
799 | &opp_regs[inst], &opp_shift, &opp_mask); | |
800 | return &opp->base; | |
801 | } | |
802 | ||
803 | struct dce_aux *dcn20_aux_engine_create( | |
804 | struct dc_context *ctx, | |
805 | uint32_t inst) | |
806 | { | |
807 | struct aux_engine_dce110 *aux_engine = | |
3bb11050 | 808 | kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC); |
7ed4e635 HW |
809 | |
810 | if (!aux_engine) | |
811 | return NULL; | |
812 | ||
813 | dce110_aux_engine_construct(aux_engine, ctx, inst, | |
814 | SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, | |
8276dd87 | 815 | &aux_engine_regs[inst], |
816 | &aux_mask, | |
f6040a43 | 817 | &aux_shift, |
818 | ctx->dc->caps.extended_aux_timeout_support); | |
7ed4e635 HW |
819 | |
820 | return &aux_engine->base; | |
821 | } | |
822 | #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } | |
823 | ||
824 | static const struct dce_i2c_registers i2c_hw_regs[] = { | |
825 | i2c_inst_regs(1), | |
826 | i2c_inst_regs(2), | |
827 | i2c_inst_regs(3), | |
828 | i2c_inst_regs(4), | |
829 | i2c_inst_regs(5), | |
830 | i2c_inst_regs(6), | |
831 | }; | |
832 | ||
833 | static const struct dce_i2c_shift i2c_shifts = { | |
834 | I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) | |
835 | }; | |
836 | ||
837 | static const struct dce_i2c_mask i2c_masks = { | |
838 | I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) | |
839 | }; | |
840 | ||
841 | struct dce_i2c_hw *dcn20_i2c_hw_create( | |
842 | struct dc_context *ctx, | |
843 | uint32_t inst) | |
844 | { | |
845 | struct dce_i2c_hw *dce_i2c_hw = | |
3bb11050 | 846 | kzalloc(sizeof(struct dce_i2c_hw), GFP_ATOMIC); |
7ed4e635 HW |
847 | |
848 | if (!dce_i2c_hw) | |
849 | return NULL; | |
850 | ||
851 | dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, | |
852 | &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); | |
853 | ||
854 | return dce_i2c_hw; | |
855 | } | |
856 | struct mpc *dcn20_mpc_create(struct dc_context *ctx) | |
857 | { | |
858 | struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), | |
3bb11050 | 859 | GFP_ATOMIC); |
7ed4e635 HW |
860 | |
861 | if (!mpc20) | |
862 | return NULL; | |
863 | ||
864 | dcn20_mpc_construct(mpc20, ctx, | |
865 | &mpc_regs, | |
866 | &mpc_shift, | |
867 | &mpc_mask, | |
868 | 6); | |
869 | ||
870 | return &mpc20->base; | |
871 | } | |
872 | ||
873 | struct hubbub *dcn20_hubbub_create(struct dc_context *ctx) | |
874 | { | |
875 | int i; | |
876 | struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), | |
3bb11050 | 877 | GFP_ATOMIC); |
7ed4e635 HW |
878 | |
879 | if (!hubbub) | |
880 | return NULL; | |
881 | ||
882 | hubbub2_construct(hubbub, ctx, | |
883 | &hubbub_reg, | |
884 | &hubbub_shift, | |
885 | &hubbub_mask); | |
886 | ||
887 | for (i = 0; i < res_cap_nv10.num_vmid; i++) { | |
888 | struct dcn20_vmid *vmid = &hubbub->vmid[i]; | |
889 | ||
890 | vmid->ctx = ctx; | |
891 | ||
892 | vmid->regs = &vmid_regs[i]; | |
893 | vmid->shifts = &vmid_shifts; | |
894 | vmid->masks = &vmid_masks; | |
895 | } | |
896 | ||
897 | return &hubbub->base; | |
898 | } | |
899 | ||
900 | struct timing_generator *dcn20_timing_generator_create( | |
901 | struct dc_context *ctx, | |
902 | uint32_t instance) | |
903 | { | |
904 | struct optc *tgn10 = | |
3bb11050 | 905 | kzalloc(sizeof(struct optc), GFP_ATOMIC); |
7ed4e635 HW |
906 | |
907 | if (!tgn10) | |
908 | return NULL; | |
909 | ||
910 | tgn10->base.inst = instance; | |
911 | tgn10->base.ctx = ctx; | |
912 | ||
913 | tgn10->tg_regs = &tg_regs[instance]; | |
914 | tgn10->tg_shift = &tg_shift; | |
915 | tgn10->tg_mask = &tg_mask; | |
916 | ||
917 | dcn20_timing_generator_init(tgn10); | |
918 | ||
919 | return &tgn10->base; | |
920 | } | |
921 | ||
922 | static const struct encoder_feature_support link_enc_feature = { | |
923 | .max_hdmi_deep_color = COLOR_DEPTH_121212, | |
924 | .max_hdmi_pixel_clock = 600000, | |
925 | .hdmi_ycbcr420_supported = true, | |
926 | .dp_ycbcr420_supported = true, | |
c14b726e | 927 | .fec_supported = true, |
7ed4e635 HW |
928 | .flags.bits.IS_HBR2_CAPABLE = true, |
929 | .flags.bits.IS_HBR3_CAPABLE = true, | |
930 | .flags.bits.IS_TPS3_CAPABLE = true, | |
931 | .flags.bits.IS_TPS4_CAPABLE = true | |
932 | }; | |
933 | ||
934 | struct link_encoder *dcn20_link_encoder_create( | |
e216431b | 935 | struct dc_context *ctx, |
7ed4e635 HW |
936 | const struct encoder_init_data *enc_init_data) |
937 | { | |
938 | struct dcn20_link_encoder *enc20 = | |
939 | kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); | |
bf7f5ac3 | 940 | int link_regs_id; |
7ed4e635 HW |
941 | |
942 | if (!enc20) | |
943 | return NULL; | |
944 | ||
bf7f5ac3 YMM |
945 | link_regs_id = |
946 | map_transmitter_id_to_phy_instance(enc_init_data->transmitter); | |
947 | ||
7ed4e635 HW |
948 | dcn20_link_encoder_construct(enc20, |
949 | enc_init_data, | |
950 | &link_enc_feature, | |
bf7f5ac3 | 951 | &link_enc_regs[link_regs_id], |
7ed4e635 HW |
952 | &link_enc_aux_regs[enc_init_data->channel - 1], |
953 | &link_enc_hpd_regs[enc_init_data->hpd_source], | |
954 | &le_shift, | |
955 | &le_mask); | |
956 | ||
957 | return &enc20->enc10.base; | |
958 | } | |
959 | ||
d4caa72e | 960 | static struct panel_cntl *dcn20_panel_cntl_create(const struct panel_cntl_init_data *init_data) |
904fb6e0 | 961 | { |
d4caa72e AK |
962 | struct dce_panel_cntl *panel_cntl = |
963 | kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); | |
904fb6e0 | 964 | |
d4caa72e | 965 | if (!panel_cntl) |
904fb6e0 AK |
966 | return NULL; |
967 | ||
d4caa72e | 968 | dce_panel_cntl_construct(panel_cntl, |
904fb6e0 | 969 | init_data, |
d4caa72e AK |
970 | &panel_cntl_regs[init_data->inst], |
971 | &panel_cntl_shift, | |
972 | &panel_cntl_mask); | |
904fb6e0 | 973 | |
d4caa72e | 974 | return &panel_cntl->base; |
904fb6e0 AK |
975 | } |
976 | ||
dfd84d90 | 977 | static struct clock_source *dcn20_clock_source_create( |
7ed4e635 HW |
978 | struct dc_context *ctx, |
979 | struct dc_bios *bios, | |
980 | enum clock_source_id id, | |
981 | const struct dce110_clk_src_regs *regs, | |
982 | bool dp_clk_src) | |
983 | { | |
984 | struct dce110_clk_src *clk_src = | |
3bb11050 | 985 | kzalloc(sizeof(struct dce110_clk_src), GFP_ATOMIC); |
7ed4e635 HW |
986 | |
987 | if (!clk_src) | |
988 | return NULL; | |
989 | ||
990 | if (dcn20_clk_src_construct(clk_src, ctx, bios, id, | |
991 | regs, &cs_shift, &cs_mask)) { | |
992 | clk_src->base.dp_clk_src = dp_clk_src; | |
993 | return &clk_src->base; | |
994 | } | |
995 | ||
cabe144b | 996 | kfree(clk_src); |
7ed4e635 HW |
997 | BREAK_TO_DEBUGGER(); |
998 | return NULL; | |
999 | } | |
1000 | ||
1001 | static void read_dce_straps( | |
1002 | struct dc_context *ctx, | |
1003 | struct resource_straps *straps) | |
1004 | { | |
1005 | generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), | |
1006 | FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); | |
1007 | } | |
1008 | ||
1009 | static struct audio *dcn20_create_audio( | |
1010 | struct dc_context *ctx, unsigned int inst) | |
1011 | { | |
1012 | return dce_audio_create(ctx, inst, | |
1013 | &audio_regs[inst], &audio_shift, &audio_mask); | |
1014 | } | |
1015 | ||
1016 | struct stream_encoder *dcn20_stream_encoder_create( | |
1017 | enum engine_id eng_id, | |
1018 | struct dc_context *ctx) | |
1019 | { | |
1020 | struct dcn10_stream_encoder *enc1 = | |
1021 | kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); | |
1022 | ||
1023 | if (!enc1) | |
1024 | return NULL; | |
1025 | ||
9fd4c2d7 ZL |
1026 | if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) { |
1027 | if (eng_id >= ENGINE_ID_DIGD) | |
1028 | eng_id++; | |
1029 | } | |
1030 | ||
7ed4e635 HW |
1031 | dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, |
1032 | &stream_enc_regs[eng_id], | |
1033 | &se_shift, &se_mask); | |
1034 | ||
1035 | return &enc1->base; | |
1036 | } | |
1037 | ||
1038 | static const struct dce_hwseq_registers hwseq_reg = { | |
1039 | HWSEQ_DCN2_REG_LIST() | |
1040 | }; | |
1041 | ||
1042 | static const struct dce_hwseq_shift hwseq_shift = { | |
1043 | HWSEQ_DCN2_MASK_SH_LIST(__SHIFT) | |
1044 | }; | |
1045 | ||
1046 | static const struct dce_hwseq_mask hwseq_mask = { | |
1047 | HWSEQ_DCN2_MASK_SH_LIST(_MASK) | |
1048 | }; | |
1049 | ||
1050 | struct dce_hwseq *dcn20_hwseq_create( | |
1051 | struct dc_context *ctx) | |
1052 | { | |
1053 | struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); | |
1054 | ||
1055 | if (hws) { | |
1056 | hws->ctx = ctx; | |
1057 | hws->regs = &hwseq_reg; | |
1058 | hws->shifts = &hwseq_shift; | |
1059 | hws->masks = &hwseq_mask; | |
1060 | } | |
1061 | return hws; | |
1062 | } | |
1063 | ||
1064 | static const struct resource_create_funcs res_create_funcs = { | |
1065 | .read_dce_straps = read_dce_straps, | |
1066 | .create_audio = dcn20_create_audio, | |
1067 | .create_stream_encoder = dcn20_stream_encoder_create, | |
1068 | .create_hwseq = dcn20_hwseq_create, | |
1069 | }; | |
1070 | ||
1071 | static const struct resource_create_funcs res_create_maximus_funcs = { | |
1072 | .read_dce_straps = NULL, | |
1073 | .create_audio = NULL, | |
1074 | .create_stream_encoder = NULL, | |
1075 | .create_hwseq = dcn20_hwseq_create, | |
1076 | }; | |
1077 | ||
44e149bb AD |
1078 | static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu); |
1079 | ||
7ed4e635 HW |
1080 | void dcn20_clock_source_destroy(struct clock_source **clk_src) |
1081 | { | |
1082 | kfree(TO_DCE110_CLK_SRC(*clk_src)); | |
1083 | *clk_src = NULL; | |
1084 | } | |
1085 | ||
97bda032 HW |
1086 | |
1087 | struct display_stream_compressor *dcn20_dsc_create( | |
1088 | struct dc_context *ctx, uint32_t inst) | |
1089 | { | |
1090 | struct dcn20_dsc *dsc = | |
3bb11050 | 1091 | kzalloc(sizeof(struct dcn20_dsc), GFP_ATOMIC); |
97bda032 HW |
1092 | |
1093 | if (!dsc) { | |
1094 | BREAK_TO_DEBUGGER(); | |
1095 | return NULL; | |
1096 | } | |
1097 | ||
1098 | dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); | |
1099 | return &dsc->base; | |
1100 | } | |
1101 | ||
1102 | void dcn20_dsc_destroy(struct display_stream_compressor **dsc) | |
1103 | { | |
1104 | kfree(container_of(*dsc, struct dcn20_dsc, base)); | |
1105 | *dsc = NULL; | |
1106 | } | |
1107 | ||
7ed4e635 | 1108 | |
d9e32672 | 1109 | static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) |
7ed4e635 HW |
1110 | { |
1111 | unsigned int i; | |
1112 | ||
1113 | for (i = 0; i < pool->base.stream_enc_count; i++) { | |
1114 | if (pool->base.stream_enc[i] != NULL) { | |
1115 | kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); | |
1116 | pool->base.stream_enc[i] = NULL; | |
1117 | } | |
1118 | } | |
1119 | ||
97bda032 HW |
1120 | for (i = 0; i < pool->base.res_cap->num_dsc; i++) { |
1121 | if (pool->base.dscs[i] != NULL) | |
1122 | dcn20_dsc_destroy(&pool->base.dscs[i]); | |
1123 | } | |
7ed4e635 HW |
1124 | |
1125 | if (pool->base.mpc != NULL) { | |
1126 | kfree(TO_DCN20_MPC(pool->base.mpc)); | |
1127 | pool->base.mpc = NULL; | |
1128 | } | |
1129 | if (pool->base.hubbub != NULL) { | |
1130 | kfree(pool->base.hubbub); | |
1131 | pool->base.hubbub = NULL; | |
1132 | } | |
1133 | for (i = 0; i < pool->base.pipe_count; i++) { | |
1134 | if (pool->base.dpps[i] != NULL) | |
1135 | dcn20_dpp_destroy(&pool->base.dpps[i]); | |
1136 | ||
1137 | if (pool->base.ipps[i] != NULL) | |
1138 | pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); | |
1139 | ||
1140 | if (pool->base.hubps[i] != NULL) { | |
1141 | kfree(TO_DCN20_HUBP(pool->base.hubps[i])); | |
1142 | pool->base.hubps[i] = NULL; | |
1143 | } | |
1144 | ||
1145 | if (pool->base.irqs != NULL) { | |
1146 | dal_irq_service_destroy(&pool->base.irqs); | |
1147 | } | |
1148 | } | |
1149 | ||
1150 | for (i = 0; i < pool->base.res_cap->num_ddc; i++) { | |
1151 | if (pool->base.engines[i] != NULL) | |
1152 | dce110_engine_destroy(&pool->base.engines[i]); | |
1153 | if (pool->base.hw_i2cs[i] != NULL) { | |
1154 | kfree(pool->base.hw_i2cs[i]); | |
1155 | pool->base.hw_i2cs[i] = NULL; | |
1156 | } | |
1157 | if (pool->base.sw_i2cs[i] != NULL) { | |
1158 | kfree(pool->base.sw_i2cs[i]); | |
1159 | pool->base.sw_i2cs[i] = NULL; | |
1160 | } | |
1161 | } | |
1162 | ||
1163 | for (i = 0; i < pool->base.res_cap->num_opp; i++) { | |
1164 | if (pool->base.opps[i] != NULL) | |
1165 | pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); | |
1166 | } | |
1167 | ||
1168 | for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { | |
1169 | if (pool->base.timing_generators[i] != NULL) { | |
1170 | kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); | |
1171 | pool->base.timing_generators[i] = NULL; | |
1172 | } | |
1173 | } | |
1174 | ||
bb21290f CL |
1175 | for (i = 0; i < pool->base.res_cap->num_dwb; i++) { |
1176 | if (pool->base.dwbc[i] != NULL) { | |
1177 | kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); | |
1178 | pool->base.dwbc[i] = NULL; | |
1179 | } | |
1180 | if (pool->base.mcif_wb[i] != NULL) { | |
1181 | kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); | |
1182 | pool->base.mcif_wb[i] = NULL; | |
1183 | } | |
1184 | } | |
1185 | ||
7ed4e635 HW |
1186 | for (i = 0; i < pool->base.audio_count; i++) { |
1187 | if (pool->base.audios[i]) | |
1188 | dce_aud_destroy(&pool->base.audios[i]); | |
1189 | } | |
1190 | ||
1191 | for (i = 0; i < pool->base.clk_src_count; i++) { | |
1192 | if (pool->base.clock_sources[i] != NULL) { | |
1193 | dcn20_clock_source_destroy(&pool->base.clock_sources[i]); | |
1194 | pool->base.clock_sources[i] = NULL; | |
1195 | } | |
1196 | } | |
1197 | ||
1198 | if (pool->base.dp_clock_source != NULL) { | |
1199 | dcn20_clock_source_destroy(&pool->base.dp_clock_source); | |
1200 | pool->base.dp_clock_source = NULL; | |
1201 | } | |
1202 | ||
1203 | ||
1204 | if (pool->base.abm != NULL) | |
1205 | dce_abm_destroy(&pool->base.abm); | |
1206 | ||
1207 | if (pool->base.dmcu != NULL) | |
1208 | dce_dmcu_destroy(&pool->base.dmcu); | |
1209 | ||
1210 | if (pool->base.dccg != NULL) | |
1211 | dcn_dccg_destroy(&pool->base.dccg); | |
1212 | ||
1213 | if (pool->base.pp_smu != NULL) | |
1214 | dcn20_pp_smu_destroy(&pool->base.pp_smu); | |
1215 | ||
d9a07577 JL |
1216 | if (pool->base.oem_device != NULL) |
1217 | dal_ddc_service_destroy(&pool->base.oem_device); | |
7ed4e635 HW |
1218 | } |
1219 | ||
1220 | struct hubp *dcn20_hubp_create( | |
1221 | struct dc_context *ctx, | |
1222 | uint32_t inst) | |
1223 | { | |
1224 | struct dcn20_hubp *hubp2 = | |
3bb11050 | 1225 | kzalloc(sizeof(struct dcn20_hubp), GFP_ATOMIC); |
7ed4e635 HW |
1226 | |
1227 | if (!hubp2) | |
1228 | return NULL; | |
1229 | ||
1230 | if (hubp2_construct(hubp2, ctx, inst, | |
1231 | &hubp_regs[inst], &hubp_shift, &hubp_mask)) | |
1232 | return &hubp2->base; | |
1233 | ||
1234 | BREAK_TO_DEBUGGER(); | |
1235 | kfree(hubp2); | |
1236 | return NULL; | |
1237 | } | |
1238 | ||
1239 | static void get_pixel_clock_parameters( | |
1240 | struct pipe_ctx *pipe_ctx, | |
1241 | struct pixel_clk_params *pixel_clk_params) | |
1242 | { | |
1243 | const struct dc_stream_state *stream = pipe_ctx->stream; | |
b1f6d01c DL |
1244 | struct pipe_ctx *odm_pipe; |
1245 | int opp_cnt = 1; | |
64d283cb JK |
1246 | struct dc_link *link = stream->link; |
1247 | struct link_encoder *link_enc = NULL; | |
88ef4c5b ST |
1248 | struct dc *dc = pipe_ctx->stream->ctx->dc; |
1249 | struct dce_hwseq *hws = dc->hwseq; | |
b1f6d01c DL |
1250 | |
1251 | for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) | |
1252 | opp_cnt++; | |
7ed4e635 HW |
1253 | |
1254 | pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; | |
64d283cb | 1255 | |
66d58bf7 | 1256 | link_enc = link_enc_cfg_get_link_enc(link); |
64d283cb JK |
1257 | if (link_enc) |
1258 | pixel_clk_params->encoder_object_id = link_enc->id; | |
0c7ea6f8 | 1259 | |
7ed4e635 HW |
1260 | pixel_clk_params->signal_type = pipe_ctx->stream->signal; |
1261 | pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; | |
1262 | /* TODO: un-hardcode*/ | |
f01ee019 | 1263 | /* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */ |
7ed4e635 HW |
1264 | pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * |
1265 | LINK_RATE_REF_FREQ_IN_KHZ; | |
1266 | pixel_clk_params->flags.ENABLE_SS = 0; | |
1267 | pixel_clk_params->color_depth = | |
1268 | stream->timing.display_color_depth; | |
1269 | pixel_clk_params->flags.DISPLAY_BLANKED = 1; | |
1270 | pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; | |
1271 | ||
1272 | if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) | |
1273 | pixel_clk_params->color_depth = COLOR_DEPTH_888; | |
1274 | ||
b1f6d01c DL |
1275 | if (opp_cnt == 4) |
1276 | pixel_clk_params->requested_pix_clk_100hz /= 4; | |
78c77382 | 1277 | else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2) |
7ed4e635 | 1278 | pixel_clk_params->requested_pix_clk_100hz /= 2; |
88ef4c5b ST |
1279 | else if (hws->funcs.is_dp_dig_pixel_rate_div_policy) { |
1280 | if (hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)) | |
1281 | pixel_clk_params->requested_pix_clk_100hz /= 2; | |
1282 | } | |
1283 | ||
7ed4e635 HW |
1284 | if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) |
1285 | pixel_clk_params->requested_pix_clk_100hz *= 2; | |
1286 | ||
1287 | } | |
1288 | ||
1289 | static void build_clamping_params(struct dc_stream_state *stream) | |
1290 | { | |
1291 | stream->clamping.clamping_level = CLAMPING_FULL_RANGE; | |
1292 | stream->clamping.c_depth = stream->timing.display_color_depth; | |
1293 | stream->clamping.pixel_encoding = stream->timing.pixel_encoding; | |
1294 | } | |
1295 | ||
1296 | static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) | |
1297 | { | |
1298 | ||
1299 | get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); | |
1300 | ||
1301 | pipe_ctx->clock_source->funcs->get_pix_clk_dividers( | |
1302 | pipe_ctx->clock_source, | |
1303 | &pipe_ctx->stream_res.pix_clk_params, | |
1304 | &pipe_ctx->pll_settings); | |
1305 | ||
1306 | pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; | |
1307 | ||
1308 | resource_build_bit_depth_reduction_params(pipe_ctx->stream, | |
1309 | &pipe_ctx->stream->bit_depth_params); | |
1310 | build_clamping_params(pipe_ctx->stream); | |
1311 | ||
1312 | return DC_OK; | |
1313 | } | |
1314 | ||
1315 | enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream) | |
1316 | { | |
1317 | enum dc_status status = DC_OK; | |
1318 | struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); | |
1319 | ||
7ed4e635 HW |
1320 | if (!pipe_ctx) |
1321 | return DC_ERROR_UNEXPECTED; | |
1322 | ||
1323 | ||
1324 | status = build_pipe_hw_param(pipe_ctx); | |
1325 | ||
1326 | return status; | |
1327 | } | |
1328 | ||
97bda032 | 1329 | |
570bc18c | 1330 | void dcn20_acquire_dsc(const struct dc *dc, |
14e49bb3 | 1331 | struct resource_context *res_ctx, |
eab4bb97 NC |
1332 | struct display_stream_compressor **dsc, |
1333 | int pipe_idx) | |
97bda032 HW |
1334 | { |
1335 | int i; | |
14e49bb3 NC |
1336 | const struct resource_pool *pool = dc->res_pool; |
1337 | struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc; | |
c9ae6e16 | 1338 | |
14e49bb3 | 1339 | ASSERT(*dsc == NULL); /* If this ASSERT fails, dsc was not released properly */ |
c9ae6e16 | 1340 | *dsc = NULL; |
97bda032 | 1341 | |
14e49bb3 | 1342 | /* Always do 1-to-1 mapping when number of DSCs is same as number of pipes */ |
eab4bb97 NC |
1343 | if (pool->res_cap->num_dsc == pool->res_cap->num_opp) { |
1344 | *dsc = pool->dscs[pipe_idx]; | |
1345 | res_ctx->is_dsc_acquired[pipe_idx] = true; | |
1346 | return; | |
1347 | } | |
1348 | ||
14e49bb3 NC |
1349 | /* Return old DSC to avoid the need for re-programming */ |
1350 | if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) { | |
1351 | *dsc = dsc_old; | |
1352 | res_ctx->is_dsc_acquired[dsc_old->inst] = true; | |
1353 | return ; | |
1354 | } | |
1355 | ||
97bda032 HW |
1356 | /* Find first free DSC */ |
1357 | for (i = 0; i < pool->res_cap->num_dsc; i++) | |
1358 | if (!res_ctx->is_dsc_acquired[i]) { | |
c9ae6e16 | 1359 | *dsc = pool->dscs[i]; |
97bda032 HW |
1360 | res_ctx->is_dsc_acquired[i] = true; |
1361 | break; | |
1362 | } | |
97bda032 HW |
1363 | } |
1364 | ||
7287a675 | 1365 | void dcn20_release_dsc(struct resource_context *res_ctx, |
97bda032 | 1366 | const struct resource_pool *pool, |
c9ae6e16 | 1367 | struct display_stream_compressor **dsc) |
97bda032 HW |
1368 | { |
1369 | int i; | |
1370 | ||
1371 | for (i = 0; i < pool->res_cap->num_dsc; i++) | |
c9ae6e16 | 1372 | if (pool->dscs[i] == *dsc) { |
97bda032 | 1373 | res_ctx->is_dsc_acquired[i] = false; |
c9ae6e16 | 1374 | *dsc = NULL; |
97bda032 HW |
1375 | break; |
1376 | } | |
1377 | } | |
1378 | ||
7ed4e635 | 1379 | |
7ed4e635 | 1380 | |
8c20a1ed | 1381 | enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, |
c9ae6e16 NC |
1382 | struct dc_state *dc_ctx, |
1383 | struct dc_stream_state *dc_stream) | |
1384 | { | |
1385 | enum dc_status result = DC_OK; | |
1386 | int i; | |
97bda032 | 1387 | |
c9ae6e16 NC |
1388 | /* Get a DSC if required and available */ |
1389 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |
1390 | struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i]; | |
97bda032 | 1391 | |
2e68ad8f BL |
1392 | if (pipe_ctx->top_pipe) |
1393 | continue; | |
1394 | ||
c9ae6e16 NC |
1395 | if (pipe_ctx->stream != dc_stream) |
1396 | continue; | |
97bda032 | 1397 | |
8c20a1ed DF |
1398 | if (pipe_ctx->stream_res.dsc) |
1399 | continue; | |
1400 | ||
570bc18c | 1401 | dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i); |
97bda032 | 1402 | |
c9ae6e16 NC |
1403 | /* The number of DSCs can be less than the number of pipes */ |
1404 | if (!pipe_ctx->stream_res.dsc) { | |
c9ae6e16 | 1405 | result = DC_NO_DSC_RESOURCE; |
97bda032 | 1406 | } |
7ed4e635 | 1407 | |
c9ae6e16 NC |
1408 | break; |
1409 | } | |
7ed4e635 HW |
1410 | |
1411 | return result; | |
1412 | } | |
1413 | ||
1414 | ||
ba32c50f | 1415 | static enum dc_status remove_dsc_from_stream_resource(struct dc *dc, |
c9ae6e16 NC |
1416 | struct dc_state *new_ctx, |
1417 | struct dc_stream_state *dc_stream) | |
7ed4e635 HW |
1418 | { |
1419 | struct pipe_ctx *pipe_ctx = NULL; | |
1420 | int i; | |
1421 | ||
7ed4e635 HW |
1422 | for (i = 0; i < MAX_PIPES; i++) { |
1423 | if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) { | |
1424 | pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; | |
b1f6d01c DL |
1425 | |
1426 | if (pipe_ctx->stream_res.dsc) | |
7287a675 | 1427 | dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc); |
7ed4e635 HW |
1428 | } |
1429 | } | |
1430 | ||
1431 | if (!pipe_ctx) | |
1432 | return DC_ERROR_UNEXPECTED; | |
b1f6d01c DL |
1433 | else |
1434 | return DC_OK; | |
7ed4e635 | 1435 | } |
c9ae6e16 NC |
1436 | |
1437 | ||
1438 | enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) | |
1439 | { | |
1440 | enum dc_status result = DC_ERROR_UNEXPECTED; | |
1441 | ||
1442 | result = resource_map_pool_resources(dc, new_ctx, dc_stream); | |
1443 | ||
1444 | if (result == DC_OK) | |
1445 | result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); | |
1446 | ||
c9ae6e16 NC |
1447 | /* Get a DSC if required and available */ |
1448 | if (result == DC_OK && dc_stream->timing.flags.DSC) | |
8c20a1ed | 1449 | result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream); |
c9ae6e16 NC |
1450 | |
1451 | if (result == DC_OK) | |
1452 | result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream); | |
1453 | ||
1454 | return result; | |
1455 | } | |
1456 | ||
1457 | ||
1458 | enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) | |
1459 | { | |
1460 | enum dc_status result = DC_OK; | |
1461 | ||
ba32c50f | 1462 | result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream); |
c9ae6e16 NC |
1463 | |
1464 | return result; | |
1465 | } | |
7ed4e635 | 1466 | |
a6126e14 RS |
1467 | /** |
1468 | * dcn20_split_stream_for_odm - Check if stream can be splited for ODM | |
1469 | * | |
1470 | * @dc: DC object with resource pool info required for pipe split | |
1471 | * @res_ctx: Persistent state of resources | |
1472 | * @prev_odm_pipe: Reference to the previous ODM pipe | |
1473 | * @next_odm_pipe: Reference to the next ODM pipe | |
1474 | * | |
1475 | * This function takes a logically active pipe and a logically free pipe and | |
1476 | * halves all the scaling parameters that need to be halved while populating | |
1477 | * the free pipe with the required resources and configuring the next/previous | |
1478 | * ODM pipe pointers. | |
1479 | * | |
1480 | * Return: | |
1481 | * Return true if split stream for ODM is possible, otherwise, return false. | |
1482 | */ | |
b6bfba6c | 1483 | bool dcn20_split_stream_for_odm( |
14e49bb3 | 1484 | const struct dc *dc, |
b1f6d01c | 1485 | struct resource_context *res_ctx, |
b1f6d01c DL |
1486 | struct pipe_ctx *prev_odm_pipe, |
1487 | struct pipe_ctx *next_odm_pipe) | |
1488 | { | |
1489 | int pipe_idx = next_odm_pipe->pipe_idx; | |
14e49bb3 | 1490 | const struct resource_pool *pool = dc->res_pool; |
b1f6d01c DL |
1491 | |
1492 | *next_odm_pipe = *prev_odm_pipe; | |
b1f6d01c DL |
1493 | |
1494 | next_odm_pipe->pipe_idx = pipe_idx; | |
1495 | next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; | |
1496 | next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; | |
1497 | next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; | |
1498 | next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; | |
1499 | next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; | |
1500 | next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; | |
b1f6d01c | 1501 | next_odm_pipe->stream_res.dsc = NULL; |
b1f6d01c | 1502 | if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) { |
b1f6d01c DL |
1503 | next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe; |
1504 | next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe; | |
1505 | } | |
2e7b43e6 DL |
1506 | if (prev_odm_pipe->top_pipe && prev_odm_pipe->top_pipe->next_odm_pipe) { |
1507 | prev_odm_pipe->top_pipe->next_odm_pipe->bottom_pipe = next_odm_pipe; | |
1508 | next_odm_pipe->top_pipe = prev_odm_pipe->top_pipe->next_odm_pipe; | |
1509 | } | |
1510 | if (prev_odm_pipe->bottom_pipe && prev_odm_pipe->bottom_pipe->next_odm_pipe) { | |
1511 | prev_odm_pipe->bottom_pipe->next_odm_pipe->top_pipe = next_odm_pipe; | |
1512 | next_odm_pipe->bottom_pipe = prev_odm_pipe->bottom_pipe->next_odm_pipe; | |
1513 | } | |
b1f6d01c DL |
1514 | prev_odm_pipe->next_odm_pipe = next_odm_pipe; |
1515 | next_odm_pipe->prev_odm_pipe = prev_odm_pipe; | |
b1f6d01c DL |
1516 | |
1517 | if (prev_odm_pipe->plane_state) { | |
c0358809 DL |
1518 | struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data; |
1519 | int new_width; | |
1520 | ||
b1f6d01c DL |
1521 | /* HACTIVE halved for odm combine */ |
1522 | sd->h_active /= 2; | |
b1f6d01c DL |
1523 | /* Calculate new vp and recout for left pipe */ |
1524 | /* Need at least 16 pixels width per side */ | |
1525 | if (sd->recout.x + 16 >= sd->h_active) | |
1526 | return false; | |
1527 | new_width = sd->h_active - sd->recout.x; | |
1528 | sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( | |
1529 | sd->ratios.horz, sd->recout.width - new_width)); | |
1530 | sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( | |
1531 | sd->ratios.horz_c, sd->recout.width - new_width)); | |
1532 | sd->recout.width = new_width; | |
1533 | ||
1534 | /* Calculate new vp and recout for right pipe */ | |
1535 | sd = &next_odm_pipe->plane_res.scl_data; | |
c0358809 DL |
1536 | /* HACTIVE halved for odm combine */ |
1537 | sd->h_active /= 2; | |
b1f6d01c DL |
1538 | /* Need at least 16 pixels width per side */ |
1539 | if (new_width <= 16) | |
1540 | return false; | |
c0358809 | 1541 | new_width = sd->recout.width + sd->recout.x - sd->h_active; |
b1f6d01c DL |
1542 | sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( |
1543 | sd->ratios.horz, sd->recout.width - new_width)); | |
1544 | sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( | |
1545 | sd->ratios.horz_c, sd->recout.width - new_width)); | |
1546 | sd->recout.width = new_width; | |
1547 | sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int( | |
1548 | sd->ratios.horz, sd->h_active - sd->recout.x)); | |
1549 | sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int( | |
1550 | sd->ratios.horz_c, sd->h_active - sd->recout.x)); | |
1551 | sd->recout.x = 0; | |
1552 | } | |
2e7b43e6 DL |
1553 | if (!next_odm_pipe->top_pipe) |
1554 | next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx]; | |
1555 | else | |
1556 | next_odm_pipe->stream_res.opp = next_odm_pipe->top_pipe->stream_res.opp; | |
73d48f08 | 1557 | if (next_odm_pipe->stream->timing.flags.DSC == 1 && !next_odm_pipe->top_pipe) { |
570bc18c | 1558 | dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx); |
b1f6d01c DL |
1559 | ASSERT(next_odm_pipe->stream_res.dsc); |
1560 | if (next_odm_pipe->stream_res.dsc == NULL) | |
1561 | return false; | |
1562 | } | |
b1f6d01c DL |
1563 | |
1564 | return true; | |
1565 | } | |
1566 | ||
65d68369 | 1567 | void dcn20_split_stream_for_mpc( |
7ed4e635 HW |
1568 | struct resource_context *res_ctx, |
1569 | const struct resource_pool *pool, | |
1570 | struct pipe_ctx *primary_pipe, | |
b1f6d01c | 1571 | struct pipe_ctx *secondary_pipe) |
7ed4e635 HW |
1572 | { |
1573 | int pipe_idx = secondary_pipe->pipe_idx; | |
7ed4e635 | 1574 | struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe; |
7ed4e635 HW |
1575 | |
1576 | *secondary_pipe = *primary_pipe; | |
1577 | secondary_pipe->bottom_pipe = sec_bot_pipe; | |
1578 | ||
1579 | secondary_pipe->pipe_idx = pipe_idx; | |
1580 | secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; | |
1581 | secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; | |
1582 | secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx]; | |
1583 | secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; | |
1584 | secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; | |
1585 | secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; | |
c92b4c46 | 1586 | secondary_pipe->stream_res.dsc = NULL; |
7ed4e635 HW |
1587 | if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) { |
1588 | ASSERT(!secondary_pipe->bottom_pipe); | |
1589 | secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; | |
1590 | secondary_pipe->bottom_pipe->top_pipe = secondary_pipe; | |
1591 | } | |
1592 | primary_pipe->bottom_pipe = secondary_pipe; | |
1593 | secondary_pipe->top_pipe = primary_pipe; | |
1594 | ||
b1f6d01c | 1595 | ASSERT(primary_pipe->plane_state); |
7ed4e635 HW |
1596 | } |
1597 | ||
7ed4e635 HW |
1598 | unsigned int dcn20_calc_max_scaled_time( |
1599 | unsigned int time_per_pixel, | |
1600 | enum mmhubbub_wbif_mode mode, | |
1601 | unsigned int urgent_watermark) | |
1602 | { | |
1603 | unsigned int time_per_byte = 0; | |
1604 | unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */ | |
1605 | unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */ | |
1606 | unsigned int small_free_entry, max_free_entry; | |
1607 | unsigned int buf_lh_capability; | |
1608 | unsigned int max_scaled_time; | |
1609 | ||
1610 | if (mode == PACKED_444) /* packed mode */ | |
1611 | time_per_byte = time_per_pixel/4; | |
1612 | else if (mode == PLANAR_420_8BPC) | |
1613 | time_per_byte = time_per_pixel; | |
1614 | else if (mode == PLANAR_420_10BPC) /* p010 */ | |
1615 | time_per_byte = time_per_pixel * 819/1024; | |
1616 | ||
1617 | if (time_per_byte == 0) | |
1618 | time_per_byte = 1; | |
1619 | ||
1620 | small_free_entry = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry; | |
1621 | max_free_entry = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry; | |
1622 | buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */ | |
1623 | max_scaled_time = buf_lh_capability - urgent_watermark; | |
1624 | return max_scaled_time; | |
1625 | } | |
1626 | ||
1627 | void dcn20_set_mcif_arb_params( | |
1628 | struct dc *dc, | |
1629 | struct dc_state *context, | |
1630 | display_e2e_pipe_params_st *pipes, | |
1631 | int pipe_cnt) | |
1632 | { | |
1633 | enum mmhubbub_wbif_mode wbif_mode; | |
1634 | struct mcif_arb_params *wb_arb_params; | |
cf689e86 | 1635 | int i, j, dwb_pipe; |
7ed4e635 HW |
1636 | |
1637 | /* Writeback MCIF_WB arbitration parameters */ | |
1638 | dwb_pipe = 0; | |
1639 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |
1640 | ||
1641 | if (!context->res_ctx.pipe_ctx[i].stream) | |
1642 | continue; | |
1643 | ||
1644 | for (j = 0; j < MAX_DWB_PIPES; j++) { | |
1645 | if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false) | |
1646 | continue; | |
1647 | ||
1648 | //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params; | |
1649 | wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe]; | |
1650 | ||
1651 | if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) { | |
1652 | if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC) | |
1653 | wbif_mode = PLANAR_420_8BPC; | |
1654 | else | |
1655 | wbif_mode = PLANAR_420_10BPC; | |
1656 | } else | |
1657 | wbif_mode = PACKED_444; | |
1658 | ||
cf689e86 MW |
1659 | DC_FP_START(); |
1660 | dcn20_fpu_set_wb_arb_params(wb_arb_params, context, pipes, pipe_cnt, i); | |
1661 | DC_FP_END(); | |
1662 | ||
7ed4e635 HW |
1663 | wb_arb_params->slice_lines = 32; |
1664 | wb_arb_params->arbitration_slice = 2; | |
1665 | wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel, | |
1666 | wbif_mode, | |
1667 | wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */ | |
1668 | ||
1669 | dwb_pipe++; | |
1670 | ||
1671 | if (dwb_pipe >= MAX_DWB_PIPES) | |
1672 | return; | |
1673 | } | |
1674 | if (dwb_pipe >= MAX_DWB_PIPES) | |
1675 | return; | |
1676 | } | |
1677 | } | |
1678 | ||
b6bfba6c | 1679 | bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) |
0ba37b20 DL |
1680 | { |
1681 | int i; | |
1682 | ||
1683 | /* Validate DSC config, dsc count validation is already done */ | |
1684 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |
1685 | struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; | |
1686 | struct dc_stream_state *stream = pipe_ctx->stream; | |
1687 | struct dsc_config dsc_cfg; | |
b1f6d01c DL |
1688 | struct pipe_ctx *odm_pipe; |
1689 | int opp_cnt = 1; | |
1690 | ||
1691 | for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) | |
1692 | opp_cnt++; | |
0ba37b20 DL |
1693 | |
1694 | /* Only need to validate top pipe */ | |
b1f6d01c | 1695 | if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC) |
0ba37b20 DL |
1696 | continue; |
1697 | ||
b1f6d01c DL |
1698 | dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left |
1699 | + stream->timing.h_border_right) / opp_cnt; | |
0ba37b20 DL |
1700 | dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top |
1701 | + stream->timing.v_border_bottom; | |
0ba37b20 DL |
1702 | dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; |
1703 | dsc_cfg.color_depth = stream->timing.display_color_depth; | |
df8e34ac | 1704 | dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; |
0ba37b20 | 1705 | dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; |
b1f6d01c | 1706 | dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; |
0ba37b20 DL |
1707 | |
1708 | if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg)) | |
1709 | return false; | |
1710 | } | |
1711 | return true; | |
1712 | } | |
0ba37b20 | 1713 | |
b6bfba6c | 1714 | struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, |
c681491a JL |
1715 | struct resource_context *res_ctx, |
1716 | const struct resource_pool *pool, | |
1717 | const struct pipe_ctx *primary_pipe) | |
1718 | { | |
1719 | struct pipe_ctx *secondary_pipe = NULL; | |
1720 | ||
1721 | if (dc && primary_pipe) { | |
1722 | int j; | |
1723 | int preferred_pipe_idx = 0; | |
1724 | ||
1725 | /* first check the prev dc state: | |
1726 | * if this primary pipe has a bottom pipe in prev. state | |
1727 | * and if the bottom pipe is still available (which it should be), | |
1728 | * pick that pipe as secondary | |
7a214cd8 | 1729 | * Same logic applies for ODM pipes |
c681491a | 1730 | */ |
324b1fcb | 1731 | if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) { |
1732 | preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx; | |
c681491a JL |
1733 | if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { |
1734 | secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; | |
1735 | secondary_pipe->pipe_idx = preferred_pipe_idx; | |
1736 | } | |
7a214cd8 SL |
1737 | } |
1738 | if (secondary_pipe == NULL && | |
324b1fcb | 1739 | dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) { |
1740 | preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx; | |
b1f6d01c DL |
1741 | if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { |
1742 | secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; | |
1743 | secondary_pipe->pipe_idx = preferred_pipe_idx; | |
1744 | } | |
c681491a JL |
1745 | } |
1746 | ||
1747 | /* | |
1748 | * if this primary pipe does not have a bottom pipe in prev. state | |
1749 | * start backward and find a pipe that did not used to be a bottom pipe in | |
1750 | * prev. dc state. This way we make sure we keep the same assignment as | |
1751 | * last state and will not have to reprogram every pipe | |
1752 | */ | |
1753 | if (secondary_pipe == NULL) { | |
1754 | for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { | |
8b8eda01 DL |
1755 | if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL |
1756 | && dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) { | |
c681491a JL |
1757 | preferred_pipe_idx = j; |
1758 | ||
1759 | if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { | |
1760 | secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; | |
1761 | secondary_pipe->pipe_idx = preferred_pipe_idx; | |
1762 | break; | |
1763 | } | |
1764 | } | |
1765 | } | |
1766 | } | |
1767 | /* | |
1768 | * We should never hit this assert unless assignments are shuffled around | |
1769 | * if this happens we will prob. hit a vsync tdr | |
1770 | */ | |
1771 | ASSERT(secondary_pipe); | |
1772 | /* | |
1773 | * search backwards for the second pipe to keep pipe | |
1774 | * assignment more consistent | |
1775 | */ | |
1776 | if (secondary_pipe == NULL) { | |
1777 | for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { | |
1778 | preferred_pipe_idx = j; | |
1779 | ||
1780 | if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { | |
1781 | secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; | |
1782 | secondary_pipe->pipe_idx = preferred_pipe_idx; | |
1783 | break; | |
1784 | } | |
1785 | } | |
1786 | } | |
1787 | } | |
1788 | ||
1789 | return secondary_pipe; | |
1790 | } | |
1791 | ||
ea817dd5 | 1792 | void dcn20_merge_pipes_for_validate( |
6de20237 | 1793 | struct dc *dc, |
b6bfba6c | 1794 | struct dc_state *context) |
7ed4e635 | 1795 | { |
b6bfba6c | 1796 | int i; |
7ed4e635 | 1797 | |
b1f6d01c DL |
1798 | /* merge previously split odm pipes since mode support needs to make the decision */ |
1799 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |
1800 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |
1801 | struct pipe_ctx *odm_pipe = pipe->next_odm_pipe; | |
1802 | ||
1803 | if (pipe->prev_odm_pipe) | |
1804 | continue; | |
1805 | ||
1806 | pipe->next_odm_pipe = NULL; | |
1807 | while (odm_pipe) { | |
1808 | struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe; | |
1809 | ||
1810 | odm_pipe->plane_state = NULL; | |
1811 | odm_pipe->stream = NULL; | |
1812 | odm_pipe->top_pipe = NULL; | |
1813 | odm_pipe->bottom_pipe = NULL; | |
1814 | odm_pipe->prev_odm_pipe = NULL; | |
1815 | odm_pipe->next_odm_pipe = NULL; | |
b1f6d01c | 1816 | if (odm_pipe->stream_res.dsc) |
7287a675 | 1817 | dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc); |
b1f6d01c DL |
1818 | /* Clear plane_res and stream_res */ |
1819 | memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res)); | |
1820 | memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res)); | |
1821 | odm_pipe = next_odm_pipe; | |
1822 | } | |
1823 | if (pipe->plane_state) | |
1824 | resource_build_scaling_params(pipe); | |
1825 | } | |
1826 | ||
1827 | /* merge previously mpc split pipes since mode support needs to make the decision */ | |
7ed4e635 HW |
1828 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
1829 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |
1830 | struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; | |
1831 | ||
1832 | if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) | |
1833 | continue; | |
1834 | ||
7ed4e635 HW |
1835 | pipe->bottom_pipe = hsplit_pipe->bottom_pipe; |
1836 | if (hsplit_pipe->bottom_pipe) | |
1837 | hsplit_pipe->bottom_pipe->top_pipe = pipe; | |
1838 | hsplit_pipe->plane_state = NULL; | |
1839 | hsplit_pipe->stream = NULL; | |
1840 | hsplit_pipe->top_pipe = NULL; | |
1841 | hsplit_pipe->bottom_pipe = NULL; | |
b1f6d01c | 1842 | |
7ed4e635 HW |
1843 | /* Clear plane_res and stream_res */ |
1844 | memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res)); | |
1845 | memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res)); | |
1846 | if (pipe->plane_state) | |
1847 | resource_build_scaling_params(pipe); | |
1848 | } | |
b6bfba6c | 1849 | } |
7ed4e635 | 1850 | |
b6bfba6c DL |
1851 | int dcn20_validate_apply_pipe_split_flags( |
1852 | struct dc *dc, | |
1853 | struct dc_state *context, | |
1854 | int vlevel, | |
65d68369 | 1855 | int *split, |
7287a675 | 1856 | bool *merge) |
b6bfba6c | 1857 | { |
b745ecdb | 1858 | int i, pipe_idx, vlevel_split; |
cd3e05a7 | 1859 | int plane_count = 0; |
b6bfba6c | 1860 | bool force_split = false; |
cd3e05a7 | 1861 | bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID; |
570bc18c DL |
1862 | struct vba_vars_st *v = &context->bw_ctx.dml.vba; |
1863 | int max_mpc_comb = v->maxMpcComb; | |
7ed4e635 | 1864 | |
cd3e05a7 DL |
1865 | if (context->stream_count > 1) { |
1866 | if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP) | |
1867 | avoid_split = true; | |
1868 | } else if (dc->debug.force_single_disp_pipe_split) | |
1869 | force_split = true; | |
1870 | ||
7ed4e635 HW |
1871 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
1872 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |
7ed4e635 | 1873 | |
b6dbb8ff NK |
1874 | /** |
1875 | * Workaround for avoiding pipe-split in cases where we'd split | |
1876 | * planes that are too small, resulting in splits that aren't | |
1877 | * valid for the scaler. | |
1878 | */ | |
1879 | if (pipe->plane_state && | |
1880 | (pipe->plane_state->dst_rect.width <= 16 || | |
1881 | pipe->plane_state->dst_rect.height <= 16 || | |
1882 | pipe->plane_state->src_rect.width <= 16 || | |
1883 | pipe->plane_state->src_rect.height <= 16)) | |
1884 | avoid_split = true; | |
1885 | ||
1886 | /* TODO: fix dc bugs and remove this split threshold thing */ | |
cd3e05a7 DL |
1887 | if (pipe->stream && !pipe->prev_odm_pipe && |
1888 | (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state)) | |
1889 | ++plane_count; | |
7ed4e635 | 1890 | } |
cd3e05a7 | 1891 | if (plane_count > dc->res_pool->pipe_count / 2) |
7ed4e635 HW |
1892 | avoid_split = true; |
1893 | ||
a0a85ac4 DZ |
1894 | /* W/A: Mode timing with borders may not work well with pipe split, avoid for this corner case */ |
1895 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |
1896 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |
1897 | struct dc_crtc_timing timing; | |
1898 | ||
1899 | if (!pipe->stream) | |
1900 | continue; | |
1901 | else { | |
1902 | timing = pipe->stream->timing; | |
1903 | if (timing.h_border_left + timing.h_border_right | |
1904 | + timing.v_border_top + timing.v_border_bottom > 0) { | |
1905 | avoid_split = true; | |
1906 | break; | |
1907 | } | |
1908 | } | |
1909 | } | |
1910 | ||
b745ecdb | 1911 | /* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */ |
b6bfba6c DL |
1912 | if (avoid_split) { |
1913 | for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { | |
1914 | if (!context->res_ctx.pipe_ctx[i].stream) | |
1915 | continue; | |
1916 | ||
b745ecdb | 1917 | for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) |
570bc18c DL |
1918 | if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 && |
1919 | v->ModeSupport[vlevel][0]) | |
b6bfba6c DL |
1920 | break; |
1921 | /* Impossible to not split this pipe */ | |
b745ecdb DL |
1922 | if (vlevel > context->bw_ctx.dml.soc.num_states) |
1923 | vlevel = vlevel_split; | |
1dfedb39 SL |
1924 | else |
1925 | max_mpc_comb = 0; | |
b6bfba6c DL |
1926 | pipe_idx++; |
1927 | } | |
570bc18c | 1928 | v->maxMpcComb = max_mpc_comb; |
b6bfba6c DL |
1929 | } |
1930 | ||
b745ecdb | 1931 | /* Split loop sets which pipe should be split based on dml outputs and dc flags */ |
7ed4e635 | 1932 | for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { |
b6bfba6c | 1933 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; |
570bc18c DL |
1934 | int pipe_plane = v->pipe_plane[pipe_idx]; |
1935 | bool split4mpc = context->stream_count == 1 && plane_count == 1 | |
1936 | && dc->config.enable_4to1MPC && dc->res_pool->pipe_count >= 4; | |
b6bfba6c | 1937 | |
7ed4e635 HW |
1938 | if (!context->res_ctx.pipe_ctx[i].stream) |
1939 | continue; | |
b6bfba6c | 1940 | |
4d765d31 DL |
1941 | if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4) |
1942 | split[i] = 4; | |
1943 | else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2) | |
65d68369 | 1944 | split[i] = 2; |
4d765d31 | 1945 | |
b6bfba6c DL |
1946 | if ((pipe->stream->view_format == |
1947 | VIEW_3D_FORMAT_SIDE_BY_SIDE || | |
1948 | pipe->stream->view_format == | |
1949 | VIEW_3D_FORMAT_TOP_AND_BOTTOM) && | |
1950 | (pipe->stream->timing.timing_3d_format == | |
1951 | TIMING_3D_FORMAT_TOP_AND_BOTTOM || | |
1952 | pipe->stream->timing.timing_3d_format == | |
1953 | TIMING_3D_FORMAT_SIDE_BY_SIDE)) | |
65d68369 | 1954 | split[i] = 2; |
b6bfba6c | 1955 | if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) { |
65d68369 | 1956 | split[i] = 2; |
570bc18c | 1957 | v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1; |
b6bfba6c | 1958 | } |
5dba4991 BL |
1959 | if (dc->debug.force_odm_combine_4to1 & (1 << pipe->stream_res.tg->inst)) { |
1960 | split[i] = 4; | |
1961 | v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1; | |
1962 | } | |
5e908012 CP |
1963 | /*420 format workaround*/ |
1964 | if (pipe->stream->timing.h_addressable > 7680 && | |
1965 | pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { | |
1966 | split[i] = 4; | |
1967 | } | |
570bc18c DL |
1968 | v->ODMCombineEnabled[pipe_plane] = |
1969 | v->ODMCombineEnablePerState[vlevel][pipe_plane]; | |
1970 | ||
1971 | if (v->ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) { | |
1972 | if (get_num_mpc_splits(pipe) == 1) { | |
1973 | /*If need split for mpc but 2 way split already*/ | |
1974 | if (split[i] == 4) | |
1975 | split[i] = 2; /* 2 -> 4 MPC */ | |
1976 | else if (split[i] == 2) | |
1977 | split[i] = 0; /* 2 -> 2 MPC */ | |
1978 | else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) | |
1979 | merge[i] = true; /* 2 -> 1 MPC */ | |
1980 | } else if (get_num_mpc_splits(pipe) == 3) { | |
1981 | /*If need split for mpc but 4 way split already*/ | |
1982 | if (split[i] == 2 && ((pipe->top_pipe && !pipe->top_pipe->top_pipe) | |
1983 | || !pipe->bottom_pipe)) { | |
1984 | merge[i] = true; /* 4 -> 2 MPC */ | |
1985 | } else if (split[i] == 0 && pipe->top_pipe && | |
1986 | pipe->top_pipe->plane_state == pipe->plane_state) | |
1987 | merge[i] = true; /* 4 -> 1 MPC */ | |
65d68369 | 1988 | split[i] = 0; |
570bc18c DL |
1989 | } else if (get_num_odm_splits(pipe)) { |
1990 | /* ODM -> MPC transition */ | |
7287a675 | 1991 | if (pipe->prev_odm_pipe) { |
570bc18c DL |
1992 | split[i] = 0; |
1993 | merge[i] = true; | |
7287a675 DL |
1994 | } |
1995 | } | |
570bc18c DL |
1996 | } else { |
1997 | if (get_num_odm_splits(pipe) == 1) { | |
1998 | /*If need split for odm but 2 way split already*/ | |
1999 | if (split[i] == 4) | |
2000 | split[i] = 2; /* 2 -> 4 ODM */ | |
2001 | else if (split[i] == 2) | |
2002 | split[i] = 0; /* 2 -> 2 ODM */ | |
2003 | else if (pipe->prev_odm_pipe) { | |
2004 | ASSERT(0); /* NOT expected yet */ | |
2005 | merge[i] = true; /* exit ODM */ | |
2006 | } | |
2007 | } else if (get_num_odm_splits(pipe) == 3) { | |
2008 | /*If need split for odm but 4 way split already*/ | |
2009 | if (split[i] == 2 && ((pipe->prev_odm_pipe && !pipe->prev_odm_pipe->prev_odm_pipe) | |
2010 | || !pipe->next_odm_pipe)) { | |
570bc18c DL |
2011 | merge[i] = true; /* 4 -> 2 ODM */ |
2012 | } else if (split[i] == 0 && pipe->prev_odm_pipe) { | |
2013 | ASSERT(0); /* NOT expected yet */ | |
2014 | merge[i] = true; /* exit ODM */ | |
2015 | } | |
65d68369 | 2016 | split[i] = 0; |
570bc18c DL |
2017 | } else if (get_num_mpc_splits(pipe)) { |
2018 | /* MPC -> ODM transition */ | |
2019 | ASSERT(0); /* NOT expected yet */ | |
2020 | if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { | |
2021 | split[i] = 0; | |
2022 | merge[i] = true; | |
2023 | } | |
65d68369 | 2024 | } |
7287a675 DL |
2025 | } |
2026 | ||
b6bfba6c | 2027 | /* Adjust dppclk when split is forced, do not bother with dispclk */ |
cf689e86 MW |
2028 | if (split[i] != 0 && v->NoOfDPP[vlevel][max_mpc_comb][pipe_idx] == 1) { |
2029 | DC_FP_START(); | |
2030 | dcn20_fpu_adjust_dppclk(v, vlevel, max_mpc_comb, pipe_idx, false); | |
2031 | DC_FP_END(); | |
2032 | } | |
7ed4e635 HW |
2033 | pipe_idx++; |
2034 | } | |
2035 | ||
b6bfba6c DL |
2036 | return vlevel; |
2037 | } | |
2038 | ||
2039 | bool dcn20_fast_validate_bw( | |
2040 | struct dc *dc, | |
2041 | struct dc_state *context, | |
2042 | display_e2e_pipe_params_st *pipes, | |
2043 | int *pipe_cnt_out, | |
2044 | int *pipe_split_from, | |
fa896813 IZ |
2045 | int *vlevel_out, |
2046 | bool fast_validate) | |
b6bfba6c DL |
2047 | { |
2048 | bool out = false; | |
65d68369 | 2049 | int split[MAX_PIPES] = { 0 }; |
b6bfba6c DL |
2050 | int pipe_cnt, i, pipe_idx, vlevel; |
2051 | ||
2052 | ASSERT(pipes); | |
2053 | if (!pipes) | |
2054 | return false; | |
2055 | ||
2056 | dcn20_merge_pipes_for_validate(dc, context); | |
2057 | ||
cf689e86 | 2058 | DC_FP_START(); |
fa896813 | 2059 | pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); |
cf689e86 | 2060 | DC_FP_END(); |
b6bfba6c DL |
2061 | |
2062 | *pipe_cnt_out = pipe_cnt; | |
2063 | ||
2064 | if (!pipe_cnt) { | |
2065 | out = true; | |
2066 | goto validate_out; | |
2067 | } | |
2068 | ||
2069 | vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); | |
2070 | ||
2071 | if (vlevel > context->bw_ctx.dml.soc.num_states) | |
2072 | goto validate_fail; | |
2073 | ||
7287a675 | 2074 | vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL); |
b6bfba6c DL |
2075 | |
2076 | /*initialize pipe_just_split_from to invalid idx*/ | |
2077 | for (i = 0; i < MAX_PIPES; i++) | |
2078 | pipe_split_from[i] = -1; | |
2079 | ||
7ed4e635 HW |
2080 | for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { |
2081 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |
2082 | struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; | |
7ed4e635 HW |
2083 | |
2084 | if (!pipe->stream || pipe_split_from[i] >= 0) | |
2085 | continue; | |
2086 | ||
2087 | pipe_idx++; | |
2088 | ||
7ed4e635 | 2089 | if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { |
c681491a | 2090 | hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); |
7ed4e635 | 2091 | ASSERT(hsplit_pipe); |
b1f6d01c | 2092 | if (!dcn20_split_stream_for_odm( |
14e49bb3 | 2093 | dc, &context->res_ctx, |
b1f6d01c | 2094 | pipe, hsplit_pipe)) |
7ed4e635 HW |
2095 | goto validate_fail; |
2096 | pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; | |
2097 | dcn20_build_mapped_resource(dc, context, pipe->stream); | |
2098 | } | |
2099 | ||
2100 | if (!pipe->plane_state) | |
2101 | continue; | |
2102 | /* Skip 2nd half of already split pipe */ | |
2103 | if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state) | |
2104 | continue; | |
2105 | ||
02ce5a79 DL |
2106 | /* We do not support mpo + odm at the moment */ |
2107 | if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state | |
2108 | && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) | |
2109 | goto validate_fail; | |
2110 | ||
65d68369 | 2111 | if (split[i] == 2) { |
7ed4e635 HW |
2112 | if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) { |
2113 | /* pipe not split previously needs split */ | |
c681491a | 2114 | hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); |
b6bfba6c | 2115 | ASSERT(hsplit_pipe); |
ff86391e | 2116 | if (!hsplit_pipe) { |
cf689e86 MW |
2117 | DC_FP_START(); |
2118 | dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true); | |
2119 | DC_FP_END(); | |
7ed4e635 | 2120 | continue; |
ff86391e | 2121 | } |
b1f6d01c DL |
2122 | if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { |
2123 | if (!dcn20_split_stream_for_odm( | |
14e49bb3 | 2124 | dc, &context->res_ctx, |
b1f6d01c DL |
2125 | pipe, hsplit_pipe)) |
2126 | goto validate_fail; | |
387596ef | 2127 | dcn20_build_mapped_resource(dc, context, pipe->stream); |
65d68369 IZ |
2128 | } else { |
2129 | dcn20_split_stream_for_mpc( | |
b8a8d34b | 2130 | &context->res_ctx, dc->res_pool, |
65d68369 | 2131 | pipe, hsplit_pipe); |
65f9ace4 SL |
2132 | resource_build_scaling_params(pipe); |
2133 | resource_build_scaling_params(hsplit_pipe); | |
65d68369 | 2134 | } |
7ed4e635 HW |
2135 | pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; |
2136 | } | |
02ce5a79 | 2137 | } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { |
7ed4e635 HW |
2138 | /* merge should already have been done */ |
2139 | ASSERT(0); | |
2140 | } | |
2141 | } | |
0ba37b20 | 2142 | /* Actual dsc count per stream dsc validation*/ |
c84ad0d6 | 2143 | if (!dcn20_validate_dsc(dc, context)) { |
0ba37b20 DL |
2144 | context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = |
2145 | DML_FAIL_DSC_VALIDATION_FAILURE; | |
2146 | goto validate_fail; | |
2147 | } | |
7ed4e635 | 2148 | |
6de20237 | 2149 | *vlevel_out = vlevel; |
42351c66 | 2150 | |
6de20237 EY |
2151 | out = true; |
2152 | goto validate_out; | |
2153 | ||
2154 | validate_fail: | |
2155 | out = false; | |
2156 | ||
2157 | validate_out: | |
2158 | return out; | |
2159 | } | |
2160 | ||
8b91fd8b DK |
2161 | bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, |
2162 | bool fast_validate) | |
2163 | { | |
41401ac6 | 2164 | bool voltage_supported; |
8b91fd8b DK |
2165 | DC_FP_START(); |
2166 | voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate); | |
7a8a3430 | 2167 | DC_FP_END(); |
057fc695 JL |
2168 | return voltage_supported; |
2169 | } | |
2170 | ||
7ed4e635 HW |
2171 | struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer( |
2172 | struct dc_state *state, | |
2173 | const struct resource_pool *pool, | |
2174 | struct dc_stream_state *stream) | |
2175 | { | |
2176 | struct resource_context *res_ctx = &state->res_ctx; | |
2177 | struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); | |
2178 | struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe); | |
2179 | ||
2180 | if (!head_pipe) | |
2181 | ASSERT(0); | |
2182 | ||
2183 | if (!idle_pipe) | |
7a17c8ce | 2184 | return NULL; |
7ed4e635 HW |
2185 | |
2186 | idle_pipe->stream = head_pipe->stream; | |
2187 | idle_pipe->stream_res.tg = head_pipe->stream_res.tg; | |
2188 | idle_pipe->stream_res.opp = head_pipe->stream_res.opp; | |
2189 | ||
2190 | idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; | |
2191 | idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; | |
2192 | idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; | |
2193 | idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; | |
2194 | ||
2195 | return idle_pipe; | |
2196 | } | |
2197 | ||
2198 | bool dcn20_get_dcc_compression_cap(const struct dc *dc, | |
2199 | const struct dc_dcc_surface_param *input, | |
2200 | struct dc_surface_dcc_cap *output) | |
2201 | { | |
2202 | return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( | |
2203 | dc->res_pool->hubbub, | |
2204 | input, | |
2205 | output); | |
2206 | } | |
2207 | ||
2208 | static void dcn20_destroy_resource_pool(struct resource_pool **pool) | |
2209 | { | |
2210 | struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool); | |
2211 | ||
d9e32672 | 2212 | dcn20_resource_destruct(dcn20_pool); |
7ed4e635 HW |
2213 | kfree(dcn20_pool); |
2214 | *pool = NULL; | |
2215 | } | |
2216 | ||
2217 | ||
2218 | static struct dc_cap_funcs cap_funcs = { | |
2219 | .get_dcc_compression_cap = dcn20_get_dcc_compression_cap | |
2220 | }; | |
2221 | ||
2222 | ||
8d8c82b6 | 2223 | enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state) |
7ed4e635 | 2224 | { |
7ed4e635 HW |
2225 | enum surface_pixel_format surf_pix_format = plane_state->format; |
2226 | unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); | |
2227 | ||
2228 | enum swizzle_mode_values swizzle = DC_SW_LINEAR; | |
2229 | ||
2230 | if (bpp == 64) | |
2231 | swizzle = DC_SW_64KB_D; | |
2232 | else | |
2233 | swizzle = DC_SW_64KB_S; | |
2234 | ||
2235 | plane_state->tiling_info.gfx9.swizzle = swizzle; | |
b1c3b7f1 | 2236 | return DC_OK; |
7ed4e635 HW |
2237 | } |
2238 | ||
25457a1f | 2239 | static const struct resource_funcs dcn20_res_pool_funcs = { |
7ed4e635 HW |
2240 | .destroy = dcn20_destroy_resource_pool, |
2241 | .link_enc_create = dcn20_link_encoder_create, | |
d4caa72e | 2242 | .panel_cntl_create = dcn20_panel_cntl_create, |
7ed4e635 | 2243 | .validate_bandwidth = dcn20_validate_bandwidth, |
7ed4e635 HW |
2244 | .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, |
2245 | .add_stream_to_ctx = dcn20_add_stream_to_ctx, | |
b4f71c8c | 2246 | .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, |
7ed4e635 HW |
2247 | .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, |
2248 | .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, | |
8d8c82b6 | 2249 | .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, |
c9ae6e16 | 2250 | .set_mcif_arb_params = dcn20_set_mcif_arb_params, |
b6bfba6c | 2251 | .populate_dml_pipes = dcn20_populate_dml_pipes_from_context, |
278141f5 | 2252 | .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link |
7ed4e635 HW |
2253 | }; |
2254 | ||
bb21290f CL |
2255 | bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) |
2256 | { | |
2257 | int i; | |
2258 | uint32_t pipe_count = pool->res_cap->num_dwb; | |
2259 | ||
bb21290f CL |
2260 | for (i = 0; i < pipe_count; i++) { |
2261 | struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc), | |
2262 | GFP_KERNEL); | |
2263 | ||
2264 | if (!dwbc20) { | |
2265 | dm_error("DC: failed to create dwbc20!\n"); | |
2266 | return false; | |
2267 | } | |
2268 | dcn20_dwbc_construct(dwbc20, ctx, | |
2269 | &dwbc20_regs[i], | |
2270 | &dwbc20_shift, | |
2271 | &dwbc20_mask, | |
2272 | i); | |
2273 | pool->dwbc[i] = &dwbc20->base; | |
2274 | } | |
2275 | return true; | |
2276 | } | |
2277 | ||
2278 | bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) | |
2279 | { | |
2280 | int i; | |
2281 | uint32_t pipe_count = pool->res_cap->num_dwb; | |
2282 | ||
2283 | ASSERT(pipe_count > 0); | |
2284 | ||
2285 | for (i = 0; i < pipe_count; i++) { | |
2286 | struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub), | |
2287 | GFP_KERNEL); | |
2288 | ||
2289 | if (!mcif_wb20) { | |
2290 | dm_error("DC: failed to create mcif_wb20!\n"); | |
2291 | return false; | |
2292 | } | |
2293 | ||
2294 | dcn20_mmhubbub_construct(mcif_wb20, ctx, | |
2295 | &mcif_wb20_regs[i], | |
2296 | &mcif_wb20_shift, | |
2297 | &mcif_wb20_mask, | |
2298 | i); | |
2299 | ||
2300 | pool->mcif_wb[i] = &mcif_wb20->base; | |
2301 | } | |
2302 | return true; | |
2303 | } | |
2304 | ||
44e149bb | 2305 | static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx) |
7ed4e635 | 2306 | { |
3bb11050 | 2307 | struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_ATOMIC); |
7ed4e635 HW |
2308 | |
2309 | if (!pp_smu) | |
2310 | return pp_smu; | |
2311 | ||
2312 | dm_pp_get_funcs(ctx, pp_smu); | |
2313 | ||
2314 | if (pp_smu->ctx.ver != PP_SMU_VER_NV) | |
2315 | pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); | |
2316 | ||
2317 | return pp_smu; | |
2318 | } | |
2319 | ||
44e149bb | 2320 | static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu) |
7ed4e635 HW |
2321 | { |
2322 | if (pp_smu && *pp_smu) { | |
2323 | kfree(*pp_smu); | |
2324 | *pp_smu = NULL; | |
2325 | } | |
2326 | } | |
2327 | ||
675a9e38 LL |
2328 | static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb( |
2329 | uint32_t hw_internal_rev) | |
2330 | { | |
e1ab4a91 ML |
2331 | if (ASICREV_IS_NAVI14_M(hw_internal_rev)) |
2332 | return &dcn2_0_nv14_soc; | |
2333 | ||
675a9e38 LL |
2334 | if (ASICREV_IS_NAVI12_P(hw_internal_rev)) |
2335 | return &dcn2_0_nv12_soc; | |
2336 | ||
2337 | return &dcn2_0_soc; | |
2338 | } | |
2339 | ||
2340 | static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params( | |
2341 | uint32_t hw_internal_rev) | |
2342 | { | |
72b741af Z |
2343 | /* NV14 */ |
2344 | if (ASICREV_IS_NAVI14_M(hw_internal_rev)) | |
2345 | return &dcn2_0_nv14_ip; | |
2346 | ||
675a9e38 LL |
2347 | /* NV12 and NV10 */ |
2348 | return &dcn2_0_ip; | |
2349 | } | |
2350 | ||
2351 | static enum dml_project get_dml_project_version(uint32_t hw_internal_rev) | |
2352 | { | |
2353 | return DML_PROJECT_NAVI10v2; | |
2354 | } | |
2355 | ||
7ed4e635 HW |
2356 | static bool init_soc_bounding_box(struct dc *dc, |
2357 | struct dcn20_resource_pool *pool) | |
2358 | { | |
675a9e38 LL |
2359 | struct _vcs_dpi_soc_bounding_box_st *loaded_bb = |
2360 | get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev); | |
2361 | struct _vcs_dpi_ip_params_st *loaded_ip = | |
2362 | get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev); | |
2363 | ||
7ed4e635 HW |
2364 | DC_LOGGER_INIT(dc->ctx->logger); |
2365 | ||
7ed4e635 HW |
2366 | if (pool->base.pp_smu) { |
2367 | struct pp_smu_nv_clock_table max_clocks = {0}; | |
2368 | unsigned int uclk_states[8] = {0}; | |
2369 | unsigned int num_states = 0; | |
2370 | enum pp_smu_status status; | |
2371 | bool clock_limits_available = false; | |
2372 | bool uclk_states_available = false; | |
2373 | ||
2374 | if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) { | |
2375 | status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) | |
2376 | (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); | |
2377 | ||
2378 | uclk_states_available = (status == PP_SMU_RESULT_OK); | |
2379 | } | |
2380 | ||
2381 | if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) { | |
2382 | status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) | |
2383 | (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks); | |
c2ad17c3 AW |
2384 | /* SMU cannot set DCF clock to anything equal to or higher than SOC clock |
2385 | */ | |
2386 | if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz) | |
2387 | max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000; | |
7ed4e635 HW |
2388 | clock_limits_available = (status == PP_SMU_RESULT_OK); |
2389 | } | |
2390 | ||
bc39a69a AJ |
2391 | if (clock_limits_available && uclk_states_available && num_states) { |
2392 | DC_FP_START(); | |
44ce0cd3 | 2393 | dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states); |
bc39a69a AJ |
2394 | DC_FP_END(); |
2395 | } else if (clock_limits_available) { | |
2396 | DC_FP_START(); | |
44ce0cd3 | 2397 | dcn20_cap_soc_clocks(loaded_bb, max_clocks); |
bc39a69a AJ |
2398 | DC_FP_END(); |
2399 | } | |
7ed4e635 HW |
2400 | } |
2401 | ||
675a9e38 LL |
2402 | loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; |
2403 | loaded_ip->max_num_dpp = pool->base.pipe_count; | |
bc39a69a | 2404 | DC_FP_START(); |
44ce0cd3 | 2405 | dcn20_patch_bounding_box(dc, loaded_bb); |
bc39a69a | 2406 | DC_FP_END(); |
7ed4e635 HW |
2407 | return true; |
2408 | } | |
2409 | ||
d9e32672 | 2410 | static bool dcn20_resource_construct( |
7ed4e635 HW |
2411 | uint8_t num_virtual_links, |
2412 | struct dc *dc, | |
2413 | struct dcn20_resource_pool *pool) | |
2414 | { | |
2415 | int i; | |
2416 | struct dc_context *ctx = dc->ctx; | |
2417 | struct irq_service_init_data init_data; | |
130ac6d8 | 2418 | struct ddc_service_init_data ddc_init_data = {0}; |
675a9e38 LL |
2419 | struct _vcs_dpi_soc_bounding_box_st *loaded_bb = |
2420 | get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev); | |
2421 | struct _vcs_dpi_ip_params_st *loaded_ip = | |
2422 | get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev); | |
2423 | enum dml_project dml_project_version = | |
2424 | get_dml_project_version(ctx->asic_id.hw_internal_rev); | |
7ed4e635 HW |
2425 | |
2426 | ctx->dc_bios->regs = &bios_regs; | |
7ed4e635 HW |
2427 | pool->base.funcs = &dcn20_res_pool_funcs; |
2428 | ||
2ebe1773 BL |
2429 | if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) { |
2430 | pool->base.res_cap = &res_cap_nv14; | |
2431 | pool->base.pipe_count = 5; | |
2432 | pool->base.mpcc_count = 5; | |
2433 | } else { | |
2434 | pool->base.res_cap = &res_cap_nv10; | |
2435 | pool->base.pipe_count = 6; | |
2436 | pool->base.mpcc_count = 6; | |
2437 | } | |
7ed4e635 HW |
2438 | /************************************************* |
2439 | * Resource + asic cap harcoding * | |
2440 | *************************************************/ | |
2441 | pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; | |
2442 | ||
7ed4e635 HW |
2443 | dc->caps.max_downscale_ratio = 200; |
2444 | dc->caps.i2c_speed_in_khz = 100; | |
b15cde19 | 2445 | dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/ |
7ed4e635 | 2446 | dc->caps.max_cursor_size = 256; |
9248681f | 2447 | dc->caps.min_horizontal_blanking_period = 80; |
7ed4e635 HW |
2448 | dc->caps.dmdata_alloc_size = 2048; |
2449 | ||
2450 | dc->caps.max_slave_planes = 1; | |
ae030570 AK |
2451 | dc->caps.max_slave_yuv_planes = 1; |
2452 | dc->caps.max_slave_rgb_planes = 1; | |
7ed4e635 HW |
2453 | dc->caps.post_blend_color_processing = true; |
2454 | dc->caps.force_dp_tps4_for_cp2520 = true; | |
ca4f844e | 2455 | dc->caps.extended_aux_timeout_support = true; |
7ed4e635 | 2456 | |
a8bf7164 KK |
2457 | /* Color pipeline capabilities */ |
2458 | dc->caps.color.dpp.dcn_arch = 1; | |
2459 | dc->caps.color.dpp.input_lut_shared = 0; | |
2460 | dc->caps.color.dpp.icsc = 1; | |
2461 | dc->caps.color.dpp.dgam_ram = 1; | |
2462 | dc->caps.color.dpp.dgam_rom_caps.srgb = 1; | |
2463 | dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; | |
2464 | dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0; | |
2465 | dc->caps.color.dpp.dgam_rom_caps.pq = 0; | |
2466 | dc->caps.color.dpp.dgam_rom_caps.hlg = 0; | |
2467 | dc->caps.color.dpp.post_csc = 0; | |
2468 | dc->caps.color.dpp.gamma_corr = 0; | |
c6160900 | 2469 | dc->caps.color.dpp.dgam_rom_for_yuv = 1; |
a8bf7164 KK |
2470 | |
2471 | dc->caps.color.dpp.hw_3d_lut = 1; | |
2472 | dc->caps.color.dpp.ogam_ram = 1; | |
2473 | // no OGAM ROM on DCN2, only MPC ROM | |
2474 | dc->caps.color.dpp.ogam_rom_caps.srgb = 0; | |
2475 | dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; | |
2476 | dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; | |
2477 | dc->caps.color.dpp.ogam_rom_caps.pq = 0; | |
2478 | dc->caps.color.dpp.ogam_rom_caps.hlg = 0; | |
2479 | dc->caps.color.dpp.ocsc = 0; | |
2480 | ||
2481 | dc->caps.color.mpc.gamut_remap = 0; | |
2482 | dc->caps.color.mpc.num_3dluts = 0; | |
2483 | dc->caps.color.mpc.shared_3d_lut = 0; | |
2484 | dc->caps.color.mpc.ogam_ram = 1; | |
2485 | dc->caps.color.mpc.ogam_rom_caps.srgb = 0; | |
2486 | dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; | |
2487 | dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; | |
2488 | dc->caps.color.mpc.ogam_rom_caps.pq = 0; | |
2489 | dc->caps.color.mpc.ogam_rom_caps.hlg = 0; | |
2490 | dc->caps.color.mpc.ocsc = 1; | |
2491 | ||
068ab0cd | 2492 | dc->caps.dp_hdmi21_pcon_support = true; |
c022375a | 2493 | |
803a1412 | 2494 | if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) { |
7ed4e635 | 2495 | dc->debug = debug_defaults_drv; |
803a1412 ES |
2496 | } else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { |
2497 | pool->base.pipe_count = 4; | |
7ed4e635 HW |
2498 | pool->base.mpcc_count = pool->base.pipe_count; |
2499 | dc->debug = debug_defaults_diags; | |
803a1412 | 2500 | } else { |
7ed4e635 | 2501 | dc->debug = debug_defaults_diags; |
803a1412 | 2502 | } |
7ed4e635 HW |
2503 | //dcn2.0x |
2504 | dc->work_arounds.dedcn20_305_wa = true; | |
2505 | ||
2506 | // Init the vm_helper | |
2507 | if (dc->vm_helper) | |
bda9afda | 2508 | vm_helper_init(dc->vm_helper, 16); |
7ed4e635 HW |
2509 | |
2510 | /************************************************* | |
2511 | * Create resources * | |
2512 | *************************************************/ | |
2513 | ||
2514 | pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = | |
2515 | dcn20_clock_source_create(ctx, ctx->dc_bios, | |
2516 | CLOCK_SOURCE_COMBO_PHY_PLL0, | |
2517 | &clk_src_regs[0], false); | |
2518 | pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = | |
2519 | dcn20_clock_source_create(ctx, ctx->dc_bios, | |
2520 | CLOCK_SOURCE_COMBO_PHY_PLL1, | |
2521 | &clk_src_regs[1], false); | |
2522 | pool->base.clock_sources[DCN20_CLK_SRC_PLL2] = | |
2523 | dcn20_clock_source_create(ctx, ctx->dc_bios, | |
2524 | CLOCK_SOURCE_COMBO_PHY_PLL2, | |
2525 | &clk_src_regs[2], false); | |
2526 | pool->base.clock_sources[DCN20_CLK_SRC_PLL3] = | |
2527 | dcn20_clock_source_create(ctx, ctx->dc_bios, | |
2528 | CLOCK_SOURCE_COMBO_PHY_PLL3, | |
2529 | &clk_src_regs[3], false); | |
2530 | pool->base.clock_sources[DCN20_CLK_SRC_PLL4] = | |
2531 | dcn20_clock_source_create(ctx, ctx->dc_bios, | |
2532 | CLOCK_SOURCE_COMBO_PHY_PLL4, | |
2533 | &clk_src_regs[4], false); | |
2534 | pool->base.clock_sources[DCN20_CLK_SRC_PLL5] = | |
2535 | dcn20_clock_source_create(ctx, ctx->dc_bios, | |
2536 | CLOCK_SOURCE_COMBO_PHY_PLL5, | |
2537 | &clk_src_regs[5], false); | |
2538 | pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL; | |
2539 | /* todo: not reuse phy_pll registers */ | |
2540 | pool->base.dp_clock_source = | |
2541 | dcn20_clock_source_create(ctx, ctx->dc_bios, | |
2542 | CLOCK_SOURCE_ID_DP_DTO, | |
2543 | &clk_src_regs[0], true); | |
2544 | ||
2545 | for (i = 0; i < pool->base.clk_src_count; i++) { | |
2546 | if (pool->base.clock_sources[i] == NULL) { | |
2547 | dm_error("DC: failed to create clock sources!\n"); | |
2548 | BREAK_TO_DEBUGGER(); | |
2549 | goto create_fail; | |
2550 | } | |
2551 | } | |
2552 | ||
2553 | pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); | |
2554 | if (pool->base.dccg == NULL) { | |
2555 | dm_error("DC: failed to create dccg!\n"); | |
2556 | BREAK_TO_DEBUGGER(); | |
2557 | goto create_fail; | |
2558 | } | |
2559 | ||
2560 | pool->base.dmcu = dcn20_dmcu_create(ctx, | |
2561 | &dmcu_regs, | |
2562 | &dmcu_shift, | |
2563 | &dmcu_mask); | |
2564 | if (pool->base.dmcu == NULL) { | |
2565 | dm_error("DC: failed to create dmcu!\n"); | |
2566 | BREAK_TO_DEBUGGER(); | |
2567 | goto create_fail; | |
2568 | } | |
2569 | ||
d7c29549 | 2570 | pool->base.abm = dce_abm_create(ctx, |
7ed4e635 HW |
2571 | &abm_regs, |
2572 | &abm_shift, | |
2573 | &abm_mask); | |
2574 | if (pool->base.abm == NULL) { | |
2575 | dm_error("DC: failed to create abm!\n"); | |
2576 | BREAK_TO_DEBUGGER(); | |
2577 | goto create_fail; | |
d7c29549 | 2578 | } |
7ed4e635 HW |
2579 | |
2580 | pool->base.pp_smu = dcn20_pp_smu_create(ctx); | |
2581 | ||
2582 | ||
2583 | if (!init_soc_bounding_box(dc, pool)) { | |
2584 | dm_error("DC: failed to initialize soc bounding box!\n"); | |
2585 | BREAK_TO_DEBUGGER(); | |
2586 | goto create_fail; | |
2587 | } | |
2588 | ||
675a9e38 | 2589 | dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version); |
7ed4e635 HW |
2590 | |
2591 | if (!dc->debug.disable_pplib_wm_range) { | |
2592 | struct pp_smu_wm_range_sets ranges = {0}; | |
2593 | int i = 0; | |
2594 | ||
2595 | ranges.num_reader_wm_sets = 0; | |
2596 | ||
675a9e38 | 2597 | if (loaded_bb->num_states == 1) { |
7ed4e635 HW |
2598 | ranges.reader_wm_sets[0].wm_inst = i; |
2599 | ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; | |
2600 | ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; | |
2601 | ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; | |
2602 | ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; | |
2603 | ||
2604 | ranges.num_reader_wm_sets = 1; | |
675a9e38 LL |
2605 | } else if (loaded_bb->num_states > 1) { |
2606 | for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { | |
7ed4e635 HW |
2607 | ranges.reader_wm_sets[i].wm_inst = i; |
2608 | ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; | |
2609 | ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; | |
cf689e86 MW |
2610 | DC_FP_START(); |
2611 | dcn20_fpu_set_wm_ranges(i, &ranges, loaded_bb); | |
2612 | DC_FP_END(); | |
7ed4e635 HW |
2613 | |
2614 | ranges.num_reader_wm_sets = i + 1; | |
2615 | } | |
7ed4e635 | 2616 | |
5d36f783 JL |
2617 | ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; |
2618 | ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; | |
2619 | } | |
7ed4e635 HW |
2620 | |
2621 | ranges.num_writer_wm_sets = 1; | |
2622 | ||
2623 | ranges.writer_wm_sets[0].wm_inst = 0; | |
2624 | ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; | |
2625 | ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; | |
2626 | ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; | |
2627 | ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; | |
2628 | ||
2629 | /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ | |
2630 | if (pool->base.pp_smu->nv_funcs.set_wm_ranges) | |
2631 | pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges); | |
2632 | } | |
2633 | ||
2634 | init_data.ctx = dc->ctx; | |
2635 | pool->base.irqs = dal_irq_service_dcn20_create(&init_data); | |
2636 | if (!pool->base.irqs) | |
2637 | goto create_fail; | |
2638 | ||
2639 | /* mem input -> ipp -> dpp -> opp -> TG */ | |
2640 | for (i = 0; i < pool->base.pipe_count; i++) { | |
2641 | pool->base.hubps[i] = dcn20_hubp_create(ctx, i); | |
2642 | if (pool->base.hubps[i] == NULL) { | |
2643 | BREAK_TO_DEBUGGER(); | |
2644 | dm_error( | |
2645 | "DC: failed to create memory input!\n"); | |
2646 | goto create_fail; | |
2647 | } | |
2648 | ||
2649 | pool->base.ipps[i] = dcn20_ipp_create(ctx, i); | |
2650 | if (pool->base.ipps[i] == NULL) { | |
2651 | BREAK_TO_DEBUGGER(); | |
2652 | dm_error( | |
2653 | "DC: failed to create input pixel processor!\n"); | |
2654 | goto create_fail; | |
2655 | } | |
2656 | ||
2657 | pool->base.dpps[i] = dcn20_dpp_create(ctx, i); | |
2658 | if (pool->base.dpps[i] == NULL) { | |
2659 | BREAK_TO_DEBUGGER(); | |
2660 | dm_error( | |
2661 | "DC: failed to create dpps!\n"); | |
2662 | goto create_fail; | |
2663 | } | |
2664 | } | |
2665 | for (i = 0; i < pool->base.res_cap->num_ddc; i++) { | |
2666 | pool->base.engines[i] = dcn20_aux_engine_create(ctx, i); | |
2667 | if (pool->base.engines[i] == NULL) { | |
2668 | BREAK_TO_DEBUGGER(); | |
2669 | dm_error( | |
2670 | "DC:failed to create aux engine!!\n"); | |
2671 | goto create_fail; | |
2672 | } | |
2673 | pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i); | |
2674 | if (pool->base.hw_i2cs[i] == NULL) { | |
2675 | BREAK_TO_DEBUGGER(); | |
2676 | dm_error( | |
2677 | "DC:failed to create hw i2c!!\n"); | |
2678 | goto create_fail; | |
2679 | } | |
2680 | pool->base.sw_i2cs[i] = NULL; | |
2681 | } | |
2682 | ||
2683 | for (i = 0; i < pool->base.res_cap->num_opp; i++) { | |
2684 | pool->base.opps[i] = dcn20_opp_create(ctx, i); | |
2685 | if (pool->base.opps[i] == NULL) { | |
2686 | BREAK_TO_DEBUGGER(); | |
2687 | dm_error( | |
2688 | "DC: failed to create output pixel processor!\n"); | |
2689 | goto create_fail; | |
2690 | } | |
2691 | } | |
2692 | ||
2693 | for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { | |
2694 | pool->base.timing_generators[i] = dcn20_timing_generator_create( | |
2695 | ctx, i); | |
2696 | if (pool->base.timing_generators[i] == NULL) { | |
2697 | BREAK_TO_DEBUGGER(); | |
2698 | dm_error("DC: failed to create tg!\n"); | |
2699 | goto create_fail; | |
2700 | } | |
2701 | } | |
2702 | ||
2703 | pool->base.timing_generator_count = i; | |
2704 | ||
2705 | pool->base.mpc = dcn20_mpc_create(ctx); | |
2706 | if (pool->base.mpc == NULL) { | |
2707 | BREAK_TO_DEBUGGER(); | |
2708 | dm_error("DC: failed to create mpc!\n"); | |
2709 | goto create_fail; | |
2710 | } | |
2711 | ||
2712 | pool->base.hubbub = dcn20_hubbub_create(ctx); | |
2713 | if (pool->base.hubbub == NULL) { | |
2714 | BREAK_TO_DEBUGGER(); | |
2715 | dm_error("DC: failed to create hubbub!\n"); | |
2716 | goto create_fail; | |
2717 | } | |
2718 | ||
97bda032 HW |
2719 | for (i = 0; i < pool->base.res_cap->num_dsc; i++) { |
2720 | pool->base.dscs[i] = dcn20_dsc_create(ctx, i); | |
2721 | if (pool->base.dscs[i] == NULL) { | |
2722 | BREAK_TO_DEBUGGER(); | |
2723 | dm_error("DC: failed to create display stream compressor %d!\n", i); | |
2724 | goto create_fail; | |
2725 | } | |
2726 | } | |
7ed4e635 | 2727 | |
bb21290f CL |
2728 | if (!dcn20_dwbc_create(ctx, &pool->base)) { |
2729 | BREAK_TO_DEBUGGER(); | |
2730 | dm_error("DC: failed to create dwbc!\n"); | |
2731 | goto create_fail; | |
2732 | } | |
2733 | if (!dcn20_mmhubbub_create(ctx, &pool->base)) { | |
2734 | BREAK_TO_DEBUGGER(); | |
2735 | dm_error("DC: failed to create mcif_wb!\n"); | |
2736 | goto create_fail; | |
2737 | } | |
2738 | ||
7ed4e635 HW |
2739 | if (!resource_construct(num_virtual_links, dc, &pool->base, |
2740 | (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? | |
2741 | &res_create_funcs : &res_create_maximus_funcs))) | |
2742 | goto create_fail; | |
2743 | ||
2744 | dcn20_hw_sequencer_construct(dc); | |
2745 | ||
3c9de4da AL |
2746 | // IF NV12, set PG function pointer to NULL. It's not that |
2747 | // PG isn't supported for NV12, it's that we don't want to | |
2748 | // program the registers because that will cause more power | |
2749 | // to be consumed. We could have created dcn20_init_hw to get | |
2750 | // the same effect by checking ASIC rev, but there was a | |
2751 | // request at some point to not check ASIC rev on hw sequencer. | |
15ce104c | 2752 | if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) { |
3c9de4da | 2753 | dc->hwseq->funcs.enable_power_gating_plane = NULL; |
15ce104c AL |
2754 | dc->debug.disable_dpp_power_gate = true; |
2755 | dc->debug.disable_hubp_power_gate = true; | |
2756 | } | |
2757 | ||
3c9de4da | 2758 | |
7ed4e635 HW |
2759 | dc->caps.max_planes = pool->base.pipe_count; |
2760 | ||
2761 | for (i = 0; i < dc->caps.max_planes; ++i) | |
2762 | dc->caps.planes[i] = plane_cap; | |
2763 | ||
2764 | dc->cap_funcs = cap_funcs; | |
2765 | ||
d9a07577 JL |
2766 | if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { |
2767 | ddc_init_data.ctx = dc->ctx; | |
2768 | ddc_init_data.link = NULL; | |
2769 | ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; | |
2770 | ddc_init_data.id.enum_id = 0; | |
2771 | ddc_init_data.id.type = OBJECT_TYPE_GENERIC; | |
2772 | pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); | |
2773 | } else { | |
2774 | pool->base.oem_device = NULL; | |
2775 | } | |
2776 | ||
7ed4e635 HW |
2777 | return true; |
2778 | ||
2779 | create_fail: | |
2780 | ||
d9e32672 | 2781 | dcn20_resource_destruct(pool); |
7ed4e635 HW |
2782 | |
2783 | return false; | |
2784 | } | |
2785 | ||
2786 | struct resource_pool *dcn20_create_resource_pool( | |
2787 | const struct dc_init_data *init_data, | |
2788 | struct dc *dc) | |
2789 | { | |
2790 | struct dcn20_resource_pool *pool = | |
3bb11050 | 2791 | kzalloc(sizeof(struct dcn20_resource_pool), GFP_ATOMIC); |
7ed4e635 HW |
2792 | |
2793 | if (!pool) | |
2794 | return NULL; | |
2795 | ||
d9e32672 | 2796 | if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool)) |
7ed4e635 HW |
2797 | return &pool->base; |
2798 | ||
2799 | BREAK_TO_DEBUGGER(); | |
2800 | kfree(pool); | |
2801 | return NULL; | |
2802 | } |