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drm/amd/display: Add Underflow Asserts to dc
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / dc / dcn20 / dcn20_resource.c
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7ed4e635
HW		 1/*
2* Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services.h"
27#include "dc.h"
28
29#include "resource.h"
30#include "include/irq_service_interface.h"
31#include "dcn20/dcn20_resource.h"
32
33#include "dcn10/dcn10_hubp.h"
34#include "dcn10/dcn10_ipp.h"
35#include "dcn20_hubbub.h"
36#include "dcn20_mpc.h"
37#include "dcn20_hubp.h"
38#include "irq/dcn20/irq_service_dcn20.h"
39#include "dcn20_dpp.h"
40#include "dcn20_optc.h"
41#include "dcn20_hwseq.h"
42#include "dce110/dce110_hw_sequencer.h"
278141f5 43#include "dcn10/dcn10_resource.h"
7ed4e635
HW		 44#include "dcn20_opp.h"
45
97bda032
HW		 46#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
47#include "dcn20_dsc.h"
48#endif
49
7ed4e635
HW		 50#include "dcn20_link_encoder.h"
51#include "dcn20_stream_encoder.h"
52#include "dce/dce_clock_source.h"
53#include "dce/dce_audio.h"
54#include "dce/dce_hwseq.h"
55#include "virtual/virtual_stream_encoder.h"
56#include "dce110/dce110_resource.h"
57#include "dml/display_mode_vba.h"
58#include "dcn20_dccg.h"
59#include "dcn20_vmid.h"
60
61#include "navi10_ip_offset.h"
62
63#include "dcn/dcn_2_0_0_offset.h"
64#include "dcn/dcn_2_0_0_sh_mask.h"
65
66#include "nbio/nbio_2_3_offset.h"
67
bb21290f
CL		 68#include "dcn20/dcn20_dwb.h"
69#include "dcn20/dcn20_mmhubbub.h"
70
7ed4e635
HW		 71#include "mmhub/mmhub_2_0_0_offset.h"
72#include "mmhub/mmhub_2_0_0_sh_mask.h"
73
74#include "reg_helper.h"
75#include "dce/dce_abm.h"
76#include "dce/dce_dmcu.h"
77#include "dce/dce_aux.h"
78#include "dce/dce_i2c.h"
79#include "vm_helper.h"
80
81#include "amdgpu_socbb.h"
82
83#define SOC_BOUNDING_BOX_VALID false
84#define DC_LOGGER_INIT(logger)
85
86struct _vcs_dpi_ip_params_st dcn2_0_ip = {
87 .odm_capable = 1,
88 .gpuvm_enable = 0,
89 .hostvm_enable = 0,
90 .gpuvm_max_page_table_levels = 4,
91 .hostvm_max_page_table_levels = 4,
92 .hostvm_cached_page_table_levels = 0,
93 .pte_group_size_bytes = 2048,
97bda032
HW		 94#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
95 .num_dsc = 6,
96#else
7ed4e635 97 .num_dsc = 0,
97bda032 98#endif
7ed4e635
HW		 99 .rob_buffer_size_kbytes = 168,
100 .det_buffer_size_kbytes = 164,
101 .dpte_buffer_size_in_pte_reqs_luma = 84,
102 .pde_proc_buffer_size_64k_reqs = 48,
103 .dpp_output_buffer_pixels = 2560,
104 .opp_output_buffer_lines = 1,
105 .pixel_chunk_size_kbytes = 8,
106 .pte_chunk_size_kbytes = 2,
107 .meta_chunk_size_kbytes = 2,
108 .writeback_chunk_size_kbytes = 2,
109 .line_buffer_size_bits = 789504,
110 .is_line_buffer_bpp_fixed = 0,
111 .line_buffer_fixed_bpp = 0,
112 .dcc_supported = true,
113 .max_line_buffer_lines = 12,
114 .writeback_luma_buffer_size_kbytes = 12,
115 .writeback_chroma_buffer_size_kbytes = 8,
116 .writeback_chroma_line_buffer_width_pixels = 4,
117 .writeback_max_hscl_ratio = 1,
118 .writeback_max_vscl_ratio = 1,
119 .writeback_min_hscl_ratio = 1,
120 .writeback_min_vscl_ratio = 1,
121 .writeback_max_hscl_taps = 12,
122 .writeback_max_vscl_taps = 12,
123 .writeback_line_buffer_luma_buffer_size = 0,
124 .writeback_line_buffer_chroma_buffer_size = 14643,
125 .cursor_buffer_size = 8,
126 .cursor_chunk_size = 2,
127 .max_num_otg = 6,
128 .max_num_dpp = 6,
129 .max_num_wb = 1,
130 .max_dchub_pscl_bw_pix_per_clk = 4,
131 .max_pscl_lb_bw_pix_per_clk = 2,
132 .max_lb_vscl_bw_pix_per_clk = 4,
133 .max_vscl_hscl_bw_pix_per_clk = 4,
134 .max_hscl_ratio = 8,
135 .max_vscl_ratio = 8,
136 .hscl_mults = 4,
137 .vscl_mults = 4,
138 .max_hscl_taps = 8,
139 .max_vscl_taps = 8,
140 .dispclk_ramp_margin_percent = 1,
141 .underscan_factor = 1.10,
142 .min_vblank_lines = 32, //
143 .dppclk_delay_subtotal = 77, //
144 .dppclk_delay_scl_lb_only = 16,
145 .dppclk_delay_scl = 50,
146 .dppclk_delay_cnvc_formatter = 8,
147 .dppclk_delay_cnvc_cursor = 6,
148 .dispclk_delay_subtotal = 87, //
149 .dcfclk_cstate_latency = 10, // SRExitTime
150 .max_inter_dcn_tile_repeaters = 8,
151
152 .xfc_supported = true,
153 .xfc_fill_bw_overhead_percent = 10.0,
154 .xfc_fill_constant_bytes = 0,
155};
156
157struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = { 0 };
158
159
160#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
161 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
162 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
163 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
164 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
165 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
166 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
167 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
168 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
169 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
170 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
171 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
172 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
173 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
174 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
175#endif
176
177
178enum dcn20_clk_src_array_id {
179 DCN20_CLK_SRC_PLL0,
180 DCN20_CLK_SRC_PLL1,
181 DCN20_CLK_SRC_PLL2,
182 DCN20_CLK_SRC_PLL3,
183 DCN20_CLK_SRC_PLL4,
184 DCN20_CLK_SRC_PLL5,
185 DCN20_CLK_SRC_TOTAL
186};
187
188/* begin *********************
189 * macros to expend register list macro defined in HW object header file */
190
191/* DCN */
192/* TODO awful hack. fixup dcn20_dwb.h */
193#undef BASE_INNER
194#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
195
196#define BASE(seg) BASE_INNER(seg)
197
198#define SR(reg_name)\
199 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
200 mm ## reg_name
201
202#define SRI(reg_name, block, id)\
203 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
204 mm ## block ## id ## _ ## reg_name
205
206#define SRIR(var_name, reg_name, block, id)\
207 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
208 mm ## block ## id ## _ ## reg_name
209
210#define SRII(reg_name, block, id)\
211 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
212 mm ## block ## id ## _ ## reg_name
213
214#define DCCG_SRII(reg_name, block, id)\
215 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
216 mm ## block ## id ## _ ## reg_name
217
218/* NBIO */
219#define NBIO_BASE_INNER(seg) \
220 NBIO_BASE__INST0_SEG ## seg
221
222#define NBIO_BASE(seg) \
223 NBIO_BASE_INNER(seg)
224
225#define NBIO_SR(reg_name)\
226 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
227 mm ## reg_name
228
229/* MMHUB */
230#define MMHUB_BASE_INNER(seg) \
231 MMHUB_BASE__INST0_SEG ## seg
232
233#define MMHUB_BASE(seg) \
234 MMHUB_BASE_INNER(seg)
235
236#define MMHUB_SR(reg_name)\
237 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
238 mmMM ## reg_name
239
240static const struct bios_registers bios_regs = {
241 NBIO_SR(BIOS_SCRATCH_3),
242 NBIO_SR(BIOS_SCRATCH_6)
243};
244
245#define clk_src_regs(index, pllid)\
246[index] = {\
247 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
248}
249
250static const struct dce110_clk_src_regs clk_src_regs[] = {
251 clk_src_regs(0, A),
252 clk_src_regs(1, B),
253 clk_src_regs(2, C),
254 clk_src_regs(3, D),
255 clk_src_regs(4, E),
256 clk_src_regs(5, F)
257};
258
259static const struct dce110_clk_src_shift cs_shift = {
260 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
261};
262
263static const struct dce110_clk_src_mask cs_mask = {
264 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
265};
266
267static const struct dce_dmcu_registers dmcu_regs = {
268 DMCU_DCN10_REG_LIST()
269};
270
271static const struct dce_dmcu_shift dmcu_shift = {
272 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
273};
274
275static const struct dce_dmcu_mask dmcu_mask = {
276 DMCU_MASK_SH_LIST_DCN10(_MASK)
277};
d7c29549 278
7ed4e635 279static const struct dce_abm_registers abm_regs = {
d7c29549 280 ABM_DCN20_REG_LIST()
7ed4e635
HW		 281};
282
283static const struct dce_abm_shift abm_shift = {
d7c29549 284 ABM_MASK_SH_LIST_DCN20(__SHIFT)
7ed4e635
HW		 285};
286
287static const struct dce_abm_mask abm_mask = {
d7c29549 288 ABM_MASK_SH_LIST_DCN20(_MASK)
7ed4e635 289};
d7c29549 290
7ed4e635
HW		 291#define audio_regs(id)\
292[id] = {\
293 AUD_COMMON_REG_LIST(id)\
294}
295
296static const struct dce_audio_registers audio_regs[] = {
297 audio_regs(0),
298 audio_regs(1),
299 audio_regs(2),
300 audio_regs(3),
301 audio_regs(4),
302 audio_regs(5),
303 audio_regs(6),
304};
305
306#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
307 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
308 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
309 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
310
311static const struct dce_audio_shift audio_shift = {
312 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
313};
314
315static const struct dce_aduio_mask audio_mask = {
316 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
317};
318
319#define stream_enc_regs(id)\
320[id] = {\
321 SE_DCN2_REG_LIST(id)\
322}
323
324static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
325 stream_enc_regs(0),
326 stream_enc_regs(1),
327 stream_enc_regs(2),
328 stream_enc_regs(3),
329 stream_enc_regs(4),
330 stream_enc_regs(5),
331};
332
333static const struct dcn10_stream_encoder_shift se_shift = {
334 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
335};
336
337static const struct dcn10_stream_encoder_mask se_mask = {
338 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
339};
340
341
342#define aux_regs(id)\
343[id] = {\
344 DCN2_AUX_REG_LIST(id)\
345}
346
347static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
348 aux_regs(0),
349 aux_regs(1),
350 aux_regs(2),
351 aux_regs(3),
352 aux_regs(4),
353 aux_regs(5)
354};
355
356#define hpd_regs(id)\
357[id] = {\
358 HPD_REG_LIST(id)\
359}
360
361static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
362 hpd_regs(0),
363 hpd_regs(1),
364 hpd_regs(2),
365 hpd_regs(3),
366 hpd_regs(4),
367 hpd_regs(5)
368};
369
370#define link_regs(id, phyid)\
371[id] = {\
372 LE_DCN10_REG_LIST(id), \
373 UNIPHY_DCN2_REG_LIST(phyid), \
374 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
375}
376
377static const struct dcn10_link_enc_registers link_enc_regs[] = {
378 link_regs(0, A),
379 link_regs(1, B),
380 link_regs(2, C),
381 link_regs(3, D),
382 link_regs(4, E),
383 link_regs(5, F)
384};
385
386static const struct dcn10_link_enc_shift le_shift = {
387 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT)
388};
389
390static const struct dcn10_link_enc_mask le_mask = {
391 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK)
392};
393
394#define ipp_regs(id)\
395[id] = {\
396 IPP_REG_LIST_DCN20(id),\
397}
398
399static const struct dcn10_ipp_registers ipp_regs[] = {
400 ipp_regs(0),
401 ipp_regs(1),
402 ipp_regs(2),
403 ipp_regs(3),
404 ipp_regs(4),
405 ipp_regs(5),
406};
407
408static const struct dcn10_ipp_shift ipp_shift = {
409 IPP_MASK_SH_LIST_DCN20(__SHIFT)
410};
411
412static const struct dcn10_ipp_mask ipp_mask = {
413 IPP_MASK_SH_LIST_DCN20(_MASK),
414};
415
416#define opp_regs(id)\
417[id] = {\
418 OPP_REG_LIST_DCN20(id),\
419}
420
421static const struct dcn20_opp_registers opp_regs[] = {
422 opp_regs(0),
423 opp_regs(1),
424 opp_regs(2),
425 opp_regs(3),
426 opp_regs(4),
427 opp_regs(5),
428};
429
430static const struct dcn20_opp_shift opp_shift = {
431 OPP_MASK_SH_LIST_DCN20(__SHIFT)
432};
433
434static const struct dcn20_opp_mask opp_mask = {
435 OPP_MASK_SH_LIST_DCN20(_MASK)
436};
437
438#define aux_engine_regs(id)\
439[id] = {\
440 AUX_COMMON_REG_LIST0(id), \
441 .AUXN_IMPCAL = 0, \
442 .AUXP_IMPCAL = 0, \
443 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
444}
445
446static const struct dce110_aux_registers aux_engine_regs[] = {
447 aux_engine_regs(0),
448 aux_engine_regs(1),
449 aux_engine_regs(2),
450 aux_engine_regs(3),
451 aux_engine_regs(4),
452 aux_engine_regs(5)
453};
454
455#define tf_regs(id)\
456[id] = {\
457 TF_REG_LIST_DCN20(id),\
458}
459
460static const struct dcn2_dpp_registers tf_regs[] = {
461 tf_regs(0),
462 tf_regs(1),
463 tf_regs(2),
464 tf_regs(3),
465 tf_regs(4),
466 tf_regs(5),
467};
468
469static const struct dcn2_dpp_shift tf_shift = {
470 TF_REG_LIST_SH_MASK_DCN20(__SHIFT)
471};
472
473static const struct dcn2_dpp_mask tf_mask = {
474 TF_REG_LIST_SH_MASK_DCN20(_MASK)
475};
476
bb21290f
CL		 477#define dwbc_regs_dcn2(id)\
478[id] = {\
479 DWBC_COMMON_REG_LIST_DCN2_0(id),\
480 }
481
482static const struct dcn20_dwbc_registers dwbc20_regs[] = {
483 dwbc_regs_dcn2(0),
484};
485
486static const struct dcn20_dwbc_shift dwbc20_shift = {
487 DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
488};
489
490static const struct dcn20_dwbc_mask dwbc20_mask = {
491 DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
492};
493
494#define mcif_wb_regs_dcn2(id)\
495[id] = {\
496 MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\
497 }
498
499static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {
500 mcif_wb_regs_dcn2(0),
501};
502
503static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {
504 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
505};
506
507static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {
508 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
509};
510
7ed4e635
HW		 511static const struct dcn20_mpc_registers mpc_regs = {
512 MPC_REG_LIST_DCN2_0(0),
513 MPC_REG_LIST_DCN2_0(1),
514 MPC_REG_LIST_DCN2_0(2),
515 MPC_REG_LIST_DCN2_0(3),
516 MPC_REG_LIST_DCN2_0(4),
517 MPC_REG_LIST_DCN2_0(5),
518 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
519 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
520 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
521 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
522 MPC_OUT_MUX_REG_LIST_DCN2_0(4),
523 MPC_OUT_MUX_REG_LIST_DCN2_0(5),
524};
525
526static const struct dcn20_mpc_shift mpc_shift = {
527 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
528};
529
530static const struct dcn20_mpc_mask mpc_mask = {
531 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
532};
533
534#define tg_regs(id)\
535[id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
536
537
538static const struct dcn_optc_registers tg_regs[] = {
539 tg_regs(0),
540 tg_regs(1),
541 tg_regs(2),
542 tg_regs(3),
543 tg_regs(4),
544 tg_regs(5)
545};
546
547static const struct dcn_optc_shift tg_shift = {
548 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
549};
550
551static const struct dcn_optc_mask tg_mask = {
552 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
553};
554
555#define hubp_regs(id)\
556[id] = {\
557 HUBP_REG_LIST_DCN20(id)\
558}
559
560static const struct dcn_hubp2_registers hubp_regs[] = {
561 hubp_regs(0),
562 hubp_regs(1),
563 hubp_regs(2),
564 hubp_regs(3),
565 hubp_regs(4),
566 hubp_regs(5)
567};
568
569static const struct dcn_hubp2_shift hubp_shift = {
570 HUBP_MASK_SH_LIST_DCN20(__SHIFT)
571};
572
573static const struct dcn_hubp2_mask hubp_mask = {
574 HUBP_MASK_SH_LIST_DCN20(_MASK)
575};
576
577static const struct dcn_hubbub_registers hubbub_reg = {
578 HUBBUB_REG_LIST_DCN20(0)
579};
580
581static const struct dcn_hubbub_shift hubbub_shift = {
582 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT)
583};
584
585static const struct dcn_hubbub_mask hubbub_mask = {
586 HUBBUB_MASK_SH_LIST_DCN20(_MASK)
587};
588
589#define vmid_regs(id)\
590[id] = {\
591 DCN20_VMID_REG_LIST(id)\
592}
593
594static const struct dcn_vmid_registers vmid_regs[] = {
595 vmid_regs(0),
596 vmid_regs(1),
597 vmid_regs(2),
598 vmid_regs(3),
599 vmid_regs(4),
600 vmid_regs(5),
601 vmid_regs(6),
602 vmid_regs(7),
603 vmid_regs(8),
604 vmid_regs(9),
605 vmid_regs(10),
606 vmid_regs(11),
607 vmid_regs(12),
608 vmid_regs(13),
609 vmid_regs(14),
610 vmid_regs(15)
611};
612
613static const struct dcn20_vmid_shift vmid_shifts = {
614 DCN20_VMID_MASK_SH_LIST(__SHIFT)
615};
616
617static const struct dcn20_vmid_mask vmid_masks = {
618 DCN20_VMID_MASK_SH_LIST(_MASK)
619};
620
97bda032
HW		 621#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
622#define dsc_regsDCN20(id)\
623[id] = {\
624 DSC_REG_LIST_DCN20(id)\
625}
626
627static const struct dcn20_dsc_registers dsc_regs[] = {
628 dsc_regsDCN20(0),
629 dsc_regsDCN20(1),
630 dsc_regsDCN20(2),
631 dsc_regsDCN20(3),
632 dsc_regsDCN20(4),
633 dsc_regsDCN20(5)
634};
635
636static const struct dcn20_dsc_shift dsc_shift = {
637 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
638};
639
640static const struct dcn20_dsc_mask dsc_mask = {
641 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
642};
643#endif
7ed4e635
HW		 644
645static const struct dccg_registers dccg_regs = {
646 DCCG_REG_LIST_DCN2()
647};
648
649static const struct dccg_shift dccg_shift = {
650 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
651};
652
653static const struct dccg_mask dccg_mask = {
654 DCCG_MASK_SH_LIST_DCN2(_MASK)
655};
656
657static const struct resource_caps res_cap_nv10 = {
658 .num_timing_generator = 6,
659 .num_opp = 6,
660 .num_video_plane = 6,
661 .num_audio = 7,
662 .num_stream_encoder = 6,
663 .num_pll = 6,
0d7bd17c 664 .num_dwb = 0,
7ed4e635
HW		 665 .num_ddc = 6,
666 .num_vmid = 16,
97bda032
HW		 667#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
668 .num_dsc = 6,
669#endif
7ed4e635
HW		 670};
671
672static const struct dc_plane_cap plane_cap = {
673 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
674 .blends_with_above = true,
675 .blends_with_below = true,
7ed4e635 676 .per_pixel_alpha = true,
5b1b2f20
AD		 677
678 .pixel_format_support = {
679 .argb8888 = true,
680 .nv12 = true,
681 .fp16 = true
682 },
683
684 .max_upscale_factor = {
685 .argb8888 = 16000,
686 .nv12 = 16000,
687 .fp16 = 1
688 },
689
690 .max_downscale_factor = {
691 .argb8888 = 250,
692 .nv12 = 250,
693 .fp16 = 1
694 }
7ed4e635
HW		 695};
696
697static const struct dc_debug_options debug_defaults_drv = {
698 .disable_dmcu = true,
699 .force_abm_enable = false,
700 .timing_trace = false,
701 .clock_trace = true,
702 .disable_pplib_clock_request = true,
703 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
704 .force_single_disp_pipe_split = true,
705 .disable_dcc = DCC_ENABLE,
706 .vsr_support = true,
707 .performance_trace = false,
708 .max_downscale_src_width = 5120,/*upto 5K*/
709 .disable_pplib_wm_range = false,
710 .scl_reset_length10 = true,
9e14d4f1 711 .sanity_checks = false,
7ed4e635 712 .disable_tri_buf = true,
1a7d296d 713 .underflow_assert_delay_us = 0xFFFFFFFF,
7ed4e635
HW		 714};
715
716static const struct dc_debug_options debug_defaults_diags = {
717 .disable_dmcu = true,
718 .force_abm_enable = false,
719 .timing_trace = true,
720 .clock_trace = true,
721 .disable_dpp_power_gate = true,
722 .disable_hubp_power_gate = true,
723 .disable_clock_gate = true,
724 .disable_pplib_clock_request = true,
725 .disable_pplib_wm_range = true,
726 .disable_stutter = true,
727 .scl_reset_length10 = true,
1a7d296d 728 .underflow_assert_delay_us = 0xFFFFFFFF,
7ed4e635
HW		 729};
730
731void dcn20_dpp_destroy(struct dpp **dpp)
732{
733 kfree(TO_DCN20_DPP(*dpp));
734 *dpp = NULL;
735}
736
737struct dpp *dcn20_dpp_create(
738 struct dc_context *ctx,
739 uint32_t inst)
740{
741 struct dcn20_dpp *dpp =
742 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
743
744 if (!dpp)
745 return NULL;
746
747 if (dpp2_construct(dpp, ctx, inst,
748 &tf_regs[inst], &tf_shift, &tf_mask))
749 return &dpp->base;
750
751 BREAK_TO_DEBUGGER();
752 kfree(dpp);
753 return NULL;
754}
755
756struct input_pixel_processor *dcn20_ipp_create(
757 struct dc_context *ctx, uint32_t inst)
758{
759 struct dcn10_ipp *ipp =
760 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
761
762 if (!ipp) {
763 BREAK_TO_DEBUGGER();
764 return NULL;
765 }
766
767 dcn20_ipp_construct(ipp, ctx, inst,
768 &ipp_regs[inst], &ipp_shift, &ipp_mask);
769 return &ipp->base;
770}
771
772
773struct output_pixel_processor *dcn20_opp_create(
774 struct dc_context *ctx, uint32_t inst)
775{
776 struct dcn20_opp *opp =
777 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
778
779 if (!opp) {
780 BREAK_TO_DEBUGGER();
781 return NULL;
782 }
783
784 dcn20_opp_construct(opp, ctx, inst,
785 &opp_regs[inst], &opp_shift, &opp_mask);
786 return &opp->base;
787}
788
789struct dce_aux *dcn20_aux_engine_create(
790 struct dc_context *ctx,
791 uint32_t inst)
792{
793 struct aux_engine_dce110 *aux_engine =
794 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
795
796 if (!aux_engine)
797 return NULL;
798
799 dce110_aux_engine_construct(aux_engine, ctx, inst,
800 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
801 &aux_engine_regs[inst]);
802
803 return &aux_engine->base;
804}
805#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
806
807static const struct dce_i2c_registers i2c_hw_regs[] = {
808 i2c_inst_regs(1),
809 i2c_inst_regs(2),
810 i2c_inst_regs(3),
811 i2c_inst_regs(4),
812 i2c_inst_regs(5),
813 i2c_inst_regs(6),
814};
815
816static const struct dce_i2c_shift i2c_shifts = {
817 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
818};
819
820static const struct dce_i2c_mask i2c_masks = {
821 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
822};
823
824struct dce_i2c_hw *dcn20_i2c_hw_create(
825 struct dc_context *ctx,
826 uint32_t inst)
827{
828 struct dce_i2c_hw *dce_i2c_hw =
829 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
830
831 if (!dce_i2c_hw)
832 return NULL;
833
834 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
835 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
836
837 return dce_i2c_hw;
838}
839struct mpc *dcn20_mpc_create(struct dc_context *ctx)
840{
841 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
842 GFP_KERNEL);
843
844 if (!mpc20)
845 return NULL;
846
847 dcn20_mpc_construct(mpc20, ctx,
848 &mpc_regs,
849 &mpc_shift,
850 &mpc_mask,
851 6);
852
853 return &mpc20->base;
854}
855
856struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)
857{
858 int i;
859 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
860 GFP_KERNEL);
861
862 if (!hubbub)
863 return NULL;
864
865 hubbub2_construct(hubbub, ctx,
866 &hubbub_reg,
867 &hubbub_shift,
868 &hubbub_mask);
869
870 for (i = 0; i < res_cap_nv10.num_vmid; i++) {
871 struct dcn20_vmid *vmid = &hubbub->vmid[i];
872
873 vmid->ctx = ctx;
874
875 vmid->regs = &vmid_regs[i];
876 vmid->shifts = &vmid_shifts;
877 vmid->masks = &vmid_masks;
878 }
879
880 return &hubbub->base;
881}
882
883struct timing_generator *dcn20_timing_generator_create(
884 struct dc_context *ctx,
885 uint32_t instance)
886{
887 struct optc *tgn10 =
888 kzalloc(sizeof(struct optc), GFP_KERNEL);
889
890 if (!tgn10)
891 return NULL;
892
893 tgn10->base.inst = instance;
894 tgn10->base.ctx = ctx;
895
896 tgn10->tg_regs = &tg_regs[instance];
897 tgn10->tg_shift = &tg_shift;
898 tgn10->tg_mask = &tg_mask;
899
900 dcn20_timing_generator_init(tgn10);
901
902 return &tgn10->base;
903}
904
905static const struct encoder_feature_support link_enc_feature = {
906 .max_hdmi_deep_color = COLOR_DEPTH_121212,
907 .max_hdmi_pixel_clock = 600000,
908 .hdmi_ycbcr420_supported = true,
909 .dp_ycbcr420_supported = true,
910 .flags.bits.IS_HBR2_CAPABLE = true,
911 .flags.bits.IS_HBR3_CAPABLE = true,
912 .flags.bits.IS_TPS3_CAPABLE = true,
913 .flags.bits.IS_TPS4_CAPABLE = true
914};
915
916struct link_encoder *dcn20_link_encoder_create(
917 const struct encoder_init_data *enc_init_data)
918{
919 struct dcn20_link_encoder *enc20 =
920 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
921
922 if (!enc20)
923 return NULL;
924
925 dcn20_link_encoder_construct(enc20,
926 enc_init_data,
927 &link_enc_feature,
928 &link_enc_regs[enc_init_data->transmitter],
929 &link_enc_aux_regs[enc_init_data->channel - 1],
930 &link_enc_hpd_regs[enc_init_data->hpd_source],
931 &le_shift,
932 &le_mask);
933
934 return &enc20->enc10.base;
935}
936
937struct clock_source *dcn20_clock_source_create(
938 struct dc_context *ctx,
939 struct dc_bios *bios,
940 enum clock_source_id id,
941 const struct dce110_clk_src_regs *regs,
942 bool dp_clk_src)
943{
944 struct dce110_clk_src *clk_src =
945 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
946
947 if (!clk_src)
948 return NULL;
949
950 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
951 regs, &cs_shift, &cs_mask)) {
952 clk_src->base.dp_clk_src = dp_clk_src;
953 return &clk_src->base;
954 }
955
956 BREAK_TO_DEBUGGER();
957 return NULL;
958}
959
960static void read_dce_straps(
961 struct dc_context *ctx,
962 struct resource_straps *straps)
963{
964 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
965 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
966}
967
968static struct audio *dcn20_create_audio(
969 struct dc_context *ctx, unsigned int inst)
970{
971 return dce_audio_create(ctx, inst,
972 &audio_regs[inst], &audio_shift, &audio_mask);
973}
974
975struct stream_encoder *dcn20_stream_encoder_create(
976 enum engine_id eng_id,
977 struct dc_context *ctx)
978{
979 struct dcn10_stream_encoder *enc1 =
980 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
981
982 if (!enc1)
983 return NULL;
984
985 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
986 &stream_enc_regs[eng_id],
987 &se_shift, &se_mask);
988
989 return &enc1->base;
990}
991
992static const struct dce_hwseq_registers hwseq_reg = {
993 HWSEQ_DCN2_REG_LIST()
994};
995
996static const struct dce_hwseq_shift hwseq_shift = {
997 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT)
998};
999
1000static const struct dce_hwseq_mask hwseq_mask = {
1001 HWSEQ_DCN2_MASK_SH_LIST(_MASK)
1002};
1003
1004struct dce_hwseq *dcn20_hwseq_create(
1005 struct dc_context *ctx)
1006{
1007 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1008
1009 if (hws) {
1010 hws->ctx = ctx;
1011 hws->regs = &hwseq_reg;
1012 hws->shifts = &hwseq_shift;
1013 hws->masks = &hwseq_mask;
1014 }
1015 return hws;
1016}
1017
1018static const struct resource_create_funcs res_create_funcs = {
1019 .read_dce_straps = read_dce_straps,
1020 .create_audio = dcn20_create_audio,
1021 .create_stream_encoder = dcn20_stream_encoder_create,
1022 .create_hwseq = dcn20_hwseq_create,
1023};
1024
1025static const struct resource_create_funcs res_create_maximus_funcs = {
1026 .read_dce_straps = NULL,
1027 .create_audio = NULL,
1028 .create_stream_encoder = NULL,
1029 .create_hwseq = dcn20_hwseq_create,
1030};
1031
1032void dcn20_clock_source_destroy(struct clock_source **clk_src)
1033{
1034 kfree(TO_DCE110_CLK_SRC(*clk_src));
1035 *clk_src = NULL;
1036}
1037
97bda032
HW		 1038#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1039
1040struct display_stream_compressor *dcn20_dsc_create(
1041 struct dc_context *ctx, uint32_t inst)
1042{
1043 struct dcn20_dsc *dsc =
1044 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1045
1046 if (!dsc) {
1047 BREAK_TO_DEBUGGER();
1048 return NULL;
1049 }
1050
1051 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1052 return &dsc->base;
1053}
1054
1055void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
1056{
1057 kfree(container_of(*dsc, struct dcn20_dsc, base));
1058 *dsc = NULL;
1059}
1060
1061#endif
7ed4e635
HW		 1062
1063static void destruct(struct dcn20_resource_pool *pool)
1064{
1065 unsigned int i;
1066
1067 for (i = 0; i < pool->base.stream_enc_count; i++) {
1068 if (pool->base.stream_enc[i] != NULL) {
1069 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1070 pool->base.stream_enc[i] = NULL;
1071 }
1072 }
1073
97bda032
HW		 1074#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1075 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1076 if (pool->base.dscs[i] != NULL)
1077 dcn20_dsc_destroy(&pool->base.dscs[i]);
1078 }
1079#endif
7ed4e635
HW		 1080
1081 if (pool->base.mpc != NULL) {
1082 kfree(TO_DCN20_MPC(pool->base.mpc));
1083 pool->base.mpc = NULL;
1084 }
1085 if (pool->base.hubbub != NULL) {
1086 kfree(pool->base.hubbub);
1087 pool->base.hubbub = NULL;
1088 }
1089 for (i = 0; i < pool->base.pipe_count; i++) {
1090 if (pool->base.dpps[i] != NULL)
1091 dcn20_dpp_destroy(&pool->base.dpps[i]);
1092
1093 if (pool->base.ipps[i] != NULL)
1094 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1095
1096 if (pool->base.hubps[i] != NULL) {
1097 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1098 pool->base.hubps[i] = NULL;
1099 }
1100
1101 if (pool->base.irqs != NULL) {
1102 dal_irq_service_destroy(&pool->base.irqs);
1103 }
1104 }
1105
1106 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1107 if (pool->base.engines[i] != NULL)
1108 dce110_engine_destroy(&pool->base.engines[i]);
1109 if (pool->base.hw_i2cs[i] != NULL) {
1110 kfree(pool->base.hw_i2cs[i]);
1111 pool->base.hw_i2cs[i] = NULL;
1112 }
1113 if (pool->base.sw_i2cs[i] != NULL) {
1114 kfree(pool->base.sw_i2cs[i]);
1115 pool->base.sw_i2cs[i] = NULL;
1116 }
1117 }
1118
1119 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1120 if (pool->base.opps[i] != NULL)
1121 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1122 }
1123
1124 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1125 if (pool->base.timing_generators[i] != NULL) {
1126 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1127 pool->base.timing_generators[i] = NULL;
1128 }
1129 }
1130
bb21290f
CL		 1131 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1132 if (pool->base.dwbc[i] != NULL) {
1133 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
1134 pool->base.dwbc[i] = NULL;
1135 }
1136 if (pool->base.mcif_wb[i] != NULL) {
1137 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
1138 pool->base.mcif_wb[i] = NULL;
1139 }
1140 }
1141
7ed4e635
HW		 1142 for (i = 0; i < pool->base.audio_count; i++) {
1143 if (pool->base.audios[i])
1144 dce_aud_destroy(&pool->base.audios[i]);
1145 }
1146
1147 for (i = 0; i < pool->base.clk_src_count; i++) {
1148 if (pool->base.clock_sources[i] != NULL) {
1149 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1150 pool->base.clock_sources[i] = NULL;
1151 }
1152 }
1153
1154 if (pool->base.dp_clock_source != NULL) {
1155 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1156 pool->base.dp_clock_source = NULL;
1157 }
1158
1159
1160 if (pool->base.abm != NULL)
1161 dce_abm_destroy(&pool->base.abm);
1162
1163 if (pool->base.dmcu != NULL)
1164 dce_dmcu_destroy(&pool->base.dmcu);
1165
1166 if (pool->base.dccg != NULL)
1167 dcn_dccg_destroy(&pool->base.dccg);
1168
1169 if (pool->base.pp_smu != NULL)
1170 dcn20_pp_smu_destroy(&pool->base.pp_smu);
1171
1172}
1173
1174struct hubp *dcn20_hubp_create(
1175 struct dc_context *ctx,
1176 uint32_t inst)
1177{
1178 struct dcn20_hubp *hubp2 =
1179 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1180
1181 if (!hubp2)
1182 return NULL;
1183
1184 if (hubp2_construct(hubp2, ctx, inst,
1185 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1186 return &hubp2->base;
1187
1188 BREAK_TO_DEBUGGER();
1189 kfree(hubp2);
1190 return NULL;
1191}
1192
1193static void get_pixel_clock_parameters(
1194 struct pipe_ctx *pipe_ctx,
1195 struct pixel_clk_params *pixel_clk_params)
1196{
1197 const struct dc_stream_state *stream = pipe_ctx->stream;
1198 bool odm_combine = dc_res_get_odm_bottom_pipe(pipe_ctx) != NULL;
1199
1200 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1201 pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1202 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1203 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1204 /* TODO: un-hardcode*/
1205 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1206 LINK_RATE_REF_FREQ_IN_KHZ;
1207 pixel_clk_params->flags.ENABLE_SS = 0;
1208 pixel_clk_params->color_depth =
1209 stream->timing.display_color_depth;
1210 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1211 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1212
1213 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1214 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1215
1216 if (optc1_is_two_pixels_per_containter(&stream->timing) || odm_combine)
1217 pixel_clk_params->requested_pix_clk_100hz /= 2;
1218
1219 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1220 pixel_clk_params->requested_pix_clk_100hz *= 2;
1221
1222}
1223
1224static void build_clamping_params(struct dc_stream_state *stream)
1225{
1226 stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1227 stream->clamping.c_depth = stream->timing.display_color_depth;
1228 stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1229}
1230
1231static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1232{
1233
1234 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1235
1236 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1237 pipe_ctx->clock_source,
1238 &pipe_ctx->stream_res.pix_clk_params,
1239 &pipe_ctx->pll_settings);
1240
1241 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1242
1243 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1244 &pipe_ctx->stream->bit_depth_params);
1245 build_clamping_params(pipe_ctx->stream);
1246
1247 return DC_OK;
1248}
1249
1250enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
1251{
1252 enum dc_status status = DC_OK;
1253 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1254
1255 /*TODO Seems unneeded anymore */
1256 /* if (old_context && resource_is_stream_unchanged(old_context, stream)) {
1257 if (stream != NULL && old_context->streams[i] != NULL) {
1258 todo: shouldn't have to copy missing parameter here
1259 resource_build_bit_depth_reduction_params(stream,
1260 &stream->bit_depth_params);
1261 stream->clamping.pixel_encoding =
1262 stream->timing.pixel_encoding;
1263
1264 resource_build_bit_depth_reduction_params(stream,
1265 &stream->bit_depth_params);
1266 build_clamping_params(stream);
1267
1268 continue;
1269 }
1270 }
1271 */
1272
1273 if (!pipe_ctx)
1274 return DC_ERROR_UNEXPECTED;
1275
1276
1277 status = build_pipe_hw_param(pipe_ctx);
1278
1279 return status;
1280}
1281
97bda032
HW		 1282#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1283
c9ae6e16
NC		 1284static void acquire_dsc(struct resource_context *res_ctx,
1285 const struct resource_pool *pool,
1286 struct display_stream_compressor **dsc)
97bda032
HW		 1287{
1288 int i;
c9ae6e16
NC		 1289
1290 ASSERT(*dsc == NULL);
1291 *dsc = NULL;
97bda032
HW		 1292
1293 /* Find first free DSC */
1294 for (i = 0; i < pool->res_cap->num_dsc; i++)
1295 if (!res_ctx->is_dsc_acquired[i]) {
c9ae6e16 1296 *dsc = pool->dscs[i];
97bda032
HW		 1297 res_ctx->is_dsc_acquired[i] = true;
1298 break;
1299 }
97bda032
HW		 1300}
1301
1302static void release_dsc(struct resource_context *res_ctx,
1303 const struct resource_pool *pool,
c9ae6e16 1304 struct display_stream_compressor **dsc)
97bda032
HW		 1305{
1306 int i;
1307
1308 for (i = 0; i < pool->res_cap->num_dsc; i++)
c9ae6e16 1309 if (pool->dscs[i] == *dsc) {
97bda032 1310 res_ctx->is_dsc_acquired[i] = false;
c9ae6e16 1311 *dsc = NULL;
97bda032
HW		 1312 break;
1313 }
1314}
1315
1316#endif
7ed4e635 1317
7ed4e635 1318
97bda032 1319#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
ba32c50f 1320static enum dc_status add_dsc_to_stream_resource(struct dc *dc,
c9ae6e16
NC		 1321 struct dc_state *dc_ctx,
1322 struct dc_stream_state *dc_stream)
1323{
1324 enum dc_status result = DC_OK;
1325 int i;
1326 const struct resource_pool *pool = dc->res_pool;
97bda032 1327
c9ae6e16
NC		 1328 /* Get a DSC if required and available */
1329 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1330 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];
97bda032 1331
c9ae6e16
NC		 1332 if (pipe_ctx->stream != dc_stream)
1333 continue;
97bda032 1334
c9ae6e16 1335 acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc);
97bda032 1336
c9ae6e16
NC		 1337 /* The number of DSCs can be less than the number of pipes */
1338 if (!pipe_ctx->stream_res.dsc) {
1339 dm_output_to_console("No DSCs available\n");
1340 result = DC_NO_DSC_RESOURCE;
97bda032 1341 }
7ed4e635 1342
c9ae6e16
NC		 1343 break;
1344 }
7ed4e635
HW		 1345
1346 return result;
1347}
1348
1349
ba32c50f 1350static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
c9ae6e16
NC		 1351 struct dc_state *new_ctx,
1352 struct dc_stream_state *dc_stream)
7ed4e635
HW		 1353{
1354 struct pipe_ctx *pipe_ctx = NULL;
1355 int i;
1356
7ed4e635
HW		 1357 for (i = 0; i < MAX_PIPES; i++) {
1358 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1359 pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1360 break;
1361 }
1362 }
1363
1364 if (!pipe_ctx)
1365 return DC_ERROR_UNEXPECTED;
1366
97bda032
HW		 1367 if (pipe_ctx->stream_res.dsc) {
1368 struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
1369
c9ae6e16
NC		 1370 release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
1371 if (odm_pipe)
1372 release_dsc(&new_ctx->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
97bda032 1373 }
7ed4e635
HW		 1374
1375 return DC_OK;
1376}
c9ae6e16
NC		 1377#endif
1378
1379
1380enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1381{
1382 enum dc_status result = DC_ERROR_UNEXPECTED;
1383
1384 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1385
1386 if (result == DC_OK)
1387 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1388
1389#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1390 /* Get a DSC if required and available */
1391 if (result == DC_OK && dc_stream->timing.flags.DSC)
ba32c50f 1392 result = add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
c9ae6e16
NC		 1393#endif
1394
1395 if (result == DC_OK)
1396 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
1397
1398 return result;
1399}
1400
1401
1402enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1403{
1404 enum dc_status result = DC_OK;
1405
1406#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
ba32c50f 1407 result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
c9ae6e16
NC		 1408#endif
1409
1410 return result;
1411}
7ed4e635
HW		 1412
1413
1414static void swizzle_to_dml_params(
1415 enum swizzle_mode_values swizzle,
1416 unsigned int *sw_mode)
1417{
1418 switch (swizzle) {
1419 case DC_SW_LINEAR:
1420 *sw_mode = dm_sw_linear;
1421 break;
1422 case DC_SW_4KB_S:
1423 *sw_mode = dm_sw_4kb_s;
1424 break;
1425 case DC_SW_4KB_S_X:
1426 *sw_mode = dm_sw_4kb_s_x;
1427 break;
1428 case DC_SW_4KB_D:
1429 *sw_mode = dm_sw_4kb_d;
1430 break;
1431 case DC_SW_4KB_D_X:
1432 *sw_mode = dm_sw_4kb_d_x;
1433 break;
1434 case DC_SW_64KB_S:
1435 *sw_mode = dm_sw_64kb_s;
1436 break;
1437 case DC_SW_64KB_S_X:
1438 *sw_mode = dm_sw_64kb_s_x;
1439 break;
1440 case DC_SW_64KB_S_T:
1441 *sw_mode = dm_sw_64kb_s_t;
1442 break;
1443 case DC_SW_64KB_D:
1444 *sw_mode = dm_sw_64kb_d;
1445 break;
1446 case DC_SW_64KB_D_X:
1447 *sw_mode = dm_sw_64kb_d_x;
1448 break;
1449 case DC_SW_64KB_D_T:
1450 *sw_mode = dm_sw_64kb_d_t;
1451 break;
1452 case DC_SW_64KB_R_X:
1453 *sw_mode = dm_sw_64kb_r_x;
1454 break;
1455 case DC_SW_VAR_S:
1456 *sw_mode = dm_sw_var_s;
1457 break;
1458 case DC_SW_VAR_S_X:
1459 *sw_mode = dm_sw_var_s_x;
1460 break;
1461 case DC_SW_VAR_D:
1462 *sw_mode = dm_sw_var_d;
1463 break;
1464 case DC_SW_VAR_D_X:
1465 *sw_mode = dm_sw_var_d_x;
1466 break;
1467
1468 default:
1469 ASSERT(0); /* Not supported */
1470 break;
1471 }
1472}
1473
1474static bool dcn20_split_stream_for_combine(
1475 struct resource_context *res_ctx,
1476 const struct resource_pool *pool,
1477 struct pipe_ctx *primary_pipe,
1478 struct pipe_ctx *secondary_pipe,
1479 bool is_odm_combine)
1480{
1481 int pipe_idx = secondary_pipe->pipe_idx;
1482 struct scaler_data *sd = &primary_pipe->plane_res.scl_data;
1483 struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
1484 int new_width;
1485
1486 *secondary_pipe = *primary_pipe;
1487 secondary_pipe->bottom_pipe = sec_bot_pipe;
1488
1489 secondary_pipe->pipe_idx = pipe_idx;
1490 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
1491 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
1492 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
1493 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
1494 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
1495 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
c92b4c46
NC		 1496#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1497 secondary_pipe->stream_res.dsc = NULL;
1498#endif
7ed4e635
HW		 1499 if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
1500 ASSERT(!secondary_pipe->bottom_pipe);
1501 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
1502 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
1503 }
1504 primary_pipe->bottom_pipe = secondary_pipe;
1505 secondary_pipe->top_pipe = primary_pipe;
1506
1507 if (is_odm_combine) {
7ed4e635
HW		 1508 if (primary_pipe->plane_state) {
1509 /* HACTIVE halved for odm combine */
1510 sd->h_active /= 2;
1511 /* Copy scl_data to secondary pipe */
1512 secondary_pipe->plane_res.scl_data = *sd;
1513
1514 /* Calculate new vp and recout for left pipe */
1515 /* Need at least 16 pixels width per side */
1516 if (sd->recout.x + 16 >= sd->h_active)
1517 return false;
1518 new_width = sd->h_active - sd->recout.x;
1519 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1520 sd->ratios.horz, sd->recout.width - new_width));
1521 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1522 sd->ratios.horz_c, sd->recout.width - new_width));
1523 sd->recout.width = new_width;
1524
1525 /* Calculate new vp and recout for right pipe */
1526 sd = &secondary_pipe->plane_res.scl_data;
1527 new_width = sd->recout.width + sd->recout.x - sd->h_active;
1528 /* Need at least 16 pixels width per side */
1529 if (new_width <= 16)
1530 return false;
1531 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1532 sd->ratios.horz, sd->recout.width - new_width));
1533 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1534 sd->ratios.horz_c, sd->recout.width - new_width));
1535 sd->recout.width = new_width;
1536 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
1537 sd->ratios.horz, sd->h_active - sd->recout.x));
1538 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
1539 sd->ratios.horz_c, sd->h_active - sd->recout.x));
1540 sd->recout.x = 0;
1541 }
1542 secondary_pipe->stream_res.opp = pool->opps[secondary_pipe->pipe_idx];
97bda032 1543#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
c9ae6e16
NC		 1544 if (secondary_pipe->stream->timing.flags.DSC == 1) {
1545 acquire_dsc(res_ctx, pool, &secondary_pipe->stream_res.dsc);
97bda032
HW		 1546 ASSERT(secondary_pipe->stream_res.dsc);
1547 if (secondary_pipe->stream_res.dsc == NULL)
1548 return false;
1549 }
1550#endif
7ed4e635
HW		 1551 } else {
1552 ASSERT(primary_pipe->plane_state);
1553 resource_build_scaling_params(primary_pipe);
1554 resource_build_scaling_params(secondary_pipe);
1555 }
1556
1557 return true;
1558}
1559
1560void dcn20_populate_dml_writeback_from_context(
1561 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1562{
1563 int pipe_cnt, i;
1564
1565 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1566 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];
1567
1568 if (!res_ctx->pipe_ctx[i].stream)
1569 continue;
1570
1571 /* Set writeback information */
1572 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
1573 pipes[pipe_cnt].dout.num_active_wb++;
1574 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
1575 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
1576 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
1577 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
1578 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
1579 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1;
1580 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
1581 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
1582 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0;
1583 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0;
1584 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
1585 if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
1586 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
1587 else
1588 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
1589 } else
1590 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
1591
1592 pipe_cnt++;
1593 }
1594
1595}
1596
1597int dcn20_populate_dml_pipes_from_context(
1598 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1599{
1600 int pipe_cnt, i;
1601 bool synchronized_vblank = true;
1602
1603 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
1604 if (!res_ctx->pipe_ctx[i].stream)
1605 continue;
1606
1607 if (pipe_cnt < 0) {
1608 pipe_cnt = i;
1609 continue;
1610 }
1611 if (!resource_are_streams_timing_synchronizable(
1612 res_ctx->pipe_ctx[pipe_cnt].stream,
1613 res_ctx->pipe_ctx[i].stream)) {
1614 synchronized_vblank = false;
1615 break;
1616 }
1617 }
1618
1619 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1620 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
03fd87db 1621 int output_bpc;
7ed4e635
HW		 1622
1623 if (!res_ctx->pipe_ctx[i].stream)
1624 continue;
1625 /* todo:
1626 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
1627 pipes[pipe_cnt].pipe.src.dcc = 0;
1628 pipes[pipe_cnt].pipe.src.vm = 0;*/
1629
97bda032
HW		 1630#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1631 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
1632 /* todo: rotation?*/
1633 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
1634#endif
7ed4e635
HW		 1635 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
1636 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
1637 /* 1/2 vblank */
1638 pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
1639 (timing->v_total - timing->v_addressable
1640 - timing->v_border_top - timing->v_border_bottom) / 2;
1641 /* 36 bytes dp, 32 hdmi */
1642 pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
1643 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
1644 }
1645 pipes[pipe_cnt].pipe.src.dcc = false;
1646 pipes[pipe_cnt].pipe.src.dcc_rate = 1;
1647 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
1648 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
1649 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
1650 - timing->h_addressable
1651 - timing->h_border_left
1652 - timing->h_border_right;
1653 pipes[pipe_cnt].pipe.dest.vblank_start = timing->v_total - timing->v_front_porch;
1654 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
1655 - timing->v_addressable
1656 - timing->v_border_top
1657 - timing->v_border_bottom;
1658 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
1659 pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total;
1660 pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable;
1661 pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable;
1662 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
1663 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
1664 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1665 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
1666 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
1621f4c4 1667 pipes[pipe_cnt].dout.dp_lanes = 4;
8bb3d7e7
CL		 1668 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
1669 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
7ed4e635 1670
7ed4e635
HW		 1671 switch (res_ctx->pipe_ctx[i].stream->signal) {
1672 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1673 case SIGNAL_TYPE_DISPLAY_PORT:
1674 pipes[pipe_cnt].dout.output_type = dm_dp;
1675 break;
1676 case SIGNAL_TYPE_EDP:
1677 pipes[pipe_cnt].dout.output_type = dm_edp;
1678 break;
1679 case SIGNAL_TYPE_HDMI_TYPE_A:
1680 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1681 case SIGNAL_TYPE_DVI_DUAL_LINK:
1682 pipes[pipe_cnt].dout.output_type = dm_hdmi;
1683 break;
1684 default:
1685 /* In case there is no signal, set dp with 4 lanes to allow max config */
1686 pipes[pipe_cnt].dout.output_type = dm_dp;
1687 pipes[pipe_cnt].dout.dp_lanes = 4;
1688 }
03fd87db
IB		 1689
1690 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
1691 case COLOR_DEPTH_666:
1692 output_bpc = 6;
1693 break;
1694 case COLOR_DEPTH_888:
1695 output_bpc = 8;
1696 break;
1697 case COLOR_DEPTH_101010:
1698 output_bpc = 10;
1699 break;
1700 case COLOR_DEPTH_121212:
1701 output_bpc = 12;
1702 break;
1703 case COLOR_DEPTH_141414:
1704 output_bpc = 14;
1705 break;
1706 case COLOR_DEPTH_161616:
1707 output_bpc = 16;
1708 break;
1709#ifdef CONFIG_DRM_AMD_DC_DCN2_0
1710 case COLOR_DEPTH_999:
1711 output_bpc = 9;
1712 break;
1713 case COLOR_DEPTH_111111:
1714 output_bpc = 11;
1715 break;
1716#endif
1717 default:
1718 output_bpc = 8;
1719 break;
1720 }
1721
1722
7ed4e635
HW		 1723 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
1724 case PIXEL_ENCODING_RGB:
1725 case PIXEL_ENCODING_YCBCR444:
1726 pipes[pipe_cnt].dout.output_format = dm_444;
03fd87db 1727 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
7ed4e635
HW		 1728 break;
1729 case PIXEL_ENCODING_YCBCR420:
1730 pipes[pipe_cnt].dout.output_format = dm_420;
03fd87db 1731 pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3) / 2;
7ed4e635
HW		 1732 break;
1733 case PIXEL_ENCODING_YCBCR422:
1734 if (true) /* todo */
1735 pipes[pipe_cnt].dout.output_format = dm_s422;
1736 else
1737 pipes[pipe_cnt].dout.output_format = dm_n422;
03fd87db 1738 pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
7ed4e635
HW		 1739 break;
1740 default:
1741 pipes[pipe_cnt].dout.output_format = dm_444;
03fd87db 1742 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
7ed4e635
HW		 1743 }
1744 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1745 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
1746 == res_ctx->pipe_ctx[i].plane_state)
1747 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
1748
1749 /* todo: default max for now, until there is logic reflecting this in dc*/
1750 pipes[pipe_cnt].dout.output_bpc = 12;
1751 /*
1752 * Use max cursor settings for calculations to minimize
1753 * bw calculations due to cursor on/off
1754 */
1755 pipes[pipe_cnt].pipe.src.num_cursors = 2;
ed07237c
IB		 1756 pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
1757 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
1758 pipes[pipe_cnt].pipe.src.cur1_src_width = 256;
1759 pipes[pipe_cnt].pipe.src.cur1_bpp = dm_cur_32bit;
7ed4e635
HW		 1760
1761 if (!res_ctx->pipe_ctx[i].plane_state) {
1762 pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
1763 pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear;
1764 pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
1765 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
1766 if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
1767 pipes[pipe_cnt].pipe.src.viewport_width = 1920;
1768 pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
1769 if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
1770 pipes[pipe_cnt].pipe.src.viewport_height = 1080;
1771 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */
1772 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
1773 pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
1774 pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/
1775 pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_hsplit != 1*/
1776 pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/
1777 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
1778 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
1779 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
1780 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
1781 pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
1782 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
1783 pipes[pipe_cnt].pipe.src.is_hsplit = 0;
1784 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
8bb3d7e7
CL		 1785 pipes[pipe_cnt].pipe.dest.vtotal_min = timing->v_total;
1786 pipes[pipe_cnt].pipe.dest.vtotal_max = timing->v_total;
7ed4e635
HW		 1787 } else {
1788 struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
1789 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
1790
7ed4e635
HW		 1791 pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
1792 pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe
1793 && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
1794 || (res_ctx->pipe_ctx[i].top_pipe
1795 && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln);
1796 pipes[pipe_cnt].pipe.dest.odm_combine = (res_ctx->pipe_ctx[i].bottom_pipe
1797 && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln
1798 && res_ctx->pipe_ctx[i].bottom_pipe->stream_res.opp
1799 != res_ctx->pipe_ctx[i].stream_res.opp)
1800 || (res_ctx->pipe_ctx[i].top_pipe
1801 && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln
1802 && res_ctx->pipe_ctx[i].top_pipe->stream_res.opp
1803 != res_ctx->pipe_ctx[i].stream_res.opp);
1804 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
1805 || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
1806 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
1807 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
1808 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
1809 pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
1810 pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
1811 pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
1812 if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1813 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.video.luma_pitch;
1814 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.video.chroma_pitch;
1815 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.video.meta_pitch_l;
1816 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.video.meta_pitch_c;
1817 } else {
1818 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.grph.surface_pitch;
1819 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.grph.meta_pitch;
1820 }
1821 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
1822 pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
1823 pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
1824 pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
1825 pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
1826 if (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) {
1827 pipes[pipe_cnt].pipe.dest.full_recout_width +=
1828 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.width;
1829 pipes[pipe_cnt].pipe.dest.full_recout_height +=
1830 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.height;
1831 } else if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) {
1832 pipes[pipe_cnt].pipe.dest.full_recout_width +=
1833 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.width;
1834 pipes[pipe_cnt].pipe.dest.full_recout_height +=
1835 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.height;
1836 }
1837
ed07237c 1838 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
7ed4e635
HW		 1839 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
1840 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
1841 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
1842 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
1843 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
1844 scl->ratios.vert.value != dc_fixpt_one.value
1845 || scl->ratios.horz.value != dc_fixpt_one.value
1846 || scl->ratios.vert_c.value != dc_fixpt_one.value
1847 || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/
1848 || dc->debug.always_scale; /*support always scale*/
1849 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
1850 pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
1851 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
1852 pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
1853
b964e790
DL		 1854 pipes[pipe_cnt].pipe.src.macro_tile_size =
1855 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
7ed4e635
HW		 1856 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
1857 &pipes[pipe_cnt].pipe.src.sw_mode);
1858
1859 switch (pln->format) {
1860 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
1861 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
1862 pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
1863 break;
1864 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
1865 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
1866 pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
1867 break;
1868 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1869 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1870 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1871 pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
1872 break;
1873 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
1874 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
1875 pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
1876 break;
1877 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
1878 pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
1879 break;
1880 default:
1881 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
1882 break;
1883 }
1884 }
1885
1886 pipe_cnt++;
1887 }
1888
1889 /* populate writeback information */
1890 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
1891
1892 return pipe_cnt;
1893}
1894
1895unsigned int dcn20_calc_max_scaled_time(
1896 unsigned int time_per_pixel,
1897 enum mmhubbub_wbif_mode mode,
1898 unsigned int urgent_watermark)
1899{
1900 unsigned int time_per_byte = 0;
1901 unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */
1902 unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */
1903 unsigned int small_free_entry, max_free_entry;
1904 unsigned int buf_lh_capability;
1905 unsigned int max_scaled_time;
1906
1907 if (mode == PACKED_444) /* packed mode */
1908 time_per_byte = time_per_pixel/4;
1909 else if (mode == PLANAR_420_8BPC)
1910 time_per_byte = time_per_pixel;
1911 else if (mode == PLANAR_420_10BPC) /* p010 */
1912 time_per_byte = time_per_pixel * 819/1024;
1913
1914 if (time_per_byte == 0)
1915 time_per_byte = 1;
1916
1917 small_free_entry = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry;
1918 max_free_entry = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;
1919 buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */
1920 max_scaled_time = buf_lh_capability - urgent_watermark;
1921 return max_scaled_time;
1922}
1923
1924void dcn20_set_mcif_arb_params(
1925 struct dc *dc,
1926 struct dc_state *context,
1927 display_e2e_pipe_params_st *pipes,
1928 int pipe_cnt)
1929{
1930 enum mmhubbub_wbif_mode wbif_mode;
1931 struct mcif_arb_params *wb_arb_params;
1932 int i, j, k, dwb_pipe;
1933
1934 /* Writeback MCIF_WB arbitration parameters */
1935 dwb_pipe = 0;
1936 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1937
1938 if (!context->res_ctx.pipe_ctx[i].stream)
1939 continue;
1940
1941 for (j = 0; j < MAX_DWB_PIPES; j++) {
1942 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)
1943 continue;
1944
1945 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
1946 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
1947
1948 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {
1949 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
1950 wbif_mode = PLANAR_420_8BPC;
1951 else
1952 wbif_mode = PLANAR_420_10BPC;
1953 } else
1954 wbif_mode = PACKED_444;
1955
1956 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
1957 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1958 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1959 }
1960 wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* 4 bit fraction, ms */
1961 wb_arb_params->slice_lines = 32;
1962 wb_arb_params->arbitration_slice = 2;
1963 wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
1964 wbif_mode,
1965 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
1966
1967 dwb_pipe++;
1968
1969 if (dwb_pipe >= MAX_DWB_PIPES)
1970 return;
1971 }
1972 if (dwb_pipe >= MAX_DWB_PIPES)
1973 return;
1974 }
1975}
1976
0ba37b20
DL		 1977#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1978static bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
1979{
1980 int i;
1981
1982 /* Validate DSC config, dsc count validation is already done */
1983 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1984 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1985 struct dc_stream_state *stream = pipe_ctx->stream;
1986 struct dsc_config dsc_cfg;
1987
1988 /* Only need to validate top pipe */
1989 if (pipe_ctx->top_pipe || !stream || !stream->timing.flags.DSC)
1990 continue;
1991
1992 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left
1993 + stream->timing.h_border_right;
1994 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
1995 + stream->timing.v_border_bottom;
1996 if (dc_res_get_odm_bottom_pipe(pipe_ctx))
1997 dsc_cfg.pic_width /= 2;
1998 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
1999 dsc_cfg.color_depth = stream->timing.display_color_depth;
2000 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
2001
2002 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
2003 return false;
2004 }
2005 return true;
2006}
2007#endif
2008
254eb07c
JA		 2009bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
2010 bool fast_validate)
7ed4e635 2011{
254eb07c
JA		 2012 bool out = false;
2013
42351c66
JA		 2014 BW_VAL_TRACE_SETUP();
2015
7ed4e635
HW		 2016 int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit;
2017 int pipe_split_from[MAX_PIPES];
2018 bool odm_capable = context->bw_ctx.dml.ip.odm_capable;
2019 bool force_split = false;
0ba37b20
DL		 2020#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2021 bool failed_non_odm_dsc = false;
2022#endif
7ed4e635
HW		 2023 int split_threshold = dc->res_pool->pipe_count / 2;
2024 bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
2025 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
00999d99 2026 DC_LOGGER_INIT(dc->ctx->logger);
7ed4e635 2027
42351c66
JA		 2028 BW_VAL_TRACE_COUNT();
2029
7ed4e635
HW		 2030 ASSERT(pipes);
2031 if (!pipes)
2032 return false;
2033
2034 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2035 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2036 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2037
2038 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
2039 continue;
2040
2041 /* merge previously split pipe since mode support needs to make the decision */
2042 pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
2043 if (hsplit_pipe->bottom_pipe)
2044 hsplit_pipe->bottom_pipe->top_pipe = pipe;
2045 hsplit_pipe->plane_state = NULL;
2046 hsplit_pipe->stream = NULL;
2047 hsplit_pipe->top_pipe = NULL;
2048 hsplit_pipe->bottom_pipe = NULL;
97bda032
HW		 2049#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2050 if (hsplit_pipe->stream_res.dsc && hsplit_pipe->stream_res.dsc != pipe->stream_res.dsc)
c9ae6e16 2051 release_dsc(&context->res_ctx, dc->res_pool, &hsplit_pipe->stream_res.dsc);
97bda032 2052#endif
7ed4e635
HW		 2053 /* Clear plane_res and stream_res */
2054 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
2055 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
2056 if (pipe->plane_state)
2057 resource_build_scaling_params(pipe);
2058 }
2059
ed07237c
IB		 2060 if (dc->res_pool->funcs->populate_dml_pipes)
2061 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2062 &context->res_ctx, pipes);
2063 else
2064 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
2065 &context->res_ctx, pipes);
254eb07c
JA		 2066
2067 if (!pipe_cnt) {
42351c66 2068 BW_VAL_TRACE_SKIP(pass);
254eb07c
JA		 2069 out = true;
2070 goto validate_out;
2071 }
7ed4e635
HW		 2072
2073 context->bw_ctx.dml.ip.odm_capable = 0;
254eb07c 2074
7ed4e635 2075 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
254eb07c 2076
7ed4e635
HW		 2077 context->bw_ctx.dml.ip.odm_capable = odm_capable;
2078
0ba37b20
DL		 2079#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2080 /* 1 dsc per stream dsc validation */
2081 if (vlevel <= context->bw_ctx.dml.soc.num_states)
2082 if (!dcn20_validate_dsc(dc, context)) {
2083 failed_non_odm_dsc = true;
2084 vlevel = context->bw_ctx.dml.soc.num_states + 1;
2085 }
2086#endif
2087
7ed4e635
HW		 2088 if (vlevel > context->bw_ctx.dml.soc.num_states && odm_capable)
2089 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2090
2091 if (vlevel > context->bw_ctx.dml.soc.num_states)
2092 goto validate_fail;
2093
2094 if ((context->stream_count > split_threshold && dc->current_state->stream_count <= split_threshold)
2095 || (context->stream_count <= split_threshold && dc->current_state->stream_count > split_threshold))
2096 context->commit_hints.full_update_needed = true;
2097
2098 /*initialize pipe_just_split_from to invalid idx*/
2099 for (i = 0; i < MAX_PIPES; i++)
2100 pipe_split_from[i] = -1;
2101
2102 /* Single display only conditionals get set here */
2103 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2104 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2105 bool exit_loop = false;
2106
2107 if (!pipe->stream || pipe->top_pipe)
2108 continue;
2109
2110 if (dc->debug.force_single_disp_pipe_split) {
2111 if (!force_split)
2112 force_split = true;
2113 else {
2114 force_split = false;
2115 exit_loop = true;
2116 }
2117 }
2118 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP) {
2119 if (avoid_split)
2120 avoid_split = false;
2121 else {
2122 avoid_split = true;
2123 exit_loop = true;
2124 }
2125 }
2126 if (exit_loop)
2127 break;
2128 }
2129
2130 if (context->stream_count > split_threshold)
2131 avoid_split = true;
2132
2133 vlevel_unsplit = vlevel;
2134 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2135 if (!context->res_ctx.pipe_ctx[i].stream)
2136 continue;
2137 for (; vlevel_unsplit <= context->bw_ctx.dml.soc.num_states; vlevel_unsplit++)
2138 if (context->bw_ctx.dml.vba.NoOfDPP[vlevel_unsplit][0][pipe_idx] == 1)
2139 break;
2140 pipe_idx++;
2141 }
2142
2143 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2144 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2145 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2146 bool need_split = true;
2147 bool need_split3d;
2148
2149 if (!pipe->stream || pipe_split_from[i] >= 0)
2150 continue;
2151
2152 pipe_idx++;
2153
2154 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
2155 force_split = true;
2156 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx] = true;
2157 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = true;
2158 }
2159 if (force_split && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)
2160 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
a6465d1f
CL		 2161 if (dc->config.forced_clocks == true) {
2162 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] =
2163 context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2164 }
7ed4e635
HW		 2165 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2166 hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, dc->res_pool, pipe);
2167 ASSERT(hsplit_pipe);
2168 if (!dcn20_split_stream_for_combine(
2169 &context->res_ctx, dc->res_pool,
2170 pipe, hsplit_pipe,
2171 true))
2172 goto validate_fail;
2173 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2174 dcn20_build_mapped_resource(dc, context, pipe->stream);
2175 }
2176
2177 if (!pipe->plane_state)
2178 continue;
2179 /* Skip 2nd half of already split pipe */
2180 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
2181 continue;
2182
2183 need_split3d = ((pipe->stream->view_format ==
2184 VIEW_3D_FORMAT_SIDE_BY_SIDE ||
2185 pipe->stream->view_format ==
2186 VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
2187 (pipe->stream->timing.timing_3d_format ==
2188 TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
2189 pipe->stream->timing.timing_3d_format ==
2190 TIMING_3D_FORMAT_SIDE_BY_SIDE));
2191
2192 if (avoid_split && vlevel_unsplit <= context->bw_ctx.dml.soc.num_states && !force_split && !need_split3d) {
2193 need_split = false;
2194 vlevel = vlevel_unsplit;
2195 context->bw_ctx.dml.vba.maxMpcComb = 0;
2196 } else
be67de35 2197 need_split = context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 2;
7ed4e635 2198
02ce5a79
DL		 2199 /* We do not support mpo + odm at the moment */
2200 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
2201 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
2202 goto validate_fail;
2203
7ed4e635
HW		 2204 if (need_split3d || need_split || force_split) {
2205 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
2206 /* pipe not split previously needs split */
2207 hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, dc->res_pool, pipe);
2208 ASSERT(hsplit_pipe || force_split);
2209 if (!hsplit_pipe)
2210 continue;
2211
2212 if (!dcn20_split_stream_for_combine(
2213 &context->res_ctx, dc->res_pool,
2214 pipe, hsplit_pipe,
2215 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]))
2216 goto validate_fail;
2217 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2218 }
02ce5a79 2219 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
7ed4e635
HW		 2220 /* merge should already have been done */
2221 ASSERT(0);
2222 }
2223 }
0ba37b20
DL		 2224#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2225 /* Actual dsc count per stream dsc validation*/
2226 if (failed_non_odm_dsc && !dcn20_validate_dsc(dc, context)) {
2227 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2228 DML_FAIL_DSC_VALIDATION_FAILURE;
2229 goto validate_fail;
2230 }
2231#endif
7ed4e635 2232
42351c66
JA		 2233 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2234
254eb07c 2235 if (fast_validate) {
42351c66 2236 BW_VAL_TRACE_SKIP(fast);
254eb07c
JA		 2237 out = true;
2238 goto validate_out;
2239 }
2240
7ed4e635
HW		 2241 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2242 if (!context->res_ctx.pipe_ctx[i].stream)
2243 continue;
2244
2245 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2246 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2247
2248 if (pipe_split_from[i] < 0) {
2249 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2250 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
2251 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
2252 pipes[pipe_cnt].pipe.dest.odm_combine =
2253 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
2254 else
2255 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2256 pipe_idx++;
2257 } else {
2258 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2259 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
2260 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
2261 pipes[pipe_cnt].pipe.dest.odm_combine =
2262 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_split_from[i]];
2263 else
2264 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2265 }
a6465d1f
CL		 2266 if (dc->config.forced_clocks) {
2267 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2268 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2269 }
7ed4e635
HW		 2270 pipe_cnt++;
2271 }
2272
ed07237c
IB		 2273 if (pipe_cnt != pipe_idx) {
2274 if (dc->res_pool->funcs->populate_dml_pipes)
2275 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2276 &context->res_ctx, pipes);
2277 else
2278 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
2279 &context->res_ctx, pipes);
2280 }
7ed4e635 2281
8e27a2d4
IB		 2282 pipes[0].clks_cfg.voltage = vlevel;
2283 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2284 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2285
7ed4e635
HW		 2286 /* only pipe 0 is read for voltage and dcf/soc clocks */
2287 if (vlevel < 1) {
2288 pipes[0].clks_cfg.voltage = 1;
2289 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
2290 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
2291 }
2292 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2293 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2294 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2295 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2296 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2297
2298 if (vlevel < 2) {
2299 pipes[0].clks_cfg.voltage = 2;
2300 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2301 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2302 }
2303 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2304 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2305 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2306 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2307 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2308
2309 if (vlevel < 3) {
2310 pipes[0].clks_cfg.voltage = 3;
2311 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2312 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2313 }
2314 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2315 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2316 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2317 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2318 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2319
2320 pipes[0].clks_cfg.voltage = vlevel;
2321 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2322 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2323 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2324 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2325 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2326 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2327 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2328 /* Writeback MCIF_WB arbitration parameters */
2329 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
2330
2331 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
2332 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
2333 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
173932de 2334 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
7ed4e635
HW		 2335 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
2336 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
2337 context->bw_ctx.bw.dcn.clk.p_state_change_support =
2338 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
2339 != dm_dram_clock_change_unsupported;
2340 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
2341
42351c66
JA		 2342 BW_VAL_TRACE_END_WATERMARKS();
2343
7ed4e635
HW		 2344 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2345 if (!context->res_ctx.pipe_ctx[i].stream)
2346 continue;
2347 pipes[pipe_idx].pipe.dest.vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx];
2348 pipes[pipe_idx].pipe.dest.vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx];
2349 pipes[pipe_idx].pipe.dest.vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx];
2350 pipes[pipe_idx].pipe.dest.vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx];
2351 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2352 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
2353 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
2354 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
97bda032 2355#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
b7d39c58 2356 context->res_ctx.pipe_ctx[i].stream_res.dscclk_khz =
97bda032
HW		 2357 context->bw_ctx.dml.vba.DSCCLK_calculated[pipe_idx] * 1000;
2358#endif
7ed4e635
HW		 2359 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
2360 pipe_idx++;
2361 }
2362
2363 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2364 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
2365
2366 if (!context->res_ctx.pipe_ctx[i].stream)
2367 continue;
2368
2369 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
2370 &context->res_ctx.pipe_ctx[i].dlg_regs,
2371 &context->res_ctx.pipe_ctx[i].ttu_regs,
2372 pipes,
2373 pipe_cnt,
2374 pipe_idx,
2375 cstate_en,
f82c916c
CL		 2376 context->bw_ctx.bw.dcn.clk.p_state_change_support,
2377 false, false, false);
254eb07c 2378
7ed4e635
HW		 2379 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
2380 &context->res_ctx.pipe_ctx[i].rq_regs,
2381 pipes[pipe_idx].pipe);
2382 pipe_idx++;
2383 }
2384
254eb07c
JA		 2385 out = true;
2386 goto validate_out;
7ed4e635
HW		 2387
2388validate_fail:
00999d99
DL		 2389 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2390 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
254eb07c 2391
42351c66 2392 BW_VAL_TRACE_SKIP(fail);
254eb07c
JA		 2393 out = false;
2394
2395validate_out:
7ed4e635 2396 kfree(pipes);
254eb07c 2397
42351c66
JA		 2398 BW_VAL_TRACE_FINISH();
2399
254eb07c 2400 return out;
7ed4e635
HW		 2401}
2402
7ed4e635
HW		 2403struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
2404 struct dc_state *state,
2405 const struct resource_pool *pool,
2406 struct dc_stream_state *stream)
2407{
2408 struct resource_context *res_ctx = &state->res_ctx;
2409 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
2410 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
2411
2412 if (!head_pipe)
2413 ASSERT(0);
2414
2415 if (!idle_pipe)
2416 return false;
2417
2418 idle_pipe->stream = head_pipe->stream;
2419 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
2420 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
2421
2422 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
2423 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
2424 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
2425 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
2426
2427 return idle_pipe;
2428}
2429
2430bool dcn20_get_dcc_compression_cap(const struct dc *dc,
2431 const struct dc_dcc_surface_param *input,
2432 struct dc_surface_dcc_cap *output)
2433{
2434 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
2435 dc->res_pool->hubbub,
2436 input,
2437 output);
2438}
2439
2440static void dcn20_destroy_resource_pool(struct resource_pool **pool)
2441{
2442 struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);
2443
2444 destruct(dcn20_pool);
2445 kfree(dcn20_pool);
2446 *pool = NULL;
2447}
2448
2449
2450static struct dc_cap_funcs cap_funcs = {
2451 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
2452};
2453
2454
2455enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state)
2456{
2457 enum dc_status result = DC_OK;
2458
2459 enum surface_pixel_format surf_pix_format = plane_state->format;
2460 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
2461
2462 enum swizzle_mode_values swizzle = DC_SW_LINEAR;
2463
2464 if (bpp == 64)
2465 swizzle = DC_SW_64KB_D;
2466 else
2467 swizzle = DC_SW_64KB_S;
2468
2469 plane_state->tiling_info.gfx9.swizzle = swizzle;
2470 return result;
2471}
2472
2473static struct resource_funcs dcn20_res_pool_funcs = {
2474 .destroy = dcn20_destroy_resource_pool,
2475 .link_enc_create = dcn20_link_encoder_create,
2476 .validate_bandwidth = dcn20_validate_bandwidth,
7ed4e635
HW		 2477 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
2478 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
2479 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2480 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
2481 .get_default_swizzle_mode = dcn20_get_default_swizzle_mode,
c9ae6e16 2482 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
278141f5 2483 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
7ed4e635
HW		 2484};
2485
bb21290f
CL		 2486bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
2487{
2488 int i;
2489 uint32_t pipe_count = pool->res_cap->num_dwb;
2490
2491 ASSERT(pipe_count > 0);
2492
2493 for (i = 0; i < pipe_count; i++) {
2494 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
2495 GFP_KERNEL);
2496
2497 if (!dwbc20) {
2498 dm_error("DC: failed to create dwbc20!\n");
2499 return false;
2500 }
2501 dcn20_dwbc_construct(dwbc20, ctx,
2502 &dwbc20_regs[i],
2503 &dwbc20_shift,
2504 &dwbc20_mask,
2505 i);
2506 pool->dwbc[i] = &dwbc20->base;
2507 }
2508 return true;
2509}
2510
2511bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
2512{
2513 int i;
2514 uint32_t pipe_count = pool->res_cap->num_dwb;
2515
2516 ASSERT(pipe_count > 0);
2517
2518 for (i = 0; i < pipe_count; i++) {
2519 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub),
2520 GFP_KERNEL);
2521
2522 if (!mcif_wb20) {
2523 dm_error("DC: failed to create mcif_wb20!\n");
2524 return false;
2525 }
2526
2527 dcn20_mmhubbub_construct(mcif_wb20, ctx,
2528 &mcif_wb20_regs[i],
2529 &mcif_wb20_shift,
2530 &mcif_wb20_mask,
2531 i);
2532
2533 pool->mcif_wb[i] = &mcif_wb20->base;
2534 }
2535 return true;
2536}
2537
7ed4e635
HW		 2538struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
2539{
2540 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
2541
2542 if (!pp_smu)
2543 return pp_smu;
2544
2545 dm_pp_get_funcs(ctx, pp_smu);
2546
2547 if (pp_smu->ctx.ver != PP_SMU_VER_NV)
2548 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
2549
2550 return pp_smu;
2551}
2552
2553void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
2554{
2555 if (pp_smu && *pp_smu) {
2556 kfree(*pp_smu);
2557 *pp_smu = NULL;
2558 }
2559}
2560
2561static void cap_soc_clocks(
2562 struct _vcs_dpi_soc_bounding_box_st *bb,
2563 struct pp_smu_nv_clock_table max_clocks)
2564{
2565 int i;
2566
2567 // First pass - cap all clocks higher than the reported max
2568 for (i = 0; i < bb->num_states; i++) {
2569 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
2570 && max_clocks.dcfClockInKhz != 0)
2571 bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
2572
2573 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
2574 && max_clocks.uClockInKhz != 0)
2575 bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
2576
2577 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
2578 && max_clocks.fabricClockInKhz != 0)
2579 bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
2580
2581 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
2582 && max_clocks.displayClockInKhz != 0)
2583 bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
2584
2585 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
2586 && max_clocks.dppClockInKhz != 0)
2587 bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
2588
2589 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
2590 && max_clocks.phyClockInKhz != 0)
2591 bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
2592
2593 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
2594 && max_clocks.socClockInKhz != 0)
2595 bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
2596
2597 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
2598 && max_clocks.dscClockInKhz != 0)
2599 bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
2600 }
2601
2602 // Second pass - remove all duplicate clock states
2603 for (i = bb->num_states - 1; i > 1; i--) {
2604 bool duplicate = true;
2605
2606 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz)
2607 duplicate = false;
2608 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz)
2609 duplicate = false;
2610 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz)
2611 duplicate = false;
2612 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts)
2613 duplicate = false;
2614 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz)
2615 duplicate = false;
2616 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz)
2617 duplicate = false;
2618 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz)
2619 duplicate = false;
2620 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz)
2621 duplicate = false;
2622
2623 if (duplicate)
2624 bb->num_states--;
2625 }
2626}
2627
2628static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
2629 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
2630{
2631 struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES] = {0};
f18bc4e5 2632 int i;
7ed4e635 2633 int num_calculated_states = 0;
f18bc4e5 2634 int min_dcfclk = 0;
7ed4e635
HW		 2635
2636 if (num_states == 0)
2637 return;
2638
f18bc4e5
JL		 2639 if (dc->bb_overrides.min_dcfclk_mhz > 0)
2640 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
2641
7ed4e635 2642 for (i = 0; i < num_states; i++) {
f18bc4e5
JL		 2643 int min_fclk_required_by_uclk;
2644 calculated_states[i].state = i;
2645 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
7ed4e635 2646
5d36f783
JL		 2647 // FCLK:UCLK ratio is 1.08
2648 min_fclk_required_by_uclk = ((unsigned long long)uclk_states[i]) * 1080 / 1000000;
7ed4e635 2649
f18bc4e5
JL		 2650 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
2651 min_dcfclk : min_fclk_required_by_uclk;
7ed4e635 2652
f18bc4e5
JL		 2653 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
2654 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
7ed4e635 2655
f18bc4e5
JL		 2656 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
2657 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
7ed4e635 2658
f18bc4e5
JL		 2659 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
2660 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
2661 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
7ed4e635 2662
f18bc4e5 2663 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
7ed4e635 2664
f18bc4e5 2665 num_calculated_states++;
7ed4e635
HW		 2666 }
2667
7ed4e635
HW		 2668 memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
2669 bb->num_states = num_calculated_states;
f18bc4e5
JL		 2670
2671 // Duplicate the last state, DML always an extra state identical to max state to work
2672 memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st));
2673 bb->clock_limits[num_calculated_states].state = bb->num_states;
7ed4e635
HW		 2674}
2675
2676static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
2677{
2678 kernel_fpu_begin();
2679 if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
2680 && dc->bb_overrides.sr_exit_time_ns) {
2681 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
2682 }
2683
2684 if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
2685 != dc->bb_overrides.sr_enter_plus_exit_time_ns
2686 && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
2687 bb->sr_enter_plus_exit_time_us =
2688 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
2689 }
2690
2691 if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
2692 && dc->bb_overrides.urgent_latency_ns) {
2693 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
2694 }
2695
2696 if ((int)(bb->dram_clock_change_latency_us * 1000)
2697 != dc->bb_overrides.dram_clock_change_latency_ns
2698 && dc->bb_overrides.dram_clock_change_latency_ns) {
2699 bb->dram_clock_change_latency_us =
2700 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
2701 }
2702 kernel_fpu_end();
2703}
2704
2705#define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
2706#define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
2707
2708static bool init_soc_bounding_box(struct dc *dc,
2709 struct dcn20_resource_pool *pool)
2710{
2711 const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
2712 DC_LOGGER_INIT(dc->ctx->logger);
2713
2714 if (!bb && !SOC_BOUNDING_BOX_VALID) {
2715 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
2716 return false;
2717 }
2718
2719 if (bb && !SOC_BOUNDING_BOX_VALID) {
2720 int i;
2721
2722 dcn2_0_soc.sr_exit_time_us =
2723 fixed16_to_double_to_cpu(bb->sr_exit_time_us);
2724 dcn2_0_soc.sr_enter_plus_exit_time_us =
2725 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us);
2726 dcn2_0_soc.urgent_latency_us =
2727 fixed16_to_double_to_cpu(bb->urgent_latency_us);
2728 dcn2_0_soc.urgent_latency_pixel_data_only_us =
2729 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us);
2730 dcn2_0_soc.urgent_latency_pixel_mixed_with_vm_data_us =
2731 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us);
2732 dcn2_0_soc.urgent_latency_vm_data_only_us =
2733 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us);
2734 dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
2735 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes);
2736 dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
2737 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes);
2738 dcn2_0_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
2739 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes);
2740 dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
2741 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only);
2742 dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
2743 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm);
2744 dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
2745 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only);
2746 dcn2_0_soc.max_avg_sdp_bw_use_normal_percent =
2747 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent);
2748 dcn2_0_soc.max_avg_dram_bw_use_normal_percent =
2749 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent);
2750 dcn2_0_soc.writeback_latency_us =
2751 fixed16_to_double_to_cpu(bb->writeback_latency_us);
2752 dcn2_0_soc.ideal_dram_bw_after_urgent_percent =
2753 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent);
2754 dcn2_0_soc.max_request_size_bytes =
2755 le32_to_cpu(bb->max_request_size_bytes);
2756 dcn2_0_soc.dram_channel_width_bytes =
2757 le32_to_cpu(bb->dram_channel_width_bytes);
2758 dcn2_0_soc.fabric_datapath_to_dcn_data_return_bytes =
2759 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes);
2760 dcn2_0_soc.dcn_downspread_percent =
2761 fixed16_to_double_to_cpu(bb->dcn_downspread_percent);
2762 dcn2_0_soc.downspread_percent =
2763 fixed16_to_double_to_cpu(bb->downspread_percent);
2764 dcn2_0_soc.dram_page_open_time_ns =
2765 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns);
2766 dcn2_0_soc.dram_rw_turnaround_time_ns =
2767 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns);
2768 dcn2_0_soc.dram_return_buffer_per_channel_bytes =
2769 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes);
2770 dcn2_0_soc.round_trip_ping_latency_dcfclk_cycles =
2771 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles);
2772 dcn2_0_soc.urgent_out_of_order_return_per_channel_bytes =
2773 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes);
2774 dcn2_0_soc.channel_interleave_bytes =
2775 le32_to_cpu(bb->channel_interleave_bytes);
2776 dcn2_0_soc.num_banks =
2777 le32_to_cpu(bb->num_banks);
2778 dcn2_0_soc.num_chans =
2779 le32_to_cpu(bb->num_chans);
2780 dcn2_0_soc.vmm_page_size_bytes =
2781 le32_to_cpu(bb->vmm_page_size_bytes);
2782 dcn2_0_soc.dram_clock_change_latency_us =
2783 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
2784 dcn2_0_soc.writeback_dram_clock_change_latency_us =
2785 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
2786 dcn2_0_soc.return_bus_width_bytes =
2787 le32_to_cpu(bb->return_bus_width_bytes);
2788 dcn2_0_soc.dispclk_dppclk_vco_speed_mhz =
2789 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz);
2790 dcn2_0_soc.xfc_bus_transport_time_us =
2791 le32_to_cpu(bb->xfc_bus_transport_time_us);
2792 dcn2_0_soc.xfc_xbuf_latency_tolerance_us =
2793 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us);
2794 dcn2_0_soc.use_urgent_burst_bw =
2795 le32_to_cpu(bb->use_urgent_burst_bw);
2796 dcn2_0_soc.num_states =
2797 le32_to_cpu(bb->num_states);
2798
2799 for (i = 0; i < dcn2_0_soc.num_states; i++) {
2800 dcn2_0_soc.clock_limits[i].state =
2801 le32_to_cpu(bb->clock_limits[i].state);
2802 dcn2_0_soc.clock_limits[i].dcfclk_mhz =
2803 fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz);
2804 dcn2_0_soc.clock_limits[i].fabricclk_mhz =
2805 fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz);
2806 dcn2_0_soc.clock_limits[i].dispclk_mhz =
2807 fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz);
2808 dcn2_0_soc.clock_limits[i].dppclk_mhz =
2809 fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz);
2810 dcn2_0_soc.clock_limits[i].phyclk_mhz =
2811 fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz);
2812 dcn2_0_soc.clock_limits[i].socclk_mhz =
2813 fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz);
2814 dcn2_0_soc.clock_limits[i].dscclk_mhz =
2815 fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz);
2816 dcn2_0_soc.clock_limits[i].dram_speed_mts =
2817 fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
2818 }
2819 }
2820
2821 if (pool->base.pp_smu) {
2822 struct pp_smu_nv_clock_table max_clocks = {0};
2823 unsigned int uclk_states[8] = {0};
2824 unsigned int num_states = 0;
2825 enum pp_smu_status status;
2826 bool clock_limits_available = false;
2827 bool uclk_states_available = false;
2828
2829 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
2830 status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
2831 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
2832
2833 uclk_states_available = (status == PP_SMU_RESULT_OK);
2834 }
2835
2836 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
2837 status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
2838 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
c2ad17c3
AW		 2839 /* SMU cannot set DCF clock to anything equal to or higher than SOC clock
2840 */
2841 if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
2842 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
7ed4e635
HW		 2843 clock_limits_available = (status == PP_SMU_RESULT_OK);
2844 }
2845
c2ad17c3 2846 if (clock_limits_available && uclk_states_available && num_states)
7ed4e635
HW		 2847 update_bounding_box(dc, &dcn2_0_soc, &max_clocks, uclk_states, num_states);
2848 else if (clock_limits_available)
2849 cap_soc_clocks(&dcn2_0_soc, max_clocks);
2850 }
2851
2852 dcn2_0_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
2853 dcn2_0_ip.max_num_dpp = pool->base.pipe_count;
2854 patch_bounding_box(dc, &dcn2_0_soc);
2855
2856 return true;
2857}
2858
2859static bool construct(
2860 uint8_t num_virtual_links,
2861 struct dc *dc,
2862 struct dcn20_resource_pool *pool)
2863{
2864 int i;
2865 struct dc_context *ctx = dc->ctx;
2866 struct irq_service_init_data init_data;
2867
2868 ctx->dc_bios->regs = &bios_regs;
2869
2870 pool->base.res_cap = &res_cap_nv10;
2871 pool->base.funcs = &dcn20_res_pool_funcs;
2872
2873 /*************************************************
2874 * Resource + asic cap harcoding *
2875 *************************************************/
2876 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2877
2878 pool->base.pipe_count = 6;
2879 pool->base.mpcc_count = 6;
2880 dc->caps.max_downscale_ratio = 200;
2881 dc->caps.i2c_speed_in_khz = 100;
2882 dc->caps.max_cursor_size = 256;
2883 dc->caps.dmdata_alloc_size = 2048;
2884
2885 dc->caps.max_slave_planes = 1;
2886 dc->caps.post_blend_color_processing = true;
2887 dc->caps.force_dp_tps4_for_cp2520 = true;
2888 dc->caps.hw_3d_lut = true;
2889
2890 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2891 dc->debug = debug_defaults_drv;
2892 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2893 pool->base.pipe_count = 4;
2894
2895 pool->base.mpcc_count = pool->base.pipe_count;
2896 dc->debug = debug_defaults_diags;
2897 } else
2898 dc->debug = debug_defaults_diags;
2899 //dcn2.0x
2900 dc->work_arounds.dedcn20_305_wa = true;
2901
2902 // Init the vm_helper
2903 if (dc->vm_helper)
bda9afda 2904 vm_helper_init(dc->vm_helper, 16);
7ed4e635
HW		 2905
2906 /*************************************************
2907 * Create resources *
2908 *************************************************/
2909
2910 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
2911 dcn20_clock_source_create(ctx, ctx->dc_bios,
2912 CLOCK_SOURCE_COMBO_PHY_PLL0,
2913 &clk_src_regs[0], false);
2914 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
2915 dcn20_clock_source_create(ctx, ctx->dc_bios,
2916 CLOCK_SOURCE_COMBO_PHY_PLL1,
2917 &clk_src_regs[1], false);
2918 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
2919 dcn20_clock_source_create(ctx, ctx->dc_bios,
2920 CLOCK_SOURCE_COMBO_PHY_PLL2,
2921 &clk_src_regs[2], false);
2922 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
2923 dcn20_clock_source_create(ctx, ctx->dc_bios,
2924 CLOCK_SOURCE_COMBO_PHY_PLL3,
2925 &clk_src_regs[3], false);
2926 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
2927 dcn20_clock_source_create(ctx, ctx->dc_bios,
2928 CLOCK_SOURCE_COMBO_PHY_PLL4,
2929 &clk_src_regs[4], false);
2930 pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =
2931 dcn20_clock_source_create(ctx, ctx->dc_bios,
2932 CLOCK_SOURCE_COMBO_PHY_PLL5,
2933 &clk_src_regs[5], false);
2934 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;
2935 /* todo: not reuse phy_pll registers */
2936 pool->base.dp_clock_source =
2937 dcn20_clock_source_create(ctx, ctx->dc_bios,
2938 CLOCK_SOURCE_ID_DP_DTO,
2939 &clk_src_regs[0], true);
2940
2941 for (i = 0; i < pool->base.clk_src_count; i++) {
2942 if (pool->base.clock_sources[i] == NULL) {
2943 dm_error("DC: failed to create clock sources!\n");
2944 BREAK_TO_DEBUGGER();
2945 goto create_fail;
2946 }
2947 }
2948
2949 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2950 if (pool->base.dccg == NULL) {
2951 dm_error("DC: failed to create dccg!\n");
2952 BREAK_TO_DEBUGGER();
2953 goto create_fail;
2954 }
2955
2956 pool->base.dmcu = dcn20_dmcu_create(ctx,
2957 &dmcu_regs,
2958 &dmcu_shift,
2959 &dmcu_mask);
2960 if (pool->base.dmcu == NULL) {
2961 dm_error("DC: failed to create dmcu!\n");
2962 BREAK_TO_DEBUGGER();
2963 goto create_fail;
2964 }
2965
d7c29549 2966 pool->base.abm = dce_abm_create(ctx,
7ed4e635
HW		 2967 &abm_regs,
2968 &abm_shift,
2969 &abm_mask);
2970 if (pool->base.abm == NULL) {
2971 dm_error("DC: failed to create abm!\n");
2972 BREAK_TO_DEBUGGER();
2973 goto create_fail;
d7c29549 2974 }
7ed4e635
HW		 2975
2976 pool->base.pp_smu = dcn20_pp_smu_create(ctx);
2977
2978
2979 if (!init_soc_bounding_box(dc, pool)) {
2980 dm_error("DC: failed to initialize soc bounding box!\n");
2981 BREAK_TO_DEBUGGER();
2982 goto create_fail;
2983 }
2984
2985 dml_init_instance(&dc->dml, &dcn2_0_soc, &dcn2_0_ip, DML_PROJECT_NAVI10);
2986
2987 if (!dc->debug.disable_pplib_wm_range) {
2988 struct pp_smu_wm_range_sets ranges = {0};
2989 int i = 0;
2990
2991 ranges.num_reader_wm_sets = 0;
2992
2993 if (dcn2_0_soc.num_states == 1) {
2994 ranges.reader_wm_sets[0].wm_inst = i;
2995 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2996 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2997 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2998 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2999
3000 ranges.num_reader_wm_sets = 1;
3001 } else if (dcn2_0_soc.num_states > 1) {
5d36f783 3002 for (i = 0; i < 4 && i < dcn2_0_soc.num_states; i++) {
7ed4e635
HW		 3003 ranges.reader_wm_sets[i].wm_inst = i;
3004 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3005 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
5d36f783
JL		 3006 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (dcn2_0_soc.clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
3007 ranges.reader_wm_sets[i].max_fill_clk_mhz = dcn2_0_soc.clock_limits[i].dram_speed_mts / 16;
7ed4e635
HW		 3008
3009 ranges.num_reader_wm_sets = i + 1;
3010 }
7ed4e635 3011
5d36f783
JL		 3012 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3013 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3014 }
7ed4e635
HW		 3015
3016 ranges.num_writer_wm_sets = 1;
3017
3018 ranges.writer_wm_sets[0].wm_inst = 0;
3019 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3020 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3021 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3022 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3023
3024 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
3025 if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
3026 pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);
3027 }
3028
3029 init_data.ctx = dc->ctx;
3030 pool->base.irqs = dal_irq_service_dcn20_create(&init_data);
3031 if (!pool->base.irqs)
3032 goto create_fail;
3033
3034 /* mem input -> ipp -> dpp -> opp -> TG */
3035 for (i = 0; i < pool->base.pipe_count; i++) {
3036 pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
3037 if (pool->base.hubps[i] == NULL) {
3038 BREAK_TO_DEBUGGER();
3039 dm_error(
3040 "DC: failed to create memory input!\n");
3041 goto create_fail;
3042 }
3043
3044 pool->base.ipps[i] = dcn20_ipp_create(ctx, i);
3045 if (pool->base.ipps[i] == NULL) {
3046 BREAK_TO_DEBUGGER();
3047 dm_error(
3048 "DC: failed to create input pixel processor!\n");
3049 goto create_fail;
3050 }
3051
3052 pool->base.dpps[i] = dcn20_dpp_create(ctx, i);
3053 if (pool->base.dpps[i] == NULL) {
3054 BREAK_TO_DEBUGGER();
3055 dm_error(
3056 "DC: failed to create dpps!\n");
3057 goto create_fail;
3058 }
3059 }
3060 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
3061 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i);
3062 if (pool->base.engines[i] == NULL) {
3063 BREAK_TO_DEBUGGER();
3064 dm_error(
3065 "DC:failed to create aux engine!!\n");
3066 goto create_fail;
3067 }
3068 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i);
3069 if (pool->base.hw_i2cs[i] == NULL) {
3070 BREAK_TO_DEBUGGER();
3071 dm_error(
3072 "DC:failed to create hw i2c!!\n");
3073 goto create_fail;
3074 }
3075 pool->base.sw_i2cs[i] = NULL;
3076 }
3077
3078 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
3079 pool->base.opps[i] = dcn20_opp_create(ctx, i);
3080 if (pool->base.opps[i] == NULL) {
3081 BREAK_TO_DEBUGGER();
3082 dm_error(
3083 "DC: failed to create output pixel processor!\n");
3084 goto create_fail;
3085 }
3086 }
3087
3088 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
3089 pool->base.timing_generators[i] = dcn20_timing_generator_create(
3090 ctx, i);
3091 if (pool->base.timing_generators[i] == NULL) {
3092 BREAK_TO_DEBUGGER();
3093 dm_error("DC: failed to create tg!\n");
3094 goto create_fail;
3095 }
3096 }
3097
3098 pool->base.timing_generator_count = i;
3099
3100 pool->base.mpc = dcn20_mpc_create(ctx);
3101 if (pool->base.mpc == NULL) {
3102 BREAK_TO_DEBUGGER();
3103 dm_error("DC: failed to create mpc!\n");
3104 goto create_fail;
3105 }
3106
3107 pool->base.hubbub = dcn20_hubbub_create(ctx);
3108 if (pool->base.hubbub == NULL) {
3109 BREAK_TO_DEBUGGER();
3110 dm_error("DC: failed to create hubbub!\n");
3111 goto create_fail;
3112 }
3113
97bda032
HW		 3114#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3115 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
3116 pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
3117 if (pool->base.dscs[i] == NULL) {
3118 BREAK_TO_DEBUGGER();
3119 dm_error("DC: failed to create display stream compressor %d!\n", i);
3120 goto create_fail;
3121 }
3122 }
3123#endif
7ed4e635 3124
bb21290f
CL		 3125 if (!dcn20_dwbc_create(ctx, &pool->base)) {
3126 BREAK_TO_DEBUGGER();
3127 dm_error("DC: failed to create dwbc!\n");
3128 goto create_fail;
3129 }
3130 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
3131 BREAK_TO_DEBUGGER();
3132 dm_error("DC: failed to create mcif_wb!\n");
3133 goto create_fail;
3134 }
3135
7ed4e635
HW		 3136 if (!resource_construct(num_virtual_links, dc, &pool->base,
3137 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
3138 &res_create_funcs : &res_create_maximus_funcs)))
3139 goto create_fail;
3140
3141 dcn20_hw_sequencer_construct(dc);
3142
3143 dc->caps.max_planes = pool->base.pipe_count;
3144
3145 for (i = 0; i < dc->caps.max_planes; ++i)
3146 dc->caps.planes[i] = plane_cap;
3147
3148 dc->cap_funcs = cap_funcs;
3149
3150 return true;
3151
3152create_fail:
3153
3154 destruct(pool);
3155
3156 return false;
3157}
3158
3159struct resource_pool *dcn20_create_resource_pool(
3160 const struct dc_init_data *init_data,
3161 struct dc *dc)
3162{
3163 struct dcn20_resource_pool *pool =
3164 kzalloc(sizeof(struct dcn20_resource_pool), GFP_KERNEL);
3165
3166 if (!pool)
3167 return NULL;
3168
3169 if (construct(init_data->num_virtual_links, dc, pool))
3170 return &pool->base;
3171
3172 BREAK_TO_DEBUGGER();
3173 kfree(pool);
3174 return NULL;
3175}
Linux 6.x block layer and io_uring tree(s)