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amdgpu: Enable initial DCN support on POWER
[linux-block.git] / drivers / gpu / drm / amd / display / dc / dcn20 / dcn20_resource.c
CommitLineData
7ed4e635
HW		 1/*
2* Copyright 2016 Advanced Micro Devices, Inc.
6ca3928d 3 * Copyright 2019 Raptor Engineering, LLC
7ed4e635
HW		 4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
d7929c1e
AD		 27#include <linux/slab.h>
28
7ed4e635
HW		 29#include "dm_services.h"
30#include "dc.h"
31
78c77382
AK		 32#include "dcn20_init.h"
33
7ed4e635
HW		 34#include "resource.h"
35#include "include/irq_service_interface.h"
36#include "dcn20/dcn20_resource.h"
37
38#include "dcn10/dcn10_hubp.h"
39#include "dcn10/dcn10_ipp.h"
40#include "dcn20_hubbub.h"
41#include "dcn20_mpc.h"
42#include "dcn20_hubp.h"
43#include "irq/dcn20/irq_service_dcn20.h"
44#include "dcn20_dpp.h"
45#include "dcn20_optc.h"
46#include "dcn20_hwseq.h"
47#include "dce110/dce110_hw_sequencer.h"
278141f5 48#include "dcn10/dcn10_resource.h"
7ed4e635
HW		 49#include "dcn20_opp.h"
50
97bda032 51#include "dcn20_dsc.h"
97bda032 52
7ed4e635
HW		 53#include "dcn20_link_encoder.h"
54#include "dcn20_stream_encoder.h"
55#include "dce/dce_clock_source.h"
56#include "dce/dce_audio.h"
57#include "dce/dce_hwseq.h"
58#include "virtual/virtual_stream_encoder.h"
59#include "dce110/dce110_resource.h"
60#include "dml/display_mode_vba.h"
61#include "dcn20_dccg.h"
62#include "dcn20_vmid.h"
d9a07577 63#include "dc_link_ddc.h"
7ed4e635
HW		 64
65#include "navi10_ip_offset.h"
66
67#include "dcn/dcn_2_0_0_offset.h"
68#include "dcn/dcn_2_0_0_sh_mask.h"
69
70#include "nbio/nbio_2_3_offset.h"
71
bb21290f
CL		 72#include "dcn20/dcn20_dwb.h"
73#include "dcn20/dcn20_mmhubbub.h"
74
7ed4e635
HW		 75#include "mmhub/mmhub_2_0_0_offset.h"
76#include "mmhub/mmhub_2_0_0_sh_mask.h"
77
78#include "reg_helper.h"
79#include "dce/dce_abm.h"
80#include "dce/dce_dmcu.h"
81#include "dce/dce_aux.h"
82#include "dce/dce_i2c.h"
83#include "vm_helper.h"
84
85#include "amdgpu_socbb.h"
86
7ed4e635
HW		 87#define DC_LOGGER_INIT(logger)
88
89struct _vcs_dpi_ip_params_st dcn2_0_ip = {
90 .odm_capable = 1,
91 .gpuvm_enable = 0,
92 .hostvm_enable = 0,
93 .gpuvm_max_page_table_levels = 4,
94 .hostvm_max_page_table_levels = 4,
95 .hostvm_cached_page_table_levels = 0,
96 .pte_group_size_bytes = 2048,
97bda032 97 .num_dsc = 6,
7ed4e635
HW		 98 .rob_buffer_size_kbytes = 168,
99 .det_buffer_size_kbytes = 164,
100 .dpte_buffer_size_in_pte_reqs_luma = 84,
101 .pde_proc_buffer_size_64k_reqs = 48,
102 .dpp_output_buffer_pixels = 2560,
103 .opp_output_buffer_lines = 1,
104 .pixel_chunk_size_kbytes = 8,
105 .pte_chunk_size_kbytes = 2,
106 .meta_chunk_size_kbytes = 2,
107 .writeback_chunk_size_kbytes = 2,
108 .line_buffer_size_bits = 789504,
109 .is_line_buffer_bpp_fixed = 0,
110 .line_buffer_fixed_bpp = 0,
111 .dcc_supported = true,
112 .max_line_buffer_lines = 12,
113 .writeback_luma_buffer_size_kbytes = 12,
114 .writeback_chroma_buffer_size_kbytes = 8,
115 .writeback_chroma_line_buffer_width_pixels = 4,
116 .writeback_max_hscl_ratio = 1,
117 .writeback_max_vscl_ratio = 1,
118 .writeback_min_hscl_ratio = 1,
119 .writeback_min_vscl_ratio = 1,
120 .writeback_max_hscl_taps = 12,
121 .writeback_max_vscl_taps = 12,
122 .writeback_line_buffer_luma_buffer_size = 0,
123 .writeback_line_buffer_chroma_buffer_size = 14643,
124 .cursor_buffer_size = 8,
125 .cursor_chunk_size = 2,
126 .max_num_otg = 6,
127 .max_num_dpp = 6,
128 .max_num_wb = 1,
129 .max_dchub_pscl_bw_pix_per_clk = 4,
130 .max_pscl_lb_bw_pix_per_clk = 2,
131 .max_lb_vscl_bw_pix_per_clk = 4,
132 .max_vscl_hscl_bw_pix_per_clk = 4,
133 .max_hscl_ratio = 8,
134 .max_vscl_ratio = 8,
135 .hscl_mults = 4,
136 .vscl_mults = 4,
137 .max_hscl_taps = 8,
138 .max_vscl_taps = 8,
139 .dispclk_ramp_margin_percent = 1,
140 .underscan_factor = 1.10,
141 .min_vblank_lines = 32, //
142 .dppclk_delay_subtotal = 77, //
143 .dppclk_delay_scl_lb_only = 16,
144 .dppclk_delay_scl = 50,
145 .dppclk_delay_cnvc_formatter = 8,
146 .dppclk_delay_cnvc_cursor = 6,
147 .dispclk_delay_subtotal = 87, //
148 .dcfclk_cstate_latency = 10, // SRExitTime
149 .max_inter_dcn_tile_repeaters = 8,
150
151 .xfc_supported = true,
152 .xfc_fill_bw_overhead_percent = 10.0,
153 .xfc_fill_constant_bytes = 0,
154};
155
a2c63407
Z		 156struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {
157 .odm_capable = 1,
158 .gpuvm_enable = 0,
159 .hostvm_enable = 0,
160 .gpuvm_max_page_table_levels = 4,
161 .hostvm_max_page_table_levels = 4,
162 .hostvm_cached_page_table_levels = 0,
163 .num_dsc = 5,
164 .rob_buffer_size_kbytes = 168,
165 .det_buffer_size_kbytes = 164,
166 .dpte_buffer_size_in_pte_reqs_luma = 84,
167 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
168 .dpp_output_buffer_pixels = 2560,
169 .opp_output_buffer_lines = 1,
170 .pixel_chunk_size_kbytes = 8,
171 .pte_enable = 1,
172 .max_page_table_levels = 4,
173 .pte_chunk_size_kbytes = 2,
174 .meta_chunk_size_kbytes = 2,
175 .writeback_chunk_size_kbytes = 2,
176 .line_buffer_size_bits = 789504,
177 .is_line_buffer_bpp_fixed = 0,
178 .line_buffer_fixed_bpp = 0,
179 .dcc_supported = true,
180 .max_line_buffer_lines = 12,
181 .writeback_luma_buffer_size_kbytes = 12,
182 .writeback_chroma_buffer_size_kbytes = 8,
183 .writeback_chroma_line_buffer_width_pixels = 4,
184 .writeback_max_hscl_ratio = 1,
185 .writeback_max_vscl_ratio = 1,
186 .writeback_min_hscl_ratio = 1,
187 .writeback_min_vscl_ratio = 1,
188 .writeback_max_hscl_taps = 12,
189 .writeback_max_vscl_taps = 12,
190 .writeback_line_buffer_luma_buffer_size = 0,
191 .writeback_line_buffer_chroma_buffer_size = 14643,
192 .cursor_buffer_size = 8,
193 .cursor_chunk_size = 2,
194 .max_num_otg = 5,
195 .max_num_dpp = 5,
196 .max_num_wb = 1,
197 .max_dchub_pscl_bw_pix_per_clk = 4,
198 .max_pscl_lb_bw_pix_per_clk = 2,
199 .max_lb_vscl_bw_pix_per_clk = 4,
200 .max_vscl_hscl_bw_pix_per_clk = 4,
201 .max_hscl_ratio = 8,
202 .max_vscl_ratio = 8,
203 .hscl_mults = 4,
204 .vscl_mults = 4,
205 .max_hscl_taps = 8,
206 .max_vscl_taps = 8,
207 .dispclk_ramp_margin_percent = 1,
208 .underscan_factor = 1.10,
209 .min_vblank_lines = 32, //
210 .dppclk_delay_subtotal = 77, //
211 .dppclk_delay_scl_lb_only = 16,
212 .dppclk_delay_scl = 50,
213 .dppclk_delay_cnvc_formatter = 8,
214 .dppclk_delay_cnvc_cursor = 6,
215 .dispclk_delay_subtotal = 87, //
216 .dcfclk_cstate_latency = 10, // SRExitTime
217 .max_inter_dcn_tile_repeaters = 8,
218 .xfc_supported = true,
219 .xfc_fill_bw_overhead_percent = 10.0,
220 .xfc_fill_constant_bytes = 0,
221 .ptoi_supported = 0
222};
223
fb6959ae
NK		 224struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
225 /* Defaults that get patched on driver load from firmware. */
226 .clock_limits = {
227 {
228 .state = 0,
229 .dcfclk_mhz = 560.0,
230 .fabricclk_mhz = 560.0,
231 .dispclk_mhz = 513.0,
232 .dppclk_mhz = 513.0,
233 .phyclk_mhz = 540.0,
234 .socclk_mhz = 560.0,
235 .dscclk_mhz = 171.0,
236 .dram_speed_mts = 8960.0,
237 },
238 {
239 .state = 1,
240 .dcfclk_mhz = 694.0,
241 .fabricclk_mhz = 694.0,
242 .dispclk_mhz = 642.0,
243 .dppclk_mhz = 642.0,
244 .phyclk_mhz = 600.0,
245 .socclk_mhz = 694.0,
246 .dscclk_mhz = 214.0,
247 .dram_speed_mts = 11104.0,
248 },
249 {
250 .state = 2,
251 .dcfclk_mhz = 875.0,
252 .fabricclk_mhz = 875.0,
253 .dispclk_mhz = 734.0,
254 .dppclk_mhz = 734.0,
255 .phyclk_mhz = 810.0,
256 .socclk_mhz = 875.0,
257 .dscclk_mhz = 245.0,
258 .dram_speed_mts = 14000.0,
259 },
260 {
261 .state = 3,
262 .dcfclk_mhz = 1000.0,
263 .fabricclk_mhz = 1000.0,
264 .dispclk_mhz = 1100.0,
265 .dppclk_mhz = 1100.0,
266 .phyclk_mhz = 810.0,
267 .socclk_mhz = 1000.0,
268 .dscclk_mhz = 367.0,
269 .dram_speed_mts = 16000.0,
270 },
271 {
272 .state = 4,
273 .dcfclk_mhz = 1200.0,
274 .fabricclk_mhz = 1200.0,
275 .dispclk_mhz = 1284.0,
276 .dppclk_mhz = 1284.0,
277 .phyclk_mhz = 810.0,
278 .socclk_mhz = 1200.0,
279 .dscclk_mhz = 428.0,
280 .dram_speed_mts = 16000.0,
281 },
282 /*Extra state, no dispclk ramping*/
283 {
284 .state = 5,
285 .dcfclk_mhz = 1200.0,
286 .fabricclk_mhz = 1200.0,
287 .dispclk_mhz = 1284.0,
288 .dppclk_mhz = 1284.0,
289 .phyclk_mhz = 810.0,
290 .socclk_mhz = 1200.0,
291 .dscclk_mhz = 428.0,
292 .dram_speed_mts = 16000.0,
293 },
294 },
295 .num_states = 5,
296 .sr_exit_time_us = 8.6,
297 .sr_enter_plus_exit_time_us = 10.9,
298 .urgent_latency_us = 4.0,
299 .urgent_latency_pixel_data_only_us = 4.0,
300 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
301 .urgent_latency_vm_data_only_us = 4.0,
302 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
303 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
304 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
305 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
306 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
307 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
308 .max_avg_sdp_bw_use_normal_percent = 40.0,
309 .max_avg_dram_bw_use_normal_percent = 40.0,
310 .writeback_latency_us = 12.0,
311 .ideal_dram_bw_after_urgent_percent = 40.0,
312 .max_request_size_bytes = 256,
313 .dram_channel_width_bytes = 2,
314 .fabric_datapath_to_dcn_data_return_bytes = 64,
315 .dcn_downspread_percent = 0.5,
316 .downspread_percent = 0.38,
317 .dram_page_open_time_ns = 50.0,
318 .dram_rw_turnaround_time_ns = 17.5,
319 .dram_return_buffer_per_channel_bytes = 8192,
320 .round_trip_ping_latency_dcfclk_cycles = 131,
321 .urgent_out_of_order_return_per_channel_bytes = 256,
322 .channel_interleave_bytes = 256,
323 .num_banks = 8,
324 .num_chans = 16,
325 .vmm_page_size_bytes = 4096,
326 .dram_clock_change_latency_us = 404.0,
327 .dummy_pstate_latency_us = 5.0,
328 .writeback_dram_clock_change_latency_us = 23.0,
329 .return_bus_width_bytes = 64,
330 .dispclk_dppclk_vco_speed_mhz = 3850,
331 .xfc_bus_transport_time_us = 20,
332 .xfc_xbuf_latency_tolerance_us = 4,
333 .use_urgent_burst_bw = 0
334};
7ed4e635 335
675a9e38 336struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
7ed4e635
HW		 337
338#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
339 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
340 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
341 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
342 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
343 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
344 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
345 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
346 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
347 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
348 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
349 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
350 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
351 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
352 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
353#endif
354
355
356enum dcn20_clk_src_array_id {
357 DCN20_CLK_SRC_PLL0,
358 DCN20_CLK_SRC_PLL1,
359 DCN20_CLK_SRC_PLL2,
360 DCN20_CLK_SRC_PLL3,
361 DCN20_CLK_SRC_PLL4,
362 DCN20_CLK_SRC_PLL5,
363 DCN20_CLK_SRC_TOTAL
364};
365
366/* begin *********************
367 * macros to expend register list macro defined in HW object header file */
368
369/* DCN */
370/* TODO awful hack. fixup dcn20_dwb.h */
371#undef BASE_INNER
372#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
373
374#define BASE(seg) BASE_INNER(seg)
375
376#define SR(reg_name)\
377 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
378 mm ## reg_name
379
380#define SRI(reg_name, block, id)\
381 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
382 mm ## block ## id ## _ ## reg_name
383
384#define SRIR(var_name, reg_name, block, id)\
385 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
386 mm ## block ## id ## _ ## reg_name
387
388#define SRII(reg_name, block, id)\
389 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
390 mm ## block ## id ## _ ## reg_name
391
392#define DCCG_SRII(reg_name, block, id)\
393 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
394 mm ## block ## id ## _ ## reg_name
395
396/* NBIO */
397#define NBIO_BASE_INNER(seg) \
398 NBIO_BASE__INST0_SEG ## seg
399
400#define NBIO_BASE(seg) \
401 NBIO_BASE_INNER(seg)
402
403#define NBIO_SR(reg_name)\
404 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
405 mm ## reg_name
406
407/* MMHUB */
408#define MMHUB_BASE_INNER(seg) \
409 MMHUB_BASE__INST0_SEG ## seg
410
411#define MMHUB_BASE(seg) \
412 MMHUB_BASE_INNER(seg)
413
414#define MMHUB_SR(reg_name)\
415 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
416 mmMM ## reg_name
417
418static const struct bios_registers bios_regs = {
419 NBIO_SR(BIOS_SCRATCH_3),
420 NBIO_SR(BIOS_SCRATCH_6)
421};
422
423#define clk_src_regs(index, pllid)\
424[index] = {\
425 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
426}
427
428static const struct dce110_clk_src_regs clk_src_regs[] = {
429 clk_src_regs(0, A),
430 clk_src_regs(1, B),
431 clk_src_regs(2, C),
432 clk_src_regs(3, D),
433 clk_src_regs(4, E),
434 clk_src_regs(5, F)
435};
436
437static const struct dce110_clk_src_shift cs_shift = {
438 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
439};
440
441static const struct dce110_clk_src_mask cs_mask = {
442 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
443};
444
445static const struct dce_dmcu_registers dmcu_regs = {
446 DMCU_DCN10_REG_LIST()
447};
448
449static const struct dce_dmcu_shift dmcu_shift = {
450 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
451};
452
453static const struct dce_dmcu_mask dmcu_mask = {
454 DMCU_MASK_SH_LIST_DCN10(_MASK)
455};
d7c29549 456
7ed4e635 457static const struct dce_abm_registers abm_regs = {
d7c29549 458 ABM_DCN20_REG_LIST()
7ed4e635
HW		 459};
460
461static const struct dce_abm_shift abm_shift = {
d7c29549 462 ABM_MASK_SH_LIST_DCN20(__SHIFT)
7ed4e635
HW		 463};
464
465static const struct dce_abm_mask abm_mask = {
d7c29549 466 ABM_MASK_SH_LIST_DCN20(_MASK)
7ed4e635 467};
d7c29549 468
7ed4e635
HW		 469#define audio_regs(id)\
470[id] = {\
471 AUD_COMMON_REG_LIST(id)\
472}
473
474static const struct dce_audio_registers audio_regs[] = {
475 audio_regs(0),
476 audio_regs(1),
477 audio_regs(2),
478 audio_regs(3),
479 audio_regs(4),
480 audio_regs(5),
481 audio_regs(6),
482};
483
484#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
485 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
486 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
487 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
488
489static const struct dce_audio_shift audio_shift = {
490 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
491};
492
54a9bcb0 493static const struct dce_audio_mask audio_mask = {
7ed4e635
HW		 494 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
495};
496
497#define stream_enc_regs(id)\
498[id] = {\
499 SE_DCN2_REG_LIST(id)\
500}
501
502static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
503 stream_enc_regs(0),
504 stream_enc_regs(1),
505 stream_enc_regs(2),
506 stream_enc_regs(3),
507 stream_enc_regs(4),
508 stream_enc_regs(5),
509};
510
511static const struct dcn10_stream_encoder_shift se_shift = {
512 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
513};
514
515static const struct dcn10_stream_encoder_mask se_mask = {
516 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
517};
518
519
520#define aux_regs(id)\
521[id] = {\
522 DCN2_AUX_REG_LIST(id)\
523}
524
525static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
526 aux_regs(0),
527 aux_regs(1),
528 aux_regs(2),
529 aux_regs(3),
530 aux_regs(4),
531 aux_regs(5)
532};
533
534#define hpd_regs(id)\
535[id] = {\
536 HPD_REG_LIST(id)\
537}
538
539static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
540 hpd_regs(0),
541 hpd_regs(1),
542 hpd_regs(2),
543 hpd_regs(3),
544 hpd_regs(4),
545 hpd_regs(5)
546};
547
548#define link_regs(id, phyid)\
549[id] = {\
550 LE_DCN10_REG_LIST(id), \
551 UNIPHY_DCN2_REG_LIST(phyid), \
552 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
553}
554
555static const struct dcn10_link_enc_registers link_enc_regs[] = {
556 link_regs(0, A),
557 link_regs(1, B),
558 link_regs(2, C),
559 link_regs(3, D),
560 link_regs(4, E),
561 link_regs(5, F)
562};
563
564static const struct dcn10_link_enc_shift le_shift = {
565 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT)
566};
567
568static const struct dcn10_link_enc_mask le_mask = {
569 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK)
570};
571
572#define ipp_regs(id)\
573[id] = {\
574 IPP_REG_LIST_DCN20(id),\
575}
576
577static const struct dcn10_ipp_registers ipp_regs[] = {
578 ipp_regs(0),
579 ipp_regs(1),
580 ipp_regs(2),
581 ipp_regs(3),
582 ipp_regs(4),
583 ipp_regs(5),
584};
585
586static const struct dcn10_ipp_shift ipp_shift = {
587 IPP_MASK_SH_LIST_DCN20(__SHIFT)
588};
589
590static const struct dcn10_ipp_mask ipp_mask = {
591 IPP_MASK_SH_LIST_DCN20(_MASK),
592};
593
594#define opp_regs(id)\
595[id] = {\
596 OPP_REG_LIST_DCN20(id),\
597}
598
599static const struct dcn20_opp_registers opp_regs[] = {
600 opp_regs(0),
601 opp_regs(1),
602 opp_regs(2),
603 opp_regs(3),
604 opp_regs(4),
605 opp_regs(5),
606};
607
608static const struct dcn20_opp_shift opp_shift = {
609 OPP_MASK_SH_LIST_DCN20(__SHIFT)
610};
611
612static const struct dcn20_opp_mask opp_mask = {
613 OPP_MASK_SH_LIST_DCN20(_MASK)
614};
615
616#define aux_engine_regs(id)\
617[id] = {\
618 AUX_COMMON_REG_LIST0(id), \
619 .AUXN_IMPCAL = 0, \
620 .AUXP_IMPCAL = 0, \
621 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
622}
623
624static const struct dce110_aux_registers aux_engine_regs[] = {
625 aux_engine_regs(0),
626 aux_engine_regs(1),
627 aux_engine_regs(2),
628 aux_engine_regs(3),
629 aux_engine_regs(4),
630 aux_engine_regs(5)
631};
632
633#define tf_regs(id)\
634[id] = {\
635 TF_REG_LIST_DCN20(id),\
636}
637
638static const struct dcn2_dpp_registers tf_regs[] = {
639 tf_regs(0),
640 tf_regs(1),
641 tf_regs(2),
642 tf_regs(3),
643 tf_regs(4),
644 tf_regs(5),
645};
646
647static const struct dcn2_dpp_shift tf_shift = {
d56eaa7c
JA		 648 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
649 TF_DEBUG_REG_LIST_SH_DCN10
7ed4e635
HW		 650};
651
652static const struct dcn2_dpp_mask tf_mask = {
d56eaa7c
JA		 653 TF_REG_LIST_SH_MASK_DCN20(_MASK),
654 TF_DEBUG_REG_LIST_MASK_DCN10
7ed4e635
HW		 655};
656
bb21290f
CL		 657#define dwbc_regs_dcn2(id)\
658[id] = {\
659 DWBC_COMMON_REG_LIST_DCN2_0(id),\
660 }
661
662static const struct dcn20_dwbc_registers dwbc20_regs[] = {
663 dwbc_regs_dcn2(0),
664};
665
666static const struct dcn20_dwbc_shift dwbc20_shift = {
667 DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
668};
669
670static const struct dcn20_dwbc_mask dwbc20_mask = {
671 DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
672};
673
674#define mcif_wb_regs_dcn2(id)\
675[id] = {\
676 MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\
677 }
678
679static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {
680 mcif_wb_regs_dcn2(0),
681};
682
683static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {
684 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
685};
686
687static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {
688 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
689};
690
7ed4e635
HW		 691static const struct dcn20_mpc_registers mpc_regs = {
692 MPC_REG_LIST_DCN2_0(0),
693 MPC_REG_LIST_DCN2_0(1),
694 MPC_REG_LIST_DCN2_0(2),
695 MPC_REG_LIST_DCN2_0(3),
696 MPC_REG_LIST_DCN2_0(4),
697 MPC_REG_LIST_DCN2_0(5),
698 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
699 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
700 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
701 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
702 MPC_OUT_MUX_REG_LIST_DCN2_0(4),
703 MPC_OUT_MUX_REG_LIST_DCN2_0(5),
704};
705
706static const struct dcn20_mpc_shift mpc_shift = {
707 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
708};
709
710static const struct dcn20_mpc_mask mpc_mask = {
711 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
712};
713
714#define tg_regs(id)\
715[id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
716
717
718static const struct dcn_optc_registers tg_regs[] = {
719 tg_regs(0),
720 tg_regs(1),
721 tg_regs(2),
722 tg_regs(3),
723 tg_regs(4),
724 tg_regs(5)
725};
726
727static const struct dcn_optc_shift tg_shift = {
728 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
729};
730
731static const struct dcn_optc_mask tg_mask = {
732 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
733};
734
735#define hubp_regs(id)\
736[id] = {\
737 HUBP_REG_LIST_DCN20(id)\
738}
739
740static const struct dcn_hubp2_registers hubp_regs[] = {
741 hubp_regs(0),
742 hubp_regs(1),
743 hubp_regs(2),
744 hubp_regs(3),
745 hubp_regs(4),
746 hubp_regs(5)
747};
748
749static const struct dcn_hubp2_shift hubp_shift = {
750 HUBP_MASK_SH_LIST_DCN20(__SHIFT)
751};
752
753static const struct dcn_hubp2_mask hubp_mask = {
754 HUBP_MASK_SH_LIST_DCN20(_MASK)
755};
756
757static const struct dcn_hubbub_registers hubbub_reg = {
758 HUBBUB_REG_LIST_DCN20(0)
759};
760
761static const struct dcn_hubbub_shift hubbub_shift = {
762 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT)
763};
764
765static const struct dcn_hubbub_mask hubbub_mask = {
766 HUBBUB_MASK_SH_LIST_DCN20(_MASK)
767};
768
769#define vmid_regs(id)\
770[id] = {\
771 DCN20_VMID_REG_LIST(id)\
772}
773
774static const struct dcn_vmid_registers vmid_regs[] = {
775 vmid_regs(0),
776 vmid_regs(1),
777 vmid_regs(2),
778 vmid_regs(3),
779 vmid_regs(4),
780 vmid_regs(5),
781 vmid_regs(6),
782 vmid_regs(7),
783 vmid_regs(8),
784 vmid_regs(9),
785 vmid_regs(10),
786 vmid_regs(11),
787 vmid_regs(12),
788 vmid_regs(13),
789 vmid_regs(14),
790 vmid_regs(15)
791};
792
793static const struct dcn20_vmid_shift vmid_shifts = {
794 DCN20_VMID_MASK_SH_LIST(__SHIFT)
795};
796
797static const struct dcn20_vmid_mask vmid_masks = {
798 DCN20_VMID_MASK_SH_LIST(_MASK)
799};
800
8276dd87 801static const struct dce110_aux_registers_shift aux_shift = {
802 DCN_AUX_MASK_SH_LIST(__SHIFT)
803};
804
805static const struct dce110_aux_registers_mask aux_mask = {
806 DCN_AUX_MASK_SH_LIST(_MASK)
807};
808
bf7f5ac3
YMM		 809static int map_transmitter_id_to_phy_instance(
810 enum transmitter transmitter)
811{
812 switch (transmitter) {
813 case TRANSMITTER_UNIPHY_A:
814 return 0;
815 break;
816 case TRANSMITTER_UNIPHY_B:
817 return 1;
818 break;
819 case TRANSMITTER_UNIPHY_C:
820 return 2;
821 break;
822 case TRANSMITTER_UNIPHY_D:
823 return 3;
824 break;
825 case TRANSMITTER_UNIPHY_E:
826 return 4;
827 break;
828 case TRANSMITTER_UNIPHY_F:
829 return 5;
830 break;
831 default:
832 ASSERT(0);
833 return 0;
834 }
835}
8276dd87 836
97bda032
HW		 837#define dsc_regsDCN20(id)\
838[id] = {\
839 DSC_REG_LIST_DCN20(id)\
840}
841
842static const struct dcn20_dsc_registers dsc_regs[] = {
843 dsc_regsDCN20(0),
844 dsc_regsDCN20(1),
845 dsc_regsDCN20(2),
846 dsc_regsDCN20(3),
847 dsc_regsDCN20(4),
848 dsc_regsDCN20(5)
849};
850
851static const struct dcn20_dsc_shift dsc_shift = {
852 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
853};
854
855static const struct dcn20_dsc_mask dsc_mask = {
856 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
857};
7ed4e635
HW		 858
859static const struct dccg_registers dccg_regs = {
860 DCCG_REG_LIST_DCN2()
861};
862
863static const struct dccg_shift dccg_shift = {
864 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
865};
866
867static const struct dccg_mask dccg_mask = {
868 DCCG_MASK_SH_LIST_DCN2(_MASK)
869};
870
871static const struct resource_caps res_cap_nv10 = {
872 .num_timing_generator = 6,
873 .num_opp = 6,
874 .num_video_plane = 6,
875 .num_audio = 7,
876 .num_stream_encoder = 6,
877 .num_pll = 6,
9cbee6ef 878 .num_dwb = 1,
7ed4e635
HW		 879 .num_ddc = 6,
880 .num_vmid = 16,
97bda032 881 .num_dsc = 6,
7ed4e635
HW		 882};
883
884static const struct dc_plane_cap plane_cap = {
885 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
886 .blends_with_above = true,
887 .blends_with_below = true,
7ed4e635 888 .per_pixel_alpha = true,
5b1b2f20
AD		 889
890 .pixel_format_support = {
891 .argb8888 = true,
892 .nv12 = true,
893 .fp16 = true
894 },
895
896 .max_upscale_factor = {
897 .argb8888 = 16000,
898 .nv12 = 16000,
899 .fp16 = 1
900 },
901
902 .max_downscale_factor = {
903 .argb8888 = 250,
904 .nv12 = 250,
905 .fp16 = 1
906 }
7ed4e635 907};
2ebe1773
BL		 908static const struct resource_caps res_cap_nv14 = {
909 .num_timing_generator = 5,
910 .num_opp = 5,
911 .num_video_plane = 5,
912 .num_audio = 6,
913 .num_stream_encoder = 5,
914 .num_pll = 5,
80df905d 915 .num_dwb = 1,
2ebe1773 916 .num_ddc = 5,
6bb27085
ZL		 917 .num_vmid = 16,
918 .num_dsc = 5,
2ebe1773 919};
7ed4e635
HW		 920
921static const struct dc_debug_options debug_defaults_drv = {
922 .disable_dmcu = true,
923 .force_abm_enable = false,
924 .timing_trace = false,
925 .clock_trace = true,
926 .disable_pplib_clock_request = true,
927 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
4d25a0d5 928 .force_single_disp_pipe_split = false,
7ed4e635
HW		 929 .disable_dcc = DCC_ENABLE,
930 .vsr_support = true,
931 .performance_trace = false,
932 .max_downscale_src_width = 5120,/*upto 5K*/
933 .disable_pplib_wm_range = false,
934 .scl_reset_length10 = true,
9e14d4f1 935 .sanity_checks = false,
7ed4e635 936 .disable_tri_buf = true,
1a7d296d 937 .underflow_assert_delay_us = 0xFFFFFFFF,
7ed4e635
HW		 938};
939
940static const struct dc_debug_options debug_defaults_diags = {
941 .disable_dmcu = true,
942 .force_abm_enable = false,
943 .timing_trace = true,
944 .clock_trace = true,
945 .disable_dpp_power_gate = true,
946 .disable_hubp_power_gate = true,
947 .disable_clock_gate = true,
948 .disable_pplib_clock_request = true,
949 .disable_pplib_wm_range = true,
950 .disable_stutter = true,
951 .scl_reset_length10 = true,
1a7d296d 952 .underflow_assert_delay_us = 0xFFFFFFFF,
7ed4e635
HW		 953};
954
955void dcn20_dpp_destroy(struct dpp **dpp)
956{
957 kfree(TO_DCN20_DPP(*dpp));
958 *dpp = NULL;
959}
960
961struct dpp *dcn20_dpp_create(
962 struct dc_context *ctx,
963 uint32_t inst)
964{
965 struct dcn20_dpp *dpp =
966 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
967
968 if (!dpp)
969 return NULL;
970
971 if (dpp2_construct(dpp, ctx, inst,
972 &tf_regs[inst], &tf_shift, &tf_mask))
973 return &dpp->base;
974
975 BREAK_TO_DEBUGGER();
976 kfree(dpp);
977 return NULL;
978}
979
980struct input_pixel_processor *dcn20_ipp_create(
981 struct dc_context *ctx, uint32_t inst)
982{
983 struct dcn10_ipp *ipp =
984 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
985
986 if (!ipp) {
987 BREAK_TO_DEBUGGER();
988 return NULL;
989 }
990
991 dcn20_ipp_construct(ipp, ctx, inst,
992 &ipp_regs[inst], &ipp_shift, &ipp_mask);
993 return &ipp->base;
994}
995
996
997struct output_pixel_processor *dcn20_opp_create(
998 struct dc_context *ctx, uint32_t inst)
999{
1000 struct dcn20_opp *opp =
1001 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1002
1003 if (!opp) {
1004 BREAK_TO_DEBUGGER();
1005 return NULL;
1006 }
1007
1008 dcn20_opp_construct(opp, ctx, inst,
1009 &opp_regs[inst], &opp_shift, &opp_mask);
1010 return &opp->base;
1011}
1012
1013struct dce_aux *dcn20_aux_engine_create(
1014 struct dc_context *ctx,
1015 uint32_t inst)
1016{
1017 struct aux_engine_dce110 *aux_engine =
1018 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
1019
1020 if (!aux_engine)
1021 return NULL;
1022
1023 dce110_aux_engine_construct(aux_engine, ctx, inst,
1024 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
8276dd87 1025 &aux_engine_regs[inst],
1026 &aux_mask,
f6040a43 1027 &aux_shift,
1028 ctx->dc->caps.extended_aux_timeout_support);
7ed4e635
HW		 1029
1030 return &aux_engine->base;
1031}
1032#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
1033
1034static const struct dce_i2c_registers i2c_hw_regs[] = {
1035 i2c_inst_regs(1),
1036 i2c_inst_regs(2),
1037 i2c_inst_regs(3),
1038 i2c_inst_regs(4),
1039 i2c_inst_regs(5),
1040 i2c_inst_regs(6),
1041};
1042
1043static const struct dce_i2c_shift i2c_shifts = {
1044 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
1045};
1046
1047static const struct dce_i2c_mask i2c_masks = {
1048 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
1049};
1050
1051struct dce_i2c_hw *dcn20_i2c_hw_create(
1052 struct dc_context *ctx,
1053 uint32_t inst)
1054{
1055 struct dce_i2c_hw *dce_i2c_hw =
1056 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1057
1058 if (!dce_i2c_hw)
1059 return NULL;
1060
1061 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1062 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1063
1064 return dce_i2c_hw;
1065}
1066struct mpc *dcn20_mpc_create(struct dc_context *ctx)
1067{
1068 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1069 GFP_KERNEL);
1070
1071 if (!mpc20)
1072 return NULL;
1073
1074 dcn20_mpc_construct(mpc20, ctx,
1075 &mpc_regs,
1076 &mpc_shift,
1077 &mpc_mask,
1078 6);
1079
1080 return &mpc20->base;
1081}
1082
1083struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)
1084{
1085 int i;
1086 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1087 GFP_KERNEL);
1088
1089 if (!hubbub)
1090 return NULL;
1091
1092 hubbub2_construct(hubbub, ctx,
1093 &hubbub_reg,
1094 &hubbub_shift,
1095 &hubbub_mask);
1096
1097 for (i = 0; i < res_cap_nv10.num_vmid; i++) {
1098 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1099
1100 vmid->ctx = ctx;
1101
1102 vmid->regs = &vmid_regs[i];
1103 vmid->shifts = &vmid_shifts;
1104 vmid->masks = &vmid_masks;
1105 }
1106
1107 return &hubbub->base;
1108}
1109
1110struct timing_generator *dcn20_timing_generator_create(
1111 struct dc_context *ctx,
1112 uint32_t instance)
1113{
1114 struct optc *tgn10 =
1115 kzalloc(sizeof(struct optc), GFP_KERNEL);
1116
1117 if (!tgn10)
1118 return NULL;
1119
1120 tgn10->base.inst = instance;
1121 tgn10->base.ctx = ctx;
1122
1123 tgn10->tg_regs = &tg_regs[instance];
1124 tgn10->tg_shift = &tg_shift;
1125 tgn10->tg_mask = &tg_mask;
1126
1127 dcn20_timing_generator_init(tgn10);
1128
1129 return &tgn10->base;
1130}
1131
1132static const struct encoder_feature_support link_enc_feature = {
1133 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1134 .max_hdmi_pixel_clock = 600000,
1135 .hdmi_ycbcr420_supported = true,
1136 .dp_ycbcr420_supported = true,
1137 .flags.bits.IS_HBR2_CAPABLE = true,
1138 .flags.bits.IS_HBR3_CAPABLE = true,
1139 .flags.bits.IS_TPS3_CAPABLE = true,
1140 .flags.bits.IS_TPS4_CAPABLE = true
1141};
1142
1143struct link_encoder *dcn20_link_encoder_create(
1144 const struct encoder_init_data *enc_init_data)
1145{
1146 struct dcn20_link_encoder *enc20 =
1147 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
bf7f5ac3 1148 int link_regs_id;
7ed4e635
HW		 1149
1150 if (!enc20)
1151 return NULL;
1152
bf7f5ac3
YMM		 1153 link_regs_id =
1154 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1155
7ed4e635
HW		 1156 dcn20_link_encoder_construct(enc20,
1157 enc_init_data,
1158 &link_enc_feature,
bf7f5ac3 1159 &link_enc_regs[link_regs_id],
7ed4e635
HW		 1160 &link_enc_aux_regs[enc_init_data->channel - 1],
1161 &link_enc_hpd_regs[enc_init_data->hpd_source],
1162 &le_shift,
1163 &le_mask);
1164
1165 return &enc20->enc10.base;
1166}
1167
1168struct clock_source *dcn20_clock_source_create(
1169 struct dc_context *ctx,
1170 struct dc_bios *bios,
1171 enum clock_source_id id,
1172 const struct dce110_clk_src_regs *regs,
1173 bool dp_clk_src)
1174{
1175 struct dce110_clk_src *clk_src =
1176 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1177
1178 if (!clk_src)
1179 return NULL;
1180
1181 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1182 regs, &cs_shift, &cs_mask)) {
1183 clk_src->base.dp_clk_src = dp_clk_src;
1184 return &clk_src->base;
1185 }
1186
cabe144b 1187 kfree(clk_src);
7ed4e635
HW		 1188 BREAK_TO_DEBUGGER();
1189 return NULL;
1190}
1191
1192static void read_dce_straps(
1193 struct dc_context *ctx,
1194 struct resource_straps *straps)
1195{
1196 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1197 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1198}
1199
1200static struct audio *dcn20_create_audio(
1201 struct dc_context *ctx, unsigned int inst)
1202{
1203 return dce_audio_create(ctx, inst,
1204 &audio_regs[inst], &audio_shift, &audio_mask);
1205}
1206
1207struct stream_encoder *dcn20_stream_encoder_create(
1208 enum engine_id eng_id,
1209 struct dc_context *ctx)
1210{
1211 struct dcn10_stream_encoder *enc1 =
1212 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1213
1214 if (!enc1)
1215 return NULL;
1216
9fd4c2d7
ZL		 1217 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
1218 if (eng_id >= ENGINE_ID_DIGD)
1219 eng_id++;
1220 }
1221
7ed4e635
HW		 1222 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1223 &stream_enc_regs[eng_id],
1224 &se_shift, &se_mask);
1225
1226 return &enc1->base;
1227}
1228
1229static const struct dce_hwseq_registers hwseq_reg = {
1230 HWSEQ_DCN2_REG_LIST()
1231};
1232
1233static const struct dce_hwseq_shift hwseq_shift = {
1234 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT)
1235};
1236
1237static const struct dce_hwseq_mask hwseq_mask = {
1238 HWSEQ_DCN2_MASK_SH_LIST(_MASK)
1239};
1240
1241struct dce_hwseq *dcn20_hwseq_create(
1242 struct dc_context *ctx)
1243{
1244 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1245
1246 if (hws) {
1247 hws->ctx = ctx;
1248 hws->regs = &hwseq_reg;
1249 hws->shifts = &hwseq_shift;
1250 hws->masks = &hwseq_mask;
1251 }
1252 return hws;
1253}
1254
1255static const struct resource_create_funcs res_create_funcs = {
1256 .read_dce_straps = read_dce_straps,
1257 .create_audio = dcn20_create_audio,
1258 .create_stream_encoder = dcn20_stream_encoder_create,
1259 .create_hwseq = dcn20_hwseq_create,
1260};
1261
1262static const struct resource_create_funcs res_create_maximus_funcs = {
1263 .read_dce_straps = NULL,
1264 .create_audio = NULL,
1265 .create_stream_encoder = NULL,
1266 .create_hwseq = dcn20_hwseq_create,
1267};
1268
44e149bb
AD		 1269static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
1270
7ed4e635
HW		 1271void dcn20_clock_source_destroy(struct clock_source **clk_src)
1272{
1273 kfree(TO_DCE110_CLK_SRC(*clk_src));
1274 *clk_src = NULL;
1275}
1276
97bda032
HW		 1277
1278struct display_stream_compressor *dcn20_dsc_create(
1279 struct dc_context *ctx, uint32_t inst)
1280{
1281 struct dcn20_dsc *dsc =
1282 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1283
1284 if (!dsc) {
1285 BREAK_TO_DEBUGGER();
1286 return NULL;
1287 }
1288
1289 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1290 return &dsc->base;
1291}
1292
1293void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
1294{
1295 kfree(container_of(*dsc, struct dcn20_dsc, base));
1296 *dsc = NULL;
1297}
1298
7ed4e635 1299
d9e32672 1300static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)
7ed4e635
HW		 1301{
1302 unsigned int i;
1303
1304 for (i = 0; i < pool->base.stream_enc_count; i++) {
1305 if (pool->base.stream_enc[i] != NULL) {
1306 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1307 pool->base.stream_enc[i] = NULL;
1308 }
1309 }
1310
97bda032
HW		 1311 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1312 if (pool->base.dscs[i] != NULL)
1313 dcn20_dsc_destroy(&pool->base.dscs[i]);
1314 }
7ed4e635
HW		 1315
1316 if (pool->base.mpc != NULL) {
1317 kfree(TO_DCN20_MPC(pool->base.mpc));
1318 pool->base.mpc = NULL;
1319 }
1320 if (pool->base.hubbub != NULL) {
1321 kfree(pool->base.hubbub);
1322 pool->base.hubbub = NULL;
1323 }
1324 for (i = 0; i < pool->base.pipe_count; i++) {
1325 if (pool->base.dpps[i] != NULL)
1326 dcn20_dpp_destroy(&pool->base.dpps[i]);
1327
1328 if (pool->base.ipps[i] != NULL)
1329 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1330
1331 if (pool->base.hubps[i] != NULL) {
1332 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1333 pool->base.hubps[i] = NULL;
1334 }
1335
1336 if (pool->base.irqs != NULL) {
1337 dal_irq_service_destroy(&pool->base.irqs);
1338 }
1339 }
1340
1341 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1342 if (pool->base.engines[i] != NULL)
1343 dce110_engine_destroy(&pool->base.engines[i]);
1344 if (pool->base.hw_i2cs[i] != NULL) {
1345 kfree(pool->base.hw_i2cs[i]);
1346 pool->base.hw_i2cs[i] = NULL;
1347 }
1348 if (pool->base.sw_i2cs[i] != NULL) {
1349 kfree(pool->base.sw_i2cs[i]);
1350 pool->base.sw_i2cs[i] = NULL;
1351 }
1352 }
1353
1354 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1355 if (pool->base.opps[i] != NULL)
1356 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1357 }
1358
1359 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1360 if (pool->base.timing_generators[i] != NULL) {
1361 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1362 pool->base.timing_generators[i] = NULL;
1363 }
1364 }
1365
bb21290f
CL		 1366 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1367 if (pool->base.dwbc[i] != NULL) {
1368 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
1369 pool->base.dwbc[i] = NULL;
1370 }
1371 if (pool->base.mcif_wb[i] != NULL) {
1372 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
1373 pool->base.mcif_wb[i] = NULL;
1374 }
1375 }
1376
7ed4e635
HW		 1377 for (i = 0; i < pool->base.audio_count; i++) {
1378 if (pool->base.audios[i])
1379 dce_aud_destroy(&pool->base.audios[i]);
1380 }
1381
1382 for (i = 0; i < pool->base.clk_src_count; i++) {
1383 if (pool->base.clock_sources[i] != NULL) {
1384 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1385 pool->base.clock_sources[i] = NULL;
1386 }
1387 }
1388
1389 if (pool->base.dp_clock_source != NULL) {
1390 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1391 pool->base.dp_clock_source = NULL;
1392 }
1393
1394
1395 if (pool->base.abm != NULL)
1396 dce_abm_destroy(&pool->base.abm);
1397
1398 if (pool->base.dmcu != NULL)
1399 dce_dmcu_destroy(&pool->base.dmcu);
1400
1401 if (pool->base.dccg != NULL)
1402 dcn_dccg_destroy(&pool->base.dccg);
1403
1404 if (pool->base.pp_smu != NULL)
1405 dcn20_pp_smu_destroy(&pool->base.pp_smu);
1406
d9a07577
JL		 1407 if (pool->base.oem_device != NULL)
1408 dal_ddc_service_destroy(&pool->base.oem_device);
7ed4e635
HW		 1409}
1410
1411struct hubp *dcn20_hubp_create(
1412 struct dc_context *ctx,
1413 uint32_t inst)
1414{
1415 struct dcn20_hubp *hubp2 =
1416 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1417
1418 if (!hubp2)
1419 return NULL;
1420
1421 if (hubp2_construct(hubp2, ctx, inst,
1422 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1423 return &hubp2->base;
1424
1425 BREAK_TO_DEBUGGER();
1426 kfree(hubp2);
1427 return NULL;
1428}
1429
1430static void get_pixel_clock_parameters(
1431 struct pipe_ctx *pipe_ctx,
1432 struct pixel_clk_params *pixel_clk_params)
1433{
1434 const struct dc_stream_state *stream = pipe_ctx->stream;
b1f6d01c
DL		 1435 struct pipe_ctx *odm_pipe;
1436 int opp_cnt = 1;
1437
1438 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1439 opp_cnt++;
7ed4e635
HW		 1440
1441 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1442 pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1443 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1444 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1445 /* TODO: un-hardcode*/
1446 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1447 LINK_RATE_REF_FREQ_IN_KHZ;
1448 pixel_clk_params->flags.ENABLE_SS = 0;
1449 pixel_clk_params->color_depth =
1450 stream->timing.display_color_depth;
1451 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1452 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1453
1454 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1455 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1456
b1f6d01c
DL		 1457 if (opp_cnt == 4)
1458 pixel_clk_params->requested_pix_clk_100hz /= 4;
78c77382 1459 else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2)
7ed4e635
HW		 1460 pixel_clk_params->requested_pix_clk_100hz /= 2;
1461
1462 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1463 pixel_clk_params->requested_pix_clk_100hz *= 2;
1464
1465}
1466
1467static void build_clamping_params(struct dc_stream_state *stream)
1468{
1469 stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1470 stream->clamping.c_depth = stream->timing.display_color_depth;
1471 stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1472}
1473
1474static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1475{
1476
1477 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1478
1479 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1480 pipe_ctx->clock_source,
1481 &pipe_ctx->stream_res.pix_clk_params,
1482 &pipe_ctx->pll_settings);
1483
1484 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1485
1486 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1487 &pipe_ctx->stream->bit_depth_params);
1488 build_clamping_params(pipe_ctx->stream);
1489
1490 return DC_OK;
1491}
1492
1493enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
1494{
1495 enum dc_status status = DC_OK;
1496 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1497
1498 /*TODO Seems unneeded anymore */
1499 /* if (old_context && resource_is_stream_unchanged(old_context, stream)) {
1500 if (stream != NULL && old_context->streams[i] != NULL) {
1501 todo: shouldn't have to copy missing parameter here
1502 resource_build_bit_depth_reduction_params(stream,
1503 &stream->bit_depth_params);
1504 stream->clamping.pixel_encoding =
1505 stream->timing.pixel_encoding;
1506
1507 resource_build_bit_depth_reduction_params(stream,
1508 &stream->bit_depth_params);
1509 build_clamping_params(stream);
1510
1511 continue;
1512 }
1513 }
1514 */
1515
1516 if (!pipe_ctx)
1517 return DC_ERROR_UNEXPECTED;
1518
1519
1520 status = build_pipe_hw_param(pipe_ctx);
1521
1522 return status;
1523}
1524
97bda032 1525
c9ae6e16
NC		 1526static void acquire_dsc(struct resource_context *res_ctx,
1527 const struct resource_pool *pool,
eab4bb97
NC		 1528 struct display_stream_compressor **dsc,
1529 int pipe_idx)
97bda032
HW		 1530{
1531 int i;
c9ae6e16
NC		 1532
1533 ASSERT(*dsc == NULL);
1534 *dsc = NULL;
97bda032 1535
eab4bb97
NC		 1536 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) {
1537 *dsc = pool->dscs[pipe_idx];
1538 res_ctx->is_dsc_acquired[pipe_idx] = true;
1539 return;
1540 }
1541
97bda032
HW		 1542 /* Find first free DSC */
1543 for (i = 0; i < pool->res_cap->num_dsc; i++)
1544 if (!res_ctx->is_dsc_acquired[i]) {
c9ae6e16 1545 *dsc = pool->dscs[i];
97bda032
HW		 1546 res_ctx->is_dsc_acquired[i] = true;
1547 break;
1548 }
97bda032
HW		 1549}
1550
1551static void release_dsc(struct resource_context *res_ctx,
1552 const struct resource_pool *pool,
c9ae6e16 1553 struct display_stream_compressor **dsc)
97bda032
HW		 1554{
1555 int i;
1556
1557 for (i = 0; i < pool->res_cap->num_dsc; i++)
c9ae6e16 1558 if (pool->dscs[i] == *dsc) {
97bda032 1559 res_ctx->is_dsc_acquired[i] = false;
c9ae6e16 1560 *dsc = NULL;
97bda032
HW		 1561 break;
1562 }
1563}
1564
7ed4e635 1565
7ed4e635 1566
ba32c50f 1567static enum dc_status add_dsc_to_stream_resource(struct dc *dc,
c9ae6e16
NC		 1568 struct dc_state *dc_ctx,
1569 struct dc_stream_state *dc_stream)
1570{
1571 enum dc_status result = DC_OK;
1572 int i;
1573 const struct resource_pool *pool = dc->res_pool;
97bda032 1574
c9ae6e16
NC		 1575 /* Get a DSC if required and available */
1576 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1577 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];
97bda032 1578
c9ae6e16
NC		 1579 if (pipe_ctx->stream != dc_stream)
1580 continue;
97bda032 1581
eab4bb97 1582 acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc, i);
97bda032 1583
c9ae6e16
NC		 1584 /* The number of DSCs can be less than the number of pipes */
1585 if (!pipe_ctx->stream_res.dsc) {
c9ae6e16 1586 result = DC_NO_DSC_RESOURCE;
97bda032 1587 }
7ed4e635 1588
c9ae6e16
NC		 1589 break;
1590 }
7ed4e635
HW		 1591
1592 return result;
1593}
1594
1595
ba32c50f 1596static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
c9ae6e16
NC		 1597 struct dc_state *new_ctx,
1598 struct dc_stream_state *dc_stream)
7ed4e635
HW		 1599{
1600 struct pipe_ctx *pipe_ctx = NULL;
1601 int i;
1602
7ed4e635
HW		 1603 for (i = 0; i < MAX_PIPES; i++) {
1604 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1605 pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
b1f6d01c
DL		 1606
1607 if (pipe_ctx->stream_res.dsc)
1608 release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
7ed4e635
HW		 1609 }
1610 }
1611
1612 if (!pipe_ctx)
1613 return DC_ERROR_UNEXPECTED;
b1f6d01c
DL		 1614 else
1615 return DC_OK;
7ed4e635 1616}
c9ae6e16
NC		 1617
1618
1619enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1620{
1621 enum dc_status result = DC_ERROR_UNEXPECTED;
1622
1623 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1624
1625 if (result == DC_OK)
1626 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1627
c9ae6e16
NC		 1628 /* Get a DSC if required and available */
1629 if (result == DC_OK && dc_stream->timing.flags.DSC)
ba32c50f 1630 result = add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
c9ae6e16
NC		 1631
1632 if (result == DC_OK)
1633 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
1634
1635 return result;
1636}
1637
1638
1639enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1640{
1641 enum dc_status result = DC_OK;
1642
ba32c50f 1643 result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
c9ae6e16
NC		 1644
1645 return result;
1646}
7ed4e635
HW		 1647
1648
1649static void swizzle_to_dml_params(
1650 enum swizzle_mode_values swizzle,
1651 unsigned int *sw_mode)
1652{
1653 switch (swizzle) {
1654 case DC_SW_LINEAR:
1655 *sw_mode = dm_sw_linear;
1656 break;
1657 case DC_SW_4KB_S:
1658 *sw_mode = dm_sw_4kb_s;
1659 break;
1660 case DC_SW_4KB_S_X:
1661 *sw_mode = dm_sw_4kb_s_x;
1662 break;
1663 case DC_SW_4KB_D:
1664 *sw_mode = dm_sw_4kb_d;
1665 break;
1666 case DC_SW_4KB_D_X:
1667 *sw_mode = dm_sw_4kb_d_x;
1668 break;
1669 case DC_SW_64KB_S:
1670 *sw_mode = dm_sw_64kb_s;
1671 break;
1672 case DC_SW_64KB_S_X:
1673 *sw_mode = dm_sw_64kb_s_x;
1674 break;
1675 case DC_SW_64KB_S_T:
1676 *sw_mode = dm_sw_64kb_s_t;
1677 break;
1678 case DC_SW_64KB_D:
1679 *sw_mode = dm_sw_64kb_d;
1680 break;
1681 case DC_SW_64KB_D_X:
1682 *sw_mode = dm_sw_64kb_d_x;
1683 break;
1684 case DC_SW_64KB_D_T:
1685 *sw_mode = dm_sw_64kb_d_t;
1686 break;
1687 case DC_SW_64KB_R_X:
1688 *sw_mode = dm_sw_64kb_r_x;
1689 break;
1690 case DC_SW_VAR_S:
1691 *sw_mode = dm_sw_var_s;
1692 break;
1693 case DC_SW_VAR_S_X:
1694 *sw_mode = dm_sw_var_s_x;
1695 break;
1696 case DC_SW_VAR_D:
1697 *sw_mode = dm_sw_var_d;
1698 break;
1699 case DC_SW_VAR_D_X:
1700 *sw_mode = dm_sw_var_d_x;
1701 break;
1702
1703 default:
1704 ASSERT(0); /* Not supported */
1705 break;
1706 }
1707}
1708
b6bfba6c 1709bool dcn20_split_stream_for_odm(
b1f6d01c
DL		 1710 struct resource_context *res_ctx,
1711 const struct resource_pool *pool,
1712 struct pipe_ctx *prev_odm_pipe,
1713 struct pipe_ctx *next_odm_pipe)
1714{
1715 int pipe_idx = next_odm_pipe->pipe_idx;
b1f6d01c
DL		 1716
1717 *next_odm_pipe = *prev_odm_pipe;
b1f6d01c
DL		 1718
1719 next_odm_pipe->pipe_idx = pipe_idx;
1720 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
1721 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
1722 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
1723 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
1724 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
1725 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
b1f6d01c 1726 next_odm_pipe->stream_res.dsc = NULL;
b1f6d01c 1727 if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
b1f6d01c
DL		 1728 next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
1729 next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
1730 }
1731 prev_odm_pipe->next_odm_pipe = next_odm_pipe;
1732 next_odm_pipe->prev_odm_pipe = prev_odm_pipe;
1733 ASSERT(next_odm_pipe->top_pipe == NULL);
1734
1735 if (prev_odm_pipe->plane_state) {
c0358809
DL		 1736 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
1737 int new_width;
1738
b1f6d01c
DL		 1739 /* HACTIVE halved for odm combine */
1740 sd->h_active /= 2;
b1f6d01c
DL		 1741 /* Calculate new vp and recout for left pipe */
1742 /* Need at least 16 pixels width per side */
1743 if (sd->recout.x + 16 >= sd->h_active)
1744 return false;
1745 new_width = sd->h_active - sd->recout.x;
1746 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1747 sd->ratios.horz, sd->recout.width - new_width));
1748 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1749 sd->ratios.horz_c, sd->recout.width - new_width));
1750 sd->recout.width = new_width;
1751
1752 /* Calculate new vp and recout for right pipe */
1753 sd = &next_odm_pipe->plane_res.scl_data;
c0358809
DL		 1754 /* HACTIVE halved for odm combine */
1755 sd->h_active /= 2;
b1f6d01c
DL		 1756 /* Need at least 16 pixels width per side */
1757 if (new_width <= 16)
1758 return false;
c0358809 1759 new_width = sd->recout.width + sd->recout.x - sd->h_active;
b1f6d01c
DL		 1760 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1761 sd->ratios.horz, sd->recout.width - new_width));
1762 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1763 sd->ratios.horz_c, sd->recout.width - new_width));
1764 sd->recout.width = new_width;
1765 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
1766 sd->ratios.horz, sd->h_active - sd->recout.x));
1767 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
1768 sd->ratios.horz_c, sd->h_active - sd->recout.x));
1769 sd->recout.x = 0;
1770 }
1771 next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
b1f6d01c 1772 if (next_odm_pipe->stream->timing.flags.DSC == 1) {
eab4bb97 1773 acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);
b1f6d01c
DL		 1774 ASSERT(next_odm_pipe->stream_res.dsc);
1775 if (next_odm_pipe->stream_res.dsc == NULL)
1776 return false;
1777 }
b1f6d01c
DL		 1778
1779 return true;
1780}
1781
b6bfba6c 1782void dcn20_split_stream_for_mpc(
7ed4e635
HW		 1783 struct resource_context *res_ctx,
1784 const struct resource_pool *pool,
1785 struct pipe_ctx *primary_pipe,
b1f6d01c 1786 struct pipe_ctx *secondary_pipe)
7ed4e635
HW		 1787{
1788 int pipe_idx = secondary_pipe->pipe_idx;
7ed4e635 1789 struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
7ed4e635
HW		 1790
1791 *secondary_pipe = *primary_pipe;
1792 secondary_pipe->bottom_pipe = sec_bot_pipe;
1793
1794 secondary_pipe->pipe_idx = pipe_idx;
1795 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
1796 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
1797 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
1798 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
1799 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
1800 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
c92b4c46 1801 secondary_pipe->stream_res.dsc = NULL;
7ed4e635
HW		 1802 if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
1803 ASSERT(!secondary_pipe->bottom_pipe);
1804 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
1805 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
1806 }
1807 primary_pipe->bottom_pipe = secondary_pipe;
1808 secondary_pipe->top_pipe = primary_pipe;
1809
b1f6d01c
DL		 1810 ASSERT(primary_pipe->plane_state);
1811 resource_build_scaling_params(primary_pipe);
1812 resource_build_scaling_params(secondary_pipe);
7ed4e635
HW		 1813}
1814
1815void dcn20_populate_dml_writeback_from_context(
1816 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1817{
1818 int pipe_cnt, i;
1819
1820 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1821 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];
1822
1823 if (!res_ctx->pipe_ctx[i].stream)
1824 continue;
1825
1826 /* Set writeback information */
1827 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
1828 pipes[pipe_cnt].dout.num_active_wb++;
1829 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
1830 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
1831 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
1832 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
1833 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
1834 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1;
1835 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
1836 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
1837 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0;
1838 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0;
1839 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
1840 if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
1841 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
1842 else
1843 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
1844 } else
1845 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
1846
1847 pipe_cnt++;
1848 }
1849
1850}
1851
1852int dcn20_populate_dml_pipes_from_context(
2f488884 1853 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)
7ed4e635
HW		 1854{
1855 int pipe_cnt, i;
1856 bool synchronized_vblank = true;
2f488884 1857 struct resource_context *res_ctx = &context->res_ctx;
7ed4e635
HW		 1858
1859 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
1860 if (!res_ctx->pipe_ctx[i].stream)
1861 continue;
1862
1863 if (pipe_cnt < 0) {
1864 pipe_cnt = i;
1865 continue;
1866 }
785908cf 1867 if (dc->debug.disable_timing_sync || !resource_are_streams_timing_synchronizable(
7ed4e635
HW		 1868 res_ctx->pipe_ctx[pipe_cnt].stream,
1869 res_ctx->pipe_ctx[i].stream)) {
1870 synchronized_vblank = false;
1871 break;
1872 }
1873 }
1874
1875 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1876 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
2f488884 1877 unsigned int v_total;
03fd87db 1878 int output_bpc;
7ed4e635
HW		 1879
1880 if (!res_ctx->pipe_ctx[i].stream)
1881 continue;
2f488884
AL		 1882
1883 v_total = timing->v_total;
7ed4e635
HW		 1884 /* todo:
1885 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
1886 pipes[pipe_cnt].pipe.src.dcc = 0;
1887 pipes[pipe_cnt].pipe.src.vm = 0;*/
1888
97bda032
HW		 1889 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
1890 /* todo: rotation?*/
1891 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
7ed4e635
HW		 1892 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
1893 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
1894 /* 1/2 vblank */
1895 pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
2f488884 1896 (v_total - timing->v_addressable
7ed4e635
HW		 1897 - timing->v_border_top - timing->v_border_bottom) / 2;
1898 /* 36 bytes dp, 32 hdmi */
1899 pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
1900 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
1901 }
1902 pipes[pipe_cnt].pipe.src.dcc = false;
1903 pipes[pipe_cnt].pipe.src.dcc_rate = 1;
1904 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
1905 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
1906 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
1907 - timing->h_addressable
1908 - timing->h_border_left
1909 - timing->h_border_right;
2f488884 1910 pipes[pipe_cnt].pipe.dest.vblank_start = v_total - timing->v_front_porch;
7ed4e635
HW		 1911 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
1912 - timing->v_addressable
1913 - timing->v_border_top
1914 - timing->v_border_bottom;
1915 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
2f488884 1916 pipes[pipe_cnt].pipe.dest.vtotal = v_total;
7ed4e635
HW		 1917 pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable;
1918 pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable;
1919 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
1920 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
1921 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1922 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
1923 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
1621f4c4 1924 pipes[pipe_cnt].dout.dp_lanes = 4;
8bb3d7e7
CL		 1925 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
1926 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
c0358809
DL		 1927 pipes[pipe_cnt].pipe.dest.odm_combine = res_ctx->pipe_ctx[i].prev_odm_pipe
1928 || res_ctx->pipe_ctx[i].next_odm_pipe;
1929 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1930 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
1931 == res_ctx->pipe_ctx[i].plane_state)
1932 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
1933 else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
1934 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
1935
1936 while (first_pipe->prev_odm_pipe)
1937 first_pipe = first_pipe->prev_odm_pipe;
1938 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
1939 }
7ed4e635 1940
7ed4e635
HW		 1941 switch (res_ctx->pipe_ctx[i].stream->signal) {
1942 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1943 case SIGNAL_TYPE_DISPLAY_PORT:
1944 pipes[pipe_cnt].dout.output_type = dm_dp;
1945 break;
1946 case SIGNAL_TYPE_EDP:
1947 pipes[pipe_cnt].dout.output_type = dm_edp;
1948 break;
1949 case SIGNAL_TYPE_HDMI_TYPE_A:
1950 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1951 case SIGNAL_TYPE_DVI_DUAL_LINK:
1952 pipes[pipe_cnt].dout.output_type = dm_hdmi;
1953 break;
1954 default:
1955 /* In case there is no signal, set dp with 4 lanes to allow max config */
1956 pipes[pipe_cnt].dout.output_type = dm_dp;
1957 pipes[pipe_cnt].dout.dp_lanes = 4;
1958 }
03fd87db
IB		 1959
1960 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
1961 case COLOR_DEPTH_666:
1962 output_bpc = 6;
1963 break;
1964 case COLOR_DEPTH_888:
1965 output_bpc = 8;
1966 break;
1967 case COLOR_DEPTH_101010:
1968 output_bpc = 10;
1969 break;
1970 case COLOR_DEPTH_121212:
1971 output_bpc = 12;
1972 break;
1973 case COLOR_DEPTH_141414:
1974 output_bpc = 14;
1975 break;
1976 case COLOR_DEPTH_161616:
1977 output_bpc = 16;
1978 break;
03fd87db
IB		 1979 case COLOR_DEPTH_999:
1980 output_bpc = 9;
1981 break;
1982 case COLOR_DEPTH_111111:
1983 output_bpc = 11;
1984 break;
03fd87db
IB		 1985 default:
1986 output_bpc = 8;
1987 break;
1988 }
1989
7ed4e635
HW		 1990 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
1991 case PIXEL_ENCODING_RGB:
1992 case PIXEL_ENCODING_YCBCR444:
1993 pipes[pipe_cnt].dout.output_format = dm_444;
03fd87db 1994 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
7ed4e635
HW		 1995 break;
1996 case PIXEL_ENCODING_YCBCR420:
1997 pipes[pipe_cnt].dout.output_format = dm_420;
486cc0ee 1998 pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2;
7ed4e635
HW		 1999 break;
2000 case PIXEL_ENCODING_YCBCR422:
2001 if (true) /* todo */
2002 pipes[pipe_cnt].dout.output_format = dm_s422;
2003 else
2004 pipes[pipe_cnt].dout.output_format = dm_n422;
03fd87db 2005 pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
7ed4e635
HW		 2006 break;
2007 default:
2008 pipes[pipe_cnt].dout.output_format = dm_444;
03fd87db 2009 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
7ed4e635 2010 }
7ed4e635 2011
486cc0ee
NC		 2012 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)
2013 pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
2014
7ed4e635
HW		 2015 /* todo: default max for now, until there is logic reflecting this in dc*/
2016 pipes[pipe_cnt].dout.output_bpc = 12;
2017 /*
2018 * Use max cursor settings for calculations to minimize
2019 * bw calculations due to cursor on/off
2020 */
2021 pipes[pipe_cnt].pipe.src.num_cursors = 2;
ed07237c
IB		 2022 pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
2023 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
2024 pipes[pipe_cnt].pipe.src.cur1_src_width = 256;
2025 pipes[pipe_cnt].pipe.src.cur1_bpp = dm_cur_32bit;
7ed4e635
HW		 2026
2027 if (!res_ctx->pipe_ctx[i].plane_state) {
2028 pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
2029 pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear;
2030 pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
2031 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
2032 if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
2033 pipes[pipe_cnt].pipe.src.viewport_width = 1920;
2034 pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
2035 if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
2036 pipes[pipe_cnt].pipe.src.viewport_height = 1080;
71e6bd2a 2037 pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height;
7ed4e635
HW		 2038 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */
2039 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2040 pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
2041 pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/
2042 pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_hsplit != 1*/
2043 pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/
2044 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
2045 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
2046 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
2047 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
2048 pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
2049 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
2050 pipes[pipe_cnt].pipe.src.is_hsplit = 0;
2051 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2f488884
AL		 2052 pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;
2053 pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;
7ed4e635
HW		 2054 } else {
2055 struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
2056 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
2057
7ed4e635
HW		 2058 pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
2059 pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe
2060 && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
2061 || (res_ctx->pipe_ctx[i].top_pipe
2062 && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln);
7ed4e635
HW		 2063 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
2064 || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
2065 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
2066 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
2067 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
2068 pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
2069 pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
2070 pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
71e6bd2a 2071 pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;
7ed4e635 2072 if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
12e2b2d4
DL		 2073 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2074 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
2075 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
2076 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
7ed4e635 2077 } else {
12e2b2d4
DL		 2078 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2079 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
7ed4e635
HW		 2080 }
2081 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
2082 pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
2083 pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
2084 pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
2085 pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
2086 if (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) {
2087 pipes[pipe_cnt].pipe.dest.full_recout_width +=
2088 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.width;
2089 pipes[pipe_cnt].pipe.dest.full_recout_height +=
2090 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.height;
2091 } else if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) {
2092 pipes[pipe_cnt].pipe.dest.full_recout_width +=
2093 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.width;
2094 pipes[pipe_cnt].pipe.dest.full_recout_height +=
2095 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.height;
2096 }
2097
ed07237c 2098 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
7ed4e635
HW		 2099 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
2100 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
2101 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
2102 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
2103 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
2104 scl->ratios.vert.value != dc_fixpt_one.value
2105 || scl->ratios.horz.value != dc_fixpt_one.value
2106 || scl->ratios.vert_c.value != dc_fixpt_one.value
2107 || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/
2108 || dc->debug.always_scale; /*support always scale*/
2109 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
2110 pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
2111 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
2112 pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
2113
b964e790
DL		 2114 pipes[pipe_cnt].pipe.src.macro_tile_size =
2115 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
7ed4e635
HW		 2116 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
2117 &pipes[pipe_cnt].pipe.src.sw_mode);
2118
2119 switch (pln->format) {
2120 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2121 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2122 pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
2123 break;
2124 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2125 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2126 pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
2127 break;
2128 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2129 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2130 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2131 pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
2132 break;
2133 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2134 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2135 pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
2136 break;
2137 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2138 pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
2139 break;
2140 default:
2141 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2142 break;
2143 }
2144 }
2145
2146 pipe_cnt++;
2147 }
2148
2149 /* populate writeback information */
2150 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
2151
2152 return pipe_cnt;
2153}
2154
2155unsigned int dcn20_calc_max_scaled_time(
2156 unsigned int time_per_pixel,
2157 enum mmhubbub_wbif_mode mode,
2158 unsigned int urgent_watermark)
2159{
2160 unsigned int time_per_byte = 0;
2161 unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */
2162 unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */
2163 unsigned int small_free_entry, max_free_entry;
2164 unsigned int buf_lh_capability;
2165 unsigned int max_scaled_time;
2166
2167 if (mode == PACKED_444) /* packed mode */
2168 time_per_byte = time_per_pixel/4;
2169 else if (mode == PLANAR_420_8BPC)
2170 time_per_byte = time_per_pixel;
2171 else if (mode == PLANAR_420_10BPC) /* p010 */
2172 time_per_byte = time_per_pixel * 819/1024;
2173
2174 if (time_per_byte == 0)
2175 time_per_byte = 1;
2176
2177 small_free_entry = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry;
2178 max_free_entry = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;
2179 buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */
2180 max_scaled_time = buf_lh_capability - urgent_watermark;
2181 return max_scaled_time;
2182}
2183
2184void dcn20_set_mcif_arb_params(
2185 struct dc *dc,
2186 struct dc_state *context,
2187 display_e2e_pipe_params_st *pipes,
2188 int pipe_cnt)
2189{
2190 enum mmhubbub_wbif_mode wbif_mode;
2191 struct mcif_arb_params *wb_arb_params;
2192 int i, j, k, dwb_pipe;
2193
2194 /* Writeback MCIF_WB arbitration parameters */
2195 dwb_pipe = 0;
2196 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2197
2198 if (!context->res_ctx.pipe_ctx[i].stream)
2199 continue;
2200
2201 for (j = 0; j < MAX_DWB_PIPES; j++) {
2202 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)
2203 continue;
2204
2205 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
2206 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
2207
2208 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {
2209 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
2210 wbif_mode = PLANAR_420_8BPC;
2211 else
2212 wbif_mode = PLANAR_420_10BPC;
2213 } else
2214 wbif_mode = PACKED_444;
2215
2216 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
2217 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2218 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2219 }
2220 wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* 4 bit fraction, ms */
2221 wb_arb_params->slice_lines = 32;
2222 wb_arb_params->arbitration_slice = 2;
2223 wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
2224 wbif_mode,
2225 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
2226
2227 dwb_pipe++;
2228
2229 if (dwb_pipe >= MAX_DWB_PIPES)
2230 return;
2231 }
2232 if (dwb_pipe >= MAX_DWB_PIPES)
2233 return;
2234 }
2235}
2236
b6bfba6c 2237bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
0ba37b20
DL		 2238{
2239 int i;
2240
2241 /* Validate DSC config, dsc count validation is already done */
2242 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2243 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
2244 struct dc_stream_state *stream = pipe_ctx->stream;
2245 struct dsc_config dsc_cfg;
b1f6d01c
DL		 2246 struct pipe_ctx *odm_pipe;
2247 int opp_cnt = 1;
2248
2249 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
2250 opp_cnt++;
0ba37b20
DL		 2251
2252 /* Only need to validate top pipe */
b1f6d01c 2253 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
0ba37b20
DL		 2254 continue;
2255
b1f6d01c
DL		 2256 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
2257 + stream->timing.h_border_right) / opp_cnt;
0ba37b20
DL		 2258 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
2259 + stream->timing.v_border_bottom;
0ba37b20
DL		 2260 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
2261 dsc_cfg.color_depth = stream->timing.display_color_depth;
2262 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
b1f6d01c 2263 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
0ba37b20
DL		 2264
2265 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
2266 return false;
2267 }
2268 return true;
2269}
0ba37b20 2270
b6bfba6c 2271struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
c681491a
JL		 2272 struct resource_context *res_ctx,
2273 const struct resource_pool *pool,
2274 const struct pipe_ctx *primary_pipe)
2275{
2276 struct pipe_ctx *secondary_pipe = NULL;
2277
2278 if (dc && primary_pipe) {
2279 int j;
2280 int preferred_pipe_idx = 0;
2281
2282 /* first check the prev dc state:
2283 * if this primary pipe has a bottom pipe in prev. state
2284 * and if the bottom pipe is still available (which it should be),
2285 * pick that pipe as secondary
b1f6d01c
DL		 2286 * Same logic applies for ODM pipes. Since mpo is not allowed with odm
2287 * check in else case.
c681491a
JL		 2288 */
2289 if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {
2290 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
2291 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2292 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2293 secondary_pipe->pipe_idx = preferred_pipe_idx;
2294 }
b1f6d01c
DL		 2295 } else if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {
2296 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;
2297 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2298 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2299 secondary_pipe->pipe_idx = preferred_pipe_idx;
2300 }
c681491a
JL		 2301 }
2302
2303 /*
2304 * if this primary pipe does not have a bottom pipe in prev. state
2305 * start backward and find a pipe that did not used to be a bottom pipe in
2306 * prev. dc state. This way we make sure we keep the same assignment as
2307 * last state and will not have to reprogram every pipe
2308 */
2309 if (secondary_pipe == NULL) {
2310 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
8b8eda01
DL		 2311 if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL
2312 && dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) {
c681491a
JL		 2313 preferred_pipe_idx = j;
2314
2315 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2316 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2317 secondary_pipe->pipe_idx = preferred_pipe_idx;
2318 break;
2319 }
2320 }
2321 }
2322 }
2323 /*
2324 * We should never hit this assert unless assignments are shuffled around
2325 * if this happens we will prob. hit a vsync tdr
2326 */
2327 ASSERT(secondary_pipe);
2328 /*
2329 * search backwards for the second pipe to keep pipe
2330 * assignment more consistent
2331 */
2332 if (secondary_pipe == NULL) {
2333 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2334 preferred_pipe_idx = j;
2335
2336 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2337 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2338 secondary_pipe->pipe_idx = preferred_pipe_idx;
2339 break;
2340 }
2341 }
2342 }
2343 }
2344
2345 return secondary_pipe;
2346}
2347
b6bfba6c 2348void dcn20_merge_pipes_for_validate(
6de20237 2349 struct dc *dc,
b6bfba6c 2350 struct dc_state *context)
7ed4e635 2351{
b6bfba6c 2352 int i;
7ed4e635 2353
b1f6d01c
DL		 2354 /* merge previously split odm pipes since mode support needs to make the decision */
2355 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2356 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2357 struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;
2358
2359 if (pipe->prev_odm_pipe)
2360 continue;
2361
2362 pipe->next_odm_pipe = NULL;
2363 while (odm_pipe) {
2364 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
2365
2366 odm_pipe->plane_state = NULL;
2367 odm_pipe->stream = NULL;
2368 odm_pipe->top_pipe = NULL;
2369 odm_pipe->bottom_pipe = NULL;
2370 odm_pipe->prev_odm_pipe = NULL;
2371 odm_pipe->next_odm_pipe = NULL;
b1f6d01c
DL		 2372 if (odm_pipe->stream_res.dsc)
2373 release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
b1f6d01c
DL		 2374 /* Clear plane_res and stream_res */
2375 memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));
2376 memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));
2377 odm_pipe = next_odm_pipe;
2378 }
2379 if (pipe->plane_state)
2380 resource_build_scaling_params(pipe);
2381 }
2382
2383 /* merge previously mpc split pipes since mode support needs to make the decision */
7ed4e635
HW		 2384 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2385 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2386 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2387
2388 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
2389 continue;
2390
7ed4e635
HW		 2391 pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
2392 if (hsplit_pipe->bottom_pipe)
2393 hsplit_pipe->bottom_pipe->top_pipe = pipe;
2394 hsplit_pipe->plane_state = NULL;
2395 hsplit_pipe->stream = NULL;
2396 hsplit_pipe->top_pipe = NULL;
2397 hsplit_pipe->bottom_pipe = NULL;
b1f6d01c 2398
7ed4e635
HW		 2399 /* Clear plane_res and stream_res */
2400 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
2401 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
2402 if (pipe->plane_state)
2403 resource_build_scaling_params(pipe);
2404 }
b6bfba6c 2405}
7ed4e635 2406
b6bfba6c
DL		 2407int dcn20_validate_apply_pipe_split_flags(
2408 struct dc *dc,
2409 struct dc_state *context,
2410 int vlevel,
2411 bool *split)
2412{
b745ecdb 2413 int i, pipe_idx, vlevel_split;
b6bfba6c
DL		 2414 bool force_split = false;
2415 bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
7ed4e635 2416
b745ecdb 2417 /* Single display loop, exits if there is more than one display */
7ed4e635
HW		 2418 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2419 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2420 bool exit_loop = false;
2421
2422 if (!pipe->stream || pipe->top_pipe)
2423 continue;
2424
2425 if (dc->debug.force_single_disp_pipe_split) {
2426 if (!force_split)
2427 force_split = true;
2428 else {
2429 force_split = false;
2430 exit_loop = true;
2431 }
2432 }
2433 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP) {
2434 if (avoid_split)
2435 avoid_split = false;
2436 else {
2437 avoid_split = true;
2438 exit_loop = true;
2439 }
2440 }
2441 if (exit_loop)
2442 break;
2443 }
b6bfba6c
DL		 2444 /* TODO: fix dc bugs and remove this split threshold thing */
2445 if (context->stream_count > dc->res_pool->pipe_count / 2)
7ed4e635
HW		 2446 avoid_split = true;
2447
b745ecdb 2448 /* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */
b6bfba6c
DL		 2449 if (avoid_split) {
2450 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2451 if (!context->res_ctx.pipe_ctx[i].stream)
2452 continue;
2453
b745ecdb 2454 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
b6bfba6c
DL		 2455 if (context->bw_ctx.dml.vba.NoOfDPP[vlevel][0][pipe_idx] == 1)
2456 break;
2457 /* Impossible to not split this pipe */
b745ecdb
DL		 2458 if (vlevel > context->bw_ctx.dml.soc.num_states)
2459 vlevel = vlevel_split;
b6bfba6c
DL		 2460 pipe_idx++;
2461 }
2462 context->bw_ctx.dml.vba.maxMpcComb = 0;
2463 }
2464
b745ecdb 2465 /* Split loop sets which pipe should be split based on dml outputs and dc flags */
7ed4e635 2466 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
b6bfba6c
DL		 2467 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2468
7ed4e635
HW		 2469 if (!context->res_ctx.pipe_ctx[i].stream)
2470 continue;
b6bfba6c
DL		 2471
2472 if (force_split || context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] > 1)
2473 split[i] = true;
2474 if ((pipe->stream->view_format ==
2475 VIEW_3D_FORMAT_SIDE_BY_SIDE ||
2476 pipe->stream->view_format ==
2477 VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
2478 (pipe->stream->timing.timing_3d_format ==
2479 TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
2480 pipe->stream->timing.timing_3d_format ==
2481 TIMING_3D_FORMAT_SIDE_BY_SIDE))
2482 split[i] = true;
2483 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
2484 split[i] = true;
2485 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = true;
2486 }
78ea008b
DL		 2487 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx] =
2488 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
b6bfba6c
DL		 2489 /* Adjust dppclk when split is forced, do not bother with dispclk */
2490 if (split[i] && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)
2491 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
7ed4e635
HW		 2492 pipe_idx++;
2493 }
2494
b6bfba6c
DL		 2495 return vlevel;
2496}
2497
2498bool dcn20_fast_validate_bw(
2499 struct dc *dc,
2500 struct dc_state *context,
2501 display_e2e_pipe_params_st *pipes,
2502 int *pipe_cnt_out,
2503 int *pipe_split_from,
2504 int *vlevel_out)
2505{
2506 bool out = false;
2507 bool split[MAX_PIPES] = { false };
2508 int pipe_cnt, i, pipe_idx, vlevel;
2509
2510 ASSERT(pipes);
2511 if (!pipes)
2512 return false;
2513
2514 dcn20_merge_pipes_for_validate(dc, context);
2515
2f488884 2516 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes);
b6bfba6c
DL		 2517
2518 *pipe_cnt_out = pipe_cnt;
2519
2520 if (!pipe_cnt) {
2521 out = true;
2522 goto validate_out;
2523 }
2524
2525 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2526
2527 if (vlevel > context->bw_ctx.dml.soc.num_states)
2528 goto validate_fail;
2529
2530 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split);
2531
2532 /*initialize pipe_just_split_from to invalid idx*/
2533 for (i = 0; i < MAX_PIPES; i++)
2534 pipe_split_from[i] = -1;
2535
7ed4e635
HW		 2536 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2537 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2538 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
7ed4e635
HW		 2539
2540 if (!pipe->stream || pipe_split_from[i] >= 0)
2541 continue;
2542
2543 pipe_idx++;
2544
7ed4e635 2545 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
c681491a 2546 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
7ed4e635 2547 ASSERT(hsplit_pipe);
b1f6d01c 2548 if (!dcn20_split_stream_for_odm(
7ed4e635 2549 &context->res_ctx, dc->res_pool,
b1f6d01c 2550 pipe, hsplit_pipe))
7ed4e635
HW		 2551 goto validate_fail;
2552 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2553 dcn20_build_mapped_resource(dc, context, pipe->stream);
2554 }
2555
2556 if (!pipe->plane_state)
2557 continue;
2558 /* Skip 2nd half of already split pipe */
2559 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
2560 continue;
2561
02ce5a79
DL		 2562 /* We do not support mpo + odm at the moment */
2563 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
2564 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
2565 goto validate_fail;
2566
b6bfba6c 2567 if (split[i]) {
7ed4e635
HW		 2568 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
2569 /* pipe not split previously needs split */
c681491a 2570 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
b6bfba6c 2571 ASSERT(hsplit_pipe);
ff86391e
MS		 2572 if (!hsplit_pipe) {
2573 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2;
7ed4e635 2574 continue;
ff86391e 2575 }
b1f6d01c
DL		 2576 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2577 if (!dcn20_split_stream_for_odm(
2578 &context->res_ctx, dc->res_pool,
2579 pipe, hsplit_pipe))
2580 goto validate_fail;
387596ef 2581 dcn20_build_mapped_resource(dc, context, pipe->stream);
b1f6d01c
DL		 2582 } else
2583 dcn20_split_stream_for_mpc(
7ed4e635 2584 &context->res_ctx, dc->res_pool,
b1f6d01c 2585 pipe, hsplit_pipe);
7ed4e635
HW		 2586 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2587 }
02ce5a79 2588 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
7ed4e635
HW		 2589 /* merge should already have been done */
2590 ASSERT(0);
2591 }
2592 }
0ba37b20 2593 /* Actual dsc count per stream dsc validation*/
c84ad0d6 2594 if (!dcn20_validate_dsc(dc, context)) {
0ba37b20
DL		 2595 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2596 DML_FAIL_DSC_VALIDATION_FAILURE;
2597 goto validate_fail;
2598 }
7ed4e635 2599
6de20237 2600 *vlevel_out = vlevel;
42351c66 2601
6de20237
EY		 2602 out = true;
2603 goto validate_out;
2604
2605validate_fail:
2606 out = false;
2607
2608validate_out:
2609 return out;
2610}
2611
e2e316d5 2612static void dcn20_calculate_wm(
6de20237
EY		 2613 struct dc *dc, struct dc_state *context,
2614 display_e2e_pipe_params_st *pipes,
2615 int *out_pipe_cnt,
2616 int *pipe_split_from,
2617 int vlevel)
2618{
2619 int pipe_cnt, i, pipe_idx;
254eb07c 2620
7ed4e635 2621 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
41f03a6d
DL		 2622 if (!context->res_ctx.pipe_ctx[i].stream)
2623 continue;
7ed4e635 2624
41f03a6d
DL		 2625 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2626 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
7ed4e635 2627
41f03a6d
DL		 2628 if (pipe_split_from[i] < 0) {
2629 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2630 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
2631 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
2632 pipes[pipe_cnt].pipe.dest.odm_combine =
b6bfba6c 2633 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx];
41f03a6d
DL		 2634 else
2635 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2636 pipe_idx++;
2637 } else {
2638 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2639 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
2640 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
2641 pipes[pipe_cnt].pipe.dest.odm_combine =
b6bfba6c 2642 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]];
41f03a6d
DL		 2643 else
2644 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
7ed4e635 2645 }
6de20237 2646
41f03a6d
DL		 2647 if (dc->config.forced_clocks) {
2648 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2649 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
a6465d1f 2650 }
41f03a6d
DL		 2651 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
2652 pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2653 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
2654 pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2655
2656 pipe_cnt++;
2657 }
7ed4e635 2658
41f03a6d
DL		 2659 if (pipe_cnt != pipe_idx) {
2660 if (dc->res_pool->funcs->populate_dml_pipes)
2661 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2f488884 2662 context, pipes);
41f03a6d
DL		 2663 else
2664 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
2f488884 2665 context, pipes);
41f03a6d 2666 }
7ed4e635 2667
41f03a6d 2668 *out_pipe_cnt = pipe_cnt;
6de20237 2669
41f03a6d
DL		 2670 pipes[0].clks_cfg.voltage = vlevel;
2671 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2672 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2673
2674 /* only pipe 0 is read for voltage and dcf/soc clocks */
2675 if (vlevel < 1) {
2676 pipes[0].clks_cfg.voltage = 1;
2677 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
2678 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
2679 }
2680 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2681 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2682 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2683 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2684 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
4de094ee
BL		 2685 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2686 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
b617b265 2687 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
41f03a6d
DL		 2688
2689 if (vlevel < 2) {
2690 pipes[0].clks_cfg.voltage = 2;
2691 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2692 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2693 }
2694 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2695 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2696 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2697 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2698 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
4de094ee
BL		 2699 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2700 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
41f03a6d
DL		 2701
2702 if (vlevel < 3) {
2703 pipes[0].clks_cfg.voltage = 3;
2704 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2705 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2706 }
2707 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2708 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2709 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2710 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2711 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
4de094ee
BL		 2712 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2713 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
41f03a6d
DL		 2714
2715 pipes[0].clks_cfg.voltage = vlevel;
2716 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2717 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2718 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2719 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2720 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2721 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2722 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
4de094ee
BL		 2723 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2724 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
6de20237
EY		 2725}
2726
2727void dcn20_calculate_dlg_params(
2728 struct dc *dc, struct dc_state *context,
2729 display_e2e_pipe_params_st *pipes,
2730 int pipe_cnt,
2731 int vlevel)
2732{
41f03a6d
DL		 2733 int i, j, pipe_idx, pipe_idx_unsplit;
2734 bool visited[MAX_PIPES] = { 0 };
8e27a2d4 2735
7ed4e635
HW		 2736 /* Writeback MCIF_WB arbitration parameters */
2737 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
2738
2739 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
2740 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
2741 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
173932de 2742 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
7ed4e635 2743 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
799c5b9c 2744 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
7ed4e635
HW		 2745 context->bw_ctx.bw.dcn.clk.p_state_change_support =
2746 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
2747 != dm_dram_clock_change_unsupported;
2748 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
2749
41f03a6d
DL		 2750 /*
2751 * An artifact of dml pipe split/odm is that pipes get merged back together for
2752 * calculation. Therefore we need to only extract for first pipe in ascending index order
2753 * and copy into the other split half.
2754 */
2755 for (i = 0, pipe_idx = 0, pipe_idx_unsplit = 0; i < dc->res_pool->pipe_count; i++) {
2756 if (!context->res_ctx.pipe_ctx[i].stream)
2757 continue;
6de20237 2758
41f03a6d 2759 if (!visited[pipe_idx]) {
74df06dd
DL		 2760 display_pipe_source_params_st *src = &pipes[pipe_idx].pipe.src;
2761 display_pipe_dest_params_st *dst = &pipes[pipe_idx].pipe.dest;
41f03a6d
DL		 2762
2763 dst->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
2764 dst->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
2765 dst->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
2766 dst->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
2767 /*
2768 * j iterates inside pipes array, unlike i which iterates inside
2769 * pipe_ctx array
2770 */
2771 if (src->is_hsplit)
2772 for (j = pipe_idx + 1; j < pipe_cnt; j++) {
2773 display_pipe_source_params_st *src_j = &pipes[j].pipe.src;
2774 display_pipe_dest_params_st *dst_j = &pipes[j].pipe.dest;
2775
2776 if (src_j->is_hsplit && !visited[j]
2777 && src->hsplit_grp == src_j->hsplit_grp) {
2778 dst_j->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
2779 dst_j->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
2780 dst_j->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
2781 dst_j->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
2782 visited[j] = true;
2783 }
2784 }
2785 visited[pipe_idx] = true;
2786 pipe_idx_unsplit++;
2787 }
2788 pipe_idx++;
2789 }
42351c66 2790
7ed4e635
HW		 2791 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2792 if (!context->res_ctx.pipe_ctx[i].stream)
2793 continue;
7ed4e635
HW		 2794 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2795 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
2796 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
2797 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
41f03a6d 2798 ASSERT(visited[pipe_idx]);
7ed4e635
HW		 2799 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
2800 pipe_idx++;
2801 }
925f566c
CL		 2802 /*save a original dppclock copy*/
2803 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
2804 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
41f03a6d
DL		 2805 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
2806 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
7ed4e635
HW		 2807
2808 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2809 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
2810
2811 if (!context->res_ctx.pipe_ctx[i].stream)
2812 continue;
2813
2814 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
2815 &context->res_ctx.pipe_ctx[i].dlg_regs,
2816 &context->res_ctx.pipe_ctx[i].ttu_regs,
2817 pipes,
2818 pipe_cnt,
2819 pipe_idx,
2820 cstate_en,
f82c916c
CL		 2821 context->bw_ctx.bw.dcn.clk.p_state_change_support,
2822 false, false, false);
254eb07c 2823
7ed4e635
HW		 2824 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
2825 &context->res_ctx.pipe_ctx[i].rq_regs,
2826 pipes[pipe_idx].pipe);
2827 pipe_idx++;
2828 }
6de20237
EY		 2829}
2830
057fc695 2831static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
6de20237
EY		 2832 bool fast_validate)
2833{
2834 bool out = false;
2835
2836 BW_VAL_TRACE_SETUP();
2837
2838 int vlevel = 0;
2839 int pipe_split_from[MAX_PIPES];
2840 int pipe_cnt = 0;
2841 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2842 DC_LOGGER_INIT(dc->ctx->logger);
2843
2844 BW_VAL_TRACE_COUNT();
2845
5e335add
EY		 2846 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
2847
2848 if (pipe_cnt == 0)
2849 goto validate_out;
6de20237
EY		 2850
2851 if (!out)
2852 goto validate_fail;
2853
2854 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2855
2856 if (fast_validate) {
2857 BW_VAL_TRACE_SKIP(fast);
2858 goto validate_out;
2859 }
2860
2861 dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
2862 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2863
2864 BW_VAL_TRACE_END_WATERMARKS();
7ed4e635 2865
254eb07c 2866 goto validate_out;
7ed4e635
HW		 2867
2868validate_fail:
00999d99
DL		 2869 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2870 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
254eb07c 2871
42351c66 2872 BW_VAL_TRACE_SKIP(fail);
254eb07c
JA		 2873 out = false;
2874
2875validate_out:
7ed4e635 2876 kfree(pipes);
254eb07c 2877
42351c66
JA		 2878 BW_VAL_TRACE_FINISH();
2879
254eb07c 2880 return out;
7ed4e635
HW		 2881}
2882
057fc695
JL		 2883
2884bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
2885 bool fast_validate)
2886{
2887 bool voltage_supported = false;
2888 bool full_pstate_supported = false;
2889 bool dummy_pstate_supported = false;
2890 double p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
5622b2d6 2891 context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support = dc->debug.disable_dram_clock_change_vactive_support;
057fc695
JL		 2892
2893 if (fast_validate)
2894 return dcn20_validate_bandwidth_internal(dc, context, true);
2895
2896
2897 // Best case, we support full UCLK switch latency
2898 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
2899 full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
2900
2901 if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
2902 (voltage_supported && full_pstate_supported)) {
2903 context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
2904 goto restore_dml_state;
2905 }
2906
b9e8d95a 2907 // Fallback: Try to only support G6 temperature read latency
057fc695
JL		 2908 context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
2909
2910 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
2911 dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
2912
2913 if (voltage_supported && dummy_pstate_supported) {
2914 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
2915 goto restore_dml_state;
2916 }
2917
b9e8d95a 2918 // ERROR: fallback is supposed to always work.
057fc695
JL		 2919 ASSERT(false);
2920
2921restore_dml_state:
057fc695
JL		 2922 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
2923
2924 return voltage_supported;
2925}
2926
7ed4e635
HW		 2927struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
2928 struct dc_state *state,
2929 const struct resource_pool *pool,
2930 struct dc_stream_state *stream)
2931{
2932 struct resource_context *res_ctx = &state->res_ctx;
2933 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
2934 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
2935
2936 if (!head_pipe)
2937 ASSERT(0);
2938
2939 if (!idle_pipe)
7a17c8ce 2940 return NULL;
7ed4e635
HW		 2941
2942 idle_pipe->stream = head_pipe->stream;
2943 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
2944 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
2945
2946 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
2947 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
2948 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
2949 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
2950
2951 return idle_pipe;
2952}
2953
2954bool dcn20_get_dcc_compression_cap(const struct dc *dc,
2955 const struct dc_dcc_surface_param *input,
2956 struct dc_surface_dcc_cap *output)
2957{
2958 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
2959 dc->res_pool->hubbub,
2960 input,
2961 output);
2962}
2963
2964static void dcn20_destroy_resource_pool(struct resource_pool **pool)
2965{
2966 struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);
2967
d9e32672 2968 dcn20_resource_destruct(dcn20_pool);
7ed4e635
HW		 2969 kfree(dcn20_pool);
2970 *pool = NULL;
2971}
2972
2973
2974static struct dc_cap_funcs cap_funcs = {
2975 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
2976};
2977
2978
2979enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state)
2980{
2981 enum dc_status result = DC_OK;
2982
2983 enum surface_pixel_format surf_pix_format = plane_state->format;
2984 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
2985
2986 enum swizzle_mode_values swizzle = DC_SW_LINEAR;
2987
2988 if (bpp == 64)
2989 swizzle = DC_SW_64KB_D;
2990 else
2991 swizzle = DC_SW_64KB_S;
2992
2993 plane_state->tiling_info.gfx9.swizzle = swizzle;
2994 return result;
2995}
2996
2997static struct resource_funcs dcn20_res_pool_funcs = {
2998 .destroy = dcn20_destroy_resource_pool,
2999 .link_enc_create = dcn20_link_encoder_create,
3000 .validate_bandwidth = dcn20_validate_bandwidth,
7ed4e635
HW		 3001 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
3002 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
3003 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
3004 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
3005 .get_default_swizzle_mode = dcn20_get_default_swizzle_mode,
c9ae6e16 3006 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
b6bfba6c 3007 .populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
278141f5 3008 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
7ed4e635
HW		 3009};
3010
bb21290f
CL		 3011bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
3012{
3013 int i;
3014 uint32_t pipe_count = pool->res_cap->num_dwb;
3015
bb21290f
CL		 3016 for (i = 0; i < pipe_count; i++) {
3017 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
3018 GFP_KERNEL);
3019
3020 if (!dwbc20) {
3021 dm_error("DC: failed to create dwbc20!\n");
3022 return false;
3023 }
3024 dcn20_dwbc_construct(dwbc20, ctx,
3025 &dwbc20_regs[i],
3026 &dwbc20_shift,
3027 &dwbc20_mask,
3028 i);
3029 pool->dwbc[i] = &dwbc20->base;
3030 }
3031 return true;
3032}
3033
3034bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
3035{
3036 int i;
3037 uint32_t pipe_count = pool->res_cap->num_dwb;
3038
3039 ASSERT(pipe_count > 0);
3040
3041 for (i = 0; i < pipe_count; i++) {
3042 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub),
3043 GFP_KERNEL);
3044
3045 if (!mcif_wb20) {
3046 dm_error("DC: failed to create mcif_wb20!\n");
3047 return false;
3048 }
3049
3050 dcn20_mmhubbub_construct(mcif_wb20, ctx,
3051 &mcif_wb20_regs[i],
3052 &mcif_wb20_shift,
3053 &mcif_wb20_mask,
3054 i);
3055
3056 pool->mcif_wb[i] = &mcif_wb20->base;
3057 }
3058 return true;
3059}
3060
44e149bb 3061static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
7ed4e635
HW		 3062{
3063 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
3064
3065 if (!pp_smu)
3066 return pp_smu;
3067
3068 dm_pp_get_funcs(ctx, pp_smu);
3069
3070 if (pp_smu->ctx.ver != PP_SMU_VER_NV)
3071 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
3072
3073 return pp_smu;
3074}
3075
44e149bb 3076static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
7ed4e635
HW		 3077{
3078 if (pp_smu && *pp_smu) {
3079 kfree(*pp_smu);
3080 *pp_smu = NULL;
3081 }
3082}
3083
44ce0cd3 3084void dcn20_cap_soc_clocks(
7ed4e635
HW		 3085 struct _vcs_dpi_soc_bounding_box_st *bb,
3086 struct pp_smu_nv_clock_table max_clocks)
3087{
3088 int i;
3089
3090 // First pass - cap all clocks higher than the reported max
3091 for (i = 0; i < bb->num_states; i++) {
3092 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
3093 && max_clocks.dcfClockInKhz != 0)
3094 bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
3095
3096 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
3097 && max_clocks.uClockInKhz != 0)
3098 bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
3099
3100 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
3101 && max_clocks.fabricClockInKhz != 0)
3102 bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
3103
3104 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
3105 && max_clocks.displayClockInKhz != 0)
3106 bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
3107
3108 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
3109 && max_clocks.dppClockInKhz != 0)
3110 bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
3111
3112 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
3113 && max_clocks.phyClockInKhz != 0)
3114 bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
3115
3116 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
3117 && max_clocks.socClockInKhz != 0)
3118 bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
3119
3120 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
3121 && max_clocks.dscClockInKhz != 0)
3122 bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
3123 }
3124
3125 // Second pass - remove all duplicate clock states
3126 for (i = bb->num_states - 1; i > 1; i--) {
3127 bool duplicate = true;
3128
3129 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz)
3130 duplicate = false;
3131 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz)
3132 duplicate = false;
3133 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz)
3134 duplicate = false;
3135 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts)
3136 duplicate = false;
3137 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz)
3138 duplicate = false;
3139 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz)
3140 duplicate = false;
3141 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz)
3142 duplicate = false;
3143 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz)
3144 duplicate = false;
3145
3146 if (duplicate)
3147 bb->num_states--;
3148 }
3149}
3150
44ce0cd3 3151void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
7ed4e635
HW		 3152 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
3153{
960b6f4f 3154 struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES];
f18bc4e5 3155 int i;
7ed4e635 3156 int num_calculated_states = 0;
f18bc4e5 3157 int min_dcfclk = 0;
7ed4e635
HW		 3158
3159 if (num_states == 0)
3160 return;
3161
960b6f4f
RR		 3162 memset(calculated_states, 0, sizeof(calculated_states));
3163
f18bc4e5
JL		 3164 if (dc->bb_overrides.min_dcfclk_mhz > 0)
3165 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
6ce2427d
AL		 3166 else {
3167 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
3168 min_dcfclk = 310;
3169 else
3170 // Accounting for SOC/DCF relationship, we can go as high as
3171 // 506Mhz in Vmin.
3172 min_dcfclk = 506;
3173 }
f18bc4e5 3174
7ed4e635 3175 for (i = 0; i < num_states; i++) {
f18bc4e5
JL		 3176 int min_fclk_required_by_uclk;
3177 calculated_states[i].state = i;
3178 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
7ed4e635 3179
5d36f783 3180 // FCLK:UCLK ratio is 1.08
5f65ae34 3181 min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32);
7ed4e635 3182
f18bc4e5
JL		 3183 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
3184 min_dcfclk : min_fclk_required_by_uclk;
7ed4e635 3185
f18bc4e5
JL		 3186 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
3187 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
7ed4e635 3188
f18bc4e5
JL		 3189 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
3190 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
7ed4e635 3191
f18bc4e5
JL		 3192 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
3193 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
3194 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
7ed4e635 3195
f18bc4e5 3196 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
7ed4e635 3197
f18bc4e5 3198 num_calculated_states++;
7ed4e635
HW		 3199 }
3200
6da16270
JL		 3201 calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
3202 calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
3203 calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
3204
7ed4e635
HW		 3205 memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
3206 bb->num_states = num_calculated_states;
f18bc4e5
JL		 3207
3208 // Duplicate the last state, DML always an extra state identical to max state to work
3209 memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st));
3210 bb->clock_limits[num_calculated_states].state = bb->num_states;
7ed4e635
HW		 3211}
3212
44ce0cd3 3213void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
7ed4e635 3214{
6ca3928d 3215 DC_FP_START();
7ed4e635
HW		 3216 if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
3217 && dc->bb_overrides.sr_exit_time_ns) {
3218 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
3219 }
3220
3221 if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
3222 != dc->bb_overrides.sr_enter_plus_exit_time_ns
3223 && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
3224 bb->sr_enter_plus_exit_time_us =
3225 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
3226 }
3227
3228 if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
3229 && dc->bb_overrides.urgent_latency_ns) {
3230 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
3231 }
3232
3233 if ((int)(bb->dram_clock_change_latency_us * 1000)
3234 != dc->bb_overrides.dram_clock_change_latency_ns
3235 && dc->bb_overrides.dram_clock_change_latency_ns) {
3236 bb->dram_clock_change_latency_us =
3237 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
3238 }
6ca3928d 3239 DC_FP_END();
7ed4e635
HW		 3240}
3241
675a9e38
LL		 3242static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
3243 uint32_t hw_internal_rev)
3244{
3245 if (ASICREV_IS_NAVI12_P(hw_internal_rev))
3246 return &dcn2_0_nv12_soc;
3247
3248 return &dcn2_0_soc;
3249}
3250
3251static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(
3252 uint32_t hw_internal_rev)
3253{
72b741af
Z		 3254 /* NV14 */
3255 if (ASICREV_IS_NAVI14_M(hw_internal_rev))
3256 return &dcn2_0_nv14_ip;
3257
675a9e38
LL		 3258 /* NV12 and NV10 */
3259 return &dcn2_0_ip;
3260}
3261
3262static enum dml_project get_dml_project_version(uint32_t hw_internal_rev)
3263{
3264 return DML_PROJECT_NAVI10v2;
3265}
3266
7ed4e635
HW		 3267#define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
3268#define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
3269
3270static bool init_soc_bounding_box(struct dc *dc,
3271 struct dcn20_resource_pool *pool)
3272{
3273 const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
675a9e38
LL		 3274 struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3275 get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);
3276 struct _vcs_dpi_ip_params_st *loaded_ip =
3277 get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);
3278
7ed4e635
HW		 3279 DC_LOGGER_INIT(dc->ctx->logger);
3280
3e0c55f3
ZL		 3281 /* TODO: upstream NV12 bounding box when its launched */
3282 if (!bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
7ed4e635
HW		 3283 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
3284 return false;
3285 }
3286
3e0c55f3 3287 if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
7ed4e635
HW		 3288 int i;
3289
675a9e38 3290 dcn2_0_nv12_soc.sr_exit_time_us =
7ed4e635 3291 fixed16_to_double_to_cpu(bb->sr_exit_time_us);
675a9e38 3292 dcn2_0_nv12_soc.sr_enter_plus_exit_time_us =
7ed4e635 3293 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us);
675a9e38 3294 dcn2_0_nv12_soc.urgent_latency_us =
7ed4e635 3295 fixed16_to_double_to_cpu(bb->urgent_latency_us);
675a9e38 3296 dcn2_0_nv12_soc.urgent_latency_pixel_data_only_us =
7ed4e635 3297 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us);
675a9e38 3298 dcn2_0_nv12_soc.urgent_latency_pixel_mixed_with_vm_data_us =
7ed4e635 3299 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us);
675a9e38 3300 dcn2_0_nv12_soc.urgent_latency_vm_data_only_us =
7ed4e635 3301 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us);
675a9e38 3302 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
7ed4e635 3303 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes);
675a9e38 3304 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
7ed4e635 3305 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes);
675a9e38 3306 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
7ed4e635 3307 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes);
675a9e38 3308 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
7ed4e635 3309 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only);
675a9e38 3310 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
7ed4e635 3311 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm);
675a9e38 3312 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
7ed4e635 3313 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only);
675a9e38 3314 dcn2_0_nv12_soc.max_avg_sdp_bw_use_normal_percent =
7ed4e635 3315 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent);
675a9e38 3316 dcn2_0_nv12_soc.max_avg_dram_bw_use_normal_percent =
7ed4e635 3317 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent);
675a9e38 3318 dcn2_0_nv12_soc.writeback_latency_us =
7ed4e635 3319 fixed16_to_double_to_cpu(bb->writeback_latency_us);
675a9e38 3320 dcn2_0_nv12_soc.ideal_dram_bw_after_urgent_percent =
7ed4e635 3321 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent);
675a9e38 3322 dcn2_0_nv12_soc.max_request_size_bytes =
7ed4e635 3323 le32_to_cpu(bb->max_request_size_bytes);
675a9e38 3324 dcn2_0_nv12_soc.dram_channel_width_bytes =
7ed4e635 3325 le32_to_cpu(bb->dram_channel_width_bytes);
675a9e38 3326 dcn2_0_nv12_soc.fabric_datapath_to_dcn_data_return_bytes =
7ed4e635 3327 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes);
675a9e38 3328 dcn2_0_nv12_soc.dcn_downspread_percent =
7ed4e635 3329 fixed16_to_double_to_cpu(bb->dcn_downspread_percent);
675a9e38 3330 dcn2_0_nv12_soc.downspread_percent =
7ed4e635 3331 fixed16_to_double_to_cpu(bb->downspread_percent);
675a9e38 3332 dcn2_0_nv12_soc.dram_page_open_time_ns =
7ed4e635 3333 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns);
675a9e38 3334 dcn2_0_nv12_soc.dram_rw_turnaround_time_ns =
7ed4e635 3335 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns);
675a9e38 3336 dcn2_0_nv12_soc.dram_return_buffer_per_channel_bytes =
7ed4e635 3337 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes);
675a9e38 3338 dcn2_0_nv12_soc.round_trip_ping_latency_dcfclk_cycles =
7ed4e635 3339 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles);
675a9e38 3340 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_bytes =
7ed4e635 3341 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes);
675a9e38 3342 dcn2_0_nv12_soc.channel_interleave_bytes =
7ed4e635 3343 le32_to_cpu(bb->channel_interleave_bytes);
675a9e38 3344 dcn2_0_nv12_soc.num_banks =
7ed4e635 3345 le32_to_cpu(bb->num_banks);
675a9e38 3346 dcn2_0_nv12_soc.num_chans =
7ed4e635 3347 le32_to_cpu(bb->num_chans);
675a9e38 3348 dcn2_0_nv12_soc.vmm_page_size_bytes =
7ed4e635 3349 le32_to_cpu(bb->vmm_page_size_bytes);
675a9e38 3350 dcn2_0_nv12_soc.dram_clock_change_latency_us =
7ed4e635 3351 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
675a9e38
LL		 3352 // HACK!! Lower uclock latency switch time so we don't switch
3353 dcn2_0_nv12_soc.dram_clock_change_latency_us = 10;
3354 dcn2_0_nv12_soc.writeback_dram_clock_change_latency_us =
7ed4e635 3355 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
675a9e38 3356 dcn2_0_nv12_soc.return_bus_width_bytes =
7ed4e635 3357 le32_to_cpu(bb->return_bus_width_bytes);
675a9e38 3358 dcn2_0_nv12_soc.dispclk_dppclk_vco_speed_mhz =
7ed4e635 3359 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz);
675a9e38 3360 dcn2_0_nv12_soc.xfc_bus_transport_time_us =
7ed4e635 3361 le32_to_cpu(bb->xfc_bus_transport_time_us);
675a9e38 3362 dcn2_0_nv12_soc.xfc_xbuf_latency_tolerance_us =
7ed4e635 3363 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us);
675a9e38 3364 dcn2_0_nv12_soc.use_urgent_burst_bw =
7ed4e635 3365 le32_to_cpu(bb->use_urgent_burst_bw);
675a9e38 3366 dcn2_0_nv12_soc.num_states =
7ed4e635
HW		 3367 le32_to_cpu(bb->num_states);
3368
675a9e38
LL		 3369 for (i = 0; i < dcn2_0_nv12_soc.num_states; i++) {
3370 dcn2_0_nv12_soc.clock_limits[i].state =
7ed4e635 3371 le32_to_cpu(bb->clock_limits[i].state);
675a9e38 3372 dcn2_0_nv12_soc.clock_limits[i].dcfclk_mhz =
7ed4e635 3373 fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz);
675a9e38 3374 dcn2_0_nv12_soc.clock_limits[i].fabricclk_mhz =
7ed4e635 3375 fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz);
675a9e38 3376 dcn2_0_nv12_soc.clock_limits[i].dispclk_mhz =
7ed4e635 3377 fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz);
675a9e38 3378 dcn2_0_nv12_soc.clock_limits[i].dppclk_mhz =
7ed4e635 3379 fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz);
675a9e38 3380 dcn2_0_nv12_soc.clock_limits[i].phyclk_mhz =
7ed4e635 3381 fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz);
675a9e38 3382 dcn2_0_nv12_soc.clock_limits[i].socclk_mhz =
7ed4e635 3383 fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz);
675a9e38 3384 dcn2_0_nv12_soc.clock_limits[i].dscclk_mhz =
7ed4e635 3385 fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz);
675a9e38 3386 dcn2_0_nv12_soc.clock_limits[i].dram_speed_mts =
7ed4e635
HW		 3387 fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
3388 }
3389 }
3390
3391 if (pool->base.pp_smu) {
3392 struct pp_smu_nv_clock_table max_clocks = {0};
3393 unsigned int uclk_states[8] = {0};
3394 unsigned int num_states = 0;
3395 enum pp_smu_status status;
3396 bool clock_limits_available = false;
3397 bool uclk_states_available = false;
3398
3399 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
3400 status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
3401 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
3402
3403 uclk_states_available = (status == PP_SMU_RESULT_OK);
3404 }
3405
3406 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
3407 status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
3408 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
c2ad17c3
AW		 3409 /* SMU cannot set DCF clock to anything equal to or higher than SOC clock
3410 */
3411 if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
3412 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
7ed4e635
HW		 3413 clock_limits_available = (status == PP_SMU_RESULT_OK);
3414 }
3415
c2ad17c3 3416 if (clock_limits_available && uclk_states_available && num_states)
44ce0cd3 3417 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
7ed4e635 3418 else if (clock_limits_available)
44ce0cd3 3419 dcn20_cap_soc_clocks(loaded_bb, max_clocks);
7ed4e635
HW		 3420 }
3421
675a9e38
LL		 3422 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
3423 loaded_ip->max_num_dpp = pool->base.pipe_count;
44ce0cd3 3424 dcn20_patch_bounding_box(dc, loaded_bb);
7ed4e635
HW		 3425
3426 return true;
3427}
3428
d9e32672 3429static bool dcn20_resource_construct(
7ed4e635
HW		 3430 uint8_t num_virtual_links,
3431 struct dc *dc,
3432 struct dcn20_resource_pool *pool)
3433{
3434 int i;
3435 struct dc_context *ctx = dc->ctx;
3436 struct irq_service_init_data init_data;
d9a07577 3437 struct ddc_service_init_data ddc_init_data;
675a9e38
LL		 3438 struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3439 get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);
3440 struct _vcs_dpi_ip_params_st *loaded_ip =
3441 get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev);
3442 enum dml_project dml_project_version =
3443 get_dml_project_version(ctx->asic_id.hw_internal_rev);
7ed4e635
HW		 3444
3445 ctx->dc_bios->regs = &bios_regs;
7ed4e635
HW		 3446 pool->base.funcs = &dcn20_res_pool_funcs;
3447
2ebe1773
BL		 3448 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
3449 pool->base.res_cap = &res_cap_nv14;
3450 pool->base.pipe_count = 5;
3451 pool->base.mpcc_count = 5;
3452 } else {
3453 pool->base.res_cap = &res_cap_nv10;
3454 pool->base.pipe_count = 6;
3455 pool->base.mpcc_count = 6;
3456 }
7ed4e635
HW		 3457 /*************************************************
3458 * Resource + asic cap harcoding *
3459 *************************************************/
3460 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
3461
7ed4e635
HW		 3462 dc->caps.max_downscale_ratio = 200;
3463 dc->caps.i2c_speed_in_khz = 100;
3464 dc->caps.max_cursor_size = 256;
3465 dc->caps.dmdata_alloc_size = 2048;
3466
3467 dc->caps.max_slave_planes = 1;
3468 dc->caps.post_blend_color_processing = true;
3469 dc->caps.force_dp_tps4_for_cp2520 = true;
3470 dc->caps.hw_3d_lut = true;
f6040a43 3471 dc->caps.extended_aux_timeout_support = true;
7ed4e635 3472
803a1412 3473 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) {
7ed4e635 3474 dc->debug = debug_defaults_drv;
803a1412
ES		 3475 } else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
3476 pool->base.pipe_count = 4;
7ed4e635
HW		 3477 pool->base.mpcc_count = pool->base.pipe_count;
3478 dc->debug = debug_defaults_diags;
803a1412 3479 } else {
7ed4e635 3480 dc->debug = debug_defaults_diags;
803a1412 3481 }
7ed4e635
HW		 3482 //dcn2.0x
3483 dc->work_arounds.dedcn20_305_wa = true;
3484
3485 // Init the vm_helper
3486 if (dc->vm_helper)
bda9afda 3487 vm_helper_init(dc->vm_helper, 16);
7ed4e635
HW		 3488
3489 /*************************************************
3490 * Create resources *
3491 *************************************************/
3492
3493 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
3494 dcn20_clock_source_create(ctx, ctx->dc_bios,
3495 CLOCK_SOURCE_COMBO_PHY_PLL0,
3496 &clk_src_regs[0], false);
3497 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
3498 dcn20_clock_source_create(ctx, ctx->dc_bios,
3499 CLOCK_SOURCE_COMBO_PHY_PLL1,
3500 &clk_src_regs[1], false);
3501 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
3502 dcn20_clock_source_create(ctx, ctx->dc_bios,
3503 CLOCK_SOURCE_COMBO_PHY_PLL2,
3504 &clk_src_regs[2], false);
3505 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
3506 dcn20_clock_source_create(ctx, ctx->dc_bios,
3507 CLOCK_SOURCE_COMBO_PHY_PLL3,
3508 &clk_src_regs[3], false);
3509 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
3510 dcn20_clock_source_create(ctx, ctx->dc_bios,
3511 CLOCK_SOURCE_COMBO_PHY_PLL4,
3512 &clk_src_regs[4], false);
3513 pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =
3514 dcn20_clock_source_create(ctx, ctx->dc_bios,
3515 CLOCK_SOURCE_COMBO_PHY_PLL5,
3516 &clk_src_regs[5], false);
3517 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;
3518 /* todo: not reuse phy_pll registers */
3519 pool->base.dp_clock_source =
3520 dcn20_clock_source_create(ctx, ctx->dc_bios,
3521 CLOCK_SOURCE_ID_DP_DTO,
3522 &clk_src_regs[0], true);
3523
3524 for (i = 0; i < pool->base.clk_src_count; i++) {
3525 if (pool->base.clock_sources[i] == NULL) {
3526 dm_error("DC: failed to create clock sources!\n");
3527 BREAK_TO_DEBUGGER();
3528 goto create_fail;
3529 }
3530 }
3531
3532 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
3533 if (pool->base.dccg == NULL) {
3534 dm_error("DC: failed to create dccg!\n");
3535 BREAK_TO_DEBUGGER();
3536 goto create_fail;
3537 }
3538
3539 pool->base.dmcu = dcn20_dmcu_create(ctx,
3540 &dmcu_regs,
3541 &dmcu_shift,
3542 &dmcu_mask);
3543 if (pool->base.dmcu == NULL) {
3544 dm_error("DC: failed to create dmcu!\n");
3545 BREAK_TO_DEBUGGER();
3546 goto create_fail;
3547 }
3548
d7c29549 3549 pool->base.abm = dce_abm_create(ctx,
7ed4e635
HW		 3550 &abm_regs,
3551 &abm_shift,
3552 &abm_mask);
3553 if (pool->base.abm == NULL) {
3554 dm_error("DC: failed to create abm!\n");
3555 BREAK_TO_DEBUGGER();
3556 goto create_fail;
d7c29549 3557 }
7ed4e635
HW		 3558
3559 pool->base.pp_smu = dcn20_pp_smu_create(ctx);
3560
3561
3562 if (!init_soc_bounding_box(dc, pool)) {
3563 dm_error("DC: failed to initialize soc bounding box!\n");
3564 BREAK_TO_DEBUGGER();
3565 goto create_fail;
3566 }
3567
675a9e38 3568 dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version);
7ed4e635
HW		 3569
3570 if (!dc->debug.disable_pplib_wm_range) {
3571 struct pp_smu_wm_range_sets ranges = {0};
3572 int i = 0;
3573
3574 ranges.num_reader_wm_sets = 0;
3575
675a9e38 3576 if (loaded_bb->num_states == 1) {
7ed4e635
HW		 3577 ranges.reader_wm_sets[0].wm_inst = i;
3578 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3579 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3580 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3581 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3582
3583 ranges.num_reader_wm_sets = 1;
675a9e38
LL		 3584 } else if (loaded_bb->num_states > 1) {
3585 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
7ed4e635
HW		 3586 ranges.reader_wm_sets[i].wm_inst = i;
3587 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3588 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
675a9e38
LL		 3589 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
3590 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
7ed4e635
HW		 3591
3592 ranges.num_reader_wm_sets = i + 1;
3593 }
7ed4e635 3594
5d36f783
JL		 3595 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3596 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3597 }
7ed4e635
HW		 3598
3599 ranges.num_writer_wm_sets = 1;
3600
3601 ranges.writer_wm_sets[0].wm_inst = 0;
3602 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3603 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3604 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3605 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3606
3607 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
3608 if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
3609 pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);
3610 }
3611
3612 init_data.ctx = dc->ctx;
3613 pool->base.irqs = dal_irq_service_dcn20_create(&init_data);
3614 if (!pool->base.irqs)
3615 goto create_fail;
3616
3617 /* mem input -> ipp -> dpp -> opp -> TG */
3618 for (i = 0; i < pool->base.pipe_count; i++) {
3619 pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
3620 if (pool->base.hubps[i] == NULL) {
3621 BREAK_TO_DEBUGGER();
3622 dm_error(
3623 "DC: failed to create memory input!\n");
3624 goto create_fail;
3625 }
3626
3627 pool->base.ipps[i] = dcn20_ipp_create(ctx, i);
3628 if (pool->base.ipps[i] == NULL) {
3629 BREAK_TO_DEBUGGER();
3630 dm_error(
3631 "DC: failed to create input pixel processor!\n");
3632 goto create_fail;
3633 }
3634
3635 pool->base.dpps[i] = dcn20_dpp_create(ctx, i);
3636 if (pool->base.dpps[i] == NULL) {
3637 BREAK_TO_DEBUGGER();
3638 dm_error(
3639 "DC: failed to create dpps!\n");
3640 goto create_fail;
3641 }
3642 }
3643 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
3644 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i);
3645 if (pool->base.engines[i] == NULL) {
3646 BREAK_TO_DEBUGGER();
3647 dm_error(
3648 "DC:failed to create aux engine!!\n");
3649 goto create_fail;
3650 }
3651 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i);
3652 if (pool->base.hw_i2cs[i] == NULL) {
3653 BREAK_TO_DEBUGGER();
3654 dm_error(
3655 "DC:failed to create hw i2c!!\n");
3656 goto create_fail;
3657 }
3658 pool->base.sw_i2cs[i] = NULL;
3659 }
3660
3661 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
3662 pool->base.opps[i] = dcn20_opp_create(ctx, i);
3663 if (pool->base.opps[i] == NULL) {
3664 BREAK_TO_DEBUGGER();
3665 dm_error(
3666 "DC: failed to create output pixel processor!\n");
3667 goto create_fail;
3668 }
3669 }
3670
3671 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
3672 pool->base.timing_generators[i] = dcn20_timing_generator_create(
3673 ctx, i);
3674 if (pool->base.timing_generators[i] == NULL) {
3675 BREAK_TO_DEBUGGER();
3676 dm_error("DC: failed to create tg!\n");
3677 goto create_fail;
3678 }
3679 }
3680
3681 pool->base.timing_generator_count = i;
3682
3683 pool->base.mpc = dcn20_mpc_create(ctx);
3684 if (pool->base.mpc == NULL) {
3685 BREAK_TO_DEBUGGER();
3686 dm_error("DC: failed to create mpc!\n");
3687 goto create_fail;
3688 }
3689
3690 pool->base.hubbub = dcn20_hubbub_create(ctx);
3691 if (pool->base.hubbub == NULL) {
3692 BREAK_TO_DEBUGGER();
3693 dm_error("DC: failed to create hubbub!\n");
3694 goto create_fail;
3695 }
3696
97bda032
HW		 3697 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
3698 pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
3699 if (pool->base.dscs[i] == NULL) {
3700 BREAK_TO_DEBUGGER();
3701 dm_error("DC: failed to create display stream compressor %d!\n", i);
3702 goto create_fail;
3703 }
3704 }
7ed4e635 3705
bb21290f
CL		 3706 if (!dcn20_dwbc_create(ctx, &pool->base)) {
3707 BREAK_TO_DEBUGGER();
3708 dm_error("DC: failed to create dwbc!\n");
3709 goto create_fail;
3710 }
3711 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
3712 BREAK_TO_DEBUGGER();
3713 dm_error("DC: failed to create mcif_wb!\n");
3714 goto create_fail;
3715 }
3716
7ed4e635
HW		 3717 if (!resource_construct(num_virtual_links, dc, &pool->base,
3718 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
3719 &res_create_funcs : &res_create_maximus_funcs)))
3720 goto create_fail;
3721
3722 dcn20_hw_sequencer_construct(dc);
3723
3724 dc->caps.max_planes = pool->base.pipe_count;
3725
3726 for (i = 0; i < dc->caps.max_planes; ++i)
3727 dc->caps.planes[i] = plane_cap;
3728
3729 dc->cap_funcs = cap_funcs;
3730
d9a07577
JL		 3731 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
3732 ddc_init_data.ctx = dc->ctx;
3733 ddc_init_data.link = NULL;
3734 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
3735 ddc_init_data.id.enum_id = 0;
3736 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
3737 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
3738 } else {
3739 pool->base.oem_device = NULL;
3740 }
3741
7ed4e635
HW		 3742 return true;
3743
3744create_fail:
3745
d9e32672 3746 dcn20_resource_destruct(pool);
7ed4e635
HW		 3747
3748 return false;
3749}
3750
3751struct resource_pool *dcn20_create_resource_pool(
3752 const struct dc_init_data *init_data,
3753 struct dc *dc)
3754{
3755 struct dcn20_resource_pool *pool =
3756 kzalloc(sizeof(struct dcn20_resource_pool), GFP_KERNEL);
3757
3758 if (!pool)
3759 return NULL;
3760
d9e32672 3761 if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool))
7ed4e635
HW		 3762 return &pool->base;
3763
3764 BREAK_TO_DEBUGGER();
3765 kfree(pool);
3766 return NULL;
3767}
Linux 6.x block layer and io_uring tree(s)