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drm/amd/display: Soft reset DMUIF during DMUB reset
[linux-block.git] / drivers / gpu / drm / amd / display / dc / dcn20 / dcn20_resource.c
CommitLineData
7ed4e635
HW		 1/*
2* Copyright 2016 Advanced Micro Devices, Inc.
6ca3928d 3 * Copyright 2019 Raptor Engineering, LLC
7ed4e635
HW		 4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
d7929c1e
AD		 27#include <linux/slab.h>
28
7ed4e635
HW		 29#include "dm_services.h"
30#include "dc.h"
31
78c77382
AK		 32#include "dcn20_init.h"
33
7ed4e635
HW		 34#include "resource.h"
35#include "include/irq_service_interface.h"
36#include "dcn20/dcn20_resource.h"
37
38#include "dcn10/dcn10_hubp.h"
39#include "dcn10/dcn10_ipp.h"
40#include "dcn20_hubbub.h"
41#include "dcn20_mpc.h"
42#include "dcn20_hubp.h"
43#include "irq/dcn20/irq_service_dcn20.h"
44#include "dcn20_dpp.h"
45#include "dcn20_optc.h"
46#include "dcn20_hwseq.h"
47#include "dce110/dce110_hw_sequencer.h"
278141f5 48#include "dcn10/dcn10_resource.h"
7ed4e635
HW		 49#include "dcn20_opp.h"
50
97bda032 51#include "dcn20_dsc.h"
97bda032 52
7ed4e635
HW		 53#include "dcn20_link_encoder.h"
54#include "dcn20_stream_encoder.h"
55#include "dce/dce_clock_source.h"
56#include "dce/dce_audio.h"
57#include "dce/dce_hwseq.h"
58#include "virtual/virtual_stream_encoder.h"
59#include "dce110/dce110_resource.h"
60#include "dml/display_mode_vba.h"
61#include "dcn20_dccg.h"
62#include "dcn20_vmid.h"
d9a07577 63#include "dc_link_ddc.h"
7ed4e635
HW		 64
65#include "navi10_ip_offset.h"
66
67#include "dcn/dcn_2_0_0_offset.h"
68#include "dcn/dcn_2_0_0_sh_mask.h"
a771ded8
RL		 69#include "dpcs/dpcs_2_0_0_offset.h"
70#include "dpcs/dpcs_2_0_0_sh_mask.h"
7ed4e635
HW		 71
72#include "nbio/nbio_2_3_offset.h"
73
bb21290f
CL		 74#include "dcn20/dcn20_dwb.h"
75#include "dcn20/dcn20_mmhubbub.h"
76
7ed4e635
HW		 77#include "mmhub/mmhub_2_0_0_offset.h"
78#include "mmhub/mmhub_2_0_0_sh_mask.h"
79
80#include "reg_helper.h"
81#include "dce/dce_abm.h"
82#include "dce/dce_dmcu.h"
83#include "dce/dce_aux.h"
84#include "dce/dce_i2c.h"
85#include "vm_helper.h"
86
87#include "amdgpu_socbb.h"
88
7ed4e635
HW		 89#define DC_LOGGER_INIT(logger)
90
91struct _vcs_dpi_ip_params_st dcn2_0_ip = {
92 .odm_capable = 1,
93 .gpuvm_enable = 0,
94 .hostvm_enable = 0,
95 .gpuvm_max_page_table_levels = 4,
96 .hostvm_max_page_table_levels = 4,
97 .hostvm_cached_page_table_levels = 0,
98 .pte_group_size_bytes = 2048,
97bda032 99 .num_dsc = 6,
7ed4e635
HW		 100 .rob_buffer_size_kbytes = 168,
101 .det_buffer_size_kbytes = 164,
102 .dpte_buffer_size_in_pte_reqs_luma = 84,
103 .pde_proc_buffer_size_64k_reqs = 48,
104 .dpp_output_buffer_pixels = 2560,
105 .opp_output_buffer_lines = 1,
106 .pixel_chunk_size_kbytes = 8,
107 .pte_chunk_size_kbytes = 2,
108 .meta_chunk_size_kbytes = 2,
109 .writeback_chunk_size_kbytes = 2,
110 .line_buffer_size_bits = 789504,
111 .is_line_buffer_bpp_fixed = 0,
112 .line_buffer_fixed_bpp = 0,
113 .dcc_supported = true,
114 .max_line_buffer_lines = 12,
115 .writeback_luma_buffer_size_kbytes = 12,
116 .writeback_chroma_buffer_size_kbytes = 8,
117 .writeback_chroma_line_buffer_width_pixels = 4,
118 .writeback_max_hscl_ratio = 1,
119 .writeback_max_vscl_ratio = 1,
120 .writeback_min_hscl_ratio = 1,
121 .writeback_min_vscl_ratio = 1,
122 .writeback_max_hscl_taps = 12,
123 .writeback_max_vscl_taps = 12,
124 .writeback_line_buffer_luma_buffer_size = 0,
125 .writeback_line_buffer_chroma_buffer_size = 14643,
126 .cursor_buffer_size = 8,
127 .cursor_chunk_size = 2,
128 .max_num_otg = 6,
129 .max_num_dpp = 6,
130 .max_num_wb = 1,
131 .max_dchub_pscl_bw_pix_per_clk = 4,
132 .max_pscl_lb_bw_pix_per_clk = 2,
133 .max_lb_vscl_bw_pix_per_clk = 4,
134 .max_vscl_hscl_bw_pix_per_clk = 4,
135 .max_hscl_ratio = 8,
136 .max_vscl_ratio = 8,
137 .hscl_mults = 4,
138 .vscl_mults = 4,
139 .max_hscl_taps = 8,
140 .max_vscl_taps = 8,
141 .dispclk_ramp_margin_percent = 1,
142 .underscan_factor = 1.10,
143 .min_vblank_lines = 32, //
144 .dppclk_delay_subtotal = 77, //
145 .dppclk_delay_scl_lb_only = 16,
146 .dppclk_delay_scl = 50,
147 .dppclk_delay_cnvc_formatter = 8,
148 .dppclk_delay_cnvc_cursor = 6,
149 .dispclk_delay_subtotal = 87, //
150 .dcfclk_cstate_latency = 10, // SRExitTime
151 .max_inter_dcn_tile_repeaters = 8,
152
153 .xfc_supported = true,
154 .xfc_fill_bw_overhead_percent = 10.0,
155 .xfc_fill_constant_bytes = 0,
156};
157
a2c63407
Z		 158struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {
159 .odm_capable = 1,
160 .gpuvm_enable = 0,
161 .hostvm_enable = 0,
162 .gpuvm_max_page_table_levels = 4,
163 .hostvm_max_page_table_levels = 4,
164 .hostvm_cached_page_table_levels = 0,
165 .num_dsc = 5,
166 .rob_buffer_size_kbytes = 168,
167 .det_buffer_size_kbytes = 164,
168 .dpte_buffer_size_in_pte_reqs_luma = 84,
169 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
170 .dpp_output_buffer_pixels = 2560,
171 .opp_output_buffer_lines = 1,
172 .pixel_chunk_size_kbytes = 8,
173 .pte_enable = 1,
174 .max_page_table_levels = 4,
175 .pte_chunk_size_kbytes = 2,
176 .meta_chunk_size_kbytes = 2,
177 .writeback_chunk_size_kbytes = 2,
178 .line_buffer_size_bits = 789504,
179 .is_line_buffer_bpp_fixed = 0,
180 .line_buffer_fixed_bpp = 0,
181 .dcc_supported = true,
182 .max_line_buffer_lines = 12,
183 .writeback_luma_buffer_size_kbytes = 12,
184 .writeback_chroma_buffer_size_kbytes = 8,
185 .writeback_chroma_line_buffer_width_pixels = 4,
186 .writeback_max_hscl_ratio = 1,
187 .writeback_max_vscl_ratio = 1,
188 .writeback_min_hscl_ratio = 1,
189 .writeback_min_vscl_ratio = 1,
190 .writeback_max_hscl_taps = 12,
191 .writeback_max_vscl_taps = 12,
192 .writeback_line_buffer_luma_buffer_size = 0,
193 .writeback_line_buffer_chroma_buffer_size = 14643,
194 .cursor_buffer_size = 8,
195 .cursor_chunk_size = 2,
196 .max_num_otg = 5,
197 .max_num_dpp = 5,
198 .max_num_wb = 1,
199 .max_dchub_pscl_bw_pix_per_clk = 4,
200 .max_pscl_lb_bw_pix_per_clk = 2,
201 .max_lb_vscl_bw_pix_per_clk = 4,
202 .max_vscl_hscl_bw_pix_per_clk = 4,
203 .max_hscl_ratio = 8,
204 .max_vscl_ratio = 8,
205 .hscl_mults = 4,
206 .vscl_mults = 4,
207 .max_hscl_taps = 8,
208 .max_vscl_taps = 8,
209 .dispclk_ramp_margin_percent = 1,
210 .underscan_factor = 1.10,
211 .min_vblank_lines = 32, //
212 .dppclk_delay_subtotal = 77, //
213 .dppclk_delay_scl_lb_only = 16,
214 .dppclk_delay_scl = 50,
215 .dppclk_delay_cnvc_formatter = 8,
216 .dppclk_delay_cnvc_cursor = 6,
217 .dispclk_delay_subtotal = 87, //
218 .dcfclk_cstate_latency = 10, // SRExitTime
219 .max_inter_dcn_tile_repeaters = 8,
220 .xfc_supported = true,
221 .xfc_fill_bw_overhead_percent = 10.0,
222 .xfc_fill_constant_bytes = 0,
223 .ptoi_supported = 0
224};
225
fb6959ae
NK		 226struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
227 /* Defaults that get patched on driver load from firmware. */
228 .clock_limits = {
229 {
230 .state = 0,
231 .dcfclk_mhz = 560.0,
232 .fabricclk_mhz = 560.0,
233 .dispclk_mhz = 513.0,
234 .dppclk_mhz = 513.0,
235 .phyclk_mhz = 540.0,
236 .socclk_mhz = 560.0,
237 .dscclk_mhz = 171.0,
238 .dram_speed_mts = 8960.0,
239 },
240 {
241 .state = 1,
242 .dcfclk_mhz = 694.0,
243 .fabricclk_mhz = 694.0,
244 .dispclk_mhz = 642.0,
245 .dppclk_mhz = 642.0,
246 .phyclk_mhz = 600.0,
247 .socclk_mhz = 694.0,
248 .dscclk_mhz = 214.0,
249 .dram_speed_mts = 11104.0,
250 },
251 {
252 .state = 2,
253 .dcfclk_mhz = 875.0,
254 .fabricclk_mhz = 875.0,
255 .dispclk_mhz = 734.0,
256 .dppclk_mhz = 734.0,
257 .phyclk_mhz = 810.0,
258 .socclk_mhz = 875.0,
259 .dscclk_mhz = 245.0,
260 .dram_speed_mts = 14000.0,
261 },
262 {
263 .state = 3,
264 .dcfclk_mhz = 1000.0,
265 .fabricclk_mhz = 1000.0,
266 .dispclk_mhz = 1100.0,
267 .dppclk_mhz = 1100.0,
268 .phyclk_mhz = 810.0,
269 .socclk_mhz = 1000.0,
270 .dscclk_mhz = 367.0,
271 .dram_speed_mts = 16000.0,
272 },
273 {
274 .state = 4,
275 .dcfclk_mhz = 1200.0,
276 .fabricclk_mhz = 1200.0,
277 .dispclk_mhz = 1284.0,
278 .dppclk_mhz = 1284.0,
279 .phyclk_mhz = 810.0,
280 .socclk_mhz = 1200.0,
281 .dscclk_mhz = 428.0,
282 .dram_speed_mts = 16000.0,
283 },
284 /*Extra state, no dispclk ramping*/
285 {
286 .state = 5,
287 .dcfclk_mhz = 1200.0,
288 .fabricclk_mhz = 1200.0,
289 .dispclk_mhz = 1284.0,
290 .dppclk_mhz = 1284.0,
291 .phyclk_mhz = 810.0,
292 .socclk_mhz = 1200.0,
293 .dscclk_mhz = 428.0,
294 .dram_speed_mts = 16000.0,
295 },
296 },
297 .num_states = 5,
298 .sr_exit_time_us = 8.6,
299 .sr_enter_plus_exit_time_us = 10.9,
300 .urgent_latency_us = 4.0,
301 .urgent_latency_pixel_data_only_us = 4.0,
302 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
303 .urgent_latency_vm_data_only_us = 4.0,
304 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
305 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
306 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
307 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
308 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
309 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
310 .max_avg_sdp_bw_use_normal_percent = 40.0,
311 .max_avg_dram_bw_use_normal_percent = 40.0,
312 .writeback_latency_us = 12.0,
313 .ideal_dram_bw_after_urgent_percent = 40.0,
314 .max_request_size_bytes = 256,
315 .dram_channel_width_bytes = 2,
316 .fabric_datapath_to_dcn_data_return_bytes = 64,
317 .dcn_downspread_percent = 0.5,
318 .downspread_percent = 0.38,
319 .dram_page_open_time_ns = 50.0,
320 .dram_rw_turnaround_time_ns = 17.5,
321 .dram_return_buffer_per_channel_bytes = 8192,
322 .round_trip_ping_latency_dcfclk_cycles = 131,
323 .urgent_out_of_order_return_per_channel_bytes = 256,
324 .channel_interleave_bytes = 256,
325 .num_banks = 8,
326 .num_chans = 16,
327 .vmm_page_size_bytes = 4096,
328 .dram_clock_change_latency_us = 404.0,
329 .dummy_pstate_latency_us = 5.0,
330 .writeback_dram_clock_change_latency_us = 23.0,
331 .return_bus_width_bytes = 64,
332 .dispclk_dppclk_vco_speed_mhz = 3850,
333 .xfc_bus_transport_time_us = 20,
334 .xfc_xbuf_latency_tolerance_us = 4,
335 .use_urgent_burst_bw = 0
336};
7ed4e635 337
675a9e38 338struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
7ed4e635
HW		 339
340#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
341 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
342 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
343 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
344 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
345 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
346 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
347 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
348 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
349 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
350 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
351 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
352 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
353 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
354 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
355#endif
356
357
358enum dcn20_clk_src_array_id {
359 DCN20_CLK_SRC_PLL0,
360 DCN20_CLK_SRC_PLL1,
361 DCN20_CLK_SRC_PLL2,
362 DCN20_CLK_SRC_PLL3,
363 DCN20_CLK_SRC_PLL4,
364 DCN20_CLK_SRC_PLL5,
365 DCN20_CLK_SRC_TOTAL
366};
367
368/* begin *********************
369 * macros to expend register list macro defined in HW object header file */
370
371/* DCN */
372/* TODO awful hack. fixup dcn20_dwb.h */
373#undef BASE_INNER
374#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
375
376#define BASE(seg) BASE_INNER(seg)
377
378#define SR(reg_name)\
379 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
380 mm ## reg_name
381
382#define SRI(reg_name, block, id)\
383 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
384 mm ## block ## id ## _ ## reg_name
385
386#define SRIR(var_name, reg_name, block, id)\
387 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
388 mm ## block ## id ## _ ## reg_name
389
390#define SRII(reg_name, block, id)\
391 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
392 mm ## block ## id ## _ ## reg_name
393
394#define DCCG_SRII(reg_name, block, id)\
395 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
396 mm ## block ## id ## _ ## reg_name
397
398/* NBIO */
399#define NBIO_BASE_INNER(seg) \
400 NBIO_BASE__INST0_SEG ## seg
401
402#define NBIO_BASE(seg) \
403 NBIO_BASE_INNER(seg)
404
405#define NBIO_SR(reg_name)\
406 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
407 mm ## reg_name
408
409/* MMHUB */
410#define MMHUB_BASE_INNER(seg) \
411 MMHUB_BASE__INST0_SEG ## seg
412
413#define MMHUB_BASE(seg) \
414 MMHUB_BASE_INNER(seg)
415
416#define MMHUB_SR(reg_name)\
417 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
418 mmMM ## reg_name
419
420static const struct bios_registers bios_regs = {
421 NBIO_SR(BIOS_SCRATCH_3),
422 NBIO_SR(BIOS_SCRATCH_6)
423};
424
425#define clk_src_regs(index, pllid)\
426[index] = {\
427 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
428}
429
430static const struct dce110_clk_src_regs clk_src_regs[] = {
431 clk_src_regs(0, A),
432 clk_src_regs(1, B),
433 clk_src_regs(2, C),
434 clk_src_regs(3, D),
435 clk_src_regs(4, E),
436 clk_src_regs(5, F)
437};
438
439static const struct dce110_clk_src_shift cs_shift = {
440 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
441};
442
443static const struct dce110_clk_src_mask cs_mask = {
444 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
445};
446
447static const struct dce_dmcu_registers dmcu_regs = {
448 DMCU_DCN10_REG_LIST()
449};
450
451static const struct dce_dmcu_shift dmcu_shift = {
452 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
453};
454
455static const struct dce_dmcu_mask dmcu_mask = {
456 DMCU_MASK_SH_LIST_DCN10(_MASK)
457};
d7c29549 458
7ed4e635 459static const struct dce_abm_registers abm_regs = {
d7c29549 460 ABM_DCN20_REG_LIST()
7ed4e635
HW		 461};
462
463static const struct dce_abm_shift abm_shift = {
d7c29549 464 ABM_MASK_SH_LIST_DCN20(__SHIFT)
7ed4e635
HW		 465};
466
467static const struct dce_abm_mask abm_mask = {
d7c29549 468 ABM_MASK_SH_LIST_DCN20(_MASK)
7ed4e635 469};
d7c29549 470
7ed4e635
HW		 471#define audio_regs(id)\
472[id] = {\
473 AUD_COMMON_REG_LIST(id)\
474}
475
476static const struct dce_audio_registers audio_regs[] = {
477 audio_regs(0),
478 audio_regs(1),
479 audio_regs(2),
480 audio_regs(3),
481 audio_regs(4),
482 audio_regs(5),
483 audio_regs(6),
484};
485
486#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
487 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
488 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
489 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
490
491static const struct dce_audio_shift audio_shift = {
492 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
493};
494
54a9bcb0 495static const struct dce_audio_mask audio_mask = {
7ed4e635
HW		 496 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
497};
498
499#define stream_enc_regs(id)\
500[id] = {\
501 SE_DCN2_REG_LIST(id)\
502}
503
504static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
505 stream_enc_regs(0),
506 stream_enc_regs(1),
507 stream_enc_regs(2),
508 stream_enc_regs(3),
509 stream_enc_regs(4),
510 stream_enc_regs(5),
511};
512
513static const struct dcn10_stream_encoder_shift se_shift = {
514 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
515};
516
517static const struct dcn10_stream_encoder_mask se_mask = {
518 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
519};
520
521
522#define aux_regs(id)\
523[id] = {\
524 DCN2_AUX_REG_LIST(id)\
525}
526
527static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
528 aux_regs(0),
529 aux_regs(1),
530 aux_regs(2),
531 aux_regs(3),
532 aux_regs(4),
533 aux_regs(5)
534};
535
536#define hpd_regs(id)\
537[id] = {\
538 HPD_REG_LIST(id)\
539}
540
541static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
542 hpd_regs(0),
543 hpd_regs(1),
544 hpd_regs(2),
545 hpd_regs(3),
546 hpd_regs(4),
547 hpd_regs(5)
548};
549
550#define link_regs(id, phyid)\
551[id] = {\
552 LE_DCN10_REG_LIST(id), \
553 UNIPHY_DCN2_REG_LIST(phyid), \
a771ded8 554 DPCS_DCN2_REG_LIST(id), \
7ed4e635
HW		 555 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
556}
557
558static const struct dcn10_link_enc_registers link_enc_regs[] = {
559 link_regs(0, A),
560 link_regs(1, B),
561 link_regs(2, C),
562 link_regs(3, D),
563 link_regs(4, E),
564 link_regs(5, F)
565};
566
567static const struct dcn10_link_enc_shift le_shift = {
a771ded8
RL		 568 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
569 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
7ed4e635
HW		 570};
571
572static const struct dcn10_link_enc_mask le_mask = {
a771ded8
RL		 573 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
574 DPCS_DCN2_MASK_SH_LIST(_MASK)
7ed4e635
HW		 575};
576
577#define ipp_regs(id)\
578[id] = {\
579 IPP_REG_LIST_DCN20(id),\
580}
581
582static const struct dcn10_ipp_registers ipp_regs[] = {
583 ipp_regs(0),
584 ipp_regs(1),
585 ipp_regs(2),
586 ipp_regs(3),
587 ipp_regs(4),
588 ipp_regs(5),
589};
590
591static const struct dcn10_ipp_shift ipp_shift = {
592 IPP_MASK_SH_LIST_DCN20(__SHIFT)
593};
594
595static const struct dcn10_ipp_mask ipp_mask = {
596 IPP_MASK_SH_LIST_DCN20(_MASK),
597};
598
599#define opp_regs(id)\
600[id] = {\
601 OPP_REG_LIST_DCN20(id),\
602}
603
604static const struct dcn20_opp_registers opp_regs[] = {
605 opp_regs(0),
606 opp_regs(1),
607 opp_regs(2),
608 opp_regs(3),
609 opp_regs(4),
610 opp_regs(5),
611};
612
613static const struct dcn20_opp_shift opp_shift = {
614 OPP_MASK_SH_LIST_DCN20(__SHIFT)
615};
616
617static const struct dcn20_opp_mask opp_mask = {
618 OPP_MASK_SH_LIST_DCN20(_MASK)
619};
620
621#define aux_engine_regs(id)\
622[id] = {\
623 AUX_COMMON_REG_LIST0(id), \
624 .AUXN_IMPCAL = 0, \
625 .AUXP_IMPCAL = 0, \
626 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
627}
628
629static const struct dce110_aux_registers aux_engine_regs[] = {
630 aux_engine_regs(0),
631 aux_engine_regs(1),
632 aux_engine_regs(2),
633 aux_engine_regs(3),
634 aux_engine_regs(4),
635 aux_engine_regs(5)
636};
637
638#define tf_regs(id)\
639[id] = {\
640 TF_REG_LIST_DCN20(id),\
641}
642
643static const struct dcn2_dpp_registers tf_regs[] = {
644 tf_regs(0),
645 tf_regs(1),
646 tf_regs(2),
647 tf_regs(3),
648 tf_regs(4),
649 tf_regs(5),
650};
651
652static const struct dcn2_dpp_shift tf_shift = {
d56eaa7c
JA		 653 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
654 TF_DEBUG_REG_LIST_SH_DCN10
7ed4e635
HW		 655};
656
657static const struct dcn2_dpp_mask tf_mask = {
d56eaa7c
JA		 658 TF_REG_LIST_SH_MASK_DCN20(_MASK),
659 TF_DEBUG_REG_LIST_MASK_DCN10
7ed4e635
HW		 660};
661
bb21290f
CL		 662#define dwbc_regs_dcn2(id)\
663[id] = {\
664 DWBC_COMMON_REG_LIST_DCN2_0(id),\
665 }
666
667static const struct dcn20_dwbc_registers dwbc20_regs[] = {
668 dwbc_regs_dcn2(0),
669};
670
671static const struct dcn20_dwbc_shift dwbc20_shift = {
672 DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
673};
674
675static const struct dcn20_dwbc_mask dwbc20_mask = {
676 DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
677};
678
679#define mcif_wb_regs_dcn2(id)\
680[id] = {\
681 MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\
682 }
683
684static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {
685 mcif_wb_regs_dcn2(0),
686};
687
688static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {
689 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
690};
691
692static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {
693 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
694};
695
7ed4e635
HW		 696static const struct dcn20_mpc_registers mpc_regs = {
697 MPC_REG_LIST_DCN2_0(0),
698 MPC_REG_LIST_DCN2_0(1),
699 MPC_REG_LIST_DCN2_0(2),
700 MPC_REG_LIST_DCN2_0(3),
701 MPC_REG_LIST_DCN2_0(4),
702 MPC_REG_LIST_DCN2_0(5),
703 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
704 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
705 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
706 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
707 MPC_OUT_MUX_REG_LIST_DCN2_0(4),
708 MPC_OUT_MUX_REG_LIST_DCN2_0(5),
709};
710
711static const struct dcn20_mpc_shift mpc_shift = {
712 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
713};
714
715static const struct dcn20_mpc_mask mpc_mask = {
716 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
717};
718
719#define tg_regs(id)\
720[id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
721
722
723static const struct dcn_optc_registers tg_regs[] = {
724 tg_regs(0),
725 tg_regs(1),
726 tg_regs(2),
727 tg_regs(3),
728 tg_regs(4),
729 tg_regs(5)
730};
731
732static const struct dcn_optc_shift tg_shift = {
733 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
734};
735
736static const struct dcn_optc_mask tg_mask = {
737 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
738};
739
740#define hubp_regs(id)\
741[id] = {\
742 HUBP_REG_LIST_DCN20(id)\
743}
744
745static const struct dcn_hubp2_registers hubp_regs[] = {
746 hubp_regs(0),
747 hubp_regs(1),
748 hubp_regs(2),
749 hubp_regs(3),
750 hubp_regs(4),
751 hubp_regs(5)
752};
753
754static const struct dcn_hubp2_shift hubp_shift = {
755 HUBP_MASK_SH_LIST_DCN20(__SHIFT)
756};
757
758static const struct dcn_hubp2_mask hubp_mask = {
759 HUBP_MASK_SH_LIST_DCN20(_MASK)
760};
761
762static const struct dcn_hubbub_registers hubbub_reg = {
763 HUBBUB_REG_LIST_DCN20(0)
764};
765
766static const struct dcn_hubbub_shift hubbub_shift = {
767 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT)
768};
769
770static const struct dcn_hubbub_mask hubbub_mask = {
771 HUBBUB_MASK_SH_LIST_DCN20(_MASK)
772};
773
774#define vmid_regs(id)\
775[id] = {\
776 DCN20_VMID_REG_LIST(id)\
777}
778
779static const struct dcn_vmid_registers vmid_regs[] = {
780 vmid_regs(0),
781 vmid_regs(1),
782 vmid_regs(2),
783 vmid_regs(3),
784 vmid_regs(4),
785 vmid_regs(5),
786 vmid_regs(6),
787 vmid_regs(7),
788 vmid_regs(8),
789 vmid_regs(9),
790 vmid_regs(10),
791 vmid_regs(11),
792 vmid_regs(12),
793 vmid_regs(13),
794 vmid_regs(14),
795 vmid_regs(15)
796};
797
798static const struct dcn20_vmid_shift vmid_shifts = {
799 DCN20_VMID_MASK_SH_LIST(__SHIFT)
800};
801
802static const struct dcn20_vmid_mask vmid_masks = {
803 DCN20_VMID_MASK_SH_LIST(_MASK)
804};
805
8276dd87 806static const struct dce110_aux_registers_shift aux_shift = {
807 DCN_AUX_MASK_SH_LIST(__SHIFT)
808};
809
810static const struct dce110_aux_registers_mask aux_mask = {
811 DCN_AUX_MASK_SH_LIST(_MASK)
812};
813
bf7f5ac3
YMM		 814static int map_transmitter_id_to_phy_instance(
815 enum transmitter transmitter)
816{
817 switch (transmitter) {
818 case TRANSMITTER_UNIPHY_A:
819 return 0;
820 break;
821 case TRANSMITTER_UNIPHY_B:
822 return 1;
823 break;
824 case TRANSMITTER_UNIPHY_C:
825 return 2;
826 break;
827 case TRANSMITTER_UNIPHY_D:
828 return 3;
829 break;
830 case TRANSMITTER_UNIPHY_E:
831 return 4;
832 break;
833 case TRANSMITTER_UNIPHY_F:
834 return 5;
835 break;
836 default:
837 ASSERT(0);
838 return 0;
839 }
840}
8276dd87 841
97bda032
HW		 842#define dsc_regsDCN20(id)\
843[id] = {\
844 DSC_REG_LIST_DCN20(id)\
845}
846
847static const struct dcn20_dsc_registers dsc_regs[] = {
848 dsc_regsDCN20(0),
849 dsc_regsDCN20(1),
850 dsc_regsDCN20(2),
851 dsc_regsDCN20(3),
852 dsc_regsDCN20(4),
853 dsc_regsDCN20(5)
854};
855
856static const struct dcn20_dsc_shift dsc_shift = {
857 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
858};
859
860static const struct dcn20_dsc_mask dsc_mask = {
861 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
862};
7ed4e635
HW		 863
864static const struct dccg_registers dccg_regs = {
865 DCCG_REG_LIST_DCN2()
866};
867
868static const struct dccg_shift dccg_shift = {
869 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
870};
871
872static const struct dccg_mask dccg_mask = {
873 DCCG_MASK_SH_LIST_DCN2(_MASK)
874};
875
876static const struct resource_caps res_cap_nv10 = {
877 .num_timing_generator = 6,
878 .num_opp = 6,
879 .num_video_plane = 6,
880 .num_audio = 7,
881 .num_stream_encoder = 6,
882 .num_pll = 6,
9cbee6ef 883 .num_dwb = 1,
7ed4e635
HW		 884 .num_ddc = 6,
885 .num_vmid = 16,
97bda032 886 .num_dsc = 6,
7ed4e635
HW		 887};
888
889static const struct dc_plane_cap plane_cap = {
890 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
891 .blends_with_above = true,
892 .blends_with_below = true,
7ed4e635 893 .per_pixel_alpha = true,
5b1b2f20
AD		 894
895 .pixel_format_support = {
896 .argb8888 = true,
897 .nv12 = true,
898 .fp16 = true
899 },
900
901 .max_upscale_factor = {
902 .argb8888 = 16000,
903 .nv12 = 16000,
904 .fp16 = 1
905 },
906
907 .max_downscale_factor = {
908 .argb8888 = 250,
909 .nv12 = 250,
910 .fp16 = 1
911 }
7ed4e635 912};
2ebe1773
BL		 913static const struct resource_caps res_cap_nv14 = {
914 .num_timing_generator = 5,
915 .num_opp = 5,
916 .num_video_plane = 5,
917 .num_audio = 6,
918 .num_stream_encoder = 5,
919 .num_pll = 5,
80df905d 920 .num_dwb = 1,
2ebe1773 921 .num_ddc = 5,
6bb27085
ZL		 922 .num_vmid = 16,
923 .num_dsc = 5,
2ebe1773 924};
7ed4e635
HW		 925
926static const struct dc_debug_options debug_defaults_drv = {
927 .disable_dmcu = true,
928 .force_abm_enable = false,
929 .timing_trace = false,
930 .clock_trace = true,
931 .disable_pplib_clock_request = true,
932 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
4d25a0d5 933 .force_single_disp_pipe_split = false,
7ed4e635
HW		 934 .disable_dcc = DCC_ENABLE,
935 .vsr_support = true,
936 .performance_trace = false,
937 .max_downscale_src_width = 5120,/*upto 5K*/
938 .disable_pplib_wm_range = false,
939 .scl_reset_length10 = true,
9e14d4f1 940 .sanity_checks = false,
7ed4e635 941 .disable_tri_buf = true,
1a7d296d 942 .underflow_assert_delay_us = 0xFFFFFFFF,
7ed4e635
HW		 943};
944
945static const struct dc_debug_options debug_defaults_diags = {
946 .disable_dmcu = true,
947 .force_abm_enable = false,
948 .timing_trace = true,
949 .clock_trace = true,
950 .disable_dpp_power_gate = true,
951 .disable_hubp_power_gate = true,
952 .disable_clock_gate = true,
953 .disable_pplib_clock_request = true,
954 .disable_pplib_wm_range = true,
955 .disable_stutter = true,
956 .scl_reset_length10 = true,
1a7d296d 957 .underflow_assert_delay_us = 0xFFFFFFFF,
7ed4e635
HW		 958};
959
960void dcn20_dpp_destroy(struct dpp **dpp)
961{
962 kfree(TO_DCN20_DPP(*dpp));
963 *dpp = NULL;
964}
965
966struct dpp *dcn20_dpp_create(
967 struct dc_context *ctx,
968 uint32_t inst)
969{
970 struct dcn20_dpp *dpp =
971 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
972
973 if (!dpp)
974 return NULL;
975
976 if (dpp2_construct(dpp, ctx, inst,
977 &tf_regs[inst], &tf_shift, &tf_mask))
978 return &dpp->base;
979
980 BREAK_TO_DEBUGGER();
981 kfree(dpp);
982 return NULL;
983}
984
985struct input_pixel_processor *dcn20_ipp_create(
986 struct dc_context *ctx, uint32_t inst)
987{
988 struct dcn10_ipp *ipp =
989 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
990
991 if (!ipp) {
992 BREAK_TO_DEBUGGER();
993 return NULL;
994 }
995
996 dcn20_ipp_construct(ipp, ctx, inst,
997 &ipp_regs[inst], &ipp_shift, &ipp_mask);
998 return &ipp->base;
999}
1000
1001
1002struct output_pixel_processor *dcn20_opp_create(
1003 struct dc_context *ctx, uint32_t inst)
1004{
1005 struct dcn20_opp *opp =
1006 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1007
1008 if (!opp) {
1009 BREAK_TO_DEBUGGER();
1010 return NULL;
1011 }
1012
1013 dcn20_opp_construct(opp, ctx, inst,
1014 &opp_regs[inst], &opp_shift, &opp_mask);
1015 return &opp->base;
1016}
1017
1018struct dce_aux *dcn20_aux_engine_create(
1019 struct dc_context *ctx,
1020 uint32_t inst)
1021{
1022 struct aux_engine_dce110 *aux_engine =
1023 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
1024
1025 if (!aux_engine)
1026 return NULL;
1027
1028 dce110_aux_engine_construct(aux_engine, ctx, inst,
1029 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
8276dd87 1030 &aux_engine_regs[inst],
1031 &aux_mask,
f6040a43 1032 &aux_shift,
1033 ctx->dc->caps.extended_aux_timeout_support);
7ed4e635
HW		 1034
1035 return &aux_engine->base;
1036}
1037#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
1038
1039static const struct dce_i2c_registers i2c_hw_regs[] = {
1040 i2c_inst_regs(1),
1041 i2c_inst_regs(2),
1042 i2c_inst_regs(3),
1043 i2c_inst_regs(4),
1044 i2c_inst_regs(5),
1045 i2c_inst_regs(6),
1046};
1047
1048static const struct dce_i2c_shift i2c_shifts = {
1049 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
1050};
1051
1052static const struct dce_i2c_mask i2c_masks = {
1053 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
1054};
1055
1056struct dce_i2c_hw *dcn20_i2c_hw_create(
1057 struct dc_context *ctx,
1058 uint32_t inst)
1059{
1060 struct dce_i2c_hw *dce_i2c_hw =
1061 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1062
1063 if (!dce_i2c_hw)
1064 return NULL;
1065
1066 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1067 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1068
1069 return dce_i2c_hw;
1070}
1071struct mpc *dcn20_mpc_create(struct dc_context *ctx)
1072{
1073 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1074 GFP_KERNEL);
1075
1076 if (!mpc20)
1077 return NULL;
1078
1079 dcn20_mpc_construct(mpc20, ctx,
1080 &mpc_regs,
1081 &mpc_shift,
1082 &mpc_mask,
1083 6);
1084
1085 return &mpc20->base;
1086}
1087
1088struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)
1089{
1090 int i;
1091 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1092 GFP_KERNEL);
1093
1094 if (!hubbub)
1095 return NULL;
1096
1097 hubbub2_construct(hubbub, ctx,
1098 &hubbub_reg,
1099 &hubbub_shift,
1100 &hubbub_mask);
1101
1102 for (i = 0; i < res_cap_nv10.num_vmid; i++) {
1103 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1104
1105 vmid->ctx = ctx;
1106
1107 vmid->regs = &vmid_regs[i];
1108 vmid->shifts = &vmid_shifts;
1109 vmid->masks = &vmid_masks;
1110 }
1111
1112 return &hubbub->base;
1113}
1114
1115struct timing_generator *dcn20_timing_generator_create(
1116 struct dc_context *ctx,
1117 uint32_t instance)
1118{
1119 struct optc *tgn10 =
1120 kzalloc(sizeof(struct optc), GFP_KERNEL);
1121
1122 if (!tgn10)
1123 return NULL;
1124
1125 tgn10->base.inst = instance;
1126 tgn10->base.ctx = ctx;
1127
1128 tgn10->tg_regs = &tg_regs[instance];
1129 tgn10->tg_shift = &tg_shift;
1130 tgn10->tg_mask = &tg_mask;
1131
1132 dcn20_timing_generator_init(tgn10);
1133
1134 return &tgn10->base;
1135}
1136
1137static const struct encoder_feature_support link_enc_feature = {
1138 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1139 .max_hdmi_pixel_clock = 600000,
1140 .hdmi_ycbcr420_supported = true,
1141 .dp_ycbcr420_supported = true,
1142 .flags.bits.IS_HBR2_CAPABLE = true,
1143 .flags.bits.IS_HBR3_CAPABLE = true,
1144 .flags.bits.IS_TPS3_CAPABLE = true,
1145 .flags.bits.IS_TPS4_CAPABLE = true
1146};
1147
1148struct link_encoder *dcn20_link_encoder_create(
1149 const struct encoder_init_data *enc_init_data)
1150{
1151 struct dcn20_link_encoder *enc20 =
1152 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
bf7f5ac3 1153 int link_regs_id;
7ed4e635
HW		 1154
1155 if (!enc20)
1156 return NULL;
1157
bf7f5ac3
YMM		 1158 link_regs_id =
1159 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1160
7ed4e635
HW		 1161 dcn20_link_encoder_construct(enc20,
1162 enc_init_data,
1163 &link_enc_feature,
bf7f5ac3 1164 &link_enc_regs[link_regs_id],
7ed4e635
HW		 1165 &link_enc_aux_regs[enc_init_data->channel - 1],
1166 &link_enc_hpd_regs[enc_init_data->hpd_source],
1167 &le_shift,
1168 &le_mask);
1169
1170 return &enc20->enc10.base;
1171}
1172
1173struct clock_source *dcn20_clock_source_create(
1174 struct dc_context *ctx,
1175 struct dc_bios *bios,
1176 enum clock_source_id id,
1177 const struct dce110_clk_src_regs *regs,
1178 bool dp_clk_src)
1179{
1180 struct dce110_clk_src *clk_src =
1181 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1182
1183 if (!clk_src)
1184 return NULL;
1185
1186 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1187 regs, &cs_shift, &cs_mask)) {
1188 clk_src->base.dp_clk_src = dp_clk_src;
1189 return &clk_src->base;
1190 }
1191
cabe144b 1192 kfree(clk_src);
7ed4e635
HW		 1193 BREAK_TO_DEBUGGER();
1194 return NULL;
1195}
1196
1197static void read_dce_straps(
1198 struct dc_context *ctx,
1199 struct resource_straps *straps)
1200{
1201 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1202 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1203}
1204
1205static struct audio *dcn20_create_audio(
1206 struct dc_context *ctx, unsigned int inst)
1207{
1208 return dce_audio_create(ctx, inst,
1209 &audio_regs[inst], &audio_shift, &audio_mask);
1210}
1211
1212struct stream_encoder *dcn20_stream_encoder_create(
1213 enum engine_id eng_id,
1214 struct dc_context *ctx)
1215{
1216 struct dcn10_stream_encoder *enc1 =
1217 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1218
1219 if (!enc1)
1220 return NULL;
1221
9fd4c2d7
ZL		 1222 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
1223 if (eng_id >= ENGINE_ID_DIGD)
1224 eng_id++;
1225 }
1226
7ed4e635
HW		 1227 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1228 &stream_enc_regs[eng_id],
1229 &se_shift, &se_mask);
1230
1231 return &enc1->base;
1232}
1233
1234static const struct dce_hwseq_registers hwseq_reg = {
1235 HWSEQ_DCN2_REG_LIST()
1236};
1237
1238static const struct dce_hwseq_shift hwseq_shift = {
1239 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT)
1240};
1241
1242static const struct dce_hwseq_mask hwseq_mask = {
1243 HWSEQ_DCN2_MASK_SH_LIST(_MASK)
1244};
1245
1246struct dce_hwseq *dcn20_hwseq_create(
1247 struct dc_context *ctx)
1248{
1249 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1250
1251 if (hws) {
1252 hws->ctx = ctx;
1253 hws->regs = &hwseq_reg;
1254 hws->shifts = &hwseq_shift;
1255 hws->masks = &hwseq_mask;
1256 }
1257 return hws;
1258}
1259
1260static const struct resource_create_funcs res_create_funcs = {
1261 .read_dce_straps = read_dce_straps,
1262 .create_audio = dcn20_create_audio,
1263 .create_stream_encoder = dcn20_stream_encoder_create,
1264 .create_hwseq = dcn20_hwseq_create,
1265};
1266
1267static const struct resource_create_funcs res_create_maximus_funcs = {
1268 .read_dce_straps = NULL,
1269 .create_audio = NULL,
1270 .create_stream_encoder = NULL,
1271 .create_hwseq = dcn20_hwseq_create,
1272};
1273
44e149bb
AD		 1274static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
1275
7ed4e635
HW		 1276void dcn20_clock_source_destroy(struct clock_source **clk_src)
1277{
1278 kfree(TO_DCE110_CLK_SRC(*clk_src));
1279 *clk_src = NULL;
1280}
1281
97bda032
HW		 1282
1283struct display_stream_compressor *dcn20_dsc_create(
1284 struct dc_context *ctx, uint32_t inst)
1285{
1286 struct dcn20_dsc *dsc =
1287 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1288
1289 if (!dsc) {
1290 BREAK_TO_DEBUGGER();
1291 return NULL;
1292 }
1293
1294 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1295 return &dsc->base;
1296}
1297
1298void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
1299{
1300 kfree(container_of(*dsc, struct dcn20_dsc, base));
1301 *dsc = NULL;
1302}
1303
7ed4e635 1304
d9e32672 1305static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)
7ed4e635
HW		 1306{
1307 unsigned int i;
1308
1309 for (i = 0; i < pool->base.stream_enc_count; i++) {
1310 if (pool->base.stream_enc[i] != NULL) {
1311 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1312 pool->base.stream_enc[i] = NULL;
1313 }
1314 }
1315
97bda032
HW		 1316 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1317 if (pool->base.dscs[i] != NULL)
1318 dcn20_dsc_destroy(&pool->base.dscs[i]);
1319 }
7ed4e635
HW		 1320
1321 if (pool->base.mpc != NULL) {
1322 kfree(TO_DCN20_MPC(pool->base.mpc));
1323 pool->base.mpc = NULL;
1324 }
1325 if (pool->base.hubbub != NULL) {
1326 kfree(pool->base.hubbub);
1327 pool->base.hubbub = NULL;
1328 }
1329 for (i = 0; i < pool->base.pipe_count; i++) {
1330 if (pool->base.dpps[i] != NULL)
1331 dcn20_dpp_destroy(&pool->base.dpps[i]);
1332
1333 if (pool->base.ipps[i] != NULL)
1334 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1335
1336 if (pool->base.hubps[i] != NULL) {
1337 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1338 pool->base.hubps[i] = NULL;
1339 }
1340
1341 if (pool->base.irqs != NULL) {
1342 dal_irq_service_destroy(&pool->base.irqs);
1343 }
1344 }
1345
1346 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1347 if (pool->base.engines[i] != NULL)
1348 dce110_engine_destroy(&pool->base.engines[i]);
1349 if (pool->base.hw_i2cs[i] != NULL) {
1350 kfree(pool->base.hw_i2cs[i]);
1351 pool->base.hw_i2cs[i] = NULL;
1352 }
1353 if (pool->base.sw_i2cs[i] != NULL) {
1354 kfree(pool->base.sw_i2cs[i]);
1355 pool->base.sw_i2cs[i] = NULL;
1356 }
1357 }
1358
1359 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1360 if (pool->base.opps[i] != NULL)
1361 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1362 }
1363
1364 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1365 if (pool->base.timing_generators[i] != NULL) {
1366 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1367 pool->base.timing_generators[i] = NULL;
1368 }
1369 }
1370
bb21290f
CL		 1371 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1372 if (pool->base.dwbc[i] != NULL) {
1373 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
1374 pool->base.dwbc[i] = NULL;
1375 }
1376 if (pool->base.mcif_wb[i] != NULL) {
1377 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
1378 pool->base.mcif_wb[i] = NULL;
1379 }
1380 }
1381
7ed4e635
HW		 1382 for (i = 0; i < pool->base.audio_count; i++) {
1383 if (pool->base.audios[i])
1384 dce_aud_destroy(&pool->base.audios[i]);
1385 }
1386
1387 for (i = 0; i < pool->base.clk_src_count; i++) {
1388 if (pool->base.clock_sources[i] != NULL) {
1389 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1390 pool->base.clock_sources[i] = NULL;
1391 }
1392 }
1393
1394 if (pool->base.dp_clock_source != NULL) {
1395 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1396 pool->base.dp_clock_source = NULL;
1397 }
1398
1399
1400 if (pool->base.abm != NULL)
1401 dce_abm_destroy(&pool->base.abm);
1402
1403 if (pool->base.dmcu != NULL)
1404 dce_dmcu_destroy(&pool->base.dmcu);
1405
1406 if (pool->base.dccg != NULL)
1407 dcn_dccg_destroy(&pool->base.dccg);
1408
1409 if (pool->base.pp_smu != NULL)
1410 dcn20_pp_smu_destroy(&pool->base.pp_smu);
1411
d9a07577
JL		 1412 if (pool->base.oem_device != NULL)
1413 dal_ddc_service_destroy(&pool->base.oem_device);
7ed4e635
HW		 1414}
1415
1416struct hubp *dcn20_hubp_create(
1417 struct dc_context *ctx,
1418 uint32_t inst)
1419{
1420 struct dcn20_hubp *hubp2 =
1421 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1422
1423 if (!hubp2)
1424 return NULL;
1425
1426 if (hubp2_construct(hubp2, ctx, inst,
1427 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1428 return &hubp2->base;
1429
1430 BREAK_TO_DEBUGGER();
1431 kfree(hubp2);
1432 return NULL;
1433}
1434
1435static void get_pixel_clock_parameters(
1436 struct pipe_ctx *pipe_ctx,
1437 struct pixel_clk_params *pixel_clk_params)
1438{
1439 const struct dc_stream_state *stream = pipe_ctx->stream;
b1f6d01c
DL		 1440 struct pipe_ctx *odm_pipe;
1441 int opp_cnt = 1;
1442
1443 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1444 opp_cnt++;
7ed4e635
HW		 1445
1446 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1447 pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1448 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1449 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1450 /* TODO: un-hardcode*/
1451 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1452 LINK_RATE_REF_FREQ_IN_KHZ;
1453 pixel_clk_params->flags.ENABLE_SS = 0;
1454 pixel_clk_params->color_depth =
1455 stream->timing.display_color_depth;
1456 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1457 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1458
1459 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1460 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1461
b1f6d01c
DL		 1462 if (opp_cnt == 4)
1463 pixel_clk_params->requested_pix_clk_100hz /= 4;
78c77382 1464 else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2)
7ed4e635
HW		 1465 pixel_clk_params->requested_pix_clk_100hz /= 2;
1466
1467 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1468 pixel_clk_params->requested_pix_clk_100hz *= 2;
1469
1470}
1471
1472static void build_clamping_params(struct dc_stream_state *stream)
1473{
1474 stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1475 stream->clamping.c_depth = stream->timing.display_color_depth;
1476 stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1477}
1478
1479static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1480{
1481
1482 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1483
1484 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1485 pipe_ctx->clock_source,
1486 &pipe_ctx->stream_res.pix_clk_params,
1487 &pipe_ctx->pll_settings);
1488
1489 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1490
1491 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1492 &pipe_ctx->stream->bit_depth_params);
1493 build_clamping_params(pipe_ctx->stream);
1494
1495 return DC_OK;
1496}
1497
1498enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
1499{
1500 enum dc_status status = DC_OK;
1501 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1502
1503 /*TODO Seems unneeded anymore */
1504 /* if (old_context && resource_is_stream_unchanged(old_context, stream)) {
1505 if (stream != NULL && old_context->streams[i] != NULL) {
1506 todo: shouldn't have to copy missing parameter here
1507 resource_build_bit_depth_reduction_params(stream,
1508 &stream->bit_depth_params);
1509 stream->clamping.pixel_encoding =
1510 stream->timing.pixel_encoding;
1511
1512 resource_build_bit_depth_reduction_params(stream,
1513 &stream->bit_depth_params);
1514 build_clamping_params(stream);
1515
1516 continue;
1517 }
1518 }
1519 */
1520
1521 if (!pipe_ctx)
1522 return DC_ERROR_UNEXPECTED;
1523
1524
1525 status = build_pipe_hw_param(pipe_ctx);
1526
1527 return status;
1528}
1529
97bda032 1530
c9ae6e16
NC		 1531static void acquire_dsc(struct resource_context *res_ctx,
1532 const struct resource_pool *pool,
eab4bb97
NC		 1533 struct display_stream_compressor **dsc,
1534 int pipe_idx)
97bda032
HW		 1535{
1536 int i;
c9ae6e16
NC		 1537
1538 ASSERT(*dsc == NULL);
1539 *dsc = NULL;
97bda032 1540
eab4bb97
NC		 1541 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) {
1542 *dsc = pool->dscs[pipe_idx];
1543 res_ctx->is_dsc_acquired[pipe_idx] = true;
1544 return;
1545 }
1546
97bda032
HW		 1547 /* Find first free DSC */
1548 for (i = 0; i < pool->res_cap->num_dsc; i++)
1549 if (!res_ctx->is_dsc_acquired[i]) {
c9ae6e16 1550 *dsc = pool->dscs[i];
97bda032
HW		 1551 res_ctx->is_dsc_acquired[i] = true;
1552 break;
1553 }
97bda032
HW		 1554}
1555
1556static void release_dsc(struct resource_context *res_ctx,
1557 const struct resource_pool *pool,
c9ae6e16 1558 struct display_stream_compressor **dsc)
97bda032
HW		 1559{
1560 int i;
1561
1562 for (i = 0; i < pool->res_cap->num_dsc; i++)
c9ae6e16 1563 if (pool->dscs[i] == *dsc) {
97bda032 1564 res_ctx->is_dsc_acquired[i] = false;
c9ae6e16 1565 *dsc = NULL;
97bda032
HW		 1566 break;
1567 }
1568}
1569
7ed4e635 1570
7ed4e635 1571
8c20a1ed 1572enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc,
c9ae6e16
NC		 1573 struct dc_state *dc_ctx,
1574 struct dc_stream_state *dc_stream)
1575{
1576 enum dc_status result = DC_OK;
1577 int i;
1578 const struct resource_pool *pool = dc->res_pool;
97bda032 1579
c9ae6e16
NC		 1580 /* Get a DSC if required and available */
1581 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1582 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];
97bda032 1583
c9ae6e16
NC		 1584 if (pipe_ctx->stream != dc_stream)
1585 continue;
97bda032 1586
8c20a1ed
DF		 1587 if (pipe_ctx->stream_res.dsc)
1588 continue;
1589
eab4bb97 1590 acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc, i);
97bda032 1591
c9ae6e16
NC		 1592 /* The number of DSCs can be less than the number of pipes */
1593 if (!pipe_ctx->stream_res.dsc) {
c9ae6e16 1594 result = DC_NO_DSC_RESOURCE;
97bda032 1595 }
7ed4e635 1596
c9ae6e16
NC		 1597 break;
1598 }
7ed4e635
HW		 1599
1600 return result;
1601}
1602
1603
ba32c50f 1604static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
c9ae6e16
NC		 1605 struct dc_state *new_ctx,
1606 struct dc_stream_state *dc_stream)
7ed4e635
HW		 1607{
1608 struct pipe_ctx *pipe_ctx = NULL;
1609 int i;
1610
7ed4e635
HW		 1611 for (i = 0; i < MAX_PIPES; i++) {
1612 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1613 pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
b1f6d01c
DL		 1614
1615 if (pipe_ctx->stream_res.dsc)
1616 release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
7ed4e635
HW		 1617 }
1618 }
1619
1620 if (!pipe_ctx)
1621 return DC_ERROR_UNEXPECTED;
b1f6d01c
DL		 1622 else
1623 return DC_OK;
7ed4e635 1624}
c9ae6e16
NC		 1625
1626
1627enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1628{
1629 enum dc_status result = DC_ERROR_UNEXPECTED;
1630
1631 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1632
1633 if (result == DC_OK)
1634 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1635
c9ae6e16
NC		 1636 /* Get a DSC if required and available */
1637 if (result == DC_OK && dc_stream->timing.flags.DSC)
8c20a1ed 1638 result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
c9ae6e16
NC		 1639
1640 if (result == DC_OK)
1641 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
1642
1643 return result;
1644}
1645
1646
1647enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1648{
1649 enum dc_status result = DC_OK;
1650
ba32c50f 1651 result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
c9ae6e16
NC		 1652
1653 return result;
1654}
7ed4e635
HW		 1655
1656
1657static void swizzle_to_dml_params(
1658 enum swizzle_mode_values swizzle,
1659 unsigned int *sw_mode)
1660{
1661 switch (swizzle) {
1662 case DC_SW_LINEAR:
1663 *sw_mode = dm_sw_linear;
1664 break;
1665 case DC_SW_4KB_S:
1666 *sw_mode = dm_sw_4kb_s;
1667 break;
1668 case DC_SW_4KB_S_X:
1669 *sw_mode = dm_sw_4kb_s_x;
1670 break;
1671 case DC_SW_4KB_D:
1672 *sw_mode = dm_sw_4kb_d;
1673 break;
1674 case DC_SW_4KB_D_X:
1675 *sw_mode = dm_sw_4kb_d_x;
1676 break;
1677 case DC_SW_64KB_S:
1678 *sw_mode = dm_sw_64kb_s;
1679 break;
1680 case DC_SW_64KB_S_X:
1681 *sw_mode = dm_sw_64kb_s_x;
1682 break;
1683 case DC_SW_64KB_S_T:
1684 *sw_mode = dm_sw_64kb_s_t;
1685 break;
1686 case DC_SW_64KB_D:
1687 *sw_mode = dm_sw_64kb_d;
1688 break;
1689 case DC_SW_64KB_D_X:
1690 *sw_mode = dm_sw_64kb_d_x;
1691 break;
1692 case DC_SW_64KB_D_T:
1693 *sw_mode = dm_sw_64kb_d_t;
1694 break;
1695 case DC_SW_64KB_R_X:
1696 *sw_mode = dm_sw_64kb_r_x;
1697 break;
1698 case DC_SW_VAR_S:
1699 *sw_mode = dm_sw_var_s;
1700 break;
1701 case DC_SW_VAR_S_X:
1702 *sw_mode = dm_sw_var_s_x;
1703 break;
1704 case DC_SW_VAR_D:
1705 *sw_mode = dm_sw_var_d;
1706 break;
1707 case DC_SW_VAR_D_X:
1708 *sw_mode = dm_sw_var_d_x;
1709 break;
1710
1711 default:
1712 ASSERT(0); /* Not supported */
1713 break;
1714 }
1715}
1716
b6bfba6c 1717bool dcn20_split_stream_for_odm(
b1f6d01c
DL		 1718 struct resource_context *res_ctx,
1719 const struct resource_pool *pool,
1720 struct pipe_ctx *prev_odm_pipe,
1721 struct pipe_ctx *next_odm_pipe)
1722{
1723 int pipe_idx = next_odm_pipe->pipe_idx;
b1f6d01c
DL		 1724
1725 *next_odm_pipe = *prev_odm_pipe;
b1f6d01c
DL		 1726
1727 next_odm_pipe->pipe_idx = pipe_idx;
1728 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
1729 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
1730 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
1731 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
1732 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
1733 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
b1f6d01c 1734 next_odm_pipe->stream_res.dsc = NULL;
b1f6d01c 1735 if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
b1f6d01c
DL		 1736 next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
1737 next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
1738 }
1739 prev_odm_pipe->next_odm_pipe = next_odm_pipe;
1740 next_odm_pipe->prev_odm_pipe = prev_odm_pipe;
1741 ASSERT(next_odm_pipe->top_pipe == NULL);
1742
1743 if (prev_odm_pipe->plane_state) {
c0358809
DL		 1744 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
1745 int new_width;
1746
b1f6d01c
DL		 1747 /* HACTIVE halved for odm combine */
1748 sd->h_active /= 2;
b1f6d01c
DL		 1749 /* Calculate new vp and recout for left pipe */
1750 /* Need at least 16 pixels width per side */
1751 if (sd->recout.x + 16 >= sd->h_active)
1752 return false;
1753 new_width = sd->h_active - sd->recout.x;
1754 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1755 sd->ratios.horz, sd->recout.width - new_width));
1756 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1757 sd->ratios.horz_c, sd->recout.width - new_width));
1758 sd->recout.width = new_width;
1759
1760 /* Calculate new vp and recout for right pipe */
1761 sd = &next_odm_pipe->plane_res.scl_data;
c0358809
DL		 1762 /* HACTIVE halved for odm combine */
1763 sd->h_active /= 2;
b1f6d01c
DL		 1764 /* Need at least 16 pixels width per side */
1765 if (new_width <= 16)
1766 return false;
c0358809 1767 new_width = sd->recout.width + sd->recout.x - sd->h_active;
b1f6d01c
DL		 1768 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1769 sd->ratios.horz, sd->recout.width - new_width));
1770 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1771 sd->ratios.horz_c, sd->recout.width - new_width));
1772 sd->recout.width = new_width;
1773 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
1774 sd->ratios.horz, sd->h_active - sd->recout.x));
1775 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
1776 sd->ratios.horz_c, sd->h_active - sd->recout.x));
1777 sd->recout.x = 0;
1778 }
1779 next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
b1f6d01c 1780 if (next_odm_pipe->stream->timing.flags.DSC == 1) {
eab4bb97 1781 acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);
b1f6d01c
DL		 1782 ASSERT(next_odm_pipe->stream_res.dsc);
1783 if (next_odm_pipe->stream_res.dsc == NULL)
1784 return false;
1785 }
b1f6d01c
DL		 1786
1787 return true;
1788}
1789
b6bfba6c 1790void dcn20_split_stream_for_mpc(
7ed4e635
HW		 1791 struct resource_context *res_ctx,
1792 const struct resource_pool *pool,
1793 struct pipe_ctx *primary_pipe,
b1f6d01c 1794 struct pipe_ctx *secondary_pipe)
7ed4e635
HW		 1795{
1796 int pipe_idx = secondary_pipe->pipe_idx;
7ed4e635 1797 struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
7ed4e635
HW		 1798
1799 *secondary_pipe = *primary_pipe;
1800 secondary_pipe->bottom_pipe = sec_bot_pipe;
1801
1802 secondary_pipe->pipe_idx = pipe_idx;
1803 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
1804 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
1805 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
1806 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
1807 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
1808 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
c92b4c46 1809 secondary_pipe->stream_res.dsc = NULL;
7ed4e635
HW		 1810 if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
1811 ASSERT(!secondary_pipe->bottom_pipe);
1812 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
1813 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
1814 }
1815 primary_pipe->bottom_pipe = secondary_pipe;
1816 secondary_pipe->top_pipe = primary_pipe;
1817
b1f6d01c
DL		 1818 ASSERT(primary_pipe->plane_state);
1819 resource_build_scaling_params(primary_pipe);
1820 resource_build_scaling_params(secondary_pipe);
7ed4e635
HW		 1821}
1822
1823void dcn20_populate_dml_writeback_from_context(
1824 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1825{
1826 int pipe_cnt, i;
1827
1828 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1829 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];
1830
1831 if (!res_ctx->pipe_ctx[i].stream)
1832 continue;
1833
1834 /* Set writeback information */
1835 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
1836 pipes[pipe_cnt].dout.num_active_wb++;
1837 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
1838 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
1839 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
1840 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
1841 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
1842 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1;
1843 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
1844 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
1845 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0;
1846 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0;
1847 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
1848 if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
1849 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
1850 else
1851 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
1852 } else
1853 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
1854
1855 pipe_cnt++;
1856 }
1857
1858}
1859
1860int dcn20_populate_dml_pipes_from_context(
2f488884 1861 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)
7ed4e635
HW		 1862{
1863 int pipe_cnt, i;
1864 bool synchronized_vblank = true;
2f488884 1865 struct resource_context *res_ctx = &context->res_ctx;
7ed4e635
HW		 1866
1867 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
1868 if (!res_ctx->pipe_ctx[i].stream)
1869 continue;
1870
1871 if (pipe_cnt < 0) {
1872 pipe_cnt = i;
1873 continue;
1874 }
785908cf 1875 if (dc->debug.disable_timing_sync || !resource_are_streams_timing_synchronizable(
7ed4e635
HW		 1876 res_ctx->pipe_ctx[pipe_cnt].stream,
1877 res_ctx->pipe_ctx[i].stream)) {
1878 synchronized_vblank = false;
1879 break;
1880 }
1881 }
1882
1883 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1884 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
2f488884 1885 unsigned int v_total;
1075735e 1886 unsigned int front_porch;
03fd87db 1887 int output_bpc;
7ed4e635
HW		 1888
1889 if (!res_ctx->pipe_ctx[i].stream)
1890 continue;
2f488884
AL		 1891
1892 v_total = timing->v_total;
1075735e 1893 front_porch = timing->v_front_porch;
7ed4e635
HW		 1894 /* todo:
1895 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
1896 pipes[pipe_cnt].pipe.src.dcc = 0;
1897 pipes[pipe_cnt].pipe.src.vm = 0;*/
1898
97bda032
HW		 1899 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
1900 /* todo: rotation?*/
1901 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
7ed4e635
HW		 1902 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
1903 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
1904 /* 1/2 vblank */
1905 pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
2f488884 1906 (v_total - timing->v_addressable
7ed4e635
HW		 1907 - timing->v_border_top - timing->v_border_bottom) / 2;
1908 /* 36 bytes dp, 32 hdmi */
1909 pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
1910 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
1911 }
1912 pipes[pipe_cnt].pipe.src.dcc = false;
1913 pipes[pipe_cnt].pipe.src.dcc_rate = 1;
1914 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
1915 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
1916 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
1917 - timing->h_addressable
1918 - timing->h_border_left
1919 - timing->h_border_right;
1075735e 1920 pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch;
7ed4e635
HW		 1921 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
1922 - timing->v_addressable
1923 - timing->v_border_top
1924 - timing->v_border_bottom;
1925 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
2f488884 1926 pipes[pipe_cnt].pipe.dest.vtotal = v_total;
7ed4e635
HW		 1927 pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable;
1928 pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable;
1929 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
1930 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
1931 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1932 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
1933 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
1621f4c4 1934 pipes[pipe_cnt].dout.dp_lanes = 4;
8bb3d7e7
CL		 1935 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
1936 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
c0358809
DL		 1937 pipes[pipe_cnt].pipe.dest.odm_combine = res_ctx->pipe_ctx[i].prev_odm_pipe
1938 || res_ctx->pipe_ctx[i].next_odm_pipe;
1939 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1940 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
1941 == res_ctx->pipe_ctx[i].plane_state)
1942 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
1943 else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
1944 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
1945
1946 while (first_pipe->prev_odm_pipe)
1947 first_pipe = first_pipe->prev_odm_pipe;
1948 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
1949 }
7ed4e635 1950
7ed4e635
HW		 1951 switch (res_ctx->pipe_ctx[i].stream->signal) {
1952 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1953 case SIGNAL_TYPE_DISPLAY_PORT:
1954 pipes[pipe_cnt].dout.output_type = dm_dp;
1955 break;
1956 case SIGNAL_TYPE_EDP:
1957 pipes[pipe_cnt].dout.output_type = dm_edp;
1958 break;
1959 case SIGNAL_TYPE_HDMI_TYPE_A:
1960 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1961 case SIGNAL_TYPE_DVI_DUAL_LINK:
1962 pipes[pipe_cnt].dout.output_type = dm_hdmi;
1963 break;
1964 default:
1965 /* In case there is no signal, set dp with 4 lanes to allow max config */
1966 pipes[pipe_cnt].dout.output_type = dm_dp;
1967 pipes[pipe_cnt].dout.dp_lanes = 4;
1968 }
03fd87db
IB		 1969
1970 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
1971 case COLOR_DEPTH_666:
1972 output_bpc = 6;
1973 break;
1974 case COLOR_DEPTH_888:
1975 output_bpc = 8;
1976 break;
1977 case COLOR_DEPTH_101010:
1978 output_bpc = 10;
1979 break;
1980 case COLOR_DEPTH_121212:
1981 output_bpc = 12;
1982 break;
1983 case COLOR_DEPTH_141414:
1984 output_bpc = 14;
1985 break;
1986 case COLOR_DEPTH_161616:
1987 output_bpc = 16;
1988 break;
03fd87db
IB		 1989 case COLOR_DEPTH_999:
1990 output_bpc = 9;
1991 break;
1992 case COLOR_DEPTH_111111:
1993 output_bpc = 11;
1994 break;
03fd87db
IB		 1995 default:
1996 output_bpc = 8;
1997 break;
1998 }
1999
7ed4e635
HW		 2000 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
2001 case PIXEL_ENCODING_RGB:
2002 case PIXEL_ENCODING_YCBCR444:
2003 pipes[pipe_cnt].dout.output_format = dm_444;
03fd87db 2004 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
7ed4e635
HW		 2005 break;
2006 case PIXEL_ENCODING_YCBCR420:
2007 pipes[pipe_cnt].dout.output_format = dm_420;
486cc0ee 2008 pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2;
7ed4e635
HW		 2009 break;
2010 case PIXEL_ENCODING_YCBCR422:
2011 if (true) /* todo */
2012 pipes[pipe_cnt].dout.output_format = dm_s422;
2013 else
2014 pipes[pipe_cnt].dout.output_format = dm_n422;
03fd87db 2015 pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
7ed4e635
HW		 2016 break;
2017 default:
2018 pipes[pipe_cnt].dout.output_format = dm_444;
03fd87db 2019 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
7ed4e635 2020 }
7ed4e635 2021
486cc0ee
NC		 2022 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)
2023 pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
2024
7ed4e635
HW		 2025 /* todo: default max for now, until there is logic reflecting this in dc*/
2026 pipes[pipe_cnt].dout.output_bpc = 12;
2027 /*
2028 * Use max cursor settings for calculations to minimize
2029 * bw calculations due to cursor on/off
2030 */
2031 pipes[pipe_cnt].pipe.src.num_cursors = 2;
ed07237c
IB		 2032 pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
2033 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
2034 pipes[pipe_cnt].pipe.src.cur1_src_width = 256;
2035 pipes[pipe_cnt].pipe.src.cur1_bpp = dm_cur_32bit;
7ed4e635
HW		 2036
2037 if (!res_ctx->pipe_ctx[i].plane_state) {
2038 pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
2039 pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear;
2040 pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
2041 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
2042 if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
2043 pipes[pipe_cnt].pipe.src.viewport_width = 1920;
2044 pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
2045 if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
2046 pipes[pipe_cnt].pipe.src.viewport_height = 1080;
71e6bd2a 2047 pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height;
7ed4e635
HW		 2048 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */
2049 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2050 pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
2051 pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/
2052 pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_hsplit != 1*/
2053 pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/
2054 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
2055 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
2056 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
2057 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
2058 pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
2059 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
2060 pipes[pipe_cnt].pipe.src.is_hsplit = 0;
2061 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2f488884
AL		 2062 pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;
2063 pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;
7ed4e635
HW		 2064 } else {
2065 struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
2066 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
2067
7ed4e635
HW		 2068 pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
2069 pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe
2070 && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
2071 || (res_ctx->pipe_ctx[i].top_pipe
2072 && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln);
7ed4e635
HW		 2073 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
2074 || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
2075 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
2076 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
2077 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
2078 pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
2079 pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
2080 pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
71e6bd2a 2081 pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;
7ed4e635 2082 if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
12e2b2d4
DL		 2083 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2084 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
2085 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
2086 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
7ed4e635 2087 } else {
12e2b2d4
DL		 2088 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2089 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
7ed4e635
HW		 2090 }
2091 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
2092 pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
2093 pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
2094 pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
2095 pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
2096 if (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) {
2097 pipes[pipe_cnt].pipe.dest.full_recout_width +=
2098 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.width;
2099 pipes[pipe_cnt].pipe.dest.full_recout_height +=
2100 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.height;
2101 } else if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) {
2102 pipes[pipe_cnt].pipe.dest.full_recout_width +=
2103 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.width;
2104 pipes[pipe_cnt].pipe.dest.full_recout_height +=
2105 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.height;
2106 }
2107
ed07237c 2108 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
7ed4e635
HW		 2109 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
2110 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
2111 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
2112 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
2113 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
2114 scl->ratios.vert.value != dc_fixpt_one.value
2115 || scl->ratios.horz.value != dc_fixpt_one.value
2116 || scl->ratios.vert_c.value != dc_fixpt_one.value
2117 || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/
2118 || dc->debug.always_scale; /*support always scale*/
2119 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
2120 pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
2121 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
2122 pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
2123
b964e790
DL		 2124 pipes[pipe_cnt].pipe.src.macro_tile_size =
2125 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
7ed4e635
HW		 2126 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
2127 &pipes[pipe_cnt].pipe.src.sw_mode);
2128
2129 switch (pln->format) {
2130 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2131 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2132 pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
2133 break;
2134 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2135 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2136 pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
2137 break;
2138 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2139 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2140 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2141 pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
2142 break;
2143 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2144 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2145 pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
2146 break;
2147 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2148 pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
2149 break;
2150 default:
2151 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2152 break;
2153 }
2154 }
2155
2156 pipe_cnt++;
2157 }
2158
2159 /* populate writeback information */
2160 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
2161
2162 return pipe_cnt;
2163}
2164
2165unsigned int dcn20_calc_max_scaled_time(
2166 unsigned int time_per_pixel,
2167 enum mmhubbub_wbif_mode mode,
2168 unsigned int urgent_watermark)
2169{
2170 unsigned int time_per_byte = 0;
2171 unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */
2172 unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */
2173 unsigned int small_free_entry, max_free_entry;
2174 unsigned int buf_lh_capability;
2175 unsigned int max_scaled_time;
2176
2177 if (mode == PACKED_444) /* packed mode */
2178 time_per_byte = time_per_pixel/4;
2179 else if (mode == PLANAR_420_8BPC)
2180 time_per_byte = time_per_pixel;
2181 else if (mode == PLANAR_420_10BPC) /* p010 */
2182 time_per_byte = time_per_pixel * 819/1024;
2183
2184 if (time_per_byte == 0)
2185 time_per_byte = 1;
2186
2187 small_free_entry = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry;
2188 max_free_entry = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;
2189 buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */
2190 max_scaled_time = buf_lh_capability - urgent_watermark;
2191 return max_scaled_time;
2192}
2193
2194void dcn20_set_mcif_arb_params(
2195 struct dc *dc,
2196 struct dc_state *context,
2197 display_e2e_pipe_params_st *pipes,
2198 int pipe_cnt)
2199{
2200 enum mmhubbub_wbif_mode wbif_mode;
2201 struct mcif_arb_params *wb_arb_params;
2202 int i, j, k, dwb_pipe;
2203
2204 /* Writeback MCIF_WB arbitration parameters */
2205 dwb_pipe = 0;
2206 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2207
2208 if (!context->res_ctx.pipe_ctx[i].stream)
2209 continue;
2210
2211 for (j = 0; j < MAX_DWB_PIPES; j++) {
2212 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)
2213 continue;
2214
2215 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
2216 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
2217
2218 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {
2219 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
2220 wbif_mode = PLANAR_420_8BPC;
2221 else
2222 wbif_mode = PLANAR_420_10BPC;
2223 } else
2224 wbif_mode = PACKED_444;
2225
2226 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
2227 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2228 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2229 }
2230 wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* 4 bit fraction, ms */
2231 wb_arb_params->slice_lines = 32;
2232 wb_arb_params->arbitration_slice = 2;
2233 wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
2234 wbif_mode,
2235 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
2236
2237 dwb_pipe++;
2238
2239 if (dwb_pipe >= MAX_DWB_PIPES)
2240 return;
2241 }
2242 if (dwb_pipe >= MAX_DWB_PIPES)
2243 return;
2244 }
2245}
2246
b6bfba6c 2247bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
0ba37b20
DL		 2248{
2249 int i;
2250
2251 /* Validate DSC config, dsc count validation is already done */
2252 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2253 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
2254 struct dc_stream_state *stream = pipe_ctx->stream;
2255 struct dsc_config dsc_cfg;
b1f6d01c
DL		 2256 struct pipe_ctx *odm_pipe;
2257 int opp_cnt = 1;
2258
2259 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
2260 opp_cnt++;
0ba37b20
DL		 2261
2262 /* Only need to validate top pipe */
b1f6d01c 2263 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
0ba37b20
DL		 2264 continue;
2265
b1f6d01c
DL		 2266 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
2267 + stream->timing.h_border_right) / opp_cnt;
0ba37b20
DL		 2268 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
2269 + stream->timing.v_border_bottom;
0ba37b20
DL		 2270 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
2271 dsc_cfg.color_depth = stream->timing.display_color_depth;
2272 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
b1f6d01c 2273 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
0ba37b20
DL		 2274
2275 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
2276 return false;
2277 }
2278 return true;
2279}
0ba37b20 2280
b6bfba6c 2281struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
c681491a
JL		 2282 struct resource_context *res_ctx,
2283 const struct resource_pool *pool,
2284 const struct pipe_ctx *primary_pipe)
2285{
2286 struct pipe_ctx *secondary_pipe = NULL;
2287
2288 if (dc && primary_pipe) {
2289 int j;
2290 int preferred_pipe_idx = 0;
2291
2292 /* first check the prev dc state:
2293 * if this primary pipe has a bottom pipe in prev. state
2294 * and if the bottom pipe is still available (which it should be),
2295 * pick that pipe as secondary
b1f6d01c
DL		 2296 * Same logic applies for ODM pipes. Since mpo is not allowed with odm
2297 * check in else case.
c681491a
JL		 2298 */
2299 if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {
2300 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
2301 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2302 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2303 secondary_pipe->pipe_idx = preferred_pipe_idx;
2304 }
b1f6d01c
DL		 2305 } else if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {
2306 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;
2307 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2308 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2309 secondary_pipe->pipe_idx = preferred_pipe_idx;
2310 }
c681491a
JL		 2311 }
2312
2313 /*
2314 * if this primary pipe does not have a bottom pipe in prev. state
2315 * start backward and find a pipe that did not used to be a bottom pipe in
2316 * prev. dc state. This way we make sure we keep the same assignment as
2317 * last state and will not have to reprogram every pipe
2318 */
2319 if (secondary_pipe == NULL) {
2320 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
8b8eda01
DL		 2321 if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL
2322 && dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) {
c681491a
JL		 2323 preferred_pipe_idx = j;
2324
2325 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2326 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2327 secondary_pipe->pipe_idx = preferred_pipe_idx;
2328 break;
2329 }
2330 }
2331 }
2332 }
2333 /*
2334 * We should never hit this assert unless assignments are shuffled around
2335 * if this happens we will prob. hit a vsync tdr
2336 */
2337 ASSERT(secondary_pipe);
2338 /*
2339 * search backwards for the second pipe to keep pipe
2340 * assignment more consistent
2341 */
2342 if (secondary_pipe == NULL) {
2343 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2344 preferred_pipe_idx = j;
2345
2346 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2347 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2348 secondary_pipe->pipe_idx = preferred_pipe_idx;
2349 break;
2350 }
2351 }
2352 }
2353 }
2354
2355 return secondary_pipe;
2356}
2357
b6bfba6c 2358void dcn20_merge_pipes_for_validate(
6de20237 2359 struct dc *dc,
b6bfba6c 2360 struct dc_state *context)
7ed4e635 2361{
b6bfba6c 2362 int i;
7ed4e635 2363
b1f6d01c
DL		 2364 /* merge previously split odm pipes since mode support needs to make the decision */
2365 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2366 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2367 struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;
2368
2369 if (pipe->prev_odm_pipe)
2370 continue;
2371
2372 pipe->next_odm_pipe = NULL;
2373 while (odm_pipe) {
2374 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
2375
2376 odm_pipe->plane_state = NULL;
2377 odm_pipe->stream = NULL;
2378 odm_pipe->top_pipe = NULL;
2379 odm_pipe->bottom_pipe = NULL;
2380 odm_pipe->prev_odm_pipe = NULL;
2381 odm_pipe->next_odm_pipe = NULL;
b1f6d01c
DL		 2382 if (odm_pipe->stream_res.dsc)
2383 release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
b1f6d01c
DL		 2384 /* Clear plane_res and stream_res */
2385 memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));
2386 memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));
2387 odm_pipe = next_odm_pipe;
2388 }
2389 if (pipe->plane_state)
2390 resource_build_scaling_params(pipe);
2391 }
2392
2393 /* merge previously mpc split pipes since mode support needs to make the decision */
7ed4e635
HW		 2394 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2395 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2396 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2397
2398 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
2399 continue;
2400
7ed4e635
HW		 2401 pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
2402 if (hsplit_pipe->bottom_pipe)
2403 hsplit_pipe->bottom_pipe->top_pipe = pipe;
2404 hsplit_pipe->plane_state = NULL;
2405 hsplit_pipe->stream = NULL;
2406 hsplit_pipe->top_pipe = NULL;
2407 hsplit_pipe->bottom_pipe = NULL;
b1f6d01c 2408
7ed4e635
HW		 2409 /* Clear plane_res and stream_res */
2410 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
2411 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
2412 if (pipe->plane_state)
2413 resource_build_scaling_params(pipe);
2414 }
b6bfba6c 2415}
7ed4e635 2416
b6bfba6c
DL		 2417int dcn20_validate_apply_pipe_split_flags(
2418 struct dc *dc,
2419 struct dc_state *context,
2420 int vlevel,
2421 bool *split)
2422{
b745ecdb 2423 int i, pipe_idx, vlevel_split;
b6bfba6c
DL		 2424 bool force_split = false;
2425 bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
7ed4e635 2426
b745ecdb 2427 /* Single display loop, exits if there is more than one display */
7ed4e635
HW		 2428 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2429 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2430 bool exit_loop = false;
2431
2432 if (!pipe->stream || pipe->top_pipe)
2433 continue;
2434
2435 if (dc->debug.force_single_disp_pipe_split) {
2436 if (!force_split)
2437 force_split = true;
2438 else {
2439 force_split = false;
2440 exit_loop = true;
2441 }
2442 }
2443 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP) {
2444 if (avoid_split)
2445 avoid_split = false;
2446 else {
2447 avoid_split = true;
2448 exit_loop = true;
2449 }
2450 }
2451 if (exit_loop)
2452 break;
2453 }
b6bfba6c
DL		 2454 /* TODO: fix dc bugs and remove this split threshold thing */
2455 if (context->stream_count > dc->res_pool->pipe_count / 2)
7ed4e635
HW		 2456 avoid_split = true;
2457
b745ecdb 2458 /* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */
b6bfba6c
DL		 2459 if (avoid_split) {
2460 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2461 if (!context->res_ctx.pipe_ctx[i].stream)
2462 continue;
2463
b745ecdb 2464 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
b6bfba6c
DL		 2465 if (context->bw_ctx.dml.vba.NoOfDPP[vlevel][0][pipe_idx] == 1)
2466 break;
2467 /* Impossible to not split this pipe */
b745ecdb
DL		 2468 if (vlevel > context->bw_ctx.dml.soc.num_states)
2469 vlevel = vlevel_split;
b6bfba6c
DL		 2470 pipe_idx++;
2471 }
2472 context->bw_ctx.dml.vba.maxMpcComb = 0;
2473 }
2474
b745ecdb 2475 /* Split loop sets which pipe should be split based on dml outputs and dc flags */
7ed4e635 2476 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
b6bfba6c
DL		 2477 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2478
7ed4e635
HW		 2479 if (!context->res_ctx.pipe_ctx[i].stream)
2480 continue;
b6bfba6c
DL		 2481
2482 if (force_split || context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] > 1)
2483 split[i] = true;
2484 if ((pipe->stream->view_format ==
2485 VIEW_3D_FORMAT_SIDE_BY_SIDE ||
2486 pipe->stream->view_format ==
2487 VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
2488 (pipe->stream->timing.timing_3d_format ==
2489 TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
2490 pipe->stream->timing.timing_3d_format ==
2491 TIMING_3D_FORMAT_SIDE_BY_SIDE))
2492 split[i] = true;
2493 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
2494 split[i] = true;
2495 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = true;
2496 }
78ea008b
DL		 2497 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx] =
2498 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
b6bfba6c
DL		 2499 /* Adjust dppclk when split is forced, do not bother with dispclk */
2500 if (split[i] && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)
2501 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
7ed4e635
HW		 2502 pipe_idx++;
2503 }
2504
b6bfba6c
DL		 2505 return vlevel;
2506}
2507
2508bool dcn20_fast_validate_bw(
2509 struct dc *dc,
2510 struct dc_state *context,
2511 display_e2e_pipe_params_st *pipes,
2512 int *pipe_cnt_out,
2513 int *pipe_split_from,
2514 int *vlevel_out)
2515{
2516 bool out = false;
2517 bool split[MAX_PIPES] = { false };
2518 int pipe_cnt, i, pipe_idx, vlevel;
2519
2520 ASSERT(pipes);
2521 if (!pipes)
2522 return false;
2523
2524 dcn20_merge_pipes_for_validate(dc, context);
2525
2f488884 2526 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes);
b6bfba6c
DL		 2527
2528 *pipe_cnt_out = pipe_cnt;
2529
2530 if (!pipe_cnt) {
2531 out = true;
2532 goto validate_out;
2533 }
2534
2535 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2536
2537 if (vlevel > context->bw_ctx.dml.soc.num_states)
2538 goto validate_fail;
2539
2540 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split);
2541
2542 /*initialize pipe_just_split_from to invalid idx*/
2543 for (i = 0; i < MAX_PIPES; i++)
2544 pipe_split_from[i] = -1;
2545
7ed4e635
HW		 2546 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2547 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2548 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
7ed4e635
HW		 2549
2550 if (!pipe->stream || pipe_split_from[i] >= 0)
2551 continue;
2552
2553 pipe_idx++;
2554
7ed4e635 2555 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
c681491a 2556 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
7ed4e635 2557 ASSERT(hsplit_pipe);
b1f6d01c 2558 if (!dcn20_split_stream_for_odm(
7ed4e635 2559 &context->res_ctx, dc->res_pool,
b1f6d01c 2560 pipe, hsplit_pipe))
7ed4e635
HW		 2561 goto validate_fail;
2562 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2563 dcn20_build_mapped_resource(dc, context, pipe->stream);
2564 }
2565
2566 if (!pipe->plane_state)
2567 continue;
2568 /* Skip 2nd half of already split pipe */
2569 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
2570 continue;
2571
02ce5a79
DL		 2572 /* We do not support mpo + odm at the moment */
2573 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
2574 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
2575 goto validate_fail;
2576
b6bfba6c 2577 if (split[i]) {
7ed4e635
HW		 2578 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
2579 /* pipe not split previously needs split */
c681491a 2580 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
b6bfba6c 2581 ASSERT(hsplit_pipe);
ff86391e
MS		 2582 if (!hsplit_pipe) {
2583 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2;
7ed4e635 2584 continue;
ff86391e 2585 }
b1f6d01c
DL		 2586 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2587 if (!dcn20_split_stream_for_odm(
2588 &context->res_ctx, dc->res_pool,
2589 pipe, hsplit_pipe))
2590 goto validate_fail;
387596ef 2591 dcn20_build_mapped_resource(dc, context, pipe->stream);
b1f6d01c
DL		 2592 } else
2593 dcn20_split_stream_for_mpc(
7ed4e635 2594 &context->res_ctx, dc->res_pool,
b1f6d01c 2595 pipe, hsplit_pipe);
7ed4e635
HW		 2596 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2597 }
02ce5a79 2598 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
7ed4e635
HW		 2599 /* merge should already have been done */
2600 ASSERT(0);
2601 }
2602 }
0ba37b20 2603 /* Actual dsc count per stream dsc validation*/
c84ad0d6 2604 if (!dcn20_validate_dsc(dc, context)) {
0ba37b20
DL		 2605 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2606 DML_FAIL_DSC_VALIDATION_FAILURE;
2607 goto validate_fail;
2608 }
7ed4e635 2609
6de20237 2610 *vlevel_out = vlevel;
42351c66 2611
6de20237
EY		 2612 out = true;
2613 goto validate_out;
2614
2615validate_fail:
2616 out = false;
2617
2618validate_out:
2619 return out;
2620}
2621
e2e316d5 2622static void dcn20_calculate_wm(
6de20237
EY		 2623 struct dc *dc, struct dc_state *context,
2624 display_e2e_pipe_params_st *pipes,
2625 int *out_pipe_cnt,
2626 int *pipe_split_from,
2627 int vlevel)
2628{
2629 int pipe_cnt, i, pipe_idx;
254eb07c 2630
7ed4e635 2631 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
41f03a6d
DL		 2632 if (!context->res_ctx.pipe_ctx[i].stream)
2633 continue;
7ed4e635 2634
41f03a6d
DL		 2635 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2636 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
7ed4e635 2637
41f03a6d
DL		 2638 if (pipe_split_from[i] < 0) {
2639 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2640 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
2641 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
2642 pipes[pipe_cnt].pipe.dest.odm_combine =
b6bfba6c 2643 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx];
41f03a6d
DL		 2644 else
2645 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2646 pipe_idx++;
2647 } else {
2648 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2649 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
2650 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
2651 pipes[pipe_cnt].pipe.dest.odm_combine =
b6bfba6c 2652 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]];
41f03a6d
DL		 2653 else
2654 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
7ed4e635 2655 }
6de20237 2656
41f03a6d
DL		 2657 if (dc->config.forced_clocks) {
2658 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2659 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
a6465d1f 2660 }
41f03a6d
DL		 2661 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
2662 pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2663 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
2664 pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2665
2666 pipe_cnt++;
2667 }
7ed4e635 2668
41f03a6d
DL		 2669 if (pipe_cnt != pipe_idx) {
2670 if (dc->res_pool->funcs->populate_dml_pipes)
2671 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2f488884 2672 context, pipes);
41f03a6d
DL		 2673 else
2674 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
2f488884 2675 context, pipes);
41f03a6d 2676 }
7ed4e635 2677
41f03a6d 2678 *out_pipe_cnt = pipe_cnt;
6de20237 2679
41f03a6d
DL		 2680 pipes[0].clks_cfg.voltage = vlevel;
2681 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2682 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2683
2684 /* only pipe 0 is read for voltage and dcf/soc clocks */
2685 if (vlevel < 1) {
2686 pipes[0].clks_cfg.voltage = 1;
2687 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
2688 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
2689 }
2690 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2691 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2692 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2693 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2694 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
4de094ee
BL		 2695 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2696 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
b617b265 2697 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
41f03a6d
DL		 2698
2699 if (vlevel < 2) {
2700 pipes[0].clks_cfg.voltage = 2;
2701 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2702 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2703 }
2704 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2705 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2706 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2707 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2708 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
4de094ee
BL		 2709 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2710 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
41f03a6d
DL		 2711
2712 if (vlevel < 3) {
2713 pipes[0].clks_cfg.voltage = 3;
2714 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2715 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2716 }
2717 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2718 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2719 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2720 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2721 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
4de094ee
BL		 2722 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2723 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
41f03a6d
DL		 2724
2725 pipes[0].clks_cfg.voltage = vlevel;
2726 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2727 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2728 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2729 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2730 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2731 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2732 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
4de094ee
BL		 2733 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2734 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
6de20237
EY		 2735}
2736
2737void dcn20_calculate_dlg_params(
2738 struct dc *dc, struct dc_state *context,
2739 display_e2e_pipe_params_st *pipes,
2740 int pipe_cnt,
2741 int vlevel)
2742{
41f03a6d
DL		 2743 int i, j, pipe_idx, pipe_idx_unsplit;
2744 bool visited[MAX_PIPES] = { 0 };
8e27a2d4 2745
7ed4e635
HW		 2746 /* Writeback MCIF_WB arbitration parameters */
2747 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
2748
2749 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
2750 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
2751 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
173932de 2752 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
7ed4e635 2753 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
799c5b9c 2754 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
7ed4e635
HW		 2755 context->bw_ctx.bw.dcn.clk.p_state_change_support =
2756 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
2757 != dm_dram_clock_change_unsupported;
2758 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
2759
41f03a6d
DL		 2760 /*
2761 * An artifact of dml pipe split/odm is that pipes get merged back together for
2762 * calculation. Therefore we need to only extract for first pipe in ascending index order
2763 * and copy into the other split half.
2764 */
2765 for (i = 0, pipe_idx = 0, pipe_idx_unsplit = 0; i < dc->res_pool->pipe_count; i++) {
2766 if (!context->res_ctx.pipe_ctx[i].stream)
2767 continue;
6de20237 2768
41f03a6d 2769 if (!visited[pipe_idx]) {
74df06dd
DL		 2770 display_pipe_source_params_st *src = &pipes[pipe_idx].pipe.src;
2771 display_pipe_dest_params_st *dst = &pipes[pipe_idx].pipe.dest;
41f03a6d
DL		 2772
2773 dst->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
2774 dst->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
2775 dst->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
2776 dst->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
2777 /*
2778 * j iterates inside pipes array, unlike i which iterates inside
2779 * pipe_ctx array
2780 */
2781 if (src->is_hsplit)
2782 for (j = pipe_idx + 1; j < pipe_cnt; j++) {
2783 display_pipe_source_params_st *src_j = &pipes[j].pipe.src;
2784 display_pipe_dest_params_st *dst_j = &pipes[j].pipe.dest;
2785
2786 if (src_j->is_hsplit && !visited[j]
2787 && src->hsplit_grp == src_j->hsplit_grp) {
2788 dst_j->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
2789 dst_j->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
2790 dst_j->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
2791 dst_j->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
2792 visited[j] = true;
2793 }
2794 }
2795 visited[pipe_idx] = true;
2796 pipe_idx_unsplit++;
2797 }
2798 pipe_idx++;
2799 }
42351c66 2800
7ed4e635
HW		 2801 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2802 if (!context->res_ctx.pipe_ctx[i].stream)
2803 continue;
7ed4e635
HW		 2804 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2805 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
2806 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
2807 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
41f03a6d 2808 ASSERT(visited[pipe_idx]);
7ed4e635
HW		 2809 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
2810 pipe_idx++;
2811 }
925f566c
CL		 2812 /*save a original dppclock copy*/
2813 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
2814 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
41f03a6d
DL		 2815 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
2816 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
7ed4e635
HW		 2817
2818 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2819 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
2820
2821 if (!context->res_ctx.pipe_ctx[i].stream)
2822 continue;
2823
2824 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
2825 &context->res_ctx.pipe_ctx[i].dlg_regs,
2826 &context->res_ctx.pipe_ctx[i].ttu_regs,
2827 pipes,
2828 pipe_cnt,
2829 pipe_idx,
2830 cstate_en,
f82c916c
CL		 2831 context->bw_ctx.bw.dcn.clk.p_state_change_support,
2832 false, false, false);
254eb07c 2833
7ed4e635
HW		 2834 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
2835 &context->res_ctx.pipe_ctx[i].rq_regs,
2836 pipes[pipe_idx].pipe);
2837 pipe_idx++;
2838 }
6de20237
EY		 2839}
2840
057fc695 2841static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
6de20237
EY		 2842 bool fast_validate)
2843{
2844 bool out = false;
2845
2846 BW_VAL_TRACE_SETUP();
2847
2848 int vlevel = 0;
2849 int pipe_split_from[MAX_PIPES];
2850 int pipe_cnt = 0;
2851 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2852 DC_LOGGER_INIT(dc->ctx->logger);
2853
2854 BW_VAL_TRACE_COUNT();
2855
5e335add
EY		 2856 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
2857
2858 if (pipe_cnt == 0)
2859 goto validate_out;
6de20237
EY		 2860
2861 if (!out)
2862 goto validate_fail;
2863
2864 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2865
2866 if (fast_validate) {
2867 BW_VAL_TRACE_SKIP(fast);
2868 goto validate_out;
2869 }
2870
2871 dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
2872 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2873
2874 BW_VAL_TRACE_END_WATERMARKS();
7ed4e635 2875
254eb07c 2876 goto validate_out;
7ed4e635
HW		 2877
2878validate_fail:
00999d99
DL		 2879 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2880 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
254eb07c 2881
42351c66 2882 BW_VAL_TRACE_SKIP(fail);
254eb07c
JA		 2883 out = false;
2884
2885validate_out:
7ed4e635 2886 kfree(pipes);
254eb07c 2887
42351c66
JA		 2888 BW_VAL_TRACE_FINISH();
2889
254eb07c 2890 return out;
7ed4e635
HW		 2891}
2892
057fc695
JL		 2893
2894bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
2895 bool fast_validate)
2896{
2897 bool voltage_supported = false;
2898 bool full_pstate_supported = false;
2899 bool dummy_pstate_supported = false;
7a8a3430 2900 double p_state_latency_us;
057fc695 2901
7a8a3430
TP		 2902 DC_FP_START();
2903 p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
2904 context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support =
2905 dc->debug.disable_dram_clock_change_vactive_support;
057fc695 2906
7a8a3430
TP		 2907 if (fast_validate) {
2908 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, true);
2909
2910 DC_FP_END();
2911 return voltage_supported;
2912 }
057fc695
JL		 2913
2914 // Best case, we support full UCLK switch latency
2915 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
2916 full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
2917
2918 if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
2919 (voltage_supported && full_pstate_supported)) {
2920 context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
2921 goto restore_dml_state;
2922 }
2923
b9e8d95a 2924 // Fallback: Try to only support G6 temperature read latency
057fc695
JL		 2925 context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
2926
2927 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
2928 dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
2929
2930 if (voltage_supported && dummy_pstate_supported) {
2931 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
2932 goto restore_dml_state;
2933 }
2934
b9e8d95a 2935 // ERROR: fallback is supposed to always work.
057fc695
JL		 2936 ASSERT(false);
2937
2938restore_dml_state:
057fc695
JL		 2939 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
2940
7a8a3430 2941 DC_FP_END();
057fc695
JL		 2942 return voltage_supported;
2943}
2944
7ed4e635
HW		 2945struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
2946 struct dc_state *state,
2947 const struct resource_pool *pool,
2948 struct dc_stream_state *stream)
2949{
2950 struct resource_context *res_ctx = &state->res_ctx;
2951 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
2952 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
2953
2954 if (!head_pipe)
2955 ASSERT(0);
2956
2957 if (!idle_pipe)
7a17c8ce 2958 return NULL;
7ed4e635
HW		 2959
2960 idle_pipe->stream = head_pipe->stream;
2961 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
2962 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
2963
2964 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
2965 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
2966 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
2967 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
2968
2969 return idle_pipe;
2970}
2971
2972bool dcn20_get_dcc_compression_cap(const struct dc *dc,
2973 const struct dc_dcc_surface_param *input,
2974 struct dc_surface_dcc_cap *output)
2975{
2976 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
2977 dc->res_pool->hubbub,
2978 input,
2979 output);
2980}
2981
2982static void dcn20_destroy_resource_pool(struct resource_pool **pool)
2983{
2984 struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);
2985
d9e32672 2986 dcn20_resource_destruct(dcn20_pool);
7ed4e635
HW		 2987 kfree(dcn20_pool);
2988 *pool = NULL;
2989}
2990
2991
2992static struct dc_cap_funcs cap_funcs = {
2993 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
2994};
2995
2996
2997enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state)
2998{
2999 enum dc_status result = DC_OK;
3000
3001 enum surface_pixel_format surf_pix_format = plane_state->format;
3002 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
3003
3004 enum swizzle_mode_values swizzle = DC_SW_LINEAR;
3005
3006 if (bpp == 64)
3007 swizzle = DC_SW_64KB_D;
3008 else
3009 swizzle = DC_SW_64KB_S;
3010
3011 plane_state->tiling_info.gfx9.swizzle = swizzle;
3012 return result;
3013}
3014
3015static struct resource_funcs dcn20_res_pool_funcs = {
3016 .destroy = dcn20_destroy_resource_pool,
3017 .link_enc_create = dcn20_link_encoder_create,
3018 .validate_bandwidth = dcn20_validate_bandwidth,
7ed4e635
HW		 3019 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
3020 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
3021 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
3022 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
3023 .get_default_swizzle_mode = dcn20_get_default_swizzle_mode,
c9ae6e16 3024 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
b6bfba6c 3025 .populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
278141f5 3026 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
7ed4e635
HW		 3027};
3028
bb21290f
CL		 3029bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
3030{
3031 int i;
3032 uint32_t pipe_count = pool->res_cap->num_dwb;
3033
bb21290f
CL		 3034 for (i = 0; i < pipe_count; i++) {
3035 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
3036 GFP_KERNEL);
3037
3038 if (!dwbc20) {
3039 dm_error("DC: failed to create dwbc20!\n");
3040 return false;
3041 }
3042 dcn20_dwbc_construct(dwbc20, ctx,
3043 &dwbc20_regs[i],
3044 &dwbc20_shift,
3045 &dwbc20_mask,
3046 i);
3047 pool->dwbc[i] = &dwbc20->base;
3048 }
3049 return true;
3050}
3051
3052bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
3053{
3054 int i;
3055 uint32_t pipe_count = pool->res_cap->num_dwb;
3056
3057 ASSERT(pipe_count > 0);
3058
3059 for (i = 0; i < pipe_count; i++) {
3060 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub),
3061 GFP_KERNEL);
3062
3063 if (!mcif_wb20) {
3064 dm_error("DC: failed to create mcif_wb20!\n");
3065 return false;
3066 }
3067
3068 dcn20_mmhubbub_construct(mcif_wb20, ctx,
3069 &mcif_wb20_regs[i],
3070 &mcif_wb20_shift,
3071 &mcif_wb20_mask,
3072 i);
3073
3074 pool->mcif_wb[i] = &mcif_wb20->base;
3075 }
3076 return true;
3077}
3078
44e149bb 3079static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
7ed4e635
HW		 3080{
3081 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
3082
3083 if (!pp_smu)
3084 return pp_smu;
3085
3086 dm_pp_get_funcs(ctx, pp_smu);
3087
3088 if (pp_smu->ctx.ver != PP_SMU_VER_NV)
3089 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
3090
3091 return pp_smu;
3092}
3093
44e149bb 3094static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
7ed4e635
HW		 3095{
3096 if (pp_smu && *pp_smu) {
3097 kfree(*pp_smu);
3098 *pp_smu = NULL;
3099 }
3100}
3101
44ce0cd3 3102void dcn20_cap_soc_clocks(
7ed4e635
HW		 3103 struct _vcs_dpi_soc_bounding_box_st *bb,
3104 struct pp_smu_nv_clock_table max_clocks)
3105{
3106 int i;
3107
3108 // First pass - cap all clocks higher than the reported max
3109 for (i = 0; i < bb->num_states; i++) {
3110 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
3111 && max_clocks.dcfClockInKhz != 0)
3112 bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
3113
3114 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
3115 && max_clocks.uClockInKhz != 0)
3116 bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
3117
3118 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
3119 && max_clocks.fabricClockInKhz != 0)
3120 bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
3121
3122 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
3123 && max_clocks.displayClockInKhz != 0)
3124 bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
3125
3126 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
3127 && max_clocks.dppClockInKhz != 0)
3128 bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
3129
3130 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
3131 && max_clocks.phyClockInKhz != 0)
3132 bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
3133
3134 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
3135 && max_clocks.socClockInKhz != 0)
3136 bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
3137
3138 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
3139 && max_clocks.dscClockInKhz != 0)
3140 bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
3141 }
3142
3143 // Second pass - remove all duplicate clock states
3144 for (i = bb->num_states - 1; i > 1; i--) {
3145 bool duplicate = true;
3146
3147 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz)
3148 duplicate = false;
3149 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz)
3150 duplicate = false;
3151 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz)
3152 duplicate = false;
3153 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts)
3154 duplicate = false;
3155 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz)
3156 duplicate = false;
3157 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz)
3158 duplicate = false;
3159 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz)
3160 duplicate = false;
3161 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz)
3162 duplicate = false;
3163
3164 if (duplicate)
3165 bb->num_states--;
3166 }
3167}
3168
44ce0cd3 3169void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
7ed4e635
HW		 3170 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
3171{
960b6f4f 3172 struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES];
f18bc4e5 3173 int i;
7ed4e635 3174 int num_calculated_states = 0;
f18bc4e5 3175 int min_dcfclk = 0;
7ed4e635
HW		 3176
3177 if (num_states == 0)
3178 return;
3179
960b6f4f
RR		 3180 memset(calculated_states, 0, sizeof(calculated_states));
3181
f18bc4e5
JL		 3182 if (dc->bb_overrides.min_dcfclk_mhz > 0)
3183 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
6ce2427d
AL		 3184 else {
3185 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
3186 min_dcfclk = 310;
3187 else
3188 // Accounting for SOC/DCF relationship, we can go as high as
3189 // 506Mhz in Vmin.
3190 min_dcfclk = 506;
3191 }
f18bc4e5 3192
7ed4e635 3193 for (i = 0; i < num_states; i++) {
f18bc4e5
JL		 3194 int min_fclk_required_by_uclk;
3195 calculated_states[i].state = i;
3196 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
7ed4e635 3197
5d36f783 3198 // FCLK:UCLK ratio is 1.08
5f65ae34 3199 min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32);
7ed4e635 3200
f18bc4e5
JL		 3201 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
3202 min_dcfclk : min_fclk_required_by_uclk;
7ed4e635 3203
f18bc4e5
JL		 3204 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
3205 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
7ed4e635 3206
f18bc4e5
JL		 3207 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
3208 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
7ed4e635 3209
f18bc4e5
JL		 3210 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
3211 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
3212 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
7ed4e635 3213
f18bc4e5 3214 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
7ed4e635 3215
f18bc4e5 3216 num_calculated_states++;
7ed4e635
HW		 3217 }
3218
6da16270
JL		 3219 calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
3220 calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
3221 calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
3222
7ed4e635
HW		 3223 memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
3224 bb->num_states = num_calculated_states;
f18bc4e5
JL		 3225
3226 // Duplicate the last state, DML always an extra state identical to max state to work
3227 memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st));
3228 bb->clock_limits[num_calculated_states].state = bb->num_states;
7ed4e635
HW		 3229}
3230
44ce0cd3 3231void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
7ed4e635 3232{
7ed4e635
HW		 3233 if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
3234 && dc->bb_overrides.sr_exit_time_ns) {
3235 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
3236 }
3237
3238 if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
3239 != dc->bb_overrides.sr_enter_plus_exit_time_ns
3240 && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
3241 bb->sr_enter_plus_exit_time_us =
3242 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
3243 }
3244
3245 if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
3246 && dc->bb_overrides.urgent_latency_ns) {
3247 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
3248 }
3249
3250 if ((int)(bb->dram_clock_change_latency_us * 1000)
3251 != dc->bb_overrides.dram_clock_change_latency_ns
3252 && dc->bb_overrides.dram_clock_change_latency_ns) {
3253 bb->dram_clock_change_latency_us =
3254 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
3255 }
7ed4e635
HW		 3256}
3257
675a9e38
LL		 3258static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
3259 uint32_t hw_internal_rev)
3260{
3261 if (ASICREV_IS_NAVI12_P(hw_internal_rev))
3262 return &dcn2_0_nv12_soc;
3263
3264 return &dcn2_0_soc;
3265}
3266
3267static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(
3268 uint32_t hw_internal_rev)
3269{
72b741af
Z		 3270 /* NV14 */
3271 if (ASICREV_IS_NAVI14_M(hw_internal_rev))
3272 return &dcn2_0_nv14_ip;
3273
675a9e38
LL		 3274 /* NV12 and NV10 */
3275 return &dcn2_0_ip;
3276}
3277
3278static enum dml_project get_dml_project_version(uint32_t hw_internal_rev)
3279{
3280 return DML_PROJECT_NAVI10v2;
3281}
3282
7ed4e635
HW		 3283#define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
3284#define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
3285
3286static bool init_soc_bounding_box(struct dc *dc,
3287 struct dcn20_resource_pool *pool)
3288{
3289 const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
675a9e38
LL		 3290 struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3291 get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);
3292 struct _vcs_dpi_ip_params_st *loaded_ip =
3293 get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);
3294
7ed4e635
HW		 3295 DC_LOGGER_INIT(dc->ctx->logger);
3296
3e0c55f3
ZL		 3297 /* TODO: upstream NV12 bounding box when its launched */
3298 if (!bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
7ed4e635
HW		 3299 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
3300 return false;
3301 }
3302
3e0c55f3 3303 if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
7ed4e635
HW		 3304 int i;
3305
675a9e38 3306 dcn2_0_nv12_soc.sr_exit_time_us =
7ed4e635 3307 fixed16_to_double_to_cpu(bb->sr_exit_time_us);
675a9e38 3308 dcn2_0_nv12_soc.sr_enter_plus_exit_time_us =
7ed4e635 3309 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us);
675a9e38 3310 dcn2_0_nv12_soc.urgent_latency_us =
7ed4e635 3311 fixed16_to_double_to_cpu(bb->urgent_latency_us);
675a9e38 3312 dcn2_0_nv12_soc.urgent_latency_pixel_data_only_us =
7ed4e635 3313 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us);
675a9e38 3314 dcn2_0_nv12_soc.urgent_latency_pixel_mixed_with_vm_data_us =
7ed4e635 3315 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us);
675a9e38 3316 dcn2_0_nv12_soc.urgent_latency_vm_data_only_us =
7ed4e635 3317 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us);
675a9e38 3318 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
7ed4e635 3319 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes);
675a9e38 3320 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
7ed4e635 3321 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes);
675a9e38 3322 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
7ed4e635 3323 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes);
675a9e38 3324 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
7ed4e635 3325 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only);
675a9e38 3326 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
7ed4e635 3327 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm);
675a9e38 3328 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
7ed4e635 3329 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only);
675a9e38 3330 dcn2_0_nv12_soc.max_avg_sdp_bw_use_normal_percent =
7ed4e635 3331 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent);
675a9e38 3332 dcn2_0_nv12_soc.max_avg_dram_bw_use_normal_percent =
7ed4e635 3333 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent);
675a9e38 3334 dcn2_0_nv12_soc.writeback_latency_us =
7ed4e635 3335 fixed16_to_double_to_cpu(bb->writeback_latency_us);
675a9e38 3336 dcn2_0_nv12_soc.ideal_dram_bw_after_urgent_percent =
7ed4e635 3337 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent);
675a9e38 3338 dcn2_0_nv12_soc.max_request_size_bytes =
7ed4e635 3339 le32_to_cpu(bb->max_request_size_bytes);
675a9e38 3340 dcn2_0_nv12_soc.dram_channel_width_bytes =
7ed4e635 3341 le32_to_cpu(bb->dram_channel_width_bytes);
675a9e38 3342 dcn2_0_nv12_soc.fabric_datapath_to_dcn_data_return_bytes =
7ed4e635 3343 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes);
675a9e38 3344 dcn2_0_nv12_soc.dcn_downspread_percent =
7ed4e635 3345 fixed16_to_double_to_cpu(bb->dcn_downspread_percent);
675a9e38 3346 dcn2_0_nv12_soc.downspread_percent =
7ed4e635 3347 fixed16_to_double_to_cpu(bb->downspread_percent);
675a9e38 3348 dcn2_0_nv12_soc.dram_page_open_time_ns =
7ed4e635 3349 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns);
675a9e38 3350 dcn2_0_nv12_soc.dram_rw_turnaround_time_ns =
7ed4e635 3351 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns);
675a9e38 3352 dcn2_0_nv12_soc.dram_return_buffer_per_channel_bytes =
7ed4e635 3353 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes);
675a9e38 3354 dcn2_0_nv12_soc.round_trip_ping_latency_dcfclk_cycles =
7ed4e635 3355 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles);
675a9e38 3356 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_bytes =
7ed4e635 3357 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes);
675a9e38 3358 dcn2_0_nv12_soc.channel_interleave_bytes =
7ed4e635 3359 le32_to_cpu(bb->channel_interleave_bytes);
675a9e38 3360 dcn2_0_nv12_soc.num_banks =
7ed4e635 3361 le32_to_cpu(bb->num_banks);
675a9e38 3362 dcn2_0_nv12_soc.num_chans =
7ed4e635 3363 le32_to_cpu(bb->num_chans);
675a9e38 3364 dcn2_0_nv12_soc.vmm_page_size_bytes =
7ed4e635 3365 le32_to_cpu(bb->vmm_page_size_bytes);
675a9e38 3366 dcn2_0_nv12_soc.dram_clock_change_latency_us =
7ed4e635 3367 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
675a9e38
LL		 3368 // HACK!! Lower uclock latency switch time so we don't switch
3369 dcn2_0_nv12_soc.dram_clock_change_latency_us = 10;
3370 dcn2_0_nv12_soc.writeback_dram_clock_change_latency_us =
7ed4e635 3371 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
675a9e38 3372 dcn2_0_nv12_soc.return_bus_width_bytes =
7ed4e635 3373 le32_to_cpu(bb->return_bus_width_bytes);
675a9e38 3374 dcn2_0_nv12_soc.dispclk_dppclk_vco_speed_mhz =
7ed4e635 3375 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz);
675a9e38 3376 dcn2_0_nv12_soc.xfc_bus_transport_time_us =
7ed4e635 3377 le32_to_cpu(bb->xfc_bus_transport_time_us);
675a9e38 3378 dcn2_0_nv12_soc.xfc_xbuf_latency_tolerance_us =
7ed4e635 3379 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us);
675a9e38 3380 dcn2_0_nv12_soc.use_urgent_burst_bw =
7ed4e635 3381 le32_to_cpu(bb->use_urgent_burst_bw);
675a9e38 3382 dcn2_0_nv12_soc.num_states =
7ed4e635
HW		 3383 le32_to_cpu(bb->num_states);
3384
675a9e38
LL		 3385 for (i = 0; i < dcn2_0_nv12_soc.num_states; i++) {
3386 dcn2_0_nv12_soc.clock_limits[i].state =
7ed4e635 3387 le32_to_cpu(bb->clock_limits[i].state);
675a9e38 3388 dcn2_0_nv12_soc.clock_limits[i].dcfclk_mhz =
7ed4e635 3389 fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz);
675a9e38 3390 dcn2_0_nv12_soc.clock_limits[i].fabricclk_mhz =
7ed4e635 3391 fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz);
675a9e38 3392 dcn2_0_nv12_soc.clock_limits[i].dispclk_mhz =
7ed4e635 3393 fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz);
675a9e38 3394 dcn2_0_nv12_soc.clock_limits[i].dppclk_mhz =
7ed4e635 3395 fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz);
675a9e38 3396 dcn2_0_nv12_soc.clock_limits[i].phyclk_mhz =
7ed4e635 3397 fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz);
675a9e38 3398 dcn2_0_nv12_soc.clock_limits[i].socclk_mhz =
7ed4e635 3399 fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz);
675a9e38 3400 dcn2_0_nv12_soc.clock_limits[i].dscclk_mhz =
7ed4e635 3401 fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz);
675a9e38 3402 dcn2_0_nv12_soc.clock_limits[i].dram_speed_mts =
7ed4e635
HW		 3403 fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
3404 }
3405 }
3406
3407 if (pool->base.pp_smu) {
3408 struct pp_smu_nv_clock_table max_clocks = {0};
3409 unsigned int uclk_states[8] = {0};
3410 unsigned int num_states = 0;
3411 enum pp_smu_status status;
3412 bool clock_limits_available = false;
3413 bool uclk_states_available = false;
3414
3415 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
3416 status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
3417 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
3418
3419 uclk_states_available = (status == PP_SMU_RESULT_OK);
3420 }
3421
3422 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
3423 status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
3424 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
c2ad17c3
AW		 3425 /* SMU cannot set DCF clock to anything equal to or higher than SOC clock
3426 */
3427 if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
3428 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
7ed4e635
HW		 3429 clock_limits_available = (status == PP_SMU_RESULT_OK);
3430 }
3431
c2ad17c3 3432 if (clock_limits_available && uclk_states_available && num_states)
44ce0cd3 3433 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
7ed4e635 3434 else if (clock_limits_available)
44ce0cd3 3435 dcn20_cap_soc_clocks(loaded_bb, max_clocks);
7ed4e635
HW		 3436 }
3437
675a9e38
LL		 3438 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
3439 loaded_ip->max_num_dpp = pool->base.pipe_count;
44ce0cd3 3440 dcn20_patch_bounding_box(dc, loaded_bb);
7ed4e635
HW		 3441
3442 return true;
3443}
3444
d9e32672 3445static bool dcn20_resource_construct(
7ed4e635
HW		 3446 uint8_t num_virtual_links,
3447 struct dc *dc,
3448 struct dcn20_resource_pool *pool)
3449{
3450 int i;
3451 struct dc_context *ctx = dc->ctx;
3452 struct irq_service_init_data init_data;
d9a07577 3453 struct ddc_service_init_data ddc_init_data;
675a9e38
LL		 3454 struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3455 get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);
3456 struct _vcs_dpi_ip_params_st *loaded_ip =
3457 get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev);
3458 enum dml_project dml_project_version =
3459 get_dml_project_version(ctx->asic_id.hw_internal_rev);
7ed4e635 3460
7a8a3430
TP		 3461 DC_FP_START();
3462
7ed4e635 3463 ctx->dc_bios->regs = &bios_regs;
7ed4e635
HW		 3464 pool->base.funcs = &dcn20_res_pool_funcs;
3465
2ebe1773
BL		 3466 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
3467 pool->base.res_cap = &res_cap_nv14;
3468 pool->base.pipe_count = 5;
3469 pool->base.mpcc_count = 5;
3470 } else {
3471 pool->base.res_cap = &res_cap_nv10;
3472 pool->base.pipe_count = 6;
3473 pool->base.mpcc_count = 6;
3474 }
7ed4e635
HW		 3475 /*************************************************
3476 * Resource + asic cap harcoding *
3477 *************************************************/
3478 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
3479
7ed4e635
HW		 3480 dc->caps.max_downscale_ratio = 200;
3481 dc->caps.i2c_speed_in_khz = 100;
3482 dc->caps.max_cursor_size = 256;
3483 dc->caps.dmdata_alloc_size = 2048;
3484
3485 dc->caps.max_slave_planes = 1;
3486 dc->caps.post_blend_color_processing = true;
3487 dc->caps.force_dp_tps4_for_cp2520 = true;
3488 dc->caps.hw_3d_lut = true;
ca4f844e 3489 dc->caps.extended_aux_timeout_support = true;
7ed4e635 3490
803a1412 3491 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) {
7ed4e635 3492 dc->debug = debug_defaults_drv;
803a1412
ES		 3493 } else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
3494 pool->base.pipe_count = 4;
7ed4e635
HW		 3495 pool->base.mpcc_count = pool->base.pipe_count;
3496 dc->debug = debug_defaults_diags;
803a1412 3497 } else {
7ed4e635 3498 dc->debug = debug_defaults_diags;
803a1412 3499 }
7ed4e635
HW		 3500 //dcn2.0x
3501 dc->work_arounds.dedcn20_305_wa = true;
3502
3503 // Init the vm_helper
3504 if (dc->vm_helper)
bda9afda 3505 vm_helper_init(dc->vm_helper, 16);
7ed4e635
HW		 3506
3507 /*************************************************
3508 * Create resources *
3509 *************************************************/
3510
3511 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
3512 dcn20_clock_source_create(ctx, ctx->dc_bios,
3513 CLOCK_SOURCE_COMBO_PHY_PLL0,
3514 &clk_src_regs[0], false);
3515 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
3516 dcn20_clock_source_create(ctx, ctx->dc_bios,
3517 CLOCK_SOURCE_COMBO_PHY_PLL1,
3518 &clk_src_regs[1], false);
3519 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
3520 dcn20_clock_source_create(ctx, ctx->dc_bios,
3521 CLOCK_SOURCE_COMBO_PHY_PLL2,
3522 &clk_src_regs[2], false);
3523 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
3524 dcn20_clock_source_create(ctx, ctx->dc_bios,
3525 CLOCK_SOURCE_COMBO_PHY_PLL3,
3526 &clk_src_regs[3], false);
3527 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
3528 dcn20_clock_source_create(ctx, ctx->dc_bios,
3529 CLOCK_SOURCE_COMBO_PHY_PLL4,
3530 &clk_src_regs[4], false);
3531 pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =
3532 dcn20_clock_source_create(ctx, ctx->dc_bios,
3533 CLOCK_SOURCE_COMBO_PHY_PLL5,
3534 &clk_src_regs[5], false);
3535 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;
3536 /* todo: not reuse phy_pll registers */
3537 pool->base.dp_clock_source =
3538 dcn20_clock_source_create(ctx, ctx->dc_bios,
3539 CLOCK_SOURCE_ID_DP_DTO,
3540 &clk_src_regs[0], true);
3541
3542 for (i = 0; i < pool->base.clk_src_count; i++) {
3543 if (pool->base.clock_sources[i] == NULL) {
3544 dm_error("DC: failed to create clock sources!\n");
3545 BREAK_TO_DEBUGGER();
3546 goto create_fail;
3547 }
3548 }
3549
3550 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
3551 if (pool->base.dccg == NULL) {
3552 dm_error("DC: failed to create dccg!\n");
3553 BREAK_TO_DEBUGGER();
3554 goto create_fail;
3555 }
3556
3557 pool->base.dmcu = dcn20_dmcu_create(ctx,
3558 &dmcu_regs,
3559 &dmcu_shift,
3560 &dmcu_mask);
3561 if (pool->base.dmcu == NULL) {
3562 dm_error("DC: failed to create dmcu!\n");
3563 BREAK_TO_DEBUGGER();
3564 goto create_fail;
3565 }
3566
d7c29549 3567 pool->base.abm = dce_abm_create(ctx,
7ed4e635
HW		 3568 &abm_regs,
3569 &abm_shift,
3570 &abm_mask);
3571 if (pool->base.abm == NULL) {
3572 dm_error("DC: failed to create abm!\n");
3573 BREAK_TO_DEBUGGER();
3574 goto create_fail;
d7c29549 3575 }
7ed4e635
HW		 3576
3577 pool->base.pp_smu = dcn20_pp_smu_create(ctx);
3578
3579
3580 if (!init_soc_bounding_box(dc, pool)) {
3581 dm_error("DC: failed to initialize soc bounding box!\n");
3582 BREAK_TO_DEBUGGER();
3583 goto create_fail;
3584 }
3585
675a9e38 3586 dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version);
7ed4e635
HW		 3587
3588 if (!dc->debug.disable_pplib_wm_range) {
3589 struct pp_smu_wm_range_sets ranges = {0};
3590 int i = 0;
3591
3592 ranges.num_reader_wm_sets = 0;
3593
675a9e38 3594 if (loaded_bb->num_states == 1) {
7ed4e635
HW		 3595 ranges.reader_wm_sets[0].wm_inst = i;
3596 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3597 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3598 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3599 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3600
3601 ranges.num_reader_wm_sets = 1;
675a9e38
LL		 3602 } else if (loaded_bb->num_states > 1) {
3603 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
7ed4e635
HW		 3604 ranges.reader_wm_sets[i].wm_inst = i;
3605 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3606 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
675a9e38
LL		 3607 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
3608 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
7ed4e635
HW		 3609
3610 ranges.num_reader_wm_sets = i + 1;
3611 }
7ed4e635 3612
5d36f783
JL		 3613 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3614 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3615 }
7ed4e635
HW		 3616
3617 ranges.num_writer_wm_sets = 1;
3618
3619 ranges.writer_wm_sets[0].wm_inst = 0;
3620 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3621 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3622 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3623 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3624
3625 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
3626 if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
3627 pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);
3628 }
3629
3630 init_data.ctx = dc->ctx;
3631 pool->base.irqs = dal_irq_service_dcn20_create(&init_data);
3632 if (!pool->base.irqs)
3633 goto create_fail;
3634
3635 /* mem input -> ipp -> dpp -> opp -> TG */
3636 for (i = 0; i < pool->base.pipe_count; i++) {
3637 pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
3638 if (pool->base.hubps[i] == NULL) {
3639 BREAK_TO_DEBUGGER();
3640 dm_error(
3641 "DC: failed to create memory input!\n");
3642 goto create_fail;
3643 }
3644
3645 pool->base.ipps[i] = dcn20_ipp_create(ctx, i);
3646 if (pool->base.ipps[i] == NULL) {
3647 BREAK_TO_DEBUGGER();
3648 dm_error(
3649 "DC: failed to create input pixel processor!\n");
3650 goto create_fail;
3651 }
3652
3653 pool->base.dpps[i] = dcn20_dpp_create(ctx, i);
3654 if (pool->base.dpps[i] == NULL) {
3655 BREAK_TO_DEBUGGER();
3656 dm_error(
3657 "DC: failed to create dpps!\n");
3658 goto create_fail;
3659 }
3660 }
3661 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
3662 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i);
3663 if (pool->base.engines[i] == NULL) {
3664 BREAK_TO_DEBUGGER();
3665 dm_error(
3666 "DC:failed to create aux engine!!\n");
3667 goto create_fail;
3668 }
3669 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i);
3670 if (pool->base.hw_i2cs[i] == NULL) {
3671 BREAK_TO_DEBUGGER();
3672 dm_error(
3673 "DC:failed to create hw i2c!!\n");
3674 goto create_fail;
3675 }
3676 pool->base.sw_i2cs[i] = NULL;
3677 }
3678
3679 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
3680 pool->base.opps[i] = dcn20_opp_create(ctx, i);
3681 if (pool->base.opps[i] == NULL) {
3682 BREAK_TO_DEBUGGER();
3683 dm_error(
3684 "DC: failed to create output pixel processor!\n");
3685 goto create_fail;
3686 }
3687 }
3688
3689 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
3690 pool->base.timing_generators[i] = dcn20_timing_generator_create(
3691 ctx, i);
3692 if (pool->base.timing_generators[i] == NULL) {
3693 BREAK_TO_DEBUGGER();
3694 dm_error("DC: failed to create tg!\n");
3695 goto create_fail;
3696 }
3697 }
3698
3699 pool->base.timing_generator_count = i;
3700
3701 pool->base.mpc = dcn20_mpc_create(ctx);
3702 if (pool->base.mpc == NULL) {
3703 BREAK_TO_DEBUGGER();
3704 dm_error("DC: failed to create mpc!\n");
3705 goto create_fail;
3706 }
3707
3708 pool->base.hubbub = dcn20_hubbub_create(ctx);
3709 if (pool->base.hubbub == NULL) {
3710 BREAK_TO_DEBUGGER();
3711 dm_error("DC: failed to create hubbub!\n");
3712 goto create_fail;
3713 }
3714
97bda032
HW		 3715 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
3716 pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
3717 if (pool->base.dscs[i] == NULL) {
3718 BREAK_TO_DEBUGGER();
3719 dm_error("DC: failed to create display stream compressor %d!\n", i);
3720 goto create_fail;
3721 }
3722 }
7ed4e635 3723
bb21290f
CL		 3724 if (!dcn20_dwbc_create(ctx, &pool->base)) {
3725 BREAK_TO_DEBUGGER();
3726 dm_error("DC: failed to create dwbc!\n");
3727 goto create_fail;
3728 }
3729 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
3730 BREAK_TO_DEBUGGER();
3731 dm_error("DC: failed to create mcif_wb!\n");
3732 goto create_fail;
3733 }
3734
7ed4e635
HW		 3735 if (!resource_construct(num_virtual_links, dc, &pool->base,
3736 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
3737 &res_create_funcs : &res_create_maximus_funcs)))
3738 goto create_fail;
3739
3740 dcn20_hw_sequencer_construct(dc);
3741
3742 dc->caps.max_planes = pool->base.pipe_count;
3743
3744 for (i = 0; i < dc->caps.max_planes; ++i)
3745 dc->caps.planes[i] = plane_cap;
3746
3747 dc->cap_funcs = cap_funcs;
3748
d9a07577
JL		 3749 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
3750 ddc_init_data.ctx = dc->ctx;
3751 ddc_init_data.link = NULL;
3752 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
3753 ddc_init_data.id.enum_id = 0;
3754 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
3755 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
3756 } else {
3757 pool->base.oem_device = NULL;
3758 }
3759
7a8a3430 3760 DC_FP_END();
7ed4e635
HW		 3761 return true;
3762
3763create_fail:
3764
7a8a3430 3765 DC_FP_END();
d9e32672 3766 dcn20_resource_destruct(pool);
7ed4e635
HW		 3767
3768 return false;
3769}
3770
3771struct resource_pool *dcn20_create_resource_pool(
3772 const struct dc_init_data *init_data,
3773 struct dc *dc)
3774{
3775 struct dcn20_resource_pool *pool =
3776 kzalloc(sizeof(struct dcn20_resource_pool), GFP_KERNEL);
3777
3778 if (!pool)
3779 return NULL;
3780
d9e32672 3781 if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool))
7ed4e635
HW		 3782 return &pool->base;
3783
3784 BREAK_TO_DEBUGGER();
3785 kfree(pool);
3786 return NULL;
3787}
Linux 6.x block layer and io_uring tree(s)