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drm/amd/display: 3.2.44
[linux-block.git] / drivers / gpu / drm / amd / display / dc / dcn20 / dcn20_resource.c
CommitLineData
7ed4e635
HW		 1/*
2* Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
d7929c1e
AD		 26#include <linux/slab.h>
27
7ed4e635
HW		 28#include "dm_services.h"
29#include "dc.h"
30
31#include "resource.h"
32#include "include/irq_service_interface.h"
33#include "dcn20/dcn20_resource.h"
34
35#include "dcn10/dcn10_hubp.h"
36#include "dcn10/dcn10_ipp.h"
37#include "dcn20_hubbub.h"
38#include "dcn20_mpc.h"
39#include "dcn20_hubp.h"
40#include "irq/dcn20/irq_service_dcn20.h"
41#include "dcn20_dpp.h"
42#include "dcn20_optc.h"
43#include "dcn20_hwseq.h"
44#include "dce110/dce110_hw_sequencer.h"
278141f5 45#include "dcn10/dcn10_resource.h"
7ed4e635
HW		 46#include "dcn20_opp.h"
47
97bda032
HW		 48#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
49#include "dcn20_dsc.h"
50#endif
51
7ed4e635
HW		 52#include "dcn20_link_encoder.h"
53#include "dcn20_stream_encoder.h"
54#include "dce/dce_clock_source.h"
55#include "dce/dce_audio.h"
56#include "dce/dce_hwseq.h"
57#include "virtual/virtual_stream_encoder.h"
58#include "dce110/dce110_resource.h"
59#include "dml/display_mode_vba.h"
60#include "dcn20_dccg.h"
61#include "dcn20_vmid.h"
62
63#include "navi10_ip_offset.h"
64
65#include "dcn/dcn_2_0_0_offset.h"
66#include "dcn/dcn_2_0_0_sh_mask.h"
67
68#include "nbio/nbio_2_3_offset.h"
69
bb21290f
CL		 70#include "dcn20/dcn20_dwb.h"
71#include "dcn20/dcn20_mmhubbub.h"
72
7ed4e635
HW		 73#include "mmhub/mmhub_2_0_0_offset.h"
74#include "mmhub/mmhub_2_0_0_sh_mask.h"
75
76#include "reg_helper.h"
77#include "dce/dce_abm.h"
78#include "dce/dce_dmcu.h"
79#include "dce/dce_aux.h"
80#include "dce/dce_i2c.h"
81#include "vm_helper.h"
82
83#include "amdgpu_socbb.h"
84
fb6959ae 85#define SOC_BOUNDING_BOX_VALID true
7ed4e635
HW		 86#define DC_LOGGER_INIT(logger)
87
88struct _vcs_dpi_ip_params_st dcn2_0_ip = {
89 .odm_capable = 1,
90 .gpuvm_enable = 0,
91 .hostvm_enable = 0,
92 .gpuvm_max_page_table_levels = 4,
93 .hostvm_max_page_table_levels = 4,
94 .hostvm_cached_page_table_levels = 0,
95 .pte_group_size_bytes = 2048,
97bda032
HW		 96#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
97 .num_dsc = 6,
98#else
7ed4e635 99 .num_dsc = 0,
97bda032 100#endif
7ed4e635
HW		 101 .rob_buffer_size_kbytes = 168,
102 .det_buffer_size_kbytes = 164,
103 .dpte_buffer_size_in_pte_reqs_luma = 84,
104 .pde_proc_buffer_size_64k_reqs = 48,
105 .dpp_output_buffer_pixels = 2560,
106 .opp_output_buffer_lines = 1,
107 .pixel_chunk_size_kbytes = 8,
108 .pte_chunk_size_kbytes = 2,
109 .meta_chunk_size_kbytes = 2,
110 .writeback_chunk_size_kbytes = 2,
111 .line_buffer_size_bits = 789504,
112 .is_line_buffer_bpp_fixed = 0,
113 .line_buffer_fixed_bpp = 0,
114 .dcc_supported = true,
115 .max_line_buffer_lines = 12,
116 .writeback_luma_buffer_size_kbytes = 12,
117 .writeback_chroma_buffer_size_kbytes = 8,
118 .writeback_chroma_line_buffer_width_pixels = 4,
119 .writeback_max_hscl_ratio = 1,
120 .writeback_max_vscl_ratio = 1,
121 .writeback_min_hscl_ratio = 1,
122 .writeback_min_vscl_ratio = 1,
123 .writeback_max_hscl_taps = 12,
124 .writeback_max_vscl_taps = 12,
125 .writeback_line_buffer_luma_buffer_size = 0,
126 .writeback_line_buffer_chroma_buffer_size = 14643,
127 .cursor_buffer_size = 8,
128 .cursor_chunk_size = 2,
129 .max_num_otg = 6,
130 .max_num_dpp = 6,
131 .max_num_wb = 1,
132 .max_dchub_pscl_bw_pix_per_clk = 4,
133 .max_pscl_lb_bw_pix_per_clk = 2,
134 .max_lb_vscl_bw_pix_per_clk = 4,
135 .max_vscl_hscl_bw_pix_per_clk = 4,
136 .max_hscl_ratio = 8,
137 .max_vscl_ratio = 8,
138 .hscl_mults = 4,
139 .vscl_mults = 4,
140 .max_hscl_taps = 8,
141 .max_vscl_taps = 8,
142 .dispclk_ramp_margin_percent = 1,
143 .underscan_factor = 1.10,
144 .min_vblank_lines = 32, //
145 .dppclk_delay_subtotal = 77, //
146 .dppclk_delay_scl_lb_only = 16,
147 .dppclk_delay_scl = 50,
148 .dppclk_delay_cnvc_formatter = 8,
149 .dppclk_delay_cnvc_cursor = 6,
150 .dispclk_delay_subtotal = 87, //
151 .dcfclk_cstate_latency = 10, // SRExitTime
152 .max_inter_dcn_tile_repeaters = 8,
153
154 .xfc_supported = true,
155 .xfc_fill_bw_overhead_percent = 10.0,
156 .xfc_fill_constant_bytes = 0,
157};
158
fb6959ae
NK		 159struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
160 /* Defaults that get patched on driver load from firmware. */
161 .clock_limits = {
162 {
163 .state = 0,
164 .dcfclk_mhz = 560.0,
165 .fabricclk_mhz = 560.0,
166 .dispclk_mhz = 513.0,
167 .dppclk_mhz = 513.0,
168 .phyclk_mhz = 540.0,
169 .socclk_mhz = 560.0,
170 .dscclk_mhz = 171.0,
171 .dram_speed_mts = 8960.0,
172 },
173 {
174 .state = 1,
175 .dcfclk_mhz = 694.0,
176 .fabricclk_mhz = 694.0,
177 .dispclk_mhz = 642.0,
178 .dppclk_mhz = 642.0,
179 .phyclk_mhz = 600.0,
180 .socclk_mhz = 694.0,
181 .dscclk_mhz = 214.0,
182 .dram_speed_mts = 11104.0,
183 },
184 {
185 .state = 2,
186 .dcfclk_mhz = 875.0,
187 .fabricclk_mhz = 875.0,
188 .dispclk_mhz = 734.0,
189 .dppclk_mhz = 734.0,
190 .phyclk_mhz = 810.0,
191 .socclk_mhz = 875.0,
192 .dscclk_mhz = 245.0,
193 .dram_speed_mts = 14000.0,
194 },
195 {
196 .state = 3,
197 .dcfclk_mhz = 1000.0,
198 .fabricclk_mhz = 1000.0,
199 .dispclk_mhz = 1100.0,
200 .dppclk_mhz = 1100.0,
201 .phyclk_mhz = 810.0,
202 .socclk_mhz = 1000.0,
203 .dscclk_mhz = 367.0,
204 .dram_speed_mts = 16000.0,
205 },
206 {
207 .state = 4,
208 .dcfclk_mhz = 1200.0,
209 .fabricclk_mhz = 1200.0,
210 .dispclk_mhz = 1284.0,
211 .dppclk_mhz = 1284.0,
212 .phyclk_mhz = 810.0,
213 .socclk_mhz = 1200.0,
214 .dscclk_mhz = 428.0,
215 .dram_speed_mts = 16000.0,
216 },
217 /*Extra state, no dispclk ramping*/
218 {
219 .state = 5,
220 .dcfclk_mhz = 1200.0,
221 .fabricclk_mhz = 1200.0,
222 .dispclk_mhz = 1284.0,
223 .dppclk_mhz = 1284.0,
224 .phyclk_mhz = 810.0,
225 .socclk_mhz = 1200.0,
226 .dscclk_mhz = 428.0,
227 .dram_speed_mts = 16000.0,
228 },
229 },
230 .num_states = 5,
231 .sr_exit_time_us = 8.6,
232 .sr_enter_plus_exit_time_us = 10.9,
233 .urgent_latency_us = 4.0,
234 .urgent_latency_pixel_data_only_us = 4.0,
235 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
236 .urgent_latency_vm_data_only_us = 4.0,
237 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
238 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
239 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
240 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
241 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
242 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
243 .max_avg_sdp_bw_use_normal_percent = 40.0,
244 .max_avg_dram_bw_use_normal_percent = 40.0,
245 .writeback_latency_us = 12.0,
246 .ideal_dram_bw_after_urgent_percent = 40.0,
247 .max_request_size_bytes = 256,
248 .dram_channel_width_bytes = 2,
249 .fabric_datapath_to_dcn_data_return_bytes = 64,
250 .dcn_downspread_percent = 0.5,
251 .downspread_percent = 0.38,
252 .dram_page_open_time_ns = 50.0,
253 .dram_rw_turnaround_time_ns = 17.5,
254 .dram_return_buffer_per_channel_bytes = 8192,
255 .round_trip_ping_latency_dcfclk_cycles = 131,
256 .urgent_out_of_order_return_per_channel_bytes = 256,
257 .channel_interleave_bytes = 256,
258 .num_banks = 8,
259 .num_chans = 16,
260 .vmm_page_size_bytes = 4096,
261 .dram_clock_change_latency_us = 404.0,
262 .dummy_pstate_latency_us = 5.0,
263 .writeback_dram_clock_change_latency_us = 23.0,
264 .return_bus_width_bytes = 64,
265 .dispclk_dppclk_vco_speed_mhz = 3850,
266 .xfc_bus_transport_time_us = 20,
267 .xfc_xbuf_latency_tolerance_us = 4,
268 .use_urgent_burst_bw = 0
269};
7ed4e635
HW		 270
271
272#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
273 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
274 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
275 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
276 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
277 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
278 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
279 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
280 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
281 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
282 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
283 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
284 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
285 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
286 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
287#endif
288
289
290enum dcn20_clk_src_array_id {
291 DCN20_CLK_SRC_PLL0,
292 DCN20_CLK_SRC_PLL1,
293 DCN20_CLK_SRC_PLL2,
294 DCN20_CLK_SRC_PLL3,
295 DCN20_CLK_SRC_PLL4,
296 DCN20_CLK_SRC_PLL5,
297 DCN20_CLK_SRC_TOTAL
298};
299
300/* begin *********************
301 * macros to expend register list macro defined in HW object header file */
302
303/* DCN */
304/* TODO awful hack. fixup dcn20_dwb.h */
305#undef BASE_INNER
306#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
307
308#define BASE(seg) BASE_INNER(seg)
309
310#define SR(reg_name)\
311 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
312 mm ## reg_name
313
314#define SRI(reg_name, block, id)\
315 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
316 mm ## block ## id ## _ ## reg_name
317
318#define SRIR(var_name, reg_name, block, id)\
319 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
320 mm ## block ## id ## _ ## reg_name
321
322#define SRII(reg_name, block, id)\
323 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
324 mm ## block ## id ## _ ## reg_name
325
326#define DCCG_SRII(reg_name, block, id)\
327 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
328 mm ## block ## id ## _ ## reg_name
329
330/* NBIO */
331#define NBIO_BASE_INNER(seg) \
332 NBIO_BASE__INST0_SEG ## seg
333
334#define NBIO_BASE(seg) \
335 NBIO_BASE_INNER(seg)
336
337#define NBIO_SR(reg_name)\
338 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
339 mm ## reg_name
340
341/* MMHUB */
342#define MMHUB_BASE_INNER(seg) \
343 MMHUB_BASE__INST0_SEG ## seg
344
345#define MMHUB_BASE(seg) \
346 MMHUB_BASE_INNER(seg)
347
348#define MMHUB_SR(reg_name)\
349 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
350 mmMM ## reg_name
351
352static const struct bios_registers bios_regs = {
353 NBIO_SR(BIOS_SCRATCH_3),
354 NBIO_SR(BIOS_SCRATCH_6)
355};
356
357#define clk_src_regs(index, pllid)\
358[index] = {\
359 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
360}
361
362static const struct dce110_clk_src_regs clk_src_regs[] = {
363 clk_src_regs(0, A),
364 clk_src_regs(1, B),
365 clk_src_regs(2, C),
366 clk_src_regs(3, D),
367 clk_src_regs(4, E),
368 clk_src_regs(5, F)
369};
370
371static const struct dce110_clk_src_shift cs_shift = {
372 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
373};
374
375static const struct dce110_clk_src_mask cs_mask = {
376 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
377};
378
379static const struct dce_dmcu_registers dmcu_regs = {
380 DMCU_DCN10_REG_LIST()
381};
382
383static const struct dce_dmcu_shift dmcu_shift = {
384 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
385};
386
387static const struct dce_dmcu_mask dmcu_mask = {
388 DMCU_MASK_SH_LIST_DCN10(_MASK)
389};
d7c29549 390
7ed4e635 391static const struct dce_abm_registers abm_regs = {
d7c29549 392 ABM_DCN20_REG_LIST()
7ed4e635
HW		 393};
394
395static const struct dce_abm_shift abm_shift = {
d7c29549 396 ABM_MASK_SH_LIST_DCN20(__SHIFT)
7ed4e635
HW		 397};
398
399static const struct dce_abm_mask abm_mask = {
d7c29549 400 ABM_MASK_SH_LIST_DCN20(_MASK)
7ed4e635 401};
d7c29549 402
7ed4e635
HW		 403#define audio_regs(id)\
404[id] = {\
405 AUD_COMMON_REG_LIST(id)\
406}
407
408static const struct dce_audio_registers audio_regs[] = {
409 audio_regs(0),
410 audio_regs(1),
411 audio_regs(2),
412 audio_regs(3),
413 audio_regs(4),
414 audio_regs(5),
415 audio_regs(6),
416};
417
418#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
419 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
420 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
421 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
422
423static const struct dce_audio_shift audio_shift = {
424 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
425};
426
54a9bcb0 427static const struct dce_audio_mask audio_mask = {
7ed4e635
HW		 428 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
429};
430
431#define stream_enc_regs(id)\
432[id] = {\
433 SE_DCN2_REG_LIST(id)\
434}
435
436static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
437 stream_enc_regs(0),
438 stream_enc_regs(1),
439 stream_enc_regs(2),
440 stream_enc_regs(3),
441 stream_enc_regs(4),
442 stream_enc_regs(5),
443};
444
445static const struct dcn10_stream_encoder_shift se_shift = {
446 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
447};
448
449static const struct dcn10_stream_encoder_mask se_mask = {
450 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
451};
452
453
454#define aux_regs(id)\
455[id] = {\
456 DCN2_AUX_REG_LIST(id)\
457}
458
459static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
460 aux_regs(0),
461 aux_regs(1),
462 aux_regs(2),
463 aux_regs(3),
464 aux_regs(4),
465 aux_regs(5)
466};
467
468#define hpd_regs(id)\
469[id] = {\
470 HPD_REG_LIST(id)\
471}
472
473static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
474 hpd_regs(0),
475 hpd_regs(1),
476 hpd_regs(2),
477 hpd_regs(3),
478 hpd_regs(4),
479 hpd_regs(5)
480};
481
482#define link_regs(id, phyid)\
483[id] = {\
484 LE_DCN10_REG_LIST(id), \
485 UNIPHY_DCN2_REG_LIST(phyid), \
486 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
487}
488
489static const struct dcn10_link_enc_registers link_enc_regs[] = {
490 link_regs(0, A),
491 link_regs(1, B),
492 link_regs(2, C),
493 link_regs(3, D),
494 link_regs(4, E),
495 link_regs(5, F)
496};
497
498static const struct dcn10_link_enc_shift le_shift = {
499 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT)
500};
501
502static const struct dcn10_link_enc_mask le_mask = {
503 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK)
504};
505
506#define ipp_regs(id)\
507[id] = {\
508 IPP_REG_LIST_DCN20(id),\
509}
510
511static const struct dcn10_ipp_registers ipp_regs[] = {
512 ipp_regs(0),
513 ipp_regs(1),
514 ipp_regs(2),
515 ipp_regs(3),
516 ipp_regs(4),
517 ipp_regs(5),
518};
519
520static const struct dcn10_ipp_shift ipp_shift = {
521 IPP_MASK_SH_LIST_DCN20(__SHIFT)
522};
523
524static const struct dcn10_ipp_mask ipp_mask = {
525 IPP_MASK_SH_LIST_DCN20(_MASK),
526};
527
528#define opp_regs(id)\
529[id] = {\
530 OPP_REG_LIST_DCN20(id),\
531}
532
533static const struct dcn20_opp_registers opp_regs[] = {
534 opp_regs(0),
535 opp_regs(1),
536 opp_regs(2),
537 opp_regs(3),
538 opp_regs(4),
539 opp_regs(5),
540};
541
542static const struct dcn20_opp_shift opp_shift = {
543 OPP_MASK_SH_LIST_DCN20(__SHIFT)
544};
545
546static const struct dcn20_opp_mask opp_mask = {
547 OPP_MASK_SH_LIST_DCN20(_MASK)
548};
549
550#define aux_engine_regs(id)\
551[id] = {\
552 AUX_COMMON_REG_LIST0(id), \
553 .AUXN_IMPCAL = 0, \
554 .AUXP_IMPCAL = 0, \
555 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
556}
557
558static const struct dce110_aux_registers aux_engine_regs[] = {
559 aux_engine_regs(0),
560 aux_engine_regs(1),
561 aux_engine_regs(2),
562 aux_engine_regs(3),
563 aux_engine_regs(4),
564 aux_engine_regs(5)
565};
566
567#define tf_regs(id)\
568[id] = {\
569 TF_REG_LIST_DCN20(id),\
570}
571
572static const struct dcn2_dpp_registers tf_regs[] = {
573 tf_regs(0),
574 tf_regs(1),
575 tf_regs(2),
576 tf_regs(3),
577 tf_regs(4),
578 tf_regs(5),
579};
580
581static const struct dcn2_dpp_shift tf_shift = {
582 TF_REG_LIST_SH_MASK_DCN20(__SHIFT)
583};
584
585static const struct dcn2_dpp_mask tf_mask = {
586 TF_REG_LIST_SH_MASK_DCN20(_MASK)
587};
588
bb21290f
CL		 589#define dwbc_regs_dcn2(id)\
590[id] = {\
591 DWBC_COMMON_REG_LIST_DCN2_0(id),\
592 }
593
594static const struct dcn20_dwbc_registers dwbc20_regs[] = {
595 dwbc_regs_dcn2(0),
596};
597
598static const struct dcn20_dwbc_shift dwbc20_shift = {
599 DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
600};
601
602static const struct dcn20_dwbc_mask dwbc20_mask = {
603 DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
604};
605
606#define mcif_wb_regs_dcn2(id)\
607[id] = {\
608 MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\
609 }
610
611static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {
612 mcif_wb_regs_dcn2(0),
613};
614
615static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {
616 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
617};
618
619static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {
620 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
621};
622
7ed4e635
HW		 623static const struct dcn20_mpc_registers mpc_regs = {
624 MPC_REG_LIST_DCN2_0(0),
625 MPC_REG_LIST_DCN2_0(1),
626 MPC_REG_LIST_DCN2_0(2),
627 MPC_REG_LIST_DCN2_0(3),
628 MPC_REG_LIST_DCN2_0(4),
629 MPC_REG_LIST_DCN2_0(5),
630 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
631 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
632 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
633 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
634 MPC_OUT_MUX_REG_LIST_DCN2_0(4),
635 MPC_OUT_MUX_REG_LIST_DCN2_0(5),
636};
637
638static const struct dcn20_mpc_shift mpc_shift = {
639 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
640};
641
642static const struct dcn20_mpc_mask mpc_mask = {
643 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
644};
645
646#define tg_regs(id)\
647[id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
648
649
650static const struct dcn_optc_registers tg_regs[] = {
651 tg_regs(0),
652 tg_regs(1),
653 tg_regs(2),
654 tg_regs(3),
655 tg_regs(4),
656 tg_regs(5)
657};
658
659static const struct dcn_optc_shift tg_shift = {
660 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
661};
662
663static const struct dcn_optc_mask tg_mask = {
664 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
665};
666
667#define hubp_regs(id)\
668[id] = {\
669 HUBP_REG_LIST_DCN20(id)\
670}
671
672static const struct dcn_hubp2_registers hubp_regs[] = {
673 hubp_regs(0),
674 hubp_regs(1),
675 hubp_regs(2),
676 hubp_regs(3),
677 hubp_regs(4),
678 hubp_regs(5)
679};
680
681static const struct dcn_hubp2_shift hubp_shift = {
682 HUBP_MASK_SH_LIST_DCN20(__SHIFT)
683};
684
685static const struct dcn_hubp2_mask hubp_mask = {
686 HUBP_MASK_SH_LIST_DCN20(_MASK)
687};
688
689static const struct dcn_hubbub_registers hubbub_reg = {
690 HUBBUB_REG_LIST_DCN20(0)
691};
692
693static const struct dcn_hubbub_shift hubbub_shift = {
694 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT)
695};
696
697static const struct dcn_hubbub_mask hubbub_mask = {
698 HUBBUB_MASK_SH_LIST_DCN20(_MASK)
699};
700
701#define vmid_regs(id)\
702[id] = {\
703 DCN20_VMID_REG_LIST(id)\
704}
705
706static const struct dcn_vmid_registers vmid_regs[] = {
707 vmid_regs(0),
708 vmid_regs(1),
709 vmid_regs(2),
710 vmid_regs(3),
711 vmid_regs(4),
712 vmid_regs(5),
713 vmid_regs(6),
714 vmid_regs(7),
715 vmid_regs(8),
716 vmid_regs(9),
717 vmid_regs(10),
718 vmid_regs(11),
719 vmid_regs(12),
720 vmid_regs(13),
721 vmid_regs(14),
722 vmid_regs(15)
723};
724
725static const struct dcn20_vmid_shift vmid_shifts = {
726 DCN20_VMID_MASK_SH_LIST(__SHIFT)
727};
728
729static const struct dcn20_vmid_mask vmid_masks = {
730 DCN20_VMID_MASK_SH_LIST(_MASK)
731};
732
97bda032
HW		 733#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
734#define dsc_regsDCN20(id)\
735[id] = {\
736 DSC_REG_LIST_DCN20(id)\
737}
738
739static const struct dcn20_dsc_registers dsc_regs[] = {
740 dsc_regsDCN20(0),
741 dsc_regsDCN20(1),
742 dsc_regsDCN20(2),
743 dsc_regsDCN20(3),
744 dsc_regsDCN20(4),
745 dsc_regsDCN20(5)
746};
747
748static const struct dcn20_dsc_shift dsc_shift = {
749 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
750};
751
752static const struct dcn20_dsc_mask dsc_mask = {
753 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
754};
755#endif
7ed4e635
HW		 756
757static const struct dccg_registers dccg_regs = {
758 DCCG_REG_LIST_DCN2()
759};
760
761static const struct dccg_shift dccg_shift = {
762 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
763};
764
765static const struct dccg_mask dccg_mask = {
766 DCCG_MASK_SH_LIST_DCN2(_MASK)
767};
768
769static const struct resource_caps res_cap_nv10 = {
770 .num_timing_generator = 6,
771 .num_opp = 6,
772 .num_video_plane = 6,
773 .num_audio = 7,
774 .num_stream_encoder = 6,
775 .num_pll = 6,
9cbee6ef 776 .num_dwb = 1,
7ed4e635
HW		 777 .num_ddc = 6,
778 .num_vmid = 16,
97bda032
HW		 779#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
780 .num_dsc = 6,
781#endif
7ed4e635
HW		 782};
783
784static const struct dc_plane_cap plane_cap = {
785 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
786 .blends_with_above = true,
787 .blends_with_below = true,
7ed4e635 788 .per_pixel_alpha = true,
5b1b2f20
AD		 789
790 .pixel_format_support = {
791 .argb8888 = true,
792 .nv12 = true,
793 .fp16 = true
794 },
795
796 .max_upscale_factor = {
797 .argb8888 = 16000,
798 .nv12 = 16000,
799 .fp16 = 1
800 },
801
802 .max_downscale_factor = {
803 .argb8888 = 250,
804 .nv12 = 250,
805 .fp16 = 1
806 }
7ed4e635 807};
2ebe1773
BL		 808static const struct resource_caps res_cap_nv14 = {
809 .num_timing_generator = 5,
810 .num_opp = 5,
811 .num_video_plane = 5,
812 .num_audio = 6,
813 .num_stream_encoder = 5,
814 .num_pll = 5,
c5cc14e3 815 .num_dwb = 0,
2ebe1773
BL		 816 .num_ddc = 5,
817};
7ed4e635
HW		 818
819static const struct dc_debug_options debug_defaults_drv = {
820 .disable_dmcu = true,
821 .force_abm_enable = false,
822 .timing_trace = false,
823 .clock_trace = true,
824 .disable_pplib_clock_request = true,
825 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
826 .force_single_disp_pipe_split = true,
827 .disable_dcc = DCC_ENABLE,
828 .vsr_support = true,
829 .performance_trace = false,
830 .max_downscale_src_width = 5120,/*upto 5K*/
831 .disable_pplib_wm_range = false,
832 .scl_reset_length10 = true,
9e14d4f1 833 .sanity_checks = false,
7ed4e635 834 .disable_tri_buf = true,
1a7d296d 835 .underflow_assert_delay_us = 0xFFFFFFFF,
7ed4e635
HW		 836};
837
838static const struct dc_debug_options debug_defaults_diags = {
839 .disable_dmcu = true,
840 .force_abm_enable = false,
841 .timing_trace = true,
842 .clock_trace = true,
843 .disable_dpp_power_gate = true,
844 .disable_hubp_power_gate = true,
845 .disable_clock_gate = true,
846 .disable_pplib_clock_request = true,
847 .disable_pplib_wm_range = true,
848 .disable_stutter = true,
849 .scl_reset_length10 = true,
1a7d296d 850 .underflow_assert_delay_us = 0xFFFFFFFF,
7ed4e635
HW		 851};
852
853void dcn20_dpp_destroy(struct dpp **dpp)
854{
855 kfree(TO_DCN20_DPP(*dpp));
856 *dpp = NULL;
857}
858
859struct dpp *dcn20_dpp_create(
860 struct dc_context *ctx,
861 uint32_t inst)
862{
863 struct dcn20_dpp *dpp =
864 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
865
866 if (!dpp)
867 return NULL;
868
869 if (dpp2_construct(dpp, ctx, inst,
870 &tf_regs[inst], &tf_shift, &tf_mask))
871 return &dpp->base;
872
873 BREAK_TO_DEBUGGER();
874 kfree(dpp);
875 return NULL;
876}
877
878struct input_pixel_processor *dcn20_ipp_create(
879 struct dc_context *ctx, uint32_t inst)
880{
881 struct dcn10_ipp *ipp =
882 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
883
884 if (!ipp) {
885 BREAK_TO_DEBUGGER();
886 return NULL;
887 }
888
889 dcn20_ipp_construct(ipp, ctx, inst,
890 &ipp_regs[inst], &ipp_shift, &ipp_mask);
891 return &ipp->base;
892}
893
894
895struct output_pixel_processor *dcn20_opp_create(
896 struct dc_context *ctx, uint32_t inst)
897{
898 struct dcn20_opp *opp =
899 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
900
901 if (!opp) {
902 BREAK_TO_DEBUGGER();
903 return NULL;
904 }
905
906 dcn20_opp_construct(opp, ctx, inst,
907 &opp_regs[inst], &opp_shift, &opp_mask);
908 return &opp->base;
909}
910
911struct dce_aux *dcn20_aux_engine_create(
912 struct dc_context *ctx,
913 uint32_t inst)
914{
915 struct aux_engine_dce110 *aux_engine =
916 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
917
918 if (!aux_engine)
919 return NULL;
920
921 dce110_aux_engine_construct(aux_engine, ctx, inst,
922 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
923 &aux_engine_regs[inst]);
924
925 return &aux_engine->base;
926}
927#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
928
929static const struct dce_i2c_registers i2c_hw_regs[] = {
930 i2c_inst_regs(1),
931 i2c_inst_regs(2),
932 i2c_inst_regs(3),
933 i2c_inst_regs(4),
934 i2c_inst_regs(5),
935 i2c_inst_regs(6),
936};
937
938static const struct dce_i2c_shift i2c_shifts = {
939 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
940};
941
942static const struct dce_i2c_mask i2c_masks = {
943 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
944};
945
946struct dce_i2c_hw *dcn20_i2c_hw_create(
947 struct dc_context *ctx,
948 uint32_t inst)
949{
950 struct dce_i2c_hw *dce_i2c_hw =
951 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
952
953 if (!dce_i2c_hw)
954 return NULL;
955
956 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
957 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
958
959 return dce_i2c_hw;
960}
961struct mpc *dcn20_mpc_create(struct dc_context *ctx)
962{
963 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
964 GFP_KERNEL);
965
966 if (!mpc20)
967 return NULL;
968
969 dcn20_mpc_construct(mpc20, ctx,
970 &mpc_regs,
971 &mpc_shift,
972 &mpc_mask,
973 6);
974
975 return &mpc20->base;
976}
977
978struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)
979{
980 int i;
981 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
982 GFP_KERNEL);
983
984 if (!hubbub)
985 return NULL;
986
987 hubbub2_construct(hubbub, ctx,
988 &hubbub_reg,
989 &hubbub_shift,
990 &hubbub_mask);
991
992 for (i = 0; i < res_cap_nv10.num_vmid; i++) {
993 struct dcn20_vmid *vmid = &hubbub->vmid[i];
994
995 vmid->ctx = ctx;
996
997 vmid->regs = &vmid_regs[i];
998 vmid->shifts = &vmid_shifts;
999 vmid->masks = &vmid_masks;
1000 }
1001
1002 return &hubbub->base;
1003}
1004
1005struct timing_generator *dcn20_timing_generator_create(
1006 struct dc_context *ctx,
1007 uint32_t instance)
1008{
1009 struct optc *tgn10 =
1010 kzalloc(sizeof(struct optc), GFP_KERNEL);
1011
1012 if (!tgn10)
1013 return NULL;
1014
1015 tgn10->base.inst = instance;
1016 tgn10->base.ctx = ctx;
1017
1018 tgn10->tg_regs = &tg_regs[instance];
1019 tgn10->tg_shift = &tg_shift;
1020 tgn10->tg_mask = &tg_mask;
1021
1022 dcn20_timing_generator_init(tgn10);
1023
1024 return &tgn10->base;
1025}
1026
1027static const struct encoder_feature_support link_enc_feature = {
1028 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1029 .max_hdmi_pixel_clock = 600000,
1030 .hdmi_ycbcr420_supported = true,
1031 .dp_ycbcr420_supported = true,
1032 .flags.bits.IS_HBR2_CAPABLE = true,
1033 .flags.bits.IS_HBR3_CAPABLE = true,
1034 .flags.bits.IS_TPS3_CAPABLE = true,
1035 .flags.bits.IS_TPS4_CAPABLE = true
1036};
1037
1038struct link_encoder *dcn20_link_encoder_create(
1039 const struct encoder_init_data *enc_init_data)
1040{
1041 struct dcn20_link_encoder *enc20 =
1042 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1043
1044 if (!enc20)
1045 return NULL;
1046
1047 dcn20_link_encoder_construct(enc20,
1048 enc_init_data,
1049 &link_enc_feature,
1050 &link_enc_regs[enc_init_data->transmitter],
1051 &link_enc_aux_regs[enc_init_data->channel - 1],
1052 &link_enc_hpd_regs[enc_init_data->hpd_source],
1053 &le_shift,
1054 &le_mask);
1055
1056 return &enc20->enc10.base;
1057}
1058
1059struct clock_source *dcn20_clock_source_create(
1060 struct dc_context *ctx,
1061 struct dc_bios *bios,
1062 enum clock_source_id id,
1063 const struct dce110_clk_src_regs *regs,
1064 bool dp_clk_src)
1065{
1066 struct dce110_clk_src *clk_src =
1067 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1068
1069 if (!clk_src)
1070 return NULL;
1071
1072 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1073 regs, &cs_shift, &cs_mask)) {
1074 clk_src->base.dp_clk_src = dp_clk_src;
1075 return &clk_src->base;
1076 }
1077
1078 BREAK_TO_DEBUGGER();
1079 return NULL;
1080}
1081
1082static void read_dce_straps(
1083 struct dc_context *ctx,
1084 struct resource_straps *straps)
1085{
1086 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1087 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1088}
1089
1090static struct audio *dcn20_create_audio(
1091 struct dc_context *ctx, unsigned int inst)
1092{
1093 return dce_audio_create(ctx, inst,
1094 &audio_regs[inst], &audio_shift, &audio_mask);
1095}
1096
1097struct stream_encoder *dcn20_stream_encoder_create(
1098 enum engine_id eng_id,
1099 struct dc_context *ctx)
1100{
1101 struct dcn10_stream_encoder *enc1 =
1102 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1103
1104 if (!enc1)
1105 return NULL;
1106
1107 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1108 &stream_enc_regs[eng_id],
1109 &se_shift, &se_mask);
1110
1111 return &enc1->base;
1112}
1113
1114static const struct dce_hwseq_registers hwseq_reg = {
1115 HWSEQ_DCN2_REG_LIST()
1116};
1117
1118static const struct dce_hwseq_shift hwseq_shift = {
1119 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT)
1120};
1121
1122static const struct dce_hwseq_mask hwseq_mask = {
1123 HWSEQ_DCN2_MASK_SH_LIST(_MASK)
1124};
1125
1126struct dce_hwseq *dcn20_hwseq_create(
1127 struct dc_context *ctx)
1128{
1129 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1130
1131 if (hws) {
1132 hws->ctx = ctx;
1133 hws->regs = &hwseq_reg;
1134 hws->shifts = &hwseq_shift;
1135 hws->masks = &hwseq_mask;
1136 }
1137 return hws;
1138}
1139
1140static const struct resource_create_funcs res_create_funcs = {
1141 .read_dce_straps = read_dce_straps,
1142 .create_audio = dcn20_create_audio,
1143 .create_stream_encoder = dcn20_stream_encoder_create,
1144 .create_hwseq = dcn20_hwseq_create,
1145};
1146
1147static const struct resource_create_funcs res_create_maximus_funcs = {
1148 .read_dce_straps = NULL,
1149 .create_audio = NULL,
1150 .create_stream_encoder = NULL,
1151 .create_hwseq = dcn20_hwseq_create,
1152};
1153
1154void dcn20_clock_source_destroy(struct clock_source **clk_src)
1155{
1156 kfree(TO_DCE110_CLK_SRC(*clk_src));
1157 *clk_src = NULL;
1158}
1159
97bda032
HW		 1160#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1161
1162struct display_stream_compressor *dcn20_dsc_create(
1163 struct dc_context *ctx, uint32_t inst)
1164{
1165 struct dcn20_dsc *dsc =
1166 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1167
1168 if (!dsc) {
1169 BREAK_TO_DEBUGGER();
1170 return NULL;
1171 }
1172
1173 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1174 return &dsc->base;
1175}
1176
1177void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
1178{
1179 kfree(container_of(*dsc, struct dcn20_dsc, base));
1180 *dsc = NULL;
1181}
1182
1183#endif
7ed4e635
HW		 1184
1185static void destruct(struct dcn20_resource_pool *pool)
1186{
1187 unsigned int i;
1188
1189 for (i = 0; i < pool->base.stream_enc_count; i++) {
1190 if (pool->base.stream_enc[i] != NULL) {
1191 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1192 pool->base.stream_enc[i] = NULL;
1193 }
1194 }
1195
97bda032
HW		 1196#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1197 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1198 if (pool->base.dscs[i] != NULL)
1199 dcn20_dsc_destroy(&pool->base.dscs[i]);
1200 }
1201#endif
7ed4e635
HW		 1202
1203 if (pool->base.mpc != NULL) {
1204 kfree(TO_DCN20_MPC(pool->base.mpc));
1205 pool->base.mpc = NULL;
1206 }
1207 if (pool->base.hubbub != NULL) {
1208 kfree(pool->base.hubbub);
1209 pool->base.hubbub = NULL;
1210 }
1211 for (i = 0; i < pool->base.pipe_count; i++) {
1212 if (pool->base.dpps[i] != NULL)
1213 dcn20_dpp_destroy(&pool->base.dpps[i]);
1214
1215 if (pool->base.ipps[i] != NULL)
1216 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1217
1218 if (pool->base.hubps[i] != NULL) {
1219 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1220 pool->base.hubps[i] = NULL;
1221 }
1222
1223 if (pool->base.irqs != NULL) {
1224 dal_irq_service_destroy(&pool->base.irqs);
1225 }
1226 }
1227
1228 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1229 if (pool->base.engines[i] != NULL)
1230 dce110_engine_destroy(&pool->base.engines[i]);
1231 if (pool->base.hw_i2cs[i] != NULL) {
1232 kfree(pool->base.hw_i2cs[i]);
1233 pool->base.hw_i2cs[i] = NULL;
1234 }
1235 if (pool->base.sw_i2cs[i] != NULL) {
1236 kfree(pool->base.sw_i2cs[i]);
1237 pool->base.sw_i2cs[i] = NULL;
1238 }
1239 }
1240
1241 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1242 if (pool->base.opps[i] != NULL)
1243 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1244 }
1245
1246 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1247 if (pool->base.timing_generators[i] != NULL) {
1248 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1249 pool->base.timing_generators[i] = NULL;
1250 }
1251 }
1252
bb21290f
CL		 1253 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1254 if (pool->base.dwbc[i] != NULL) {
1255 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
1256 pool->base.dwbc[i] = NULL;
1257 }
1258 if (pool->base.mcif_wb[i] != NULL) {
1259 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
1260 pool->base.mcif_wb[i] = NULL;
1261 }
1262 }
1263
7ed4e635
HW		 1264 for (i = 0; i < pool->base.audio_count; i++) {
1265 if (pool->base.audios[i])
1266 dce_aud_destroy(&pool->base.audios[i]);
1267 }
1268
1269 for (i = 0; i < pool->base.clk_src_count; i++) {
1270 if (pool->base.clock_sources[i] != NULL) {
1271 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1272 pool->base.clock_sources[i] = NULL;
1273 }
1274 }
1275
1276 if (pool->base.dp_clock_source != NULL) {
1277 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1278 pool->base.dp_clock_source = NULL;
1279 }
1280
1281
1282 if (pool->base.abm != NULL)
1283 dce_abm_destroy(&pool->base.abm);
1284
1285 if (pool->base.dmcu != NULL)
1286 dce_dmcu_destroy(&pool->base.dmcu);
1287
1288 if (pool->base.dccg != NULL)
1289 dcn_dccg_destroy(&pool->base.dccg);
1290
1291 if (pool->base.pp_smu != NULL)
1292 dcn20_pp_smu_destroy(&pool->base.pp_smu);
1293
1294}
1295
1296struct hubp *dcn20_hubp_create(
1297 struct dc_context *ctx,
1298 uint32_t inst)
1299{
1300 struct dcn20_hubp *hubp2 =
1301 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1302
1303 if (!hubp2)
1304 return NULL;
1305
1306 if (hubp2_construct(hubp2, ctx, inst,
1307 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1308 return &hubp2->base;
1309
1310 BREAK_TO_DEBUGGER();
1311 kfree(hubp2);
1312 return NULL;
1313}
1314
1315static void get_pixel_clock_parameters(
1316 struct pipe_ctx *pipe_ctx,
1317 struct pixel_clk_params *pixel_clk_params)
1318{
1319 const struct dc_stream_state *stream = pipe_ctx->stream;
1320 bool odm_combine = dc_res_get_odm_bottom_pipe(pipe_ctx) != NULL;
1321
1322 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1323 pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1324 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1325 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1326 /* TODO: un-hardcode*/
1327 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1328 LINK_RATE_REF_FREQ_IN_KHZ;
1329 pixel_clk_params->flags.ENABLE_SS = 0;
1330 pixel_clk_params->color_depth =
1331 stream->timing.display_color_depth;
1332 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1333 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1334
1335 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1336 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1337
1338 if (optc1_is_two_pixels_per_containter(&stream->timing) || odm_combine)
1339 pixel_clk_params->requested_pix_clk_100hz /= 2;
1340
1341 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1342 pixel_clk_params->requested_pix_clk_100hz *= 2;
1343
1344}
1345
1346static void build_clamping_params(struct dc_stream_state *stream)
1347{
1348 stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1349 stream->clamping.c_depth = stream->timing.display_color_depth;
1350 stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1351}
1352
1353static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1354{
1355
1356 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1357
1358 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1359 pipe_ctx->clock_source,
1360 &pipe_ctx->stream_res.pix_clk_params,
1361 &pipe_ctx->pll_settings);
1362
1363 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1364
1365 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1366 &pipe_ctx->stream->bit_depth_params);
1367 build_clamping_params(pipe_ctx->stream);
1368
1369 return DC_OK;
1370}
1371
1372enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
1373{
1374 enum dc_status status = DC_OK;
1375 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1376
1377 /*TODO Seems unneeded anymore */
1378 /* if (old_context && resource_is_stream_unchanged(old_context, stream)) {
1379 if (stream != NULL && old_context->streams[i] != NULL) {
1380 todo: shouldn't have to copy missing parameter here
1381 resource_build_bit_depth_reduction_params(stream,
1382 &stream->bit_depth_params);
1383 stream->clamping.pixel_encoding =
1384 stream->timing.pixel_encoding;
1385
1386 resource_build_bit_depth_reduction_params(stream,
1387 &stream->bit_depth_params);
1388 build_clamping_params(stream);
1389
1390 continue;
1391 }
1392 }
1393 */
1394
1395 if (!pipe_ctx)
1396 return DC_ERROR_UNEXPECTED;
1397
1398
1399 status = build_pipe_hw_param(pipe_ctx);
1400
1401 return status;
1402}
1403
97bda032
HW		 1404#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1405
c9ae6e16
NC		 1406static void acquire_dsc(struct resource_context *res_ctx,
1407 const struct resource_pool *pool,
1408 struct display_stream_compressor **dsc)
97bda032
HW		 1409{
1410 int i;
c9ae6e16
NC		 1411
1412 ASSERT(*dsc == NULL);
1413 *dsc = NULL;
97bda032
HW		 1414
1415 /* Find first free DSC */
1416 for (i = 0; i < pool->res_cap->num_dsc; i++)
1417 if (!res_ctx->is_dsc_acquired[i]) {
c9ae6e16 1418 *dsc = pool->dscs[i];
97bda032
HW		 1419 res_ctx->is_dsc_acquired[i] = true;
1420 break;
1421 }
97bda032
HW		 1422}
1423
1424static void release_dsc(struct resource_context *res_ctx,
1425 const struct resource_pool *pool,
c9ae6e16 1426 struct display_stream_compressor **dsc)
97bda032
HW		 1427{
1428 int i;
1429
1430 for (i = 0; i < pool->res_cap->num_dsc; i++)
c9ae6e16 1431 if (pool->dscs[i] == *dsc) {
97bda032 1432 res_ctx->is_dsc_acquired[i] = false;
c9ae6e16 1433 *dsc = NULL;
97bda032
HW		 1434 break;
1435 }
1436}
1437
1438#endif
7ed4e635 1439
7ed4e635 1440
97bda032 1441#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
ba32c50f 1442static enum dc_status add_dsc_to_stream_resource(struct dc *dc,
c9ae6e16
NC		 1443 struct dc_state *dc_ctx,
1444 struct dc_stream_state *dc_stream)
1445{
1446 enum dc_status result = DC_OK;
1447 int i;
1448 const struct resource_pool *pool = dc->res_pool;
97bda032 1449
c9ae6e16
NC		 1450 /* Get a DSC if required and available */
1451 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1452 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];
97bda032 1453
c9ae6e16
NC		 1454 if (pipe_ctx->stream != dc_stream)
1455 continue;
97bda032 1456
c9ae6e16 1457 acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc);
97bda032 1458
c9ae6e16
NC		 1459 /* The number of DSCs can be less than the number of pipes */
1460 if (!pipe_ctx->stream_res.dsc) {
1461 dm_output_to_console("No DSCs available\n");
1462 result = DC_NO_DSC_RESOURCE;
97bda032 1463 }
7ed4e635 1464
c9ae6e16
NC		 1465 break;
1466 }
7ed4e635
HW		 1467
1468 return result;
1469}
1470
1471
ba32c50f 1472static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
c9ae6e16
NC		 1473 struct dc_state *new_ctx,
1474 struct dc_stream_state *dc_stream)
7ed4e635
HW		 1475{
1476 struct pipe_ctx *pipe_ctx = NULL;
1477 int i;
1478
7ed4e635
HW		 1479 for (i = 0; i < MAX_PIPES; i++) {
1480 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1481 pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1482 break;
1483 }
1484 }
1485
1486 if (!pipe_ctx)
1487 return DC_ERROR_UNEXPECTED;
1488
97bda032
HW		 1489 if (pipe_ctx->stream_res.dsc) {
1490 struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
1491
c9ae6e16
NC		 1492 release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
1493 if (odm_pipe)
1494 release_dsc(&new_ctx->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
97bda032 1495 }
7ed4e635
HW		 1496
1497 return DC_OK;
1498}
c9ae6e16
NC		 1499#endif
1500
1501
1502enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1503{
1504 enum dc_status result = DC_ERROR_UNEXPECTED;
1505
1506 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1507
1508 if (result == DC_OK)
1509 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1510
1511#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1512 /* Get a DSC if required and available */
1513 if (result == DC_OK && dc_stream->timing.flags.DSC)
ba32c50f 1514 result = add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
c9ae6e16
NC		 1515#endif
1516
1517 if (result == DC_OK)
1518 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
1519
1520 return result;
1521}
1522
1523
1524enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1525{
1526 enum dc_status result = DC_OK;
1527
1528#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
ba32c50f 1529 result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
c9ae6e16
NC		 1530#endif
1531
1532 return result;
1533}
7ed4e635
HW		 1534
1535
1536static void swizzle_to_dml_params(
1537 enum swizzle_mode_values swizzle,
1538 unsigned int *sw_mode)
1539{
1540 switch (swizzle) {
1541 case DC_SW_LINEAR:
1542 *sw_mode = dm_sw_linear;
1543 break;
1544 case DC_SW_4KB_S:
1545 *sw_mode = dm_sw_4kb_s;
1546 break;
1547 case DC_SW_4KB_S_X:
1548 *sw_mode = dm_sw_4kb_s_x;
1549 break;
1550 case DC_SW_4KB_D:
1551 *sw_mode = dm_sw_4kb_d;
1552 break;
1553 case DC_SW_4KB_D_X:
1554 *sw_mode = dm_sw_4kb_d_x;
1555 break;
1556 case DC_SW_64KB_S:
1557 *sw_mode = dm_sw_64kb_s;
1558 break;
1559 case DC_SW_64KB_S_X:
1560 *sw_mode = dm_sw_64kb_s_x;
1561 break;
1562 case DC_SW_64KB_S_T:
1563 *sw_mode = dm_sw_64kb_s_t;
1564 break;
1565 case DC_SW_64KB_D:
1566 *sw_mode = dm_sw_64kb_d;
1567 break;
1568 case DC_SW_64KB_D_X:
1569 *sw_mode = dm_sw_64kb_d_x;
1570 break;
1571 case DC_SW_64KB_D_T:
1572 *sw_mode = dm_sw_64kb_d_t;
1573 break;
1574 case DC_SW_64KB_R_X:
1575 *sw_mode = dm_sw_64kb_r_x;
1576 break;
1577 case DC_SW_VAR_S:
1578 *sw_mode = dm_sw_var_s;
1579 break;
1580 case DC_SW_VAR_S_X:
1581 *sw_mode = dm_sw_var_s_x;
1582 break;
1583 case DC_SW_VAR_D:
1584 *sw_mode = dm_sw_var_d;
1585 break;
1586 case DC_SW_VAR_D_X:
1587 *sw_mode = dm_sw_var_d_x;
1588 break;
1589
1590 default:
1591 ASSERT(0); /* Not supported */
1592 break;
1593 }
1594}
1595
1596static bool dcn20_split_stream_for_combine(
1597 struct resource_context *res_ctx,
1598 const struct resource_pool *pool,
1599 struct pipe_ctx *primary_pipe,
1600 struct pipe_ctx *secondary_pipe,
1601 bool is_odm_combine)
1602{
1603 int pipe_idx = secondary_pipe->pipe_idx;
1604 struct scaler_data *sd = &primary_pipe->plane_res.scl_data;
1605 struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
1606 int new_width;
1607
1608 *secondary_pipe = *primary_pipe;
1609 secondary_pipe->bottom_pipe = sec_bot_pipe;
1610
1611 secondary_pipe->pipe_idx = pipe_idx;
1612 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
1613 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
1614 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
1615 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
1616 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
1617 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
c92b4c46
NC		 1618#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1619 secondary_pipe->stream_res.dsc = NULL;
1620#endif
7ed4e635
HW		 1621 if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
1622 ASSERT(!secondary_pipe->bottom_pipe);
1623 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
1624 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
1625 }
1626 primary_pipe->bottom_pipe = secondary_pipe;
1627 secondary_pipe->top_pipe = primary_pipe;
1628
1629 if (is_odm_combine) {
7ed4e635
HW		 1630 if (primary_pipe->plane_state) {
1631 /* HACTIVE halved for odm combine */
1632 sd->h_active /= 2;
1633 /* Copy scl_data to secondary pipe */
1634 secondary_pipe->plane_res.scl_data = *sd;
1635
1636 /* Calculate new vp and recout for left pipe */
1637 /* Need at least 16 pixels width per side */
1638 if (sd->recout.x + 16 >= sd->h_active)
1639 return false;
1640 new_width = sd->h_active - sd->recout.x;
1641 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1642 sd->ratios.horz, sd->recout.width - new_width));
1643 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1644 sd->ratios.horz_c, sd->recout.width - new_width));
1645 sd->recout.width = new_width;
1646
1647 /* Calculate new vp and recout for right pipe */
1648 sd = &secondary_pipe->plane_res.scl_data;
1649 new_width = sd->recout.width + sd->recout.x - sd->h_active;
1650 /* Need at least 16 pixels width per side */
1651 if (new_width <= 16)
1652 return false;
1653 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1654 sd->ratios.horz, sd->recout.width - new_width));
1655 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1656 sd->ratios.horz_c, sd->recout.width - new_width));
1657 sd->recout.width = new_width;
1658 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
1659 sd->ratios.horz, sd->h_active - sd->recout.x));
1660 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
1661 sd->ratios.horz_c, sd->h_active - sd->recout.x));
1662 sd->recout.x = 0;
1663 }
1664 secondary_pipe->stream_res.opp = pool->opps[secondary_pipe->pipe_idx];
97bda032 1665#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
c9ae6e16
NC		 1666 if (secondary_pipe->stream->timing.flags.DSC == 1) {
1667 acquire_dsc(res_ctx, pool, &secondary_pipe->stream_res.dsc);
97bda032
HW		 1668 ASSERT(secondary_pipe->stream_res.dsc);
1669 if (secondary_pipe->stream_res.dsc == NULL)
1670 return false;
1671 }
1672#endif
7ed4e635
HW		 1673 } else {
1674 ASSERT(primary_pipe->plane_state);
1675 resource_build_scaling_params(primary_pipe);
1676 resource_build_scaling_params(secondary_pipe);
1677 }
1678
1679 return true;
1680}
1681
1682void dcn20_populate_dml_writeback_from_context(
1683 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1684{
1685 int pipe_cnt, i;
1686
1687 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1688 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];
1689
1690 if (!res_ctx->pipe_ctx[i].stream)
1691 continue;
1692
1693 /* Set writeback information */
1694 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
1695 pipes[pipe_cnt].dout.num_active_wb++;
1696 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
1697 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
1698 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
1699 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
1700 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
1701 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1;
1702 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
1703 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
1704 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0;
1705 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0;
1706 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
1707 if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
1708 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
1709 else
1710 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
1711 } else
1712 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
1713
1714 pipe_cnt++;
1715 }
1716
1717}
1718
1719int dcn20_populate_dml_pipes_from_context(
1720 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1721{
1722 int pipe_cnt, i;
1723 bool synchronized_vblank = true;
1724
1725 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
1726 if (!res_ctx->pipe_ctx[i].stream)
1727 continue;
1728
1729 if (pipe_cnt < 0) {
1730 pipe_cnt = i;
1731 continue;
1732 }
1733 if (!resource_are_streams_timing_synchronizable(
1734 res_ctx->pipe_ctx[pipe_cnt].stream,
1735 res_ctx->pipe_ctx[i].stream)) {
1736 synchronized_vblank = false;
1737 break;
1738 }
1739 }
1740
1741 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1742 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
03fd87db 1743 int output_bpc;
7ed4e635
HW		 1744
1745 if (!res_ctx->pipe_ctx[i].stream)
1746 continue;
1747 /* todo:
1748 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
1749 pipes[pipe_cnt].pipe.src.dcc = 0;
1750 pipes[pipe_cnt].pipe.src.vm = 0;*/
1751
97bda032
HW		 1752#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1753 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
1754 /* todo: rotation?*/
1755 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
1756#endif
7ed4e635
HW		 1757 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
1758 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
1759 /* 1/2 vblank */
1760 pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
1761 (timing->v_total - timing->v_addressable
1762 - timing->v_border_top - timing->v_border_bottom) / 2;
1763 /* 36 bytes dp, 32 hdmi */
1764 pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
1765 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
1766 }
1767 pipes[pipe_cnt].pipe.src.dcc = false;
1768 pipes[pipe_cnt].pipe.src.dcc_rate = 1;
1769 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
1770 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
1771 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
1772 - timing->h_addressable
1773 - timing->h_border_left
1774 - timing->h_border_right;
1775 pipes[pipe_cnt].pipe.dest.vblank_start = timing->v_total - timing->v_front_porch;
1776 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
1777 - timing->v_addressable
1778 - timing->v_border_top
1779 - timing->v_border_bottom;
1780 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
1781 pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total;
1782 pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable;
1783 pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable;
1784 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
1785 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
1786 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1787 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
1788 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
1621f4c4 1789 pipes[pipe_cnt].dout.dp_lanes = 4;
8bb3d7e7
CL		 1790 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
1791 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
7ed4e635 1792
7ed4e635
HW		 1793 switch (res_ctx->pipe_ctx[i].stream->signal) {
1794 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1795 case SIGNAL_TYPE_DISPLAY_PORT:
1796 pipes[pipe_cnt].dout.output_type = dm_dp;
1797 break;
1798 case SIGNAL_TYPE_EDP:
1799 pipes[pipe_cnt].dout.output_type = dm_edp;
1800 break;
1801 case SIGNAL_TYPE_HDMI_TYPE_A:
1802 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1803 case SIGNAL_TYPE_DVI_DUAL_LINK:
1804 pipes[pipe_cnt].dout.output_type = dm_hdmi;
1805 break;
1806 default:
1807 /* In case there is no signal, set dp with 4 lanes to allow max config */
1808 pipes[pipe_cnt].dout.output_type = dm_dp;
1809 pipes[pipe_cnt].dout.dp_lanes = 4;
1810 }
03fd87db
IB		 1811
1812 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
1813 case COLOR_DEPTH_666:
1814 output_bpc = 6;
1815 break;
1816 case COLOR_DEPTH_888:
1817 output_bpc = 8;
1818 break;
1819 case COLOR_DEPTH_101010:
1820 output_bpc = 10;
1821 break;
1822 case COLOR_DEPTH_121212:
1823 output_bpc = 12;
1824 break;
1825 case COLOR_DEPTH_141414:
1826 output_bpc = 14;
1827 break;
1828 case COLOR_DEPTH_161616:
1829 output_bpc = 16;
1830 break;
1831#ifdef CONFIG_DRM_AMD_DC_DCN2_0
1832 case COLOR_DEPTH_999:
1833 output_bpc = 9;
1834 break;
1835 case COLOR_DEPTH_111111:
1836 output_bpc = 11;
1837 break;
1838#endif
1839 default:
1840 output_bpc = 8;
1841 break;
1842 }
1843
1844
7ed4e635
HW		 1845 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
1846 case PIXEL_ENCODING_RGB:
1847 case PIXEL_ENCODING_YCBCR444:
1848 pipes[pipe_cnt].dout.output_format = dm_444;
03fd87db 1849 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
7ed4e635
HW		 1850 break;
1851 case PIXEL_ENCODING_YCBCR420:
1852 pipes[pipe_cnt].dout.output_format = dm_420;
03fd87db 1853 pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3) / 2;
7ed4e635
HW		 1854 break;
1855 case PIXEL_ENCODING_YCBCR422:
1856 if (true) /* todo */
1857 pipes[pipe_cnt].dout.output_format = dm_s422;
1858 else
1859 pipes[pipe_cnt].dout.output_format = dm_n422;
03fd87db 1860 pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
7ed4e635
HW		 1861 break;
1862 default:
1863 pipes[pipe_cnt].dout.output_format = dm_444;
03fd87db 1864 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
7ed4e635
HW		 1865 }
1866 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1867 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
1868 == res_ctx->pipe_ctx[i].plane_state)
1869 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
1870
1871 /* todo: default max for now, until there is logic reflecting this in dc*/
1872 pipes[pipe_cnt].dout.output_bpc = 12;
1873 /*
1874 * Use max cursor settings for calculations to minimize
1875 * bw calculations due to cursor on/off
1876 */
1877 pipes[pipe_cnt].pipe.src.num_cursors = 2;
ed07237c
IB		 1878 pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
1879 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
1880 pipes[pipe_cnt].pipe.src.cur1_src_width = 256;
1881 pipes[pipe_cnt].pipe.src.cur1_bpp = dm_cur_32bit;
7ed4e635
HW		 1882
1883 if (!res_ctx->pipe_ctx[i].plane_state) {
1884 pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
1885 pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear;
1886 pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
1887 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
1888 if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
1889 pipes[pipe_cnt].pipe.src.viewport_width = 1920;
1890 pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
1891 if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
1892 pipes[pipe_cnt].pipe.src.viewport_height = 1080;
1893 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */
1894 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
1895 pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
1896 pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/
1897 pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_hsplit != 1*/
1898 pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/
1899 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
1900 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
1901 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
1902 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
1903 pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
1904 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
1905 pipes[pipe_cnt].pipe.src.is_hsplit = 0;
1906 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
8bb3d7e7
CL		 1907 pipes[pipe_cnt].pipe.dest.vtotal_min = timing->v_total;
1908 pipes[pipe_cnt].pipe.dest.vtotal_max = timing->v_total;
7ed4e635
HW		 1909 } else {
1910 struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
1911 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
1912
7ed4e635
HW		 1913 pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
1914 pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe
1915 && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
1916 || (res_ctx->pipe_ctx[i].top_pipe
1917 && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln);
1918 pipes[pipe_cnt].pipe.dest.odm_combine = (res_ctx->pipe_ctx[i].bottom_pipe
1919 && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln
1920 && res_ctx->pipe_ctx[i].bottom_pipe->stream_res.opp
1921 != res_ctx->pipe_ctx[i].stream_res.opp)
1922 || (res_ctx->pipe_ctx[i].top_pipe
1923 && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln
1924 && res_ctx->pipe_ctx[i].top_pipe->stream_res.opp
1925 != res_ctx->pipe_ctx[i].stream_res.opp);
1926 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
1927 || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
1928 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
1929 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
1930 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
1931 pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
1932 pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
1933 pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
1934 if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
12e2b2d4
DL		 1935 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
1936 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
1937 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
1938 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
7ed4e635 1939 } else {
12e2b2d4
DL		 1940 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
1941 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
7ed4e635
HW		 1942 }
1943 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
1944 pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
1945 pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
1946 pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
1947 pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
1948 if (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) {
1949 pipes[pipe_cnt].pipe.dest.full_recout_width +=
1950 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.width;
1951 pipes[pipe_cnt].pipe.dest.full_recout_height +=
1952 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.height;
1953 } else if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) {
1954 pipes[pipe_cnt].pipe.dest.full_recout_width +=
1955 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.width;
1956 pipes[pipe_cnt].pipe.dest.full_recout_height +=
1957 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.height;
1958 }
1959
ed07237c 1960 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
7ed4e635
HW		 1961 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
1962 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
1963 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
1964 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
1965 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
1966 scl->ratios.vert.value != dc_fixpt_one.value
1967 || scl->ratios.horz.value != dc_fixpt_one.value
1968 || scl->ratios.vert_c.value != dc_fixpt_one.value
1969 || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/
1970 || dc->debug.always_scale; /*support always scale*/
1971 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
1972 pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
1973 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
1974 pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
1975
b964e790
DL		 1976 pipes[pipe_cnt].pipe.src.macro_tile_size =
1977 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
7ed4e635
HW		 1978 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
1979 &pipes[pipe_cnt].pipe.src.sw_mode);
1980
1981 switch (pln->format) {
1982 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
1983 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
1984 pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
1985 break;
1986 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
1987 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
1988 pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
1989 break;
1990 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1991 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1992 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1993 pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
1994 break;
1995 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
1996 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
1997 pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
1998 break;
1999 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2000 pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
2001 break;
2002 default:
2003 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2004 break;
2005 }
2006 }
2007
2008 pipe_cnt++;
2009 }
2010
2011 /* populate writeback information */
2012 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
2013
2014 return pipe_cnt;
2015}
2016
2017unsigned int dcn20_calc_max_scaled_time(
2018 unsigned int time_per_pixel,
2019 enum mmhubbub_wbif_mode mode,
2020 unsigned int urgent_watermark)
2021{
2022 unsigned int time_per_byte = 0;
2023 unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */
2024 unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */
2025 unsigned int small_free_entry, max_free_entry;
2026 unsigned int buf_lh_capability;
2027 unsigned int max_scaled_time;
2028
2029 if (mode == PACKED_444) /* packed mode */
2030 time_per_byte = time_per_pixel/4;
2031 else if (mode == PLANAR_420_8BPC)
2032 time_per_byte = time_per_pixel;
2033 else if (mode == PLANAR_420_10BPC) /* p010 */
2034 time_per_byte = time_per_pixel * 819/1024;
2035
2036 if (time_per_byte == 0)
2037 time_per_byte = 1;
2038
2039 small_free_entry = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry;
2040 max_free_entry = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;
2041 buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */
2042 max_scaled_time = buf_lh_capability - urgent_watermark;
2043 return max_scaled_time;
2044}
2045
2046void dcn20_set_mcif_arb_params(
2047 struct dc *dc,
2048 struct dc_state *context,
2049 display_e2e_pipe_params_st *pipes,
2050 int pipe_cnt)
2051{
2052 enum mmhubbub_wbif_mode wbif_mode;
2053 struct mcif_arb_params *wb_arb_params;
2054 int i, j, k, dwb_pipe;
2055
2056 /* Writeback MCIF_WB arbitration parameters */
2057 dwb_pipe = 0;
2058 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2059
2060 if (!context->res_ctx.pipe_ctx[i].stream)
2061 continue;
2062
2063 for (j = 0; j < MAX_DWB_PIPES; j++) {
2064 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)
2065 continue;
2066
2067 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
2068 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
2069
2070 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {
2071 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
2072 wbif_mode = PLANAR_420_8BPC;
2073 else
2074 wbif_mode = PLANAR_420_10BPC;
2075 } else
2076 wbif_mode = PACKED_444;
2077
2078 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
2079 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2080 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2081 }
2082 wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* 4 bit fraction, ms */
2083 wb_arb_params->slice_lines = 32;
2084 wb_arb_params->arbitration_slice = 2;
2085 wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
2086 wbif_mode,
2087 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
2088
2089 dwb_pipe++;
2090
2091 if (dwb_pipe >= MAX_DWB_PIPES)
2092 return;
2093 }
2094 if (dwb_pipe >= MAX_DWB_PIPES)
2095 return;
2096 }
2097}
2098
0ba37b20
DL		 2099#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2100static bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
2101{
2102 int i;
2103
2104 /* Validate DSC config, dsc count validation is already done */
2105 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2106 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
2107 struct dc_stream_state *stream = pipe_ctx->stream;
2108 struct dsc_config dsc_cfg;
2109
2110 /* Only need to validate top pipe */
2111 if (pipe_ctx->top_pipe || !stream || !stream->timing.flags.DSC)
2112 continue;
2113
2114 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left
2115 + stream->timing.h_border_right;
2116 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
2117 + stream->timing.v_border_bottom;
2118 if (dc_res_get_odm_bottom_pipe(pipe_ctx))
2119 dsc_cfg.pic_width /= 2;
2120 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
2121 dsc_cfg.color_depth = stream->timing.display_color_depth;
2122 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
2123
2124 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
2125 return false;
2126 }
2127 return true;
2128}
2129#endif
2130
6de20237
EY		 2131bool dcn20_fast_validate_bw(
2132 struct dc *dc,
2133 struct dc_state *context,
2134 display_e2e_pipe_params_st *pipes,
5e335add 2135 int *pipe_cnt_out,
6de20237
EY		 2136 int *pipe_split_from,
2137 int *vlevel_out)
7ed4e635 2138{
254eb07c
JA		 2139 bool out = false;
2140
7ed4e635 2141 int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit;
7ed4e635
HW		 2142 bool odm_capable = context->bw_ctx.dml.ip.odm_capable;
2143 bool force_split = false;
0ba37b20
DL		 2144#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2145 bool failed_non_odm_dsc = false;
2146#endif
7ed4e635
HW		 2147 int split_threshold = dc->res_pool->pipe_count / 2;
2148 bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
7ed4e635 2149
42351c66 2150
7ed4e635
HW		 2151 ASSERT(pipes);
2152 if (!pipes)
2153 return false;
2154
2155 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2156 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2157 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2158
2159 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
2160 continue;
2161
2162 /* merge previously split pipe since mode support needs to make the decision */
2163 pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
2164 if (hsplit_pipe->bottom_pipe)
2165 hsplit_pipe->bottom_pipe->top_pipe = pipe;
2166 hsplit_pipe->plane_state = NULL;
2167 hsplit_pipe->stream = NULL;
2168 hsplit_pipe->top_pipe = NULL;
2169 hsplit_pipe->bottom_pipe = NULL;
97bda032
HW		 2170#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2171 if (hsplit_pipe->stream_res.dsc && hsplit_pipe->stream_res.dsc != pipe->stream_res.dsc)
c9ae6e16 2172 release_dsc(&context->res_ctx, dc->res_pool, &hsplit_pipe->stream_res.dsc);
97bda032 2173#endif
7ed4e635
HW		 2174 /* Clear plane_res and stream_res */
2175 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
2176 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
2177 if (pipe->plane_state)
2178 resource_build_scaling_params(pipe);
2179 }
2180
ed07237c
IB		 2181 if (dc->res_pool->funcs->populate_dml_pipes)
2182 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2183 &context->res_ctx, pipes);
2184 else
2185 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
2186 &context->res_ctx, pipes);
254eb07c 2187
5e335add
EY		 2188 *pipe_cnt_out = pipe_cnt;
2189
254eb07c
JA		 2190 if (!pipe_cnt) {
2191 out = true;
2192 goto validate_out;
2193 }
7ed4e635
HW		 2194
2195 context->bw_ctx.dml.ip.odm_capable = 0;
254eb07c 2196
7ed4e635 2197 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
254eb07c 2198
7ed4e635
HW		 2199 context->bw_ctx.dml.ip.odm_capable = odm_capable;
2200
0ba37b20
DL		 2201#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2202 /* 1 dsc per stream dsc validation */
2203 if (vlevel <= context->bw_ctx.dml.soc.num_states)
2204 if (!dcn20_validate_dsc(dc, context)) {
2205 failed_non_odm_dsc = true;
2206 vlevel = context->bw_ctx.dml.soc.num_states + 1;
2207 }
2208#endif
2209
7ed4e635
HW		 2210 if (vlevel > context->bw_ctx.dml.soc.num_states && odm_capable)
2211 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2212
2213 if (vlevel > context->bw_ctx.dml.soc.num_states)
2214 goto validate_fail;
2215
2216 if ((context->stream_count > split_threshold && dc->current_state->stream_count <= split_threshold)
2217 || (context->stream_count <= split_threshold && dc->current_state->stream_count > split_threshold))
2218 context->commit_hints.full_update_needed = true;
2219
2220 /*initialize pipe_just_split_from to invalid idx*/
2221 for (i = 0; i < MAX_PIPES; i++)
2222 pipe_split_from[i] = -1;
2223
2224 /* Single display only conditionals get set here */
2225 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2226 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2227 bool exit_loop = false;
2228
2229 if (!pipe->stream || pipe->top_pipe)
2230 continue;
2231
2232 if (dc->debug.force_single_disp_pipe_split) {
2233 if (!force_split)
2234 force_split = true;
2235 else {
2236 force_split = false;
2237 exit_loop = true;
2238 }
2239 }
2240 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP) {
2241 if (avoid_split)
2242 avoid_split = false;
2243 else {
2244 avoid_split = true;
2245 exit_loop = true;
2246 }
2247 }
2248 if (exit_loop)
2249 break;
2250 }
2251
2252 if (context->stream_count > split_threshold)
2253 avoid_split = true;
2254
2255 vlevel_unsplit = vlevel;
2256 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2257 if (!context->res_ctx.pipe_ctx[i].stream)
2258 continue;
2259 for (; vlevel_unsplit <= context->bw_ctx.dml.soc.num_states; vlevel_unsplit++)
2260 if (context->bw_ctx.dml.vba.NoOfDPP[vlevel_unsplit][0][pipe_idx] == 1)
2261 break;
2262 pipe_idx++;
2263 }
2264
2265 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2266 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2267 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2268 bool need_split = true;
2269 bool need_split3d;
2270
2271 if (!pipe->stream || pipe_split_from[i] >= 0)
2272 continue;
2273
2274 pipe_idx++;
2275
2276 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
2277 force_split = true;
2278 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx] = true;
2279 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = true;
2280 }
2281 if (force_split && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)
2282 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
7ed4e635
HW		 2283 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2284 hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, dc->res_pool, pipe);
2285 ASSERT(hsplit_pipe);
2286 if (!dcn20_split_stream_for_combine(
2287 &context->res_ctx, dc->res_pool,
2288 pipe, hsplit_pipe,
2289 true))
2290 goto validate_fail;
2291 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2292 dcn20_build_mapped_resource(dc, context, pipe->stream);
2293 }
2294
2295 if (!pipe->plane_state)
2296 continue;
2297 /* Skip 2nd half of already split pipe */
2298 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
2299 continue;
2300
2301 need_split3d = ((pipe->stream->view_format ==
2302 VIEW_3D_FORMAT_SIDE_BY_SIDE ||
2303 pipe->stream->view_format ==
2304 VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
2305 (pipe->stream->timing.timing_3d_format ==
2306 TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
2307 pipe->stream->timing.timing_3d_format ==
2308 TIMING_3D_FORMAT_SIDE_BY_SIDE));
2309
2310 if (avoid_split && vlevel_unsplit <= context->bw_ctx.dml.soc.num_states && !force_split && !need_split3d) {
2311 need_split = false;
2312 vlevel = vlevel_unsplit;
2313 context->bw_ctx.dml.vba.maxMpcComb = 0;
2314 } else
be67de35 2315 need_split = context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 2;
7ed4e635 2316
02ce5a79
DL		 2317 /* We do not support mpo + odm at the moment */
2318 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
2319 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
2320 goto validate_fail;
2321
7ed4e635
HW		 2322 if (need_split3d || need_split || force_split) {
2323 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
2324 /* pipe not split previously needs split */
2325 hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, dc->res_pool, pipe);
2326 ASSERT(hsplit_pipe || force_split);
2327 if (!hsplit_pipe)
2328 continue;
2329
2330 if (!dcn20_split_stream_for_combine(
2331 &context->res_ctx, dc->res_pool,
2332 pipe, hsplit_pipe,
2333 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]))
2334 goto validate_fail;
2335 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2336 }
02ce5a79 2337 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
7ed4e635
HW		 2338 /* merge should already have been done */
2339 ASSERT(0);
2340 }
2341 }
0ba37b20
DL		 2342#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2343 /* Actual dsc count per stream dsc validation*/
2344 if (failed_non_odm_dsc && !dcn20_validate_dsc(dc, context)) {
2345 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2346 DML_FAIL_DSC_VALIDATION_FAILURE;
2347 goto validate_fail;
2348 }
2349#endif
7ed4e635 2350
6de20237 2351 *vlevel_out = vlevel;
42351c66 2352
6de20237
EY		 2353 out = true;
2354 goto validate_out;
2355
2356validate_fail:
2357 out = false;
2358
2359validate_out:
2360 return out;
2361}
2362
2363void dcn20_calculate_wm(
2364 struct dc *dc, struct dc_state *context,
2365 display_e2e_pipe_params_st *pipes,
2366 int *out_pipe_cnt,
2367 int *pipe_split_from,
2368 int vlevel)
2369{
2370 int pipe_cnt, i, pipe_idx;
254eb07c 2371
7ed4e635 2372 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
6de20237
EY		 2373 if (!context->res_ctx.pipe_ctx[i].stream)
2374 continue;
7ed4e635 2375
6de20237
EY		 2376 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2377 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
7ed4e635 2378
6de20237
EY		 2379 if (pipe_split_from[i] < 0) {
2380 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2381 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
2382 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
2383 pipes[pipe_cnt].pipe.dest.odm_combine =
2384 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
2385 else
2386 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2387 pipe_idx++;
2388 } else {
2389 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2390 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
2391 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
2392 pipes[pipe_cnt].pipe.dest.odm_combine =
2393 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_split_from[i]];
2394 else
2395 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2396 }
2397
2398 if (dc->config.forced_clocks) {
2399 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2400 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2401 }
e9bcc1e0
DL		 2402 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
2403 pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2404 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
2405 pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
6de20237
EY		 2406
2407 pipe_cnt++;
7ed4e635 2408 }
6de20237
EY		 2409
2410 if (pipe_cnt != pipe_idx) {
2411 if (dc->res_pool->funcs->populate_dml_pipes)
2412 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2413 &context->res_ctx, pipes);
2414 else
2415 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
2416 &context->res_ctx, pipes);
a6465d1f 2417 }
7ed4e635 2418
6de20237 2419 *out_pipe_cnt = pipe_cnt;
7ed4e635 2420
6de20237
EY		 2421 pipes[0].clks_cfg.voltage = vlevel;
2422 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2423 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2424
2425 /* only pipe 0 is read for voltage and dcf/soc clocks */
2426 if (vlevel < 1) {
2427 pipes[0].clks_cfg.voltage = 1;
2428 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
2429 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
2430 }
2431 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2432 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2433 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2434 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2435 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2436
2437 if (vlevel < 2) {
2438 pipes[0].clks_cfg.voltage = 2;
2439 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2440 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2441 }
2442 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2443 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2444 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2445 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2446 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2447
2448 if (vlevel < 3) {
2449 pipes[0].clks_cfg.voltage = 3;
2450 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2451 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2452 }
2453 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2454 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2455 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2456 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2457 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2458
2459 pipes[0].clks_cfg.voltage = vlevel;
2460 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2461 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2462 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2463 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2464 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2465 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2466 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2467}
2468
2469void dcn20_calculate_dlg_params(
2470 struct dc *dc, struct dc_state *context,
2471 display_e2e_pipe_params_st *pipes,
2472 int pipe_cnt,
2473 int vlevel)
2474{
2475 int i, pipe_idx;
8e27a2d4 2476
7ed4e635
HW		 2477 /* Writeback MCIF_WB arbitration parameters */
2478 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
2479
2480 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
2481 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
2482 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
173932de 2483 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
7ed4e635 2484 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
f7f38ffe 2485 context->bw_ctx.bw.dcn.clk.fclk_khz = 0;
7ed4e635
HW		 2486 context->bw_ctx.bw.dcn.clk.p_state_change_support =
2487 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
2488 != dm_dram_clock_change_unsupported;
2489 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
2490
6de20237 2491
42351c66 2492
7ed4e635
HW		 2493 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2494 if (!context->res_ctx.pipe_ctx[i].stream)
2495 continue;
2496 pipes[pipe_idx].pipe.dest.vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx];
2497 pipes[pipe_idx].pipe.dest.vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx];
2498 pipes[pipe_idx].pipe.dest.vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx];
2499 pipes[pipe_idx].pipe.dest.vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx];
2500 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2501 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
2502 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
2503 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
97bda032 2504#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
b7d39c58 2505 context->res_ctx.pipe_ctx[i].stream_res.dscclk_khz =
97bda032
HW		 2506 context->bw_ctx.dml.vba.DSCCLK_calculated[pipe_idx] * 1000;
2507#endif
7ed4e635
HW		 2508 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
2509 pipe_idx++;
2510 }
925f566c
CL		 2511 /*save a original dppclock copy*/
2512 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
2513 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
2514 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz*1000;
2515 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz*1000;
7ed4e635
HW		 2516
2517 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2518 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
2519
2520 if (!context->res_ctx.pipe_ctx[i].stream)
2521 continue;
2522
2523 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
2524 &context->res_ctx.pipe_ctx[i].dlg_regs,
2525 &context->res_ctx.pipe_ctx[i].ttu_regs,
2526 pipes,
2527 pipe_cnt,
2528 pipe_idx,
2529 cstate_en,
f82c916c
CL		 2530 context->bw_ctx.bw.dcn.clk.p_state_change_support,
2531 false, false, false);
254eb07c 2532
7ed4e635
HW		 2533 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
2534 &context->res_ctx.pipe_ctx[i].rq_regs,
2535 pipes[pipe_idx].pipe);
2536 pipe_idx++;
2537 }
6de20237
EY		 2538}
2539
057fc695 2540static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
6de20237
EY		 2541 bool fast_validate)
2542{
2543 bool out = false;
2544
2545 BW_VAL_TRACE_SETUP();
2546
2547 int vlevel = 0;
2548 int pipe_split_from[MAX_PIPES];
2549 int pipe_cnt = 0;
2550 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2551 DC_LOGGER_INIT(dc->ctx->logger);
2552
2553 BW_VAL_TRACE_COUNT();
2554
5e335add
EY		 2555 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
2556
2557 if (pipe_cnt == 0)
2558 goto validate_out;
6de20237
EY		 2559
2560 if (!out)
2561 goto validate_fail;
2562
2563 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2564
2565 if (fast_validate) {
2566 BW_VAL_TRACE_SKIP(fast);
2567 goto validate_out;
2568 }
2569
2570 dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
2571 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2572
2573 BW_VAL_TRACE_END_WATERMARKS();
7ed4e635 2574
254eb07c 2575 goto validate_out;
7ed4e635
HW		 2576
2577validate_fail:
00999d99
DL		 2578 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2579 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
254eb07c 2580
42351c66 2581 BW_VAL_TRACE_SKIP(fail);
254eb07c
JA		 2582 out = false;
2583
2584validate_out:
7ed4e635 2585 kfree(pipes);
254eb07c 2586
42351c66
JA		 2587 BW_VAL_TRACE_FINISH();
2588
254eb07c 2589 return out;
7ed4e635
HW		 2590}
2591
057fc695
JL		 2592
2593bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
2594 bool fast_validate)
2595{
2596 bool voltage_supported = false;
2597 bool full_pstate_supported = false;
2598 bool dummy_pstate_supported = false;
2599 double p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
2600
2601 if (fast_validate)
2602 return dcn20_validate_bandwidth_internal(dc, context, true);
2603
2604
2605 // Best case, we support full UCLK switch latency
2606 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
2607 full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
2608
2609 if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
2610 (voltage_supported && full_pstate_supported)) {
2611 context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
2612 goto restore_dml_state;
2613 }
2614
b9e8d95a 2615 // Fallback: Try to only support G6 temperature read latency
057fc695
JL		 2616 context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
2617
2618 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
2619 dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
2620
2621 if (voltage_supported && dummy_pstate_supported) {
2622 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
2623 goto restore_dml_state;
2624 }
2625
b9e8d95a 2626 // ERROR: fallback is supposed to always work.
057fc695
JL		 2627 ASSERT(false);
2628
2629restore_dml_state:
2630 memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
2631 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
2632
2633 return voltage_supported;
2634}
2635
7ed4e635
HW		 2636struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
2637 struct dc_state *state,
2638 const struct resource_pool *pool,
2639 struct dc_stream_state *stream)
2640{
2641 struct resource_context *res_ctx = &state->res_ctx;
2642 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
2643 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
2644
2645 if (!head_pipe)
2646 ASSERT(0);
2647
2648 if (!idle_pipe)
7a17c8ce 2649 return NULL;
7ed4e635
HW		 2650
2651 idle_pipe->stream = head_pipe->stream;
2652 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
2653 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
2654
2655 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
2656 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
2657 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
2658 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
2659
2660 return idle_pipe;
2661}
2662
2663bool dcn20_get_dcc_compression_cap(const struct dc *dc,
2664 const struct dc_dcc_surface_param *input,
2665 struct dc_surface_dcc_cap *output)
2666{
2667 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
2668 dc->res_pool->hubbub,
2669 input,
2670 output);
2671}
2672
2673static void dcn20_destroy_resource_pool(struct resource_pool **pool)
2674{
2675 struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);
2676
2677 destruct(dcn20_pool);
2678 kfree(dcn20_pool);
2679 *pool = NULL;
2680}
2681
2682
2683static struct dc_cap_funcs cap_funcs = {
2684 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
2685};
2686
2687
2688enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state)
2689{
2690 enum dc_status result = DC_OK;
2691
2692 enum surface_pixel_format surf_pix_format = plane_state->format;
2693 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
2694
2695 enum swizzle_mode_values swizzle = DC_SW_LINEAR;
2696
2697 if (bpp == 64)
2698 swizzle = DC_SW_64KB_D;
2699 else
2700 swizzle = DC_SW_64KB_S;
2701
2702 plane_state->tiling_info.gfx9.swizzle = swizzle;
2703 return result;
2704}
2705
2706static struct resource_funcs dcn20_res_pool_funcs = {
2707 .destroy = dcn20_destroy_resource_pool,
2708 .link_enc_create = dcn20_link_encoder_create,
2709 .validate_bandwidth = dcn20_validate_bandwidth,
7ed4e635
HW		 2710 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
2711 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
2712 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2713 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
2714 .get_default_swizzle_mode = dcn20_get_default_swizzle_mode,
c9ae6e16 2715 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
278141f5 2716 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
7ed4e635
HW		 2717};
2718
bb21290f
CL		 2719bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
2720{
2721 int i;
2722 uint32_t pipe_count = pool->res_cap->num_dwb;
2723
2724 ASSERT(pipe_count > 0);
2725
2726 for (i = 0; i < pipe_count; i++) {
2727 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
2728 GFP_KERNEL);
2729
2730 if (!dwbc20) {
2731 dm_error("DC: failed to create dwbc20!\n");
2732 return false;
2733 }
2734 dcn20_dwbc_construct(dwbc20, ctx,
2735 &dwbc20_regs[i],
2736 &dwbc20_shift,
2737 &dwbc20_mask,
2738 i);
2739 pool->dwbc[i] = &dwbc20->base;
2740 }
2741 return true;
2742}
2743
2744bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
2745{
2746 int i;
2747 uint32_t pipe_count = pool->res_cap->num_dwb;
2748
2749 ASSERT(pipe_count > 0);
2750
2751 for (i = 0; i < pipe_count; i++) {
2752 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub),
2753 GFP_KERNEL);
2754
2755 if (!mcif_wb20) {
2756 dm_error("DC: failed to create mcif_wb20!\n");
2757 return false;
2758 }
2759
2760 dcn20_mmhubbub_construct(mcif_wb20, ctx,
2761 &mcif_wb20_regs[i],
2762 &mcif_wb20_shift,
2763 &mcif_wb20_mask,
2764 i);
2765
2766 pool->mcif_wb[i] = &mcif_wb20->base;
2767 }
2768 return true;
2769}
2770
7ed4e635
HW		 2771struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
2772{
2773 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
2774
2775 if (!pp_smu)
2776 return pp_smu;
2777
2778 dm_pp_get_funcs(ctx, pp_smu);
2779
2780 if (pp_smu->ctx.ver != PP_SMU_VER_NV)
2781 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
2782
2783 return pp_smu;
2784}
2785
2786void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
2787{
2788 if (pp_smu && *pp_smu) {
2789 kfree(*pp_smu);
2790 *pp_smu = NULL;
2791 }
2792}
2793
2794static void cap_soc_clocks(
2795 struct _vcs_dpi_soc_bounding_box_st *bb,
2796 struct pp_smu_nv_clock_table max_clocks)
2797{
2798 int i;
2799
2800 // First pass - cap all clocks higher than the reported max
2801 for (i = 0; i < bb->num_states; i++) {
2802 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
2803 && max_clocks.dcfClockInKhz != 0)
2804 bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
2805
2806 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
2807 && max_clocks.uClockInKhz != 0)
2808 bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
2809
2810 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
2811 && max_clocks.fabricClockInKhz != 0)
2812 bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
2813
2814 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
2815 && max_clocks.displayClockInKhz != 0)
2816 bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
2817
2818 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
2819 && max_clocks.dppClockInKhz != 0)
2820 bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
2821
2822 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
2823 && max_clocks.phyClockInKhz != 0)
2824 bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
2825
2826 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
2827 && max_clocks.socClockInKhz != 0)
2828 bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
2829
2830 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
2831 && max_clocks.dscClockInKhz != 0)
2832 bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
2833 }
2834
2835 // Second pass - remove all duplicate clock states
2836 for (i = bb->num_states - 1; i > 1; i--) {
2837 bool duplicate = true;
2838
2839 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz)
2840 duplicate = false;
2841 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz)
2842 duplicate = false;
2843 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz)
2844 duplicate = false;
2845 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts)
2846 duplicate = false;
2847 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz)
2848 duplicate = false;
2849 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz)
2850 duplicate = false;
2851 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz)
2852 duplicate = false;
2853 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz)
2854 duplicate = false;
2855
2856 if (duplicate)
2857 bb->num_states--;
2858 }
2859}
2860
2861static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
2862 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
2863{
2864 struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES] = {0};
f18bc4e5 2865 int i;
7ed4e635 2866 int num_calculated_states = 0;
f18bc4e5 2867 int min_dcfclk = 0;
7ed4e635
HW		 2868
2869 if (num_states == 0)
2870 return;
2871
f18bc4e5
JL		 2872 if (dc->bb_overrides.min_dcfclk_mhz > 0)
2873 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
ff4258d5
JL		 2874 else
2875 // Accounting for SOC/DCF relationship, we can go as high as
2876 // 506Mhz in Vmin. We need to code 507 since SMU will round down to 506.
2877 min_dcfclk = 507;
f18bc4e5 2878
7ed4e635 2879 for (i = 0; i < num_states; i++) {
f18bc4e5
JL		 2880 int min_fclk_required_by_uclk;
2881 calculated_states[i].state = i;
2882 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
7ed4e635 2883
5d36f783 2884 // FCLK:UCLK ratio is 1.08
5f65ae34 2885 min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32);
7ed4e635 2886
f18bc4e5
JL		 2887 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
2888 min_dcfclk : min_fclk_required_by_uclk;
7ed4e635 2889
f18bc4e5
JL		 2890 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
2891 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
7ed4e635 2892
f18bc4e5
JL		 2893 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
2894 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
7ed4e635 2895
f18bc4e5
JL		 2896 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
2897 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
2898 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
7ed4e635 2899
f18bc4e5 2900 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
7ed4e635 2901
f18bc4e5 2902 num_calculated_states++;
7ed4e635
HW		 2903 }
2904
6da16270
JL		 2905 calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
2906 calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
2907 calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
2908
7ed4e635
HW		 2909 memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
2910 bb->num_states = num_calculated_states;
f18bc4e5
JL		 2911
2912 // Duplicate the last state, DML always an extra state identical to max state to work
2913 memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st));
2914 bb->clock_limits[num_calculated_states].state = bb->num_states;
7ed4e635
HW		 2915}
2916
2917static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
2918{
2919 kernel_fpu_begin();
2920 if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
2921 && dc->bb_overrides.sr_exit_time_ns) {
2922 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
2923 }
2924
2925 if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
2926 != dc->bb_overrides.sr_enter_plus_exit_time_ns
2927 && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
2928 bb->sr_enter_plus_exit_time_us =
2929 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
2930 }
2931
2932 if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
2933 && dc->bb_overrides.urgent_latency_ns) {
2934 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
2935 }
2936
2937 if ((int)(bb->dram_clock_change_latency_us * 1000)
2938 != dc->bb_overrides.dram_clock_change_latency_ns
2939 && dc->bb_overrides.dram_clock_change_latency_ns) {
2940 bb->dram_clock_change_latency_us =
2941 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
2942 }
2943 kernel_fpu_end();
2944}
2945
2946#define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
2947#define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
2948
2949static bool init_soc_bounding_box(struct dc *dc,
2950 struct dcn20_resource_pool *pool)
2951{
2952 const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
2953 DC_LOGGER_INIT(dc->ctx->logger);
2954
2955 if (!bb && !SOC_BOUNDING_BOX_VALID) {
2956 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
2957 return false;
2958 }
2959
2960 if (bb && !SOC_BOUNDING_BOX_VALID) {
2961 int i;
2962
2963 dcn2_0_soc.sr_exit_time_us =
2964 fixed16_to_double_to_cpu(bb->sr_exit_time_us);
2965 dcn2_0_soc.sr_enter_plus_exit_time_us =
2966 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us);
2967 dcn2_0_soc.urgent_latency_us =
2968 fixed16_to_double_to_cpu(bb->urgent_latency_us);
2969 dcn2_0_soc.urgent_latency_pixel_data_only_us =
2970 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us);
2971 dcn2_0_soc.urgent_latency_pixel_mixed_with_vm_data_us =
2972 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us);
2973 dcn2_0_soc.urgent_latency_vm_data_only_us =
2974 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us);
2975 dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
2976 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes);
2977 dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
2978 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes);
2979 dcn2_0_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
2980 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes);
2981 dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
2982 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only);
2983 dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
2984 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm);
2985 dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
2986 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only);
2987 dcn2_0_soc.max_avg_sdp_bw_use_normal_percent =
2988 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent);
2989 dcn2_0_soc.max_avg_dram_bw_use_normal_percent =
2990 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent);
2991 dcn2_0_soc.writeback_latency_us =
2992 fixed16_to_double_to_cpu(bb->writeback_latency_us);
2993 dcn2_0_soc.ideal_dram_bw_after_urgent_percent =
2994 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent);
2995 dcn2_0_soc.max_request_size_bytes =
2996 le32_to_cpu(bb->max_request_size_bytes);
2997 dcn2_0_soc.dram_channel_width_bytes =
2998 le32_to_cpu(bb->dram_channel_width_bytes);
2999 dcn2_0_soc.fabric_datapath_to_dcn_data_return_bytes =
3000 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes);
3001 dcn2_0_soc.dcn_downspread_percent =
3002 fixed16_to_double_to_cpu(bb->dcn_downspread_percent);
3003 dcn2_0_soc.downspread_percent =
3004 fixed16_to_double_to_cpu(bb->downspread_percent);
3005 dcn2_0_soc.dram_page_open_time_ns =
3006 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns);
3007 dcn2_0_soc.dram_rw_turnaround_time_ns =
3008 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns);
3009 dcn2_0_soc.dram_return_buffer_per_channel_bytes =
3010 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes);
3011 dcn2_0_soc.round_trip_ping_latency_dcfclk_cycles =
3012 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles);
3013 dcn2_0_soc.urgent_out_of_order_return_per_channel_bytes =
3014 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes);
3015 dcn2_0_soc.channel_interleave_bytes =
3016 le32_to_cpu(bb->channel_interleave_bytes);
3017 dcn2_0_soc.num_banks =
3018 le32_to_cpu(bb->num_banks);
3019 dcn2_0_soc.num_chans =
3020 le32_to_cpu(bb->num_chans);
3021 dcn2_0_soc.vmm_page_size_bytes =
3022 le32_to_cpu(bb->vmm_page_size_bytes);
3023 dcn2_0_soc.dram_clock_change_latency_us =
3024 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
3025 dcn2_0_soc.writeback_dram_clock_change_latency_us =
3026 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
3027 dcn2_0_soc.return_bus_width_bytes =
3028 le32_to_cpu(bb->return_bus_width_bytes);
3029 dcn2_0_soc.dispclk_dppclk_vco_speed_mhz =
3030 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz);
3031 dcn2_0_soc.xfc_bus_transport_time_us =
3032 le32_to_cpu(bb->xfc_bus_transport_time_us);
3033 dcn2_0_soc.xfc_xbuf_latency_tolerance_us =
3034 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us);
3035 dcn2_0_soc.use_urgent_burst_bw =
3036 le32_to_cpu(bb->use_urgent_burst_bw);
3037 dcn2_0_soc.num_states =
3038 le32_to_cpu(bb->num_states);
3039
3040 for (i = 0; i < dcn2_0_soc.num_states; i++) {
3041 dcn2_0_soc.clock_limits[i].state =
3042 le32_to_cpu(bb->clock_limits[i].state);
3043 dcn2_0_soc.clock_limits[i].dcfclk_mhz =
3044 fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz);
3045 dcn2_0_soc.clock_limits[i].fabricclk_mhz =
3046 fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz);
3047 dcn2_0_soc.clock_limits[i].dispclk_mhz =
3048 fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz);
3049 dcn2_0_soc.clock_limits[i].dppclk_mhz =
3050 fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz);
3051 dcn2_0_soc.clock_limits[i].phyclk_mhz =
3052 fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz);
3053 dcn2_0_soc.clock_limits[i].socclk_mhz =
3054 fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz);
3055 dcn2_0_soc.clock_limits[i].dscclk_mhz =
3056 fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz);
3057 dcn2_0_soc.clock_limits[i].dram_speed_mts =
3058 fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
3059 }
3060 }
3061
3062 if (pool->base.pp_smu) {
3063 struct pp_smu_nv_clock_table max_clocks = {0};
3064 unsigned int uclk_states[8] = {0};
3065 unsigned int num_states = 0;
3066 enum pp_smu_status status;
3067 bool clock_limits_available = false;
3068 bool uclk_states_available = false;
3069
3070 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
3071 status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
3072 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
3073
3074 uclk_states_available = (status == PP_SMU_RESULT_OK);
3075 }
3076
3077 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
3078 status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
3079 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
c2ad17c3
AW		 3080 /* SMU cannot set DCF clock to anything equal to or higher than SOC clock
3081 */
3082 if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
3083 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
7ed4e635
HW		 3084 clock_limits_available = (status == PP_SMU_RESULT_OK);
3085 }
3086
c2ad17c3 3087 if (clock_limits_available && uclk_states_available && num_states)
7ed4e635
HW		 3088 update_bounding_box(dc, &dcn2_0_soc, &max_clocks, uclk_states, num_states);
3089 else if (clock_limits_available)
3090 cap_soc_clocks(&dcn2_0_soc, max_clocks);
3091 }
3092
3093 dcn2_0_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
3094 dcn2_0_ip.max_num_dpp = pool->base.pipe_count;
3095 patch_bounding_box(dc, &dcn2_0_soc);
3096
3097 return true;
3098}
3099
3100static bool construct(
3101 uint8_t num_virtual_links,
3102 struct dc *dc,
3103 struct dcn20_resource_pool *pool)
3104{
3105 int i;
3106 struct dc_context *ctx = dc->ctx;
3107 struct irq_service_init_data init_data;
3108
3109 ctx->dc_bios->regs = &bios_regs;
7ed4e635
HW		 3110 pool->base.funcs = &dcn20_res_pool_funcs;
3111
2ebe1773
BL		 3112 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
3113 pool->base.res_cap = &res_cap_nv14;
3114 pool->base.pipe_count = 5;
3115 pool->base.mpcc_count = 5;
3116 } else {
3117 pool->base.res_cap = &res_cap_nv10;
3118 pool->base.pipe_count = 6;
3119 pool->base.mpcc_count = 6;
3120 }
7ed4e635
HW		 3121 /*************************************************
3122 * Resource + asic cap harcoding *
3123 *************************************************/
3124 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
3125
7ed4e635
HW		 3126 dc->caps.max_downscale_ratio = 200;
3127 dc->caps.i2c_speed_in_khz = 100;
3128 dc->caps.max_cursor_size = 256;
3129 dc->caps.dmdata_alloc_size = 2048;
3130
3131 dc->caps.max_slave_planes = 1;
3132 dc->caps.post_blend_color_processing = true;
3133 dc->caps.force_dp_tps4_for_cp2520 = true;
3134 dc->caps.hw_3d_lut = true;
3135
803a1412 3136 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) {
7ed4e635 3137 dc->debug = debug_defaults_drv;
803a1412
ES		 3138 } else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
3139 pool->base.pipe_count = 4;
7ed4e635
HW		 3140 pool->base.mpcc_count = pool->base.pipe_count;
3141 dc->debug = debug_defaults_diags;
803a1412 3142 } else {
7ed4e635 3143 dc->debug = debug_defaults_diags;
803a1412 3144 }
7ed4e635
HW		 3145 //dcn2.0x
3146 dc->work_arounds.dedcn20_305_wa = true;
3147
3148 // Init the vm_helper
3149 if (dc->vm_helper)
bda9afda 3150 vm_helper_init(dc->vm_helper, 16);
7ed4e635
HW		 3151
3152 /*************************************************
3153 * Create resources *
3154 *************************************************/
3155
3156 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
3157 dcn20_clock_source_create(ctx, ctx->dc_bios,
3158 CLOCK_SOURCE_COMBO_PHY_PLL0,
3159 &clk_src_regs[0], false);
3160 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
3161 dcn20_clock_source_create(ctx, ctx->dc_bios,
3162 CLOCK_SOURCE_COMBO_PHY_PLL1,
3163 &clk_src_regs[1], false);
3164 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
3165 dcn20_clock_source_create(ctx, ctx->dc_bios,
3166 CLOCK_SOURCE_COMBO_PHY_PLL2,
3167 &clk_src_regs[2], false);
3168 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
3169 dcn20_clock_source_create(ctx, ctx->dc_bios,
3170 CLOCK_SOURCE_COMBO_PHY_PLL3,
3171 &clk_src_regs[3], false);
3172 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
3173 dcn20_clock_source_create(ctx, ctx->dc_bios,
3174 CLOCK_SOURCE_COMBO_PHY_PLL4,
3175 &clk_src_regs[4], false);
3176 pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =
3177 dcn20_clock_source_create(ctx, ctx->dc_bios,
3178 CLOCK_SOURCE_COMBO_PHY_PLL5,
3179 &clk_src_regs[5], false);
3180 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;
3181 /* todo: not reuse phy_pll registers */
3182 pool->base.dp_clock_source =
3183 dcn20_clock_source_create(ctx, ctx->dc_bios,
3184 CLOCK_SOURCE_ID_DP_DTO,
3185 &clk_src_regs[0], true);
3186
3187 for (i = 0; i < pool->base.clk_src_count; i++) {
3188 if (pool->base.clock_sources[i] == NULL) {
3189 dm_error("DC: failed to create clock sources!\n");
3190 BREAK_TO_DEBUGGER();
3191 goto create_fail;
3192 }
3193 }
3194
3195 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
3196 if (pool->base.dccg == NULL) {
3197 dm_error("DC: failed to create dccg!\n");
3198 BREAK_TO_DEBUGGER();
3199 goto create_fail;
3200 }
3201
3202 pool->base.dmcu = dcn20_dmcu_create(ctx,
3203 &dmcu_regs,
3204 &dmcu_shift,
3205 &dmcu_mask);
3206 if (pool->base.dmcu == NULL) {
3207 dm_error("DC: failed to create dmcu!\n");
3208 BREAK_TO_DEBUGGER();
3209 goto create_fail;
3210 }
3211
d7c29549 3212 pool->base.abm = dce_abm_create(ctx,
7ed4e635
HW		 3213 &abm_regs,
3214 &abm_shift,
3215 &abm_mask);
3216 if (pool->base.abm == NULL) {
3217 dm_error("DC: failed to create abm!\n");
3218 BREAK_TO_DEBUGGER();
3219 goto create_fail;
d7c29549 3220 }
7ed4e635
HW		 3221
3222 pool->base.pp_smu = dcn20_pp_smu_create(ctx);
3223
3224
3225 if (!init_soc_bounding_box(dc, pool)) {
3226 dm_error("DC: failed to initialize soc bounding box!\n");
3227 BREAK_TO_DEBUGGER();
3228 goto create_fail;
3229 }
3230
b9e8d95a 3231 dml_init_instance(&dc->dml, &dcn2_0_soc, &dcn2_0_ip, DML_PROJECT_NAVI10v2);
7ed4e635
HW		 3232
3233 if (!dc->debug.disable_pplib_wm_range) {
3234 struct pp_smu_wm_range_sets ranges = {0};
3235 int i = 0;
3236
3237 ranges.num_reader_wm_sets = 0;
3238
3239 if (dcn2_0_soc.num_states == 1) {
3240 ranges.reader_wm_sets[0].wm_inst = i;
3241 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3242 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3243 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3244 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3245
3246 ranges.num_reader_wm_sets = 1;
3247 } else if (dcn2_0_soc.num_states > 1) {
5d36f783 3248 for (i = 0; i < 4 && i < dcn2_0_soc.num_states; i++) {
7ed4e635
HW		 3249 ranges.reader_wm_sets[i].wm_inst = i;
3250 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3251 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
5d36f783
JL		 3252 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (dcn2_0_soc.clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
3253 ranges.reader_wm_sets[i].max_fill_clk_mhz = dcn2_0_soc.clock_limits[i].dram_speed_mts / 16;
7ed4e635
HW		 3254
3255 ranges.num_reader_wm_sets = i + 1;
3256 }
7ed4e635 3257
5d36f783
JL		 3258 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3259 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3260 }
7ed4e635
HW		 3261
3262 ranges.num_writer_wm_sets = 1;
3263
3264 ranges.writer_wm_sets[0].wm_inst = 0;
3265 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3266 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3267 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3268 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3269
3270 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
3271 if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
3272 pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);
3273 }
3274
3275 init_data.ctx = dc->ctx;
3276 pool->base.irqs = dal_irq_service_dcn20_create(&init_data);
3277 if (!pool->base.irqs)
3278 goto create_fail;
3279
3280 /* mem input -> ipp -> dpp -> opp -> TG */
3281 for (i = 0; i < pool->base.pipe_count; i++) {
3282 pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
3283 if (pool->base.hubps[i] == NULL) {
3284 BREAK_TO_DEBUGGER();
3285 dm_error(
3286 "DC: failed to create memory input!\n");
3287 goto create_fail;
3288 }
3289
3290 pool->base.ipps[i] = dcn20_ipp_create(ctx, i);
3291 if (pool->base.ipps[i] == NULL) {
3292 BREAK_TO_DEBUGGER();
3293 dm_error(
3294 "DC: failed to create input pixel processor!\n");
3295 goto create_fail;
3296 }
3297
3298 pool->base.dpps[i] = dcn20_dpp_create(ctx, i);
3299 if (pool->base.dpps[i] == NULL) {
3300 BREAK_TO_DEBUGGER();
3301 dm_error(
3302 "DC: failed to create dpps!\n");
3303 goto create_fail;
3304 }
3305 }
3306 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
3307 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i);
3308 if (pool->base.engines[i] == NULL) {
3309 BREAK_TO_DEBUGGER();
3310 dm_error(
3311 "DC:failed to create aux engine!!\n");
3312 goto create_fail;
3313 }
3314 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i);
3315 if (pool->base.hw_i2cs[i] == NULL) {
3316 BREAK_TO_DEBUGGER();
3317 dm_error(
3318 "DC:failed to create hw i2c!!\n");
3319 goto create_fail;
3320 }
3321 pool->base.sw_i2cs[i] = NULL;
3322 }
3323
3324 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
3325 pool->base.opps[i] = dcn20_opp_create(ctx, i);
3326 if (pool->base.opps[i] == NULL) {
3327 BREAK_TO_DEBUGGER();
3328 dm_error(
3329 "DC: failed to create output pixel processor!\n");
3330 goto create_fail;
3331 }
3332 }
3333
3334 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
3335 pool->base.timing_generators[i] = dcn20_timing_generator_create(
3336 ctx, i);
3337 if (pool->base.timing_generators[i] == NULL) {
3338 BREAK_TO_DEBUGGER();
3339 dm_error("DC: failed to create tg!\n");
3340 goto create_fail;
3341 }
3342 }
3343
3344 pool->base.timing_generator_count = i;
3345
3346 pool->base.mpc = dcn20_mpc_create(ctx);
3347 if (pool->base.mpc == NULL) {
3348 BREAK_TO_DEBUGGER();
3349 dm_error("DC: failed to create mpc!\n");
3350 goto create_fail;
3351 }
3352
3353 pool->base.hubbub = dcn20_hubbub_create(ctx);
3354 if (pool->base.hubbub == NULL) {
3355 BREAK_TO_DEBUGGER();
3356 dm_error("DC: failed to create hubbub!\n");
3357 goto create_fail;
3358 }
3359
97bda032
HW		 3360#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3361 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
3362 pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
3363 if (pool->base.dscs[i] == NULL) {
3364 BREAK_TO_DEBUGGER();
3365 dm_error("DC: failed to create display stream compressor %d!\n", i);
3366 goto create_fail;
3367 }
3368 }
3369#endif
7ed4e635 3370
bb21290f
CL		 3371 if (!dcn20_dwbc_create(ctx, &pool->base)) {
3372 BREAK_TO_DEBUGGER();
3373 dm_error("DC: failed to create dwbc!\n");
3374 goto create_fail;
3375 }
3376 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
3377 BREAK_TO_DEBUGGER();
3378 dm_error("DC: failed to create mcif_wb!\n");
3379 goto create_fail;
3380 }
3381
7ed4e635
HW		 3382 if (!resource_construct(num_virtual_links, dc, &pool->base,
3383 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
3384 &res_create_funcs : &res_create_maximus_funcs)))
3385 goto create_fail;
3386
3387 dcn20_hw_sequencer_construct(dc);
3388
3389 dc->caps.max_planes = pool->base.pipe_count;
3390
3391 for (i = 0; i < dc->caps.max_planes; ++i)
3392 dc->caps.planes[i] = plane_cap;
3393
3394 dc->cap_funcs = cap_funcs;
3395
3396 return true;
3397
3398create_fail:
3399
3400 destruct(pool);
3401
3402 return false;
3403}
3404
3405struct resource_pool *dcn20_create_resource_pool(
3406 const struct dc_init_data *init_data,
3407 struct dc *dc)
3408{
3409 struct dcn20_resource_pool *pool =
3410 kzalloc(sizeof(struct dcn20_resource_pool), GFP_KERNEL);
3411
3412 if (!pool)
3413 return NULL;
3414
3415 if (construct(init_data->num_virtual_links, dc, pool))
3416 return &pool->base;
3417
3418 BREAK_TO_DEBUGGER();
3419 kfree(pool);
3420 return NULL;
3421}
Linux 6.x block layer and io_uring tree(s)