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drm/amd/display: Add infrastructure for enabling FAMS for DCN30
[linux-block.git] / drivers / gpu / drm / amd / display / dc / dcn20 / dcn20_hwseq.c
CommitLineData
7ed4e635
HW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
c602b36f 25#include <linux/delay.h>
7ed4e635
HW		 26
27#include "dm_services.h"
78c77382 28#include "basics/dc_common.h"
7ed4e635
HW		 29#include "dm_helpers.h"
30#include "core_types.h"
31#include "resource.h"
78c77382 32#include "dcn20_resource.h"
7ed4e635
HW		 33#include "dcn20_hwseq.h"
34#include "dce/dce_hwseq.h"
78c77382
AK		 35#include "dcn20_dsc.h"
36#include "dcn20_optc.h"
7ed4e635
HW		 37#include "abm.h"
38#include "clk_mgr.h"
39#include "dmcu.h"
40#include "hubp.h"
41#include "timing_generator.h"
42#include "opp.h"
43#include "ipp.h"
44#include "mpc.h"
45#include "mcif_wb.h"
78c77382 46#include "dchubbub.h"
7ed4e635
HW		 47#include "reg_helper.h"
48#include "dcn10/dcn10_cm_common.h"
7ed4e635
HW		 49#include "vm_helper.h"
50#include "dccg.h"
dc6e2448
WW		 51#include "dc_dmub_srv.h"
52#include "dce/dmub_hw_lock_mgr.h"
60df8441 53#include "hw_sequencer.h"
3550d622 54#include "dpcd_defs.h"
0d4b4253 55#include "inc/link_enc_cfg.h"
dfabe597 56#include "link_hwss.h"
d5a43956 57#include "link.h"
7ed4e635
HW		 58
59#define DC_LOGGER_INIT(logger)
60
61#define CTX \
62 hws->ctx
63#define REG(reg)\
64 hws->regs->reg
65
66#undef FN
67#define FN(reg_name, field_name) \
68 hws->shifts->field_name, hws->masks->field_name
69
78c77382
AK		 70static int find_free_gsl_group(const struct dc *dc)
71{
72 if (dc->res_pool->gsl_groups.gsl_0 == 0)
73 return 1;
74 if (dc->res_pool->gsl_groups.gsl_1 == 0)
75 return 2;
76 if (dc->res_pool->gsl_groups.gsl_2 == 0)
77 return 3;
78
79 return 0;
80}
81
82/* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock)
83 * This is only used to lock pipes in pipe splitting case with immediate flip
84 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate,
85 * so we get tearing with freesync since we cannot flip multiple pipes
86 * atomically.
87 * We use GSL for this:
88 * - immediate flip: find first available GSL group if not already assigned
89 * program gsl with that group, set current OTG as master
90 * and always us 0x4 = AND of flip_ready from all pipes
91 * - vsync flip: disable GSL if used
92 *
93 * Groups in stream_res are stored as +1 from HW registers, i.e.
94 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
95 * Using a magic value like -1 would require tracking all inits/resets
96 */
97static void dcn20_setup_gsl_group_as_lock(
98 const struct dc *dc,
99 struct pipe_ctx *pipe_ctx,
100 bool enable)
101{
102 struct gsl_params gsl;
103 int group_idx;
104
105 memset(&gsl, 0, sizeof(struct gsl_params));
106
107 if (enable) {
108 /* return if group already assigned since GSL was set up
109 * for vsync flip, we would unassign so it can't be "left over"
110 */
111 if (pipe_ctx->stream_res.gsl_group > 0)
112 return;
113
114 group_idx = find_free_gsl_group(dc);
115 ASSERT(group_idx != 0);
116 pipe_ctx->stream_res.gsl_group = group_idx;
117
118 /* set gsl group reg field and mark resource used */
119 switch (group_idx) {
120 case 1:
121 gsl.gsl0_en = 1;
122 dc->res_pool->gsl_groups.gsl_0 = 1;
123 break;
124 case 2:
125 gsl.gsl1_en = 1;
126 dc->res_pool->gsl_groups.gsl_1 = 1;
127 break;
128 case 3:
129 gsl.gsl2_en = 1;
130 dc->res_pool->gsl_groups.gsl_2 = 1;
131 break;
132 default:
133 BREAK_TO_DEBUGGER();
134 return; // invalid case
135 }
136 gsl.gsl_master_en = 1;
137 } else {
138 group_idx = pipe_ctx->stream_res.gsl_group;
139 if (group_idx == 0)
140 return; // if not in use, just return
141
142 pipe_ctx->stream_res.gsl_group = 0;
143
144 /* unset gsl group reg field and mark resource free */
145 switch (group_idx) {
146 case 1:
147 gsl.gsl0_en = 0;
148 dc->res_pool->gsl_groups.gsl_0 = 0;
149 break;
150 case 2:
151 gsl.gsl1_en = 0;
152 dc->res_pool->gsl_groups.gsl_1 = 0;
153 break;
154 case 3:
155 gsl.gsl2_en = 0;
156 dc->res_pool->gsl_groups.gsl_2 = 0;
157 break;
158 default:
159 BREAK_TO_DEBUGGER();
160 return;
161 }
162 gsl.gsl_master_en = 0;
163 }
164
165 /* at this point we want to program whether it's to enable or disable */
166 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
167 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
168 pipe_ctx->stream_res.tg->funcs->set_gsl(
169 pipe_ctx->stream_res.tg,
170 &gsl);
171
172 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
173 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0);
174 } else
175 BREAK_TO_DEBUGGER();
176}
177
178void dcn20_set_flip_control_gsl(
179 struct pipe_ctx *pipe_ctx,
180 bool flip_immediate)
181{
182 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)
183 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(
184 pipe_ctx->plane_res.hubp, flip_immediate);
185
186}
187
188void dcn20_enable_power_gating_plane(
7ed4e635
HW		 189 struct dce_hwseq *hws,
190 bool enable)
191{
0bb80369 192 bool force_on = true; /* disable power gating */
504d3cae 193 uint32_t org_ip_request_cntl = 0;
7ed4e635
HW		 194
195 if (enable)
0bb80369 196 force_on = false;
7ed4e635 197
504d3cae
HW		 198 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
199 if (org_ip_request_cntl == 0)
200 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
201
7ed4e635
HW		 202 /* DCHUBP0/1/2/3/4/5 */
203 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
204 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
205 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
206 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
46825fcf
TC		 207 if (REG(DOMAIN8_PG_CONFIG))
208 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
209 if (REG(DOMAIN10_PG_CONFIG))
210 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
7ed4e635
HW		 211
212 /* DPP0/1/2/3/4/5 */
213 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
214 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
215 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
216 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
46825fcf
TC		 217 if (REG(DOMAIN9_PG_CONFIG))
218 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
219 if (REG(DOMAIN11_PG_CONFIG))
220 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
7ed4e635 221
46825fcf 222 /* DCS0/1/2/3/4/5 */
7ed4e635
HW		 223 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on);
224 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on);
225 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on);
46825fcf
TC		 226 if (REG(DOMAIN19_PG_CONFIG))
227 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on);
228 if (REG(DOMAIN20_PG_CONFIG))
229 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on);
230 if (REG(DOMAIN21_PG_CONFIG))
231 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on);
504d3cae
HW		 232
233 if (org_ip_request_cntl == 0)
234 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
235
7ed4e635
HW		 236}
237
c70b4016 238void dcn20_dccg_init(struct dce_hwseq *hws)
7ed4e635
HW		 239{
240 /*
241 * set MICROSECOND_TIME_BASE_DIV
242 * 100Mhz refclk -> 0x120264
243 * 27Mhz refclk -> 0x12021b
244 * 48Mhz refclk -> 0x120230
245 *
246 */
247 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264);
248
249 /*
250 * set MILLISECOND_TIME_BASE_DIV
251 * 100Mhz refclk -> 0x1186a0
252 * 27Mhz refclk -> 0x106978
253 * 48Mhz refclk -> 0x10bb80
254 *
255 */
256 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
257
258 /* This value is dependent on the hardware pipeline delay so set once per SOC */
3577e167 259 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c);
7ed4e635
HW		 260}
261
8a31820b 262void dcn20_disable_vga(
7ed4e635
HW		 263 struct dce_hwseq *hws)
264{
265 REG_WRITE(D1VGA_CONTROL, 0);
266 REG_WRITE(D2VGA_CONTROL, 0);
267 REG_WRITE(D3VGA_CONTROL, 0);
268 REG_WRITE(D4VGA_CONTROL, 0);
269 REG_WRITE(D5VGA_CONTROL, 0);
270 REG_WRITE(D6VGA_CONTROL, 0);
271}
272
78c77382 273void dcn20_program_triple_buffer(
7ed4e635
HW		 274 const struct dc *dc,
275 struct pipe_ctx *pipe_ctx,
78c77382 276 bool enable_triple_buffer)
7ed4e635
HW		 277{
278 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {
279 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(
280 pipe_ctx->plane_res.hubp,
78c77382 281 enable_triple_buffer);
7ed4e635
HW		 282 }
283}
284
285/* Blank pixel data during initialization */
c70b4016 286void dcn20_init_blank(
7ed4e635
HW		 287 struct dc *dc,
288 struct timing_generator *tg)
289{
f42ea55b 290 struct dce_hwseq *hws = dc->hwseq;
7ed4e635
HW		 291 enum dc_color_space color_space;
292 struct tg_color black_color = {0};
293 struct output_pixel_processor *opp = NULL;
294 struct output_pixel_processor *bottom_opp = NULL;
295 uint32_t num_opps, opp_id_src0, opp_id_src1;
296 uint32_t otg_active_width, otg_active_height;
297
298 /* program opp dpg blank color */
299 color_space = COLOR_SPACE_SRGB;
300 color_space_to_black_color(dc, color_space, &black_color);
301
302 /* get the OTG active size */
303 tg->funcs->get_otg_active_size(tg,
304 &otg_active_width,
305 &otg_active_height);
306
307 /* get the OPTC source */
308 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
245a0221
AC		 309
310 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) {
311 ASSERT(false);
312 return;
313 }
7ed4e635
HW		 314 opp = dc->res_pool->opps[opp_id_src0];
315
316 if (num_opps == 2) {
317 otg_active_width = otg_active_width / 2;
245a0221
AC		 318
319 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) {
320 ASSERT(false);
321 return;
322 }
7ed4e635
HW		 323 bottom_opp = dc->res_pool->opps[opp_id_src1];
324 }
325
326 opp->funcs->opp_set_disp_pattern_generator(
327 opp,
328 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
2057b7e1 329 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
7ed4e635
HW		 330 COLOR_DEPTH_UNDEFINED,
331 &black_color,
332 otg_active_width,
10b4e64e
WL		 333 otg_active_height,
334 0);
7ed4e635
HW		 335
336 if (num_opps == 2) {
337 bottom_opp->funcs->opp_set_disp_pattern_generator(
338 bottom_opp,
339 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
2057b7e1 340 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
7ed4e635
HW		 341 COLOR_DEPTH_UNDEFINED,
342 &black_color,
343 otg_active_width,
10b4e64e
WL		 344 otg_active_height,
345 0);
7ed4e635
HW		 346 }
347
f42ea55b 348 hws->funcs.wait_for_blank_complete(opp);
7ed4e635
HW		 349}
350
78c77382 351void dcn20_dsc_pg_control(
97bda032
HW		 352 struct dce_hwseq *hws,
353 unsigned int dsc_inst,
354 bool power_on)
355{
356 uint32_t power_gate = power_on ? 0 : 1;
357 uint32_t pwr_status = power_on ? 0 : 2;
98ce8cc1 358 uint32_t org_ip_request_cntl = 0;
97bda032
HW		 359
360 if (hws->ctx->dc->debug.disable_dsc_power_gate)
361 return;
362
363 if (REG(DOMAIN16_PG_CONFIG) == 0)
364 return;
365
98ce8cc1
NC		 366 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
367 if (org_ip_request_cntl == 0)
368 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
369
97bda032
HW		 370 switch (dsc_inst) {
371 case 0: /* DSC0 */
372 REG_UPDATE(DOMAIN16_PG_CONFIG,
373 DOMAIN16_POWER_GATE, power_gate);
374
375 REG_WAIT(DOMAIN16_PG_STATUS,
376 DOMAIN16_PGFSM_PWR_STATUS, pwr_status,
377 1, 1000);
378 break;
379 case 1: /* DSC1 */
380 REG_UPDATE(DOMAIN17_PG_CONFIG,
381 DOMAIN17_POWER_GATE, power_gate);
382
383 REG_WAIT(DOMAIN17_PG_STATUS,
384 DOMAIN17_PGFSM_PWR_STATUS, pwr_status,
385 1, 1000);
386 break;
387 case 2: /* DSC2 */
388 REG_UPDATE(DOMAIN18_PG_CONFIG,
389 DOMAIN18_POWER_GATE, power_gate);
390
391 REG_WAIT(DOMAIN18_PG_STATUS,
392 DOMAIN18_PGFSM_PWR_STATUS, pwr_status,
393 1, 1000);
394 break;
395 case 3: /* DSC3 */
396 REG_UPDATE(DOMAIN19_PG_CONFIG,
397 DOMAIN19_POWER_GATE, power_gate);
398
399 REG_WAIT(DOMAIN19_PG_STATUS,
400 DOMAIN19_PGFSM_PWR_STATUS, pwr_status,
401 1, 1000);
402 break;
403 case 4: /* DSC4 */
404 REG_UPDATE(DOMAIN20_PG_CONFIG,
405 DOMAIN20_POWER_GATE, power_gate);
406
407 REG_WAIT(DOMAIN20_PG_STATUS,
408 DOMAIN20_PGFSM_PWR_STATUS, pwr_status,
409 1, 1000);
410 break;
411 case 5: /* DSC5 */
412 REG_UPDATE(DOMAIN21_PG_CONFIG,
413 DOMAIN21_POWER_GATE, power_gate);
414
415 REG_WAIT(DOMAIN21_PG_STATUS,
416 DOMAIN21_PGFSM_PWR_STATUS, pwr_status,
417 1, 1000);
418 break;
419 default:
420 BREAK_TO_DEBUGGER();
421 break;
422 }
98ce8cc1
NC		 423
424 if (org_ip_request_cntl == 0)
425 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
97bda032 426}
7ed4e635 427
78c77382 428void dcn20_dpp_pg_control(
7ed4e635
HW		 429 struct dce_hwseq *hws,
430 unsigned int dpp_inst,
431 bool power_on)
432{
433 uint32_t power_gate = power_on ? 0 : 1;
434 uint32_t pwr_status = power_on ? 0 : 2;
435
436 if (hws->ctx->dc->debug.disable_dpp_power_gate)
437 return;
438 if (REG(DOMAIN1_PG_CONFIG) == 0)
439 return;
440
441 switch (dpp_inst) {
442 case 0: /* DPP0 */
443 REG_UPDATE(DOMAIN1_PG_CONFIG,
444 DOMAIN1_POWER_GATE, power_gate);
445
446 REG_WAIT(DOMAIN1_PG_STATUS,
447 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
448 1, 1000);
449 break;
450 case 1: /* DPP1 */
451 REG_UPDATE(DOMAIN3_PG_CONFIG,
452 DOMAIN3_POWER_GATE, power_gate);
453
454 REG_WAIT(DOMAIN3_PG_STATUS,
455 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
456 1, 1000);
457 break;
458 case 2: /* DPP2 */
459 REG_UPDATE(DOMAIN5_PG_CONFIG,
460 DOMAIN5_POWER_GATE, power_gate);
461
462 REG_WAIT(DOMAIN5_PG_STATUS,
463 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
464 1, 1000);
465 break;
466 case 3: /* DPP3 */
467 REG_UPDATE(DOMAIN7_PG_CONFIG,
468 DOMAIN7_POWER_GATE, power_gate);
469
470 REG_WAIT(DOMAIN7_PG_STATUS,
471 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
472 1, 1000);
473 break;
474 case 4: /* DPP4 */
475 REG_UPDATE(DOMAIN9_PG_CONFIG,
476 DOMAIN9_POWER_GATE, power_gate);
477
478 REG_WAIT(DOMAIN9_PG_STATUS,
479 DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
480 1, 1000);
481 break;
482 case 5: /* DPP5 */
483 /*
484 * Do not power gate DPP5, should be left at HW default, power on permanently.
485 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
486 * reset.
487 * REG_UPDATE(DOMAIN11_PG_CONFIG,
488 * DOMAIN11_POWER_GATE, power_gate);
489 *
490 * REG_WAIT(DOMAIN11_PG_STATUS,
491 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status,
492 * 1, 1000);
493 */
494 break;
495 default:
496 BREAK_TO_DEBUGGER();
497 break;
498 }
499}
500
501
78c77382 502void dcn20_hubp_pg_control(
7ed4e635
HW		 503 struct dce_hwseq *hws,
504 unsigned int hubp_inst,
505 bool power_on)
506{
507 uint32_t power_gate = power_on ? 0 : 1;
508 uint32_t pwr_status = power_on ? 0 : 2;
509
510 if (hws->ctx->dc->debug.disable_hubp_power_gate)
511 return;
512 if (REG(DOMAIN0_PG_CONFIG) == 0)
513 return;
514
515 switch (hubp_inst) {
516 case 0: /* DCHUBP0 */
517 REG_UPDATE(DOMAIN0_PG_CONFIG,
518 DOMAIN0_POWER_GATE, power_gate);
519
520 REG_WAIT(DOMAIN0_PG_STATUS,
521 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
522 1, 1000);
523 break;
524 case 1: /* DCHUBP1 */
525 REG_UPDATE(DOMAIN2_PG_CONFIG,
526 DOMAIN2_POWER_GATE, power_gate);
527
528 REG_WAIT(DOMAIN2_PG_STATUS,
529 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
530 1, 1000);
531 break;
532 case 2: /* DCHUBP2 */
533 REG_UPDATE(DOMAIN4_PG_CONFIG,
534 DOMAIN4_POWER_GATE, power_gate);
535
536 REG_WAIT(DOMAIN4_PG_STATUS,
537 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
538 1, 1000);
539 break;
540 case 3: /* DCHUBP3 */
541 REG_UPDATE(DOMAIN6_PG_CONFIG,
542 DOMAIN6_POWER_GATE, power_gate);
543
544 REG_WAIT(DOMAIN6_PG_STATUS,
545 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
546 1, 1000);
547 break;
548 case 4: /* DCHUBP4 */
549 REG_UPDATE(DOMAIN8_PG_CONFIG,
550 DOMAIN8_POWER_GATE, power_gate);
551
552 REG_WAIT(DOMAIN8_PG_STATUS,
553 DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
554 1, 1000);
555 break;
556 case 5: /* DCHUBP5 */
557 /*
558 * Do not power gate DCHUB5, should be left at HW default, power on permanently.
559 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
560 * reset.
561 * REG_UPDATE(DOMAIN10_PG_CONFIG,
562 * DOMAIN10_POWER_GATE, power_gate);
563 *
564 * REG_WAIT(DOMAIN10_PG_STATUS,
565 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status,
566 * 1, 1000);
567 */
568 break;
569 default:
570 BREAK_TO_DEBUGGER();
571 break;
572 }
573}
574
575
7ed4e635
HW		 576/* disable HW used by plane.
577 * note: cannot disable until disconnect is complete
578 */
78c77382 579void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
7ed4e635 580{
f42ea55b 581 struct dce_hwseq *hws = dc->hwseq;
7ed4e635
HW		 582 struct hubp *hubp = pipe_ctx->plane_res.hubp;
583 struct dpp *dpp = pipe_ctx->plane_res.dpp;
7ed4e635
HW		 584
585 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
586
6bd8d7d3
AC		 587 /* In flip immediate with pipe splitting case GSL is used for
588 * synchronization so we must disable it when the plane is disabled.
589 */
590 if (pipe_ctx->stream_res.gsl_group != 0)
591 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);
592
a5b50a0c
AL		 593 if (hubp->funcs->hubp_update_mall_sel)
594 hubp->funcs->hubp_update_mall_sel(hubp, 0, false);
595
6bd8d7d3
AC		 596 dc->hwss.set_flip_control_gsl(pipe_ctx, false);
597
7ed4e635
HW		 598 hubp->funcs->hubp_clk_cntl(hubp, false);
599
600 dpp->funcs->dpp_dppclk_control(dpp, false, false);
601
7ed4e635 602 hubp->power_gated = true;
7ed4e635 603
f42ea55b 604 hws->funcs.plane_atomic_power_down(dc,
8a31820b
ML		 605 pipe_ctx->plane_res.dpp,
606 pipe_ctx->plane_res.hubp);
7ed4e635
HW		 607
608 pipe_ctx->stream = NULL;
609 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
610 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
611 pipe_ctx->top_pipe = NULL;
612 pipe_ctx->bottom_pipe = NULL;
613 pipe_ctx->plane_state = NULL;
614}
615
616
ff344c8d 617void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
7ed4e635 618{
a5b50a0c
AL		 619 bool is_phantom = pipe_ctx->plane_state && pipe_ctx->plane_state->is_phantom;
620 struct timing_generator *tg = is_phantom ? pipe_ctx->stream_res.tg : NULL;
621
7ed4e635
HW		 622 DC_LOGGER_INIT(dc->ctx->logger);
623
624 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
625 return;
626
627 dcn20_plane_atomic_disable(dc, pipe_ctx);
628
a5b50a0c
AL		 629 /* Turn back off the phantom OTG after the phantom plane is fully disabled
630 */
631 if (is_phantom)
632 if (tg && tg->funcs->disable_phantom_crtc)
633 tg->funcs->disable_phantom_crtc(tg);
634
7ed4e635
HW		 635 DC_LOG_DC("Power down front end %d\n",
636 pipe_ctx->pipe_idx);
637}
638
4866b0bf
ML		 639void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank)
640{
641 dcn20_blank_pixel_data(dc, pipe_ctx, blank);
642}
643
d99f1387
BL		 644static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
645 int opp_cnt)
646{
647 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing);
648 int flow_ctrl_cnt;
649
2665fded 650 if (opp_cnt >= 2)
d99f1387
BL		 651 hblank_halved = true;
652
653 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable -
654 stream->timing.h_border_left -
655 stream->timing.h_border_right;
656
657 if (hblank_halved)
658 flow_ctrl_cnt /= 2;
659
660 /* ODM combine 4:1 case */
661 if (opp_cnt == 4)
662 flow_ctrl_cnt /= 2;
663
664 return flow_ctrl_cnt;
665}
d99f1387 666
7ed4e635
HW		 667enum dc_status dcn20_enable_stream_timing(
668 struct pipe_ctx *pipe_ctx,
669 struct dc_state *context,
670 struct dc *dc)
671{
f42ea55b 672 struct dce_hwseq *hws = dc->hwseq;
7ed4e635 673 struct dc_stream_state *stream = pipe_ctx->stream;
7ed4e635
HW		 674 struct drr_params params = {0};
675 unsigned int event_triggers = 0;
b1f6d01c
DL		 676 struct pipe_ctx *odm_pipe;
677 int opp_cnt = 1;
678 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
d99f1387
BL		 679 bool interlace = stream->timing.flags.INTERLACE;
680 int i;
d99f1387
BL		 681 struct mpc_dwb_flow_control flow_control;
682 struct mpc *mpc = dc->res_pool->mpc;
683 bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing));
49f59499
JL		 684 unsigned int k1_div = PIXEL_RATE_DIV_NA;
685 unsigned int k2_div = PIXEL_RATE_DIV_NA;
d99f1387 686
49f59499
JL		 687 if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {
688 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
689
690 dc->res_pool->dccg->funcs->set_pixel_rate_div(
691 dc->res_pool->dccg,
692 pipe_ctx->stream_res.tg->inst,
693 k1_div, k2_div);
694 }
7ed4e635
HW		 695 /* by upper caller loop, pipe0 is parent pipe and be called first.
696 * back end is set up by for pipe0. Other children pipe share back end
697 * with pipe 0. No program is needed.
698 */
699 if (pipe_ctx->top_pipe != NULL)
700 return DC_OK;
701
702 /* TODO check if timing_changed, disable stream if timing changed */
703
b1f6d01c
DL		 704 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
705 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
706 opp_cnt++;
707 }
2b162fd3 708
b1f6d01c 709 if (opp_cnt > 1)
7ed4e635
HW		 710 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
711 pipe_ctx->stream_res.tg,
b1f6d01c 712 opp_inst, opp_cnt,
2b162fd3 713 &pipe_ctx->stream->timing);
b1f6d01c 714
7ed4e635
HW		 715 /* HW program guide assume display already disable
716 * by unplug sequence. OTG assume stop.
717 */
718 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
719
720 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
721 pipe_ctx->clock_source,
722 &pipe_ctx->stream_res.pix_clk_params,
98ce7d32 723 dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),
7ed4e635
HW		 724 &pipe_ctx->pll_settings)) {
725 BREAK_TO_DEBUGGER();
726 return DC_ERROR_UNEXPECTED;
727 }
728
9c75891f
WL		 729 if (dc_is_hdmi_tmds_signal(stream->signal)) {
730 stream->link->phy_state.symclk_ref_cnts.otg = 1;
731 if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF)
732 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
733 else
734 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
735 }
736
1ef893e2
YS		 737 if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal)))
738 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);
739
7ed4e635
HW		 740 pipe_ctx->stream_res.tg->funcs->program_timing(
741 pipe_ctx->stream_res.tg,
742 &stream->timing,
743 pipe_ctx->pipe_dlg_param.vready_offset,
744 pipe_ctx->pipe_dlg_param.vstartup_start,
745 pipe_ctx->pipe_dlg_param.vupdate_offset,
746 pipe_ctx->pipe_dlg_param.vupdate_width,
747 pipe_ctx->stream->signal,
748 true);
749
d99f1387
BL		 750 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1;
751 flow_control.flow_ctrl_mode = 0;
752 flow_control.flow_ctrl_cnt0 = 0x80;
753 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt);
754 if (mpc->funcs->set_out_rate_control) {
755 for (i = 0; i < opp_cnt; ++i) {
756 mpc->funcs->set_out_rate_control(
757 mpc, opp_inst[i],
758 true,
759 rate_control_2x_pclk,
760 &flow_control);
761 }
762 }
20f2ffe5 763
b1f6d01c 764 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
7ed4e635
HW		 765 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
766 odm_pipe->stream_res.opp,
767 true);
768
7ed4e635
HW		 769 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
770 pipe_ctx->stream_res.opp,
771 true);
772
f42ea55b 773 hws->funcs.blank_pixel_data(dc, pipe_ctx, true);
7ed4e635
HW		 774
775 /* VTG is within DCHUB command block. DCFCLK is always on */
776 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
777 BREAK_TO_DEBUGGER();
778 return DC_ERROR_UNEXPECTED;
779 }
780
f42ea55b 781 hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp);
7ed4e635
HW		 782
783 params.vertical_total_min = stream->adjust.v_total_min;
784 params.vertical_total_max = stream->adjust.v_total_max;
470e2ca5
BZ		 785 params.vertical_total_mid = stream->adjust.v_total_mid;
786 params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num;
7ed4e635
HW		 787 if (pipe_ctx->stream_res.tg->funcs->set_drr)
788 pipe_ctx->stream_res.tg->funcs->set_drr(
789 pipe_ctx->stream_res.tg, &params);
790
791 // DRR should set trigger event to monitor surface update event
792 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
793 event_triggers = 0x80;
5b5abe95
AK		 794 /* Event triggers and num frames initialized for DRR, but can be
795 * later updated for PSR use. Note DRR trigger events are generated
796 * regardless of whether num frames met.
797 */
7ed4e635
HW		 798 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
799 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
5b5abe95 800 pipe_ctx->stream_res.tg, event_triggers, 2);
7ed4e635
HW		 801
802 /* TODO program crtc source select for non-virtual signal*/
803 /* TODO program FMT */
804 /* TODO setup link_enc */
805 /* TODO set stream attributes */
806 /* TODO program audio */
807 /* TODO enable stream if timing changed */
808 /* TODO unblank stream if DP */
809
d3dfceb5
AP		 810 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) {
811 if (pipe_ctx->stream_res.tg && pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable)
812 pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg);
813 }
7ed4e635
HW		 814 return DC_OK;
815}
816
817void dcn20_program_output_csc(struct dc *dc,
818 struct pipe_ctx *pipe_ctx,
819 enum dc_color_space colorspace,
820 uint16_t *matrix,
821 int opp_id)
822{
823 struct mpc *mpc = dc->res_pool->mpc;
824 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
54461859
CL		 825 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
826
827 if (mpc->funcs->power_on_mpc_mem_pwr)
828 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
7ed4e635
HW		 829
830 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
831 if (mpc->funcs->set_output_csc != NULL)
832 mpc->funcs->set_output_csc(mpc,
833 opp_id,
834 matrix,
835 ocsc_mode);
836 } else {
837 if (mpc->funcs->set_ocsc_default != NULL)
838 mpc->funcs->set_ocsc_default(mpc,
839 opp_id,
840 colorspace,
841 ocsc_mode);
842 }
843}
844
78c77382 845bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
7ed4e635
HW		 846 const struct dc_stream_state *stream)
847{
848 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
849 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
850 struct pwl_params *params = NULL;
851 /*
852 * program OGAM only for the top pipe
853 * if there is a pipe split then fix diagnostic is required:
854 * how to pass OGAM parameter for stream.
855 * if programming for all pipes is required then remove condition
856 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic.
857 */
54461859
CL		 858 if (mpc->funcs->power_on_mpc_mem_pwr)
859 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
b1f6d01c 860 if (pipe_ctx->top_pipe == NULL
7ed4e635
HW		 861 && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
862 if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
863 params = &stream->out_transfer_func->pwl;
864 else if (pipe_ctx->stream->out_transfer_func->type ==
865 TF_TYPE_DISTRIBUTED_POINTS &&
866 cm_helper_translate_curve_to_hw_format(
867 stream->out_transfer_func,
868 &mpc->blender_params, false))
869 params = &mpc->blender_params;
870 /*
871 * there is no ROM
872 */
873 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
874 BREAK_TO_DEBUGGER();
875 }
876 /*
877 * if above if is not executed then 'params' equal to 0 and set in bypass
878 */
879 mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
880
881 return true;
882}
883
ff344c8d 884bool dcn20_set_blend_lut(
7ed4e635
HW		 885 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
886{
887 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
888 bool result = true;
889 struct pwl_params *blend_lut = NULL;
890
891 if (plane_state->blend_tf) {
892 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
893 blend_lut = &plane_state->blend_tf->pwl;
894 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
895 cm_helper_translate_curve_to_hw_format(
896 plane_state->blend_tf,
897 &dpp_base->regamma_params, false);
898 blend_lut = &dpp_base->regamma_params;
899 }
900 }
901 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
902
903 return result;
904}
905
ff344c8d 906bool dcn20_set_shaper_3dlut(
7ed4e635
HW		 907 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
908{
909 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
910 bool result = true;
911 struct pwl_params *shaper_lut = NULL;
912
913 if (plane_state->in_shaper_func) {
914 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
915 shaper_lut = &plane_state->in_shaper_func->pwl;
916 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
917 cm_helper_translate_curve_to_hw_format(
918 plane_state->in_shaper_func,
919 &dpp_base->shaper_params, true);
920 shaper_lut = &dpp_base->shaper_params;
921 }
922 }
923
924 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut);
925 if (plane_state->lut3d_func &&
a2080098 926 plane_state->lut3d_func->state.bits.initialized == 1)
7ed4e635
HW		 927 result = dpp_base->funcs->dpp_program_3dlut(dpp_base,
928 &plane_state->lut3d_func->lut_3d);
929 else
930 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL);
931
7ed4e635
HW		 932 return result;
933}
934
78c77382
AK		 935bool dcn20_set_input_transfer_func(struct dc *dc,
936 struct pipe_ctx *pipe_ctx,
937 const struct dc_plane_state *plane_state)
7ed4e635 938{
f42ea55b 939 struct dce_hwseq *hws = dc->hwseq;
7ed4e635
HW		 940 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
941 const struct dc_transfer_func *tf = NULL;
942 bool result = true;
943 bool use_degamma_ram = false;
944
945 if (dpp_base == NULL || plane_state == NULL)
946 return false;
947
f42ea55b
AK		 948 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
949 hws->funcs.set_blend_lut(pipe_ctx, plane_state);
7ed4e635
HW		 950
951 if (plane_state->in_transfer_func)
952 tf = plane_state->in_transfer_func;
953
954
955 if (tf == NULL) {
956 dpp_base->funcs->dpp_set_degamma(dpp_base,
957 IPP_DEGAMMA_MODE_BYPASS);
958 return true;
959 }
960
961 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS)
962 use_degamma_ram = true;
963
964 if (use_degamma_ram == true) {
965 if (tf->type == TF_TYPE_HWPWL)
966 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
967 &tf->pwl);
968 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
969 cm_helper_translate_curve_to_degamma_hw_format(tf,
970 &dpp_base->degamma_params);
971 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
972 &dpp_base->degamma_params);
973 }
974 return true;
975 }
976 /* handle here the optimized cases when de-gamma ROM could be used.
977 *
978 */
979 if (tf->type == TF_TYPE_PREDEFINED) {
980 switch (tf->tf) {
981 case TRANSFER_FUNCTION_SRGB:
982 dpp_base->funcs->dpp_set_degamma(dpp_base,
983 IPP_DEGAMMA_MODE_HW_sRGB);
984 break;
985 case TRANSFER_FUNCTION_BT709:
986 dpp_base->funcs->dpp_set_degamma(dpp_base,
987 IPP_DEGAMMA_MODE_HW_xvYCC);
988 break;
989 case TRANSFER_FUNCTION_LINEAR:
990 dpp_base->funcs->dpp_set_degamma(dpp_base,
991 IPP_DEGAMMA_MODE_BYPASS);
992 break;
993 case TRANSFER_FUNCTION_PQ:
e6616410
RA		 994 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL);
995 cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params);
996 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params);
997 result = true;
998 break;
7ed4e635
HW		 999 default:
1000 result = false;
1001 break;
1002 }
1003 } else if (tf->type == TF_TYPE_BYPASS)
1004 dpp_base->funcs->dpp_set_degamma(dpp_base,
1005 IPP_DEGAMMA_MODE_BYPASS);
1006 else {
1007 /*
1008 * if we are here, we did not handle correctly.
1009 * fix is required for this use case
1010 */
1011 BREAK_TO_DEBUGGER();
1012 dpp_base->funcs->dpp_set_degamma(dpp_base,
1013 IPP_DEGAMMA_MODE_BYPASS);
1014 }
1015
1016 return result;
1017}
1018
78c77382 1019void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
7ed4e635 1020{
b1f6d01c
DL		 1021 struct pipe_ctx *odm_pipe;
1022 int opp_cnt = 1;
1023 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
7ed4e635 1024
b1f6d01c
DL		 1025 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1026 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
1027 opp_cnt++;
1028 }
2b162fd3 1029
b1f6d01c 1030 if (opp_cnt > 1)
7ed4e635
HW		 1031 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
1032 pipe_ctx->stream_res.tg,
b1f6d01c 1033 opp_inst, opp_cnt,
2b162fd3 1034 &pipe_ctx->stream->timing);
b1f6d01c 1035 else
7ed4e635
HW		 1036 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
1037 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1038}
1039
1040void dcn20_blank_pixel_data(
1041 struct dc *dc,
1042 struct pipe_ctx *pipe_ctx,
1043 bool blank)
1044{
7ed4e635
HW		 1045 struct tg_color black_color = {0};
1046 struct stream_resource *stream_res = &pipe_ctx->stream_res;
1047 struct dc_stream_state *stream = pipe_ctx->stream;
324707fd 1048 enum dc_color_space color_space = stream->output_color_space;
7ed4e635 1049 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
2057b7e1 1050 enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
b1f6d01c
DL		 1051 struct pipe_ctx *odm_pipe;
1052 int odm_cnt = 1;
7ed4e635 1053
7ed4e635
HW		 1054 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
1055 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
1056
31635887
WL		 1057 if (stream->link->test_pattern_enabled)
1058 return;
1059
324707fd 1060 /* get opp dpg blank color */
7ed4e635
HW		 1061 color_space_to_black_color(dc, color_space, &black_color);
1062
b1f6d01c
DL		 1063 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1064 odm_cnt++;
1065
1066 width = width / odm_cnt;
7ed4e635
HW		 1067
1068 if (blank) {
3ba01817 1069 dc->hwss.set_abm_immediate_disable(pipe_ctx);
7ed4e635 1070
2057b7e1 1071 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {
324707fd 1072 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
2057b7e1
WL		 1073 test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
1074 }
324707fd
JA		 1075 } else {
1076 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
1077 }
7ed4e635 1078
dbf5256b
JA		 1079 dc->hwss.set_disp_pattern_generator(dc,
1080 pipe_ctx,
7ed4e635 1081 test_pattern,
2057b7e1 1082 test_pattern_color_space,
7ed4e635
HW		 1083 stream->timing.display_color_depth,
1084 &black_color,
1085 width,
10b4e64e
WL		 1086 height,
1087 0);
7ed4e635 1088
b1f6d01c 1089 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
dbf5256b
JA		 1090 dc->hwss.set_disp_pattern_generator(dc,
1091 odm_pipe,
436d9635 1092 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ?
324707fd 1093 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
2057b7e1 1094 test_pattern_color_space,
7ed4e635
HW		 1095 stream->timing.display_color_depth,
1096 &black_color,
1097 width,
10b4e64e
WL		 1098 height,
1099 0);
7ed4e635
HW		 1100 }
1101
7fbf451e
DV		 1102 if (!blank && dc->debug.enable_single_display_2to1_odm_policy) {
1103 /* when exiting dynamic ODM need to reinit DPG state for unused pipes */
1104 struct pipe_ctx *old_odm_pipe = dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx].next_odm_pipe;
1105
1106 odm_pipe = pipe_ctx->next_odm_pipe;
1107
1108 while (old_odm_pipe) {
1109 if (!odm_pipe || old_odm_pipe->pipe_idx != odm_pipe->pipe_idx)
1110 dc->hwss.set_disp_pattern_generator(dc,
1111 old_odm_pipe,
1112 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
1113 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
1114 COLOR_DEPTH_888,
1115 NULL,
1116 0,
1117 0,
1118 0);
1119 old_odm_pipe = old_odm_pipe->next_odm_pipe;
1120 if (odm_pipe)
1121 odm_pipe = odm_pipe->next_odm_pipe;
1122 }
1123 }
1124
7ed4e635
HW		 1125 if (!blank)
1126 if (stream_res->abm) {
474ac4a8 1127 dc->hwss.set_pipe(pipe_ctx);
7ed4e635
HW		 1128 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
1129 }
1130}
1131
1132
bf224e00 1133static void dcn20_power_on_plane_resources(
7ed4e635
HW		 1134 struct dce_hwseq *hws,
1135 struct pipe_ctx *pipe_ctx)
1136{
1137 DC_LOGGER_INIT(hws->ctx->logger);
bf224e00
NK		 1138
1139 if (hws->funcs.dpp_root_clock_control)
1140 hws->funcs.dpp_root_clock_control(hws, pipe_ctx->plane_res.dpp->inst, true);
1141
7ed4e635
HW		 1142 if (REG(DC_IP_REQUEST_CNTL)) {
1143 REG_SET(DC_IP_REQUEST_CNTL, 0,
1144 IP_REQUEST_EN, 1);
c74f865f
NK		 1145
1146 if (hws->funcs.dpp_pg_control)
1147 hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);
1148
1149 if (hws->funcs.hubp_pg_control)
1150 hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);
1151
7ed4e635
HW		 1152 REG_SET(DC_IP_REQUEST_CNTL, 0,
1153 IP_REQUEST_EN, 0);
1154 DC_LOG_DEBUG(
1155 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);
1156 }
1157}
1158
240e6d25
IB		 1159static void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,
1160 struct dc_state *context)
7ed4e635
HW		 1161{
1162 //if (dc->debug.sanity_checks) {
1163 // dcn10_verify_allow_pstate_change_high(dc);
1164 //}
bf224e00 1165 dcn20_power_on_plane_resources(dc->hwseq, pipe_ctx);
7ed4e635
HW		 1166
1167 /* enable DCFCLK current DCHUB */
1168 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1169
89cb5614
ZYL		 1170 /* initialize HUBP on power up */
1171 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);
1172
7ed4e635
HW		 1173 /* make sure OPP_PIPE_CLOCK_EN = 1 */
1174 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1175 pipe_ctx->stream_res.opp,
1176 true);
1177
1178/* TODO: enable/disable in dm as per update type.
1179 if (plane_state) {
1180 DC_LOG_DC(dc->ctx->logger,
1181 "Pipe:%d 0x%x: addr hi:0x%x, "
1182 "addr low:0x%x, "
1183 "src: %d, %d, %d,"
1184 " %d; dst: %d, %d, %d, %d;\n",
1185 pipe_ctx->pipe_idx,
1186 plane_state,
1187 plane_state->address.grph.addr.high_part,
1188 plane_state->address.grph.addr.low_part,
1189 plane_state->src_rect.x,
1190 plane_state->src_rect.y,
1191 plane_state->src_rect.width,
1192 plane_state->src_rect.height,
1193 plane_state->dst_rect.x,
1194 plane_state->dst_rect.y,
1195 plane_state->dst_rect.width,
1196 plane_state->dst_rect.height);
1197
1198 DC_LOG_DC(dc->ctx->logger,
1199 "Pipe %d: width, height, x, y format:%d\n"
1200 "viewport:%d, %d, %d, %d\n"
1201 "recout: %d, %d, %d, %d\n",
1202 pipe_ctx->pipe_idx,
1203 plane_state->format,
1204 pipe_ctx->plane_res.scl_data.viewport.width,
1205 pipe_ctx->plane_res.scl_data.viewport.height,
1206 pipe_ctx->plane_res.scl_data.viewport.x,
1207 pipe_ctx->plane_res.scl_data.viewport.y,
1208 pipe_ctx->plane_res.scl_data.recout.width,
1209 pipe_ctx->plane_res.scl_data.recout.height,
1210 pipe_ctx->plane_res.scl_data.recout.x,
1211 pipe_ctx->plane_res.scl_data.recout.y);
1212 print_rq_dlg_ttu(dc, pipe_ctx);
1213 }
1214*/
bda9afda 1215 if (dc->vm_pa_config.valid) {
7ed4e635
HW		 1216 struct vm_system_aperture_param apt;
1217
1218 apt.sys_default.quad_part = 0;
7ed4e635 1219
6d988a55
JL		 1220 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr;
1221 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr;
7ed4e635
HW		 1222
1223 // Program system aperture settings
1224 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);
1225 }
1226
0c66824b
QZ		 1227 if (!pipe_ctx->top_pipe
1228 && pipe_ctx->plane_state
1229 && pipe_ctx->plane_state->flip_int_enabled
1230 && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)
1231 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);
1232
7ed4e635
HW		 1233// if (dc->debug.sanity_checks) {
1234// dcn10_verify_allow_pstate_change_high(dc);
1235// }
1236}
1237
ff344c8d 1238void dcn20_pipe_control_lock(
7ed4e635
HW		 1239 struct dc *dc,
1240 struct pipe_ctx *pipe,
1241 bool lock)
1242{
6f2239cc 1243 struct pipe_ctx *temp_pipe;
7ed4e635
HW		 1244 bool flip_immediate = false;
1245
1246 /* use TG master update lock to lock everything on the TG
1247 * therefore only top pipe need to lock
1248 */
009114f6 1249 if (!pipe || pipe->top_pipe)
7ed4e635
HW		 1250 return;
1251
1252 if (pipe->plane_state != NULL)
1253 flip_immediate = pipe->plane_state->flip_immediate;
1254
4f6274b3
AL		 1255 if (pipe->stream_res.gsl_group > 0) {
1256 temp_pipe = pipe->bottom_pipe;
1257 while (!flip_immediate && temp_pipe) {
1258 if (temp_pipe->plane_state != NULL)
1259 flip_immediate = temp_pipe->plane_state->flip_immediate;
1260 temp_pipe = temp_pipe->bottom_pipe;
1261 }
6f2239cc
AL		 1262 }
1263
0e29be9e
AD		 1264 if (flip_immediate && lock) {
1265 const int TIMEOUT_FOR_FLIP_PENDING = 100000;
1266 int i;
1267
e9917ef8
AC		 1268 temp_pipe = pipe;
1269 while (temp_pipe) {
1270 if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) {
1271 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
1272 if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp))
1273 break;
1274 udelay(1);
1275 }
1276
1277 /* no reason it should take this long for immediate flips */
1278 ASSERT(i != TIMEOUT_FOR_FLIP_PENDING);
0e29be9e 1279 }
e9917ef8 1280 temp_pipe = temp_pipe->bottom_pipe;
0e29be9e
AD		 1281 }
1282 }
1283
7ed4e635
HW		 1284 /* In flip immediate and pipe splitting case, we need to use GSL
1285 * for synchronization. Only do setup on locking and on flip type change.
1286 */
86c5a9e3 1287 if (lock && (pipe->bottom_pipe != NULL || !flip_immediate))
7ed4e635
HW		 1288 if ((flip_immediate && pipe->stream_res.gsl_group == 0) ||
1289 (!flip_immediate && pipe->stream_res.gsl_group > 0))
2e2e73fc 1290 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
7ed4e635 1291
ec76bd6f
AL		 1292 if (pipe->plane_state != NULL)
1293 flip_immediate = pipe->plane_state->flip_immediate;
1294
6f2239cc
AL		 1295 temp_pipe = pipe->bottom_pipe;
1296 while (flip_immediate && temp_pipe) {
1297 if (temp_pipe->plane_state != NULL)
1298 flip_immediate = temp_pipe->plane_state->flip_immediate;
1299 temp_pipe = temp_pipe->bottom_pipe;
1300 }
1301
1302 if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state &&
1303 !flip_immediate)
1304 dcn20_setup_gsl_group_as_lock(dc, pipe, false);
1305
dc6e2448
WW		 1306 if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) {
1307 union dmub_hw_lock_flags hw_locks = { 0 };
1308 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
1309
1310 hw_locks.bits.lock_pipe = 1;
1311 inst_flags.otg_inst = pipe->stream_res.tg->inst;
1312
1313 if (pipe->plane_state != NULL)
1314 hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips;
1315
1316 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
1317 lock,
1318 &hw_locks,
1319 &inst_flags);
1320 } else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {
7ed4e635
HW		 1321 if (lock)
1322 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);
1323 else
1324 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg);
1325 } else {
1326 if (lock)
1327 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1328 else
1329 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1330 }
1331}
1332
b6e881c9 1333static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe)
7ed4e635 1334{
b6e881c9 1335 new_pipe->update_flags.raw = 0;
7ed4e635 1336
e267f5e6
AL		 1337 /* If non-phantom pipe is being transitioned to a phantom pipe,
1338 * set disable and return immediately. This is because the pipe
1339 * that was previously in use must be fully disabled before we
1340 * can "enable" it as a phantom pipe (since the OTG will certainly
1341 * be different). The post_unlock sequence will set the correct
1342 * update flags to enable the phantom pipe.
1343 */
1344 if (old_pipe->plane_state && !old_pipe->plane_state->is_phantom &&
1345 new_pipe->plane_state && new_pipe->plane_state->is_phantom) {
1346 new_pipe->update_flags.bits.disable = 1;
1347 return;
1348 }
1349
b6e881c9
DL		 1350 /* Exit on unchanged, unused pipe */
1351 if (!old_pipe->plane_state && !new_pipe->plane_state)
7ed4e635 1352 return;
b6e881c9 1353 /* Detect pipe enable/disable */
c0838cbe 1354 if (!old_pipe->plane_state && new_pipe->plane_state) {
b6e881c9
DL		 1355 new_pipe->update_flags.bits.enable = 1;
1356 new_pipe->update_flags.bits.mpcc = 1;
1357 new_pipe->update_flags.bits.dppclk = 1;
1358 new_pipe->update_flags.bits.hubp_interdependent = 1;
1359 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1360 new_pipe->update_flags.bits.gamut_remap = 1;
1361 new_pipe->update_flags.bits.scaler = 1;
1362 new_pipe->update_flags.bits.viewport = 1;
ba5a5371 1363 new_pipe->update_flags.bits.det_size = 1;
b6e881c9
DL		 1364 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1365 new_pipe->update_flags.bits.odm = 1;
1366 new_pipe->update_flags.bits.global_sync = 1;
1367 }
1368 return;
1369 }
85f4bc0c
AL		 1370
1371 /* For SubVP we need to unconditionally enable because any phantom pipes are
1372 * always removed then newly added for every full updates whenever SubVP is in use.
1373 * The remove-add sequence of the phantom pipe always results in the pipe
1374 * being blanked in enable_stream_timing (DPG).
1375 */
1376 if (new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM)
1377 new_pipe->update_flags.bits.enable = 1;
1378
14eb72ff
AL		 1379 /* Phantom pipes are effectively disabled, if the pipe was previously phantom
1380 * we have to enable
1381 */
1382 if (old_pipe->plane_state && old_pipe->plane_state->is_phantom &&
1383 new_pipe->plane_state && !new_pipe->plane_state->is_phantom)
1384 new_pipe->update_flags.bits.enable = 1;
1385
b6e881c9
DL		 1386 if (old_pipe->plane_state && !new_pipe->plane_state) {
1387 new_pipe->update_flags.bits.disable = 1;
1388 return;
1389 }
7ed4e635 1390
498563cf
JX		 1391 /* Detect plane change */
1392 if (old_pipe->plane_state != new_pipe->plane_state) {
1393 new_pipe->update_flags.bits.plane_changed = true;
1394 }
1395
b6e881c9
DL		 1396 /* Detect top pipe only changes */
1397 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1398 /* Detect odm changes */
1399 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe
1400 && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx)
1401 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe)
1402 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe)
1403 || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1404 new_pipe->update_flags.bits.odm = 1;
1405
1406 /* Detect global sync changes */
1407 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset
1408 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start
1409 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset
1410 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width)
1411 new_pipe->update_flags.bits.global_sync = 1;
1412 }
21ffcc94 1413
ba5a5371
NK		 1414 if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb)
1415 new_pipe->update_flags.bits.det_size = 1;
8fe44c08 1416
b6e881c9
DL		 1417 /*
1418 * Detect opp / tg change, only set on change, not on enable
1419 * Assume mpcc inst = pipe index, if not this code needs to be updated
1420 * since mpcc is what is affected by these. In fact all of our sequence
1421 * makes this assumption at the moment with how hubp reset is matched to
1422 * same index mpcc reset.
1423 */
1424 if (old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1425 new_pipe->update_flags.bits.opp_changed = 1;
1426 if (old_pipe->stream_res.tg != new_pipe->stream_res.tg)
1427 new_pipe->update_flags.bits.tg_changed = 1;
1428
ed8ec123
DL		 1429 /*
1430 * Detect mpcc blending changes, only dpp inst and opp matter here,
1431 * mpccs getting removed/inserted update connected ones during their own
1432 * programming
1433 */
b6e881c9 1434 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp
ed8ec123 1435 || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
b6e881c9
DL		 1436 new_pipe->update_flags.bits.mpcc = 1;
1437
1438 /* Detect dppclk change */
1439 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz)
1440 new_pipe->update_flags.bits.dppclk = 1;
1441
1442 /* Check for scl update */
1443 if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data)))
1444 new_pipe->update_flags.bits.scaler = 1;
1445 /* Check for vp update */
1446 if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect))
1447 || memcmp(&old_pipe->plane_res.scl_data.viewport_c,
1448 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect)))
1449 new_pipe->update_flags.bits.viewport = 1;
1450
1451 /* Detect dlg/ttu/rq updates */
1452 {
1453 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs;
1454 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs;
1455 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs;
1456 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs;
1457
1458 /* Detect pipe interdependent updates */
1459 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch ||
1460 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch ||
1461 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c ||
1462 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank ||
1463 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank ||
1464 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip ||
1465 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip ||
1466 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l ||
1467 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c ||
1468 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l ||
1469 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l ||
1470 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c ||
1471 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l ||
1472 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c ||
1473 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 ||
1474 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 ||
1475 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank ||
1476 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) {
1477 old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch;
1478 old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch;
1479 old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c;
1480 old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank;
1481 old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank;
1482 old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip;
1483 old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip;
1484 old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l;
1485 old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c;
1486 old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l;
1487 old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l;
1488 old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c;
1489 old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l;
1490 old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c;
1491 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0;
1492 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1;
1493 old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank;
1494 old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip;
1495 new_pipe->update_flags.bits.hubp_interdependent = 1;
1496 }
1497 /* Detect any other updates to ttu/rq/dlg */
1498 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) ||
1499 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) ||
1500 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs)))
1501 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
21ffcc94 1502 }
b6e881c9 1503}
21ffcc94 1504
b6e881c9
DL		 1505static void dcn20_update_dchubp_dpp(
1506 struct dc *dc,
1507 struct pipe_ctx *pipe_ctx,
1508 struct dc_state *context)
1509{
f42ea55b 1510 struct dce_hwseq *hws = dc->hwseq;
b6e881c9
DL		 1511 struct hubp *hubp = pipe_ctx->plane_res.hubp;
1512 struct dpp *dpp = pipe_ctx->plane_res.dpp;
1513 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
d4965c53 1514 struct dccg *dccg = dc->res_pool->dccg;
cf27a6d1 1515 bool viewport_changed = false;
7ed4e635 1516
1ea8751b 1517 if (pipe_ctx->update_flags.bits.dppclk)
b6e881c9 1518 dpp->funcs->dpp_dppclk_control(dpp, false, true);
4e0cbbbf 1519
d4965c53
DM		 1520 if (pipe_ctx->update_flags.bits.enable)
1521 dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);
1522
b6e881c9
DL		 1523 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
1524 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
1525 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
1526 */
1527 if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) {
1528 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
1529
1530 hubp->funcs->hubp_setup(
1531 hubp,
1532 &pipe_ctx->dlg_regs,
1533 &pipe_ctx->ttu_regs,
1534 &pipe_ctx->rq_regs,
1535 &pipe_ctx->pipe_dlg_param);
8fe44c08 1536
ba5a5371
NK		 1537 if (hubp->funcs->set_unbounded_requesting)
1538 hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req);
b6e881c9
DL		 1539 }
1540 if (pipe_ctx->update_flags.bits.hubp_interdependent)
1541 hubp->funcs->hubp_setup_interdependent(
1542 hubp,
1543 &pipe_ctx->dlg_regs,
1544 &pipe_ctx->ttu_regs);
1545
1546 if (pipe_ctx->update_flags.bits.enable ||
498563cf 1547 pipe_ctx->update_flags.bits.plane_changed ||
b6e881c9
DL		 1548 plane_state->update_flags.bits.bpp_change ||
1549 plane_state->update_flags.bits.input_csc_change ||
1550 plane_state->update_flags.bits.color_space_change ||
1551 plane_state->update_flags.bits.coeff_reduction_change) {
1552 struct dc_bias_and_scale bns_params = {0};
1553
1554 // program the input csc
1555 dpp->funcs->dpp_setup(dpp,
1556 plane_state->format,
1557 EXPANSION_MODE_ZERO,
1558 plane_state->input_csc_color_matrix,
1559 plane_state->color_space,
1560 NULL);
1561
1562 if (dpp->funcs->dpp_program_bias_and_scale) {
1563 //TODO :for CNVC set scale and bias registers if necessary
78c77382 1564 build_prescale_params(&bns_params, plane_state);
b6e881c9
DL		 1565 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1566 }
7ed4e635
HW		 1567 }
1568
b6e881c9 1569 if (pipe_ctx->update_flags.bits.mpcc
498563cf 1570 || pipe_ctx->update_flags.bits.plane_changed
b6e881c9
DL		 1571 || plane_state->update_flags.bits.global_alpha_change
1572 || plane_state->update_flags.bits.per_pixel_alpha_change) {
8b0fbb36 1573 // MPCC inst is equal to pipe index in practice
1380c1bf 1574 int mpcc_inst = hubp->inst;
8b0fbb36 1575 int opp_inst;
0120e8b8 1576 int opp_count = dc->res_pool->pipe_count;
8b0fbb36
NA		 1577
1578 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
1579 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
b6e881c9 1580 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
8b0fbb36
NA		 1581 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
1582 break;
b6e881c9 1583 }
7ed4e635 1584 }
f42ea55b 1585 hws->funcs.update_mpcc(dc, pipe_ctx);
b6e881c9 1586 }
7ed4e635 1587
b6e881c9
DL		 1588 if (pipe_ctx->update_flags.bits.scaler ||
1589 plane_state->update_flags.bits.scaling_change ||
1590 plane_state->update_flags.bits.position_change ||
1591 plane_state->update_flags.bits.per_pixel_alpha_change ||
1592 pipe_ctx->stream->update_flags.bits.scaling) {
1593 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;
a316db72 1594 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP);
b6e881c9
DL		 1595 /* scaler configuration */
1596 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
1597 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
1598 }
7ed4e635 1599
b6e881c9 1600 if (pipe_ctx->update_flags.bits.viewport ||
b34659de 1601 (context == dc->current_state && plane_state->update_flags.bits.position_change) ||
b6e881c9 1602 (context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||
cf27a6d1
EY		 1603 (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {
1604
b6e881c9
DL		 1605 hubp->funcs->mem_program_viewport(
1606 hubp,
1607 &pipe_ctx->plane_res.scl_data.viewport,
cf27a6d1
EY		 1608 &pipe_ctx->plane_res.scl_data.viewport_c);
1609 viewport_changed = true;
1610 }
b6e881c9
DL		 1611
1612 /* Any updates are handled in dc interface, just need to apply existing for plane enable */
74cc5f02 1613 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||
8e80d482
PH		 1614 pipe_ctx->update_flags.bits.scaler || viewport_changed == true) &&
1615 pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
b6e881c9
DL		 1616 dc->hwss.set_cursor_position(pipe_ctx);
1617 dc->hwss.set_cursor_attribute(pipe_ctx);
1618
1619 if (dc->hwss.set_cursor_sdr_white_level)
1620 dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
1621 }
7ed4e635 1622
b6e881c9
DL		 1623 /* Any updates are handled in dc interface, just need
1624 * to apply existing for plane enable / opp change */
1625 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed
441595ba 1626 || pipe_ctx->update_flags.bits.plane_changed
b6e881c9
DL		 1627 || pipe_ctx->stream->update_flags.bits.gamut_remap
1628 || pipe_ctx->stream->update_flags.bits.out_csc) {
90d1a626
DV		 1629 /* dpp/cm gamut remap*/
1630 dc->hwss.program_gamut_remap(pipe_ctx);
b6e881c9
DL		 1631
1632 /*call the dcn2 method which uses mpc csc*/
1633 dc->hwss.program_output_csc(dc,
1634 pipe_ctx,
1635 pipe_ctx->stream->output_color_space,
1636 pipe_ctx->stream->csc_color_matrix.matrix,
1637 hubp->opp_id);
7ed4e635
HW		 1638 }
1639
b6e881c9 1640 if (pipe_ctx->update_flags.bits.enable ||
498563cf 1641 pipe_ctx->update_flags.bits.plane_changed ||
b6e881c9
DL		 1642 pipe_ctx->update_flags.bits.opp_changed ||
1643 plane_state->update_flags.bits.pixel_format_change ||
1644 plane_state->update_flags.bits.horizontal_mirror_change ||
1645 plane_state->update_flags.bits.rotation_change ||
1646 plane_state->update_flags.bits.swizzle_change ||
1647 plane_state->update_flags.bits.dcc_change ||
1648 plane_state->update_flags.bits.bpp_change ||
1649 plane_state->update_flags.bits.scaling_change ||
1650 plane_state->update_flags.bits.plane_size_change) {
1651 struct plane_size size = plane_state->plane_size;
1652
1653 size.surface_size = pipe_ctx->plane_res.scl_data.viewport;
1654 hubp->funcs->hubp_program_surface_config(
1655 hubp,
1656 plane_state->format,
1657 &plane_state->tiling_info,
1658 &size,
1659 plane_state->rotation,
1660 &plane_state->dcc,
1661 plane_state->horizontal_mirror,
1662 0);
1663 hubp->power_gated = false;
1664 }
1665
498563cf
JX		 1666 if (pipe_ctx->update_flags.bits.enable ||
1667 pipe_ctx->update_flags.bits.plane_changed ||
1668 plane_state->update_flags.bits.addr_update)
f42ea55b 1669 hws->funcs.update_plane_addr(dc, pipe_ctx);
b6e881c9 1670
e7a30ade 1671 if (pipe_ctx->update_flags.bits.enable)
0b7421f0 1672 hubp->funcs->set_blank(hubp, false);
d3dfceb5
AP		 1673 /* If the stream paired with this plane is phantom, the plane is also phantom */
1674 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM
1675 && hubp->funcs->phantom_hubp_post_enable)
1676 hubp->funcs->phantom_hubp_post_enable(hubp);
b6e881c9
DL		 1677}
1678
5842abd9
WC		 1679static int calculate_vready_offset_for_group(struct pipe_ctx *pipe)
1680{
1681 struct pipe_ctx *other_pipe;
1682 int vready_offset = pipe->pipe_dlg_param.vready_offset;
1683
1684 /* Always use the largest vready_offset of all connected pipes */
1685 for (other_pipe = pipe->bottom_pipe; other_pipe != NULL; other_pipe = other_pipe->bottom_pipe) {
1686 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset)
1687 vready_offset = other_pipe->pipe_dlg_param.vready_offset;
1688 }
1689 for (other_pipe = pipe->top_pipe; other_pipe != NULL; other_pipe = other_pipe->top_pipe) {
1690 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset)
1691 vready_offset = other_pipe->pipe_dlg_param.vready_offset;
1692 }
1693 for (other_pipe = pipe->next_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->next_odm_pipe) {
1694 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset)
1695 vready_offset = other_pipe->pipe_dlg_param.vready_offset;
1696 }
1697 for (other_pipe = pipe->prev_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->prev_odm_pipe) {
1698 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset)
1699 vready_offset = other_pipe->pipe_dlg_param.vready_offset;
1700 }
1701
1702 return vready_offset;
1703}
b6e881c9
DL		 1704
1705static void dcn20_program_pipe(
1706 struct dc *dc,
1707 struct pipe_ctx *pipe_ctx,
1708 struct dc_state *context)
1709{
f42ea55b 1710 struct dce_hwseq *hws = dc->hwseq;
b6e881c9 1711 /* Only need to unblank on top pipe */
d3dfceb5 1712
b6e881c9
DL		 1713 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level)
1714 && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
f42ea55b 1715 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
b6e881c9 1716
a71e5529
AC		 1717 /* Only update TG on top pipe */
1718 if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe
1719 && !pipe_ctx->prev_odm_pipe) {
b6e881c9
DL		 1720 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1721 pipe_ctx->stream_res.tg,
5842abd9 1722 calculate_vready_offset_for_group(pipe_ctx),
b6e881c9
DL		 1723 pipe_ctx->pipe_dlg_param.vstartup_start,
1724 pipe_ctx->pipe_dlg_param.vupdate_offset,
1725 pipe_ctx->pipe_dlg_param.vupdate_width);
1726
ac84304d 1727 if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM)
203ccaf5 1728 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
a71e5529 1729
a14e9e02 1730 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
a71e5529 1731 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);
1caba4e8 1732
f42ea55b
AK		 1733 if (hws->funcs.setup_vupdate_interrupt)
1734 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
a14e9e02
DL		 1735 }
1736
b6e881c9 1737 if (pipe_ctx->update_flags.bits.odm)
f42ea55b 1738 hws->funcs.update_odm(dc, context, pipe_ctx);
b6e881c9 1739
868149c9 1740 if (pipe_ctx->update_flags.bits.enable) {
b6e881c9 1741 dcn20_enable_plane(dc, pipe_ctx, context);
868149c9
JA		 1742 if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes)
1743 dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub);
1744 }
b6e881c9 1745
ba5a5371
NK		 1746 if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size)
1747 dc->res_pool->hubbub->funcs->program_det_size(
1748 dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);
ba5a5371 1749
74701238 1750 if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw)
b6e881c9
DL		 1751 dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
1752
1753 if (pipe_ctx->update_flags.bits.enable
46250a0c 1754 || pipe_ctx->plane_state->update_flags.bits.hdr_mult)
f42ea55b 1755 hws->funcs.set_hdr_multiplier(pipe_ctx);
b6e881c9
DL		 1756
1757 if (pipe_ctx->update_flags.bits.enable ||
1758 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
1759 pipe_ctx->plane_state->update_flags.bits.gamma_change)
f42ea55b 1760 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
b6e881c9
DL		 1761
1762 /* dcn10_translate_regamma_to_hw_format takes 750us to finish
1763 * only do gamma programming for powering on, internal memcmp to avoid
1764 * updating on slave planes
1765 */
bb622e0c
DV		 1766 if (pipe_ctx->update_flags.bits.enable ||
1767 pipe_ctx->update_flags.bits.plane_changed ||
1768 pipe_ctx->stream->update_flags.bits.out_tf ||
1769 pipe_ctx->plane_state->update_flags.bits.output_tf_change)
f42ea55b 1770 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
377c9d04
JP		 1771
1772 /* If the pipe has been enabled or has a different opp, we
1773 * should reprogram the fmt. This deals with cases where
1774 * interation between mpc and odm combine on different streams
1775 * causes a different pipe to be chosen to odm combine with.
1776 */
1777 if (pipe_ctx->update_flags.bits.enable
1778 || pipe_ctx->update_flags.bits.opp_changed) {
1779
1780 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1781 pipe_ctx->stream_res.opp,
1782 COLOR_SPACE_YCBCR601,
1783 pipe_ctx->stream->timing.display_color_depth,
1784 pipe_ctx->stream->signal);
1785
1786 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1787 pipe_ctx->stream_res.opp,
1788 &pipe_ctx->stream->bit_depth_params,
1789 &pipe_ctx->stream->clamping);
1790 }
32e3da43
LH		 1791
1792 /* Set ABM pipe after other pipe configurations done */
1793 if (pipe_ctx->plane_state->visible) {
1794 if (pipe_ctx->stream_res.abm) {
1795 dc->hwss.set_pipe(pipe_ctx);
1796 pipe_ctx->stream_res.abm->funcs->set_abm_level(pipe_ctx->stream_res.abm,
1797 pipe_ctx->stream->abm_level);
1798 }
1799 }
b6e881c9
DL		 1800}
1801
78c77382 1802void dcn20_program_front_end_for_ctx(
b6e881c9
DL		 1803 struct dc *dc,
1804 struct dc_state *context)
1805{
b6e881c9 1806 int i;
f42ea55b 1807 struct dce_hwseq *hws = dc->hwseq;
b6e881c9
DL		 1808 DC_LOGGER_INIT(dc->ctx->logger);
1809
d5c0af57 1810 /* Carry over GSL groups in case the context is changing. */
931fa55b
JC		 1811 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1812 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1813 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1814
1815 if (pipe_ctx->stream == old_pipe_ctx->stream)
1816 pipe_ctx->stream_res.gsl_group = old_pipe_ctx->stream_res.gsl_group;
1817 }
d5c0af57 1818
091018a5
AC		 1819 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
1820 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1821 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
009114f6 1822
091018a5
AC		 1823 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) {
1824 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
009114f6
AK		 1825 /*turn off triple buffer for full update*/
1826 dc->hwss.program_triplebuffer(
091018a5 1827 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
009114f6
AK		 1828 }
1829 }
1830 }
1831
b6e881c9
DL		 1832 /* Set pipe update flags and lock pipes */
1833 for (i = 0; i < dc->res_pool->pipe_count; i++)
1834 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i],
1835 &context->res_ctx.pipe_ctx[i]);
7ed4e635 1836
a5b50a0c
AL		 1837 /* When disabling phantom pipes, turn on phantom OTG first (so we can get double
1838 * buffer updates properly)
1839 */
af23aee9
AP		 1840 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1841 struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream;
1842
1843 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable && stream &&
1844 dc->current_state->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) {
a5b50a0c
AL		 1845 struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg;
1846
1847 if (tg->funcs->enable_crtc)
1848 tg->funcs->enable_crtc(tg);
1849 }
af23aee9 1850 }
b6e881c9
DL		 1851 /* OTG blank before disabling all front ends */
1852 for (i = 0; i < dc->res_pool->pipe_count; i++)
1853 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1854 && !context->res_ctx.pipe_ctx[i].top_pipe
1855 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe
1856 && context->res_ctx.pipe_ctx[i].stream)
f42ea55b 1857 hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);
b6e881c9 1858
d4930b7a 1859
b6e881c9
DL		 1860 /* Disconnect mpcc */
1861 for (i = 0; i < dc->res_pool->pipe_count; i++)
1862 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1863 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {
ba5a5371
NK		 1864 struct hubbub *hubbub = dc->res_pool->hubbub;
1865
14eb72ff
AL		 1866 /* Phantom pipe DET should be 0, but if a pipe in use is being transitioned to phantom
1867 * then we want to do the programming here (effectively it's being disabled). If we do
1868 * the programming later the DET won't be updated until the OTG for the phantom pipe is
1869 * turned on (i.e. in an MCLK switch) which can come in too late and cause issues with
1870 * DET allocation.
1871 */
1872 if (hubbub->funcs->program_det_size && (context->res_ctx.pipe_ctx[i].update_flags.bits.disable ||
1873 (context->res_ctx.pipe_ctx[i].plane_state && context->res_ctx.pipe_ctx[i].plane_state->is_phantom)))
ba5a5371 1874 hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);
f42ea55b 1875 hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
b6e881c9 1876 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
7ed4e635
HW		 1877 }
1878
b6e881c9
DL		 1879 /*
1880 * Program all updated pipes, order matters for mpcc setup. Start with
1881 * top pipe and program all pipes that follow in order
1882 */
1883 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1884 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
7ed4e635 1885
b6e881c9
DL		 1886 if (pipe->plane_state && !pipe->top_pipe) {
1887 while (pipe) {
7f63d8a1
PH		 1888 if (hws->funcs.program_pipe)
1889 hws->funcs.program_pipe(dc, pipe, context);
14eb72ff
AL		 1890 else {
1891 /* Don't program phantom pipes in the regular front end programming sequence.
1892 * There is an MPO transition case where a pipe being used by a video plane is
1893 * transitioned directly to be a phantom pipe when closing the MPO video. However
1894 * the phantom pipe will program a new HUBP_VTG_SEL (update takes place right away),
1895 * but the MPO still exists until the double buffered update of the main pipe so we
1896 * will get a frame of underflow if the phantom pipe is programmed here.
1897 */
1898 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_PHANTOM)
1899 dcn20_program_pipe(dc, pipe, context);
1900 }
7f63d8a1 1901
b6e881c9
DL		 1902 pipe = pipe->bottom_pipe;
1903 }
b6e881c9 1904 }
82367e7f
RC		 1905 /* Program secondary blending tree and writeback pipes */
1906 pipe = &context->res_ctx.pipe_ctx[i];
1907 if (!pipe->top_pipe && !pipe->prev_odm_pipe
1908 && pipe->stream && pipe->stream->num_wb_info > 0
1909 && (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw)
1910 || pipe->stream->update_flags.raw)
1911 && hws->funcs.program_all_writeback_pipes_in_tree)
1912 hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
dd15640b
BL		 1913
1914 /* Avoid underflow by check of pipe line read when adding 2nd plane. */
1915 if (hws->wa.wait_hubpret_read_start_during_mpo_transition &&
1916 !pipe->top_pipe &&
1917 pipe->stream &&
1918 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start &&
1919 dc->current_state->stream_status[0].plane_count == 1 &&
1920 context->stream_status[0].plane_count > 1) {
1921 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp);
1922 }
1cb69b43
DV		 1923
1924 /* when dynamic ODM is active, pipes must be reconfigured when all planes are
1925 * disabled, as some transitions will leave software and hardware state
1926 * mismatched.
1927 */
1928 if (dc->debug.enable_single_display_2to1_odm_policy &&
1929 pipe->stream &&
1930 pipe->update_flags.bits.disable &&
1931 !pipe->prev_odm_pipe &&
1932 hws->funcs.update_odm)
1933 hws->funcs.update_odm(dc, context, pipe);
b6e881c9 1934 }
bbf5f6c3
AK		 1935}
1936
1937void dcn20_post_unlock_program_front_end(
1938 struct dc *dc,
1939 struct dc_state *context)
1940{
1941 int i;
1942 const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100;
d9758768 1943 struct dce_hwseq *hwseq = dc->hwseq;
bbf5f6c3
AK		 1944
1945 DC_LOGGER_INIT(dc->ctx->logger);
b6e881c9
DL		 1946
1947 for (i = 0; i < dc->res_pool->pipe_count; i++)
1948 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
1949 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
986936d1
JL		 1950
1951 /*
1952 * If we are enabling a pipe, we need to wait for pending clear as this is a critical
1953 * part of the enable operation otherwise, DM may request an immediate flip which
1954 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which
1955 * is unsupported on DCN.
1956 */
b6e881c9
DL		 1957 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1958 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
85f4bc0c
AL		 1959 // Don't check flip pending on phantom pipes
1960 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable &&
1961 pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) {
b6e881c9
DL		 1962 struct hubp *hubp = pipe->plane_res.hubp;
1963 int j = 0;
1964
38259bac 1965 for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000
b6e881c9 1966 && hubp->funcs->hubp_is_flip_pending(hubp); j++)
345b1696 1967 udelay(1);
986936d1
JL		 1968 }
1969 }
f93e29f0 1970
14eb72ff
AL		 1971 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1972 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1973
1974 if (pipe->plane_state && !pipe->top_pipe) {
1975 /* Program phantom pipe here to prevent a frame of underflow in the MPO transition
1976 * case (if a pipe being used for a video plane transitions to a phantom pipe, it
1977 * can underflow due to HUBP_VTG_SEL programming if done in the regular front end
1978 * programming sequence).
1979 */
b0d6de32
AL		 1980 while (pipe) {
1981 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
e267f5e6
AL		 1982 /* When turning on the phantom pipe we want to run through the
1983 * entire enable sequence, so apply all the "enable" flags.
1984 */
1985 if (dc->hwss.apply_update_flags_for_phantom)
1986 dc->hwss.apply_update_flags_for_phantom(pipe);
b0d6de32
AL		 1987 if (dc->hwss.update_phantom_vp_position)
1988 dc->hwss.update_phantom_vp_position(dc, context, pipe);
1989 dcn20_program_pipe(dc, pipe, context);
1990 }
1991 pipe = pipe->bottom_pipe;
43080c9b 1992 }
14eb72ff
AL		 1993 }
1994 }
1995
1996 /* Only program the MALL registers after all the main and phantom pipes
1997 * are done programming.
1998 */
1999 if (hwseq->funcs.program_mall_pipe_config)
2000 hwseq->funcs.program_mall_pipe_config(dc, context);
2001
f93e29f0 2002 /* WA to apply WM setting*/
d9758768 2003 if (hwseq->wa.DEGVIDCN21)
f93e29f0 2004 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);
d9758768
GS		 2005
2006
2007 /* WA for stutter underflow during MPO transitions when adding 2nd plane */
2008 if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) {
2009
2010 if (dc->current_state->stream_status[0].plane_count == 1 &&
2011 context->stream_status[0].plane_count > 1) {
2012
2013 struct timing_generator *tg = dc->res_pool->timing_generators[0];
2014
2015 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false);
2016
2017 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true;
2018 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg);
2019 }
2020 }
7ed4e635
HW		 2021}
2022
7ed4e635
HW		 2023void dcn20_prepare_bandwidth(
2024 struct dc *dc,
2025 struct dc_state *context)
2026{
2027 struct hubbub *hubbub = dc->res_pool->hubbub;
2e6e14c9 2028 unsigned int compbuf_size_kb = 0;
85f4bc0c
AL		 2029 unsigned int cache_wm_a = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns;
2030 unsigned int i;
7ed4e635 2031
057fc695
JL		 2032 dc->clk_mgr->funcs->update_clocks(
2033 dc->clk_mgr,
2034 context,
2035 false);
2036
85f4bc0c
AL		 2037 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2038 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2039
2040 // At optimize don't restore the original watermark value
2041 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) {
2042 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;
2043 break;
2044 }
2045 }
2046
2710d6c1
AL		 2047 /* program dchubbub watermarks:
2048 * For assigning wm_optimized_required, use |= operator since we don't want
2049 * to clear the value if the optimize has not happened yet
2050 */
2051 dc->wm_optimized_required |= hubbub->funcs->program_watermarks(hubbub,
7ed4e635
HW		 2052 &context->bw_ctx.bw.dcn.watermarks,
2053 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
2054 false);
2e6e14c9 2055
85f4bc0c
AL		 2056 // Restore the real watermark so we can commit the value to DMCUB
2057 // DMCUB uses the "original" watermark value in SubVP MCLK switch
2058 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = cache_wm_a;
2059
ba5a5371 2060 /* decrease compbuf size */
2e6e14c9 2061 if (hubbub->funcs->program_compbuf_size) {
9a10c126 2062 if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes) {
2e6e14c9 2063 compbuf_size_kb = context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes;
9a10c126
DV		 2064 dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.dml.ip.min_comp_buffer_size_kbytes);
2065 } else {
2e6e14c9 2066 compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb;
9a10c126
DV		 2067 dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.bw.dcn.compbuf_size_kb);
2068 }
2e6e14c9
DM		 2069
2070 hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, false);
2071 }
7ed4e635
HW		 2072}
2073
2074void dcn20_optimize_bandwidth(
2075 struct dc *dc,
2076 struct dc_state *context)
2077{
2078 struct hubbub *hubbub = dc->res_pool->hubbub;
e5fc7825 2079 int i;
7ed4e635 2080
85f4bc0c
AL		 2081 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2082 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2083
2084 // At optimize don't need to restore the original watermark value
2085 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) {
2086 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;
2087 break;
2088 }
2089 }
2090
4c631826
YS		 2091 /* program dchubbub watermarks */
2092 hubbub->funcs->program_watermarks(hubbub,
2093 &context->bw_ctx.bw.dcn.watermarks,
2094 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
2095 true);
7ed4e635 2096
4866b0bf
ML		 2097 if (dc->clk_mgr->dc_mode_softmax_enabled)
2098 if (dc->clk_mgr->clks.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
2099 context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
2100 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
2101
b808a7eb
DV		 2102 /* increase compbuf size */
2103 if (hubbub->funcs->program_compbuf_size)
2104 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);
2105
4c631826
YS		 2106 dc->clk_mgr->funcs->update_clocks(
2107 dc->clk_mgr,
2108 context,
2109 true);
e5fc7825
GT		 2110 if (dc_extended_blank_supported(dc) && context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) {
2111 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
2112 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2113
2114 if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank
2115 && pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max
2116 && pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total)
2117 pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp,
2118 pipe_ctx->dlg_regs.optimized_min_dst_y_next_start);
2119 }
2120 }
7ed4e635
HW		 2121}
2122
2123bool dcn20_update_bandwidth(
2124 struct dc *dc,
2125 struct dc_state *context)
2126{
2127 int i;
f42ea55b 2128 struct dce_hwseq *hws = dc->hwseq;
7ed4e635
HW		 2129
2130 /* recalculate DML parameters */
254eb07c 2131 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false))
7ed4e635 2132 return false;
7ed4e635
HW		 2133
2134 /* apply updated bandwidth parameters */
2135 dc->hwss.prepare_bandwidth(dc, context);
2136
2137 /* update hubp configs for all pipes */
2138 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2139 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2140
2141 if (pipe_ctx->plane_state == NULL)
2142 continue;
2143
2144 if (pipe_ctx->top_pipe == NULL) {
2145 bool blank = !is_pipe_tree_visible(pipe_ctx);
2146
2147 pipe_ctx->stream_res.tg->funcs->program_global_sync(
2148 pipe_ctx->stream_res.tg,
5842abd9 2149 calculate_vready_offset_for_group(pipe_ctx),
7ed4e635
HW		 2150 pipe_ctx->pipe_dlg_param.vstartup_start,
2151 pipe_ctx->pipe_dlg_param.vupdate_offset,
2152 pipe_ctx->pipe_dlg_param.vupdate_width);
2153
3972c350 2154 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
5200c401 2155 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);
1caba4e8 2156
b1f6d01c 2157 if (pipe_ctx->prev_odm_pipe == NULL)
f42ea55b 2158 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);
1caba4e8 2159
f42ea55b
AK		 2160 if (hws->funcs.setup_vupdate_interrupt)
2161 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
7ed4e635
HW		 2162 }
2163
2164 pipe_ctx->plane_res.hubp->funcs->hubp_setup(
2165 pipe_ctx->plane_res.hubp,
2166 &pipe_ctx->dlg_regs,
2167 &pipe_ctx->ttu_regs,
2168 &pipe_ctx->rq_regs,
2169 &pipe_ctx->pipe_dlg_param);
2170 }
2171
2172 return true;
2173}
2174
78c77382 2175void dcn20_enable_writeback(
7ed4e635 2176 struct dc *dc,
edb922b0
JP		 2177 struct dc_writeback_info *wb_info,
2178 struct dc_state *context)
7ed4e635
HW		 2179{
2180 struct dwbc *dwb;
2181 struct mcif_wb *mcif_wb;
2182 struct timing_generator *optc;
2183
2184 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
2185 ASSERT(wb_info->wb_enabled);
2186 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
2187 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
2188
2189 /* set the OPTC source mux */
6a652f6d 2190 optc = dc->res_pool->timing_generators[dwb->otg_inst];
7ed4e635
HW		 2191 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
2192 /* set MCIF_WB buffer and arbitration configuration */
2193 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);
edb922b0 2194 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
7ed4e635
HW		 2195 /* Enable MCIF_WB */
2196 mcif_wb->funcs->enable_mcif(mcif_wb);
2197 /* Enable DWB */
2198 dwb->funcs->enable(dwb, &wb_info->dwb_params);
2199 /* TODO: add sequence to enable/disable warmup */
2200}
2201
2202void dcn20_disable_writeback(
2203 struct dc *dc,
2204 unsigned int dwb_pipe_inst)
2205{
2206 struct dwbc *dwb;
2207 struct mcif_wb *mcif_wb;
2208
2209 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
2210 dwb = dc->res_pool->dwbc[dwb_pipe_inst];
2211 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
2212
2213 dwb->funcs->disable(dwb);
2214 mcif_wb->funcs->disable_mcif(mcif_wb);
2215}
2216
78c77382 2217bool dcn20_wait_for_blank_complete(
7ed4e635
HW		 2218 struct output_pixel_processor *opp)
2219{
2220 int counter;
2221
2222 for (counter = 0; counter < 1000; counter++) {
2223 if (opp->funcs->dpg_is_blanked(opp))
2224 break;
2225
2226 udelay(100);
2227 }
2228
2229 if (counter == 1000) {
2230 dm_error("DC: failed to blank crtc!\n");
2231 return false;
2232 }
2233
2234 return true;
2235}
2236
2237bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)
2238{
2239 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2240
2241 if (!hubp)
2242 return false;
2243 return hubp->funcs->dmdata_status_done(hubp);
2244}
2245
78c77382 2246void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
7ed4e635 2247{
97bda032 2248 struct dce_hwseq *hws = dc->hwseq;
97bda032
HW		 2249
2250 if (pipe_ctx->stream_res.dsc) {
b1f6d01c
DL		 2251 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2252
20cc44c9 2253 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);
b1f6d01c 2254 while (odm_pipe) {
20cc44c9 2255 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);
b1f6d01c
DL		 2256 odm_pipe = odm_pipe->next_odm_pipe;
2257 }
97bda032 2258 }
7ed4e635
HW		 2259}
2260
78c77382 2261void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
7ed4e635 2262{
97bda032 2263 struct dce_hwseq *hws = dc->hwseq;
97bda032
HW		 2264
2265 if (pipe_ctx->stream_res.dsc) {
b1f6d01c
DL		 2266 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2267
20cc44c9 2268 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);
b1f6d01c 2269 while (odm_pipe) {
20cc44c9 2270 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);
b1f6d01c
DL		 2271 odm_pipe = odm_pipe->next_odm_pipe;
2272 }
97bda032 2273 }
7ed4e635
HW		 2274}
2275
2276void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)
2277{
2278 struct dc_dmdata_attributes attr = { 0 };
2279 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2280
2281 attr.dmdata_mode = DMDATA_HW_MODE;
2282 attr.dmdata_size =
2283 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;
2284 attr.address.quad_part =
2285 pipe_ctx->stream->dmdata_address.quad_part;
2286 attr.dmdata_dl_delta = 0;
2287 attr.dmdata_qos_mode = 0;
2288 attr.dmdata_qos_level = 0;
2289 attr.dmdata_repeat = 1; /* always repeat */
2290 attr.dmdata_updated = 1;
2291 attr.dmdata_sw_data = NULL;
2292
2293 hubp->funcs->dmdata_set_attributes(hubp, &attr);
2294}
2295
78c77382 2296void dcn20_init_vm_ctx(
bda9afda
DL		 2297 struct dce_hwseq *hws,
2298 struct dc *dc,
2299 struct dc_virtual_addr_space_config *va_config,
2300 int vmid)
7ed4e635 2301{
bda9afda
DL		 2302 struct dcn_hubbub_virt_addr_config config;
2303
2304 if (vmid == 0) {
2305 ASSERT(0); /* VMID cannot be 0 for vm context */
2306 return;
2307 }
2308
2309 config.page_table_start_addr = va_config->page_table_start_addr;
2310 config.page_table_end_addr = va_config->page_table_end_addr;
2311 config.page_table_block_size = va_config->page_table_block_size_in_bytes;
2312 config.page_table_depth = va_config->page_table_depth;
2313 config.page_table_base_addr = va_config->page_table_base_addr;
2314
2315 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid);
2316}
2317
78c77382 2318int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
bda9afda
DL		 2319{
2320 struct dcn_hubbub_phys_addr_config config;
2321
2322 config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
2323 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
2324 config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
2325 config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
2326 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
2327 config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
2328 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
2329 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
2330 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
ee80de54 2331 config.page_table_default_page_addr = pa_config->page_table_default_page_addr;
bda9afda
DL		 2332
2333 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
7ed4e635
HW		 2334}
2335
2336static bool patch_address_for_sbs_tb_stereo(
2337 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
2338{
2339 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2340 bool sec_split = pipe_ctx->top_pipe &&
2341 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
2342 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2343 (pipe_ctx->stream->timing.timing_3d_format ==
2344 TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2345 pipe_ctx->stream->timing.timing_3d_format ==
2346 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
2347 *addr = plane_state->address.grph_stereo.left_addr;
2348 plane_state->address.grph_stereo.left_addr =
2349 plane_state->address.grph_stereo.right_addr;
2350 return true;
2351 }
2352
2353 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
2354 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
2355 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
2356 plane_state->address.grph_stereo.right_addr =
2357 plane_state->address.grph_stereo.left_addr;
480c5b8f
AL		 2358 plane_state->address.grph_stereo.right_meta_addr =
2359 plane_state->address.grph_stereo.left_meta_addr;
7ed4e635
HW		 2360 }
2361 return false;
2362}
2363
78c77382 2364void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
7ed4e635
HW		 2365{
2366 bool addr_patched = false;
2367 PHYSICAL_ADDRESS_LOC addr;
2368 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
7ed4e635
HW		 2369
2370 if (plane_state == NULL)
2371 return;
2372
2373 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
2374
bda9afda
DL		 2375 // Call Helper to track VMID use
2376 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);
7ed4e635
HW		 2377
2378 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
2379 pipe_ctx->plane_res.hubp,
2380 &plane_state->address,
bda9afda 2381 plane_state->flip_immediate);
7ed4e635
HW		 2382
2383 plane_state->status.requested_address = plane_state->address;
2384
2385 if (plane_state->flip_immediate)
2386 plane_state->status.current_address = plane_state->address;
2387
2388 if (addr_patched)
2389 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
2390}
2391
2392void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
2393 struct dc_link_settings *link_settings)
2394{
c78abac9 2395 struct encoder_unblank_param params = {0};
7ed4e635
HW		 2396 struct dc_stream_state *stream = pipe_ctx->stream;
2397 struct dc_link *link = stream->link;
f42ea55b 2398 struct dce_hwseq *hws = link->dc->hwseq;
b1f6d01c 2399 struct pipe_ctx *odm_pipe;
7ed4e635 2400
b1f6d01c
DL		 2401 params.opp_cnt = 1;
2402 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
2403 params.opp_cnt++;
2404 }
7ed4e635
HW		 2405 /* only 3 items below are used by unblank */
2406 params.timing = pipe_ctx->stream->timing;
2407
2408 params.link_settings.link_rate = link_settings->link_rate;
2409
98ce7d32 2410 if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
f01ee019
FZ		 2411 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
2412 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(
2413 pipe_ctx->stream_res.hpo_dp_stream_enc,
2414 pipe_ctx->stream_res.tg->inst);
2415 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
78c77382 2416 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1)
7ed4e635
HW		 2417 params.timing.pix_clk_100hz /= 2;
2418 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
1f332460 2419 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1);
3550d622 2420 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);
7ed4e635
HW		 2421 }
2422
2423 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
f42ea55b 2424 hws->funcs.edp_backlight_control(link, true);
7ed4e635
HW		 2425 }
2426}
2427
78c77382 2428void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
7ed4e635
HW		 2429{
2430 struct timing_generator *tg = pipe_ctx->stream_res.tg;
78c77382 2431 int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
7ed4e635 2432
7fad39ca
EB		 2433 if (start_line < 0)
2434 start_line = 0;
7ed4e635
HW		 2435
2436 if (tg->funcs->setup_vertical_interrupt2)
2437 tg->funcs->setup_vertical_interrupt2(tg, start_line);
2438}
2439
2440static void dcn20_reset_back_end_for_pipe(
2441 struct dc *dc,
2442 struct pipe_ctx *pipe_ctx,
2443 struct dc_state *context)
2444{
2445 int i;
9c75891f
WL		 2446 struct dc_link *link = pipe_ctx->stream->link;
2447 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
2448
7ed4e635
HW		 2449 DC_LOGGER_INIT(dc->ctx->logger);
2450 if (pipe_ctx->stream_res.stream_enc == NULL) {
2451 pipe_ctx->stream = NULL;
2452 return;
2453 }
2454
2455 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
efca0905
PH		 2456 /* DPMS may already disable or */
2457 /* dpms_off status is incorrect due to fastboot
2458 * feature. When system resume from S4 with second
2459 * screen only, the dpms_off would be true but
2460 * VBIOS lit up eDP, so check link status too.
2461 */
9c75891f 2462 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
98ce7d32 2463 dc->link_srv->set_dpms_off(pipe_ctx);
9c75891f 2464 else if (pipe_ctx->stream_res.audio)
57430404
SSC		 2465 dc->hwss.disable_audio_stream(pipe_ctx);
2466
2467 /* free acquired resources */
2468 if (pipe_ctx->stream_res.audio) {
2469 /*disable az_endpoint*/
2470 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2471
2472 /*free audio*/
2473 if (dc->caps.dynamic_audio == true) {
2474 /*we have to dynamic arbitrate the audio endpoints*/
2475 /*we free the resource, need reset is_audio_acquired*/
2476 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2477 pipe_ctx->stream_res.audio, false);
2478 pipe_ctx->stream_res.audio = NULL;
2479 }
7ed4e635 2480 }
7ed4e635 2481 }
606b3551 2482 else if (pipe_ctx->stream_res.dsc) {
98ce7d32 2483 dc->link_srv->set_dsc_enable(pipe_ctx, false);
606b3551 2484 }
7ed4e635
HW		 2485
2486 /* by upper caller loop, parent pipe: pipe0, will be reset last.
2487 * back end share by all pipes and will be disable only when disable
2488 * parent pipe.
2489 */
2490 if (pipe_ctx->top_pipe == NULL) {
9edf202d 2491
3ba01817 2492 dc->hwss.set_abm_immediate_disable(pipe_ctx);
9edf202d 2493
7ed4e635
HW		 2494 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
2495
2496 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
2497 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
2498 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
2499 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
38df0701
WL		 2500
2501 if (pipe_ctx->stream_res.tg->funcs->set_drr)
2502 pipe_ctx->stream_res.tg->funcs->set_drr(
2503 pipe_ctx->stream_res.tg, NULL);
9c75891f
WL		 2504 /* TODO - convert symclk_ref_cnts for otg to a bit map to solve
2505 * the case where the same symclk is shared across multiple otg
2506 * instances
2507 */
2508 link->phy_state.symclk_ref_cnts.otg = 0;
2509 if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) {
2510 link_hwss->disable_link_output(link,
2511 &pipe_ctx->link_res, pipe_ctx->stream->signal);
2512 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
2513 }
7ed4e635
HW		 2514 }
2515
2516 for (i = 0; i < dc->res_pool->pipe_count; i++)
2517 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
2518 break;
2519
2520 if (i == dc->res_pool->pipe_count)
2521 return;
2522
2523 pipe_ctx->stream = NULL;
2524 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
2525 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
2526}
2527
78c77382 2528void dcn20_reset_hw_ctx_wrap(
7ed4e635
HW		 2529 struct dc *dc,
2530 struct dc_state *context)
2531{
2532 int i;
f42ea55b 2533 struct dce_hwseq *hws = dc->hwseq;
7ed4e635
HW		 2534
2535 /* Reset Back End*/
2536 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
2537 struct pipe_ctx *pipe_ctx_old =
2538 &dc->current_state->res_ctx.pipe_ctx[i];
2539 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2540
2541 if (!pipe_ctx_old->stream)
2542 continue;
2543
b1f6d01c 2544 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
7ed4e635
HW		 2545 continue;
2546
2547 if (!pipe_ctx->stream ||
2548 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2549 struct clock_source *old_clk = pipe_ctx_old->clock_source;
2550
2551 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
f42ea55b 2552 if (hws->funcs.enable_stream_gating)
ae6c9601 2553 hws->funcs.enable_stream_gating(dc, pipe_ctx_old);
7ed4e635
HW		 2554 if (old_clk)
2555 old_clk->funcs->cs_power_down(old_clk);
2556 }
2557 }
2558}
2559
60df8441 2560void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id)
123c53a9 2561{
60df8441 2562 struct mpc *mpc = dc->res_pool->mpc;
123c53a9 2563
60df8441
WW		 2564 // input to MPCC is always RGB, by default leave black_color at 0
2565 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)
2566 get_hdr_visual_confirm_color(pipe_ctx, color);
2567 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
2568 get_surface_visual_confirm_color(pipe_ctx, color);
2569 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE)
2570 get_mpctree_visual_confirm_color(pipe_ctx, color);
793c82ee
PTC		 2571 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)
2572 get_surface_tile_visual_confirm_color(pipe_ctx, color);
94adb993
LHM		 2573 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP)
2574 get_subvp_visual_confirm_color(dc, pipe_ctx, color);
60df8441 2575
b09c1fff
LHM		 2576 if (mpc->funcs->set_bg_color) {
2577 memcpy(&pipe_ctx->plane_state->visual_confirm_color, color, sizeof(struct tg_color));
60df8441 2578 mpc->funcs->set_bg_color(mpc, color, mpcc_id);
b09c1fff 2579 }
123c53a9
JL		 2580}
2581
3ca40237
WW		 2582void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
2583{
7ed4e635 2584 struct hubp *hubp = pipe_ctx->plane_res.hubp;
c78abac9 2585 struct mpcc_blnd_cfg blnd_cfg = {0};
473e0ecb 2586 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
7ed4e635
HW		 2587 int mpcc_id;
2588 struct mpcc *new_mpcc;
2589 struct mpc *mpc = dc->res_pool->mpc;
2590 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
2591
7ed4e635
HW		 2592 blnd_cfg.overlap_only = false;
2593 blnd_cfg.global_gain = 0xff;
2594
76818cdd
SJK		 2595 if (per_pixel_alpha) {
2596 blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha;
2597 if (pipe_ctx->plane_state->global_alpha) {
2598 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN;
2599 blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;
2600 } else {
2601 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
2602 }
67229b27 2603 } else {
76818cdd 2604 blnd_cfg.pre_multiplied_alpha = false;
67229b27
MW		 2605 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
2606 }
2607
7ed4e635
HW		 2608 if (pipe_ctx->plane_state->global_alpha)
2609 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
2610 else
2611 blnd_cfg.global_alpha = 0xff;
2612
2613 blnd_cfg.background_color_bpc = 4;
2614 blnd_cfg.bottom_gain_mode = 0;
2615 blnd_cfg.top_gain = 0x1f000;
2616 blnd_cfg.bottom_inside_gain = 0x1f000;
2617 blnd_cfg.bottom_outside_gain = 0x1f000;
76818cdd 2618
d99f1387
BL		 2619 if (pipe_ctx->plane_state->format
2620 == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA)
2621 blnd_cfg.pre_multiplied_alpha = false;
7ed4e635
HW		 2622
2623 /*
2624 * TODO: remove hack
2625 * Note: currently there is a bug in init_hw such that
2626 * on resume from hibernate, BIOS sets up MPCC0, and
2627 * we do mpcc_remove but the mpcc cannot go to idle
2628 * after remove. This cause us to pick mpcc1 here,
2629 * which causes a pstate hang for yet unknown reason.
2630 */
2631 mpcc_id = hubp->inst;
2632
c97c8d77 2633 /* If there is no full update, don't need to touch MPC tree*/
68c10ac9
AC		 2634 if (!pipe_ctx->plane_state->update_flags.bits.full_update &&
2635 !pipe_ctx->update_flags.bits.mpcc) {
c97c8d77 2636 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
60df8441 2637 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
c97c8d77
NK		 2638 return;
2639 }
2640
7ed4e635
HW		 2641 /* check if this MPCC is already being used */
2642 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
2643 /* remove MPCC if being used */
2644 if (new_mpcc != NULL)
2645 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
2646 else
2647 if (dc->debug.sanity_checks)
2648 mpc->funcs->assert_mpcc_idle_before_connect(
2649 dc->res_pool->mpc, mpcc_id);
2650
2651 /* Call MPC to insert new plane */
2652 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2653 mpc_tree_params,
2654 &blnd_cfg,
2655 NULL,
2656 NULL,
2657 hubp->inst,
2658 mpcc_id);
60df8441 2659 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
7ed4e635
HW		 2660
2661 ASSERT(new_mpcc != NULL);
2662 hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2663 hubp->mpcc_id = mpcc_id;
2664}
2665
7462475e
WL		 2666static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link)
2667{
2668 switch (link->link_enc->transmitter) {
2669 case TRANSMITTER_UNIPHY_A:
2670 return PHYD32CLKA;
2671 case TRANSMITTER_UNIPHY_B:
2672 return PHYD32CLKB;
2673 case TRANSMITTER_UNIPHY_C:
2674 return PHYD32CLKC;
2675 case TRANSMITTER_UNIPHY_D:
2676 return PHYD32CLKD;
2677 case TRANSMITTER_UNIPHY_E:
2678 return PHYD32CLKE;
2679 default:
2680 return PHYD32CLKA;
2681 }
2682}
2683
2684static int get_odm_segment_count(struct pipe_ctx *pipe_ctx)
2685{
2686 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2687 int count = 1;
2688
2689 while (odm_pipe != NULL) {
2690 count++;
2691 odm_pipe = odm_pipe->next_odm_pipe;
2692 }
2693
2694 return count;
2695}
2696
78c77382 2697void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
f591344e
JP		 2698{
2699 enum dc_lane_count lane_count =
2700 pipe_ctx->stream->link->cur_link_settings.lane_count;
2701
2702 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
2703 struct dc_link *link = pipe_ctx->stream->link;
2704
2705 uint32_t active_total_with_borders;
2706 uint32_t early_control = 0;
2707 struct timing_generator *tg = pipe_ctx->stream_res.tg;
9d8033d6
WL		 2708 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
2709 struct dc *dc = pipe_ctx->stream->ctx->dc;
7462475e
WL		 2710 struct dtbclk_dto_params dto_params = {0};
2711 struct dccg *dccg = dc->res_pool->dccg;
2712 enum phyd32clk_clock_source phyd32clk;
2713 int dp_hpo_inst;
a10a22b0
WL		 2714 struct dce_hwseq *hws = dc->hwseq;
2715 unsigned int k1_div = PIXEL_RATE_DIV_NA;
2716 unsigned int k2_div = PIXEL_RATE_DIV_NA;
64d283cb 2717
98ce7d32 2718 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
9d8033d6
WL		 2719 if (dc->hwseq->funcs.setup_hpo_hw_control)
2720 dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, true);
f01ee019
FZ		 2721 }
2722
98ce7d32 2723 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
7462475e
WL		 2724 dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
2725 dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst);
2726
2727 phyd32clk = get_phyd32clk_src(link);
2728 dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);
2729
2730 dto_params.otg_inst = tg->inst;
2731 dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
2732 dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx);
2733 dto_params.timing = &pipe_ctx->stream->timing;
2734 dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);
2735 dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
2736 }
2737
a10a22b0
WL		 2738 if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {
2739 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
2740
2741 dc->res_pool->dccg->funcs->set_pixel_rate_div(
2742 dc->res_pool->dccg,
2743 pipe_ctx->stream_res.tg->inst,
2744 k1_div, k2_div);
2745 }
2746
9d8033d6 2747 link_hwss->setup_stream_encoder(pipe_ctx);
3550d622 2748
ce10a0f3 2749 if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {
9d8033d6
WL		 2750 if (dc->hwss.program_dmdata_engine)
2751 dc->hwss.program_dmdata_engine(pipe_ctx);
ce10a0f3 2752 }
f591344e 2753
9d8033d6 2754 dc->hwss.update_info_frame(pipe_ctx);
f591344e 2755
3550d622 2756 if (dc_is_dp_signal(pipe_ctx->stream->signal))
98ce7d32 2757 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
3550d622 2758
f591344e
JP		 2759 /* enable early control to avoid corruption on DP monitor*/
2760 active_total_with_borders =
2761 timing->h_addressable
2762 + timing->h_border_left
2763 + timing->h_border_right;
2764
2765 if (lane_count != 0)
2766 early_control = active_total_with_borders % lane_count;
2767
2768 if (early_control == 0)
2769 early_control = lane_count;
2770
2771 tg->funcs->set_early_control(tg, early_control);
2772
64a30aaf
EB		 2773 if (dc->hwseq->funcs.set_pixels_per_cycle)
2774 dc->hwseq->funcs.set_pixels_per_cycle(pipe_ctx);
f591344e
JP		 2775}
2776
78c77382 2777void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
f591344e
JP		 2778{
2779 struct dc_stream_state *stream = pipe_ctx->stream;
2780 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2781 bool enable = false;
2782 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
2783 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal)
2784 ? dmdata_dp
2785 : dmdata_hdmi;
2786
2787 /* if using dynamic meta, don't set up generic infopackets */
2788 if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
2789 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
2790 enable = true;
2791 }
2792
2793 if (!hubp)
2794 return;
2795
2796 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
2797 return;
2798
2799 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
2800 hubp->inst, mode);
2801}
2802
78c77382 2803void dcn20_fpga_init_hw(struct dc *dc)
8a31820b
ML		 2804{
2805 int i, j;
2806 struct dce_hwseq *hws = dc->hwseq;
2807 struct resource_pool *res_pool = dc->res_pool;
2808 struct dc_state *context = dc->current_state;
2809
2810 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
2811 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
2812
2813 // Initialize the dccg
2814 if (res_pool->dccg->funcs->dccg_init)
2815 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
2816
2817 //Enable ability to power gate / don't force power on permanently
f42ea55b 2818 hws->funcs.enable_power_gating_plane(hws, true);
8a31820b
ML		 2819
2820 // Specific to FPGA dccg and registers
2821 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
2822 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
2823
f42ea55b 2824 hws->funcs.dccg_init(hws);
8a31820b
ML		 2825
2826 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
2827 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
3ebd17f5
DL		 2828 if (REG(REFCLK_CNTL))
2829 REG_WRITE(REFCLK_CNTL, 0);
8a31820b
ML		 2830 //
2831
2832
2833 /* Blank pixel data with OPP DPG */
2834 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2835 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2836
2837 if (tg->funcs->is_tg_enabled(tg))
2838 dcn20_init_blank(dc, tg);
2839 }
2840
2841 for (i = 0; i < res_pool->timing_generator_count; i++) {
2842 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2843
2844 if (tg->funcs->is_tg_enabled(tg))
2845 tg->funcs->lock(tg);
2846 }
2847
2848 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2849 struct dpp *dpp = res_pool->dpps[i];
2850
2851 dpp->funcs->dpp_reset(dpp);
2852 }
2853
2854 /* Reset all MPCC muxes */
2855 res_pool->mpc->funcs->mpc_init(res_pool->mpc);
2856
2857 /* initialize OPP mpc_tree parameter */
2858 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
2859 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
2860 res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2861 for (j = 0; j < MAX_PIPES; j++)
2862 res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
2863 }
2864
2865 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2866 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2867 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2868 struct hubp *hubp = dc->res_pool->hubps[i];
2869 struct dpp *dpp = dc->res_pool->dpps[i];
2870
2871 pipe_ctx->stream_res.tg = tg;
2872 pipe_ctx->pipe_idx = i;
2873
2874 pipe_ctx->plane_res.hubp = hubp;
2875 pipe_ctx->plane_res.dpp = dpp;
2876 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
2877 hubp->mpcc_id = dpp->inst;
2878 hubp->opp_id = OPP_ID_INVALID;
2879 hubp->power_gated = false;
2880 pipe_ctx->stream_res.opp = NULL;
2881
2882 hubp->funcs->hubp_init(hubp);
2883
2884 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
2885 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2886 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
2887 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
2888 /*to do*/
f42ea55b 2889 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx);
8a31820b
ML		 2890 }
2891
2892 /* initialize DWB pointer to MCIF_WB */
2893 for (i = 0; i < res_pool->res_cap->num_dwb; i++)
2894 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
2895
2896 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2897 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2898
2899 if (tg->funcs->is_tg_enabled(tg))
2900 tg->funcs->unlock(tg);
2901 }
2902
2903 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2904 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2905
2906 dc->hwss.disable_plane(dc, pipe_ctx);
2907
2908 pipe_ctx->stream_res.tg = NULL;
2909 pipe_ctx->plane_res.hubp = NULL;
2910 }
2911
2912 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2913 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2914
2915 tg->funcs->tg_init(tg);
2916 }
8fe44c08 2917
ba5a5371
NK		 2918 if (dc->res_pool->hubbub->funcs->init_crb)
2919 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
8a31820b 2920}
471c1dd9
RA		 2921#ifndef TRIM_FSFT
2922bool dcn20_optimize_timing_for_fsft(struct dc *dc,
2923 struct dc_crtc_timing *timing,
2924 unsigned int max_input_rate_in_khz)
2925{
2926 unsigned int old_v_front_porch;
2927 unsigned int old_v_total;
2928 unsigned int max_input_rate_in_100hz;
2929 unsigned long long new_v_total;
2930
2931 max_input_rate_in_100hz = max_input_rate_in_khz * 10;
2932 if (max_input_rate_in_100hz < timing->pix_clk_100hz)
2933 return false;
2934
2935 old_v_total = timing->v_total;
2936 old_v_front_porch = timing->v_front_porch;
2937
2938 timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz;
2939 timing->pix_clk_100hz = max_input_rate_in_100hz;
2940
2941 new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz);
2942
2943 timing->v_total = new_v_total;
2944 timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total);
2945 return true;
2946}
2947#endif
dbf5256b
JA		 2948
2949void dcn20_set_disp_pattern_generator(const struct dc *dc,
2950 struct pipe_ctx *pipe_ctx,
2951 enum controller_dp_test_pattern test_pattern,
2952 enum controller_dp_color_space color_space,
2953 enum dc_color_depth color_depth,
2954 const struct tg_color *solid_color,
2955 int width, int height, int offset)
2956{
2957 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
2958 color_space, color_depth, solid_color, width, height, offset);
a71e5529 2959}
Linux 6.x block layer and io_uring tree(s)