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drm/amd/display: Apply 60us prefetch for DCFCLK <= 300Mhz
[linux-block.git] / drivers / gpu / drm / amd / display / dc / dcn20 / dcn20_hwseq.c
CommitLineData
7ed4e635
HW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
c602b36f 25#include <linux/delay.h>
7ed4e635
HW		 26
27#include "dm_services.h"
78c77382 28#include "basics/dc_common.h"
7ed4e635
HW		 29#include "dm_helpers.h"
30#include "core_types.h"
31#include "resource.h"
78c77382 32#include "dcn20_resource.h"
7ed4e635
HW		 33#include "dcn20_hwseq.h"
34#include "dce/dce_hwseq.h"
78c77382
AK		 35#include "dcn20_dsc.h"
36#include "dcn20_optc.h"
7ed4e635
HW		 37#include "abm.h"
38#include "clk_mgr.h"
39#include "dmcu.h"
40#include "hubp.h"
41#include "timing_generator.h"
42#include "opp.h"
43#include "ipp.h"
44#include "mpc.h"
45#include "mcif_wb.h"
78c77382 46#include "dchubbub.h"
7ed4e635
HW		 47#include "reg_helper.h"
48#include "dcn10/dcn10_cm_common.h"
7ed4e635
HW		 49#include "vm_helper.h"
50#include "dccg.h"
dc6e2448
WW		 51#include "dc_dmub_srv.h"
52#include "dce/dmub_hw_lock_mgr.h"
60df8441 53#include "hw_sequencer.h"
3550d622 54#include "dpcd_defs.h"
0d4b4253 55#include "inc/link_enc_cfg.h"
dfabe597 56#include "link_hwss.h"
d5a43956 57#include "link.h"
7ed4e635
HW		 58
59#define DC_LOGGER_INIT(logger)
60
61#define CTX \
62 hws->ctx
63#define REG(reg)\
64 hws->regs->reg
65
66#undef FN
67#define FN(reg_name, field_name) \
68 hws->shifts->field_name, hws->masks->field_name
69
78c77382
AK		 70static int find_free_gsl_group(const struct dc *dc)
71{
72 if (dc->res_pool->gsl_groups.gsl_0 == 0)
73 return 1;
74 if (dc->res_pool->gsl_groups.gsl_1 == 0)
75 return 2;
76 if (dc->res_pool->gsl_groups.gsl_2 == 0)
77 return 3;
78
79 return 0;
80}
81
82/* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock)
83 * This is only used to lock pipes in pipe splitting case with immediate flip
84 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate,
85 * so we get tearing with freesync since we cannot flip multiple pipes
86 * atomically.
87 * We use GSL for this:
88 * - immediate flip: find first available GSL group if not already assigned
89 * program gsl with that group, set current OTG as master
90 * and always us 0x4 = AND of flip_ready from all pipes
91 * - vsync flip: disable GSL if used
92 *
93 * Groups in stream_res are stored as +1 from HW registers, i.e.
94 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
95 * Using a magic value like -1 would require tracking all inits/resets
96 */
97static void dcn20_setup_gsl_group_as_lock(
98 const struct dc *dc,
99 struct pipe_ctx *pipe_ctx,
100 bool enable)
101{
102 struct gsl_params gsl;
103 int group_idx;
104
105 memset(&gsl, 0, sizeof(struct gsl_params));
106
107 if (enable) {
108 /* return if group already assigned since GSL was set up
109 * for vsync flip, we would unassign so it can't be "left over"
110 */
111 if (pipe_ctx->stream_res.gsl_group > 0)
112 return;
113
114 group_idx = find_free_gsl_group(dc);
115 ASSERT(group_idx != 0);
116 pipe_ctx->stream_res.gsl_group = group_idx;
117
118 /* set gsl group reg field and mark resource used */
119 switch (group_idx) {
120 case 1:
121 gsl.gsl0_en = 1;
122 dc->res_pool->gsl_groups.gsl_0 = 1;
123 break;
124 case 2:
125 gsl.gsl1_en = 1;
126 dc->res_pool->gsl_groups.gsl_1 = 1;
127 break;
128 case 3:
129 gsl.gsl2_en = 1;
130 dc->res_pool->gsl_groups.gsl_2 = 1;
131 break;
132 default:
133 BREAK_TO_DEBUGGER();
134 return; // invalid case
135 }
136 gsl.gsl_master_en = 1;
137 } else {
138 group_idx = pipe_ctx->stream_res.gsl_group;
139 if (group_idx == 0)
140 return; // if not in use, just return
141
142 pipe_ctx->stream_res.gsl_group = 0;
143
144 /* unset gsl group reg field and mark resource free */
145 switch (group_idx) {
146 case 1:
147 gsl.gsl0_en = 0;
148 dc->res_pool->gsl_groups.gsl_0 = 0;
149 break;
150 case 2:
151 gsl.gsl1_en = 0;
152 dc->res_pool->gsl_groups.gsl_1 = 0;
153 break;
154 case 3:
155 gsl.gsl2_en = 0;
156 dc->res_pool->gsl_groups.gsl_2 = 0;
157 break;
158 default:
159 BREAK_TO_DEBUGGER();
160 return;
161 }
162 gsl.gsl_master_en = 0;
163 }
164
165 /* at this point we want to program whether it's to enable or disable */
166 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
167 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
168 pipe_ctx->stream_res.tg->funcs->set_gsl(
169 pipe_ctx->stream_res.tg,
170 &gsl);
171
172 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
173 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0);
174 } else
175 BREAK_TO_DEBUGGER();
176}
177
178void dcn20_set_flip_control_gsl(
179 struct pipe_ctx *pipe_ctx,
180 bool flip_immediate)
181{
182 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)
183 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(
184 pipe_ctx->plane_res.hubp, flip_immediate);
185
186}
187
188void dcn20_enable_power_gating_plane(
7ed4e635
HW		 189 struct dce_hwseq *hws,
190 bool enable)
191{
0bb80369 192 bool force_on = true; /* disable power gating */
504d3cae 193 uint32_t org_ip_request_cntl = 0;
7ed4e635
HW		 194
195 if (enable)
0bb80369 196 force_on = false;
7ed4e635 197
504d3cae
HW		 198 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
199 if (org_ip_request_cntl == 0)
200 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
201
7ed4e635
HW		 202 /* DCHUBP0/1/2/3/4/5 */
203 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
204 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
205 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
206 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
46825fcf
TC		 207 if (REG(DOMAIN8_PG_CONFIG))
208 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
209 if (REG(DOMAIN10_PG_CONFIG))
210 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
7ed4e635
HW		 211
212 /* DPP0/1/2/3/4/5 */
213 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
214 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
215 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
216 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
46825fcf
TC		 217 if (REG(DOMAIN9_PG_CONFIG))
218 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
219 if (REG(DOMAIN11_PG_CONFIG))
220 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
7ed4e635 221
46825fcf 222 /* DCS0/1/2/3/4/5 */
7ed4e635
HW		 223 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on);
224 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on);
225 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on);
46825fcf
TC		 226 if (REG(DOMAIN19_PG_CONFIG))
227 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on);
228 if (REG(DOMAIN20_PG_CONFIG))
229 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on);
230 if (REG(DOMAIN21_PG_CONFIG))
231 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on);
504d3cae
HW		 232
233 if (org_ip_request_cntl == 0)
234 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
235
7ed4e635
HW		 236}
237
c70b4016 238void dcn20_dccg_init(struct dce_hwseq *hws)
7ed4e635
HW		 239{
240 /*
241 * set MICROSECOND_TIME_BASE_DIV
242 * 100Mhz refclk -> 0x120264
243 * 27Mhz refclk -> 0x12021b
244 * 48Mhz refclk -> 0x120230
245 *
246 */
247 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264);
248
249 /*
250 * set MILLISECOND_TIME_BASE_DIV
251 * 100Mhz refclk -> 0x1186a0
252 * 27Mhz refclk -> 0x106978
253 * 48Mhz refclk -> 0x10bb80
254 *
255 */
256 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
257
258 /* This value is dependent on the hardware pipeline delay so set once per SOC */
3577e167 259 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c);
7ed4e635
HW		 260}
261
8a31820b 262void dcn20_disable_vga(
7ed4e635
HW		 263 struct dce_hwseq *hws)
264{
265 REG_WRITE(D1VGA_CONTROL, 0);
266 REG_WRITE(D2VGA_CONTROL, 0);
267 REG_WRITE(D3VGA_CONTROL, 0);
268 REG_WRITE(D4VGA_CONTROL, 0);
269 REG_WRITE(D5VGA_CONTROL, 0);
270 REG_WRITE(D6VGA_CONTROL, 0);
271}
272
78c77382 273void dcn20_program_triple_buffer(
7ed4e635
HW		 274 const struct dc *dc,
275 struct pipe_ctx *pipe_ctx,
78c77382 276 bool enable_triple_buffer)
7ed4e635
HW		 277{
278 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {
279 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(
280 pipe_ctx->plane_res.hubp,
78c77382 281 enable_triple_buffer);
7ed4e635
HW		 282 }
283}
284
285/* Blank pixel data during initialization */
c70b4016 286void dcn20_init_blank(
7ed4e635
HW		 287 struct dc *dc,
288 struct timing_generator *tg)
289{
f42ea55b 290 struct dce_hwseq *hws = dc->hwseq;
7ed4e635
HW		 291 enum dc_color_space color_space;
292 struct tg_color black_color = {0};
293 struct output_pixel_processor *opp = NULL;
294 struct output_pixel_processor *bottom_opp = NULL;
295 uint32_t num_opps, opp_id_src0, opp_id_src1;
296 uint32_t otg_active_width, otg_active_height;
297
298 /* program opp dpg blank color */
299 color_space = COLOR_SPACE_SRGB;
300 color_space_to_black_color(dc, color_space, &black_color);
301
302 /* get the OTG active size */
303 tg->funcs->get_otg_active_size(tg,
304 &otg_active_width,
305 &otg_active_height);
306
307 /* get the OPTC source */
308 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
245a0221
AC		 309
310 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) {
311 ASSERT(false);
312 return;
313 }
7ed4e635
HW		 314 opp = dc->res_pool->opps[opp_id_src0];
315
7052a801
MM		 316 /* don't override the blank pattern if already enabled with the correct one. */
317 if (opp->funcs->dpg_is_blanked && opp->funcs->dpg_is_blanked(opp))
318 return;
319
7ed4e635
HW		 320 if (num_opps == 2) {
321 otg_active_width = otg_active_width / 2;
245a0221
AC		 322
323 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) {
324 ASSERT(false);
325 return;
326 }
7ed4e635
HW		 327 bottom_opp = dc->res_pool->opps[opp_id_src1];
328 }
329
330 opp->funcs->opp_set_disp_pattern_generator(
331 opp,
332 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
2057b7e1 333 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
7ed4e635
HW		 334 COLOR_DEPTH_UNDEFINED,
335 &black_color,
336 otg_active_width,
10b4e64e
WL		 337 otg_active_height,
338 0);
7ed4e635
HW		 339
340 if (num_opps == 2) {
341 bottom_opp->funcs->opp_set_disp_pattern_generator(
342 bottom_opp,
343 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
2057b7e1 344 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
7ed4e635
HW		 345 COLOR_DEPTH_UNDEFINED,
346 &black_color,
347 otg_active_width,
10b4e64e
WL		 348 otg_active_height,
349 0);
7ed4e635
HW		 350 }
351
f42ea55b 352 hws->funcs.wait_for_blank_complete(opp);
7ed4e635
HW		 353}
354
78c77382 355void dcn20_dsc_pg_control(
97bda032
HW		 356 struct dce_hwseq *hws,
357 unsigned int dsc_inst,
358 bool power_on)
359{
360 uint32_t power_gate = power_on ? 0 : 1;
361 uint32_t pwr_status = power_on ? 0 : 2;
98ce8cc1 362 uint32_t org_ip_request_cntl = 0;
97bda032
HW		 363
364 if (hws->ctx->dc->debug.disable_dsc_power_gate)
365 return;
366
367 if (REG(DOMAIN16_PG_CONFIG) == 0)
368 return;
369
98ce8cc1
NC		 370 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
371 if (org_ip_request_cntl == 0)
372 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
373
97bda032
HW		 374 switch (dsc_inst) {
375 case 0: /* DSC0 */
376 REG_UPDATE(DOMAIN16_PG_CONFIG,
377 DOMAIN16_POWER_GATE, power_gate);
378
379 REG_WAIT(DOMAIN16_PG_STATUS,
380 DOMAIN16_PGFSM_PWR_STATUS, pwr_status,
381 1, 1000);
382 break;
383 case 1: /* DSC1 */
384 REG_UPDATE(DOMAIN17_PG_CONFIG,
385 DOMAIN17_POWER_GATE, power_gate);
386
387 REG_WAIT(DOMAIN17_PG_STATUS,
388 DOMAIN17_PGFSM_PWR_STATUS, pwr_status,
389 1, 1000);
390 break;
391 case 2: /* DSC2 */
392 REG_UPDATE(DOMAIN18_PG_CONFIG,
393 DOMAIN18_POWER_GATE, power_gate);
394
395 REG_WAIT(DOMAIN18_PG_STATUS,
396 DOMAIN18_PGFSM_PWR_STATUS, pwr_status,
397 1, 1000);
398 break;
399 case 3: /* DSC3 */
400 REG_UPDATE(DOMAIN19_PG_CONFIG,
401 DOMAIN19_POWER_GATE, power_gate);
402
403 REG_WAIT(DOMAIN19_PG_STATUS,
404 DOMAIN19_PGFSM_PWR_STATUS, pwr_status,
405 1, 1000);
406 break;
407 case 4: /* DSC4 */
408 REG_UPDATE(DOMAIN20_PG_CONFIG,
409 DOMAIN20_POWER_GATE, power_gate);
410
411 REG_WAIT(DOMAIN20_PG_STATUS,
412 DOMAIN20_PGFSM_PWR_STATUS, pwr_status,
413 1, 1000);
414 break;
415 case 5: /* DSC5 */
416 REG_UPDATE(DOMAIN21_PG_CONFIG,
417 DOMAIN21_POWER_GATE, power_gate);
418
419 REG_WAIT(DOMAIN21_PG_STATUS,
420 DOMAIN21_PGFSM_PWR_STATUS, pwr_status,
421 1, 1000);
422 break;
423 default:
424 BREAK_TO_DEBUGGER();
425 break;
426 }
98ce8cc1
NC		 427
428 if (org_ip_request_cntl == 0)
429 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
97bda032 430}
7ed4e635 431
78c77382 432void dcn20_dpp_pg_control(
7ed4e635
HW		 433 struct dce_hwseq *hws,
434 unsigned int dpp_inst,
435 bool power_on)
436{
437 uint32_t power_gate = power_on ? 0 : 1;
438 uint32_t pwr_status = power_on ? 0 : 2;
439
440 if (hws->ctx->dc->debug.disable_dpp_power_gate)
441 return;
442 if (REG(DOMAIN1_PG_CONFIG) == 0)
443 return;
444
445 switch (dpp_inst) {
446 case 0: /* DPP0 */
447 REG_UPDATE(DOMAIN1_PG_CONFIG,
448 DOMAIN1_POWER_GATE, power_gate);
449
450 REG_WAIT(DOMAIN1_PG_STATUS,
451 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
452 1, 1000);
453 break;
454 case 1: /* DPP1 */
455 REG_UPDATE(DOMAIN3_PG_CONFIG,
456 DOMAIN3_POWER_GATE, power_gate);
457
458 REG_WAIT(DOMAIN3_PG_STATUS,
459 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
460 1, 1000);
461 break;
462 case 2: /* DPP2 */
463 REG_UPDATE(DOMAIN5_PG_CONFIG,
464 DOMAIN5_POWER_GATE, power_gate);
465
466 REG_WAIT(DOMAIN5_PG_STATUS,
467 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
468 1, 1000);
469 break;
470 case 3: /* DPP3 */
471 REG_UPDATE(DOMAIN7_PG_CONFIG,
472 DOMAIN7_POWER_GATE, power_gate);
473
474 REG_WAIT(DOMAIN7_PG_STATUS,
475 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
476 1, 1000);
477 break;
478 case 4: /* DPP4 */
479 REG_UPDATE(DOMAIN9_PG_CONFIG,
480 DOMAIN9_POWER_GATE, power_gate);
481
482 REG_WAIT(DOMAIN9_PG_STATUS,
483 DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
484 1, 1000);
485 break;
486 case 5: /* DPP5 */
487 /*
488 * Do not power gate DPP5, should be left at HW default, power on permanently.
489 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
490 * reset.
491 * REG_UPDATE(DOMAIN11_PG_CONFIG,
492 * DOMAIN11_POWER_GATE, power_gate);
493 *
494 * REG_WAIT(DOMAIN11_PG_STATUS,
495 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status,
496 * 1, 1000);
497 */
498 break;
499 default:
500 BREAK_TO_DEBUGGER();
501 break;
502 }
503}
504
505
78c77382 506void dcn20_hubp_pg_control(
7ed4e635
HW		 507 struct dce_hwseq *hws,
508 unsigned int hubp_inst,
509 bool power_on)
510{
511 uint32_t power_gate = power_on ? 0 : 1;
512 uint32_t pwr_status = power_on ? 0 : 2;
513
514 if (hws->ctx->dc->debug.disable_hubp_power_gate)
515 return;
516 if (REG(DOMAIN0_PG_CONFIG) == 0)
517 return;
518
519 switch (hubp_inst) {
520 case 0: /* DCHUBP0 */
521 REG_UPDATE(DOMAIN0_PG_CONFIG,
522 DOMAIN0_POWER_GATE, power_gate);
523
524 REG_WAIT(DOMAIN0_PG_STATUS,
525 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
526 1, 1000);
527 break;
528 case 1: /* DCHUBP1 */
529 REG_UPDATE(DOMAIN2_PG_CONFIG,
530 DOMAIN2_POWER_GATE, power_gate);
531
532 REG_WAIT(DOMAIN2_PG_STATUS,
533 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
534 1, 1000);
535 break;
536 case 2: /* DCHUBP2 */
537 REG_UPDATE(DOMAIN4_PG_CONFIG,
538 DOMAIN4_POWER_GATE, power_gate);
539
540 REG_WAIT(DOMAIN4_PG_STATUS,
541 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
542 1, 1000);
543 break;
544 case 3: /* DCHUBP3 */
545 REG_UPDATE(DOMAIN6_PG_CONFIG,
546 DOMAIN6_POWER_GATE, power_gate);
547
548 REG_WAIT(DOMAIN6_PG_STATUS,
549 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
550 1, 1000);
551 break;
552 case 4: /* DCHUBP4 */
553 REG_UPDATE(DOMAIN8_PG_CONFIG,
554 DOMAIN8_POWER_GATE, power_gate);
555
556 REG_WAIT(DOMAIN8_PG_STATUS,
557 DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
558 1, 1000);
559 break;
560 case 5: /* DCHUBP5 */
561 /*
562 * Do not power gate DCHUB5, should be left at HW default, power on permanently.
563 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
564 * reset.
565 * REG_UPDATE(DOMAIN10_PG_CONFIG,
566 * DOMAIN10_POWER_GATE, power_gate);
567 *
568 * REG_WAIT(DOMAIN10_PG_STATUS,
569 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status,
570 * 1, 1000);
571 */
572 break;
573 default:
574 BREAK_TO_DEBUGGER();
575 break;
576 }
577}
578
579
7ed4e635
HW		 580/* disable HW used by plane.
581 * note: cannot disable until disconnect is complete
582 */
78c77382 583void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
7ed4e635 584{
f42ea55b 585 struct dce_hwseq *hws = dc->hwseq;
7ed4e635
HW		 586 struct hubp *hubp = pipe_ctx->plane_res.hubp;
587 struct dpp *dpp = pipe_ctx->plane_res.dpp;
7ed4e635
HW		 588
589 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
590
6bd8d7d3
AC		 591 /* In flip immediate with pipe splitting case GSL is used for
592 * synchronization so we must disable it when the plane is disabled.
593 */
594 if (pipe_ctx->stream_res.gsl_group != 0)
595 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);
596
a5b50a0c
AL		 597 if (hubp->funcs->hubp_update_mall_sel)
598 hubp->funcs->hubp_update_mall_sel(hubp, 0, false);
599
6bd8d7d3
AC		 600 dc->hwss.set_flip_control_gsl(pipe_ctx, false);
601
7ed4e635
HW		 602 hubp->funcs->hubp_clk_cntl(hubp, false);
603
604 dpp->funcs->dpp_dppclk_control(dpp, false, false);
605
7ed4e635 606 hubp->power_gated = true;
7ed4e635 607
f42ea55b 608 hws->funcs.plane_atomic_power_down(dc,
8a31820b
ML		 609 pipe_ctx->plane_res.dpp,
610 pipe_ctx->plane_res.hubp);
7ed4e635
HW		 611
612 pipe_ctx->stream = NULL;
613 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
614 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
615 pipe_ctx->top_pipe = NULL;
616 pipe_ctx->bottom_pipe = NULL;
617 pipe_ctx->plane_state = NULL;
618}
619
620
ff344c8d 621void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
7ed4e635 622{
a5b50a0c
AL		 623 bool is_phantom = pipe_ctx->plane_state && pipe_ctx->plane_state->is_phantom;
624 struct timing_generator *tg = is_phantom ? pipe_ctx->stream_res.tg : NULL;
625
7ed4e635
HW		 626 DC_LOGGER_INIT(dc->ctx->logger);
627
628 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
629 return;
630
631 dcn20_plane_atomic_disable(dc, pipe_ctx);
632
a5b50a0c
AL		 633 /* Turn back off the phantom OTG after the phantom plane is fully disabled
634 */
635 if (is_phantom)
636 if (tg && tg->funcs->disable_phantom_crtc)
637 tg->funcs->disable_phantom_crtc(tg);
638
7ed4e635
HW		 639 DC_LOG_DC("Power down front end %d\n",
640 pipe_ctx->pipe_idx);
641}
642
4866b0bf
ML		 643void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank)
644{
645 dcn20_blank_pixel_data(dc, pipe_ctx, blank);
646}
647
d99f1387
BL		 648static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
649 int opp_cnt)
650{
651 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing);
652 int flow_ctrl_cnt;
653
2665fded 654 if (opp_cnt >= 2)
d99f1387
BL		 655 hblank_halved = true;
656
657 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable -
658 stream->timing.h_border_left -
659 stream->timing.h_border_right;
660
661 if (hblank_halved)
662 flow_ctrl_cnt /= 2;
663
664 /* ODM combine 4:1 case */
665 if (opp_cnt == 4)
666 flow_ctrl_cnt /= 2;
667
668 return flow_ctrl_cnt;
669}
d99f1387 670
7ed4e635
HW		 671enum dc_status dcn20_enable_stream_timing(
672 struct pipe_ctx *pipe_ctx,
673 struct dc_state *context,
674 struct dc *dc)
675{
f42ea55b 676 struct dce_hwseq *hws = dc->hwseq;
7ed4e635 677 struct dc_stream_state *stream = pipe_ctx->stream;
7ed4e635
HW		 678 struct drr_params params = {0};
679 unsigned int event_triggers = 0;
b1f6d01c
DL		 680 struct pipe_ctx *odm_pipe;
681 int opp_cnt = 1;
682 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
d99f1387
BL		 683 bool interlace = stream->timing.flags.INTERLACE;
684 int i;
d99f1387
BL		 685 struct mpc_dwb_flow_control flow_control;
686 struct mpc *mpc = dc->res_pool->mpc;
687 bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing));
49f59499
JL		 688 unsigned int k1_div = PIXEL_RATE_DIV_NA;
689 unsigned int k2_div = PIXEL_RATE_DIV_NA;
d99f1387 690
49f59499
JL		 691 if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {
692 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
693
694 dc->res_pool->dccg->funcs->set_pixel_rate_div(
695 dc->res_pool->dccg,
696 pipe_ctx->stream_res.tg->inst,
697 k1_div, k2_div);
698 }
7ed4e635
HW		 699 /* by upper caller loop, pipe0 is parent pipe and be called first.
700 * back end is set up by for pipe0. Other children pipe share back end
701 * with pipe 0. No program is needed.
702 */
703 if (pipe_ctx->top_pipe != NULL)
704 return DC_OK;
705
706 /* TODO check if timing_changed, disable stream if timing changed */
707
b1f6d01c
DL		 708 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
709 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
710 opp_cnt++;
711 }
2b162fd3 712
b1f6d01c 713 if (opp_cnt > 1)
7ed4e635
HW		 714 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
715 pipe_ctx->stream_res.tg,
b1f6d01c 716 opp_inst, opp_cnt,
2b162fd3 717 &pipe_ctx->stream->timing);
b1f6d01c 718
7ed4e635
HW		 719 /* HW program guide assume display already disable
720 * by unplug sequence. OTG assume stop.
721 */
722 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
723
724 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
725 pipe_ctx->clock_source,
726 &pipe_ctx->stream_res.pix_clk_params,
98ce7d32 727 dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),
7ed4e635
HW		 728 &pipe_ctx->pll_settings)) {
729 BREAK_TO_DEBUGGER();
730 return DC_ERROR_UNEXPECTED;
731 }
732
9c75891f
WL		 733 if (dc_is_hdmi_tmds_signal(stream->signal)) {
734 stream->link->phy_state.symclk_ref_cnts.otg = 1;
735 if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF)
736 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
737 else
738 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
739 }
740
1ef893e2
YS		 741 if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal)))
742 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);
743
7ed4e635
HW		 744 pipe_ctx->stream_res.tg->funcs->program_timing(
745 pipe_ctx->stream_res.tg,
746 &stream->timing,
747 pipe_ctx->pipe_dlg_param.vready_offset,
748 pipe_ctx->pipe_dlg_param.vstartup_start,
749 pipe_ctx->pipe_dlg_param.vupdate_offset,
750 pipe_ctx->pipe_dlg_param.vupdate_width,
751 pipe_ctx->stream->signal,
752 true);
753
d99f1387
BL		 754 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1;
755 flow_control.flow_ctrl_mode = 0;
756 flow_control.flow_ctrl_cnt0 = 0x80;
757 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt);
758 if (mpc->funcs->set_out_rate_control) {
759 for (i = 0; i < opp_cnt; ++i) {
760 mpc->funcs->set_out_rate_control(
761 mpc, opp_inst[i],
762 true,
763 rate_control_2x_pclk,
764 &flow_control);
765 }
766 }
20f2ffe5 767
b1f6d01c 768 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
7ed4e635
HW		 769 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
770 odm_pipe->stream_res.opp,
771 true);
772
7ed4e635
HW		 773 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
774 pipe_ctx->stream_res.opp,
775 true);
776
f42ea55b 777 hws->funcs.blank_pixel_data(dc, pipe_ctx, true);
7ed4e635
HW		 778
779 /* VTG is within DCHUB command block. DCFCLK is always on */
780 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
781 BREAK_TO_DEBUGGER();
782 return DC_ERROR_UNEXPECTED;
783 }
784
f42ea55b 785 hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp);
7ed4e635
HW		 786
787 params.vertical_total_min = stream->adjust.v_total_min;
788 params.vertical_total_max = stream->adjust.v_total_max;
470e2ca5
BZ		 789 params.vertical_total_mid = stream->adjust.v_total_mid;
790 params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num;
7ed4e635
HW		 791 if (pipe_ctx->stream_res.tg->funcs->set_drr)
792 pipe_ctx->stream_res.tg->funcs->set_drr(
793 pipe_ctx->stream_res.tg, &params);
794
795 // DRR should set trigger event to monitor surface update event
796 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
797 event_triggers = 0x80;
5b5abe95
AK		 798 /* Event triggers and num frames initialized for DRR, but can be
799 * later updated for PSR use. Note DRR trigger events are generated
800 * regardless of whether num frames met.
801 */
7ed4e635
HW		 802 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
803 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
5b5abe95 804 pipe_ctx->stream_res.tg, event_triggers, 2);
7ed4e635
HW		 805
806 /* TODO program crtc source select for non-virtual signal*/
807 /* TODO program FMT */
808 /* TODO setup link_enc */
809 /* TODO set stream attributes */
810 /* TODO program audio */
811 /* TODO enable stream if timing changed */
812 /* TODO unblank stream if DP */
813
d3dfceb5
AP		 814 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) {
815 if (pipe_ctx->stream_res.tg && pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable)
816 pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg);
817 }
7ed4e635
HW		 818 return DC_OK;
819}
820
821void dcn20_program_output_csc(struct dc *dc,
822 struct pipe_ctx *pipe_ctx,
823 enum dc_color_space colorspace,
824 uint16_t *matrix,
825 int opp_id)
826{
827 struct mpc *mpc = dc->res_pool->mpc;
828 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
54461859
CL		 829 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
830
831 if (mpc->funcs->power_on_mpc_mem_pwr)
832 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
7ed4e635
HW		 833
834 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
835 if (mpc->funcs->set_output_csc != NULL)
836 mpc->funcs->set_output_csc(mpc,
837 opp_id,
838 matrix,
839 ocsc_mode);
840 } else {
841 if (mpc->funcs->set_ocsc_default != NULL)
842 mpc->funcs->set_ocsc_default(mpc,
843 opp_id,
844 colorspace,
845 ocsc_mode);
846 }
847}
848
78c77382 849bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
7ed4e635
HW		 850 const struct dc_stream_state *stream)
851{
852 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
853 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
854 struct pwl_params *params = NULL;
855 /*
856 * program OGAM only for the top pipe
857 * if there is a pipe split then fix diagnostic is required:
858 * how to pass OGAM parameter for stream.
859 * if programming for all pipes is required then remove condition
860 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic.
861 */
54461859
CL		 862 if (mpc->funcs->power_on_mpc_mem_pwr)
863 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
b1f6d01c 864 if (pipe_ctx->top_pipe == NULL
7ed4e635
HW		 865 && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
866 if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
867 params = &stream->out_transfer_func->pwl;
868 else if (pipe_ctx->stream->out_transfer_func->type ==
869 TF_TYPE_DISTRIBUTED_POINTS &&
870 cm_helper_translate_curve_to_hw_format(
871 stream->out_transfer_func,
872 &mpc->blender_params, false))
873 params = &mpc->blender_params;
874 /*
875 * there is no ROM
876 */
877 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
878 BREAK_TO_DEBUGGER();
879 }
880 /*
881 * if above if is not executed then 'params' equal to 0 and set in bypass
882 */
883 mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
884
885 return true;
886}
887
ff344c8d 888bool dcn20_set_blend_lut(
7ed4e635
HW		 889 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
890{
891 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
892 bool result = true;
893 struct pwl_params *blend_lut = NULL;
894
895 if (plane_state->blend_tf) {
896 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
897 blend_lut = &plane_state->blend_tf->pwl;
898 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
899 cm_helper_translate_curve_to_hw_format(
900 plane_state->blend_tf,
901 &dpp_base->regamma_params, false);
902 blend_lut = &dpp_base->regamma_params;
903 }
904 }
905 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
906
907 return result;
908}
909
ff344c8d 910bool dcn20_set_shaper_3dlut(
7ed4e635
HW		 911 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
912{
913 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
914 bool result = true;
915 struct pwl_params *shaper_lut = NULL;
916
917 if (plane_state->in_shaper_func) {
918 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
919 shaper_lut = &plane_state->in_shaper_func->pwl;
920 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
921 cm_helper_translate_curve_to_hw_format(
922 plane_state->in_shaper_func,
923 &dpp_base->shaper_params, true);
924 shaper_lut = &dpp_base->shaper_params;
925 }
926 }
927
928 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut);
929 if (plane_state->lut3d_func &&
a2080098 930 plane_state->lut3d_func->state.bits.initialized == 1)
7ed4e635
HW		 931 result = dpp_base->funcs->dpp_program_3dlut(dpp_base,
932 &plane_state->lut3d_func->lut_3d);
933 else
934 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL);
935
7ed4e635
HW		 936 return result;
937}
938
78c77382
AK		 939bool dcn20_set_input_transfer_func(struct dc *dc,
940 struct pipe_ctx *pipe_ctx,
941 const struct dc_plane_state *plane_state)
7ed4e635 942{
f42ea55b 943 struct dce_hwseq *hws = dc->hwseq;
7ed4e635
HW		 944 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
945 const struct dc_transfer_func *tf = NULL;
946 bool result = true;
947 bool use_degamma_ram = false;
948
949 if (dpp_base == NULL || plane_state == NULL)
950 return false;
951
f42ea55b
AK		 952 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
953 hws->funcs.set_blend_lut(pipe_ctx, plane_state);
7ed4e635
HW		 954
955 if (plane_state->in_transfer_func)
956 tf = plane_state->in_transfer_func;
957
958
959 if (tf == NULL) {
960 dpp_base->funcs->dpp_set_degamma(dpp_base,
961 IPP_DEGAMMA_MODE_BYPASS);
962 return true;
963 }
964
965 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS)
966 use_degamma_ram = true;
967
968 if (use_degamma_ram == true) {
969 if (tf->type == TF_TYPE_HWPWL)
970 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
971 &tf->pwl);
972 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
973 cm_helper_translate_curve_to_degamma_hw_format(tf,
974 &dpp_base->degamma_params);
975 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
976 &dpp_base->degamma_params);
977 }
978 return true;
979 }
980 /* handle here the optimized cases when de-gamma ROM could be used.
981 *
982 */
983 if (tf->type == TF_TYPE_PREDEFINED) {
984 switch (tf->tf) {
985 case TRANSFER_FUNCTION_SRGB:
986 dpp_base->funcs->dpp_set_degamma(dpp_base,
987 IPP_DEGAMMA_MODE_HW_sRGB);
988 break;
989 case TRANSFER_FUNCTION_BT709:
990 dpp_base->funcs->dpp_set_degamma(dpp_base,
991 IPP_DEGAMMA_MODE_HW_xvYCC);
992 break;
993 case TRANSFER_FUNCTION_LINEAR:
994 dpp_base->funcs->dpp_set_degamma(dpp_base,
995 IPP_DEGAMMA_MODE_BYPASS);
996 break;
997 case TRANSFER_FUNCTION_PQ:
e6616410
RA		 998 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL);
999 cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params);
1000 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params);
1001 result = true;
1002 break;
7ed4e635
HW		 1003 default:
1004 result = false;
1005 break;
1006 }
1007 } else if (tf->type == TF_TYPE_BYPASS)
1008 dpp_base->funcs->dpp_set_degamma(dpp_base,
1009 IPP_DEGAMMA_MODE_BYPASS);
1010 else {
1011 /*
1012 * if we are here, we did not handle correctly.
1013 * fix is required for this use case
1014 */
1015 BREAK_TO_DEBUGGER();
1016 dpp_base->funcs->dpp_set_degamma(dpp_base,
1017 IPP_DEGAMMA_MODE_BYPASS);
1018 }
1019
1020 return result;
1021}
1022
78c77382 1023void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
7ed4e635 1024{
b1f6d01c
DL		 1025 struct pipe_ctx *odm_pipe;
1026 int opp_cnt = 1;
1027 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
7ed4e635 1028
b1f6d01c
DL		 1029 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1030 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
1031 opp_cnt++;
1032 }
2b162fd3 1033
b1f6d01c 1034 if (opp_cnt > 1)
7ed4e635
HW		 1035 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
1036 pipe_ctx->stream_res.tg,
b1f6d01c 1037 opp_inst, opp_cnt,
2b162fd3 1038 &pipe_ctx->stream->timing);
b1f6d01c 1039 else
7ed4e635
HW		 1040 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
1041 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1042}
1043
1044void dcn20_blank_pixel_data(
1045 struct dc *dc,
1046 struct pipe_ctx *pipe_ctx,
1047 bool blank)
1048{
7ed4e635
HW		 1049 struct tg_color black_color = {0};
1050 struct stream_resource *stream_res = &pipe_ctx->stream_res;
1051 struct dc_stream_state *stream = pipe_ctx->stream;
324707fd 1052 enum dc_color_space color_space = stream->output_color_space;
7ed4e635 1053 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
2057b7e1 1054 enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
b1f6d01c
DL		 1055 struct pipe_ctx *odm_pipe;
1056 int odm_cnt = 1;
7ed4e635 1057
7ed4e635
HW		 1058 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
1059 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
1060
31635887
WL		 1061 if (stream->link->test_pattern_enabled)
1062 return;
1063
324707fd 1064 /* get opp dpg blank color */
7ed4e635
HW		 1065 color_space_to_black_color(dc, color_space, &black_color);
1066
b1f6d01c
DL		 1067 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1068 odm_cnt++;
1069
1070 width = width / odm_cnt;
7ed4e635
HW		 1071
1072 if (blank) {
3ba01817 1073 dc->hwss.set_abm_immediate_disable(pipe_ctx);
7ed4e635 1074
2057b7e1 1075 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {
324707fd 1076 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
2057b7e1
WL		 1077 test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
1078 }
324707fd
JA		 1079 } else {
1080 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
1081 }
7ed4e635 1082
dbf5256b
JA		 1083 dc->hwss.set_disp_pattern_generator(dc,
1084 pipe_ctx,
7ed4e635 1085 test_pattern,
2057b7e1 1086 test_pattern_color_space,
7ed4e635
HW		 1087 stream->timing.display_color_depth,
1088 &black_color,
1089 width,
10b4e64e
WL		 1090 height,
1091 0);
7ed4e635 1092
b1f6d01c 1093 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
dbf5256b
JA		 1094 dc->hwss.set_disp_pattern_generator(dc,
1095 odm_pipe,
436d9635 1096 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ?
324707fd 1097 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
2057b7e1 1098 test_pattern_color_space,
7ed4e635
HW		 1099 stream->timing.display_color_depth,
1100 &black_color,
1101 width,
10b4e64e
WL		 1102 height,
1103 0);
7ed4e635
HW		 1104 }
1105
7fbf451e
DV		 1106 if (!blank && dc->debug.enable_single_display_2to1_odm_policy) {
1107 /* when exiting dynamic ODM need to reinit DPG state for unused pipes */
1108 struct pipe_ctx *old_odm_pipe = dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx].next_odm_pipe;
1109
1110 odm_pipe = pipe_ctx->next_odm_pipe;
1111
1112 while (old_odm_pipe) {
1113 if (!odm_pipe || old_odm_pipe->pipe_idx != odm_pipe->pipe_idx)
1114 dc->hwss.set_disp_pattern_generator(dc,
1115 old_odm_pipe,
1116 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
1117 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
1118 COLOR_DEPTH_888,
1119 NULL,
1120 0,
1121 0,
1122 0);
1123 old_odm_pipe = old_odm_pipe->next_odm_pipe;
1124 if (odm_pipe)
1125 odm_pipe = odm_pipe->next_odm_pipe;
1126 }
1127 }
1128
7ed4e635
HW		 1129 if (!blank)
1130 if (stream_res->abm) {
474ac4a8 1131 dc->hwss.set_pipe(pipe_ctx);
7ed4e635
HW		 1132 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
1133 }
1134}
1135
1136
bf224e00 1137static void dcn20_power_on_plane_resources(
7ed4e635
HW		 1138 struct dce_hwseq *hws,
1139 struct pipe_ctx *pipe_ctx)
1140{
1141 DC_LOGGER_INIT(hws->ctx->logger);
bf224e00
NK		 1142
1143 if (hws->funcs.dpp_root_clock_control)
1144 hws->funcs.dpp_root_clock_control(hws, pipe_ctx->plane_res.dpp->inst, true);
1145
7ed4e635
HW		 1146 if (REG(DC_IP_REQUEST_CNTL)) {
1147 REG_SET(DC_IP_REQUEST_CNTL, 0,
1148 IP_REQUEST_EN, 1);
c74f865f
NK		 1149
1150 if (hws->funcs.dpp_pg_control)
1151 hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);
1152
1153 if (hws->funcs.hubp_pg_control)
1154 hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);
1155
7ed4e635
HW		 1156 REG_SET(DC_IP_REQUEST_CNTL, 0,
1157 IP_REQUEST_EN, 0);
1158 DC_LOG_DEBUG(
1159 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);
1160 }
1161}
1162
240e6d25
IB		 1163static void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,
1164 struct dc_state *context)
7ed4e635
HW		 1165{
1166 //if (dc->debug.sanity_checks) {
1167 // dcn10_verify_allow_pstate_change_high(dc);
1168 //}
bf224e00 1169 dcn20_power_on_plane_resources(dc->hwseq, pipe_ctx);
7ed4e635
HW		 1170
1171 /* enable DCFCLK current DCHUB */
1172 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1173
89cb5614
ZYL		 1174 /* initialize HUBP on power up */
1175 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);
1176
7ed4e635
HW		 1177 /* make sure OPP_PIPE_CLOCK_EN = 1 */
1178 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1179 pipe_ctx->stream_res.opp,
1180 true);
1181
1182/* TODO: enable/disable in dm as per update type.
1183 if (plane_state) {
1184 DC_LOG_DC(dc->ctx->logger,
1185 "Pipe:%d 0x%x: addr hi:0x%x, "
1186 "addr low:0x%x, "
1187 "src: %d, %d, %d,"
1188 " %d; dst: %d, %d, %d, %d;\n",
1189 pipe_ctx->pipe_idx,
1190 plane_state,
1191 plane_state->address.grph.addr.high_part,
1192 plane_state->address.grph.addr.low_part,
1193 plane_state->src_rect.x,
1194 plane_state->src_rect.y,
1195 plane_state->src_rect.width,
1196 plane_state->src_rect.height,
1197 plane_state->dst_rect.x,
1198 plane_state->dst_rect.y,
1199 plane_state->dst_rect.width,
1200 plane_state->dst_rect.height);
1201
1202 DC_LOG_DC(dc->ctx->logger,
1203 "Pipe %d: width, height, x, y format:%d\n"
1204 "viewport:%d, %d, %d, %d\n"
1205 "recout: %d, %d, %d, %d\n",
1206 pipe_ctx->pipe_idx,
1207 plane_state->format,
1208 pipe_ctx->plane_res.scl_data.viewport.width,
1209 pipe_ctx->plane_res.scl_data.viewport.height,
1210 pipe_ctx->plane_res.scl_data.viewport.x,
1211 pipe_ctx->plane_res.scl_data.viewport.y,
1212 pipe_ctx->plane_res.scl_data.recout.width,
1213 pipe_ctx->plane_res.scl_data.recout.height,
1214 pipe_ctx->plane_res.scl_data.recout.x,
1215 pipe_ctx->plane_res.scl_data.recout.y);
1216 print_rq_dlg_ttu(dc, pipe_ctx);
1217 }
1218*/
bda9afda 1219 if (dc->vm_pa_config.valid) {
7ed4e635
HW		 1220 struct vm_system_aperture_param apt;
1221
1222 apt.sys_default.quad_part = 0;
7ed4e635 1223
6d988a55
JL		 1224 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr;
1225 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr;
7ed4e635
HW		 1226
1227 // Program system aperture settings
1228 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);
1229 }
1230
0c66824b
QZ		 1231 if (!pipe_ctx->top_pipe
1232 && pipe_ctx->plane_state
1233 && pipe_ctx->plane_state->flip_int_enabled
1234 && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)
1235 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);
1236
7ed4e635
HW		 1237// if (dc->debug.sanity_checks) {
1238// dcn10_verify_allow_pstate_change_high(dc);
1239// }
1240}
1241
ff344c8d 1242void dcn20_pipe_control_lock(
7ed4e635
HW		 1243 struct dc *dc,
1244 struct pipe_ctx *pipe,
1245 bool lock)
1246{
6f2239cc 1247 struct pipe_ctx *temp_pipe;
7ed4e635
HW		 1248 bool flip_immediate = false;
1249
1250 /* use TG master update lock to lock everything on the TG
1251 * therefore only top pipe need to lock
1252 */
009114f6 1253 if (!pipe || pipe->top_pipe)
7ed4e635
HW		 1254 return;
1255
1256 if (pipe->plane_state != NULL)
1257 flip_immediate = pipe->plane_state->flip_immediate;
1258
4f6274b3
AL		 1259 if (pipe->stream_res.gsl_group > 0) {
1260 temp_pipe = pipe->bottom_pipe;
1261 while (!flip_immediate && temp_pipe) {
1262 if (temp_pipe->plane_state != NULL)
1263 flip_immediate = temp_pipe->plane_state->flip_immediate;
1264 temp_pipe = temp_pipe->bottom_pipe;
1265 }
6f2239cc
AL		 1266 }
1267
0e29be9e
AD		 1268 if (flip_immediate && lock) {
1269 const int TIMEOUT_FOR_FLIP_PENDING = 100000;
1270 int i;
1271
e9917ef8
AC		 1272 temp_pipe = pipe;
1273 while (temp_pipe) {
1274 if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) {
1275 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
1276 if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp))
1277 break;
1278 udelay(1);
1279 }
1280
1281 /* no reason it should take this long for immediate flips */
1282 ASSERT(i != TIMEOUT_FOR_FLIP_PENDING);
0e29be9e 1283 }
e9917ef8 1284 temp_pipe = temp_pipe->bottom_pipe;
0e29be9e
AD		 1285 }
1286 }
1287
7ed4e635
HW		 1288 /* In flip immediate and pipe splitting case, we need to use GSL
1289 * for synchronization. Only do setup on locking and on flip type change.
1290 */
86c5a9e3 1291 if (lock && (pipe->bottom_pipe != NULL || !flip_immediate))
7ed4e635
HW		 1292 if ((flip_immediate && pipe->stream_res.gsl_group == 0) ||
1293 (!flip_immediate && pipe->stream_res.gsl_group > 0))
2e2e73fc 1294 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
7ed4e635 1295
ec76bd6f
AL		 1296 if (pipe->plane_state != NULL)
1297 flip_immediate = pipe->plane_state->flip_immediate;
1298
6f2239cc
AL		 1299 temp_pipe = pipe->bottom_pipe;
1300 while (flip_immediate && temp_pipe) {
1301 if (temp_pipe->plane_state != NULL)
1302 flip_immediate = temp_pipe->plane_state->flip_immediate;
1303 temp_pipe = temp_pipe->bottom_pipe;
1304 }
1305
1306 if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state &&
1307 !flip_immediate)
1308 dcn20_setup_gsl_group_as_lock(dc, pipe, false);
1309
dc6e2448
WW		 1310 if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) {
1311 union dmub_hw_lock_flags hw_locks = { 0 };
1312 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
1313
1314 hw_locks.bits.lock_pipe = 1;
1315 inst_flags.otg_inst = pipe->stream_res.tg->inst;
1316
1317 if (pipe->plane_state != NULL)
1318 hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips;
1319
1320 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
1321 lock,
1322 &hw_locks,
1323 &inst_flags);
1324 } else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {
7ed4e635
HW		 1325 if (lock)
1326 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);
1327 else
1328 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg);
1329 } else {
1330 if (lock)
1331 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1332 else
1333 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1334 }
1335}
1336
b6e881c9 1337static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe)
7ed4e635 1338{
b6e881c9 1339 new_pipe->update_flags.raw = 0;
7ed4e635 1340
e267f5e6
AL		 1341 /* If non-phantom pipe is being transitioned to a phantom pipe,
1342 * set disable and return immediately. This is because the pipe
1343 * that was previously in use must be fully disabled before we
1344 * can "enable" it as a phantom pipe (since the OTG will certainly
1345 * be different). The post_unlock sequence will set the correct
1346 * update flags to enable the phantom pipe.
1347 */
1348 if (old_pipe->plane_state && !old_pipe->plane_state->is_phantom &&
1349 new_pipe->plane_state && new_pipe->plane_state->is_phantom) {
1350 new_pipe->update_flags.bits.disable = 1;
1351 return;
1352 }
1353
b6e881c9
DL		 1354 /* Exit on unchanged, unused pipe */
1355 if (!old_pipe->plane_state && !new_pipe->plane_state)
7ed4e635 1356 return;
b6e881c9 1357 /* Detect pipe enable/disable */
c0838cbe 1358 if (!old_pipe->plane_state && new_pipe->plane_state) {
b6e881c9
DL		 1359 new_pipe->update_flags.bits.enable = 1;
1360 new_pipe->update_flags.bits.mpcc = 1;
1361 new_pipe->update_flags.bits.dppclk = 1;
1362 new_pipe->update_flags.bits.hubp_interdependent = 1;
1363 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
fe9fa385 1364 new_pipe->update_flags.bits.unbounded_req = 1;
b6e881c9
DL		 1365 new_pipe->update_flags.bits.gamut_remap = 1;
1366 new_pipe->update_flags.bits.scaler = 1;
1367 new_pipe->update_flags.bits.viewport = 1;
ba5a5371 1368 new_pipe->update_flags.bits.det_size = 1;
b6e881c9
DL		 1369 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1370 new_pipe->update_flags.bits.odm = 1;
1371 new_pipe->update_flags.bits.global_sync = 1;
1372 }
1373 return;
1374 }
85f4bc0c
AL		 1375
1376 /* For SubVP we need to unconditionally enable because any phantom pipes are
1377 * always removed then newly added for every full updates whenever SubVP is in use.
1378 * The remove-add sequence of the phantom pipe always results in the pipe
1379 * being blanked in enable_stream_timing (DPG).
1380 */
1381 if (new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM)
1382 new_pipe->update_flags.bits.enable = 1;
1383
14eb72ff
AL		 1384 /* Phantom pipes are effectively disabled, if the pipe was previously phantom
1385 * we have to enable
1386 */
1387 if (old_pipe->plane_state && old_pipe->plane_state->is_phantom &&
1388 new_pipe->plane_state && !new_pipe->plane_state->is_phantom)
1389 new_pipe->update_flags.bits.enable = 1;
1390
b6e881c9
DL		 1391 if (old_pipe->plane_state && !new_pipe->plane_state) {
1392 new_pipe->update_flags.bits.disable = 1;
1393 return;
1394 }
7ed4e635 1395
498563cf
JX		 1396 /* Detect plane change */
1397 if (old_pipe->plane_state != new_pipe->plane_state) {
1398 new_pipe->update_flags.bits.plane_changed = true;
1399 }
1400
b6e881c9
DL		 1401 /* Detect top pipe only changes */
1402 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1403 /* Detect odm changes */
1404 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe
1405 && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx)
1406 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe)
1407 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe)
1408 || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1409 new_pipe->update_flags.bits.odm = 1;
1410
1411 /* Detect global sync changes */
1412 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset
1413 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start
1414 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset
1415 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width)
1416 new_pipe->update_flags.bits.global_sync = 1;
1417 }
21ffcc94 1418
ba5a5371
NK		 1419 if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb)
1420 new_pipe->update_flags.bits.det_size = 1;
8fe44c08 1421
b6e881c9
DL		 1422 /*
1423 * Detect opp / tg change, only set on change, not on enable
1424 * Assume mpcc inst = pipe index, if not this code needs to be updated
1425 * since mpcc is what is affected by these. In fact all of our sequence
1426 * makes this assumption at the moment with how hubp reset is matched to
1427 * same index mpcc reset.
1428 */
1429 if (old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1430 new_pipe->update_flags.bits.opp_changed = 1;
1431 if (old_pipe->stream_res.tg != new_pipe->stream_res.tg)
1432 new_pipe->update_flags.bits.tg_changed = 1;
1433
ed8ec123
DL		 1434 /*
1435 * Detect mpcc blending changes, only dpp inst and opp matter here,
1436 * mpccs getting removed/inserted update connected ones during their own
1437 * programming
1438 */
b6e881c9 1439 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp
ed8ec123 1440 || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
b6e881c9
DL		 1441 new_pipe->update_flags.bits.mpcc = 1;
1442
1443 /* Detect dppclk change */
1444 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz)
1445 new_pipe->update_flags.bits.dppclk = 1;
1446
1447 /* Check for scl update */
1448 if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data)))
1449 new_pipe->update_flags.bits.scaler = 1;
1450 /* Check for vp update */
1451 if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect))
1452 || memcmp(&old_pipe->plane_res.scl_data.viewport_c,
1453 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect)))
1454 new_pipe->update_flags.bits.viewport = 1;
1455
1456 /* Detect dlg/ttu/rq updates */
1457 {
1458 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs;
1459 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs;
1460 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs;
1461 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs;
1462
1463 /* Detect pipe interdependent updates */
1464 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch ||
1465 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch ||
1466 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c ||
1467 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank ||
1468 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank ||
1469 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip ||
1470 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip ||
1471 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l ||
1472 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c ||
1473 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l ||
1474 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l ||
1475 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c ||
1476 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l ||
1477 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c ||
1478 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 ||
1479 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 ||
1480 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank ||
1481 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) {
1482 old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch;
1483 old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch;
1484 old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c;
1485 old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank;
1486 old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank;
1487 old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip;
1488 old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip;
1489 old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l;
1490 old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c;
1491 old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l;
1492 old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l;
1493 old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c;
1494 old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l;
1495 old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c;
1496 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0;
1497 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1;
1498 old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank;
1499 old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip;
1500 new_pipe->update_flags.bits.hubp_interdependent = 1;
1501 }
1502 /* Detect any other updates to ttu/rq/dlg */
1503 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) ||
1504 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) ||
1505 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs)))
1506 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
21ffcc94 1507 }
fe9fa385
AL		 1508
1509 if (old_pipe->unbounded_req != new_pipe->unbounded_req)
1510 new_pipe->update_flags.bits.unbounded_req = 1;
b6e881c9 1511}
21ffcc94 1512
b6e881c9
DL		 1513static void dcn20_update_dchubp_dpp(
1514 struct dc *dc,
1515 struct pipe_ctx *pipe_ctx,
1516 struct dc_state *context)
1517{
f42ea55b 1518 struct dce_hwseq *hws = dc->hwseq;
b6e881c9
DL		 1519 struct hubp *hubp = pipe_ctx->plane_res.hubp;
1520 struct dpp *dpp = pipe_ctx->plane_res.dpp;
1521 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
d4965c53 1522 struct dccg *dccg = dc->res_pool->dccg;
cf27a6d1 1523 bool viewport_changed = false;
7ed4e635 1524
1ea8751b 1525 if (pipe_ctx->update_flags.bits.dppclk)
b6e881c9 1526 dpp->funcs->dpp_dppclk_control(dpp, false, true);
4e0cbbbf 1527
d4965c53
DM		 1528 if (pipe_ctx->update_flags.bits.enable)
1529 dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);
1530
b6e881c9
DL		 1531 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
1532 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
1533 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
1534 */
1535 if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) {
1536 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
1537
1538 hubp->funcs->hubp_setup(
1539 hubp,
1540 &pipe_ctx->dlg_regs,
1541 &pipe_ctx->ttu_regs,
1542 &pipe_ctx->rq_regs,
1543 &pipe_ctx->pipe_dlg_param);
1544 }
fe9fa385
AL		 1545
1546 if (pipe_ctx->update_flags.bits.unbounded_req && hubp->funcs->set_unbounded_requesting)
1547 hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req);
1548
b6e881c9
DL		 1549 if (pipe_ctx->update_flags.bits.hubp_interdependent)
1550 hubp->funcs->hubp_setup_interdependent(
1551 hubp,
1552 &pipe_ctx->dlg_regs,
1553 &pipe_ctx->ttu_regs);
1554
1555 if (pipe_ctx->update_flags.bits.enable ||
498563cf 1556 pipe_ctx->update_flags.bits.plane_changed ||
b6e881c9
DL		 1557 plane_state->update_flags.bits.bpp_change ||
1558 plane_state->update_flags.bits.input_csc_change ||
1559 plane_state->update_flags.bits.color_space_change ||
1560 plane_state->update_flags.bits.coeff_reduction_change) {
1561 struct dc_bias_and_scale bns_params = {0};
1562
1563 // program the input csc
1564 dpp->funcs->dpp_setup(dpp,
1565 plane_state->format,
1566 EXPANSION_MODE_ZERO,
1567 plane_state->input_csc_color_matrix,
1568 plane_state->color_space,
1569 NULL);
1570
1571 if (dpp->funcs->dpp_program_bias_and_scale) {
1572 //TODO :for CNVC set scale and bias registers if necessary
78c77382 1573 build_prescale_params(&bns_params, plane_state);
b6e881c9
DL		 1574 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1575 }
7ed4e635
HW		 1576 }
1577
b6e881c9 1578 if (pipe_ctx->update_flags.bits.mpcc
498563cf 1579 || pipe_ctx->update_flags.bits.plane_changed
b6e881c9
DL		 1580 || plane_state->update_flags.bits.global_alpha_change
1581 || plane_state->update_flags.bits.per_pixel_alpha_change) {
8b0fbb36 1582 // MPCC inst is equal to pipe index in practice
1380c1bf 1583 int mpcc_inst = hubp->inst;
8b0fbb36 1584 int opp_inst;
0120e8b8 1585 int opp_count = dc->res_pool->pipe_count;
8b0fbb36
NA		 1586
1587 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
1588 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
b6e881c9 1589 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
8b0fbb36
NA		 1590 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
1591 break;
b6e881c9 1592 }
7ed4e635 1593 }
f42ea55b 1594 hws->funcs.update_mpcc(dc, pipe_ctx);
b6e881c9 1595 }
7ed4e635 1596
b6e881c9
DL		 1597 if (pipe_ctx->update_flags.bits.scaler ||
1598 plane_state->update_flags.bits.scaling_change ||
1599 plane_state->update_flags.bits.position_change ||
1600 plane_state->update_flags.bits.per_pixel_alpha_change ||
1601 pipe_ctx->stream->update_flags.bits.scaling) {
1602 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;
a316db72 1603 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP);
b6e881c9
DL		 1604 /* scaler configuration */
1605 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
1606 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
1607 }
7ed4e635 1608
b6e881c9 1609 if (pipe_ctx->update_flags.bits.viewport ||
b34659de 1610 (context == dc->current_state && plane_state->update_flags.bits.position_change) ||
b6e881c9 1611 (context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||
cf27a6d1
EY		 1612 (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {
1613
b6e881c9
DL		 1614 hubp->funcs->mem_program_viewport(
1615 hubp,
1616 &pipe_ctx->plane_res.scl_data.viewport,
cf27a6d1
EY		 1617 &pipe_ctx->plane_res.scl_data.viewport_c);
1618 viewport_changed = true;
1619 }
b6e881c9
DL		 1620
1621 /* Any updates are handled in dc interface, just need to apply existing for plane enable */
74cc5f02 1622 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||
8e80d482
PH		 1623 pipe_ctx->update_flags.bits.scaler || viewport_changed == true) &&
1624 pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
b6e881c9
DL		 1625 dc->hwss.set_cursor_position(pipe_ctx);
1626 dc->hwss.set_cursor_attribute(pipe_ctx);
1627
1628 if (dc->hwss.set_cursor_sdr_white_level)
1629 dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
1630 }
7ed4e635 1631
b6e881c9
DL		 1632 /* Any updates are handled in dc interface, just need
1633 * to apply existing for plane enable / opp change */
1634 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed
441595ba 1635 || pipe_ctx->update_flags.bits.plane_changed
b6e881c9
DL		 1636 || pipe_ctx->stream->update_flags.bits.gamut_remap
1637 || pipe_ctx->stream->update_flags.bits.out_csc) {
90d1a626
DV		 1638 /* dpp/cm gamut remap*/
1639 dc->hwss.program_gamut_remap(pipe_ctx);
b6e881c9
DL		 1640
1641 /*call the dcn2 method which uses mpc csc*/
1642 dc->hwss.program_output_csc(dc,
1643 pipe_ctx,
1644 pipe_ctx->stream->output_color_space,
1645 pipe_ctx->stream->csc_color_matrix.matrix,
1646 hubp->opp_id);
7ed4e635
HW		 1647 }
1648
b6e881c9 1649 if (pipe_ctx->update_flags.bits.enable ||
498563cf 1650 pipe_ctx->update_flags.bits.plane_changed ||
b6e881c9
DL		 1651 pipe_ctx->update_flags.bits.opp_changed ||
1652 plane_state->update_flags.bits.pixel_format_change ||
1653 plane_state->update_flags.bits.horizontal_mirror_change ||
1654 plane_state->update_flags.bits.rotation_change ||
1655 plane_state->update_flags.bits.swizzle_change ||
1656 plane_state->update_flags.bits.dcc_change ||
1657 plane_state->update_flags.bits.bpp_change ||
1658 plane_state->update_flags.bits.scaling_change ||
1659 plane_state->update_flags.bits.plane_size_change) {
1660 struct plane_size size = plane_state->plane_size;
1661
1662 size.surface_size = pipe_ctx->plane_res.scl_data.viewport;
1663 hubp->funcs->hubp_program_surface_config(
1664 hubp,
1665 plane_state->format,
1666 &plane_state->tiling_info,
1667 &size,
1668 plane_state->rotation,
1669 &plane_state->dcc,
1670 plane_state->horizontal_mirror,
1671 0);
1672 hubp->power_gated = false;
1673 }
1674
498563cf
JX		 1675 if (pipe_ctx->update_flags.bits.enable ||
1676 pipe_ctx->update_flags.bits.plane_changed ||
1677 plane_state->update_flags.bits.addr_update)
f42ea55b 1678 hws->funcs.update_plane_addr(dc, pipe_ctx);
b6e881c9 1679
e7a30ade 1680 if (pipe_ctx->update_flags.bits.enable)
0b7421f0 1681 hubp->funcs->set_blank(hubp, false);
d3dfceb5
AP		 1682 /* If the stream paired with this plane is phantom, the plane is also phantom */
1683 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM
1684 && hubp->funcs->phantom_hubp_post_enable)
1685 hubp->funcs->phantom_hubp_post_enable(hubp);
b6e881c9
DL		 1686}
1687
5842abd9
WC		 1688static int calculate_vready_offset_for_group(struct pipe_ctx *pipe)
1689{
1690 struct pipe_ctx *other_pipe;
1691 int vready_offset = pipe->pipe_dlg_param.vready_offset;
1692
1693 /* Always use the largest vready_offset of all connected pipes */
1694 for (other_pipe = pipe->bottom_pipe; other_pipe != NULL; other_pipe = other_pipe->bottom_pipe) {
1695 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset)
1696 vready_offset = other_pipe->pipe_dlg_param.vready_offset;
1697 }
1698 for (other_pipe = pipe->top_pipe; other_pipe != NULL; other_pipe = other_pipe->top_pipe) {
1699 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset)
1700 vready_offset = other_pipe->pipe_dlg_param.vready_offset;
1701 }
1702 for (other_pipe = pipe->next_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->next_odm_pipe) {
1703 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset)
1704 vready_offset = other_pipe->pipe_dlg_param.vready_offset;
1705 }
1706 for (other_pipe = pipe->prev_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->prev_odm_pipe) {
1707 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset)
1708 vready_offset = other_pipe->pipe_dlg_param.vready_offset;
1709 }
1710
1711 return vready_offset;
1712}
b6e881c9
DL		 1713
1714static void dcn20_program_pipe(
1715 struct dc *dc,
1716 struct pipe_ctx *pipe_ctx,
1717 struct dc_state *context)
1718{
f42ea55b 1719 struct dce_hwseq *hws = dc->hwseq;
b6e881c9 1720 /* Only need to unblank on top pipe */
d3dfceb5 1721
b6e881c9
DL		 1722 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level)
1723 && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
f42ea55b 1724 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
b6e881c9 1725
a71e5529
AC		 1726 /* Only update TG on top pipe */
1727 if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe
1728 && !pipe_ctx->prev_odm_pipe) {
b6e881c9
DL		 1729 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1730 pipe_ctx->stream_res.tg,
5842abd9 1731 calculate_vready_offset_for_group(pipe_ctx),
b6e881c9
DL		 1732 pipe_ctx->pipe_dlg_param.vstartup_start,
1733 pipe_ctx->pipe_dlg_param.vupdate_offset,
1734 pipe_ctx->pipe_dlg_param.vupdate_width);
1735
ac84304d 1736 if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM)
203ccaf5 1737 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
a71e5529 1738
a14e9e02 1739 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
a71e5529 1740 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);
1caba4e8 1741
f42ea55b
AK		 1742 if (hws->funcs.setup_vupdate_interrupt)
1743 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
a14e9e02
DL		 1744 }
1745
b6e881c9 1746 if (pipe_ctx->update_flags.bits.odm)
f42ea55b 1747 hws->funcs.update_odm(dc, context, pipe_ctx);
b6e881c9 1748
868149c9 1749 if (pipe_ctx->update_flags.bits.enable) {
b6e881c9 1750 dcn20_enable_plane(dc, pipe_ctx, context);
868149c9
JA		 1751 if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes)
1752 dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub);
1753 }
b6e881c9 1754
ba5a5371
NK		 1755 if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size)
1756 dc->res_pool->hubbub->funcs->program_det_size(
1757 dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);
ba5a5371 1758
74701238 1759 if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw)
b6e881c9
DL		 1760 dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
1761
1762 if (pipe_ctx->update_flags.bits.enable
46250a0c 1763 || pipe_ctx->plane_state->update_flags.bits.hdr_mult)
f42ea55b 1764 hws->funcs.set_hdr_multiplier(pipe_ctx);
b6e881c9
DL		 1765
1766 if (pipe_ctx->update_flags.bits.enable ||
1767 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
1768 pipe_ctx->plane_state->update_flags.bits.gamma_change)
f42ea55b 1769 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
b6e881c9
DL		 1770
1771 /* dcn10_translate_regamma_to_hw_format takes 750us to finish
1772 * only do gamma programming for powering on, internal memcmp to avoid
1773 * updating on slave planes
1774 */
bb622e0c
DV		 1775 if (pipe_ctx->update_flags.bits.enable ||
1776 pipe_ctx->update_flags.bits.plane_changed ||
1777 pipe_ctx->stream->update_flags.bits.out_tf ||
1778 pipe_ctx->plane_state->update_flags.bits.output_tf_change)
f42ea55b 1779 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
377c9d04
JP		 1780
1781 /* If the pipe has been enabled or has a different opp, we
1782 * should reprogram the fmt. This deals with cases where
1783 * interation between mpc and odm combine on different streams
1784 * causes a different pipe to be chosen to odm combine with.
1785 */
1786 if (pipe_ctx->update_flags.bits.enable
1787 || pipe_ctx->update_flags.bits.opp_changed) {
1788
1789 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1790 pipe_ctx->stream_res.opp,
1791 COLOR_SPACE_YCBCR601,
1792 pipe_ctx->stream->timing.display_color_depth,
1793 pipe_ctx->stream->signal);
1794
1795 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1796 pipe_ctx->stream_res.opp,
1797 &pipe_ctx->stream->bit_depth_params,
1798 &pipe_ctx->stream->clamping);
1799 }
32e3da43
LH		 1800
1801 /* Set ABM pipe after other pipe configurations done */
1802 if (pipe_ctx->plane_state->visible) {
1803 if (pipe_ctx->stream_res.abm) {
1804 dc->hwss.set_pipe(pipe_ctx);
1805 pipe_ctx->stream_res.abm->funcs->set_abm_level(pipe_ctx->stream_res.abm,
1806 pipe_ctx->stream->abm_level);
1807 }
1808 }
b6e881c9
DL		 1809}
1810
78c77382 1811void dcn20_program_front_end_for_ctx(
b6e881c9
DL		 1812 struct dc *dc,
1813 struct dc_state *context)
1814{
b6e881c9 1815 int i;
f42ea55b 1816 struct dce_hwseq *hws = dc->hwseq;
b6e881c9
DL		 1817 DC_LOGGER_INIT(dc->ctx->logger);
1818
d5c0af57 1819 /* Carry over GSL groups in case the context is changing. */
931fa55b
JC		 1820 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1821 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1822 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1823
1824 if (pipe_ctx->stream == old_pipe_ctx->stream)
1825 pipe_ctx->stream_res.gsl_group = old_pipe_ctx->stream_res.gsl_group;
1826 }
d5c0af57 1827
091018a5
AC		 1828 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
1829 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1830 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
009114f6 1831
091018a5
AC		 1832 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) {
1833 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
009114f6
AK		 1834 /*turn off triple buffer for full update*/
1835 dc->hwss.program_triplebuffer(
091018a5 1836 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
009114f6
AK		 1837 }
1838 }
1839 }
1840
b6e881c9
DL		 1841 /* Set pipe update flags and lock pipes */
1842 for (i = 0; i < dc->res_pool->pipe_count; i++)
1843 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i],
1844 &context->res_ctx.pipe_ctx[i]);
7ed4e635 1845
a5b50a0c
AL		 1846 /* When disabling phantom pipes, turn on phantom OTG first (so we can get double
1847 * buffer updates properly)
1848 */
af23aee9
AP		 1849 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1850 struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream;
1851
1852 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable && stream &&
1853 dc->current_state->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) {
a5b50a0c
AL		 1854 struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg;
1855
1856 if (tg->funcs->enable_crtc)
1857 tg->funcs->enable_crtc(tg);
1858 }
af23aee9 1859 }
b6e881c9
DL		 1860 /* OTG blank before disabling all front ends */
1861 for (i = 0; i < dc->res_pool->pipe_count; i++)
1862 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1863 && !context->res_ctx.pipe_ctx[i].top_pipe
1864 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe
1865 && context->res_ctx.pipe_ctx[i].stream)
f42ea55b 1866 hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);
b6e881c9 1867
d4930b7a 1868
b6e881c9
DL		 1869 /* Disconnect mpcc */
1870 for (i = 0; i < dc->res_pool->pipe_count; i++)
1871 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1872 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {
ba5a5371
NK		 1873 struct hubbub *hubbub = dc->res_pool->hubbub;
1874
14eb72ff
AL		 1875 /* Phantom pipe DET should be 0, but if a pipe in use is being transitioned to phantom
1876 * then we want to do the programming here (effectively it's being disabled). If we do
1877 * the programming later the DET won't be updated until the OTG for the phantom pipe is
1878 * turned on (i.e. in an MCLK switch) which can come in too late and cause issues with
1879 * DET allocation.
1880 */
1881 if (hubbub->funcs->program_det_size && (context->res_ctx.pipe_ctx[i].update_flags.bits.disable ||
1882 (context->res_ctx.pipe_ctx[i].plane_state && context->res_ctx.pipe_ctx[i].plane_state->is_phantom)))
ba5a5371 1883 hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);
f42ea55b 1884 hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
b6e881c9 1885 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
7ed4e635
HW		 1886 }
1887
b6e881c9
DL		 1888 /*
1889 * Program all updated pipes, order matters for mpcc setup. Start with
1890 * top pipe and program all pipes that follow in order
1891 */
1892 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1893 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
7ed4e635 1894
b6e881c9
DL		 1895 if (pipe->plane_state && !pipe->top_pipe) {
1896 while (pipe) {
7f63d8a1
PH		 1897 if (hws->funcs.program_pipe)
1898 hws->funcs.program_pipe(dc, pipe, context);
14eb72ff
AL		 1899 else {
1900 /* Don't program phantom pipes in the regular front end programming sequence.
1901 * There is an MPO transition case where a pipe being used by a video plane is
1902 * transitioned directly to be a phantom pipe when closing the MPO video. However
1903 * the phantom pipe will program a new HUBP_VTG_SEL (update takes place right away),
1904 * but the MPO still exists until the double buffered update of the main pipe so we
1905 * will get a frame of underflow if the phantom pipe is programmed here.
1906 */
1907 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_PHANTOM)
1908 dcn20_program_pipe(dc, pipe, context);
1909 }
7f63d8a1 1910
b6e881c9
DL		 1911 pipe = pipe->bottom_pipe;
1912 }
b6e881c9 1913 }
82367e7f
RC		 1914 /* Program secondary blending tree and writeback pipes */
1915 pipe = &context->res_ctx.pipe_ctx[i];
1916 if (!pipe->top_pipe && !pipe->prev_odm_pipe
1917 && pipe->stream && pipe->stream->num_wb_info > 0
1918 && (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw)
1919 || pipe->stream->update_flags.raw)
1920 && hws->funcs.program_all_writeback_pipes_in_tree)
1921 hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
dd15640b
BL		 1922
1923 /* Avoid underflow by check of pipe line read when adding 2nd plane. */
1924 if (hws->wa.wait_hubpret_read_start_during_mpo_transition &&
1925 !pipe->top_pipe &&
1926 pipe->stream &&
1927 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start &&
1928 dc->current_state->stream_status[0].plane_count == 1 &&
1929 context->stream_status[0].plane_count > 1) {
1930 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp);
1931 }
1cb69b43
DV		 1932
1933 /* when dynamic ODM is active, pipes must be reconfigured when all planes are
1934 * disabled, as some transitions will leave software and hardware state
1935 * mismatched.
1936 */
1937 if (dc->debug.enable_single_display_2to1_odm_policy &&
1938 pipe->stream &&
1939 pipe->update_flags.bits.disable &&
1940 !pipe->prev_odm_pipe &&
1941 hws->funcs.update_odm)
1942 hws->funcs.update_odm(dc, context, pipe);
b6e881c9 1943 }
bbf5f6c3
AK		 1944}
1945
1946void dcn20_post_unlock_program_front_end(
1947 struct dc *dc,
1948 struct dc_state *context)
1949{
1950 int i;
1951 const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100;
d9758768 1952 struct dce_hwseq *hwseq = dc->hwseq;
bbf5f6c3
AK		 1953
1954 DC_LOGGER_INIT(dc->ctx->logger);
b6e881c9
DL		 1955
1956 for (i = 0; i < dc->res_pool->pipe_count; i++)
1957 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
1958 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
986936d1
JL		 1959
1960 /*
1961 * If we are enabling a pipe, we need to wait for pending clear as this is a critical
1962 * part of the enable operation otherwise, DM may request an immediate flip which
1963 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which
1964 * is unsupported on DCN.
1965 */
b6e881c9
DL		 1966 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1967 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
85f4bc0c
AL		 1968 // Don't check flip pending on phantom pipes
1969 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable &&
1970 pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) {
b6e881c9
DL		 1971 struct hubp *hubp = pipe->plane_res.hubp;
1972 int j = 0;
1973
38259bac 1974 for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000
b6e881c9 1975 && hubp->funcs->hubp_is_flip_pending(hubp); j++)
345b1696 1976 udelay(1);
986936d1
JL		 1977 }
1978 }
f93e29f0 1979
14eb72ff
AL		 1980 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1981 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1982
1983 if (pipe->plane_state && !pipe->top_pipe) {
1984 /* Program phantom pipe here to prevent a frame of underflow in the MPO transition
1985 * case (if a pipe being used for a video plane transitions to a phantom pipe, it
1986 * can underflow due to HUBP_VTG_SEL programming if done in the regular front end
1987 * programming sequence).
1988 */
b0d6de32
AL		 1989 while (pipe) {
1990 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
e267f5e6
AL		 1991 /* When turning on the phantom pipe we want to run through the
1992 * entire enable sequence, so apply all the "enable" flags.
1993 */
1994 if (dc->hwss.apply_update_flags_for_phantom)
1995 dc->hwss.apply_update_flags_for_phantom(pipe);
b0d6de32
AL		 1996 if (dc->hwss.update_phantom_vp_position)
1997 dc->hwss.update_phantom_vp_position(dc, context, pipe);
1998 dcn20_program_pipe(dc, pipe, context);
1999 }
2000 pipe = pipe->bottom_pipe;
43080c9b 2001 }
14eb72ff
AL		 2002 }
2003 }
2004
4ed79308
AL		 2005 /* P-State support transitions:
2006 * Natural -> FPO: P-State disabled in prepare, force disallow anytime is safe
2007 * FPO -> Natural: Unforce anytime after FW disable is safe (P-State will assert naturally)
2008 * Unsupported -> FPO: P-State enabled in optimize, force disallow anytime is safe
2009 * FPO -> Unsupported: P-State disabled in prepare, unforce disallow anytime is safe
2010 * FPO <-> SubVP: Force disallow is maintained on the FPO / SubVP pipes
2011 */
2012 if (hwseq && hwseq->funcs.update_force_pstate)
2013 dc->hwseq->funcs.update_force_pstate(dc, context);
2014
14eb72ff
AL		 2015 /* Only program the MALL registers after all the main and phantom pipes
2016 * are done programming.
2017 */
2018 if (hwseq->funcs.program_mall_pipe_config)
2019 hwseq->funcs.program_mall_pipe_config(dc, context);
2020
f93e29f0 2021 /* WA to apply WM setting*/
d9758768 2022 if (hwseq->wa.DEGVIDCN21)
f93e29f0 2023 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);
d9758768
GS		 2024
2025
2026 /* WA for stutter underflow during MPO transitions when adding 2nd plane */
2027 if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) {
2028
2029 if (dc->current_state->stream_status[0].plane_count == 1 &&
2030 context->stream_status[0].plane_count > 1) {
2031
2032 struct timing_generator *tg = dc->res_pool->timing_generators[0];
2033
2034 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false);
2035
2036 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true;
2037 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg);
2038 }
2039 }
7ed4e635
HW		 2040}
2041
7ed4e635
HW		 2042void dcn20_prepare_bandwidth(
2043 struct dc *dc,
2044 struct dc_state *context)
2045{
2046 struct hubbub *hubbub = dc->res_pool->hubbub;
2e6e14c9 2047 unsigned int compbuf_size_kb = 0;
85f4bc0c
AL		 2048 unsigned int cache_wm_a = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns;
2049 unsigned int i;
7ed4e635 2050
057fc695
JL		 2051 dc->clk_mgr->funcs->update_clocks(
2052 dc->clk_mgr,
2053 context,
2054 false);
2055
85f4bc0c
AL		 2056 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2057 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2058
2059 // At optimize don't restore the original watermark value
2060 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) {
2061 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;
2062 break;
2063 }
2064 }
2065
2710d6c1
AL		 2066 /* program dchubbub watermarks:
2067 * For assigning wm_optimized_required, use |= operator since we don't want
2068 * to clear the value if the optimize has not happened yet
2069 */
2070 dc->wm_optimized_required |= hubbub->funcs->program_watermarks(hubbub,
7ed4e635
HW		 2071 &context->bw_ctx.bw.dcn.watermarks,
2072 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
2073 false);
2e6e14c9 2074
85f4bc0c
AL		 2075 // Restore the real watermark so we can commit the value to DMCUB
2076 // DMCUB uses the "original" watermark value in SubVP MCLK switch
2077 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = cache_wm_a;
2078
ba5a5371 2079 /* decrease compbuf size */
2e6e14c9 2080 if (hubbub->funcs->program_compbuf_size) {
9a10c126 2081 if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes) {
2e6e14c9 2082 compbuf_size_kb = context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes;
9a10c126
DV		 2083 dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.dml.ip.min_comp_buffer_size_kbytes);
2084 } else {
2e6e14c9 2085 compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb;
9a10c126
DV		 2086 dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.bw.dcn.compbuf_size_kb);
2087 }
2e6e14c9
DM		 2088
2089 hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, false);
2090 }
7ed4e635
HW		 2091}
2092
2093void dcn20_optimize_bandwidth(
2094 struct dc *dc,
2095 struct dc_state *context)
2096{
2097 struct hubbub *hubbub = dc->res_pool->hubbub;
e5fc7825 2098 int i;
7ed4e635 2099
85f4bc0c
AL		 2100 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2101 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2102
2103 // At optimize don't need to restore the original watermark value
2104 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) {
2105 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;
2106 break;
2107 }
2108 }
2109
4c631826
YS		 2110 /* program dchubbub watermarks */
2111 hubbub->funcs->program_watermarks(hubbub,
2112 &context->bw_ctx.bw.dcn.watermarks,
2113 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
2114 true);
7ed4e635 2115
4866b0bf
ML		 2116 if (dc->clk_mgr->dc_mode_softmax_enabled)
2117 if (dc->clk_mgr->clks.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
2118 context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
2119 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
2120
b808a7eb
DV		 2121 /* increase compbuf size */
2122 if (hubbub->funcs->program_compbuf_size)
2123 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);
2124
e101bf95
WC		 2125 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
2126 dc_dmub_srv_p_state_delegate(dc,
2127 true, context);
2128 context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
751e1714
WC		 2129 dc->clk_mgr->clks.fw_based_mclk_switching = true;
2130 } else {
2131 dc->clk_mgr->clks.fw_based_mclk_switching = false;
e101bf95
WC		 2132 }
2133
4c631826
YS		 2134 dc->clk_mgr->funcs->update_clocks(
2135 dc->clk_mgr,
2136 context,
2137 true);
469a6293 2138 if (context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) {
e5fc7825
GT		 2139 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
2140 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2141
2142 if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank
2143 && pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max
2144 && pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total)
2145 pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp,
469a6293 2146 pipe_ctx->dlg_regs.min_dst_y_next_start);
e5fc7825
GT		 2147 }
2148 }
7ed4e635
HW		 2149}
2150
2151bool dcn20_update_bandwidth(
2152 struct dc *dc,
2153 struct dc_state *context)
2154{
2155 int i;
f42ea55b 2156 struct dce_hwseq *hws = dc->hwseq;
7ed4e635
HW		 2157
2158 /* recalculate DML parameters */
254eb07c 2159 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false))
7ed4e635 2160 return false;
7ed4e635
HW		 2161
2162 /* apply updated bandwidth parameters */
2163 dc->hwss.prepare_bandwidth(dc, context);
2164
2165 /* update hubp configs for all pipes */
2166 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2167 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2168
2169 if (pipe_ctx->plane_state == NULL)
2170 continue;
2171
2172 if (pipe_ctx->top_pipe == NULL) {
2173 bool blank = !is_pipe_tree_visible(pipe_ctx);
2174
2175 pipe_ctx->stream_res.tg->funcs->program_global_sync(
2176 pipe_ctx->stream_res.tg,
5842abd9 2177 calculate_vready_offset_for_group(pipe_ctx),
7ed4e635
HW		 2178 pipe_ctx->pipe_dlg_param.vstartup_start,
2179 pipe_ctx->pipe_dlg_param.vupdate_offset,
2180 pipe_ctx->pipe_dlg_param.vupdate_width);
2181
3972c350 2182 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
5200c401 2183 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);
1caba4e8 2184
b1f6d01c 2185 if (pipe_ctx->prev_odm_pipe == NULL)
f42ea55b 2186 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);
1caba4e8 2187
f42ea55b
AK		 2188 if (hws->funcs.setup_vupdate_interrupt)
2189 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
7ed4e635
HW		 2190 }
2191
2192 pipe_ctx->plane_res.hubp->funcs->hubp_setup(
2193 pipe_ctx->plane_res.hubp,
2194 &pipe_ctx->dlg_regs,
2195 &pipe_ctx->ttu_regs,
2196 &pipe_ctx->rq_regs,
2197 &pipe_ctx->pipe_dlg_param);
2198 }
2199
2200 return true;
2201}
2202
78c77382 2203void dcn20_enable_writeback(
7ed4e635 2204 struct dc *dc,
edb922b0
JP		 2205 struct dc_writeback_info *wb_info,
2206 struct dc_state *context)
7ed4e635
HW		 2207{
2208 struct dwbc *dwb;
2209 struct mcif_wb *mcif_wb;
2210 struct timing_generator *optc;
2211
2212 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
2213 ASSERT(wb_info->wb_enabled);
2214 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
2215 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
2216
2217 /* set the OPTC source mux */
6a652f6d 2218 optc = dc->res_pool->timing_generators[dwb->otg_inst];
7ed4e635
HW		 2219 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
2220 /* set MCIF_WB buffer and arbitration configuration */
2221 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);
edb922b0 2222 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
7ed4e635
HW		 2223 /* Enable MCIF_WB */
2224 mcif_wb->funcs->enable_mcif(mcif_wb);
2225 /* Enable DWB */
2226 dwb->funcs->enable(dwb, &wb_info->dwb_params);
2227 /* TODO: add sequence to enable/disable warmup */
2228}
2229
2230void dcn20_disable_writeback(
2231 struct dc *dc,
2232 unsigned int dwb_pipe_inst)
2233{
2234 struct dwbc *dwb;
2235 struct mcif_wb *mcif_wb;
2236
2237 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
2238 dwb = dc->res_pool->dwbc[dwb_pipe_inst];
2239 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
2240
2241 dwb->funcs->disable(dwb);
2242 mcif_wb->funcs->disable_mcif(mcif_wb);
2243}
2244
78c77382 2245bool dcn20_wait_for_blank_complete(
7ed4e635
HW		 2246 struct output_pixel_processor *opp)
2247{
2248 int counter;
2249
2250 for (counter = 0; counter < 1000; counter++) {
2251 if (opp->funcs->dpg_is_blanked(opp))
2252 break;
2253
2254 udelay(100);
2255 }
2256
2257 if (counter == 1000) {
2258 dm_error("DC: failed to blank crtc!\n");
2259 return false;
2260 }
2261
2262 return true;
2263}
2264
2265bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)
2266{
2267 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2268
2269 if (!hubp)
2270 return false;
2271 return hubp->funcs->dmdata_status_done(hubp);
2272}
2273
78c77382 2274void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
7ed4e635 2275{
97bda032 2276 struct dce_hwseq *hws = dc->hwseq;
97bda032
HW		 2277
2278 if (pipe_ctx->stream_res.dsc) {
b1f6d01c
DL		 2279 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2280
20cc44c9 2281 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);
b1f6d01c 2282 while (odm_pipe) {
20cc44c9 2283 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);
b1f6d01c
DL		 2284 odm_pipe = odm_pipe->next_odm_pipe;
2285 }
97bda032 2286 }
7ed4e635
HW		 2287}
2288
78c77382 2289void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
7ed4e635 2290{
97bda032 2291 struct dce_hwseq *hws = dc->hwseq;
97bda032
HW		 2292
2293 if (pipe_ctx->stream_res.dsc) {
b1f6d01c
DL		 2294 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2295
20cc44c9 2296 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);
b1f6d01c 2297 while (odm_pipe) {
20cc44c9 2298 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);
b1f6d01c
DL		 2299 odm_pipe = odm_pipe->next_odm_pipe;
2300 }
97bda032 2301 }
7ed4e635
HW		 2302}
2303
2304void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)
2305{
2306 struct dc_dmdata_attributes attr = { 0 };
2307 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2308
2309 attr.dmdata_mode = DMDATA_HW_MODE;
2310 attr.dmdata_size =
2311 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;
2312 attr.address.quad_part =
2313 pipe_ctx->stream->dmdata_address.quad_part;
2314 attr.dmdata_dl_delta = 0;
2315 attr.dmdata_qos_mode = 0;
2316 attr.dmdata_qos_level = 0;
2317 attr.dmdata_repeat = 1; /* always repeat */
2318 attr.dmdata_updated = 1;
2319 attr.dmdata_sw_data = NULL;
2320
2321 hubp->funcs->dmdata_set_attributes(hubp, &attr);
2322}
2323
78c77382 2324void dcn20_init_vm_ctx(
bda9afda
DL		 2325 struct dce_hwseq *hws,
2326 struct dc *dc,
2327 struct dc_virtual_addr_space_config *va_config,
2328 int vmid)
7ed4e635 2329{
bda9afda
DL		 2330 struct dcn_hubbub_virt_addr_config config;
2331
2332 if (vmid == 0) {
2333 ASSERT(0); /* VMID cannot be 0 for vm context */
2334 return;
2335 }
2336
2337 config.page_table_start_addr = va_config->page_table_start_addr;
2338 config.page_table_end_addr = va_config->page_table_end_addr;
2339 config.page_table_block_size = va_config->page_table_block_size_in_bytes;
2340 config.page_table_depth = va_config->page_table_depth;
2341 config.page_table_base_addr = va_config->page_table_base_addr;
2342
2343 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid);
2344}
2345
78c77382 2346int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
bda9afda
DL		 2347{
2348 struct dcn_hubbub_phys_addr_config config;
2349
2350 config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
2351 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
2352 config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
2353 config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
2354 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
2355 config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
2356 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
2357 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
2358 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
ee80de54 2359 config.page_table_default_page_addr = pa_config->page_table_default_page_addr;
bda9afda
DL		 2360
2361 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
7ed4e635
HW		 2362}
2363
2364static bool patch_address_for_sbs_tb_stereo(
2365 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
2366{
2367 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2368 bool sec_split = pipe_ctx->top_pipe &&
2369 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
2370 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2371 (pipe_ctx->stream->timing.timing_3d_format ==
2372 TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2373 pipe_ctx->stream->timing.timing_3d_format ==
2374 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
2375 *addr = plane_state->address.grph_stereo.left_addr;
2376 plane_state->address.grph_stereo.left_addr =
2377 plane_state->address.grph_stereo.right_addr;
2378 return true;
2379 }
2380
2381 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
2382 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
2383 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
2384 plane_state->address.grph_stereo.right_addr =
2385 plane_state->address.grph_stereo.left_addr;
480c5b8f
AL		 2386 plane_state->address.grph_stereo.right_meta_addr =
2387 plane_state->address.grph_stereo.left_meta_addr;
7ed4e635
HW		 2388 }
2389 return false;
2390}
2391
78c77382 2392void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
7ed4e635
HW		 2393{
2394 bool addr_patched = false;
2395 PHYSICAL_ADDRESS_LOC addr;
2396 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
7ed4e635
HW		 2397
2398 if (plane_state == NULL)
2399 return;
2400
2401 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
2402
bda9afda
DL		 2403 // Call Helper to track VMID use
2404 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);
7ed4e635
HW		 2405
2406 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
2407 pipe_ctx->plane_res.hubp,
2408 &plane_state->address,
bda9afda 2409 plane_state->flip_immediate);
7ed4e635
HW		 2410
2411 plane_state->status.requested_address = plane_state->address;
2412
2413 if (plane_state->flip_immediate)
2414 plane_state->status.current_address = plane_state->address;
2415
2416 if (addr_patched)
2417 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
2418}
2419
2420void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
2421 struct dc_link_settings *link_settings)
2422{
c78abac9 2423 struct encoder_unblank_param params = {0};
7ed4e635
HW		 2424 struct dc_stream_state *stream = pipe_ctx->stream;
2425 struct dc_link *link = stream->link;
f42ea55b 2426 struct dce_hwseq *hws = link->dc->hwseq;
b1f6d01c 2427 struct pipe_ctx *odm_pipe;
7ed4e635 2428
b1f6d01c
DL		 2429 params.opp_cnt = 1;
2430 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
2431 params.opp_cnt++;
2432 }
7ed4e635
HW		 2433 /* only 3 items below are used by unblank */
2434 params.timing = pipe_ctx->stream->timing;
2435
2436 params.link_settings.link_rate = link_settings->link_rate;
2437
98ce7d32 2438 if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
f01ee019
FZ		 2439 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
2440 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(
2441 pipe_ctx->stream_res.hpo_dp_stream_enc,
2442 pipe_ctx->stream_res.tg->inst);
2443 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
78c77382 2444 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1)
7ed4e635
HW		 2445 params.timing.pix_clk_100hz /= 2;
2446 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
1f332460 2447 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1);
3550d622 2448 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);
7ed4e635
HW		 2449 }
2450
2451 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
f42ea55b 2452 hws->funcs.edp_backlight_control(link, true);
7ed4e635
HW		 2453 }
2454}
2455
78c77382 2456void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
7ed4e635
HW		 2457{
2458 struct timing_generator *tg = pipe_ctx->stream_res.tg;
78c77382 2459 int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
7ed4e635 2460
7fad39ca
EB		 2461 if (start_line < 0)
2462 start_line = 0;
7ed4e635
HW		 2463
2464 if (tg->funcs->setup_vertical_interrupt2)
2465 tg->funcs->setup_vertical_interrupt2(tg, start_line);
2466}
2467
2468static void dcn20_reset_back_end_for_pipe(
2469 struct dc *dc,
2470 struct pipe_ctx *pipe_ctx,
2471 struct dc_state *context)
2472{
2473 int i;
9c75891f
WL		 2474 struct dc_link *link = pipe_ctx->stream->link;
2475 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
2476
7ed4e635
HW		 2477 DC_LOGGER_INIT(dc->ctx->logger);
2478 if (pipe_ctx->stream_res.stream_enc == NULL) {
2479 pipe_ctx->stream = NULL;
2480 return;
2481 }
2482
2483 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
efca0905
PH		 2484 /* DPMS may already disable or */
2485 /* dpms_off status is incorrect due to fastboot
2486 * feature. When system resume from S4 with second
2487 * screen only, the dpms_off would be true but
2488 * VBIOS lit up eDP, so check link status too.
2489 */
9c75891f 2490 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
98ce7d32 2491 dc->link_srv->set_dpms_off(pipe_ctx);
9c75891f 2492 else if (pipe_ctx->stream_res.audio)
57430404
SSC		 2493 dc->hwss.disable_audio_stream(pipe_ctx);
2494
2495 /* free acquired resources */
2496 if (pipe_ctx->stream_res.audio) {
2497 /*disable az_endpoint*/
2498 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2499
2500 /*free audio*/
2501 if (dc->caps.dynamic_audio == true) {
2502 /*we have to dynamic arbitrate the audio endpoints*/
2503 /*we free the resource, need reset is_audio_acquired*/
2504 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2505 pipe_ctx->stream_res.audio, false);
2506 pipe_ctx->stream_res.audio = NULL;
2507 }
7ed4e635 2508 }
7ed4e635 2509 }
606b3551 2510 else if (pipe_ctx->stream_res.dsc) {
98ce7d32 2511 dc->link_srv->set_dsc_enable(pipe_ctx, false);
606b3551 2512 }
7ed4e635
HW		 2513
2514 /* by upper caller loop, parent pipe: pipe0, will be reset last.
2515 * back end share by all pipes and will be disable only when disable
2516 * parent pipe.
2517 */
2518 if (pipe_ctx->top_pipe == NULL) {
9edf202d 2519
3ba01817 2520 dc->hwss.set_abm_immediate_disable(pipe_ctx);
9edf202d 2521
7ed4e635
HW		 2522 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
2523
2524 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
2525 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
2526 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
2527 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
38df0701
WL		 2528
2529 if (pipe_ctx->stream_res.tg->funcs->set_drr)
2530 pipe_ctx->stream_res.tg->funcs->set_drr(
2531 pipe_ctx->stream_res.tg, NULL);
9c75891f
WL		 2532 /* TODO - convert symclk_ref_cnts for otg to a bit map to solve
2533 * the case where the same symclk is shared across multiple otg
2534 * instances
2535 */
2536 link->phy_state.symclk_ref_cnts.otg = 0;
2537 if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) {
2538 link_hwss->disable_link_output(link,
2539 &pipe_ctx->link_res, pipe_ctx->stream->signal);
2540 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
2541 }
7ed4e635
HW		 2542 }
2543
2544 for (i = 0; i < dc->res_pool->pipe_count; i++)
2545 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
2546 break;
2547
2548 if (i == dc->res_pool->pipe_count)
2549 return;
2550
2551 pipe_ctx->stream = NULL;
2552 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
2553 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
2554}
2555
78c77382 2556void dcn20_reset_hw_ctx_wrap(
7ed4e635
HW		 2557 struct dc *dc,
2558 struct dc_state *context)
2559{
2560 int i;
f42ea55b 2561 struct dce_hwseq *hws = dc->hwseq;
7ed4e635
HW		 2562
2563 /* Reset Back End*/
2564 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
2565 struct pipe_ctx *pipe_ctx_old =
2566 &dc->current_state->res_ctx.pipe_ctx[i];
2567 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2568
2569 if (!pipe_ctx_old->stream)
2570 continue;
2571
b1f6d01c 2572 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
7ed4e635
HW		 2573 continue;
2574
2575 if (!pipe_ctx->stream ||
2576 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2577 struct clock_source *old_clk = pipe_ctx_old->clock_source;
2578
2579 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
f42ea55b 2580 if (hws->funcs.enable_stream_gating)
ae6c9601 2581 hws->funcs.enable_stream_gating(dc, pipe_ctx_old);
7ed4e635
HW		 2582 if (old_clk)
2583 old_clk->funcs->cs_power_down(old_clk);
2584 }
2585 }
2586}
2587
3ca40237
WW		 2588void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
2589{
7ed4e635 2590 struct hubp *hubp = pipe_ctx->plane_res.hubp;
c78abac9 2591 struct mpcc_blnd_cfg blnd_cfg = {0};
473e0ecb 2592 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
7ed4e635
HW		 2593 int mpcc_id;
2594 struct mpcc *new_mpcc;
2595 struct mpc *mpc = dc->res_pool->mpc;
2596 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
2597
7ed4e635
HW		 2598 blnd_cfg.overlap_only = false;
2599 blnd_cfg.global_gain = 0xff;
2600
76818cdd
SJK		 2601 if (per_pixel_alpha) {
2602 blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha;
2603 if (pipe_ctx->plane_state->global_alpha) {
2604 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN;
2605 blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;
2606 } else {
2607 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
2608 }
67229b27 2609 } else {
76818cdd 2610 blnd_cfg.pre_multiplied_alpha = false;
67229b27
MW		 2611 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
2612 }
2613
7ed4e635
HW		 2614 if (pipe_ctx->plane_state->global_alpha)
2615 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
2616 else
2617 blnd_cfg.global_alpha = 0xff;
2618
2619 blnd_cfg.background_color_bpc = 4;
2620 blnd_cfg.bottom_gain_mode = 0;
2621 blnd_cfg.top_gain = 0x1f000;
2622 blnd_cfg.bottom_inside_gain = 0x1f000;
2623 blnd_cfg.bottom_outside_gain = 0x1f000;
76818cdd 2624
d99f1387
BL		 2625 if (pipe_ctx->plane_state->format
2626 == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA)
2627 blnd_cfg.pre_multiplied_alpha = false;
7ed4e635
HW		 2628
2629 /*
2630 * TODO: remove hack
2631 * Note: currently there is a bug in init_hw such that
2632 * on resume from hibernate, BIOS sets up MPCC0, and
2633 * we do mpcc_remove but the mpcc cannot go to idle
2634 * after remove. This cause us to pick mpcc1 here,
2635 * which causes a pstate hang for yet unknown reason.
2636 */
2637 mpcc_id = hubp->inst;
2638
c97c8d77 2639 /* If there is no full update, don't need to touch MPC tree*/
68c10ac9
AC		 2640 if (!pipe_ctx->plane_state->update_flags.bits.full_update &&
2641 !pipe_ctx->update_flags.bits.mpcc) {
c97c8d77 2642 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
d205a800 2643 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);
c97c8d77
NK		 2644 return;
2645 }
2646
7ed4e635
HW		 2647 /* check if this MPCC is already being used */
2648 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
2649 /* remove MPCC if being used */
2650 if (new_mpcc != NULL)
2651 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
2652 else
2653 if (dc->debug.sanity_checks)
2654 mpc->funcs->assert_mpcc_idle_before_connect(
2655 dc->res_pool->mpc, mpcc_id);
2656
2657 /* Call MPC to insert new plane */
2658 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2659 mpc_tree_params,
2660 &blnd_cfg,
2661 NULL,
2662 NULL,
2663 hubp->inst,
2664 mpcc_id);
d205a800 2665 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);
7ed4e635
HW		 2666
2667 ASSERT(new_mpcc != NULL);
2668 hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2669 hubp->mpcc_id = mpcc_id;
2670}
2671
7462475e
WL		 2672static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link)
2673{
2674 switch (link->link_enc->transmitter) {
2675 case TRANSMITTER_UNIPHY_A:
2676 return PHYD32CLKA;
2677 case TRANSMITTER_UNIPHY_B:
2678 return PHYD32CLKB;
2679 case TRANSMITTER_UNIPHY_C:
2680 return PHYD32CLKC;
2681 case TRANSMITTER_UNIPHY_D:
2682 return PHYD32CLKD;
2683 case TRANSMITTER_UNIPHY_E:
2684 return PHYD32CLKE;
2685 default:
2686 return PHYD32CLKA;
2687 }
2688}
2689
2690static int get_odm_segment_count(struct pipe_ctx *pipe_ctx)
2691{
2692 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2693 int count = 1;
2694
2695 while (odm_pipe != NULL) {
2696 count++;
2697 odm_pipe = odm_pipe->next_odm_pipe;
2698 }
2699
2700 return count;
2701}
2702
78c77382 2703void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
f591344e
JP		 2704{
2705 enum dc_lane_count lane_count =
2706 pipe_ctx->stream->link->cur_link_settings.lane_count;
2707
2708 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
2709 struct dc_link *link = pipe_ctx->stream->link;
2710
2711 uint32_t active_total_with_borders;
2712 uint32_t early_control = 0;
2713 struct timing_generator *tg = pipe_ctx->stream_res.tg;
9d8033d6
WL		 2714 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
2715 struct dc *dc = pipe_ctx->stream->ctx->dc;
7462475e
WL		 2716 struct dtbclk_dto_params dto_params = {0};
2717 struct dccg *dccg = dc->res_pool->dccg;
2718 enum phyd32clk_clock_source phyd32clk;
2719 int dp_hpo_inst;
a10a22b0
WL		 2720 struct dce_hwseq *hws = dc->hwseq;
2721 unsigned int k1_div = PIXEL_RATE_DIV_NA;
2722 unsigned int k2_div = PIXEL_RATE_DIV_NA;
64d283cb 2723
98ce7d32 2724 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
9d8033d6
WL		 2725 if (dc->hwseq->funcs.setup_hpo_hw_control)
2726 dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, true);
f01ee019
FZ		 2727 }
2728
98ce7d32 2729 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
7462475e
WL		 2730 dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
2731 dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst);
2732
2733 phyd32clk = get_phyd32clk_src(link);
2734 dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);
2735
2736 dto_params.otg_inst = tg->inst;
2737 dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
2738 dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx);
2739 dto_params.timing = &pipe_ctx->stream->timing;
2740 dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);
2741 dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
2742 }
2743
a10a22b0
WL		 2744 if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {
2745 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
2746
2747 dc->res_pool->dccg->funcs->set_pixel_rate_div(
2748 dc->res_pool->dccg,
2749 pipe_ctx->stream_res.tg->inst,
2750 k1_div, k2_div);
2751 }
2752
9d8033d6 2753 link_hwss->setup_stream_encoder(pipe_ctx);
3550d622 2754
ce10a0f3 2755 if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {
9d8033d6
WL		 2756 if (dc->hwss.program_dmdata_engine)
2757 dc->hwss.program_dmdata_engine(pipe_ctx);
ce10a0f3 2758 }
f591344e 2759
9d8033d6 2760 dc->hwss.update_info_frame(pipe_ctx);
f591344e 2761
3550d622 2762 if (dc_is_dp_signal(pipe_ctx->stream->signal))
98ce7d32 2763 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
3550d622 2764
f591344e
JP		 2765 /* enable early control to avoid corruption on DP monitor*/
2766 active_total_with_borders =
2767 timing->h_addressable
2768 + timing->h_border_left
2769 + timing->h_border_right;
2770
2771 if (lane_count != 0)
2772 early_control = active_total_with_borders % lane_count;
2773
2774 if (early_control == 0)
2775 early_control = lane_count;
2776
2777 tg->funcs->set_early_control(tg, early_control);
2778
64a30aaf
EB		 2779 if (dc->hwseq->funcs.set_pixels_per_cycle)
2780 dc->hwseq->funcs.set_pixels_per_cycle(pipe_ctx);
f591344e
JP		 2781}
2782
78c77382 2783void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
f591344e
JP		 2784{
2785 struct dc_stream_state *stream = pipe_ctx->stream;
2786 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2787 bool enable = false;
2788 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
2789 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal)
2790 ? dmdata_dp
2791 : dmdata_hdmi;
2792
2793 /* if using dynamic meta, don't set up generic infopackets */
2794 if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
2795 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
2796 enable = true;
2797 }
2798
2799 if (!hubp)
2800 return;
2801
2802 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
2803 return;
2804
2805 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
2806 hubp->inst, mode);
2807}
2808
78c77382 2809void dcn20_fpga_init_hw(struct dc *dc)
8a31820b
ML		 2810{
2811 int i, j;
2812 struct dce_hwseq *hws = dc->hwseq;
2813 struct resource_pool *res_pool = dc->res_pool;
2814 struct dc_state *context = dc->current_state;
2815
2816 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
2817 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
2818
2819 // Initialize the dccg
2820 if (res_pool->dccg->funcs->dccg_init)
2821 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
2822
2823 //Enable ability to power gate / don't force power on permanently
f42ea55b 2824 hws->funcs.enable_power_gating_plane(hws, true);
8a31820b
ML		 2825
2826 // Specific to FPGA dccg and registers
2827 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
2828 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
2829
f42ea55b 2830 hws->funcs.dccg_init(hws);
8a31820b
ML		 2831
2832 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
2833 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
3ebd17f5
DL		 2834 if (REG(REFCLK_CNTL))
2835 REG_WRITE(REFCLK_CNTL, 0);
8a31820b
ML		 2836 //
2837
2838
2839 /* Blank pixel data with OPP DPG */
2840 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2841 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2842
2843 if (tg->funcs->is_tg_enabled(tg))
2844 dcn20_init_blank(dc, tg);
2845 }
2846
2847 for (i = 0; i < res_pool->timing_generator_count; i++) {
2848 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2849
2850 if (tg->funcs->is_tg_enabled(tg))
2851 tg->funcs->lock(tg);
2852 }
2853
2854 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2855 struct dpp *dpp = res_pool->dpps[i];
2856
2857 dpp->funcs->dpp_reset(dpp);
2858 }
2859
2860 /* Reset all MPCC muxes */
2861 res_pool->mpc->funcs->mpc_init(res_pool->mpc);
2862
2863 /* initialize OPP mpc_tree parameter */
2864 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
2865 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
2866 res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2867 for (j = 0; j < MAX_PIPES; j++)
2868 res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
2869 }
2870
2871 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2872 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2873 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2874 struct hubp *hubp = dc->res_pool->hubps[i];
2875 struct dpp *dpp = dc->res_pool->dpps[i];
2876
2877 pipe_ctx->stream_res.tg = tg;
2878 pipe_ctx->pipe_idx = i;
2879
2880 pipe_ctx->plane_res.hubp = hubp;
2881 pipe_ctx->plane_res.dpp = dpp;
2882 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
2883 hubp->mpcc_id = dpp->inst;
2884 hubp->opp_id = OPP_ID_INVALID;
2885 hubp->power_gated = false;
2886 pipe_ctx->stream_res.opp = NULL;
2887
2888 hubp->funcs->hubp_init(hubp);
2889
2890 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
2891 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2892 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
2893 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
2894 /*to do*/
f42ea55b 2895 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx);
8a31820b
ML		 2896 }
2897
2898 /* initialize DWB pointer to MCIF_WB */
2899 for (i = 0; i < res_pool->res_cap->num_dwb; i++)
2900 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
2901
2902 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2903 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2904
2905 if (tg->funcs->is_tg_enabled(tg))
2906 tg->funcs->unlock(tg);
2907 }
2908
2909 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2910 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2911
2912 dc->hwss.disable_plane(dc, pipe_ctx);
2913
2914 pipe_ctx->stream_res.tg = NULL;
2915 pipe_ctx->plane_res.hubp = NULL;
2916 }
2917
2918 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2919 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2920
2921 tg->funcs->tg_init(tg);
2922 }
8fe44c08 2923
ba5a5371
NK		 2924 if (dc->res_pool->hubbub->funcs->init_crb)
2925 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
8a31820b 2926}
471c1dd9
RA		 2927#ifndef TRIM_FSFT
2928bool dcn20_optimize_timing_for_fsft(struct dc *dc,
2929 struct dc_crtc_timing *timing,
2930 unsigned int max_input_rate_in_khz)
2931{
2932 unsigned int old_v_front_porch;
2933 unsigned int old_v_total;
2934 unsigned int max_input_rate_in_100hz;
2935 unsigned long long new_v_total;
2936
2937 max_input_rate_in_100hz = max_input_rate_in_khz * 10;
2938 if (max_input_rate_in_100hz < timing->pix_clk_100hz)
2939 return false;
2940
2941 old_v_total = timing->v_total;
2942 old_v_front_porch = timing->v_front_porch;
2943
2944 timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz;
2945 timing->pix_clk_100hz = max_input_rate_in_100hz;
2946
2947 new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz);
2948
2949 timing->v_total = new_v_total;
2950 timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total);
2951 return true;
2952}
2953#endif
dbf5256b
JA		 2954
2955void dcn20_set_disp_pattern_generator(const struct dc *dc,
2956 struct pipe_ctx *pipe_ctx,
2957 enum controller_dp_test_pattern test_pattern,
2958 enum controller_dp_color_space color_space,
2959 enum dc_color_depth color_depth,
2960 const struct tg_color *solid_color,
2961 int width, int height, int offset)
2962{
2963 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
2964 color_space, color_depth, solid_color, width, height, offset);
a71e5529 2965}
Linux 6.x block layer and io_uring tree(s)