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drm/amd/display: Extend DMUB HW params to allow DM to specify boot options
[linux-block.git] / drivers / gpu / drm / amd / display / dc / dcn20 / dcn20_hwseq.c
CommitLineData
7ed4e635
HW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
c602b36f 25#include <linux/delay.h>
7ed4e635
HW		 26
27#include "dm_services.h"
78c77382 28#include "basics/dc_common.h"
7ed4e635
HW		 29#include "dm_helpers.h"
30#include "core_types.h"
31#include "resource.h"
78c77382 32#include "dcn20_resource.h"
7ed4e635
HW		 33#include "dcn20_hwseq.h"
34#include "dce/dce_hwseq.h"
78c77382
AK		 35#include "dcn20_dsc.h"
36#include "dcn20_optc.h"
7ed4e635
HW		 37#include "abm.h"
38#include "clk_mgr.h"
39#include "dmcu.h"
40#include "hubp.h"
41#include "timing_generator.h"
42#include "opp.h"
43#include "ipp.h"
44#include "mpc.h"
45#include "mcif_wb.h"
78c77382 46#include "dchubbub.h"
7ed4e635
HW		 47#include "reg_helper.h"
48#include "dcn10/dcn10_cm_common.h"
7ed4e635
HW		 49#include "dc_link_dp.h"
50#include "vm_helper.h"
51#include "dccg.h"
dc6e2448
WW		 52#include "dc_dmub_srv.h"
53#include "dce/dmub_hw_lock_mgr.h"
7ed4e635
HW		 54
55#define DC_LOGGER_INIT(logger)
56
57#define CTX \
58 hws->ctx
59#define REG(reg)\
60 hws->regs->reg
61
62#undef FN
63#define FN(reg_name, field_name) \
64 hws->shifts->field_name, hws->masks->field_name
65
78c77382
AK		 66static int find_free_gsl_group(const struct dc *dc)
67{
68 if (dc->res_pool->gsl_groups.gsl_0 == 0)
69 return 1;
70 if (dc->res_pool->gsl_groups.gsl_1 == 0)
71 return 2;
72 if (dc->res_pool->gsl_groups.gsl_2 == 0)
73 return 3;
74
75 return 0;
76}
77
78/* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock)
79 * This is only used to lock pipes in pipe splitting case with immediate flip
80 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate,
81 * so we get tearing with freesync since we cannot flip multiple pipes
82 * atomically.
83 * We use GSL for this:
84 * - immediate flip: find first available GSL group if not already assigned
85 * program gsl with that group, set current OTG as master
86 * and always us 0x4 = AND of flip_ready from all pipes
87 * - vsync flip: disable GSL if used
88 *
89 * Groups in stream_res are stored as +1 from HW registers, i.e.
90 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
91 * Using a magic value like -1 would require tracking all inits/resets
92 */
93static void dcn20_setup_gsl_group_as_lock(
94 const struct dc *dc,
95 struct pipe_ctx *pipe_ctx,
96 bool enable)
97{
98 struct gsl_params gsl;
99 int group_idx;
100
101 memset(&gsl, 0, sizeof(struct gsl_params));
102
103 if (enable) {
104 /* return if group already assigned since GSL was set up
105 * for vsync flip, we would unassign so it can't be "left over"
106 */
107 if (pipe_ctx->stream_res.gsl_group > 0)
108 return;
109
110 group_idx = find_free_gsl_group(dc);
111 ASSERT(group_idx != 0);
112 pipe_ctx->stream_res.gsl_group = group_idx;
113
114 /* set gsl group reg field and mark resource used */
115 switch (group_idx) {
116 case 1:
117 gsl.gsl0_en = 1;
118 dc->res_pool->gsl_groups.gsl_0 = 1;
119 break;
120 case 2:
121 gsl.gsl1_en = 1;
122 dc->res_pool->gsl_groups.gsl_1 = 1;
123 break;
124 case 3:
125 gsl.gsl2_en = 1;
126 dc->res_pool->gsl_groups.gsl_2 = 1;
127 break;
128 default:
129 BREAK_TO_DEBUGGER();
130 return; // invalid case
131 }
132 gsl.gsl_master_en = 1;
133 } else {
134 group_idx = pipe_ctx->stream_res.gsl_group;
135 if (group_idx == 0)
136 return; // if not in use, just return
137
138 pipe_ctx->stream_res.gsl_group = 0;
139
140 /* unset gsl group reg field and mark resource free */
141 switch (group_idx) {
142 case 1:
143 gsl.gsl0_en = 0;
144 dc->res_pool->gsl_groups.gsl_0 = 0;
145 break;
146 case 2:
147 gsl.gsl1_en = 0;
148 dc->res_pool->gsl_groups.gsl_1 = 0;
149 break;
150 case 3:
151 gsl.gsl2_en = 0;
152 dc->res_pool->gsl_groups.gsl_2 = 0;
153 break;
154 default:
155 BREAK_TO_DEBUGGER();
156 return;
157 }
158 gsl.gsl_master_en = 0;
159 }
160
161 /* at this point we want to program whether it's to enable or disable */
162 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
163 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
164 pipe_ctx->stream_res.tg->funcs->set_gsl(
165 pipe_ctx->stream_res.tg,
166 &gsl);
167
168 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
169 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0);
170 } else
171 BREAK_TO_DEBUGGER();
172}
173
174void dcn20_set_flip_control_gsl(
175 struct pipe_ctx *pipe_ctx,
176 bool flip_immediate)
177{
178 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)
179 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(
180 pipe_ctx->plane_res.hubp, flip_immediate);
181
182}
183
184void dcn20_enable_power_gating_plane(
7ed4e635
HW		 185 struct dce_hwseq *hws,
186 bool enable)
187{
0bb80369 188 bool force_on = true; /* disable power gating */
7ed4e635
HW		 189
190 if (enable)
0bb80369 191 force_on = false;
7ed4e635
HW		 192
193 /* DCHUBP0/1/2/3/4/5 */
194 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
195 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
196 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
197 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
46825fcf
TC		 198 if (REG(DOMAIN8_PG_CONFIG))
199 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
200 if (REG(DOMAIN10_PG_CONFIG))
201 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
7ed4e635
HW		 202
203 /* DPP0/1/2/3/4/5 */
204 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
205 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
206 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
207 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
46825fcf
TC		 208 if (REG(DOMAIN9_PG_CONFIG))
209 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
210 if (REG(DOMAIN11_PG_CONFIG))
211 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
7ed4e635 212
46825fcf 213 /* DCS0/1/2/3/4/5 */
7ed4e635
HW		 214 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on);
215 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on);
216 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on);
46825fcf
TC		 217 if (REG(DOMAIN19_PG_CONFIG))
218 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on);
219 if (REG(DOMAIN20_PG_CONFIG))
220 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on);
221 if (REG(DOMAIN21_PG_CONFIG))
222 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on);
7ed4e635
HW		 223}
224
c70b4016 225void dcn20_dccg_init(struct dce_hwseq *hws)
7ed4e635
HW		 226{
227 /*
228 * set MICROSECOND_TIME_BASE_DIV
229 * 100Mhz refclk -> 0x120264
230 * 27Mhz refclk -> 0x12021b
231 * 48Mhz refclk -> 0x120230
232 *
233 */
234 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264);
235
236 /*
237 * set MILLISECOND_TIME_BASE_DIV
238 * 100Mhz refclk -> 0x1186a0
239 * 27Mhz refclk -> 0x106978
240 * 48Mhz refclk -> 0x10bb80
241 *
242 */
243 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
244
245 /* This value is dependent on the hardware pipeline delay so set once per SOC */
246 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c);
247}
248
8a31820b 249void dcn20_disable_vga(
7ed4e635
HW		 250 struct dce_hwseq *hws)
251{
252 REG_WRITE(D1VGA_CONTROL, 0);
253 REG_WRITE(D2VGA_CONTROL, 0);
254 REG_WRITE(D3VGA_CONTROL, 0);
255 REG_WRITE(D4VGA_CONTROL, 0);
256 REG_WRITE(D5VGA_CONTROL, 0);
257 REG_WRITE(D6VGA_CONTROL, 0);
258}
259
78c77382 260void dcn20_program_triple_buffer(
7ed4e635
HW		 261 const struct dc *dc,
262 struct pipe_ctx *pipe_ctx,
78c77382 263 bool enable_triple_buffer)
7ed4e635
HW		 264{
265 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {
266 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(
267 pipe_ctx->plane_res.hubp,
78c77382 268 enable_triple_buffer);
7ed4e635
HW		 269 }
270}
271
272/* Blank pixel data during initialization */
c70b4016 273void dcn20_init_blank(
7ed4e635
HW		 274 struct dc *dc,
275 struct timing_generator *tg)
276{
f42ea55b 277 struct dce_hwseq *hws = dc->hwseq;
7ed4e635
HW		 278 enum dc_color_space color_space;
279 struct tg_color black_color = {0};
280 struct output_pixel_processor *opp = NULL;
281 struct output_pixel_processor *bottom_opp = NULL;
282 uint32_t num_opps, opp_id_src0, opp_id_src1;
283 uint32_t otg_active_width, otg_active_height;
284
285 /* program opp dpg blank color */
286 color_space = COLOR_SPACE_SRGB;
287 color_space_to_black_color(dc, color_space, &black_color);
288
289 /* get the OTG active size */
290 tg->funcs->get_otg_active_size(tg,
291 &otg_active_width,
292 &otg_active_height);
293
294 /* get the OPTC source */
295 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
245a0221
AC		 296
297 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) {
298 ASSERT(false);
299 return;
300 }
7ed4e635
HW		 301 opp = dc->res_pool->opps[opp_id_src0];
302
303 if (num_opps == 2) {
304 otg_active_width = otg_active_width / 2;
245a0221
AC		 305
306 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) {
307 ASSERT(false);
308 return;
309 }
7ed4e635
HW		 310 bottom_opp = dc->res_pool->opps[opp_id_src1];
311 }
312
313 opp->funcs->opp_set_disp_pattern_generator(
314 opp,
315 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
2057b7e1 316 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
7ed4e635
HW		 317 COLOR_DEPTH_UNDEFINED,
318 &black_color,
319 otg_active_width,
10b4e64e
WL		 320 otg_active_height,
321 0);
7ed4e635
HW		 322
323 if (num_opps == 2) {
324 bottom_opp->funcs->opp_set_disp_pattern_generator(
325 bottom_opp,
326 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
2057b7e1 327 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
7ed4e635
HW		 328 COLOR_DEPTH_UNDEFINED,
329 &black_color,
330 otg_active_width,
10b4e64e
WL		 331 otg_active_height,
332 0);
7ed4e635
HW		 333 }
334
f42ea55b 335 hws->funcs.wait_for_blank_complete(opp);
7ed4e635
HW		 336}
337
78c77382 338void dcn20_dsc_pg_control(
97bda032
HW		 339 struct dce_hwseq *hws,
340 unsigned int dsc_inst,
341 bool power_on)
342{
343 uint32_t power_gate = power_on ? 0 : 1;
344 uint32_t pwr_status = power_on ? 0 : 2;
98ce8cc1 345 uint32_t org_ip_request_cntl = 0;
97bda032
HW		 346
347 if (hws->ctx->dc->debug.disable_dsc_power_gate)
348 return;
349
350 if (REG(DOMAIN16_PG_CONFIG) == 0)
351 return;
352
98ce8cc1
NC		 353 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
354 if (org_ip_request_cntl == 0)
355 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
356
97bda032
HW		 357 switch (dsc_inst) {
358 case 0: /* DSC0 */
359 REG_UPDATE(DOMAIN16_PG_CONFIG,
360 DOMAIN16_POWER_GATE, power_gate);
361
362 REG_WAIT(DOMAIN16_PG_STATUS,
363 DOMAIN16_PGFSM_PWR_STATUS, pwr_status,
364 1, 1000);
365 break;
366 case 1: /* DSC1 */
367 REG_UPDATE(DOMAIN17_PG_CONFIG,
368 DOMAIN17_POWER_GATE, power_gate);
369
370 REG_WAIT(DOMAIN17_PG_STATUS,
371 DOMAIN17_PGFSM_PWR_STATUS, pwr_status,
372 1, 1000);
373 break;
374 case 2: /* DSC2 */
375 REG_UPDATE(DOMAIN18_PG_CONFIG,
376 DOMAIN18_POWER_GATE, power_gate);
377
378 REG_WAIT(DOMAIN18_PG_STATUS,
379 DOMAIN18_PGFSM_PWR_STATUS, pwr_status,
380 1, 1000);
381 break;
382 case 3: /* DSC3 */
383 REG_UPDATE(DOMAIN19_PG_CONFIG,
384 DOMAIN19_POWER_GATE, power_gate);
385
386 REG_WAIT(DOMAIN19_PG_STATUS,
387 DOMAIN19_PGFSM_PWR_STATUS, pwr_status,
388 1, 1000);
389 break;
390 case 4: /* DSC4 */
391 REG_UPDATE(DOMAIN20_PG_CONFIG,
392 DOMAIN20_POWER_GATE, power_gate);
393
394 REG_WAIT(DOMAIN20_PG_STATUS,
395 DOMAIN20_PGFSM_PWR_STATUS, pwr_status,
396 1, 1000);
397 break;
398 case 5: /* DSC5 */
399 REG_UPDATE(DOMAIN21_PG_CONFIG,
400 DOMAIN21_POWER_GATE, power_gate);
401
402 REG_WAIT(DOMAIN21_PG_STATUS,
403 DOMAIN21_PGFSM_PWR_STATUS, pwr_status,
404 1, 1000);
405 break;
406 default:
407 BREAK_TO_DEBUGGER();
408 break;
409 }
98ce8cc1
NC		 410
411 if (org_ip_request_cntl == 0)
412 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
97bda032 413}
7ed4e635 414
78c77382 415void dcn20_dpp_pg_control(
7ed4e635
HW		 416 struct dce_hwseq *hws,
417 unsigned int dpp_inst,
418 bool power_on)
419{
420 uint32_t power_gate = power_on ? 0 : 1;
421 uint32_t pwr_status = power_on ? 0 : 2;
422
423 if (hws->ctx->dc->debug.disable_dpp_power_gate)
424 return;
425 if (REG(DOMAIN1_PG_CONFIG) == 0)
426 return;
427
428 switch (dpp_inst) {
429 case 0: /* DPP0 */
430 REG_UPDATE(DOMAIN1_PG_CONFIG,
431 DOMAIN1_POWER_GATE, power_gate);
432
433 REG_WAIT(DOMAIN1_PG_STATUS,
434 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
435 1, 1000);
436 break;
437 case 1: /* DPP1 */
438 REG_UPDATE(DOMAIN3_PG_CONFIG,
439 DOMAIN3_POWER_GATE, power_gate);
440
441 REG_WAIT(DOMAIN3_PG_STATUS,
442 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
443 1, 1000);
444 break;
445 case 2: /* DPP2 */
446 REG_UPDATE(DOMAIN5_PG_CONFIG,
447 DOMAIN5_POWER_GATE, power_gate);
448
449 REG_WAIT(DOMAIN5_PG_STATUS,
450 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
451 1, 1000);
452 break;
453 case 3: /* DPP3 */
454 REG_UPDATE(DOMAIN7_PG_CONFIG,
455 DOMAIN7_POWER_GATE, power_gate);
456
457 REG_WAIT(DOMAIN7_PG_STATUS,
458 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
459 1, 1000);
460 break;
461 case 4: /* DPP4 */
462 REG_UPDATE(DOMAIN9_PG_CONFIG,
463 DOMAIN9_POWER_GATE, power_gate);
464
465 REG_WAIT(DOMAIN9_PG_STATUS,
466 DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
467 1, 1000);
468 break;
469 case 5: /* DPP5 */
470 /*
471 * Do not power gate DPP5, should be left at HW default, power on permanently.
472 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
473 * reset.
474 * REG_UPDATE(DOMAIN11_PG_CONFIG,
475 * DOMAIN11_POWER_GATE, power_gate);
476 *
477 * REG_WAIT(DOMAIN11_PG_STATUS,
478 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status,
479 * 1, 1000);
480 */
481 break;
482 default:
483 BREAK_TO_DEBUGGER();
484 break;
485 }
486}
487
488
78c77382 489void dcn20_hubp_pg_control(
7ed4e635
HW		 490 struct dce_hwseq *hws,
491 unsigned int hubp_inst,
492 bool power_on)
493{
494 uint32_t power_gate = power_on ? 0 : 1;
495 uint32_t pwr_status = power_on ? 0 : 2;
496
497 if (hws->ctx->dc->debug.disable_hubp_power_gate)
498 return;
499 if (REG(DOMAIN0_PG_CONFIG) == 0)
500 return;
501
502 switch (hubp_inst) {
503 case 0: /* DCHUBP0 */
504 REG_UPDATE(DOMAIN0_PG_CONFIG,
505 DOMAIN0_POWER_GATE, power_gate);
506
507 REG_WAIT(DOMAIN0_PG_STATUS,
508 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
509 1, 1000);
510 break;
511 case 1: /* DCHUBP1 */
512 REG_UPDATE(DOMAIN2_PG_CONFIG,
513 DOMAIN2_POWER_GATE, power_gate);
514
515 REG_WAIT(DOMAIN2_PG_STATUS,
516 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
517 1, 1000);
518 break;
519 case 2: /* DCHUBP2 */
520 REG_UPDATE(DOMAIN4_PG_CONFIG,
521 DOMAIN4_POWER_GATE, power_gate);
522
523 REG_WAIT(DOMAIN4_PG_STATUS,
524 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
525 1, 1000);
526 break;
527 case 3: /* DCHUBP3 */
528 REG_UPDATE(DOMAIN6_PG_CONFIG,
529 DOMAIN6_POWER_GATE, power_gate);
530
531 REG_WAIT(DOMAIN6_PG_STATUS,
532 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
533 1, 1000);
534 break;
535 case 4: /* DCHUBP4 */
536 REG_UPDATE(DOMAIN8_PG_CONFIG,
537 DOMAIN8_POWER_GATE, power_gate);
538
539 REG_WAIT(DOMAIN8_PG_STATUS,
540 DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
541 1, 1000);
542 break;
543 case 5: /* DCHUBP5 */
544 /*
545 * Do not power gate DCHUB5, should be left at HW default, power on permanently.
546 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
547 * reset.
548 * REG_UPDATE(DOMAIN10_PG_CONFIG,
549 * DOMAIN10_POWER_GATE, power_gate);
550 *
551 * REG_WAIT(DOMAIN10_PG_STATUS,
552 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status,
553 * 1, 1000);
554 */
555 break;
556 default:
557 BREAK_TO_DEBUGGER();
558 break;
559 }
560}
561
562
7ed4e635
HW		 563/* disable HW used by plane.
564 * note: cannot disable until disconnect is complete
565 */
78c77382 566void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
7ed4e635 567{
f42ea55b 568 struct dce_hwseq *hws = dc->hwseq;
7ed4e635
HW		 569 struct hubp *hubp = pipe_ctx->plane_res.hubp;
570 struct dpp *dpp = pipe_ctx->plane_res.dpp;
7ed4e635
HW		 571
572 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
573
6bd8d7d3
AC		 574 /* In flip immediate with pipe splitting case GSL is used for
575 * synchronization so we must disable it when the plane is disabled.
576 */
577 if (pipe_ctx->stream_res.gsl_group != 0)
578 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);
579
580 dc->hwss.set_flip_control_gsl(pipe_ctx, false);
581
7ed4e635
HW		 582 hubp->funcs->hubp_clk_cntl(hubp, false);
583
584 dpp->funcs->dpp_dppclk_control(dpp, false, false);
585
7ed4e635 586 hubp->power_gated = true;
7ed4e635 587
f42ea55b 588 hws->funcs.plane_atomic_power_down(dc,
8a31820b
ML		 589 pipe_ctx->plane_res.dpp,
590 pipe_ctx->plane_res.hubp);
7ed4e635
HW		 591
592 pipe_ctx->stream = NULL;
593 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
594 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
595 pipe_ctx->top_pipe = NULL;
596 pipe_ctx->bottom_pipe = NULL;
597 pipe_ctx->plane_state = NULL;
598}
599
600
ff344c8d 601void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
7ed4e635
HW		 602{
603 DC_LOGGER_INIT(dc->ctx->logger);
604
605 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
606 return;
607
608 dcn20_plane_atomic_disable(dc, pipe_ctx);
609
7ed4e635
HW		 610 DC_LOG_DC("Power down front end %d\n",
611 pipe_ctx->pipe_idx);
612}
613
d99f1387
BL		 614static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
615 int opp_cnt)
616{
617 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing);
618 int flow_ctrl_cnt;
619
2665fded 620 if (opp_cnt >= 2)
d99f1387
BL		 621 hblank_halved = true;
622
623 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable -
624 stream->timing.h_border_left -
625 stream->timing.h_border_right;
626
627 if (hblank_halved)
628 flow_ctrl_cnt /= 2;
629
630 /* ODM combine 4:1 case */
631 if (opp_cnt == 4)
632 flow_ctrl_cnt /= 2;
633
634 return flow_ctrl_cnt;
635}
d99f1387 636
7ed4e635
HW		 637enum dc_status dcn20_enable_stream_timing(
638 struct pipe_ctx *pipe_ctx,
639 struct dc_state *context,
640 struct dc *dc)
641{
f42ea55b 642 struct dce_hwseq *hws = dc->hwseq;
7ed4e635 643 struct dc_stream_state *stream = pipe_ctx->stream;
7ed4e635
HW		 644 struct drr_params params = {0};
645 unsigned int event_triggers = 0;
b1f6d01c
DL		 646 struct pipe_ctx *odm_pipe;
647 int opp_cnt = 1;
648 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
d99f1387
BL		 649 bool interlace = stream->timing.flags.INTERLACE;
650 int i;
d99f1387
BL		 651 struct mpc_dwb_flow_control flow_control;
652 struct mpc *mpc = dc->res_pool->mpc;
653 bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing));
654
7ed4e635
HW		 655 /* by upper caller loop, pipe0 is parent pipe and be called first.
656 * back end is set up by for pipe0. Other children pipe share back end
657 * with pipe 0. No program is needed.
658 */
659 if (pipe_ctx->top_pipe != NULL)
660 return DC_OK;
661
662 /* TODO check if timing_changed, disable stream if timing changed */
663
b1f6d01c
DL		 664 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
665 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
666 opp_cnt++;
667 }
2b162fd3 668
b1f6d01c 669 if (opp_cnt > 1)
7ed4e635
HW		 670 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
671 pipe_ctx->stream_res.tg,
b1f6d01c 672 opp_inst, opp_cnt,
2b162fd3 673 &pipe_ctx->stream->timing);
b1f6d01c 674
7ed4e635
HW		 675 /* HW program guide assume display already disable
676 * by unplug sequence. OTG assume stop.
677 */
678 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
679
680 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
681 pipe_ctx->clock_source,
682 &pipe_ctx->stream_res.pix_clk_params,
683 &pipe_ctx->pll_settings)) {
684 BREAK_TO_DEBUGGER();
685 return DC_ERROR_UNEXPECTED;
686 }
687
1ef893e2
YS		 688 if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal)))
689 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);
690
7ed4e635
HW		 691 pipe_ctx->stream_res.tg->funcs->program_timing(
692 pipe_ctx->stream_res.tg,
693 &stream->timing,
694 pipe_ctx->pipe_dlg_param.vready_offset,
695 pipe_ctx->pipe_dlg_param.vstartup_start,
696 pipe_ctx->pipe_dlg_param.vupdate_offset,
697 pipe_ctx->pipe_dlg_param.vupdate_width,
698 pipe_ctx->stream->signal,
699 true);
700
d99f1387
BL		 701 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1;
702 flow_control.flow_ctrl_mode = 0;
703 flow_control.flow_ctrl_cnt0 = 0x80;
704 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt);
705 if (mpc->funcs->set_out_rate_control) {
706 for (i = 0; i < opp_cnt; ++i) {
707 mpc->funcs->set_out_rate_control(
708 mpc, opp_inst[i],
709 true,
710 rate_control_2x_pclk,
711 &flow_control);
712 }
713 }
20f2ffe5 714
b1f6d01c 715 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
7ed4e635
HW		 716 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
717 odm_pipe->stream_res.opp,
718 true);
719
7ed4e635
HW		 720 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
721 pipe_ctx->stream_res.opp,
722 true);
723
f42ea55b 724 hws->funcs.blank_pixel_data(dc, pipe_ctx, true);
7ed4e635
HW		 725
726 /* VTG is within DCHUB command block. DCFCLK is always on */
727 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
728 BREAK_TO_DEBUGGER();
729 return DC_ERROR_UNEXPECTED;
730 }
731
f42ea55b 732 hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp);
7ed4e635
HW		 733
734 params.vertical_total_min = stream->adjust.v_total_min;
735 params.vertical_total_max = stream->adjust.v_total_max;
470e2ca5
BZ		 736 params.vertical_total_mid = stream->adjust.v_total_mid;
737 params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num;
7ed4e635
HW		 738 if (pipe_ctx->stream_res.tg->funcs->set_drr)
739 pipe_ctx->stream_res.tg->funcs->set_drr(
740 pipe_ctx->stream_res.tg, &params);
741
742 // DRR should set trigger event to monitor surface update event
743 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
744 event_triggers = 0x80;
5b5abe95
AK		 745 /* Event triggers and num frames initialized for DRR, but can be
746 * later updated for PSR use. Note DRR trigger events are generated
747 * regardless of whether num frames met.
748 */
7ed4e635
HW		 749 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
750 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
5b5abe95 751 pipe_ctx->stream_res.tg, event_triggers, 2);
7ed4e635
HW		 752
753 /* TODO program crtc source select for non-virtual signal*/
754 /* TODO program FMT */
755 /* TODO setup link_enc */
756 /* TODO set stream attributes */
757 /* TODO program audio */
758 /* TODO enable stream if timing changed */
759 /* TODO unblank stream if DP */
760
761 return DC_OK;
762}
763
764void dcn20_program_output_csc(struct dc *dc,
765 struct pipe_ctx *pipe_ctx,
766 enum dc_color_space colorspace,
767 uint16_t *matrix,
768 int opp_id)
769{
770 struct mpc *mpc = dc->res_pool->mpc;
771 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
54461859
CL		 772 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
773
774 if (mpc->funcs->power_on_mpc_mem_pwr)
775 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
7ed4e635
HW		 776
777 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
778 if (mpc->funcs->set_output_csc != NULL)
779 mpc->funcs->set_output_csc(mpc,
780 opp_id,
781 matrix,
782 ocsc_mode);
783 } else {
784 if (mpc->funcs->set_ocsc_default != NULL)
785 mpc->funcs->set_ocsc_default(mpc,
786 opp_id,
787 colorspace,
788 ocsc_mode);
789 }
790}
791
78c77382 792bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
7ed4e635
HW		 793 const struct dc_stream_state *stream)
794{
795 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
796 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
797 struct pwl_params *params = NULL;
798 /*
799 * program OGAM only for the top pipe
800 * if there is a pipe split then fix diagnostic is required:
801 * how to pass OGAM parameter for stream.
802 * if programming for all pipes is required then remove condition
803 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic.
804 */
54461859
CL		 805 if (mpc->funcs->power_on_mpc_mem_pwr)
806 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
b1f6d01c 807 if (pipe_ctx->top_pipe == NULL
7ed4e635
HW		 808 && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
809 if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
810 params = &stream->out_transfer_func->pwl;
811 else if (pipe_ctx->stream->out_transfer_func->type ==
812 TF_TYPE_DISTRIBUTED_POINTS &&
813 cm_helper_translate_curve_to_hw_format(
814 stream->out_transfer_func,
815 &mpc->blender_params, false))
816 params = &mpc->blender_params;
817 /*
818 * there is no ROM
819 */
820 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
821 BREAK_TO_DEBUGGER();
822 }
823 /*
824 * if above if is not executed then 'params' equal to 0 and set in bypass
825 */
826 mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
827
828 return true;
829}
830
ff344c8d 831bool dcn20_set_blend_lut(
7ed4e635
HW		 832 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
833{
834 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
835 bool result = true;
836 struct pwl_params *blend_lut = NULL;
837
838 if (plane_state->blend_tf) {
839 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
840 blend_lut = &plane_state->blend_tf->pwl;
841 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
842 cm_helper_translate_curve_to_hw_format(
843 plane_state->blend_tf,
844 &dpp_base->regamma_params, false);
845 blend_lut = &dpp_base->regamma_params;
846 }
847 }
848 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
849
850 return result;
851}
852
ff344c8d 853bool dcn20_set_shaper_3dlut(
7ed4e635
HW		 854 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
855{
856 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
857 bool result = true;
858 struct pwl_params *shaper_lut = NULL;
859
860 if (plane_state->in_shaper_func) {
861 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
862 shaper_lut = &plane_state->in_shaper_func->pwl;
863 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
864 cm_helper_translate_curve_to_hw_format(
865 plane_state->in_shaper_func,
866 &dpp_base->shaper_params, true);
867 shaper_lut = &dpp_base->shaper_params;
868 }
869 }
870
871 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut);
872 if (plane_state->lut3d_func &&
a2080098 873 plane_state->lut3d_func->state.bits.initialized == 1)
7ed4e635
HW		 874 result = dpp_base->funcs->dpp_program_3dlut(dpp_base,
875 &plane_state->lut3d_func->lut_3d);
876 else
877 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL);
878
7ed4e635
HW		 879 return result;
880}
881
78c77382
AK		 882bool dcn20_set_input_transfer_func(struct dc *dc,
883 struct pipe_ctx *pipe_ctx,
884 const struct dc_plane_state *plane_state)
7ed4e635 885{
f42ea55b 886 struct dce_hwseq *hws = dc->hwseq;
7ed4e635
HW		 887 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
888 const struct dc_transfer_func *tf = NULL;
889 bool result = true;
890 bool use_degamma_ram = false;
891
892 if (dpp_base == NULL || plane_state == NULL)
893 return false;
894
f42ea55b
AK		 895 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
896 hws->funcs.set_blend_lut(pipe_ctx, plane_state);
7ed4e635
HW		 897
898 if (plane_state->in_transfer_func)
899 tf = plane_state->in_transfer_func;
900
901
902 if (tf == NULL) {
903 dpp_base->funcs->dpp_set_degamma(dpp_base,
904 IPP_DEGAMMA_MODE_BYPASS);
905 return true;
906 }
907
908 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS)
909 use_degamma_ram = true;
910
911 if (use_degamma_ram == true) {
912 if (tf->type == TF_TYPE_HWPWL)
913 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
914 &tf->pwl);
915 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
916 cm_helper_translate_curve_to_degamma_hw_format(tf,
917 &dpp_base->degamma_params);
918 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
919 &dpp_base->degamma_params);
920 }
921 return true;
922 }
923 /* handle here the optimized cases when de-gamma ROM could be used.
924 *
925 */
926 if (tf->type == TF_TYPE_PREDEFINED) {
927 switch (tf->tf) {
928 case TRANSFER_FUNCTION_SRGB:
929 dpp_base->funcs->dpp_set_degamma(dpp_base,
930 IPP_DEGAMMA_MODE_HW_sRGB);
931 break;
932 case TRANSFER_FUNCTION_BT709:
933 dpp_base->funcs->dpp_set_degamma(dpp_base,
934 IPP_DEGAMMA_MODE_HW_xvYCC);
935 break;
936 case TRANSFER_FUNCTION_LINEAR:
937 dpp_base->funcs->dpp_set_degamma(dpp_base,
938 IPP_DEGAMMA_MODE_BYPASS);
939 break;
940 case TRANSFER_FUNCTION_PQ:
e6616410
RA		 941 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL);
942 cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params);
943 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params);
944 result = true;
945 break;
7ed4e635
HW		 946 default:
947 result = false;
948 break;
949 }
950 } else if (tf->type == TF_TYPE_BYPASS)
951 dpp_base->funcs->dpp_set_degamma(dpp_base,
952 IPP_DEGAMMA_MODE_BYPASS);
953 else {
954 /*
955 * if we are here, we did not handle correctly.
956 * fix is required for this use case
957 */
958 BREAK_TO_DEBUGGER();
959 dpp_base->funcs->dpp_set_degamma(dpp_base,
960 IPP_DEGAMMA_MODE_BYPASS);
961 }
962
963 return result;
964}
965
78c77382 966void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
7ed4e635 967{
b1f6d01c
DL		 968 struct pipe_ctx *odm_pipe;
969 int opp_cnt = 1;
970 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
7ed4e635 971
b1f6d01c
DL		 972 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
973 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
974 opp_cnt++;
975 }
2b162fd3 976
b1f6d01c 977 if (opp_cnt > 1)
7ed4e635
HW		 978 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
979 pipe_ctx->stream_res.tg,
b1f6d01c 980 opp_inst, opp_cnt,
2b162fd3 981 &pipe_ctx->stream->timing);
b1f6d01c 982 else
7ed4e635
HW		 983 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
984 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
985}
986
987void dcn20_blank_pixel_data(
988 struct dc *dc,
989 struct pipe_ctx *pipe_ctx,
990 bool blank)
991{
7ed4e635
HW		 992 struct tg_color black_color = {0};
993 struct stream_resource *stream_res = &pipe_ctx->stream_res;
994 struct dc_stream_state *stream = pipe_ctx->stream;
324707fd 995 enum dc_color_space color_space = stream->output_color_space;
7ed4e635 996 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
2057b7e1 997 enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
b1f6d01c
DL		 998 struct pipe_ctx *odm_pipe;
999 int odm_cnt = 1;
7ed4e635 1000
7ed4e635
HW		 1001 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
1002 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
1003
31635887
WL		 1004 if (stream->link->test_pattern_enabled)
1005 return;
1006
324707fd 1007 /* get opp dpg blank color */
7ed4e635
HW		 1008 color_space_to_black_color(dc, color_space, &black_color);
1009
b1f6d01c
DL		 1010 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1011 odm_cnt++;
1012
1013 width = width / odm_cnt;
7ed4e635
HW		 1014
1015 if (blank) {
3ba01817 1016 dc->hwss.set_abm_immediate_disable(pipe_ctx);
7ed4e635 1017
2057b7e1 1018 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {
324707fd 1019 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
2057b7e1
WL		 1020 test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
1021 }
324707fd
JA		 1022 } else {
1023 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
1024 }
7ed4e635 1025
dbf5256b
JA		 1026 dc->hwss.set_disp_pattern_generator(dc,
1027 pipe_ctx,
7ed4e635 1028 test_pattern,
2057b7e1 1029 test_pattern_color_space,
7ed4e635
HW		 1030 stream->timing.display_color_depth,
1031 &black_color,
1032 width,
10b4e64e
WL		 1033 height,
1034 0);
7ed4e635 1035
b1f6d01c 1036 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
dbf5256b
JA		 1037 dc->hwss.set_disp_pattern_generator(dc,
1038 odm_pipe,
436d9635 1039 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ?
324707fd 1040 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
2057b7e1 1041 test_pattern_color_space,
7ed4e635
HW		 1042 stream->timing.display_color_depth,
1043 &black_color,
1044 width,
10b4e64e
WL		 1045 height,
1046 0);
7ed4e635
HW		 1047 }
1048
1049 if (!blank)
1050 if (stream_res->abm) {
474ac4a8 1051 dc->hwss.set_pipe(pipe_ctx);
7ed4e635
HW		 1052 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
1053 }
1054}
1055
1056
1057static void dcn20_power_on_plane(
1058 struct dce_hwseq *hws,
1059 struct pipe_ctx *pipe_ctx)
1060{
1061 DC_LOGGER_INIT(hws->ctx->logger);
1062 if (REG(DC_IP_REQUEST_CNTL)) {
1063 REG_SET(DC_IP_REQUEST_CNTL, 0,
1064 IP_REQUEST_EN, 1);
c74f865f
NK		 1065
1066 if (hws->funcs.dpp_pg_control)
1067 hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);
1068
1069 if (hws->funcs.hubp_pg_control)
1070 hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);
1071
7ed4e635
HW		 1072 REG_SET(DC_IP_REQUEST_CNTL, 0,
1073 IP_REQUEST_EN, 0);
1074 DC_LOG_DEBUG(
1075 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);
1076 }
1077}
1078
ff344c8d 1079void dcn20_enable_plane(
7ed4e635
HW		 1080 struct dc *dc,
1081 struct pipe_ctx *pipe_ctx,
1082 struct dc_state *context)
1083{
1084 //if (dc->debug.sanity_checks) {
1085 // dcn10_verify_allow_pstate_change_high(dc);
1086 //}
1087 dcn20_power_on_plane(dc->hwseq, pipe_ctx);
1088
1089 /* enable DCFCLK current DCHUB */
1090 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1091
89cb5614
ZYL		 1092 /* initialize HUBP on power up */
1093 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);
1094
7ed4e635
HW		 1095 /* make sure OPP_PIPE_CLOCK_EN = 1 */
1096 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1097 pipe_ctx->stream_res.opp,
1098 true);
1099
1100/* TODO: enable/disable in dm as per update type.
1101 if (plane_state) {
1102 DC_LOG_DC(dc->ctx->logger,
1103 "Pipe:%d 0x%x: addr hi:0x%x, "
1104 "addr low:0x%x, "
1105 "src: %d, %d, %d,"
1106 " %d; dst: %d, %d, %d, %d;\n",
1107 pipe_ctx->pipe_idx,
1108 plane_state,
1109 plane_state->address.grph.addr.high_part,
1110 plane_state->address.grph.addr.low_part,
1111 plane_state->src_rect.x,
1112 plane_state->src_rect.y,
1113 plane_state->src_rect.width,
1114 plane_state->src_rect.height,
1115 plane_state->dst_rect.x,
1116 plane_state->dst_rect.y,
1117 plane_state->dst_rect.width,
1118 plane_state->dst_rect.height);
1119
1120 DC_LOG_DC(dc->ctx->logger,
1121 "Pipe %d: width, height, x, y format:%d\n"
1122 "viewport:%d, %d, %d, %d\n"
1123 "recout: %d, %d, %d, %d\n",
1124 pipe_ctx->pipe_idx,
1125 plane_state->format,
1126 pipe_ctx->plane_res.scl_data.viewport.width,
1127 pipe_ctx->plane_res.scl_data.viewport.height,
1128 pipe_ctx->plane_res.scl_data.viewport.x,
1129 pipe_ctx->plane_res.scl_data.viewport.y,
1130 pipe_ctx->plane_res.scl_data.recout.width,
1131 pipe_ctx->plane_res.scl_data.recout.height,
1132 pipe_ctx->plane_res.scl_data.recout.x,
1133 pipe_ctx->plane_res.scl_data.recout.y);
1134 print_rq_dlg_ttu(dc, pipe_ctx);
1135 }
1136*/
bda9afda 1137 if (dc->vm_pa_config.valid) {
7ed4e635
HW		 1138 struct vm_system_aperture_param apt;
1139
1140 apt.sys_default.quad_part = 0;
7ed4e635 1141
6d988a55
JL		 1142 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr;
1143 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr;
7ed4e635
HW		 1144
1145 // Program system aperture settings
1146 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);
1147 }
1148
0c66824b
QZ		 1149 if (!pipe_ctx->top_pipe
1150 && pipe_ctx->plane_state
1151 && pipe_ctx->plane_state->flip_int_enabled
1152 && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)
1153 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);
1154
7ed4e635
HW		 1155// if (dc->debug.sanity_checks) {
1156// dcn10_verify_allow_pstate_change_high(dc);
1157// }
1158}
1159
ff344c8d 1160void dcn20_pipe_control_lock(
7ed4e635
HW		 1161 struct dc *dc,
1162 struct pipe_ctx *pipe,
1163 bool lock)
1164{
6f2239cc 1165 struct pipe_ctx *temp_pipe;
7ed4e635
HW		 1166 bool flip_immediate = false;
1167
1168 /* use TG master update lock to lock everything on the TG
1169 * therefore only top pipe need to lock
1170 */
009114f6 1171 if (!pipe || pipe->top_pipe)
7ed4e635
HW		 1172 return;
1173
1174 if (pipe->plane_state != NULL)
1175 flip_immediate = pipe->plane_state->flip_immediate;
1176
4f6274b3
AL		 1177 if (pipe->stream_res.gsl_group > 0) {
1178 temp_pipe = pipe->bottom_pipe;
1179 while (!flip_immediate && temp_pipe) {
1180 if (temp_pipe->plane_state != NULL)
1181 flip_immediate = temp_pipe->plane_state->flip_immediate;
1182 temp_pipe = temp_pipe->bottom_pipe;
1183 }
6f2239cc
AL		 1184 }
1185
0e29be9e
AD		 1186 if (flip_immediate && lock) {
1187 const int TIMEOUT_FOR_FLIP_PENDING = 100000;
1188 int i;
1189
e9917ef8
AC		 1190 temp_pipe = pipe;
1191 while (temp_pipe) {
1192 if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) {
1193 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
1194 if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp))
1195 break;
1196 udelay(1);
1197 }
1198
1199 /* no reason it should take this long for immediate flips */
1200 ASSERT(i != TIMEOUT_FOR_FLIP_PENDING);
0e29be9e 1201 }
e9917ef8 1202 temp_pipe = temp_pipe->bottom_pipe;
0e29be9e
AD		 1203 }
1204 }
1205
7ed4e635
HW		 1206 /* In flip immediate and pipe splitting case, we need to use GSL
1207 * for synchronization. Only do setup on locking and on flip type change.
1208 */
86c5a9e3 1209 if (lock && (pipe->bottom_pipe != NULL || !flip_immediate))
7ed4e635
HW		 1210 if ((flip_immediate && pipe->stream_res.gsl_group == 0) ||
1211 (!flip_immediate && pipe->stream_res.gsl_group > 0))
2e2e73fc 1212 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
7ed4e635 1213
ec76bd6f
AL		 1214 if (pipe->plane_state != NULL)
1215 flip_immediate = pipe->plane_state->flip_immediate;
1216
6f2239cc
AL		 1217 temp_pipe = pipe->bottom_pipe;
1218 while (flip_immediate && temp_pipe) {
1219 if (temp_pipe->plane_state != NULL)
1220 flip_immediate = temp_pipe->plane_state->flip_immediate;
1221 temp_pipe = temp_pipe->bottom_pipe;
1222 }
1223
1224 if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state &&
1225 !flip_immediate)
1226 dcn20_setup_gsl_group_as_lock(dc, pipe, false);
1227
dc6e2448
WW		 1228 if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) {
1229 union dmub_hw_lock_flags hw_locks = { 0 };
1230 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
1231
1232 hw_locks.bits.lock_pipe = 1;
1233 inst_flags.otg_inst = pipe->stream_res.tg->inst;
1234
1235 if (pipe->plane_state != NULL)
1236 hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips;
1237
1238 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
1239 lock,
1240 &hw_locks,
1241 &inst_flags);
1242 } else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {
7ed4e635
HW		 1243 if (lock)
1244 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);
1245 else
1246 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg);
1247 } else {
1248 if (lock)
1249 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1250 else
1251 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1252 }
1253}
1254
b6e881c9 1255static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe)
7ed4e635 1256{
b6e881c9 1257 new_pipe->update_flags.raw = 0;
7ed4e635 1258
b6e881c9
DL		 1259 /* Exit on unchanged, unused pipe */
1260 if (!old_pipe->plane_state && !new_pipe->plane_state)
7ed4e635 1261 return;
b6e881c9 1262 /* Detect pipe enable/disable */
c0838cbe 1263 if (!old_pipe->plane_state && new_pipe->plane_state) {
b6e881c9
DL		 1264 new_pipe->update_flags.bits.enable = 1;
1265 new_pipe->update_flags.bits.mpcc = 1;
1266 new_pipe->update_flags.bits.dppclk = 1;
1267 new_pipe->update_flags.bits.hubp_interdependent = 1;
1268 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1269 new_pipe->update_flags.bits.gamut_remap = 1;
1270 new_pipe->update_flags.bits.scaler = 1;
1271 new_pipe->update_flags.bits.viewport = 1;
1272 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1273 new_pipe->update_flags.bits.odm = 1;
1274 new_pipe->update_flags.bits.global_sync = 1;
1275 }
1276 return;
1277 }
1278 if (old_pipe->plane_state && !new_pipe->plane_state) {
1279 new_pipe->update_flags.bits.disable = 1;
1280 return;
1281 }
7ed4e635 1282
498563cf
JX		 1283 /* Detect plane change */
1284 if (old_pipe->plane_state != new_pipe->plane_state) {
1285 new_pipe->update_flags.bits.plane_changed = true;
1286 }
1287
b6e881c9
DL		 1288 /* Detect top pipe only changes */
1289 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1290 /* Detect odm changes */
1291 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe
1292 && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx)
1293 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe)
1294 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe)
1295 || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1296 new_pipe->update_flags.bits.odm = 1;
1297
1298 /* Detect global sync changes */
1299 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset
1300 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start
1301 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset
1302 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width)
1303 new_pipe->update_flags.bits.global_sync = 1;
1304 }
21ffcc94 1305
b6e881c9
DL		 1306 /*
1307 * Detect opp / tg change, only set on change, not on enable
1308 * Assume mpcc inst = pipe index, if not this code needs to be updated
1309 * since mpcc is what is affected by these. In fact all of our sequence
1310 * makes this assumption at the moment with how hubp reset is matched to
1311 * same index mpcc reset.
1312 */
1313 if (old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1314 new_pipe->update_flags.bits.opp_changed = 1;
1315 if (old_pipe->stream_res.tg != new_pipe->stream_res.tg)
1316 new_pipe->update_flags.bits.tg_changed = 1;
1317
ed8ec123
DL		 1318 /*
1319 * Detect mpcc blending changes, only dpp inst and opp matter here,
1320 * mpccs getting removed/inserted update connected ones during their own
1321 * programming
1322 */
b6e881c9 1323 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp
ed8ec123 1324 || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
b6e881c9
DL		 1325 new_pipe->update_flags.bits.mpcc = 1;
1326
1327 /* Detect dppclk change */
1328 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz)
1329 new_pipe->update_flags.bits.dppclk = 1;
1330
1331 /* Check for scl update */
1332 if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data)))
1333 new_pipe->update_flags.bits.scaler = 1;
1334 /* Check for vp update */
1335 if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect))
1336 || memcmp(&old_pipe->plane_res.scl_data.viewport_c,
1337 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect)))
1338 new_pipe->update_flags.bits.viewport = 1;
1339
1340 /* Detect dlg/ttu/rq updates */
1341 {
1342 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs;
1343 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs;
1344 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs;
1345 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs;
1346
1347 /* Detect pipe interdependent updates */
1348 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch ||
1349 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch ||
1350 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c ||
1351 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank ||
1352 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank ||
1353 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip ||
1354 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip ||
1355 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l ||
1356 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c ||
1357 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l ||
1358 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l ||
1359 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c ||
1360 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l ||
1361 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c ||
1362 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 ||
1363 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 ||
1364 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank ||
1365 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) {
1366 old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch;
1367 old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch;
1368 old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c;
1369 old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank;
1370 old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank;
1371 old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip;
1372 old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip;
1373 old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l;
1374 old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c;
1375 old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l;
1376 old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l;
1377 old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c;
1378 old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l;
1379 old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c;
1380 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0;
1381 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1;
1382 old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank;
1383 old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip;
1384 new_pipe->update_flags.bits.hubp_interdependent = 1;
1385 }
1386 /* Detect any other updates to ttu/rq/dlg */
1387 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) ||
1388 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) ||
1389 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs)))
1390 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
21ffcc94 1391 }
b6e881c9 1392}
21ffcc94 1393
b6e881c9
DL		 1394static void dcn20_update_dchubp_dpp(
1395 struct dc *dc,
1396 struct pipe_ctx *pipe_ctx,
1397 struct dc_state *context)
1398{
f42ea55b 1399 struct dce_hwseq *hws = dc->hwseq;
b6e881c9
DL		 1400 struct hubp *hubp = pipe_ctx->plane_res.hubp;
1401 struct dpp *dpp = pipe_ctx->plane_res.dpp;
1402 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
cf27a6d1 1403 bool viewport_changed = false;
7ed4e635 1404
1ea8751b 1405 if (pipe_ctx->update_flags.bits.dppclk)
b6e881c9 1406 dpp->funcs->dpp_dppclk_control(dpp, false, true);
4e0cbbbf 1407
b6e881c9
DL		 1408 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
1409 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
1410 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
1411 */
1412 if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) {
1413 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
1414
1415 hubp->funcs->hubp_setup(
1416 hubp,
1417 &pipe_ctx->dlg_regs,
1418 &pipe_ctx->ttu_regs,
1419 &pipe_ctx->rq_regs,
1420 &pipe_ctx->pipe_dlg_param);
1421 }
1422 if (pipe_ctx->update_flags.bits.hubp_interdependent)
1423 hubp->funcs->hubp_setup_interdependent(
1424 hubp,
1425 &pipe_ctx->dlg_regs,
1426 &pipe_ctx->ttu_regs);
1427
1428 if (pipe_ctx->update_flags.bits.enable ||
498563cf 1429 pipe_ctx->update_flags.bits.plane_changed ||
b6e881c9
DL		 1430 plane_state->update_flags.bits.bpp_change ||
1431 plane_state->update_flags.bits.input_csc_change ||
1432 plane_state->update_flags.bits.color_space_change ||
1433 plane_state->update_flags.bits.coeff_reduction_change) {
1434 struct dc_bias_and_scale bns_params = {0};
1435
1436 // program the input csc
1437 dpp->funcs->dpp_setup(dpp,
1438 plane_state->format,
1439 EXPANSION_MODE_ZERO,
1440 plane_state->input_csc_color_matrix,
1441 plane_state->color_space,
1442 NULL);
1443
1444 if (dpp->funcs->dpp_program_bias_and_scale) {
1445 //TODO :for CNVC set scale and bias registers if necessary
78c77382 1446 build_prescale_params(&bns_params, plane_state);
b6e881c9
DL		 1447 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1448 }
7ed4e635
HW		 1449 }
1450
b6e881c9 1451 if (pipe_ctx->update_flags.bits.mpcc
498563cf 1452 || pipe_ctx->update_flags.bits.plane_changed
b6e881c9
DL		 1453 || plane_state->update_flags.bits.global_alpha_change
1454 || plane_state->update_flags.bits.per_pixel_alpha_change) {
8b0fbb36 1455 // MPCC inst is equal to pipe index in practice
1380c1bf 1456 int mpcc_inst = hubp->inst;
8b0fbb36 1457 int opp_inst;
0120e8b8 1458 int opp_count = dc->res_pool->pipe_count;
8b0fbb36
NA		 1459
1460 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
1461 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
b6e881c9 1462 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
8b0fbb36
NA		 1463 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
1464 break;
b6e881c9 1465 }
7ed4e635 1466 }
f42ea55b 1467 hws->funcs.update_mpcc(dc, pipe_ctx);
b6e881c9 1468 }
7ed4e635 1469
b6e881c9
DL		 1470 if (pipe_ctx->update_flags.bits.scaler ||
1471 plane_state->update_flags.bits.scaling_change ||
1472 plane_state->update_flags.bits.position_change ||
1473 plane_state->update_flags.bits.per_pixel_alpha_change ||
1474 pipe_ctx->stream->update_flags.bits.scaling) {
1475 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;
1476 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_30BPP);
1477 /* scaler configuration */
1478 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
1479 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
1480 }
7ed4e635 1481
b6e881c9 1482 if (pipe_ctx->update_flags.bits.viewport ||
b34659de 1483 (context == dc->current_state && plane_state->update_flags.bits.position_change) ||
b6e881c9 1484 (context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||
cf27a6d1
EY		 1485 (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {
1486
b6e881c9
DL		 1487 hubp->funcs->mem_program_viewport(
1488 hubp,
1489 &pipe_ctx->plane_res.scl_data.viewport,
cf27a6d1
EY		 1490 &pipe_ctx->plane_res.scl_data.viewport_c);
1491 viewport_changed = true;
1492 }
b6e881c9
DL		 1493
1494 /* Any updates are handled in dc interface, just need to apply existing for plane enable */
74cc5f02 1495 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||
8e80d482
PH		 1496 pipe_ctx->update_flags.bits.scaler || viewport_changed == true) &&
1497 pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
b6e881c9
DL		 1498 dc->hwss.set_cursor_position(pipe_ctx);
1499 dc->hwss.set_cursor_attribute(pipe_ctx);
1500
1501 if (dc->hwss.set_cursor_sdr_white_level)
1502 dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
1503 }
7ed4e635 1504
b6e881c9
DL		 1505 /* Any updates are handled in dc interface, just need
1506 * to apply existing for plane enable / opp change */
1507 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed
1508 || pipe_ctx->stream->update_flags.bits.gamut_remap
1509 || pipe_ctx->stream->update_flags.bits.out_csc) {
90d1a626
DV		 1510 /* dpp/cm gamut remap*/
1511 dc->hwss.program_gamut_remap(pipe_ctx);
b6e881c9
DL		 1512
1513 /*call the dcn2 method which uses mpc csc*/
1514 dc->hwss.program_output_csc(dc,
1515 pipe_ctx,
1516 pipe_ctx->stream->output_color_space,
1517 pipe_ctx->stream->csc_color_matrix.matrix,
1518 hubp->opp_id);
7ed4e635
HW		 1519 }
1520
b6e881c9 1521 if (pipe_ctx->update_flags.bits.enable ||
498563cf 1522 pipe_ctx->update_flags.bits.plane_changed ||
b6e881c9
DL		 1523 pipe_ctx->update_flags.bits.opp_changed ||
1524 plane_state->update_flags.bits.pixel_format_change ||
1525 plane_state->update_flags.bits.horizontal_mirror_change ||
1526 plane_state->update_flags.bits.rotation_change ||
1527 plane_state->update_flags.bits.swizzle_change ||
1528 plane_state->update_flags.bits.dcc_change ||
1529 plane_state->update_flags.bits.bpp_change ||
1530 plane_state->update_flags.bits.scaling_change ||
1531 plane_state->update_flags.bits.plane_size_change) {
1532 struct plane_size size = plane_state->plane_size;
1533
1534 size.surface_size = pipe_ctx->plane_res.scl_data.viewport;
1535 hubp->funcs->hubp_program_surface_config(
1536 hubp,
1537 plane_state->format,
1538 &plane_state->tiling_info,
1539 &size,
1540 plane_state->rotation,
1541 &plane_state->dcc,
1542 plane_state->horizontal_mirror,
1543 0);
1544 hubp->power_gated = false;
1545 }
1546
498563cf
JX		 1547 if (pipe_ctx->update_flags.bits.enable ||
1548 pipe_ctx->update_flags.bits.plane_changed ||
1549 plane_state->update_flags.bits.addr_update)
f42ea55b 1550 hws->funcs.update_plane_addr(dc, pipe_ctx);
b6e881c9 1551
cf27a6d1
EY		 1552
1553
e7a30ade 1554 if (pipe_ctx->update_flags.bits.enable)
0b7421f0 1555 hubp->funcs->set_blank(hubp, false);
b6e881c9
DL		 1556}
1557
1558
1559static void dcn20_program_pipe(
1560 struct dc *dc,
1561 struct pipe_ctx *pipe_ctx,
1562 struct dc_state *context)
1563{
f42ea55b 1564 struct dce_hwseq *hws = dc->hwseq;
b6e881c9
DL		 1565 /* Only need to unblank on top pipe */
1566 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level)
1567 && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
f42ea55b 1568 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
b6e881c9 1569
a71e5529
AC		 1570 /* Only update TG on top pipe */
1571 if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe
1572 && !pipe_ctx->prev_odm_pipe) {
1573
b6e881c9
DL		 1574 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1575 pipe_ctx->stream_res.tg,
1576 pipe_ctx->pipe_dlg_param.vready_offset,
1577 pipe_ctx->pipe_dlg_param.vstartup_start,
1578 pipe_ctx->pipe_dlg_param.vupdate_offset,
1579 pipe_ctx->pipe_dlg_param.vupdate_width);
1580
a71e5529
AC		 1581 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);
1582 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
1583
a14e9e02 1584 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
a71e5529 1585 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);
1caba4e8 1586
f42ea55b
AK		 1587 if (hws->funcs.setup_vupdate_interrupt)
1588 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
a14e9e02
DL		 1589 }
1590
b6e881c9 1591 if (pipe_ctx->update_flags.bits.odm)
f42ea55b 1592 hws->funcs.update_odm(dc, context, pipe_ctx);
b6e881c9 1593
868149c9 1594 if (pipe_ctx->update_flags.bits.enable) {
b6e881c9 1595 dcn20_enable_plane(dc, pipe_ctx, context);
868149c9
JA		 1596 if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes)
1597 dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub);
1598 }
b6e881c9 1599
74701238 1600 if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw)
b6e881c9
DL		 1601 dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
1602
1603 if (pipe_ctx->update_flags.bits.enable
46250a0c 1604 || pipe_ctx->plane_state->update_flags.bits.hdr_mult)
f42ea55b 1605 hws->funcs.set_hdr_multiplier(pipe_ctx);
b6e881c9
DL		 1606
1607 if (pipe_ctx->update_flags.bits.enable ||
1608 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
1609 pipe_ctx->plane_state->update_flags.bits.gamma_change)
f42ea55b 1610 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
b6e881c9
DL		 1611
1612 /* dcn10_translate_regamma_to_hw_format takes 750us to finish
1613 * only do gamma programming for powering on, internal memcmp to avoid
1614 * updating on slave planes
1615 */
1616 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf)
f42ea55b 1617 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
377c9d04
JP		 1618
1619 /* If the pipe has been enabled or has a different opp, we
1620 * should reprogram the fmt. This deals with cases where
1621 * interation between mpc and odm combine on different streams
1622 * causes a different pipe to be chosen to odm combine with.
1623 */
1624 if (pipe_ctx->update_flags.bits.enable
1625 || pipe_ctx->update_flags.bits.opp_changed) {
1626
1627 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1628 pipe_ctx->stream_res.opp,
1629 COLOR_SPACE_YCBCR601,
1630 pipe_ctx->stream->timing.display_color_depth,
1631 pipe_ctx->stream->signal);
1632
1633 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1634 pipe_ctx->stream_res.opp,
1635 &pipe_ctx->stream->bit_depth_params,
1636 &pipe_ctx->stream->clamping);
1637 }
b6e881c9
DL		 1638}
1639
78c77382 1640void dcn20_program_front_end_for_ctx(
b6e881c9
DL		 1641 struct dc *dc,
1642 struct dc_state *context)
1643{
b6e881c9 1644 int i;
f42ea55b 1645 struct dce_hwseq *hws = dc->hwseq;
b6e881c9
DL		 1646 DC_LOGGER_INIT(dc->ctx->logger);
1647
d5c0af57
BL		 1648 /* Carry over GSL groups in case the context is changing. */
1649 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1650 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1651 struct pipe_ctx *old_pipe_ctx =
1652 &dc->current_state->res_ctx.pipe_ctx[i];
1653
1654 if (pipe_ctx->stream == old_pipe_ctx->stream)
1655 pipe_ctx->stream_res.gsl_group =
1656 old_pipe_ctx->stream_res.gsl_group;
1657 }
1658
091018a5
AC		 1659 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
1660 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1661 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
009114f6 1662
091018a5
AC		 1663 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) {
1664 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
009114f6
AK		 1665 /*turn off triple buffer for full update*/
1666 dc->hwss.program_triplebuffer(
091018a5 1667 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
009114f6
AK		 1668 }
1669 }
1670 }
1671
b6e881c9
DL		 1672 /* Set pipe update flags and lock pipes */
1673 for (i = 0; i < dc->res_pool->pipe_count; i++)
1674 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i],
1675 &context->res_ctx.pipe_ctx[i]);
7ed4e635 1676
b6e881c9
DL		 1677 /* OTG blank before disabling all front ends */
1678 for (i = 0; i < dc->res_pool->pipe_count; i++)
1679 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1680 && !context->res_ctx.pipe_ctx[i].top_pipe
1681 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe
1682 && context->res_ctx.pipe_ctx[i].stream)
f42ea55b 1683 hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);
b6e881c9 1684
d4930b7a 1685
b6e881c9
DL		 1686 /* Disconnect mpcc */
1687 for (i = 0; i < dc->res_pool->pipe_count; i++)
1688 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1689 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {
f42ea55b 1690 hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
b6e881c9 1691 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
7ed4e635
HW		 1692 }
1693
b6e881c9
DL		 1694 /*
1695 * Program all updated pipes, order matters for mpcc setup. Start with
1696 * top pipe and program all pipes that follow in order
1697 */
1698 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1699 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
7ed4e635 1700
b6e881c9
DL		 1701 if (pipe->plane_state && !pipe->top_pipe) {
1702 while (pipe) {
1703 dcn20_program_pipe(dc, pipe, context);
1704 pipe = pipe->bottom_pipe;
1705 }
1706 /* Program secondary blending tree and writeback pipes */
1707 pipe = &context->res_ctx.pipe_ctx[i];
1708 if (!pipe->prev_odm_pipe && pipe->stream->num_wb_info > 0
1709 && (pipe->update_flags.raw || pipe->plane_state->update_flags.raw || pipe->stream->update_flags.raw)
f42ea55b
AK		 1710 && hws->funcs.program_all_writeback_pipes_in_tree)
1711 hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
b6e881c9
DL		 1712 }
1713 }
bbf5f6c3
AK		 1714}
1715
1716void dcn20_post_unlock_program_front_end(
1717 struct dc *dc,
1718 struct dc_state *context)
1719{
1720 int i;
1721 const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100;
d9758768 1722 struct dce_hwseq *hwseq = dc->hwseq;
bbf5f6c3
AK		 1723
1724 DC_LOGGER_INIT(dc->ctx->logger);
b6e881c9
DL		 1725
1726 for (i = 0; i < dc->res_pool->pipe_count; i++)
1727 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
1728 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
986936d1
JL		 1729
1730 /*
1731 * If we are enabling a pipe, we need to wait for pending clear as this is a critical
1732 * part of the enable operation otherwise, DM may request an immediate flip which
1733 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which
1734 * is unsupported on DCN.
1735 */
b6e881c9
DL		 1736 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1737 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1738
1739 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable) {
1740 struct hubp *hubp = pipe->plane_res.hubp;
1741 int j = 0;
1742
38259bac 1743 for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000
b6e881c9 1744 && hubp->funcs->hubp_is_flip_pending(hubp); j++)
38259bac 1745 mdelay(1);
986936d1
JL		 1746 }
1747 }
f93e29f0 1748
d209124d
BL		 1749 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1750 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
0b7421f0 1751 struct pipe_ctx *mpcc_pipe;
d209124d
BL		 1752
1753 if (pipe->vtp_locked) {
0b7421f0
AP		 1754 dc->hwseq->funcs.wait_for_blank_complete(pipe->stream_res.opp);
1755 pipe->plane_res.hubp->funcs->set_blank(pipe->plane_res.hubp, true);
d209124d 1756 pipe->vtp_locked = false;
0b7421f0
AP		 1757
1758 for (mpcc_pipe = pipe->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)
1759 mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, true);
1760
1761 for (i = 0; i < dc->res_pool->pipe_count; i++)
1762 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
1763 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
d209124d
BL		 1764 }
1765 }
f93e29f0 1766 /* WA to apply WM setting*/
d9758768 1767 if (hwseq->wa.DEGVIDCN21)
f93e29f0 1768 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);
d9758768
GS		 1769
1770
1771 /* WA for stutter underflow during MPO transitions when adding 2nd plane */
1772 if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) {
1773
1774 if (dc->current_state->stream_status[0].plane_count == 1 &&
1775 context->stream_status[0].plane_count > 1) {
1776
1777 struct timing_generator *tg = dc->res_pool->timing_generators[0];
1778
1779 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false);
1780
1781 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true;
1782 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg);
1783 }
1784 }
7ed4e635
HW		 1785}
1786
7ed4e635
HW		 1787void dcn20_prepare_bandwidth(
1788 struct dc *dc,
1789 struct dc_state *context)
1790{
1791 struct hubbub *hubbub = dc->res_pool->hubbub;
1792
057fc695
JL		 1793 dc->clk_mgr->funcs->update_clocks(
1794 dc->clk_mgr,
1795 context,
1796 false);
1797
7ed4e635 1798 /* program dchubbub watermarks */
89e94bc5 1799 dc->wm_optimized_required = hubbub->funcs->program_watermarks(hubbub,
7ed4e635
HW		 1800 &context->bw_ctx.bw.dcn.watermarks,
1801 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1802 false);
7ed4e635
HW		 1803}
1804
1805void dcn20_optimize_bandwidth(
1806 struct dc *dc,
1807 struct dc_state *context)
1808{
1809 struct hubbub *hubbub = dc->res_pool->hubbub;
1810
4c631826
YS		 1811 /* program dchubbub watermarks */
1812 hubbub->funcs->program_watermarks(hubbub,
1813 &context->bw_ctx.bw.dcn.watermarks,
1814 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1815 true);
7ed4e635 1816
4c631826
YS		 1817 dc->clk_mgr->funcs->update_clocks(
1818 dc->clk_mgr,
1819 context,
1820 true);
7ed4e635
HW		 1821}
1822
1823bool dcn20_update_bandwidth(
1824 struct dc *dc,
1825 struct dc_state *context)
1826{
1827 int i;
f42ea55b 1828 struct dce_hwseq *hws = dc->hwseq;
7ed4e635
HW		 1829
1830 /* recalculate DML parameters */
254eb07c 1831 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false))
7ed4e635 1832 return false;
7ed4e635
HW		 1833
1834 /* apply updated bandwidth parameters */
1835 dc->hwss.prepare_bandwidth(dc, context);
1836
1837 /* update hubp configs for all pipes */
1838 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1839 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1840
1841 if (pipe_ctx->plane_state == NULL)
1842 continue;
1843
1844 if (pipe_ctx->top_pipe == NULL) {
1845 bool blank = !is_pipe_tree_visible(pipe_ctx);
1846
1847 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1848 pipe_ctx->stream_res.tg,
1849 pipe_ctx->pipe_dlg_param.vready_offset,
1850 pipe_ctx->pipe_dlg_param.vstartup_start,
1851 pipe_ctx->pipe_dlg_param.vupdate_offset,
1852 pipe_ctx->pipe_dlg_param.vupdate_width);
1853
3972c350 1854 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
5200c401 1855 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);
1caba4e8 1856
b1f6d01c 1857 if (pipe_ctx->prev_odm_pipe == NULL)
f42ea55b 1858 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);
1caba4e8 1859
f42ea55b
AK		 1860 if (hws->funcs.setup_vupdate_interrupt)
1861 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
7ed4e635
HW		 1862 }
1863
1864 pipe_ctx->plane_res.hubp->funcs->hubp_setup(
1865 pipe_ctx->plane_res.hubp,
1866 &pipe_ctx->dlg_regs,
1867 &pipe_ctx->ttu_regs,
1868 &pipe_ctx->rq_regs,
1869 &pipe_ctx->pipe_dlg_param);
1870 }
1871
1872 return true;
1873}
1874
78c77382 1875void dcn20_enable_writeback(
7ed4e635 1876 struct dc *dc,
edb922b0
JP		 1877 struct dc_writeback_info *wb_info,
1878 struct dc_state *context)
7ed4e635
HW		 1879{
1880 struct dwbc *dwb;
1881 struct mcif_wb *mcif_wb;
1882 struct timing_generator *optc;
1883
1884 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
1885 ASSERT(wb_info->wb_enabled);
1886 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
1887 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
1888
1889 /* set the OPTC source mux */
6a652f6d 1890 optc = dc->res_pool->timing_generators[dwb->otg_inst];
7ed4e635
HW		 1891 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
1892 /* set MCIF_WB buffer and arbitration configuration */
1893 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);
edb922b0 1894 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
7ed4e635
HW		 1895 /* Enable MCIF_WB */
1896 mcif_wb->funcs->enable_mcif(mcif_wb);
1897 /* Enable DWB */
1898 dwb->funcs->enable(dwb, &wb_info->dwb_params);
1899 /* TODO: add sequence to enable/disable warmup */
1900}
1901
1902void dcn20_disable_writeback(
1903 struct dc *dc,
1904 unsigned int dwb_pipe_inst)
1905{
1906 struct dwbc *dwb;
1907 struct mcif_wb *mcif_wb;
1908
1909 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
1910 dwb = dc->res_pool->dwbc[dwb_pipe_inst];
1911 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
1912
1913 dwb->funcs->disable(dwb);
1914 mcif_wb->funcs->disable_mcif(mcif_wb);
1915}
1916
78c77382 1917bool dcn20_wait_for_blank_complete(
7ed4e635
HW		 1918 struct output_pixel_processor *opp)
1919{
1920 int counter;
1921
1922 for (counter = 0; counter < 1000; counter++) {
1923 if (opp->funcs->dpg_is_blanked(opp))
1924 break;
1925
1926 udelay(100);
1927 }
1928
1929 if (counter == 1000) {
1930 dm_error("DC: failed to blank crtc!\n");
1931 return false;
1932 }
1933
1934 return true;
1935}
1936
1937bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)
1938{
1939 struct hubp *hubp = pipe_ctx->plane_res.hubp;
1940
1941 if (!hubp)
1942 return false;
1943 return hubp->funcs->dmdata_status_done(hubp);
1944}
1945
78c77382 1946void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
7ed4e635 1947{
97bda032 1948 struct dce_hwseq *hws = dc->hwseq;
97bda032
HW		 1949
1950 if (pipe_ctx->stream_res.dsc) {
b1f6d01c
DL		 1951 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1952
20cc44c9 1953 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);
b1f6d01c 1954 while (odm_pipe) {
20cc44c9 1955 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);
b1f6d01c
DL		 1956 odm_pipe = odm_pipe->next_odm_pipe;
1957 }
97bda032 1958 }
7ed4e635
HW		 1959}
1960
78c77382 1961void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
7ed4e635 1962{
97bda032 1963 struct dce_hwseq *hws = dc->hwseq;
97bda032
HW		 1964
1965 if (pipe_ctx->stream_res.dsc) {
b1f6d01c
DL		 1966 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1967
20cc44c9 1968 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);
b1f6d01c 1969 while (odm_pipe) {
20cc44c9 1970 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);
b1f6d01c
DL		 1971 odm_pipe = odm_pipe->next_odm_pipe;
1972 }
97bda032 1973 }
7ed4e635
HW		 1974}
1975
1976void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)
1977{
1978 struct dc_dmdata_attributes attr = { 0 };
1979 struct hubp *hubp = pipe_ctx->plane_res.hubp;
1980
1981 attr.dmdata_mode = DMDATA_HW_MODE;
1982 attr.dmdata_size =
1983 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;
1984 attr.address.quad_part =
1985 pipe_ctx->stream->dmdata_address.quad_part;
1986 attr.dmdata_dl_delta = 0;
1987 attr.dmdata_qos_mode = 0;
1988 attr.dmdata_qos_level = 0;
1989 attr.dmdata_repeat = 1; /* always repeat */
1990 attr.dmdata_updated = 1;
1991 attr.dmdata_sw_data = NULL;
1992
1993 hubp->funcs->dmdata_set_attributes(hubp, &attr);
1994}
1995
78c77382 1996void dcn20_init_vm_ctx(
bda9afda
DL		 1997 struct dce_hwseq *hws,
1998 struct dc *dc,
1999 struct dc_virtual_addr_space_config *va_config,
2000 int vmid)
7ed4e635 2001{
bda9afda
DL		 2002 struct dcn_hubbub_virt_addr_config config;
2003
2004 if (vmid == 0) {
2005 ASSERT(0); /* VMID cannot be 0 for vm context */
2006 return;
2007 }
2008
2009 config.page_table_start_addr = va_config->page_table_start_addr;
2010 config.page_table_end_addr = va_config->page_table_end_addr;
2011 config.page_table_block_size = va_config->page_table_block_size_in_bytes;
2012 config.page_table_depth = va_config->page_table_depth;
2013 config.page_table_base_addr = va_config->page_table_base_addr;
2014
2015 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid);
2016}
2017
78c77382 2018int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
bda9afda
DL		 2019{
2020 struct dcn_hubbub_phys_addr_config config;
2021
2022 config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
2023 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
2024 config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
2025 config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
2026 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
2027 config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
2028 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
2029 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
2030 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
ee80de54 2031 config.page_table_default_page_addr = pa_config->page_table_default_page_addr;
bda9afda
DL		 2032
2033 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
7ed4e635
HW		 2034}
2035
2036static bool patch_address_for_sbs_tb_stereo(
2037 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
2038{
2039 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2040 bool sec_split = pipe_ctx->top_pipe &&
2041 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
2042 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2043 (pipe_ctx->stream->timing.timing_3d_format ==
2044 TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2045 pipe_ctx->stream->timing.timing_3d_format ==
2046 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
2047 *addr = plane_state->address.grph_stereo.left_addr;
2048 plane_state->address.grph_stereo.left_addr =
2049 plane_state->address.grph_stereo.right_addr;
2050 return true;
2051 }
2052
2053 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
2054 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
2055 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
2056 plane_state->address.grph_stereo.right_addr =
2057 plane_state->address.grph_stereo.left_addr;
480c5b8f
AL		 2058 plane_state->address.grph_stereo.right_meta_addr =
2059 plane_state->address.grph_stereo.left_meta_addr;
7ed4e635
HW		 2060 }
2061 return false;
2062}
2063
78c77382 2064void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
7ed4e635
HW		 2065{
2066 bool addr_patched = false;
2067 PHYSICAL_ADDRESS_LOC addr;
2068 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
7ed4e635
HW		 2069
2070 if (plane_state == NULL)
2071 return;
2072
2073 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
2074
bda9afda
DL		 2075 // Call Helper to track VMID use
2076 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);
7ed4e635
HW		 2077
2078 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
2079 pipe_ctx->plane_res.hubp,
2080 &plane_state->address,
bda9afda 2081 plane_state->flip_immediate);
7ed4e635
HW		 2082
2083 plane_state->status.requested_address = plane_state->address;
2084
2085 if (plane_state->flip_immediate)
2086 plane_state->status.current_address = plane_state->address;
2087
2088 if (addr_patched)
2089 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
2090}
2091
2092void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
2093 struct dc_link_settings *link_settings)
2094{
2095 struct encoder_unblank_param params = { { 0 } };
2096 struct dc_stream_state *stream = pipe_ctx->stream;
2097 struct dc_link *link = stream->link;
f42ea55b 2098 struct dce_hwseq *hws = link->dc->hwseq;
b1f6d01c 2099 struct pipe_ctx *odm_pipe;
7ed4e635 2100
b1f6d01c
DL		 2101 params.opp_cnt = 1;
2102 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
2103 params.opp_cnt++;
2104 }
7ed4e635
HW		 2105 /* only 3 items below are used by unblank */
2106 params.timing = pipe_ctx->stream->timing;
2107
2108 params.link_settings.link_rate = link_settings->link_rate;
2109
2110 if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
78c77382 2111 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1)
7ed4e635
HW		 2112 params.timing.pix_clk_100hz /= 2;
2113 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
1f332460 2114 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1);
7ed4e635
HW		 2115 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
2116 }
2117
2118 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
f42ea55b 2119 hws->funcs.edp_backlight_control(link, true);
7ed4e635
HW		 2120 }
2121}
2122
78c77382 2123void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
7ed4e635
HW		 2124{
2125 struct timing_generator *tg = pipe_ctx->stream_res.tg;
78c77382 2126 int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
7ed4e635 2127
7fad39ca
EB		 2128 if (start_line < 0)
2129 start_line = 0;
7ed4e635
HW		 2130
2131 if (tg->funcs->setup_vertical_interrupt2)
2132 tg->funcs->setup_vertical_interrupt2(tg, start_line);
2133}
2134
2135static void dcn20_reset_back_end_for_pipe(
2136 struct dc *dc,
2137 struct pipe_ctx *pipe_ctx,
2138 struct dc_state *context)
2139{
2140 int i;
efca0905 2141 struct dc_link *link;
7ed4e635
HW		 2142 DC_LOGGER_INIT(dc->ctx->logger);
2143 if (pipe_ctx->stream_res.stream_enc == NULL) {
2144 pipe_ctx->stream = NULL;
2145 return;
2146 }
2147
2148 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
efca0905
PH		 2149 link = pipe_ctx->stream->link;
2150 /* DPMS may already disable or */
2151 /* dpms_off status is incorrect due to fastboot
2152 * feature. When system resume from S4 with second
2153 * screen only, the dpms_off would be true but
2154 * VBIOS lit up eDP, so check link status too.
2155 */
2156 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
57430404
SSC		 2157 core_link_disable_stream(pipe_ctx);
2158 else if (pipe_ctx->stream_res.audio)
2159 dc->hwss.disable_audio_stream(pipe_ctx);
2160
2161 /* free acquired resources */
2162 if (pipe_ctx->stream_res.audio) {
2163 /*disable az_endpoint*/
2164 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2165
2166 /*free audio*/
2167 if (dc->caps.dynamic_audio == true) {
2168 /*we have to dynamic arbitrate the audio endpoints*/
2169 /*we free the resource, need reset is_audio_acquired*/
2170 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2171 pipe_ctx->stream_res.audio, false);
2172 pipe_ctx->stream_res.audio = NULL;
2173 }
7ed4e635 2174 }
7ed4e635 2175 }
606b3551 2176 else if (pipe_ctx->stream_res.dsc) {
ec16ac6b 2177 dp_set_dsc_enable(pipe_ctx, false);
606b3551 2178 }
7ed4e635
HW		 2179
2180 /* by upper caller loop, parent pipe: pipe0, will be reset last.
2181 * back end share by all pipes and will be disable only when disable
2182 * parent pipe.
2183 */
2184 if (pipe_ctx->top_pipe == NULL) {
9edf202d 2185
3ba01817 2186 dc->hwss.set_abm_immediate_disable(pipe_ctx);
9edf202d 2187
7ed4e635
HW		 2188 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
2189
2190 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
2191 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
2192 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
2193 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
38df0701
WL		 2194
2195 if (pipe_ctx->stream_res.tg->funcs->set_drr)
2196 pipe_ctx->stream_res.tg->funcs->set_drr(
2197 pipe_ctx->stream_res.tg, NULL);
7ed4e635
HW		 2198 }
2199
2200 for (i = 0; i < dc->res_pool->pipe_count; i++)
2201 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
2202 break;
2203
2204 if (i == dc->res_pool->pipe_count)
2205 return;
2206
2207 pipe_ctx->stream = NULL;
2208 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
2209 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
2210}
2211
78c77382 2212void dcn20_reset_hw_ctx_wrap(
7ed4e635
HW		 2213 struct dc *dc,
2214 struct dc_state *context)
2215{
2216 int i;
f42ea55b 2217 struct dce_hwseq *hws = dc->hwseq;
7ed4e635
HW		 2218
2219 /* Reset Back End*/
2220 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
2221 struct pipe_ctx *pipe_ctx_old =
2222 &dc->current_state->res_ctx.pipe_ctx[i];
2223 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2224
2225 if (!pipe_ctx_old->stream)
2226 continue;
2227
b1f6d01c 2228 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
7ed4e635
HW		 2229 continue;
2230
2231 if (!pipe_ctx->stream ||
2232 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2233 struct clock_source *old_clk = pipe_ctx_old->clock_source;
2234
2235 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
f42ea55b
AK		 2236 if (hws->funcs.enable_stream_gating)
2237 hws->funcs.enable_stream_gating(dc, pipe_ctx);
7ed4e635
HW		 2238 if (old_clk)
2239 old_clk->funcs->cs_power_down(old_clk);
2240 }
2241 }
2242}
2243
123c53a9
JL		 2244void dcn20_get_mpctree_visual_confirm_color(
2245 struct pipe_ctx *pipe_ctx,
2246 struct tg_color *color)
2247{
2248 const struct tg_color pipe_colors[6] = {
2249 {MAX_TG_COLOR_VALUE, 0, 0}, // red
31c6b7a9
AC		 2250 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE / 4, 0}, // orange
2251 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, // yellow
2252 {0, MAX_TG_COLOR_VALUE, 0}, // green
2253 {0, 0, MAX_TG_COLOR_VALUE}, // blue
123c53a9 2254 {MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, // purple
123c53a9
JL		 2255 };
2256
2257 struct pipe_ctx *top_pipe = pipe_ctx;
2258
2259 while (top_pipe->top_pipe) {
2260 top_pipe = top_pipe->top_pipe;
2261 }
2262
2263 *color = pipe_colors[top_pipe->pipe_idx];
2264}
2265
78c77382 2266void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
7ed4e635 2267{
f42ea55b 2268 struct dce_hwseq *hws = dc->hwseq;
7ed4e635
HW		 2269 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2270 struct mpcc_blnd_cfg blnd_cfg = { {0} };
473e0ecb 2271 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
7ed4e635
HW		 2272 int mpcc_id;
2273 struct mpcc *new_mpcc;
2274 struct mpc *mpc = dc->res_pool->mpc;
2275 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
2276
2277 // input to MPCC is always RGB, by default leave black_color at 0
2278 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
31c6b7a9 2279 hws->funcs.get_hdr_visual_confirm_color(pipe_ctx, &blnd_cfg.black_color);
7ed4e635 2280 } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
31c6b7a9 2281 hws->funcs.get_surface_visual_confirm_color(pipe_ctx, &blnd_cfg.black_color);
123c53a9 2282 } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) {
31c6b7a9 2283 dcn20_get_mpctree_visual_confirm_color(pipe_ctx, &blnd_cfg.black_color);
7ed4e635
HW		 2284 }
2285
2286 if (per_pixel_alpha)
2287 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
2288 else
2289 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
2290
2291 blnd_cfg.overlap_only = false;
2292 blnd_cfg.global_gain = 0xff;
2293
2294 if (pipe_ctx->plane_state->global_alpha)
2295 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
2296 else
2297 blnd_cfg.global_alpha = 0xff;
2298
2299 blnd_cfg.background_color_bpc = 4;
2300 blnd_cfg.bottom_gain_mode = 0;
2301 blnd_cfg.top_gain = 0x1f000;
2302 blnd_cfg.bottom_inside_gain = 0x1f000;
2303 blnd_cfg.bottom_outside_gain = 0x1f000;
2304 blnd_cfg.pre_multiplied_alpha = per_pixel_alpha;
d99f1387
BL		 2305 if (pipe_ctx->plane_state->format
2306 == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA)
2307 blnd_cfg.pre_multiplied_alpha = false;
7ed4e635
HW		 2308
2309 /*
2310 * TODO: remove hack
2311 * Note: currently there is a bug in init_hw such that
2312 * on resume from hibernate, BIOS sets up MPCC0, and
2313 * we do mpcc_remove but the mpcc cannot go to idle
2314 * after remove. This cause us to pick mpcc1 here,
2315 * which causes a pstate hang for yet unknown reason.
2316 */
2317 mpcc_id = hubp->inst;
2318
c97c8d77 2319 /* If there is no full update, don't need to touch MPC tree*/
68c10ac9
AC		 2320 if (!pipe_ctx->plane_state->update_flags.bits.full_update &&
2321 !pipe_ctx->update_flags.bits.mpcc) {
c97c8d77
NK		 2322 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
2323 return;
2324 }
2325
7ed4e635
HW		 2326 /* check if this MPCC is already being used */
2327 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
2328 /* remove MPCC if being used */
2329 if (new_mpcc != NULL)
2330 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
2331 else
2332 if (dc->debug.sanity_checks)
2333 mpc->funcs->assert_mpcc_idle_before_connect(
2334 dc->res_pool->mpc, mpcc_id);
2335
2336 /* Call MPC to insert new plane */
2337 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2338 mpc_tree_params,
2339 &blnd_cfg,
2340 NULL,
2341 NULL,
2342 hubp->inst,
2343 mpcc_id);
2344
2345 ASSERT(new_mpcc != NULL);
2346 hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2347 hubp->mpcc_id = mpcc_id;
2348}
2349
78c77382 2350void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
f591344e
JP		 2351{
2352 enum dc_lane_count lane_count =
2353 pipe_ctx->stream->link->cur_link_settings.lane_count;
2354
2355 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
2356 struct dc_link *link = pipe_ctx->stream->link;
2357
2358 uint32_t active_total_with_borders;
2359 uint32_t early_control = 0;
2360 struct timing_generator *tg = pipe_ctx->stream_res.tg;
2361
2362 /* For MST, there are multiply stream go to only one link.
2363 * connect DIG back_end to front_end while enable_stream and
2364 * disconnect them during disable_stream
2365 * BY this, it is logic clean to separate stream and link
2366 */
2367 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
2368 pipe_ctx->stream_res.stream_enc->id, true);
2369
ce10a0f3
CL		 2370 if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {
2371 if (link->dc->hwss.program_dmdata_engine)
2372 link->dc->hwss.program_dmdata_engine(pipe_ctx);
2373 }
f591344e
JP		 2374
2375 link->dc->hwss.update_info_frame(pipe_ctx);
2376
2377 /* enable early control to avoid corruption on DP monitor*/
2378 active_total_with_borders =
2379 timing->h_addressable
2380 + timing->h_border_left
2381 + timing->h_border_right;
2382
2383 if (lane_count != 0)
2384 early_control = active_total_with_borders % lane_count;
2385
2386 if (early_control == 0)
2387 early_control = lane_count;
2388
2389 tg->funcs->set_early_control(tg, early_control);
2390
2391 /* enable audio only within mode set */
2392 if (pipe_ctx->stream_res.audio != NULL) {
2393 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2394 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
2395 }
2396}
2397
78c77382 2398void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
f591344e
JP		 2399{
2400 struct dc_stream_state *stream = pipe_ctx->stream;
2401 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2402 bool enable = false;
2403 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
2404 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal)
2405 ? dmdata_dp
2406 : dmdata_hdmi;
2407
2408 /* if using dynamic meta, don't set up generic infopackets */
2409 if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
2410 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
2411 enable = true;
2412 }
2413
2414 if (!hubp)
2415 return;
2416
2417 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
2418 return;
2419
2420 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
2421 hubp->inst, mode);
2422}
2423
78c77382 2424void dcn20_fpga_init_hw(struct dc *dc)
8a31820b
ML		 2425{
2426 int i, j;
2427 struct dce_hwseq *hws = dc->hwseq;
2428 struct resource_pool *res_pool = dc->res_pool;
2429 struct dc_state *context = dc->current_state;
2430
2431 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
2432 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
2433
2434 // Initialize the dccg
2435 if (res_pool->dccg->funcs->dccg_init)
2436 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
2437
2438 //Enable ability to power gate / don't force power on permanently
f42ea55b 2439 hws->funcs.enable_power_gating_plane(hws, true);
8a31820b
ML		 2440
2441 // Specific to FPGA dccg and registers
2442 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
2443 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
2444
f42ea55b 2445 hws->funcs.dccg_init(hws);
8a31820b
ML		 2446
2447 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
2448 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
3ebd17f5
DL		 2449 if (REG(REFCLK_CNTL))
2450 REG_WRITE(REFCLK_CNTL, 0);
8a31820b
ML		 2451 //
2452
2453
2454 /* Blank pixel data with OPP DPG */
2455 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2456 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2457
2458 if (tg->funcs->is_tg_enabled(tg))
2459 dcn20_init_blank(dc, tg);
2460 }
2461
2462 for (i = 0; i < res_pool->timing_generator_count; i++) {
2463 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2464
2465 if (tg->funcs->is_tg_enabled(tg))
2466 tg->funcs->lock(tg);
2467 }
2468
2469 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2470 struct dpp *dpp = res_pool->dpps[i];
2471
2472 dpp->funcs->dpp_reset(dpp);
2473 }
2474
2475 /* Reset all MPCC muxes */
2476 res_pool->mpc->funcs->mpc_init(res_pool->mpc);
2477
2478 /* initialize OPP mpc_tree parameter */
2479 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
2480 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
2481 res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2482 for (j = 0; j < MAX_PIPES; j++)
2483 res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
2484 }
2485
2486 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2487 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2488 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2489 struct hubp *hubp = dc->res_pool->hubps[i];
2490 struct dpp *dpp = dc->res_pool->dpps[i];
2491
2492 pipe_ctx->stream_res.tg = tg;
2493 pipe_ctx->pipe_idx = i;
2494
2495 pipe_ctx->plane_res.hubp = hubp;
2496 pipe_ctx->plane_res.dpp = dpp;
2497 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
2498 hubp->mpcc_id = dpp->inst;
2499 hubp->opp_id = OPP_ID_INVALID;
2500 hubp->power_gated = false;
2501 pipe_ctx->stream_res.opp = NULL;
2502
2503 hubp->funcs->hubp_init(hubp);
2504
2505 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
2506 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2507 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
2508 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
2509 /*to do*/
f42ea55b 2510 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx);
8a31820b
ML		 2511 }
2512
2513 /* initialize DWB pointer to MCIF_WB */
2514 for (i = 0; i < res_pool->res_cap->num_dwb; i++)
2515 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
2516
2517 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2518 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2519
2520 if (tg->funcs->is_tg_enabled(tg))
2521 tg->funcs->unlock(tg);
2522 }
2523
2524 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2525 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2526
2527 dc->hwss.disable_plane(dc, pipe_ctx);
2528
2529 pipe_ctx->stream_res.tg = NULL;
2530 pipe_ctx->plane_res.hubp = NULL;
2531 }
2532
2533 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2534 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2535
2536 tg->funcs->tg_init(tg);
2537 }
2538}
471c1dd9
RA		 2539#ifndef TRIM_FSFT
2540bool dcn20_optimize_timing_for_fsft(struct dc *dc,
2541 struct dc_crtc_timing *timing,
2542 unsigned int max_input_rate_in_khz)
2543{
2544 unsigned int old_v_front_porch;
2545 unsigned int old_v_total;
2546 unsigned int max_input_rate_in_100hz;
2547 unsigned long long new_v_total;
2548
2549 max_input_rate_in_100hz = max_input_rate_in_khz * 10;
2550 if (max_input_rate_in_100hz < timing->pix_clk_100hz)
2551 return false;
2552
2553 old_v_total = timing->v_total;
2554 old_v_front_porch = timing->v_front_porch;
2555
2556 timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz;
2557 timing->pix_clk_100hz = max_input_rate_in_100hz;
2558
2559 new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz);
2560
2561 timing->v_total = new_v_total;
2562 timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total);
2563 return true;
2564}
2565#endif
dbf5256b
JA		 2566
2567void dcn20_set_disp_pattern_generator(const struct dc *dc,
2568 struct pipe_ctx *pipe_ctx,
2569 enum controller_dp_test_pattern test_pattern,
2570 enum controller_dp_color_space color_space,
2571 enum dc_color_depth color_depth,
2572 const struct tg_color *solid_color,
2573 int width, int height, int offset)
2574{
2575 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
2576 color_space, color_depth, solid_color, width, height, offset);
a71e5529 2577}
Linux 6.x block layer and io_uring tree(s)