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drm/amd/display: add bw logging for dcn
[linux-block.git] / drivers / gpu / drm / amd / display / dc / dcn10 / dcn10_resource.c
CommitLineData
70ccab60
HW		 1/*
2* Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services.h"
27#include "dc.h"
28
29#include "resource.h"
30#include "include/irq_service_interface.h"
31#include "dcn10/dcn10_resource.h"
32
33#include "dcn10/dcn10_ipp.h"
34#include "dcn10/dcn10_mpc.h"
35#include "irq/dcn10/irq_service_dcn10.h"
36#include "dcn10/dcn10_transform.h"
37#include "dcn10/dcn10_timing_generator.h"
38#include "dcn10/dcn10_hw_sequencer.h"
39#include "dce110/dce110_hw_sequencer.h"
40#include "dcn10/dcn10_opp.h"
41#include "dce/dce_link_encoder.h"
42#include "dce/dce_stream_encoder.h"
43#include "dce/dce_clocks.h"
44#include "dce/dce_clock_source.h"
45#include "dcn10/dcn10_mem_input.h"
46#include "dce/dce_audio.h"
47#include "dce/dce_hwseq.h"
48#include "../virtual/virtual_stream_encoder.h"
49#include "dce110/dce110_resource.h"
50
51#include "vega10/soc15ip.h"
52
53#include "raven1/DCN/dcn_1_0_offset.h"
54#include "raven1/DCN/dcn_1_0_sh_mask.h"
55
56#include "raven1/NBIO/nbio_7_0_offset.h"
57
58#include "raven1/MMHUB/mmhub_9_1_offset.h"
59#include "raven1/MMHUB/mmhub_9_1_sh_mask.h"
60
61#include "reg_helper.h"
62#include "dce/dce_abm.h"
63#include "dce/dce_dmcu.h"
64
65#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
66 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
67 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
68 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
69 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
70 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
71 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
72 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
73 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
74 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
75 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
76 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
77 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
78 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
79 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
80#endif
81
82
83enum dcn10_clk_src_array_id {
84 DCN10_CLK_SRC_PLL0,
85 DCN10_CLK_SRC_PLL1,
86 DCN10_CLK_SRC_PLL2,
87 DCN10_CLK_SRC_PLL3,
88 DCN10_CLK_SRC_TOTAL
89};
90
91/* begin *********************
92 * macros to expend register list macro defined in HW object header file */
93
94/* DCN */
95#define BASE_INNER(seg) \
96 DCE_BASE__INST0_SEG ## seg
97
98#define BASE(seg) \
99 BASE_INNER(seg)
100
101#define SR(reg_name)\
102 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
103 mm ## reg_name
104
105#define SRI(reg_name, block, id)\
106 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
107 mm ## block ## id ## _ ## reg_name
108
109
110#define SRII(reg_name, block, id)\
111 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
112 mm ## block ## id ## _ ## reg_name
113
114/* NBIO */
115#define NBIO_BASE_INNER(seg) \
116 NBIF_BASE__INST0_SEG ## seg
117
118#define NBIO_BASE(seg) \
119 NBIO_BASE_INNER(seg)
120
121#define NBIO_SR(reg_name)\
122 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
123 mm ## reg_name
124
1f7f3aec
TC		 125/* MMHUB */
126#define MMHUB_BASE_INNER(seg) \
127 MMHUB_BASE__INST0_SEG ## seg
70ccab60 128
1f7f3aec
TC		 129#define MMHUB_BASE(seg) \
130 MMHUB_BASE_INNER(seg)
70ccab60 131
1f7f3aec
TC		 132#define MMHUB_SR(reg_name)\
133 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
70ccab60
HW		 134 mm ## reg_name
135
136/* macros to expend register list macro defined in HW object header file
137 * end *********************/
138
139static const struct dce_disp_clk_registers disp_clk_regs = {
140 CLK_DCN10_REG_LIST()
141};
142
143static const struct dce_disp_clk_shift disp_clk_shift = {
144 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
145};
146
147static const struct dce_disp_clk_mask disp_clk_mask = {
148 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
149};
150
151static const struct dce_dmcu_registers dmcu_regs = {
152 DMCU_DCN10_REG_LIST()
153};
154
155static const struct dce_dmcu_shift dmcu_shift = {
156 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
157};
158
159static const struct dce_dmcu_mask dmcu_mask = {
160 DMCU_MASK_SH_LIST_DCN10(_MASK)
161};
162
163static const struct dce_abm_registers abm_regs = {
164 ABM_DCN10_REG_LIST(0)
165};
166
167static const struct dce_abm_shift abm_shift = {
168 ABM_MASK_SH_LIST_DCN10(__SHIFT)
169};
170
171static const struct dce_abm_mask abm_mask = {
172 ABM_MASK_SH_LIST_DCN10(_MASK)
173};
174
175#define stream_enc_regs(id)\
176[id] = {\
177 SE_DCN_REG_LIST(id),\
178 .TMDS_CNTL = 0,\
179 .AFMT_AVI_INFO0 = 0,\
180 .AFMT_AVI_INFO1 = 0,\
181 .AFMT_AVI_INFO2 = 0,\
182 .AFMT_AVI_INFO3 = 0,\
183}
184
185static const struct dce110_stream_enc_registers stream_enc_regs[] = {
186 stream_enc_regs(0),
187 stream_enc_regs(1),
188 stream_enc_regs(2),
189 stream_enc_regs(3),
190};
191
192static const struct dce_stream_encoder_shift se_shift = {
193 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT)
194};
195
196static const struct dce_stream_encoder_mask se_mask = {
197 SE_COMMON_MASK_SH_LIST_DCN10(_MASK),
198 .AFMT_GENERIC0_UPDATE = 0,
199 .AFMT_GENERIC2_UPDATE = 0,
200 .DP_DYN_RANGE = 0,
201 .DP_YCBCR_RANGE = 0,
202 .HDMI_AVI_INFO_SEND = 0,
203 .HDMI_AVI_INFO_CONT = 0,
204 .HDMI_AVI_INFO_LINE = 0,
205 .DP_SEC_AVI_ENABLE = 0,
206 .AFMT_AVI_INFO_VERSION = 0
207};
208
209#define audio_regs(id)\
210[id] = {\
211 AUD_COMMON_REG_LIST(id)\
212}
213
214static const struct dce_audio_registers audio_regs[] = {
215 audio_regs(0),
216 audio_regs(1),
217 audio_regs(2),
218 audio_regs(3),
219};
220
221#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
222 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
223 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
224 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
225
226static const struct dce_audio_shift audio_shift = {
227 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
228};
229
230static const struct dce_aduio_mask audio_mask = {
231 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
232};
233
234#define aux_regs(id)\
235[id] = {\
236 AUX_REG_LIST(id)\
237}
238
239static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
240 aux_regs(0),
241 aux_regs(1),
242 aux_regs(2),
243 aux_regs(3),
244 aux_regs(4),
245 aux_regs(5)
246};
247
248#define hpd_regs(id)\
249[id] = {\
250 HPD_REG_LIST(id)\
251}
252
253static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
254 hpd_regs(0),
255 hpd_regs(1),
256 hpd_regs(2),
257 hpd_regs(3),
258 hpd_regs(4),
259 hpd_regs(5)
260};
261
262#define link_regs(id)\
263[id] = {\
264 LE_DCN10_REG_LIST(id), \
265 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
266}
267
268static const struct dce110_link_enc_registers link_enc_regs[] = {
269 link_regs(0),
270 link_regs(1),
271 link_regs(2),
272 link_regs(3),
273 link_regs(4),
274 link_regs(5),
275 link_regs(6),
276};
277
278#define ipp_regs(id)\
279[id] = {\
280 IPP_DCN10_REG_LIST(id),\
281}
282
283static const struct dcn10_ipp_registers ipp_regs[] = {
284 ipp_regs(0),
285 ipp_regs(1),
286 ipp_regs(2),
287 ipp_regs(3),
288};
289
290static const struct dcn10_ipp_shift ipp_shift = {
291 IPP_DCN10_MASK_SH_LIST(__SHIFT)
292};
293
294static const struct dcn10_ipp_mask ipp_mask = {
295 IPP_DCN10_MASK_SH_LIST(_MASK),
296};
297
298#define opp_regs(id)\
299[id] = {\
300 OPP_DCN10_REG_LIST(id),\
301}
302
303static const struct dcn10_opp_registers opp_regs[] = {
304 opp_regs(0),
305 opp_regs(1),
306 opp_regs(2),
307 opp_regs(3),
308};
309
310static const struct dcn10_opp_shift opp_shift = {
311 OPP_DCN10_MASK_SH_LIST(__SHIFT)
312};
313
314static const struct dcn10_opp_mask opp_mask = {
315 OPP_DCN10_MASK_SH_LIST(_MASK),
316};
317
318#define tf_regs(id)\
319[id] = {\
320 TF_REG_LIST_DCN(id),\
321}
322
323static const struct dcn_transform_registers tf_regs[] = {
324 tf_regs(0),
325 tf_regs(1),
326 tf_regs(2),
327 tf_regs(3),
328};
329
330static const struct dcn_transform_shift tf_shift = {
331 TF_REG_LIST_SH_MASK_DCN(__SHIFT)
332};
333
334static const struct dcn_transform_mask tf_mask = {
335 TF_REG_LIST_SH_MASK_DCN(_MASK),
336};
337
338
339static const struct dcn_mpc_registers mpc_regs = {
340 MPC_COMMON_REG_LIST_DCN1_0(0),
341 MPC_COMMON_REG_LIST_DCN1_0(1),
342 MPC_COMMON_REG_LIST_DCN1_0(2),
343 MPC_COMMON_REG_LIST_DCN1_0(3),
344};
345
346static const struct dcn_mpc_shift mpc_shift = {
347 MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
348};
349
350static const struct dcn_mpc_mask mpc_mask = {
351 MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),
352};
353
354#define tg_regs(id)\
355[id] = {TG_COMMON_REG_LIST_DCN1_0(id)}
356
357static const struct dcn_tg_registers tg_regs[] = {
358 tg_regs(0),
359 tg_regs(1),
360 tg_regs(2),
361 tg_regs(3),
362};
363
364static const struct dcn_tg_shift tg_shift = {
365 TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
366};
367
368static const struct dcn_tg_mask tg_mask = {
369 TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
370};
371
372
373static const struct bios_registers bios_regs = {
374 NBIO_SR(BIOS_SCRATCH_6)
375};
376
377#define mi_regs(id)\
378[id] = {\
379 MI_DCN10_REG_LIST(id)\
380}
381
382
383static const struct dcn_mi_registers mi_regs[] = {
384 mi_regs(0),
385 mi_regs(1),
386 mi_regs(2),
387 mi_regs(3),
388};
389
390static const struct dcn_mi_shift mi_shift = {
391 MI_DCN10_MASK_SH_LIST(__SHIFT)
392};
393
394static const struct dcn_mi_mask mi_mask = {
395 MI_DCN10_MASK_SH_LIST(_MASK)
396};
397
398#define clk_src_regs(index, pllid)\
399[index] = {\
400 CS_COMMON_REG_LIST_DCN1_0(index, pllid),\
401}
402
403static const struct dce110_clk_src_regs clk_src_regs[] = {
404 clk_src_regs(0, A),
405 clk_src_regs(1, B),
406 clk_src_regs(2, C),
407 clk_src_regs(3, D)
408};
409
410static const struct dce110_clk_src_shift cs_shift = {
411 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
412};
413
414static const struct dce110_clk_src_mask cs_mask = {
415 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
416};
417
418
419static const struct resource_caps res_cap = {
420 .num_timing_generator = 4,
421 .num_video_plane = 4,
422 .num_audio = 4,
423 .num_stream_encoder = 4,
424 .num_pll = 4,
425};
426
427static const struct dc_debug debug_defaults_drv = {
428 .disable_dcc = false,
70ccab60
HW		 429 .disable_dmcu = true,
430 .force_abm_enable = false,
431 .timing_trace = false,
c9742685 432 .clock_trace = true,
70ccab60 433 .disable_pplib_clock_request = true,
d5c40d53 434 .disable_pplib_wm_range = false,
70ccab60
HW		 435#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
436 .use_dml_wm = false,
437 .use_max_voltage = true
438#endif
439};
440
441static const struct dc_debug debug_defaults_diags = {
70ccab60
HW		 442 .disable_dmcu = true,
443 .force_abm_enable = false,
444 .timing_trace = true,
c9742685 445 .clock_trace = true,
70ccab60
HW		 446#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
447 .disable_pplib_clock_request = true,
448 .disable_pplib_wm_range = true,
449 .use_dml_wm = false,
450 .use_max_voltage = false
451#endif
452};
453
454static void dcn10_transform_destroy(struct transform **xfm)
455{
456 dm_free(TO_DCN10_TRANSFORM(*xfm));
457 *xfm = NULL;
458}
459
460static struct transform *dcn10_transform_create(
461 struct dc_context *ctx,
462 uint32_t inst)
463{
464 struct dcn10_transform *transform =
465 dm_alloc(sizeof(struct dcn10_transform));
466
467 if (!transform)
468 return NULL;
469
470 if (dcn10_transform_construct(transform, ctx,
471 &tf_regs[inst], &tf_shift, &tf_mask))
472 return &transform->base;
473
474 BREAK_TO_DEBUGGER();
475 dm_free(transform);
476 return NULL;
477}
478
479static struct input_pixel_processor *dcn10_ipp_create(
480 struct dc_context *ctx, uint32_t inst)
481{
482 struct dcn10_ipp *ipp =
483 dm_alloc(sizeof(struct dcn10_ipp));
484
485 if (!ipp) {
486 BREAK_TO_DEBUGGER();
487 return NULL;
488 }
489
490 dcn10_ipp_construct(ipp, ctx, inst,
491 &ipp_regs[inst], &ipp_shift, &ipp_mask);
492 return &ipp->base;
493}
494
495
496static struct output_pixel_processor *dcn10_opp_create(
497 struct dc_context *ctx, uint32_t inst)
498{
499 struct dcn10_opp *opp =
500 dm_alloc(sizeof(struct dcn10_opp));
501
502 if (!opp) {
503 BREAK_TO_DEBUGGER();
504 return NULL;
505 }
506
507 dcn10_opp_construct(opp, ctx, inst,
508 &opp_regs[inst], &opp_shift, &opp_mask);
509 return &opp->base;
510}
511
512static struct mpc *dcn10_mpc_create(
513 struct dc_context *ctx)
514{
515 struct dcn10_mpc *mpc = dm_alloc(sizeof(struct dcn10_mpc));
516
517 if (!mpc)
518 return NULL;
519
520 mpc->base.ctx = ctx;
521 mpc->mpc_regs = &mpc_regs;
522 mpc->mpc_shift = &mpc_shift;
523 mpc->mpc_mask = &mpc_mask;
524
525 return &mpc->base;
526}
527
528static void dcn10_mpc_destroy(struct mpc **mpc_base)
529{
530 if (*mpc_base)
531 dm_free(TO_DCN10_MPC(*mpc_base));
532
533 *mpc_base = NULL;
534}
535
536static struct timing_generator *dcn10_timing_generator_create(
537 struct dc_context *ctx,
538 uint32_t instance)
539{
540 struct dcn10_timing_generator *tgn10 =
541 dm_alloc(sizeof(struct dcn10_timing_generator));
542
543 if (!tgn10)
544 return NULL;
545
546 tgn10->base.inst = instance;
547 tgn10->base.ctx = ctx;
548
549 tgn10->tg_regs = &tg_regs[instance];
550 tgn10->tg_shift = &tg_shift;
551 tgn10->tg_mask = &tg_mask;
552
553 dcn10_timing_generator_init(tgn10);
554
555 return &tgn10->base;
556}
557
558static const struct encoder_feature_support link_enc_feature = {
559 .max_hdmi_deep_color = COLOR_DEPTH_121212,
560 .max_hdmi_pixel_clock = 600000,
561 .ycbcr420_supported = true,
562 .flags.bits.IS_HBR2_CAPABLE = true,
563 .flags.bits.IS_HBR3_CAPABLE = true,
564 .flags.bits.IS_TPS3_CAPABLE = true,
565 .flags.bits.IS_TPS4_CAPABLE = true,
566 .flags.bits.IS_YCBCR_CAPABLE = true
567};
568
569struct link_encoder *dcn10_link_encoder_create(
570 const struct encoder_init_data *enc_init_data)
571{
572 struct dce110_link_encoder *enc110 =
573 dm_alloc(sizeof(struct dce110_link_encoder));
574
575 if (!enc110)
576 return NULL;
577
578 if (dce110_link_encoder_construct(
579 enc110,
580 enc_init_data,
581 &link_enc_feature,
582 &link_enc_regs[enc_init_data->transmitter],
583 &link_enc_aux_regs[enc_init_data->channel - 1],
584 &link_enc_hpd_regs[enc_init_data->hpd_source])) {
585
586 return &enc110->base;
587 }
588
589 BREAK_TO_DEBUGGER();
590 dm_free(enc110);
591 return NULL;
592}
593
594struct clock_source *dcn10_clock_source_create(
595 struct dc_context *ctx,
596 struct dc_bios *bios,
597 enum clock_source_id id,
598 const struct dce110_clk_src_regs *regs,
599 bool dp_clk_src)
600{
601 struct dce110_clk_src *clk_src =
602 dm_alloc(sizeof(struct dce110_clk_src));
603
604 if (!clk_src)
605 return NULL;
606
607 if (dce110_clk_src_construct(clk_src, ctx, bios, id,
608 regs, &cs_shift, &cs_mask)) {
609 clk_src->base.dp_clk_src = dp_clk_src;
610 return &clk_src->base;
611 }
612
613 BREAK_TO_DEBUGGER();
614 return NULL;
615}
616
617static void read_dce_straps(
618 struct dc_context *ctx,
619 struct resource_straps *straps)
620{
621 /* TODO: Registers are missing */
622 /*REG_GET_2(CC_DC_HDMI_STRAPS,
623 HDMI_DISABLE, &straps->hdmi_disable,
624 AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
625
626 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);*/
627}
628
629static struct audio *create_audio(
630 struct dc_context *ctx, unsigned int inst)
631{
632 return dce_audio_create(ctx, inst,
633 &audio_regs[inst], &audio_shift, &audio_mask);
634}
635
636static struct stream_encoder *dcn10_stream_encoder_create(
637 enum engine_id eng_id,
638 struct dc_context *ctx)
639{
640 struct dce110_stream_encoder *enc110 =
641 dm_alloc(sizeof(struct dce110_stream_encoder));
642
643 if (!enc110)
644 return NULL;
645
646 if (dce110_stream_encoder_construct(
647 enc110, ctx, ctx->dc_bios, eng_id,
648 &stream_enc_regs[eng_id], &se_shift, &se_mask))
649 return &enc110->base;
650
651 BREAK_TO_DEBUGGER();
652 dm_free(enc110);
653 return NULL;
654}
655
656static const struct dce_hwseq_registers hwseq_reg = {
657 HWSEQ_DCN1_REG_LIST()
658};
659
660static const struct dce_hwseq_shift hwseq_shift = {
661 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT)
662};
663
664static const struct dce_hwseq_mask hwseq_mask = {
665 HWSEQ_DCN1_MASK_SH_LIST(_MASK)
666};
667
668static struct dce_hwseq *dcn10_hwseq_create(
669 struct dc_context *ctx)
670{
671 struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq));
672
673 if (hws) {
674 hws->ctx = ctx;
675 hws->regs = &hwseq_reg;
676 hws->shifts = &hwseq_shift;
677 hws->masks = &hwseq_mask;
678 }
679 return hws;
680}
681
682static const struct resource_create_funcs res_create_funcs = {
683 .read_dce_straps = read_dce_straps,
684 .create_audio = create_audio,
685 .create_stream_encoder = dcn10_stream_encoder_create,
686 .create_hwseq = dcn10_hwseq_create,
687};
688
689static const struct resource_create_funcs res_create_maximus_funcs = {
690 .read_dce_straps = NULL,
691 .create_audio = NULL,
692 .create_stream_encoder = NULL,
693 .create_hwseq = dcn10_hwseq_create,
694};
695
696void dcn10_clock_source_destroy(struct clock_source **clk_src)
697{
698 dm_free(TO_DCE110_CLK_SRC(*clk_src));
699 *clk_src = NULL;
700}
701
702static void destruct(struct dcn10_resource_pool *pool)
703{
704 unsigned int i;
705
706 for (i = 0; i < pool->base.stream_enc_count; i++) {
707 if (pool->base.stream_enc[i] != NULL) {
708 /* TODO: free dcn version of stream encoder once implemented
709 * rather than using virtual stream encoder
710 */
711 dm_free(pool->base.stream_enc[i]);
712 pool->base.stream_enc[i] = NULL;
713 }
714 }
715
716 for (i = 0; i < pool->base.pipe_count; i++) {
717 if (pool->base.opps[i] != NULL)
718 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
719
720 if (pool->base.transforms[i] != NULL)
721 dcn10_transform_destroy(&pool->base.transforms[i]);
722
723 if (pool->base.ipps[i] != NULL)
724 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
725
726 if (pool->base.mis[i] != NULL) {
727 dm_free(TO_DCN10_MEM_INPUT(pool->base.mis[i]));
728 pool->base.mis[i] = NULL;
729 }
730
731 if (pool->base.irqs != NULL) {
732 dal_irq_service_destroy(&pool->base.irqs);
733 }
734
735 if (pool->base.timing_generators[i] != NULL) {
736 dm_free(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
737 pool->base.timing_generators[i] = NULL;
738 }
739 }
740
741 for (i = 0; i < pool->base.stream_enc_count; i++) {
742 if (pool->base.stream_enc[i] != NULL)
743 dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
744 }
745
746 for (i = 0; i < pool->base.audio_count; i++) {
747 if (pool->base.audios[i])
748 dce_aud_destroy(&pool->base.audios[i]);
749 }
750
751 for (i = 0; i < pool->base.clk_src_count; i++) {
752 if (pool->base.clock_sources[i] != NULL) {
753 dcn10_clock_source_destroy(&pool->base.clock_sources[i]);
754 pool->base.clock_sources[i] = NULL;
755 }
756 }
757
758 if (pool->base.dp_clock_source != NULL) {
759 dcn10_clock_source_destroy(&pool->base.dp_clock_source);
760 pool->base.dp_clock_source = NULL;
761 }
762
763 if (pool->base.mpc != NULL)
764 dcn10_mpc_destroy(&pool->base.mpc);
765
766 if (pool->base.abm != NULL)
767 dce_abm_destroy(&pool->base.abm);
768
769 if (pool->base.dmcu != NULL)
770 dce_dmcu_destroy(&pool->base.dmcu);
771
772 if (pool->base.display_clock != NULL)
773 dce_disp_clk_destroy(&pool->base.display_clock);
774}
775
776static struct mem_input *dcn10_mem_input_create(
777 struct dc_context *ctx,
778 uint32_t inst)
779{
780 struct dcn10_mem_input *mem_inputn10 =
781 dm_alloc(sizeof(struct dcn10_mem_input));
782
783 if (!mem_inputn10)
784 return NULL;
785
786 if (dcn10_mem_input_construct(mem_inputn10, ctx, inst,
787 &mi_regs[inst], &mi_shift, &mi_mask))
788 return &mem_inputn10->base;
789
790 BREAK_TO_DEBUGGER();
791 dm_free(mem_inputn10);
792 return NULL;
793}
794
795static void get_pixel_clock_parameters(
796 const struct pipe_ctx *pipe_ctx,
797 struct pixel_clk_params *pixel_clk_params)
798{
799 const struct core_stream *stream = pipe_ctx->stream;
800 pixel_clk_params->requested_pix_clk = stream->public.timing.pix_clk_khz;
801 pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
802 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
803 pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1;
804 /* TODO: un-hardcode*/
805 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
806 LINK_RATE_REF_FREQ_IN_KHZ;
807 pixel_clk_params->flags.ENABLE_SS = 0;
808 pixel_clk_params->color_depth =
809 stream->public.timing.display_color_depth;
810 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
811 pixel_clk_params->pixel_encoding = stream->public.timing.pixel_encoding;
812
813 if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
814 pixel_clk_params->color_depth = COLOR_DEPTH_888;
815
816 if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
817 pixel_clk_params->requested_pix_clk /= 2;
818
819 if (stream->public.timing. timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING ||
820 stream->public.timing. timing_3d_format == TIMING_3D_FORMAT_SW_FRAME_PACKING ||
821 stream->public.timing. timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA)
822 pixel_clk_params->requested_pix_clk *= 2;
823}
824
825static void build_clamping_params(struct core_stream *stream)
826{
827 stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
828 stream->clamping.c_depth = stream->public.timing.display_color_depth;
829 stream->clamping.pixel_encoding = stream->public.timing.pixel_encoding;
830}
831
832static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
833{
834
835 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->pix_clk_params);
836
837 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
838 pipe_ctx->clock_source,
839 &pipe_ctx->pix_clk_params,
840 &pipe_ctx->pll_settings);
841
842 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->public.timing.pixel_encoding;
843
844 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
845 &pipe_ctx->stream->bit_depth_params);
846 build_clamping_params(pipe_ctx->stream);
847
848 return DC_OK;
849}
850
851static enum dc_status validate_mapped_resource(
852 const struct core_dc *dc,
430ef426
DL		 853 struct validate_context *context,
854 struct validate_context *old_context)
70ccab60
HW		 855{
856 enum dc_status status = DC_OK;
857 uint8_t i, j;
858
859 for (i = 0; i < context->stream_count; i++) {
860 struct core_stream *stream = context->streams[i];
861 struct core_link *link = stream->sink->link;
862
430ef426
DL		 863 if (old_context && resource_is_stream_unchanged(old_context, stream)) {
864 if (stream != NULL && old_context->streams[i] != NULL) {
70ccab60
HW		 865 /* todo: shouldn't have to copy missing parameter here */
866 resource_build_bit_depth_reduction_params(stream,
867 &stream->bit_depth_params);
868 stream->clamping.pixel_encoding =
869 stream->public.timing.pixel_encoding;
870
871 resource_build_bit_depth_reduction_params(stream,
872 &stream->bit_depth_params);
873 build_clamping_params(stream);
874
875 continue;
876 }
877 }
878
879 for (j = 0; j < dc->res_pool->pipe_count ; j++) {
880 struct pipe_ctx *pipe_ctx =
881 &context->res_ctx.pipe_ctx[j];
882
883 if (context->res_ctx.pipe_ctx[j].stream != stream)
884 continue;
885
886
887 if (!pipe_ctx->tg->funcs->validate_timing(
888 pipe_ctx->tg, &stream->public.timing))
889 return DC_FAIL_CONTROLLER_VALIDATE;
890
891 status = build_pipe_hw_param(pipe_ctx);
892
893 if (status != DC_OK)
894 return status;
895
896 if (!link->link_enc->funcs->validate_output_with_stream(
897 link->link_enc, pipe_ctx))
898 return DC_FAIL_ENC_VALIDATE;
899
900 /* TODO: validate audio ASIC caps, encoder */
901
902 status = dc_link_validate_mode_timing(
903 stream, link, &stream->public.timing);
904
905 if (status != DC_OK)
906 return status;
907
908
909 /* do not need to validate non root pipes */
910 break;
911 }
912 }
913
914 return DC_OK;
915}
916
917enum dc_status dcn10_validate_with_context(
918 const struct core_dc *dc,
919 const struct dc_validation_set set[],
920 int set_count,
430ef426
DL		 921 struct validate_context *context,
922 struct validate_context *old_context)
70ccab60
HW		 923{
924 enum dc_status result = DC_OK;
925 int i;
926
927 if (set_count == 0)
928 return result;
929
930 for (i = 0; i < set_count; i++) {
931 context->streams[i] = DC_STREAM_TO_CORE(set[i].stream);
932 dc_stream_retain(&context->streams[i]->public);
933 context->stream_count++;
934 }
935
430ef426 936 result = resource_map_pool_resources(dc, context, old_context);
70ccab60
HW		 937 if (result != DC_OK)
938 return result;
939
430ef426 940 result = resource_map_phy_clock_resources(dc, context, old_context);
70ccab60
HW		 941 if (result != DC_OK)
942 return result;
943
430ef426 944 result = validate_mapped_resource(dc, context, old_context);
70ccab60
HW		 945 if (result != DC_OK)
946 return result;
947
948 if (!resource_validate_attach_surfaces(set, set_count,
430ef426 949 old_context, context, dc->res_pool))
70ccab60
HW		 950 return DC_FAIL_ATTACH_SURFACES;
951
952 result = resource_build_scaling_params_for_context(dc, context);
953 if (result != DC_OK)
954 return result;
955
956 if (!dcn_validate_bandwidth(dc, context))
957 return DC_FAIL_BANDWIDTH_VALIDATE;
958
959 return result;
960}
961
962enum dc_status dcn10_validate_guaranteed(
963 const struct core_dc *dc,
964 const struct dc_stream *dc_stream,
965 struct validate_context *context)
966{
967 enum dc_status result = DC_ERROR_UNEXPECTED;
968
969 context->streams[0] = DC_STREAM_TO_CORE(dc_stream);
970 dc_stream_retain(&context->streams[0]->public);
971 context->stream_count++;
972
430ef426 973 result = resource_map_pool_resources(dc, context, NULL);
70ccab60
HW		 974
975 if (result == DC_OK)
430ef426 976 result = resource_map_phy_clock_resources(dc, context, NULL);
70ccab60
HW		 977
978 if (result == DC_OK)
430ef426 979 result = validate_mapped_resource(dc, context, NULL);
70ccab60
HW		 980
981 if (result == DC_OK) {
982 validate_guaranteed_copy_streams(
983 context, dc->public.caps.max_streams);
984 result = resource_build_scaling_params_for_context(dc, context);
985 }
986 if (result == DC_OK && !dcn_validate_bandwidth(dc, context))
987 return DC_FAIL_BANDWIDTH_VALIDATE;
988
989 return result;
990}
991
992static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(
993 struct validate_context *context,
994 const struct resource_pool *pool,
995 struct core_stream *stream)
996{
997 struct resource_context *res_ctx = &context->res_ctx;
998 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
999 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool);
1000
1001 if (!head_pipe)
1002 ASSERT(0);
1003
1004 if (!idle_pipe)
1005 return false;
1006
1007 idle_pipe->stream = head_pipe->stream;
1008 idle_pipe->tg = head_pipe->tg;
1009
1010 idle_pipe->mi = pool->mis[idle_pipe->pipe_idx];
1011 idle_pipe->ipp = pool->ipps[idle_pipe->pipe_idx];
1012 idle_pipe->xfm = pool->transforms[idle_pipe->pipe_idx];
1013 idle_pipe->opp = pool->opps[idle_pipe->pipe_idx];
1014
1015 return idle_pipe;
1016}
1017
1018enum dcc_control {
1019 dcc_control__256_256_xxx,
1020 dcc_control__128_128_xxx,
1021 dcc_control__256_64_64,
1022};
1023
1024enum segment_order {
1025 segment_order__na,
1026 segment_order__contiguous,
1027 segment_order__non_contiguous,
1028};
1029
1030static bool dcc_support_pixel_format(
1031 enum surface_pixel_format format,
1032 unsigned int *bytes_per_element)
1033{
1034 /* DML: get_bytes_per_element */
1035 switch (format) {
1036 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
1037 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
1038 *bytes_per_element = 2;
1039 return true;
1040 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
1041 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
1042 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
1043 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
1044 *bytes_per_element = 4;
1045 return true;
1046 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1047 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1048 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1049 *bytes_per_element = 8;
1050 return true;
1051 default:
1052 return false;
1053 }
1054}
1055
1056static bool dcc_support_swizzle(
1057 enum swizzle_mode_values swizzle,
1058 unsigned int bytes_per_element,
1059 enum segment_order *segment_order_horz,
1060 enum segment_order *segment_order_vert)
1061{
1062 bool standard_swizzle = false;
1063 bool display_swizzle = false;
1064
1065 switch (swizzle) {
1066 case DC_SW_4KB_S:
1067 case DC_SW_64KB_S:
1068 case DC_SW_VAR_S:
1069 case DC_SW_4KB_S_X:
1070 case DC_SW_64KB_S_X:
1071 case DC_SW_VAR_S_X:
1072 standard_swizzle = true;
1073 break;
1074 case DC_SW_4KB_D:
1075 case DC_SW_64KB_D:
1076 case DC_SW_VAR_D:
1077 case DC_SW_4KB_D_X:
1078 case DC_SW_64KB_D_X:
1079 case DC_SW_VAR_D_X:
1080 display_swizzle = true;
1081 break;
1082 default:
1083 break;
2801b0a8 1084 }
70ccab60
HW		 1085
1086 if (bytes_per_element == 1 && standard_swizzle) {
1087 *segment_order_horz = segment_order__contiguous;
1088 *segment_order_vert = segment_order__na;
1089 return true;
1090 }
1091 if (bytes_per_element == 2 && standard_swizzle) {
1092 *segment_order_horz = segment_order__non_contiguous;
1093 *segment_order_vert = segment_order__contiguous;
1094 return true;
1095 }
1096 if (bytes_per_element == 4 && standard_swizzle) {
1097 *segment_order_horz = segment_order__non_contiguous;
1098 *segment_order_vert = segment_order__contiguous;
1099 return true;
1100 }
1101 if (bytes_per_element == 8 && standard_swizzle) {
1102 *segment_order_horz = segment_order__na;
1103 *segment_order_vert = segment_order__contiguous;
1104 return true;
1105 }
1106 if (bytes_per_element == 8 && display_swizzle) {
1107 *segment_order_horz = segment_order__contiguous;
1108 *segment_order_vert = segment_order__non_contiguous;
1109 return true;
1110 }
1111
1112 return false;
1113}
1114
1115static void get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height,
1116 unsigned int bytes_per_element)
1117{
1118 /* copied from DML. might want to refactor DML to leverage from DML */
1119 /* DML : get_blk256_size */
1120 if (bytes_per_element == 1) {
1121 *blk256_width = 16;
1122 *blk256_height = 16;
1123 } else if (bytes_per_element == 2) {
1124 *blk256_width = 16;
1125 *blk256_height = 8;
1126 } else if (bytes_per_element == 4) {
1127 *blk256_width = 8;
1128 *blk256_height = 8;
1129 } else if (bytes_per_element == 8) {
1130 *blk256_width = 8;
1131 *blk256_height = 4;
1132 }
1133}
1134
1135static void det_request_size(
1136 unsigned int height,
1137 unsigned int width,
1138 unsigned int bpe,
1139 bool *req128_horz_wc,
1140 bool *req128_vert_wc)
1141{
1142 unsigned int detile_buf_size = 164 * 1024; /* 164KB for DCN1.0 */
1143
1144 unsigned int blk256_height = 0;
1145 unsigned int blk256_width = 0;
1146 unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc;
1147
1148 get_blk256_size(&blk256_width, &blk256_height, bpe);
1149
1150 swath_bytes_horz_wc = height * blk256_height * bpe;
1151 swath_bytes_vert_wc = width * blk256_width * bpe;
1152
1153 *req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ?
1154 false : /* full 256B request */
1155 true; /* half 128b request */
1156
1157 *req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ?
1158 false : /* full 256B request */
1159 true; /* half 128b request */
1160}
1161
1162static bool get_dcc_compression_cap(const struct dc *dc,
1163 const struct dc_dcc_surface_param *input,
1164 struct dc_surface_dcc_cap *output)
1165{
1166 /* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */
1167 enum dcc_control dcc_control;
1168 unsigned int bpe;
1169 enum segment_order segment_order_horz, segment_order_vert;
1170 bool req128_horz_wc, req128_vert_wc;
1171
1172 memset(output, 0, sizeof(*output));
1173
1174 if (dc->debug.disable_dcc)
1175 return false;
1176
1177 if (!dcc_support_pixel_format(input->format,
1178 &bpe))
1179 return false;
1180
1181 if (!dcc_support_swizzle(input->swizzle_mode, bpe,
1182 &segment_order_horz, &segment_order_vert))
1183 return false;
1184
1185 det_request_size(input->surface_size.height, input->surface_size.width,
1186 bpe, &req128_horz_wc, &req128_vert_wc);
1187
1188 if (!req128_horz_wc && !req128_vert_wc) {
1189 dcc_control = dcc_control__256_256_xxx;
1190 } else if (input->scan == SCAN_DIRECTION_HORIZONTAL) {
1191 if (!req128_horz_wc)
1192 dcc_control = dcc_control__256_256_xxx;
1193 else if (segment_order_horz == segment_order__contiguous)
1194 dcc_control = dcc_control__128_128_xxx;
1195 else
1196 dcc_control = dcc_control__256_64_64;
1197 } else if (input->scan == SCAN_DIRECTION_VERTICAL) {
1198 if (!req128_vert_wc)
1199 dcc_control = dcc_control__256_256_xxx;
1200 else if (segment_order_vert == segment_order__contiguous)
1201 dcc_control = dcc_control__128_128_xxx;
1202 else
1203 dcc_control = dcc_control__256_64_64;
1204 } else {
1205 if ((req128_horz_wc &&
1206 segment_order_horz == segment_order__non_contiguous) ||
1207 (req128_vert_wc &&
1208 segment_order_vert == segment_order__non_contiguous))
1209 /* access_dir not known, must use most constraining */
1210 dcc_control = dcc_control__256_64_64;
1211 else
1212 /* reg128 is true for either horz and vert
1213 * but segment_order is contiguous
1214 */
1215 dcc_control = dcc_control__128_128_xxx;
1216 }
1217
1218 switch (dcc_control) {
1219 case dcc_control__256_256_xxx:
1220 output->grph.rgb.max_uncompressed_blk_size = 256;
1221 output->grph.rgb.max_compressed_blk_size = 256;
1222 output->grph.rgb.independent_64b_blks = false;
1223 break;
1224 case dcc_control__128_128_xxx:
1225 output->grph.rgb.max_uncompressed_blk_size = 128;
1226 output->grph.rgb.max_compressed_blk_size = 128;
1227 output->grph.rgb.independent_64b_blks = false;
1228 break;
1229 case dcc_control__256_64_64:
1230 output->grph.rgb.max_uncompressed_blk_size = 256;
1231 output->grph.rgb.max_compressed_blk_size = 64;
1232 output->grph.rgb.independent_64b_blks = true;
1233 break;
1234 }
1235 output->capable = true;
1236 output->const_color_support = false;
1237
1238 return true;
1239}
1240
1241
1242static void dcn10_destroy_resource_pool(struct resource_pool **pool)
1243{
1244 struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool);
1245
1246 destruct(dcn10_pool);
1247 dm_free(dcn10_pool);
1248 *pool = NULL;
1249}
1250
1251
1252static struct dc_cap_funcs cap_funcs = {
1253 .get_dcc_compression_cap = get_dcc_compression_cap
1254};
1255
1256static struct resource_funcs dcn10_res_pool_funcs = {
1257 .destroy = dcn10_destroy_resource_pool,
1258 .link_enc_create = dcn10_link_encoder_create,
1259 .validate_with_context = dcn10_validate_with_context,
1260 .validate_guaranteed = dcn10_validate_guaranteed,
1261 .validate_bandwidth = dcn_validate_bandwidth,
1262 .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer,
1263};
1264
1265static bool construct(
1266 uint8_t num_virtual_links,
1267 struct core_dc *dc,
1268 struct dcn10_resource_pool *pool)
1269{
1270 int i;
1271 struct dc_context *ctx = dc->ctx;
1272
1273 ctx->dc_bios->regs = &bios_regs;
1274
1275 pool->base.res_cap = &res_cap;
1276 pool->base.funcs = &dcn10_res_pool_funcs;
1277
1278 /*
1279 * TODO fill in from actual raven resource when we create
1280 * more than virtual encoder
1281 */
1282
1283 /*************************************************
1284 * Resource + asic cap harcoding *
1285 *************************************************/
1286 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1287
1288 /* TODO: Hardcode to correct number of functional controllers */
1289 pool->base.pipe_count = 4;
1290 dc->public.caps.max_downscale_ratio = 200;
1291 dc->public.caps.i2c_speed_in_khz = 100;
1292 dc->public.caps.max_cursor_size = 256;
1293
a90fbf78
LE		 1294 dc->public.caps.max_slave_planes = 1;
1295
70ccab60
HW		 1296 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1297 dc->public.debug = debug_defaults_drv;
1298 else
1299 dc->public.debug = debug_defaults_diags;
1300
1301 /*************************************************
1302 * Create resources *
1303 *************************************************/
1304
1305 pool->base.clock_sources[DCN10_CLK_SRC_PLL0] =
1306 dcn10_clock_source_create(ctx, ctx->dc_bios,
1307 CLOCK_SOURCE_COMBO_PHY_PLL0,
1308 &clk_src_regs[0], false);
1309 pool->base.clock_sources[DCN10_CLK_SRC_PLL1] =
1310 dcn10_clock_source_create(ctx, ctx->dc_bios,
1311 CLOCK_SOURCE_COMBO_PHY_PLL1,
1312 &clk_src_regs[1], false);
1313 pool->base.clock_sources[DCN10_CLK_SRC_PLL2] =
1314 dcn10_clock_source_create(ctx, ctx->dc_bios,
1315 CLOCK_SOURCE_COMBO_PHY_PLL2,
1316 &clk_src_regs[2], false);
1317 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
1318 dcn10_clock_source_create(ctx, ctx->dc_bios,
1319 CLOCK_SOURCE_COMBO_PHY_PLL3,
1320 &clk_src_regs[3], false);
1321
1322 pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
1323
1324 pool->base.dp_clock_source =
1325 dcn10_clock_source_create(ctx, ctx->dc_bios,
1326 CLOCK_SOURCE_ID_DP_DTO,
1327 /* todo: not reuse phy_pll registers */
1328 &clk_src_regs[0], true);
1329
1330 for (i = 0; i < pool->base.clk_src_count; i++) {
1331 if (pool->base.clock_sources[i] == NULL) {
1332 dm_error("DC: failed to create clock sources!\n");
1333 BREAK_TO_DEBUGGER();
1334 goto clock_source_create_fail;
1335 }
1336 }
1337
1338 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1339 pool->base.display_clock = dce120_disp_clk_create(ctx,
1340 &disp_clk_regs,
1341 &disp_clk_shift,
1342 &disp_clk_mask);
1343 if (pool->base.display_clock == NULL) {
1344 dm_error("DC: failed to create display clock!\n");
1345 BREAK_TO_DEBUGGER();
1346 goto disp_clk_create_fail;
1347 }
1348 }
1349
1350 pool->base.dmcu = dcn10_dmcu_create(ctx,
1351 &dmcu_regs,
1352 &dmcu_shift,
1353 &dmcu_mask);
1354 if (pool->base.dmcu == NULL) {
1355 dm_error("DC: failed to create dmcu!\n");
1356 BREAK_TO_DEBUGGER();
1357 goto res_create_fail;
1358 }
1359
1360 pool->base.abm = dce_abm_create(ctx,
1361 &abm_regs,
1362 &abm_shift,
1363 &abm_mask);
1364 if (pool->base.abm == NULL) {
1365 dm_error("DC: failed to create abm!\n");
1366 BREAK_TO_DEBUGGER();
1367 goto res_create_fail;
1368 }
1369
1370 dml_init_instance(&dc->dml, DML_PROJECT_RAVEN1);
1371 dc->dcn_ip = dcn10_ip_defaults;
1372 dc->dcn_soc = dcn10_soc_defaults;
1373 if (!dc->public.debug.disable_pplib_clock_request)
1374 dcn_bw_update_from_pplib(dc);
1375 dcn_bw_sync_calcs_and_dml(dc);
1376 if (!dc->public.debug.disable_pplib_wm_range)
1377 dcn_bw_notify_pplib_of_wm_ranges(dc);
1378
1379 {
1380 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1381 struct irq_service_init_data init_data;
1382 init_data.ctx = dc->ctx;
1383 pool->base.irqs = dal_irq_service_dcn10_create(&init_data);
1384 if (!pool->base.irqs)
1385 goto irqs_create_fail;
1386 #endif
1387 }
1388
1389 /* mem input -> ipp -> transform -> opp -> TG */
1390 for (i = 0; i < pool->base.pipe_count; i++) {
1391 pool->base.mis[i] = dcn10_mem_input_create(ctx, i);
1392 if (pool->base.mis[i] == NULL) {
1393 BREAK_TO_DEBUGGER();
1394 dm_error(
1395 "DC: failed to create memory input!\n");
1396 goto mi_create_fail;
1397 }
1398
1399 pool->base.ipps[i] = dcn10_ipp_create(ctx, i);
1400 if (pool->base.ipps[i] == NULL) {
1401 BREAK_TO_DEBUGGER();
1402 dm_error(
1403 "DC: failed to create input pixel processor!\n");
1404 goto ipp_create_fail;
1405 }
1406
1407 pool->base.transforms[i] = dcn10_transform_create(ctx, i);
1408 if (pool->base.transforms[i] == NULL) {
1409 BREAK_TO_DEBUGGER();
1410 dm_error(
1411 "DC: failed to create transform!\n");
1412 goto transform_create_fail;
1413 }
1414
1415 pool->base.opps[i] = dcn10_opp_create(ctx, i);
1416 if (pool->base.opps[i] == NULL) {
1417 BREAK_TO_DEBUGGER();
1418 dm_error(
1419 "DC: failed to create output pixel processor!\n");
1420 goto opp_create_fail;
1421 }
1422
1423 pool->base.timing_generators[i] = dcn10_timing_generator_create(
1424 ctx, i);
1425 if (pool->base.timing_generators[i] == NULL) {
1426 BREAK_TO_DEBUGGER();
1427 dm_error("DC: failed to create tg!\n");
1428 goto otg_create_fail;
1429 }
1430 }
1431
1432 pool->base.mpc = dcn10_mpc_create(ctx);
1433
1434 if (!resource_construct(num_virtual_links, dc, &pool->base,
1435 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1436 &res_create_funcs : &res_create_maximus_funcs)))
1437 goto res_create_fail;
1438
1439 dcn10_hw_sequencer_construct(dc);
1440 dc->public.caps.max_surfaces = pool->base.pipe_count;
1441
1442 dc->public.cap_funcs = cap_funcs;
1443
1444 return true;
1445
1446disp_clk_create_fail:
1447otg_create_fail:
1448opp_create_fail:
1449transform_create_fail:
1450ipp_create_fail:
1451mi_create_fail:
1452irqs_create_fail:
1453res_create_fail:
1454clock_source_create_fail:
1455
1456 destruct(pool);
1457
1458 return false;
1459}
1460
1461struct resource_pool *dcn10_create_resource_pool(
1462 uint8_t num_virtual_links,
1463 struct core_dc *dc)
1464{
1465 struct dcn10_resource_pool *pool =
1466 dm_alloc(sizeof(struct dcn10_resource_pool));
1467
1468 if (!pool)
1469 return NULL;
1470
1471 if (construct(num_virtual_links, dc, pool))
1472 return &pool->base;
1473
1474 BREAK_TO_DEBUGGER();
1475 return NULL;
1476}
Linux 6.x block layer and io_uring tree(s)