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drm/amd/display: Add DCN3 DIO
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / dc / dcn10 / dcn10_link_encoder.h
CommitLineData
f0cd0a34
EB		 1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DC_LINK_ENCODER__DCN10_H__
27#define __DC_LINK_ENCODER__DCN10_H__
28
29#include "link_encoder.h"
30
31#define TO_DCN10_LINK_ENC(link_encoder)\
32 container_of(link_encoder, struct dcn10_link_encoder, base)
33
34
35#define AUX_REG_LIST(id)\
36 SRI(AUX_CONTROL, DP_AUX, id), \
37 SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id)
38
39#define HPD_REG_LIST(id)\
40 SRI(DC_HPD_CONTROL, HPD, id)
41
42#define LE_DCN_COMMON_REG_LIST(id) \
43 SRI(DIG_BE_CNTL, DIG, id), \
44 SRI(DIG_BE_EN_CNTL, DIG, id), \
8e8539c2 45 SRI(TMDS_CTL_BITS, DIG, id), \
f0cd0a34
EB		 46 SRI(DP_CONFIG, DP, id), \
47 SRI(DP_DPHY_CNTL, DP, id), \
48 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
49 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
50 SRI(DP_DPHY_SYM0, DP, id), \
51 SRI(DP_DPHY_SYM1, DP, id), \
52 SRI(DP_DPHY_SYM2, DP, id), \
53 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
54 SRI(DP_LINK_CNTL, DP, id), \
55 SRI(DP_LINK_FRAMING_CNTL, DP, id), \
56 SRI(DP_MSE_SAT0, DP, id), \
57 SRI(DP_MSE_SAT1, DP, id), \
58 SRI(DP_MSE_SAT2, DP, id), \
59 SRI(DP_MSE_SAT_UPDATE, DP, id), \
60 SRI(DP_SEC_CNTL, DP, id), \
61 SRI(DP_VID_STREAM_CNTL, DP, id), \
62 SRI(DP_DPHY_FAST_TRAINING, DP, id), \
63 SRI(DP_SEC_CNTL1, DP, id), \
64 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
f0cd0a34
EB		 65 SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
66
8e8539c2 67
f0cd0a34 68#define LE_DCN10_REG_LIST(id)\
18952c8e 69 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
f0cd0a34
EB		 70 LE_DCN_COMMON_REG_LIST(id)
71
72struct dcn10_link_enc_aux_registers {
73 uint32_t AUX_CONTROL;
74 uint32_t AUX_DPHY_RX_CONTROL0;
ca4d9b3a 75 uint32_t AUX_DPHY_TX_CONTROL;
f0cd0a34
EB		 76};
77
78struct dcn10_link_enc_hpd_registers {
79 uint32_t DC_HPD_CONTROL;
80};
81
82struct dcn10_link_enc_registers {
83 uint32_t DIG_BE_CNTL;
84 uint32_t DIG_BE_EN_CNTL;
85 uint32_t DP_CONFIG;
86 uint32_t DP_DPHY_CNTL;
87 uint32_t DP_DPHY_INTERNAL_CTRL;
88 uint32_t DP_DPHY_PRBS_CNTL;
89 uint32_t DP_DPHY_SCRAM_CNTL;
90 uint32_t DP_DPHY_SYM0;
91 uint32_t DP_DPHY_SYM1;
92 uint32_t DP_DPHY_SYM2;
93 uint32_t DP_DPHY_TRAINING_PATTERN_SEL;
94 uint32_t DP_LINK_CNTL;
95 uint32_t DP_LINK_FRAMING_CNTL;
96 uint32_t DP_MSE_SAT0;
97 uint32_t DP_MSE_SAT1;
98 uint32_t DP_MSE_SAT2;
99 uint32_t DP_MSE_SAT_UPDATE;
100 uint32_t DP_SEC_CNTL;
101 uint32_t DP_VID_STREAM_CNTL;
102 uint32_t DP_DPHY_FAST_TRAINING;
103 uint32_t DP_DPHY_BS_SR_SWAP_CNTL;
104 uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;
105 uint32_t DP_SEC_CNTL1;
8e8539c2 106 uint32_t TMDS_CTL_BITS;
ca4d9b3a
HW		 107 /* DCCG */
108 uint32_t CLOCK_ENABLE;
109 /* DIG */
110 uint32_t DIG_LANE_ENABLE;
111 /* UNIPHY */
112 uint32_t CHANNEL_XBAR_CNTL;
c7e06b0d
BL		 113 /* DPCS */
114 uint32_t RDPCSTX_PHY_CNTL3;
115 uint32_t RDPCSTX_PHY_CNTL4;
116 uint32_t RDPCSTX_PHY_CNTL5;
117 uint32_t RDPCSTX_PHY_CNTL6;
118 uint32_t RDPCSTX_PHY_CNTL7;
119 uint32_t RDPCSTX_PHY_CNTL8;
120 uint32_t RDPCSTX_PHY_CNTL9;
121 uint32_t RDPCSTX_PHY_CNTL10;
122 uint32_t RDPCSTX_PHY_CNTL11;
123 uint32_t RDPCSTX_PHY_CNTL12;
124 uint32_t RDPCSTX_PHY_CNTL13;
125 uint32_t RDPCSTX_PHY_CNTL14;
126 uint32_t RDPCSTX_PHY_CNTL15;
a771ded8
RL		 127 uint32_t RDPCSTX_CNTL;
128 uint32_t RDPCSTX_CLOCK_CNTL;
129 uint32_t RDPCSTX_PHY_CNTL0;
130 uint32_t RDPCSTX_PHY_CNTL2;
131 uint32_t RDPCSTX_PLL_UPDATE_DATA;
132 uint32_t RDPCS_TX_CR_ADDR;
133 uint32_t RDPCS_TX_CR_DATA;
134 uint32_t DPCSTX_TX_CLOCK_CNTL;
135 uint32_t DPCSTX_TX_CNTL;
136 uint32_t RDPCSTX_INTERRUPT_CONTROL;
137 uint32_t RDPCSTX_PHY_FUSE0;
138 uint32_t RDPCSTX_PHY_FUSE1;
139 uint32_t RDPCSTX_PHY_FUSE2;
140 uint32_t RDPCSTX_PHY_FUSE3;
141 uint32_t RDPCSTX_PHY_RX_LD_VAL;
142 uint32_t DPCSTX_DEBUG_CONFIG;
143 uint32_t RDPCSTX_DEBUG_CONFIG;
144 uint32_t RDPCSTX0_RDPCSTX_SCRATCH;
145 uint32_t RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG;
146 uint32_t DCIO_SOFT_RESET;
ca4d9b3a
HW		 147 /* indirect registers */
148 uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2;
149 uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3;
150 uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2;
151 uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3;
152 uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2;
153 uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3;
154 uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2;
155 uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3;
be547111
BL		 156#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
157 uint32_t TMDS_DCBALANCER_CONTROL;
158 uint32_t PHYA_LINK_CNTL2;
159 uint32_t PHYB_LINK_CNTL2;
160 uint32_t PHYC_LINK_CNTL2;
161#endif
f0cd0a34
EB		 162};
163
164#define LE_SF(reg_name, field_name, post_fix)\
165 .field_name = reg_name ## __ ## field_name ## post_fix
166
167#define LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh)\
168 LE_SF(DIG0_DIG_BE_EN_CNTL, DIG_ENABLE, mask_sh),\
169 LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\
170 LE_SF(DIG0_DIG_BE_CNTL, DIG_MODE, mask_sh),\
171 LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\
8e8539c2 172 LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
f0cd0a34
EB		 173 LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\
174 LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\
175 LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE1, mask_sh),\
176 LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE2, mask_sh),\
177 LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE3, mask_sh),\
178 LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, mask_sh),\
179 LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL, mask_sh),\
180 LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\
181 LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\
182 LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\
183 LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\
184 LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\
185 LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\
186 LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\
187 LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\
188 LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, mask_sh),\
189 LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, mask_sh),\
190 LE_SF(DP0_DP_DPHY_FAST_TRAINING, DPHY_RX_FAST_TRAINING_CAPABLE, mask_sh),\
191 LE_SF(DP0_DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, mask_sh),\
192 LE_SF(DP0_DP_DPHY_TRAINING_PATTERN_SEL, DPHY_TRAINING_PATTERN_SEL, mask_sh),\
193 LE_SF(DP0_DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL, mask_sh),\
194 LE_SF(DP0_DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, mask_sh),\
195 LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL, mask_sh),\
196 LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VBID_DISABLE, mask_sh),\
197 LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VID_ENHANCED_FRAME_MODE, mask_sh),\
198 LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
199 LE_SF(DP0_DP_CONFIG, DP_UDI_LANES, mask_sh),\
200 LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_LINE_NUM, mask_sh),\
201 LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_PRIORITY, mask_sh),\
202 LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC0, mask_sh),\
203 LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC1, mask_sh),\
204 LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT0, mask_sh),\
205 LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT1, mask_sh),\
206 LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC2, mask_sh),\
207 LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC3, mask_sh),\
208 LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT2, mask_sh),\
209 LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT3, mask_sh),\
210 LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\
211 LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_16_MTP_KEEPOUT, mask_sh),\
212 LE_SF(DP_AUX0_AUX_CONTROL, AUX_HPD_SEL, mask_sh),\
213 LE_SF(DP_AUX0_AUX_CONTROL, AUX_LS_READ_EN, mask_sh),\
214 LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW, mask_sh),\
215 LE_SF(HPD0_DC_HPD_CONTROL, DC_HPD_EN, mask_sh)
216
217#define DCN_LINK_ENCODER_REG_FIELD_LIST(type) \
218 type DIG_ENABLE;\
219 type DIG_HPD_SELECT;\
220 type DIG_MODE;\
221 type DIG_FE_SOURCE_SELECT;\
222 type DPHY_BYPASS;\
223 type DPHY_ATEST_SEL_LANE0;\
224 type DPHY_ATEST_SEL_LANE1;\
225 type DPHY_ATEST_SEL_LANE2;\
226 type DPHY_ATEST_SEL_LANE3;\
227 type DPHY_PRBS_EN;\
228 type DPHY_PRBS_SEL;\
229 type DPHY_SYM1;\
230 type DPHY_SYM2;\
231 type DPHY_SYM3;\
232 type DPHY_SYM4;\
233 type DPHY_SYM5;\
234 type DPHY_SYM6;\
235 type DPHY_SYM7;\
236 type DPHY_SYM8;\
237 type DPHY_SCRAMBLER_BS_COUNT;\
238 type DPHY_SCRAMBLER_ADVANCE;\
239 type DPHY_RX_FAST_TRAINING_CAPABLE;\
240 type DPHY_LOAD_BS_COUNT;\
241 type DPHY_TRAINING_PATTERN_SEL;\
242 type DP_DPHY_HBR2_PATTERN_CONTROL;\
243 type DP_LINK_TRAINING_COMPLETE;\
244 type DP_IDLE_BS_INTERVAL;\
245 type DP_VBID_DISABLE;\
246 type DP_VID_ENHANCED_FRAME_MODE;\
247 type DP_VID_STREAM_ENABLE;\
248 type DP_UDI_LANES;\
249 type DP_SEC_GSP0_LINE_NUM;\
250 type DP_SEC_GSP0_PRIORITY;\
251 type DP_MSE_SAT_SRC0;\
252 type DP_MSE_SAT_SRC1;\
253 type DP_MSE_SAT_SRC2;\
254 type DP_MSE_SAT_SRC3;\
255 type DP_MSE_SAT_SLOT_COUNT0;\
256 type DP_MSE_SAT_SLOT_COUNT1;\
257 type DP_MSE_SAT_SLOT_COUNT2;\
258 type DP_MSE_SAT_SLOT_COUNT3;\
259 type DP_MSE_SAT_UPDATE;\
260 type DP_MSE_16_MTP_KEEPOUT;\
8e8539c2
CL		 261 type DC_HPD_EN;\
262 type TMDS_CTL0;\
f0cd0a34
EB		 263 type AUX_HPD_SEL;\
264 type AUX_LS_READ_EN;\
8e8539c2 265 type AUX_RX_RECEIVE_WINDOW
f0cd0a34 266
ca4d9b3a
HW		 267
268#define DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type) \
269 type RDPCS_PHY_DP_TX0_DATA_EN;\
270 type RDPCS_PHY_DP_TX1_DATA_EN;\
271 type RDPCS_PHY_DP_TX2_DATA_EN;\
272 type RDPCS_PHY_DP_TX3_DATA_EN;\
273 type RDPCS_PHY_DP_TX0_PSTATE;\
274 type RDPCS_PHY_DP_TX1_PSTATE;\
275 type RDPCS_PHY_DP_TX2_PSTATE;\
276 type RDPCS_PHY_DP_TX3_PSTATE;\
277 type RDPCS_PHY_DP_TX0_MPLL_EN;\
278 type RDPCS_PHY_DP_TX1_MPLL_EN;\
279 type RDPCS_PHY_DP_TX2_MPLL_EN;\
280 type RDPCS_PHY_DP_TX3_MPLL_EN;\
281 type RDPCS_TX_FIFO_LANE0_EN;\
282 type RDPCS_TX_FIFO_LANE1_EN;\
283 type RDPCS_TX_FIFO_LANE2_EN;\
284 type RDPCS_TX_FIFO_LANE3_EN;\
285 type RDPCS_EXT_REFCLK_EN;\
286 type RDPCS_TX_FIFO_EN;\
287 type UNIPHY_LINK_ENABLE;\
91c665bd
BL		 288 type UNIPHY_CHANNEL0_XBAR_SOURCE;\
289 type UNIPHY_CHANNEL1_XBAR_SOURCE;\
290 type UNIPHY_CHANNEL2_XBAR_SOURCE;\
291 type UNIPHY_CHANNEL3_XBAR_SOURCE;\
ca4d9b3a
HW		 292 type UNIPHY_CHANNEL0_INVERT;\
293 type UNIPHY_CHANNEL1_INVERT;\
294 type UNIPHY_CHANNEL2_INVERT;\
295 type UNIPHY_CHANNEL3_INVERT;\
296 type UNIPHY_LINK_ENABLE_HPD_MASK;\
297 type UNIPHY_LANE_STAGGER_DELAY;\
298 type RDPCS_SRAMCLK_BYPASS;\
299 type RDPCS_SRAMCLK_EN;\
300 type RDPCS_SRAMCLK_CLOCK_ON;\
301 type DPCS_TX_FIFO_EN;\
302 type RDPCS_PHY_DP_TX0_DISABLE;\
303 type RDPCS_PHY_DP_TX1_DISABLE;\
304 type RDPCS_PHY_DP_TX2_DISABLE;\
305 type RDPCS_PHY_DP_TX3_DISABLE;\
306 type RDPCS_PHY_DP_TX0_CLK_RDY;\
307 type RDPCS_PHY_DP_TX1_CLK_RDY;\
308 type RDPCS_PHY_DP_TX2_CLK_RDY;\
309 type RDPCS_PHY_DP_TX3_CLK_RDY;\
310 type RDPCS_PHY_DP_TX0_REQ;\
311 type RDPCS_PHY_DP_TX1_REQ;\
312 type RDPCS_PHY_DP_TX2_REQ;\
313 type RDPCS_PHY_DP_TX3_REQ;\
314 type RDPCS_PHY_DP_TX0_ACK;\
315 type RDPCS_PHY_DP_TX1_ACK;\
316 type RDPCS_PHY_DP_TX2_ACK;\
317 type RDPCS_PHY_DP_TX3_ACK;\
318 type RDPCS_PHY_DP_TX0_RESET;\
319 type RDPCS_PHY_DP_TX1_RESET;\
320 type RDPCS_PHY_DP_TX2_RESET;\
321 type RDPCS_PHY_DP_TX3_RESET;\
322 type RDPCS_PHY_RESET;\
323 type RDPCS_PHY_CR_MUX_SEL;\
324 type RDPCS_PHY_REF_RANGE;\
325 type RDPCS_PHY_DP4_POR;\
326 type RDPCS_SRAM_BYPASS;\
327 type RDPCS_SRAM_EXT_LD_DONE;\
328 type RDPCS_PHY_DP_TX0_TERM_CTRL;\
329 type RDPCS_PHY_DP_TX1_TERM_CTRL;\
330 type RDPCS_PHY_DP_TX2_TERM_CTRL;\
331 type RDPCS_PHY_DP_TX3_TERM_CTRL;\
332 type RDPCS_PHY_DP_REF_CLK_MPLLB_DIV;\
333 type RDPCS_PHY_DP_MPLLB_MULTIPLIER;\
334 type RDPCS_PHY_DP_MPLLB_SSC_EN;\
335 type RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN;\
336 type RDPCS_PHY_DP_MPLLB_TX_CLK_DIV;\
337 type RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN;\
338 type RDPCS_PHY_DP_MPLLB_FRACN_EN;\
339 type RDPCS_PHY_DP_MPLLB_PMIX_EN;\
340 type RDPCS_PHY_DP_MPLLB_FRACN_QUOT;\
341 type RDPCS_PHY_DP_MPLLB_FRACN_DEN;\
342 type RDPCS_PHY_DP_MPLLB_FRACN_REM;\
343 type RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD;\
344 type RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE;\
345 type RDPCS_PHY_DP_MPLLB_SSC_PEAK;\
346 type RDPCS_PHY_DP_MPLLB_DIV_CLK_EN;\
347 type RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER;\
348 type RDPCS_PHY_TX_VBOOST_LVL;\
349 type RDPCS_PHY_HDMIMODE_ENABLE;\
350 type RDPCS_PHY_DP_REF_CLK_EN;\
351 type RDPCS_PLL_UPDATE_DATA;\
352 type RDPCS_SRAM_INIT_DONE;\
353 type RDPCS_TX_CR_ADDR;\
354 type RDPCS_TX_CR_DATA;\
355 type RDPCS_PHY_HDMI_MPLLB_HDMI_DIV;\
356 type RDPCS_PHY_DP_MPLLB_STATE;\
357 type RDPCS_PHY_DP_TX0_WIDTH;\
358 type RDPCS_PHY_DP_TX0_RATE;\
359 type RDPCS_PHY_DP_TX1_WIDTH;\
360 type RDPCS_PHY_DP_TX1_RATE;\
361 type RDPCS_PHY_DP_TX2_WIDTH;\
362 type RDPCS_PHY_DP_TX2_RATE;\
363 type RDPCS_PHY_DP_TX3_WIDTH;\
364 type RDPCS_PHY_DP_TX3_RATE;\
365 type DPCS_SYMCLK_CLOCK_ON;\
366 type DPCS_SYMCLK_GATE_DIS;\
367 type DPCS_SYMCLK_EN;\
368 type RDPCS_SYMCLK_DIV2_CLOCK_ON;\
369 type RDPCS_SYMCLK_DIV2_GATE_DIS;\
370 type RDPCS_SYMCLK_DIV2_EN;\
371 type DPCS_TX_DATA_SWAP;\
372 type DPCS_TX_DATA_ORDER_INVERT;\
373 type DPCS_TX_FIFO_RD_START_DELAY;\
374 type RDPCS_TX_FIFO_RD_START_DELAY;\
375 type RDPCS_REG_FIFO_ERROR_MASK;\
376 type RDPCS_TX_FIFO_ERROR_MASK;\
377 type RDPCS_DPALT_DISABLE_TOGGLE_MASK;\
378 type RDPCS_DPALT_4LANE_TOGGLE_MASK;\
f537d474 379 type RDPCS_PHY_DPALT_DP4;\
b5b1f455 380 type RDPCS_PHY_DPALT_DISABLE;\
ca4d9b3a
HW		 381 type RDPCS_PHY_DPALT_DISABLE_ACK;\
382 type RDPCS_PHY_DP_MPLLB_V2I;\
383 type RDPCS_PHY_DP_MPLLB_FREQ_VCO;\
91c665bd
BL		 384 type RDPCS_PHY_DP_MPLLB_CP_INT_GS;\
385 type RDPCS_PHY_RX_VREF_CTRL;\
ca4d9b3a
HW		 386 type RDPCS_PHY_DP_MPLLB_CP_INT;\
387 type RDPCS_PHY_DP_MPLLB_CP_PROP;\
388 type RDPCS_PHY_RX_REF_LD_VAL;\
389 type RDPCS_PHY_RX_VCO_LD_VAL;\
390 type DPCSTX_DEBUG_CONFIG; \
91c665bd
BL		 391 type RDPCSTX_DEBUG_CONFIG; \
392 type RDPCS_PHY_DP_TX0_EQ_MAIN;\
393 type RDPCS_PHY_DP_TX0_EQ_PRE;\
394 type RDPCS_PHY_DP_TX0_EQ_POST;\
395 type RDPCS_PHY_DP_TX1_EQ_MAIN;\
396 type RDPCS_PHY_DP_TX1_EQ_PRE;\
397 type RDPCS_PHY_DP_TX1_EQ_POST;\
398 type RDPCS_PHY_DP_TX2_EQ_MAIN;\
399 type RDPCS_PHY_DP_MPLLB_CP_PROP_GS;\
400 type RDPCS_PHY_DP_TX2_EQ_PRE;\
401 type RDPCS_PHY_DP_TX2_EQ_POST;\
402 type RDPCS_PHY_DP_TX3_EQ_MAIN;\
403 type RDPCS_PHY_DCO_RANGE;\
404 type RDPCS_PHY_DCO_FINETUNE;\
405 type RDPCS_PHY_DP_TX3_EQ_PRE;\
406 type RDPCS_PHY_DP_TX3_EQ_POST;\
407 type RDPCS_PHY_SUP_PRE_HP;\
408 type RDPCS_PHY_DP_TX0_VREGDRV_BYP;\
409 type RDPCS_PHY_DP_TX1_VREGDRV_BYP;\
410 type RDPCS_PHY_DP_TX2_VREGDRV_BYP;\
411 type RDPCS_PHY_DP_TX3_VREGDRV_BYP;\
412 type RDPCS_DMCU_DPALT_DIS_BLOCK_REG;\
413 type UNIPHYA_SOFT_RESET;\
414 type UNIPHYB_SOFT_RESET;\
415 type UNIPHYC_SOFT_RESET;\
416 type UNIPHYD_SOFT_RESET;\
417 type UNIPHYE_SOFT_RESET;\
418 type UNIPHYF_SOFT_RESET
ca4d9b3a
HW		 419
420#define DCN20_LINK_ENCODER_REG_FIELD_LIST(type) \
421 type DIG_LANE0EN;\
422 type DIG_LANE1EN;\
423 type DIG_LANE2EN;\
424 type DIG_LANE3EN;\
425 type DIG_CLK_EN;\
426 type SYMCLKA_CLOCK_ENABLE;\
427 type DPHY_FEC_EN;\
428 type DPHY_FEC_READY_SHADOW;\
429 type DPHY_FEC_ACTIVE_STATUS;\
430 DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type);\
431 type VCO_LD_VAL_OVRD;\
432 type VCO_LD_VAL_OVRD_EN;\
433 type REF_LD_VAL_OVRD;\
434 type REF_LD_VAL_OVRD_EN;\
435 type AUX_RX_START_WINDOW; \
436 type AUX_RX_HALF_SYM_DETECT_LEN; \
437 type AUX_RX_TRANSITION_FILTER_EN; \
438 type AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT; \
439 type AUX_RX_ALLOW_BELOW_THRESHOLD_START; \
440 type AUX_RX_ALLOW_BELOW_THRESHOLD_STOP; \
441 type AUX_RX_PHASE_DETECT_LEN; \
442 type AUX_RX_DETECTION_THRESHOLD; \
443 type AUX_TX_PRECHARGE_LEN; \
444 type AUX_TX_PRECHARGE_SYMBOLS; \
445 type AUX_MODE_DET_CHECK_DELAY;\
446 type DPCS_DBG_CBUS_DIS
ca4d9b3a 447
f0cd0a34
EB		 448struct dcn10_link_enc_shift {
449 DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
ca4d9b3a 450 DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
f0cd0a34
EB		 451};
452
453struct dcn10_link_enc_mask {
454 DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
ca4d9b3a 455 DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
f0cd0a34
EB		 456};
457
458struct dcn10_link_encoder {
459 struct link_encoder base;
460 const struct dcn10_link_enc_registers *link_regs;
461 const struct dcn10_link_enc_aux_registers *aux_regs;
462 const struct dcn10_link_enc_hpd_registers *hpd_regs;
463 const struct dcn10_link_enc_shift *link_shift;
464 const struct dcn10_link_enc_mask *link_mask;
465};
466
467
468void dcn10_link_encoder_construct(
469 struct dcn10_link_encoder *enc10,
470 const struct encoder_init_data *init_data,
471 const struct encoder_feature_support *enc_features,
472 const struct dcn10_link_enc_registers *link_regs,
473 const struct dcn10_link_enc_aux_registers *aux_regs,
474 const struct dcn10_link_enc_hpd_registers *hpd_regs,
475 const struct dcn10_link_enc_shift *link_shift,
476 const struct dcn10_link_enc_mask *link_mask);
477
478bool dcn10_link_encoder_validate_dvi_output(
479 const struct dcn10_link_encoder *enc10,
480 enum signal_type connector_signal,
481 enum signal_type signal,
482 const struct dc_crtc_timing *crtc_timing);
483
484bool dcn10_link_encoder_validate_rgb_output(
485 const struct dcn10_link_encoder *enc10,
486 const struct dc_crtc_timing *crtc_timing);
487
488bool dcn10_link_encoder_validate_dp_output(
489 const struct dcn10_link_encoder *enc10,
490 const struct dc_crtc_timing *crtc_timing);
491
492bool dcn10_link_encoder_validate_wireless_output(
493 const struct dcn10_link_encoder *enc10,
494 const struct dc_crtc_timing *crtc_timing);
495
496bool dcn10_link_encoder_validate_output_with_stream(
497 struct link_encoder *enc,
498 const struct dc_stream_state *stream);
499
500/****************** HW programming ************************/
501
502/* initialize HW */ /* why do we initialze aux in here? */
503void dcn10_link_encoder_hw_init(struct link_encoder *enc);
504
505void dcn10_link_encoder_destroy(struct link_encoder **enc);
506
507/* program DIG_MODE in DIG_BE */
508/* TODO can this be combined with enable_output? */
509void dcn10_link_encoder_setup(
510 struct link_encoder *enc,
511 enum signal_type signal);
512
2ee7c03c 513void enc1_configure_encoder(
1bd493e3
TC		 514 struct dcn10_link_encoder *enc10,
515 const struct dc_link_settings *link_settings);
516
f0cd0a34
EB		 517/* enables TMDS PHY output */
518/* TODO: still need depth or just pass in adjusted pixel clock? */
519void dcn10_link_encoder_enable_tmds_output(
520 struct link_encoder *enc,
521 enum clock_source_id clock_source,
522 enum dc_color_depth color_depth,
523 enum signal_type signal,
524 uint32_t pixel_clock);
525
526/* enables DP PHY output */
527void dcn10_link_encoder_enable_dp_output(
528 struct link_encoder *enc,
529 const struct dc_link_settings *link_settings,
530 enum clock_source_id clock_source);
531
532/* enables DP PHY output in MST mode */
533void dcn10_link_encoder_enable_dp_mst_output(
534 struct link_encoder *enc,
535 const struct dc_link_settings *link_settings,
536 enum clock_source_id clock_source);
537
538/* disable PHY output */
539void dcn10_link_encoder_disable_output(
540 struct link_encoder *enc,
541 enum signal_type signal);
542
543/* set DP lane settings */
544void dcn10_link_encoder_dp_set_lane_settings(
545 struct link_encoder *enc,
546 const struct link_training_settings *link_settings);
547
548void dcn10_link_encoder_dp_set_phy_pattern(
549 struct link_encoder *enc,
550 const struct encoder_set_dp_phy_pattern_param *param);
551
552/* programs DP MST VC payload allocation */
553void dcn10_link_encoder_update_mst_stream_allocation_table(
554 struct link_encoder *enc,
555 const struct link_mst_stream_allocation_table *table);
556
557void dcn10_link_encoder_connect_dig_be_to_fe(
558 struct link_encoder *enc,
559 enum engine_id engine,
560 bool connect);
561
562void dcn10_link_encoder_set_dp_phy_pattern_training_pattern(
563 struct link_encoder *enc,
564 uint32_t index);
565
566void dcn10_link_encoder_enable_hpd(struct link_encoder *enc);
567
568void dcn10_link_encoder_disable_hpd(struct link_encoder *enc);
569
570void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
571 bool exit_link_training_required);
572
573void dcn10_psr_program_secondary_packet(struct link_encoder *enc,
574 unsigned int sdp_transmit_line_num_deadline);
575
576bool dcn10_is_dig_enabled(struct link_encoder *enc);
577
68f1a00c
AK		 578unsigned int dcn10_get_dig_frontend(struct link_encoder *enc);
579
ac99243c
YS		 580void dcn10_aux_initialize(struct dcn10_link_encoder *enc10);
581
78d9b95e
CL		 582enum signal_type dcn10_get_dig_mode(
583 struct link_encoder *enc);
8ccf0e20
WL		 584
585void dcn10_link_encoder_get_max_link_cap(struct link_encoder *enc,
586 struct dc_link_settings *link_settings);
f0cd0a34 587#endif /* __DC_LINK_ENCODER__DCN10_H__ */
Linux 6.x block layer and io_uring tree(s)