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904fb6e0 AK |
1 | /* |
2 | * Copyright 2012-15 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | ||
26 | #include "reg_helper.h" | |
27 | #include "core_types.h" | |
28 | #include "dc_dmub_srv.h" | |
d4caa72e AK |
29 | #include "panel_cntl.h" |
30 | #include "dce_panel_cntl.h" | |
3ba01817 | 31 | #include "atom.h" |
904fb6e0 | 32 | |
d4caa72e AK |
33 | #define TO_DCE_PANEL_CNTL(panel_cntl)\ |
34 | container_of(panel_cntl, struct dce_panel_cntl, base) | |
904fb6e0 AK |
35 | |
36 | #define CTX \ | |
d4caa72e | 37 | dce_panel_cntl->base.ctx |
904fb6e0 AK |
38 | |
39 | #define DC_LOGGER \ | |
d4caa72e | 40 | dce_panel_cntl->base.ctx->logger |
904fb6e0 AK |
41 | |
42 | #define REG(reg)\ | |
d4caa72e | 43 | dce_panel_cntl->regs->reg |
904fb6e0 AK |
44 | |
45 | #undef FN | |
46 | #define FN(reg_name, field_name) \ | |
d4caa72e | 47 | dce_panel_cntl->shift->field_name, dce_panel_cntl->mask->field_name |
904fb6e0 | 48 | |
ccc87505 | 49 | static unsigned int dce_get_16_bit_backlight_from_pwm(struct panel_cntl *panel_cntl) |
904fb6e0 | 50 | { |
3ba01817 | 51 | uint64_t current_backlight; |
e738e5ae LJ |
52 | uint32_t bl_period, bl_int_count; |
53 | uint32_t bl_pwm, fractional_duty_cycle_en; | |
3ba01817 | 54 | uint32_t bl_period_mask, bl_pwm_mask; |
ccc87505 | 55 | struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl); |
904fb6e0 | 56 | |
e738e5ae | 57 | REG_READ(BL_PWM_PERIOD_CNTL); |
3ba01817 YS |
58 | REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period); |
59 | REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count); | |
60 | ||
e738e5ae | 61 | REG_READ(BL_PWM_CNTL); |
3ba01817 YS |
62 | REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm)); |
63 | REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en); | |
64 | ||
65 | if (bl_int_count == 0) | |
66 | bl_int_count = 16; | |
67 | ||
68 | bl_period_mask = (1 << bl_int_count) - 1; | |
69 | bl_period &= bl_period_mask; | |
70 | ||
71 | bl_pwm_mask = bl_period_mask << (16 - bl_int_count); | |
72 | ||
73 | if (fractional_duty_cycle_en == 0) | |
74 | bl_pwm &= bl_pwm_mask; | |
75 | else | |
76 | bl_pwm &= 0xFFFF; | |
77 | ||
1d550333 | 78 | current_backlight = (uint64_t)bl_pwm << (1 + bl_int_count); |
3ba01817 YS |
79 | |
80 | if (bl_period == 0) | |
81 | bl_period = 0xFFFF; | |
82 | ||
83 | current_backlight = div_u64(current_backlight, bl_period); | |
84 | current_backlight = (current_backlight + 1) >> 1; | |
85 | ||
3ba01817 YS |
86 | return (uint32_t)(current_backlight); |
87 | } | |
88 | ||
dfd84d90 | 89 | static uint32_t dce_panel_cntl_hw_init(struct panel_cntl *panel_cntl) |
3ba01817 YS |
90 | { |
91 | struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl); | |
92 | uint32_t value; | |
93 | uint32_t current_backlight; | |
94 | ||
95 | /* It must not be 0, so we have to restore them | |
96 | * Bios bug w/a - period resets to zero, | |
97 | * restoring to cache values which is always correct | |
98 | */ | |
99 | REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); | |
100 | ||
7530d914 CC |
101 | if (panel_cntl->stored_backlight_registers.BL_PWM_CNTL != 0) { |
102 | REG_WRITE(BL_PWM_CNTL, | |
103 | panel_cntl->stored_backlight_registers.BL_PWM_CNTL); | |
104 | REG_WRITE(BL_PWM_CNTL2, | |
105 | panel_cntl->stored_backlight_registers.BL_PWM_CNTL2); | |
106 | REG_WRITE(BL_PWM_PERIOD_CNTL, | |
107 | panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL); | |
108 | REG_UPDATE(PWRSEQ_REF_DIV, | |
109 | BL_PWM_REF_DIV, | |
110 | panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV); | |
111 | } else if ((value != 0) && (value != 1)) { | |
3ba01817 YS |
112 | panel_cntl->stored_backlight_registers.BL_PWM_CNTL = |
113 | REG_READ(BL_PWM_CNTL); | |
114 | panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 = | |
115 | REG_READ(BL_PWM_CNTL2); | |
116 | panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL = | |
117 | REG_READ(BL_PWM_PERIOD_CNTL); | |
118 | ||
119 | REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, | |
120 | &panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV); | |
7530d914 CC |
121 | } else { |
122 | /* TODO: Note: This should not really happen since VBIOS | |
123 | * should have initialized PWM registers on boot. | |
124 | */ | |
125 | REG_WRITE(BL_PWM_CNTL, 0x8000FA00); | |
126 | REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0); | |
3ba01817 YS |
127 | } |
128 | ||
129 | // Have driver take backlight control | |
130 | // TakeBacklightControl(true) | |
131 | value = REG_READ(BIOS_SCRATCH_2); | |
132 | value |= ATOM_S2_VRI_BRIGHT_ENABLE; | |
133 | REG_WRITE(BIOS_SCRATCH_2, value); | |
134 | ||
135 | // Enable the backlight output | |
136 | REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1); | |
137 | ||
138 | // Unlock group 2 backlight registers | |
139 | REG_UPDATE(BL_PWM_GRP1_REG_LOCK, | |
140 | BL_PWM_GRP1_REG_LOCK, 0); | |
141 | ||
ccc87505 | 142 | current_backlight = dce_get_16_bit_backlight_from_pwm(panel_cntl); |
3ba01817 YS |
143 | |
144 | return current_backlight; | |
904fb6e0 AK |
145 | } |
146 | ||
dfd84d90 | 147 | static bool dce_is_panel_backlight_on(struct panel_cntl *panel_cntl) |
904fb6e0 | 148 | { |
d4caa72e | 149 | struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl); |
cbf229bb | 150 | uint32_t blon, blon_ovrd, pwrseq_target_state; |
904fb6e0 | 151 | |
cbf229bb PZ |
152 | REG_GET_2(PWRSEQ_CNTL, LVTMA_BLON, &blon, LVTMA_BLON_OVRD, &blon_ovrd); |
153 | REG_GET(PWRSEQ_CNTL, LVTMA_PWRSEQ_TARGET_STATE, &pwrseq_target_state); | |
904fb6e0 | 154 | |
cbf229bb PZ |
155 | if (blon_ovrd) |
156 | return blon; | |
157 | else | |
158 | return pwrseq_target_state; | |
904fb6e0 AK |
159 | } |
160 | ||
dfd84d90 | 161 | static bool dce_is_panel_powered_on(struct panel_cntl *panel_cntl) |
904fb6e0 | 162 | { |
d4caa72e | 163 | struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl); |
904fb6e0 AK |
164 | uint32_t pwr_seq_state, dig_on, dig_on_ovrd; |
165 | ||
3ba01817 | 166 | REG_GET(PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state); |
904fb6e0 | 167 | |
3ba01817 | 168 | REG_GET_2(PWRSEQ_CNTL, LVTMA_DIGON, &dig_on, LVTMA_DIGON_OVRD, &dig_on_ovrd); |
904fb6e0 AK |
169 | |
170 | return (pwr_seq_state == 1) || (dig_on == 1 && dig_on_ovrd == 1); | |
171 | } | |
172 | ||
dfd84d90 | 173 | static void dce_store_backlight_level(struct panel_cntl *panel_cntl) |
3ba01817 YS |
174 | { |
175 | struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl); | |
176 | ||
177 | panel_cntl->stored_backlight_registers.BL_PWM_CNTL = | |
178 | REG_READ(BL_PWM_CNTL); | |
179 | panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 = | |
180 | REG_READ(BL_PWM_CNTL2); | |
181 | panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL = | |
182 | REG_READ(BL_PWM_PERIOD_CNTL); | |
183 | ||
184 | REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, | |
185 | &panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV); | |
186 | } | |
187 | ||
dfd84d90 | 188 | static void dce_driver_set_backlight(struct panel_cntl *panel_cntl, |
3ba01817 YS |
189 | uint32_t backlight_pwm_u16_16) |
190 | { | |
191 | uint32_t backlight_16bit; | |
192 | uint32_t masked_pwm_period; | |
193 | uint8_t bit_count; | |
194 | uint64_t active_duty_cycle; | |
195 | uint32_t pwm_period_bitcnt; | |
196 | struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl); | |
197 | ||
198 | /* | |
199 | * 1. Find 16 bit backlight active duty cycle, where 0 <= backlight | |
200 | * active duty cycle <= backlight period | |
201 | */ | |
202 | ||
203 | /* 1.1 Apply bitmask for backlight period value based on value of BITCNT | |
204 | */ | |
205 | REG_GET_2(BL_PWM_PERIOD_CNTL, | |
206 | BL_PWM_PERIOD_BITCNT, &pwm_period_bitcnt, | |
207 | BL_PWM_PERIOD, &masked_pwm_period); | |
208 | ||
209 | if (pwm_period_bitcnt == 0) | |
210 | bit_count = 16; | |
211 | else | |
212 | bit_count = pwm_period_bitcnt; | |
213 | ||
214 | /* e.g. maskedPwmPeriod = 0x24 when bitCount is 6 */ | |
215 | masked_pwm_period = masked_pwm_period & ((1 << bit_count) - 1); | |
216 | ||
217 | /* 1.2 Calculate integer active duty cycle required upper 16 bits | |
218 | * contain integer component, lower 16 bits contain fractional component | |
219 | * of active duty cycle e.g. 0x21BDC0 = 0xEFF0 * 0x24 | |
220 | */ | |
221 | active_duty_cycle = backlight_pwm_u16_16 * masked_pwm_period; | |
222 | ||
223 | /* 1.3 Calculate 16 bit active duty cycle from integer and fractional | |
224 | * components shift by bitCount then mask 16 bits and add rounding bit | |
225 | * from MSB of fraction e.g. 0x86F7 = ((0x21BDC0 >> 6) & 0xFFF) + 0 | |
226 | */ | |
227 | backlight_16bit = active_duty_cycle >> bit_count; | |
228 | backlight_16bit &= 0xFFFF; | |
229 | backlight_16bit += (active_duty_cycle >> (bit_count - 1)) & 0x1; | |
230 | ||
231 | /* | |
232 | * 2. Program register with updated value | |
233 | */ | |
234 | ||
235 | /* 2.1 Lock group 2 backlight registers */ | |
236 | ||
237 | REG_UPDATE_2(BL_PWM_GRP1_REG_LOCK, | |
238 | BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, 1, | |
239 | BL_PWM_GRP1_REG_LOCK, 1); | |
240 | ||
241 | // 2.2 Write new active duty cycle | |
242 | REG_UPDATE(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, backlight_16bit); | |
243 | ||
244 | /* 2.3 Unlock group 2 backlight registers */ | |
245 | REG_UPDATE(BL_PWM_GRP1_REG_LOCK, | |
246 | BL_PWM_GRP1_REG_LOCK, 0); | |
247 | ||
248 | /* 3 Wait for pending bit to be cleared */ | |
249 | REG_WAIT(BL_PWM_GRP1_REG_LOCK, | |
250 | BL_PWM_GRP1_REG_UPDATE_PENDING, 0, | |
251 | 1, 10000); | |
252 | } | |
253 | ||
d4caa72e | 254 | static void dce_panel_cntl_destroy(struct panel_cntl **panel_cntl) |
904fb6e0 | 255 | { |
d4caa72e | 256 | struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(*panel_cntl); |
904fb6e0 | 257 | |
d4caa72e AK |
258 | kfree(dce_panel_cntl); |
259 | *panel_cntl = NULL; | |
904fb6e0 AK |
260 | } |
261 | ||
d4caa72e AK |
262 | static const struct panel_cntl_funcs dce_link_panel_cntl_funcs = { |
263 | .destroy = dce_panel_cntl_destroy, | |
264 | .hw_init = dce_panel_cntl_hw_init, | |
904fb6e0 AK |
265 | .is_panel_backlight_on = dce_is_panel_backlight_on, |
266 | .is_panel_powered_on = dce_is_panel_powered_on, | |
3ba01817 YS |
267 | .store_backlight_level = dce_store_backlight_level, |
268 | .driver_set_backlight = dce_driver_set_backlight, | |
ccc87505 | 269 | .get_current_backlight = dce_get_16_bit_backlight_from_pwm, |
904fb6e0 AK |
270 | }; |
271 | ||
d4caa72e AK |
272 | void dce_panel_cntl_construct( |
273 | struct dce_panel_cntl *dce_panel_cntl, | |
274 | const struct panel_cntl_init_data *init_data, | |
275 | const struct dce_panel_cntl_registers *regs, | |
276 | const struct dce_panel_cntl_shift *shift, | |
277 | const struct dce_panel_cntl_mask *mask) | |
904fb6e0 | 278 | { |
3ba01817 YS |
279 | struct panel_cntl *base = &dce_panel_cntl->base; |
280 | ||
281 | base->stored_backlight_registers.BL_PWM_CNTL = 0; | |
282 | base->stored_backlight_registers.BL_PWM_CNTL2 = 0; | |
283 | base->stored_backlight_registers.BL_PWM_PERIOD_CNTL = 0; | |
284 | base->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV = 0; | |
285 | ||
d4caa72e AK |
286 | dce_panel_cntl->regs = regs; |
287 | dce_panel_cntl->shift = shift; | |
288 | dce_panel_cntl->mask = mask; | |
904fb6e0 | 289 | |
d4caa72e AK |
290 | dce_panel_cntl->base.funcs = &dce_link_panel_cntl_funcs; |
291 | dce_panel_cntl->base.ctx = init_data->ctx; | |
292 | dce_panel_cntl->base.inst = init_data->inst; | |
4e738260 | 293 | dce_panel_cntl->base.pwrseq_inst = 0; |
904fb6e0 | 294 | } |