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Merge remote-tracking branches 'asoc/topic/wm8753', 'asoc/topic/wm8770', 'asoc/topic...
[linux-block.git] / drivers / gpu / drm / amd / display / dc / dce / dce_hwseq.h
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#ifndef __DCE_HWSEQ_H__
26#define __DCE_HWSEQ_H__
27
28#include "hw_sequencer.h"
29
5eefbc40
YHL		 30#define BL_REG_LIST()\
31 SR(LVTMA_PWRSEQ_CNTL), \
32 SR(LVTMA_PWRSEQ_STATE)
33
4562236b
HW		 34#define HWSEQ_DCEF_REG_LIST_DCE8() \
35 .DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \
36 .DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \
37 .DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \
38 .DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \
39 .DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \
40 .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL
41
42#define HWSEQ_DCEF_REG_LIST() \
43 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
44 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
45 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
46 SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \
47 SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \
48 SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \
49 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
50
51#define HWSEQ_BLND_REG_LIST() \
52 SRII(BLND_V_UPDATE_LOCK, BLND, 0), \
53 SRII(BLND_V_UPDATE_LOCK, BLND, 1), \
54 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
55 SRII(BLND_V_UPDATE_LOCK, BLND, 3), \
56 SRII(BLND_V_UPDATE_LOCK, BLND, 4), \
57 SRII(BLND_V_UPDATE_LOCK, BLND, 5), \
58 SRII(BLND_CONTROL, BLND, 0), \
59 SRII(BLND_CONTROL, BLND, 1), \
60 SRII(BLND_CONTROL, BLND, 2), \
61 SRII(BLND_CONTROL, BLND, 3), \
62 SRII(BLND_CONTROL, BLND, 4), \
63 SRII(BLND_CONTROL, BLND, 5)
64
65#define HWSEQ_PIXEL_RATE_REG_LIST(blk) \
66 SRII(PIXEL_RATE_CNTL, blk, 0), \
67 SRII(PIXEL_RATE_CNTL, blk, 1), \
68 SRII(PIXEL_RATE_CNTL, blk, 2), \
69 SRII(PIXEL_RATE_CNTL, blk, 3), \
70 SRII(PIXEL_RATE_CNTL, blk, 4), \
71 SRII(PIXEL_RATE_CNTL, blk, 5)
72
73#define HWSEQ_PHYPLL_REG_LIST(blk) \
74 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
75 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \
76 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \
77 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \
78 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \
79 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5)
80
81#define HWSEQ_DCE11_REG_LIST_BASE() \
82 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
83 SR(DCFEV_CLOCK_CONTROL), \
84 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
85 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
86 SRII(CRTC_H_BLANK_START_END, CRTC, 0),\
87 SRII(CRTC_H_BLANK_START_END, CRTC, 1),\
88 SRII(BLND_V_UPDATE_LOCK, BLND, 0),\
89 SRII(BLND_V_UPDATE_LOCK, BLND, 1),\
90 SRII(BLND_CONTROL, BLND, 0),\
91 SRII(BLND_CONTROL, BLND, 1),\
92 SR(BLNDV_CONTROL),\
5eefbc40
YHL		 93 HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\
94 BL_REG_LIST()
4562236b
HW		 95
96#define HWSEQ_DCE8_REG_LIST() \
97 HWSEQ_DCEF_REG_LIST_DCE8(), \
98 HWSEQ_BLND_REG_LIST(), \
5eefbc40
YHL		 99 HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\
100 BL_REG_LIST()
4562236b
HW		 101
102#define HWSEQ_DCE10_REG_LIST() \
103 HWSEQ_DCEF_REG_LIST(), \
104 HWSEQ_BLND_REG_LIST(), \
5eefbc40
YHL		 105 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
106 BL_REG_LIST()
4562236b
HW		 107
108#define HWSEQ_ST_REG_LIST() \
109 HWSEQ_DCE11_REG_LIST_BASE(), \
110 .DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \
111 .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \
112 .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \
5eefbc40 113 .BLND_CONTROL[2] = mmBLNDV_CONTROL
4562236b
HW		 114
115#define HWSEQ_CZ_REG_LIST() \
116 HWSEQ_DCE11_REG_LIST_BASE(), \
117 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
118 SRII(CRTC_H_BLANK_START_END, CRTC, 2), \
119 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
120 SRII(BLND_CONTROL, BLND, 2), \
121 .DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \
122 .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \
123 .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \
124 .BLND_CONTROL[3] = mmBLNDV_CONTROL
125
08b16886
ZF		 126#define HWSEQ_DCE120_REG_LIST() \
127 HWSEQ_DCE10_REG_LIST(), \
128 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
129 HWSEQ_PHYPLL_REG_LIST(CRTC), \
130 SR(DCHUB_FB_LOCATION),\
131 SR(DCHUB_AGP_BASE),\
132 SR(DCHUB_AGP_BOT),\
5eefbc40
YHL		 133 SR(DCHUB_AGP_TOP), \
134 BL_REG_LIST()
08b16886 135
4562236b
HW		 136#define HWSEQ_DCE112_REG_LIST() \
137 HWSEQ_DCE10_REG_LIST(), \
138 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
5eefbc40
YHL		 139 HWSEQ_PHYPLL_REG_LIST(CRTC), \
140 BL_REG_LIST()
4562236b 141
184debdb 142#define HWSEQ_DCN_REG_LIST()\
184debdb
DL		 143 SRII(DCHUBP_CNTL, HUBP, 0), \
144 SRII(DCHUBP_CNTL, HUBP, 1), \
145 SRII(DCHUBP_CNTL, HUBP, 2), \
146 SRII(DCHUBP_CNTL, HUBP, 3), \
147 SRII(HUBP_CLK_CNTL, HUBP, 0), \
148 SRII(HUBP_CLK_CNTL, HUBP, 1), \
149 SRII(HUBP_CLK_CNTL, HUBP, 2), \
150 SRII(HUBP_CLK_CNTL, HUBP, 3), \
151 SRII(DPP_CONTROL, DPP_TOP, 0), \
152 SRII(DPP_CONTROL, DPP_TOP, 1), \
153 SRII(DPP_CONTROL, DPP_TOP, 2), \
154 SRII(DPP_CONTROL, DPP_TOP, 3), \
d21becbe
TC		 155 SRII(OPP_PIPE_CONTROL, OPP_PIPE, 0), \
156 SRII(OPP_PIPE_CONTROL, OPP_PIPE, 1), \
157 SRII(OPP_PIPE_CONTROL, OPP_PIPE, 2), \
158 SRII(OPP_PIPE_CONTROL, OPP_PIPE, 3), \
184debdb 159 SR(REFCLK_CNTL), \
08b16886
ZF		 160 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
161 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\
08b16886
ZF		 162 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\
163 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
164 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\
08b16886
ZF		 165 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\
166 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
167 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\
08b16886
ZF		 168 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\
169 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
170 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D),\
08b16886
ZF		 171 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\
172 SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
173 SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\
174 SR(DCHUBBUB_ARB_SAT_LEVEL),\
175 SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
184debdb 176 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
2b13d7d3
TC		 177 SR(DCHUBBUB_TEST_DEBUG_INDEX), \
178 SR(DCHUBBUB_TEST_DEBUG_DATA), \
184debdb
DL		 179 SR(DIO_MEM_PWR_CTRL), \
180 SR(DCCG_GATE_DISABLE_CNTL), \
181 SR(DCCG_GATE_DISABLE_CNTL2), \
0a87425a
TC		 182 SR(DCFCLK_CNTL),\
183 SR(DCFCLK_CNTL), \
0cb8a881
YHL		 184 /* todo: get these from GVM instead of reading registers ourselves */\
185 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\
186 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\
187 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\
188 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\
189 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\
190 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\
191 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\
192 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\
193 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\
194 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\
195 MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\
196 MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR)
184debdb 197
0c63c115
EB		 198#define HWSEQ_SR_WATERMARK_REG_LIST()\
199 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\
200 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\
201 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\
202 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\
203 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\
204 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\
205 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\
206 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D)
207
184debdb 208#define HWSEQ_DCN1_REG_LIST()\
08b16886 209 HWSEQ_DCN_REG_LIST(), \
0c63c115 210 HWSEQ_SR_WATERMARK_REG_LIST(), \
eade8350
YHL		 211 HWSEQ_PIXEL_RATE_REG_LIST(OTG), \
212 HWSEQ_PHYPLL_REG_LIST(OTG), \
08b16886
ZF		 213 SR(DCHUBBUB_SDPIF_FB_TOP),\
214 SR(DCHUBBUB_SDPIF_FB_BASE),\
215 SR(DCHUBBUB_SDPIF_FB_OFFSET),\
216 SR(DCHUBBUB_SDPIF_AGP_BASE),\
217 SR(DCHUBBUB_SDPIF_AGP_BOT),\
eade8350
YHL		 218 SR(DCHUBBUB_SDPIF_AGP_TOP),\
219 SR(DOMAIN0_PG_CONFIG), \
220 SR(DOMAIN1_PG_CONFIG), \
221 SR(DOMAIN2_PG_CONFIG), \
222 SR(DOMAIN3_PG_CONFIG), \
223 SR(DOMAIN4_PG_CONFIG), \
224 SR(DOMAIN5_PG_CONFIG), \
225 SR(DOMAIN6_PG_CONFIG), \
226 SR(DOMAIN7_PG_CONFIG), \
227 SR(DOMAIN0_PG_STATUS), \
228 SR(DOMAIN1_PG_STATUS), \
229 SR(DOMAIN2_PG_STATUS), \
230 SR(DOMAIN3_PG_STATUS), \
231 SR(DOMAIN4_PG_STATUS), \
232 SR(DOMAIN5_PG_STATUS), \
233 SR(DOMAIN6_PG_STATUS), \
d53d7866
YHL		 234 SR(DOMAIN7_PG_STATUS), \
235 SR(D1VGA_CONTROL), \
236 SR(D2VGA_CONTROL), \
237 SR(D3VGA_CONTROL), \
238 SR(D4VGA_CONTROL), \
bd9bc355 239 SR(VGA_TEST_CONTROL), \
5eefbc40
YHL		 240 SR(DC_IP_REQUEST_CNTL), \
241 BL_REG_LIST()
184debdb 242
4562236b 243struct dce_hwseq_registers {
5eefbc40
YHL		 244
245 /* Backlight registers */
246 uint32_t LVTMA_PWRSEQ_CNTL;
247 uint32_t LVTMA_PWRSEQ_STATE;
248
4562236b
HW		 249 uint32_t DCFE_CLOCK_CONTROL[6];
250 uint32_t DCFEV_CLOCK_CONTROL;
251 uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL;
252 uint32_t BLND_V_UPDATE_LOCK[6];
253 uint32_t BLND_CONTROL[6];
254 uint32_t BLNDV_CONTROL;
4562236b
HW		 255 uint32_t CRTC_H_BLANK_START_END[6];
256 uint32_t PIXEL_RATE_CNTL[6];
257 uint32_t PHYPLL_PIXEL_RATE_CNTL[6];
08b16886
ZF		 258 /*DCHUB*/
259 uint32_t DCHUB_FB_LOCATION;
260 uint32_t DCHUB_AGP_BASE;
261 uint32_t DCHUB_AGP_BOT;
262 uint32_t DCHUB_AGP_TOP;
184debdb 263
184debdb
DL		 264 uint32_t DCHUBP_CNTL[4];
265 uint32_t HUBP_CLK_CNTL[4];
266 uint32_t DPP_CONTROL[4];
d21becbe 267 uint32_t OPP_PIPE_CONTROL[4];
184debdb 268 uint32_t REFCLK_CNTL;
08b16886
ZF		 269 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;
270 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A;
271 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;
272 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;
273 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;
274 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;
275 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B;
276 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;
277 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;
278 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;
279 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;
280 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C;
281 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;
282 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;
283 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;
284 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;
285 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D;
286 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;
287 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D;
288 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;
289 uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL;
290 uint32_t DCHUBBUB_ARB_SAT_LEVEL;
291 uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND;
184debdb 292 uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL;
2b13d7d3
TC		 293 uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL;
294 uint32_t DCHUBBUB_TEST_DEBUG_INDEX;
295 uint32_t DCHUBBUB_TEST_DEBUG_DATA;
08b16886
ZF		 296 uint32_t DCHUBBUB_SDPIF_FB_TOP;
297 uint32_t DCHUBBUB_SDPIF_FB_BASE;
298 uint32_t DCHUBBUB_SDPIF_FB_OFFSET;
299 uint32_t DCHUBBUB_SDPIF_AGP_BASE;
300 uint32_t DCHUBBUB_SDPIF_AGP_BOT;
301 uint32_t DCHUBBUB_SDPIF_AGP_TOP;
184debdb
DL		 302 uint32_t DC_IP_REQUEST_CNTL;
303 uint32_t DOMAIN0_PG_CONFIG;
304 uint32_t DOMAIN1_PG_CONFIG;
305 uint32_t DOMAIN2_PG_CONFIG;
306 uint32_t DOMAIN3_PG_CONFIG;
307 uint32_t DOMAIN4_PG_CONFIG;
308 uint32_t DOMAIN5_PG_CONFIG;
309 uint32_t DOMAIN6_PG_CONFIG;
310 uint32_t DOMAIN7_PG_CONFIG;
311 uint32_t DOMAIN0_PG_STATUS;
312 uint32_t DOMAIN1_PG_STATUS;
313 uint32_t DOMAIN2_PG_STATUS;
314 uint32_t DOMAIN3_PG_STATUS;
315 uint32_t DOMAIN4_PG_STATUS;
316 uint32_t DOMAIN5_PG_STATUS;
317 uint32_t DOMAIN6_PG_STATUS;
318 uint32_t DOMAIN7_PG_STATUS;
319 uint32_t DIO_MEM_PWR_CTRL;
320 uint32_t DCCG_GATE_DISABLE_CNTL;
321 uint32_t DCCG_GATE_DISABLE_CNTL2;
322 uint32_t DCFCLK_CNTL;
b02c3b05
DL		 323 uint32_t MICROSECOND_TIME_BASE_DIV;
324 uint32_t MILLISECOND_TIME_BASE_DIV;
325 uint32_t DISPCLK_FREQ_CHANGE_CNTL;
326 uint32_t RBBMIF_TIMEOUT_DIS;
327 uint32_t RBBMIF_TIMEOUT_DIS_2;
51666631
DL		 328 uint32_t DENTIST_DISPCLK_CNTL;
329 uint32_t DCHUBBUB_CRC_CTRL;
330 uint32_t DPP_TOP0_DPP_CRC_CTRL;
331 uint32_t DPP_TOP0_DPP_CRC_VAL_R_G;
332 uint32_t DPP_TOP0_DPP_CRC_VAL_B_A;
333 uint32_t MPC_CRC_CTRL;
334 uint32_t MPC_CRC_RESULT_GB;
335 uint32_t MPC_CRC_RESULT_C;
336 uint32_t MPC_CRC_RESULT_AR;
0a87425a
TC		 337 uint32_t D1VGA_CONTROL;
338 uint32_t D2VGA_CONTROL;
339 uint32_t D3VGA_CONTROL;
340 uint32_t D4VGA_CONTROL;
bd9bc355 341 uint32_t VGA_TEST_CONTROL;
0cb8a881
YHL		 342 /* MMHUB registers. read only. temporary hack */
343 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32;
344 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
345 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32;
346 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32;
347 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32;
348 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32;
349 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32;
350 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32;
351 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;
352 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;
353 uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR;
354 uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR;
4562236b
HW		 355};
356 /* set field name */
357#define HWS_SF(blk_name, reg_name, field_name, post_fix)\
358 .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
359
360#define HWS_SF1(blk_name, reg_name, field_name, post_fix)\
361 .field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix
362
363
364#define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\
365 HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\
366 SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh)
367
368#define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\
369 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
370 HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
371 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
372 HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\
373 HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\
374 HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\
375 HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\
376 HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\
377 HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh)
378
379#define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\
380 HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\
381 HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
382
383#define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\
384 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\
385 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh)
386
387#define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\
388 .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \
389 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
390 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
391 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
392 HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\
5eefbc40 393 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
87401969 394 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\
4562236b
HW		 395 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
396
397#define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\
398 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\
399 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\
5eefbc40 400 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_), \
87401969
AJ		 401 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
402 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
4562236b
HW		 403
404#define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\
405 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
406 SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\
5eefbc40 407 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
87401969 408 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\
4562236b
HW		 409 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
410
411#define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\
412 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
5eefbc40 413 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
87401969 414 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\
4562236b
HW		 415 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)
416
08b16886
ZF		 417#define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\
418 SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\
419 SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
420 SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
421 SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
5eefbc40 422 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh), \
87401969
AJ		 423 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
424 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
08b16886 425
2c8ad2d5
AD		 426#define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\
427 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\
428 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\
429 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
08b16886 430 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\
5eefbc40 431 HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh), \
87401969
AJ		 432 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
433 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
2c8ad2d5 434
184debdb 435#define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\
ff5ef992 436 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
0b6ab57e 437 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \
184debdb
DL		 438 HWS_SF(HUBP0_, DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh), \
439 HWS_SF(HUBP0_, HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh), \
440 HWS_SF(DPP_TOP0_, DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
d21becbe 441 HWS_SF(OPP_PIPE0_, OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh),\
184debdb 442 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
08b16886
ZF		 443 HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \
444 HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \
445 HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \
446 HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \
458e9d03
BL		 447 HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \
448 HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \
08b16886
ZF		 449 HWS_SF(, DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \
450 HWS_SF(, DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \
184debdb 451 HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh)
184debdb 452
184debdb
DL		 453#define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\
454 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
455 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \
08b16886
ZF		 456 HWS_SF(, DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh), \
457 HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \
458 HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \
459 HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \
460 HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \
461 HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \
0cb8a881
YHL		 462 HWS_SF(DPP_TOP0_, DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh), \
463 /* todo: get these from GVM instead of reading registers ourselves */\
464 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
465 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
466 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
467 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\
468 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\
469 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\
470 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\
471 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\
eade8350
YHL		 472 HWS_SF(, MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh),\
473 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
474 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
475 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
476 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
477 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
478 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
479 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
480 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
481 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
482 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
483 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
484 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
485 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
486 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
487 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
488 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
489 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
490 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
491 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
492 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
493 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
494 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
495 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
d53d7866 496 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
5eefbc40 497 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
abca2400 498 HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\
219be9dd
CZ		 499 HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\
500 HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\
501 HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\
bd9bc355 502 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
abca2400
EY		 503 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\
504 HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
505 HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
ff5ef992 506
184debdb 507#define HWSEQ_REG_FIELD_LIST(type) \
4562236b
HW		 508 type DCFE_CLOCK_ENABLE; \
509 type DCFEV_CLOCK_ENABLE; \
510 type DC_MEM_GLOBAL_PWR_REQ_DIS; \
511 type BLND_DCP_GRPH_V_UPDATE_LOCK; \
512 type BLND_SCL_V_UPDATE_LOCK; \
513 type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \
514 type BLND_BLND_V_UPDATE_LOCK; \
515 type BLND_V_UPDATE_LOCK_MODE; \
516 type BLND_FEEDTHROUGH_EN; \
517 type BLND_ALPHA_MODE; \
518 type BLND_MODE; \
519 type BLND_MULTIPLIED_MODE; \
520 type DP_DTO0_ENABLE; \
521 type PIXEL_RATE_SOURCE; \
522 type PHYPLL_PIXEL_RATE_SOURCE; \
523 type PIXEL_RATE_PLL_SOURCE; \
0cb8a881
YHL		 524 /* todo: get these from GVM instead of reading registers ourselves */\
525 type PAGE_DIRECTORY_ENTRY_HI32;\
526 type PAGE_DIRECTORY_ENTRY_LO32;\
527 type LOGICAL_PAGE_NUMBER_HI4;\
528 type LOGICAL_PAGE_NUMBER_LO32;\
529 type PHYSICAL_PAGE_ADDR_HI4;\
530 type PHYSICAL_PAGE_ADDR_LO32;\
531 type PHYSICAL_PAGE_NUMBER_MSB;\
532 type PHYSICAL_PAGE_NUMBER_LSB;\
533 type LOGICAL_ADDR; \
534 type ENABLE_L1_TLB;\
5eefbc40 535 type SYSTEM_ACCESS_MODE;\
87401969
AJ		 536 type LVTMA_BLON;\
537 type LVTMA_PWRSEQ_TARGET_STATE_R;
4562236b 538
184debdb 539#define HWSEQ_DCN_REG_FIELD_LIST(type) \
184debdb
DL		 540 type HUBP_VTG_SEL; \
541 type HUBP_CLOCK_ENABLE; \
542 type DPP_CLOCK_ENABLE; \
543 type DPPCLK_RATE_CONTROL; \
08b16886
ZF		 544 type SDPIF_FB_TOP;\
545 type SDPIF_FB_BASE;\
546 type SDPIF_FB_OFFSET;\
547 type SDPIF_AGP_BASE;\
548 type SDPIF_AGP_BOT;\
549 type SDPIF_AGP_TOP;\
550 type FB_TOP;\
551 type FB_BASE;\
552 type FB_OFFSET;\
553 type AGP_BASE;\
554 type AGP_BOT;\
555 type AGP_TOP;\
184debdb 556 type DCHUBBUB_GLOBAL_TIMER_ENABLE; \
08b16886
ZF		 557 type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\
558 type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\
559 type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\
560 type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\
458e9d03
BL		 561 type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE;\
562 type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE;\
08b16886
ZF		 563 type DCHUBBUB_ARB_SAT_LEVEL;\
564 type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\
d21becbe 565 type OPP_PIPE_CLOCK_EN;\
184debdb
DL		 566 type IP_REQUEST_EN; \
567 type DOMAIN0_POWER_FORCEON; \
568 type DOMAIN0_POWER_GATE; \
569 type DOMAIN1_POWER_FORCEON; \
570 type DOMAIN1_POWER_GATE; \
571 type DOMAIN2_POWER_FORCEON; \
572 type DOMAIN2_POWER_GATE; \
573 type DOMAIN3_POWER_FORCEON; \
574 type DOMAIN3_POWER_GATE; \
575 type DOMAIN4_POWER_FORCEON; \
576 type DOMAIN4_POWER_GATE; \
577 type DOMAIN5_POWER_FORCEON; \
578 type DOMAIN5_POWER_GATE; \
579 type DOMAIN6_POWER_FORCEON; \
580 type DOMAIN6_POWER_GATE; \
581 type DOMAIN7_POWER_FORCEON; \
582 type DOMAIN7_POWER_GATE; \
583 type DOMAIN0_PGFSM_PWR_STATUS; \
584 type DOMAIN1_PGFSM_PWR_STATUS; \
585 type DOMAIN2_PGFSM_PWR_STATUS; \
586 type DOMAIN3_PGFSM_PWR_STATUS; \
587 type DOMAIN4_PGFSM_PWR_STATUS; \
588 type DOMAIN5_PGFSM_PWR_STATUS; \
589 type DOMAIN6_PGFSM_PWR_STATUS; \
590 type DOMAIN7_PGFSM_PWR_STATUS; \
b02c3b05 591 type DCFCLK_GATE_DIS; \
51666631 592 type DCHUBBUB_GLOBAL_TIMER_REFDIV; \
96d92388 593 type DENTIST_DPPCLK_WDIVIDER; \
bd9bc355
BL		 594 type DENTIST_DISPCLK_WDIVIDER; \
595 type VGA_TEST_ENABLE; \
abca2400 596 type VGA_TEST_RENDER_START; \
219be9dd
CZ		 597 type D1VGA_MODE_ENABLE; \
598 type D2VGA_MODE_ENABLE; \
599 type D3VGA_MODE_ENABLE; \
600 type D4VGA_MODE_ENABLE;
184debdb 601
4562236b 602struct dce_hwseq_shift {
184debdb 603 HWSEQ_REG_FIELD_LIST(uint8_t)
184debdb 604 HWSEQ_DCN_REG_FIELD_LIST(uint8_t)
4562236b
HW		 605};
606
607struct dce_hwseq_mask {
184debdb 608 HWSEQ_REG_FIELD_LIST(uint32_t)
184debdb 609 HWSEQ_DCN_REG_FIELD_LIST(uint32_t)
4562236b
HW		 610};
611
4562236b
HW		 612
613enum blnd_mode {
614 BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
615 BLND_MODE_OTHER_PIPE, /* Data from other pipe only */
616 BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
617};
618
619void dce_enable_fe_clock(struct dce_hwseq *hwss,
620 unsigned int inst, bool enable);
621
fb3466a4 622void dce_pipe_control_lock(struct dc *dc,
f0828115 623 struct pipe_ctx *pipe,
4562236b
HW		 624 bool lock);
625
626void dce_set_blender_mode(struct dce_hwseq *hws,
627 unsigned int blnd_inst, enum blnd_mode mode);
628
629void dce_clock_gating_power_up(struct dce_hwseq *hws,
630 bool enable);
631
632void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
633 struct clock_source *clk_src,
634 unsigned int tg_inst);
98489c02 635
3be5262e 636bool dce_use_lut(const struct dc_plane_state *plane_state);
4562236b 637#endif /*__DCE_HWSEQ_H__*/
Linux 6.x block layer and io_uring tree(s)