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drm/amd/display: Use function pointer for update_plane_addr
[linux-block.git] / drivers / gpu / drm / amd / display / dc / dce / dce_hwseq.h
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#ifndef __DCE_HWSEQ_H__
26#define __DCE_HWSEQ_H__
27
28#include "hw_sequencer.h"
29
30#define HWSEQ_DCEF_REG_LIST_DCE8() \
31 .DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \
32 .DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \
33 .DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \
34 .DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \
35 .DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \
36 .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL
37
38#define HWSEQ_DCEF_REG_LIST() \
39 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
40 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
41 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
42 SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \
43 SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \
44 SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \
45 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
46
47#define HWSEQ_BLND_REG_LIST() \
48 SRII(BLND_V_UPDATE_LOCK, BLND, 0), \
49 SRII(BLND_V_UPDATE_LOCK, BLND, 1), \
50 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
51 SRII(BLND_V_UPDATE_LOCK, BLND, 3), \
52 SRII(BLND_V_UPDATE_LOCK, BLND, 4), \
53 SRII(BLND_V_UPDATE_LOCK, BLND, 5), \
54 SRII(BLND_CONTROL, BLND, 0), \
55 SRII(BLND_CONTROL, BLND, 1), \
56 SRII(BLND_CONTROL, BLND, 2), \
57 SRII(BLND_CONTROL, BLND, 3), \
58 SRII(BLND_CONTROL, BLND, 4), \
59 SRII(BLND_CONTROL, BLND, 5)
60
61#define HWSEQ_PIXEL_RATE_REG_LIST(blk) \
62 SRII(PIXEL_RATE_CNTL, blk, 0), \
63 SRII(PIXEL_RATE_CNTL, blk, 1), \
64 SRII(PIXEL_RATE_CNTL, blk, 2), \
65 SRII(PIXEL_RATE_CNTL, blk, 3), \
66 SRII(PIXEL_RATE_CNTL, blk, 4), \
67 SRII(PIXEL_RATE_CNTL, blk, 5)
68
69#define HWSEQ_PHYPLL_REG_LIST(blk) \
70 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
71 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \
72 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \
73 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \
74 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \
75 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5)
76
77#define HWSEQ_DCE11_REG_LIST_BASE() \
78 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
79 SR(DCFEV_CLOCK_CONTROL), \
80 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
81 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
82 SRII(CRTC_H_BLANK_START_END, CRTC, 0),\
83 SRII(CRTC_H_BLANK_START_END, CRTC, 1),\
84 SRII(BLND_V_UPDATE_LOCK, BLND, 0),\
85 SRII(BLND_V_UPDATE_LOCK, BLND, 1),\
86 SRII(BLND_CONTROL, BLND, 0),\
87 SRII(BLND_CONTROL, BLND, 1),\
88 SR(BLNDV_CONTROL),\
89 HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
90
91#define HWSEQ_DCE8_REG_LIST() \
92 HWSEQ_DCEF_REG_LIST_DCE8(), \
93 HWSEQ_BLND_REG_LIST(), \
94 HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
95
96#define HWSEQ_DCE10_REG_LIST() \
97 HWSEQ_DCEF_REG_LIST(), \
98 HWSEQ_BLND_REG_LIST(), \
99 HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
100
101#define HWSEQ_ST_REG_LIST() \
102 HWSEQ_DCE11_REG_LIST_BASE(), \
103 .DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \
104 .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \
105 .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \
106 .BLND_CONTROL[2] = mmBLNDV_CONTROL,
107
108#define HWSEQ_CZ_REG_LIST() \
109 HWSEQ_DCE11_REG_LIST_BASE(), \
110 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
111 SRII(CRTC_H_BLANK_START_END, CRTC, 2), \
112 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
113 SRII(BLND_CONTROL, BLND, 2), \
114 .DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \
115 .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \
116 .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \
117 .BLND_CONTROL[3] = mmBLNDV_CONTROL
118
08b16886
ZF		 119#define HWSEQ_DCE120_REG_LIST() \
120 HWSEQ_DCE10_REG_LIST(), \
121 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
122 HWSEQ_PHYPLL_REG_LIST(CRTC), \
123 SR(DCHUB_FB_LOCATION),\
124 SR(DCHUB_AGP_BASE),\
125 SR(DCHUB_AGP_BOT),\
126 SR(DCHUB_AGP_TOP)
127
4562236b
HW		 128#define HWSEQ_DCE112_REG_LIST() \
129 HWSEQ_DCE10_REG_LIST(), \
130 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
131 HWSEQ_PHYPLL_REG_LIST(CRTC)
132
184debdb 133#define HWSEQ_DCN_REG_LIST()\
ff5ef992 134 HWSEQ_PIXEL_RATE_REG_LIST(OTG), \
184debdb
DL		 135 HWSEQ_PHYPLL_REG_LIST(OTG), \
136 SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 0), \
137 SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 1), \
138 SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 2), \
139 SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 3), \
140 SRII(DCHUBP_CNTL, HUBP, 0), \
141 SRII(DCHUBP_CNTL, HUBP, 1), \
142 SRII(DCHUBP_CNTL, HUBP, 2), \
143 SRII(DCHUBP_CNTL, HUBP, 3), \
144 SRII(HUBP_CLK_CNTL, HUBP, 0), \
145 SRII(HUBP_CLK_CNTL, HUBP, 1), \
146 SRII(HUBP_CLK_CNTL, HUBP, 2), \
147 SRII(HUBP_CLK_CNTL, HUBP, 3), \
148 SRII(DPP_CONTROL, DPP_TOP, 0), \
149 SRII(DPP_CONTROL, DPP_TOP, 1), \
150 SRII(DPP_CONTROL, DPP_TOP, 2), \
151 SRII(DPP_CONTROL, DPP_TOP, 3), \
d21becbe
TC		 152 SRII(OPP_PIPE_CONTROL, OPP_PIPE, 0), \
153 SRII(OPP_PIPE_CONTROL, OPP_PIPE, 1), \
154 SRII(OPP_PIPE_CONTROL, OPP_PIPE, 2), \
155 SRII(OPP_PIPE_CONTROL, OPP_PIPE, 3), \
184debdb 156 SR(REFCLK_CNTL), \
08b16886
ZF		 157 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
158 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\
159 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\
160 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\
161 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\
162 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
163 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\
164 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\
165 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\
166 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\
167 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
168 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\
169 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\
170 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\
171 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\
172 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
173 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D),\
174 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\
175 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D),\
176 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\
177 SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
178 SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\
179 SR(DCHUBBUB_ARB_SAT_LEVEL),\
180 SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
184debdb 181 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
2b13d7d3
TC		 182 SR(DCHUBBUB_TEST_DEBUG_INDEX), \
183 SR(DCHUBBUB_TEST_DEBUG_DATA), \
184debdb
DL		 184 SR(DC_IP_REQUEST_CNTL), \
185 SR(DOMAIN0_PG_CONFIG), \
186 SR(DOMAIN1_PG_CONFIG), \
187 SR(DOMAIN2_PG_CONFIG), \
188 SR(DOMAIN3_PG_CONFIG), \
189 SR(DOMAIN4_PG_CONFIG), \
190 SR(DOMAIN5_PG_CONFIG), \
191 SR(DOMAIN6_PG_CONFIG), \
192 SR(DOMAIN7_PG_CONFIG), \
193 SR(DOMAIN0_PG_STATUS), \
194 SR(DOMAIN1_PG_STATUS), \
195 SR(DOMAIN2_PG_STATUS), \
196 SR(DOMAIN3_PG_STATUS), \
197 SR(DOMAIN4_PG_STATUS), \
198 SR(DOMAIN5_PG_STATUS), \
199 SR(DOMAIN6_PG_STATUS), \
200 SR(DOMAIN7_PG_STATUS), \
201 SR(DIO_MEM_PWR_CTRL), \
202 SR(DCCG_GATE_DISABLE_CNTL), \
203 SR(DCCG_GATE_DISABLE_CNTL2), \
0a87425a
TC		 204 SR(DCFCLK_CNTL),\
205 SR(DCFCLK_CNTL), \
206 SR(D1VGA_CONTROL), \
207 SR(D2VGA_CONTROL), \
208 SR(D3VGA_CONTROL), \
209 SR(D4VGA_CONTROL)
184debdb 210
184debdb 211#define HWSEQ_DCN1_REG_LIST()\
08b16886
ZF		 212 HWSEQ_DCN_REG_LIST(), \
213 SR(DCHUBBUB_SDPIF_FB_TOP),\
214 SR(DCHUBBUB_SDPIF_FB_BASE),\
215 SR(DCHUBBUB_SDPIF_FB_OFFSET),\
216 SR(DCHUBBUB_SDPIF_AGP_BASE),\
217 SR(DCHUBBUB_SDPIF_AGP_BOT),\
218 SR(DCHUBBUB_SDPIF_AGP_TOP)
ff5ef992 219
184debdb 220
4562236b
HW		 221struct dce_hwseq_registers {
222 uint32_t DCFE_CLOCK_CONTROL[6];
223 uint32_t DCFEV_CLOCK_CONTROL;
224 uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL;
225 uint32_t BLND_V_UPDATE_LOCK[6];
226 uint32_t BLND_CONTROL[6];
227 uint32_t BLNDV_CONTROL;
4562236b
HW		 228 uint32_t CRTC_H_BLANK_START_END[6];
229 uint32_t PIXEL_RATE_CNTL[6];
230 uint32_t PHYPLL_PIXEL_RATE_CNTL[6];
08b16886
ZF		 231 /*DCHUB*/
232 uint32_t DCHUB_FB_LOCATION;
233 uint32_t DCHUB_AGP_BASE;
234 uint32_t DCHUB_AGP_BOT;
235 uint32_t DCHUB_AGP_TOP;
184debdb 236
184debdb
DL		 237 uint32_t OTG_GLOBAL_SYNC_STATUS[4];
238 uint32_t DCHUBP_CNTL[4];
239 uint32_t HUBP_CLK_CNTL[4];
240 uint32_t DPP_CONTROL[4];
d21becbe 241 uint32_t OPP_PIPE_CONTROL[4];
184debdb 242 uint32_t REFCLK_CNTL;
08b16886
ZF		 243 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;
244 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A;
245 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;
246 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;
247 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;
248 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;
249 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B;
250 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;
251 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;
252 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;
253 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;
254 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C;
255 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;
256 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;
257 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;
258 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;
259 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D;
260 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;
261 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D;
262 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;
263 uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL;
264 uint32_t DCHUBBUB_ARB_SAT_LEVEL;
265 uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND;
184debdb 266 uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL;
2b13d7d3
TC		 267 uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL;
268 uint32_t DCHUBBUB_TEST_DEBUG_INDEX;
269 uint32_t DCHUBBUB_TEST_DEBUG_DATA;
08b16886
ZF		 270 uint32_t DCHUBBUB_SDPIF_FB_TOP;
271 uint32_t DCHUBBUB_SDPIF_FB_BASE;
272 uint32_t DCHUBBUB_SDPIF_FB_OFFSET;
273 uint32_t DCHUBBUB_SDPIF_AGP_BASE;
274 uint32_t DCHUBBUB_SDPIF_AGP_BOT;
275 uint32_t DCHUBBUB_SDPIF_AGP_TOP;
184debdb
DL		 276 uint32_t DC_IP_REQUEST_CNTL;
277 uint32_t DOMAIN0_PG_CONFIG;
278 uint32_t DOMAIN1_PG_CONFIG;
279 uint32_t DOMAIN2_PG_CONFIG;
280 uint32_t DOMAIN3_PG_CONFIG;
281 uint32_t DOMAIN4_PG_CONFIG;
282 uint32_t DOMAIN5_PG_CONFIG;
283 uint32_t DOMAIN6_PG_CONFIG;
284 uint32_t DOMAIN7_PG_CONFIG;
285 uint32_t DOMAIN0_PG_STATUS;
286 uint32_t DOMAIN1_PG_STATUS;
287 uint32_t DOMAIN2_PG_STATUS;
288 uint32_t DOMAIN3_PG_STATUS;
289 uint32_t DOMAIN4_PG_STATUS;
290 uint32_t DOMAIN5_PG_STATUS;
291 uint32_t DOMAIN6_PG_STATUS;
292 uint32_t DOMAIN7_PG_STATUS;
293 uint32_t DIO_MEM_PWR_CTRL;
294 uint32_t DCCG_GATE_DISABLE_CNTL;
295 uint32_t DCCG_GATE_DISABLE_CNTL2;
296 uint32_t DCFCLK_CNTL;
b02c3b05
DL		 297 uint32_t MICROSECOND_TIME_BASE_DIV;
298 uint32_t MILLISECOND_TIME_BASE_DIV;
299 uint32_t DISPCLK_FREQ_CHANGE_CNTL;
300 uint32_t RBBMIF_TIMEOUT_DIS;
301 uint32_t RBBMIF_TIMEOUT_DIS_2;
51666631
DL		 302 uint32_t DENTIST_DISPCLK_CNTL;
303 uint32_t DCHUBBUB_CRC_CTRL;
304 uint32_t DPP_TOP0_DPP_CRC_CTRL;
305 uint32_t DPP_TOP0_DPP_CRC_VAL_R_G;
306 uint32_t DPP_TOP0_DPP_CRC_VAL_B_A;
307 uint32_t MPC_CRC_CTRL;
308 uint32_t MPC_CRC_RESULT_GB;
309 uint32_t MPC_CRC_RESULT_C;
310 uint32_t MPC_CRC_RESULT_AR;
0a87425a
TC		 311 uint32_t D1VGA_CONTROL;
312 uint32_t D2VGA_CONTROL;
313 uint32_t D3VGA_CONTROL;
314 uint32_t D4VGA_CONTROL;
4562236b
HW		 315};
316 /* set field name */
317#define HWS_SF(blk_name, reg_name, field_name, post_fix)\
318 .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
319
320#define HWS_SF1(blk_name, reg_name, field_name, post_fix)\
321 .field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix
322
323
324#define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\
325 HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\
326 SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh)
327
328#define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\
329 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
330 HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
331 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
332 HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\
333 HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\
334 HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\
335 HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\
336 HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\
337 HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh)
338
339#define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\
340 HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\
341 HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
342
343#define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\
344 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\
345 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh)
346
347#define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\
348 .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \
349 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
350 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
351 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
352 HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\
353 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
354
355#define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\
356 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\
357 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\
358 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
359
360#define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\
361 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
362 SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\
363 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
364
365#define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\
366 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
367 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)
368
08b16886
ZF		 369#define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\
370 SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\
371 SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
372 SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
373 SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
374 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
375
2c8ad2d5
AD		 376#define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\
377 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\
378 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\
379 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
08b16886
ZF		 380 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\
381 HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)
2c8ad2d5 382
184debdb 383#define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\
ff5ef992 384 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
0b6ab57e 385 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \
184debdb
DL		 386 HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR, mask_sh), \
387 HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_OCCURRED, mask_sh), \
184debdb
DL		 388 HWS_SF(HUBP0_, DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh), \
389 HWS_SF(HUBP0_, HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh), \
390 HWS_SF(DPP_TOP0_, DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
d21becbe 391 HWS_SF(OPP_PIPE0_, OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh),\
184debdb
DL		 392 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
393 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
394 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
395 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
396 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
397 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
398 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
399 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
400 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
401 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
402 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
403 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
404 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
405 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
406 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
407 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
408 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
409 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
410 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
411 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
412 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
413 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
414 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
415 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
416 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
417 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
08b16886
ZF		 418 HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \
419 HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \
420 HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \
421 HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \
422 HWS_SF(, DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \
423 HWS_SF(, DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \
184debdb 424 HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh)
184debdb 425
184debdb
DL		 426#define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\
427 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
428 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \
08b16886
ZF		 429 HWS_SF(, DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh), \
430 HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \
431 HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \
432 HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \
433 HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \
434 HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \
184debdb 435 HWS_SF(DPP_TOP0_, DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh)
ff5ef992 436
184debdb 437#define HWSEQ_REG_FIELD_LIST(type) \
4562236b
HW		 438 type DCFE_CLOCK_ENABLE; \
439 type DCFEV_CLOCK_ENABLE; \
440 type DC_MEM_GLOBAL_PWR_REQ_DIS; \
441 type BLND_DCP_GRPH_V_UPDATE_LOCK; \
442 type BLND_SCL_V_UPDATE_LOCK; \
443 type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \
444 type BLND_BLND_V_UPDATE_LOCK; \
445 type BLND_V_UPDATE_LOCK_MODE; \
446 type BLND_FEEDTHROUGH_EN; \
447 type BLND_ALPHA_MODE; \
448 type BLND_MODE; \
449 type BLND_MULTIPLIED_MODE; \
450 type DP_DTO0_ENABLE; \
451 type PIXEL_RATE_SOURCE; \
452 type PHYPLL_PIXEL_RATE_SOURCE; \
453 type PIXEL_RATE_PLL_SOURCE; \
454
184debdb
DL		 455#define HWSEQ_DCN_REG_FIELD_LIST(type) \
456 type VUPDATE_NO_LOCK_EVENT_CLEAR; \
457 type VUPDATE_NO_LOCK_EVENT_OCCURRED; \
184debdb
DL		 458 type HUBP_VTG_SEL; \
459 type HUBP_CLOCK_ENABLE; \
460 type DPP_CLOCK_ENABLE; \
461 type DPPCLK_RATE_CONTROL; \
08b16886
ZF		 462 type SDPIF_FB_TOP;\
463 type SDPIF_FB_BASE;\
464 type SDPIF_FB_OFFSET;\
465 type SDPIF_AGP_BASE;\
466 type SDPIF_AGP_BOT;\
467 type SDPIF_AGP_TOP;\
468 type FB_TOP;\
469 type FB_BASE;\
470 type FB_OFFSET;\
471 type AGP_BASE;\
472 type AGP_BOT;\
473 type AGP_TOP;\
184debdb 474 type DCHUBBUB_GLOBAL_TIMER_ENABLE; \
08b16886
ZF		 475 type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\
476 type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\
477 type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\
478 type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\
479 type DCHUBBUB_ARB_SAT_LEVEL;\
480 type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\
d21becbe 481 type OPP_PIPE_CLOCK_EN;\
184debdb
DL		 482 type IP_REQUEST_EN; \
483 type DOMAIN0_POWER_FORCEON; \
484 type DOMAIN0_POWER_GATE; \
485 type DOMAIN1_POWER_FORCEON; \
486 type DOMAIN1_POWER_GATE; \
487 type DOMAIN2_POWER_FORCEON; \
488 type DOMAIN2_POWER_GATE; \
489 type DOMAIN3_POWER_FORCEON; \
490 type DOMAIN3_POWER_GATE; \
491 type DOMAIN4_POWER_FORCEON; \
492 type DOMAIN4_POWER_GATE; \
493 type DOMAIN5_POWER_FORCEON; \
494 type DOMAIN5_POWER_GATE; \
495 type DOMAIN6_POWER_FORCEON; \
496 type DOMAIN6_POWER_GATE; \
497 type DOMAIN7_POWER_FORCEON; \
498 type DOMAIN7_POWER_GATE; \
499 type DOMAIN0_PGFSM_PWR_STATUS; \
500 type DOMAIN1_PGFSM_PWR_STATUS; \
501 type DOMAIN2_PGFSM_PWR_STATUS; \
502 type DOMAIN3_PGFSM_PWR_STATUS; \
503 type DOMAIN4_PGFSM_PWR_STATUS; \
504 type DOMAIN5_PGFSM_PWR_STATUS; \
505 type DOMAIN6_PGFSM_PWR_STATUS; \
506 type DOMAIN7_PGFSM_PWR_STATUS; \
b02c3b05 507 type DCFCLK_GATE_DIS; \
51666631
DL		 508 type DCHUBBUB_GLOBAL_TIMER_REFDIV; \
509 type DENTIST_DPPCLK_WDIVIDER;
184debdb 510
4562236b 511struct dce_hwseq_shift {
184debdb 512 HWSEQ_REG_FIELD_LIST(uint8_t)
184debdb 513 HWSEQ_DCN_REG_FIELD_LIST(uint8_t)
4562236b
HW		 514};
515
516struct dce_hwseq_mask {
184debdb 517 HWSEQ_REG_FIELD_LIST(uint32_t)
184debdb 518 HWSEQ_DCN_REG_FIELD_LIST(uint32_t)
4562236b
HW		 519};
520
4562236b
HW		 521
522enum blnd_mode {
523 BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
524 BLND_MODE_OTHER_PIPE, /* Data from other pipe only */
525 BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
526};
527
528void dce_enable_fe_clock(struct dce_hwseq *hwss,
529 unsigned int inst, bool enable);
530
f0828115
CL		 531void dce_pipe_control_lock(struct core_dc *dc,
532 struct pipe_ctx *pipe,
4562236b
HW		 533 bool lock);
534
535void dce_set_blender_mode(struct dce_hwseq *hws,
536 unsigned int blnd_inst, enum blnd_mode mode);
537
538void dce_clock_gating_power_up(struct dce_hwseq *hws,
539 bool enable);
540
541void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
542 struct clock_source *clk_src,
543 unsigned int tg_inst);
98489c02 544
3be5262e 545bool dce_use_lut(const struct dc_plane_state *plane_state);
4562236b 546#endif /*__DCE_HWSEQ_H__*/
Linux 6.x block layer and io_uring tree(s)