[linux-block.git] / drivers / gpu / drm / amd / display / dc / dc_types.h

/*
 * Copyright 2012-15 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */
#ifndef DC_TYPES_H_
#define DC_TYPES_H_

#include "os_types.h"
#include "fixed31_32.h"
#include "irq_types.h"
#include "dc_dp_types.h"
#include "dc_hw_types.h"
#include "dal_types.h"
#include "grph_object_defs.h"

/* forward declarations */
struct dc_plane_state;
struct dc_stream_state;
struct dc_link;
struct dc_sink;
struct dal;

/********************************
 * Environment definitions
 ********************************/
enum dce_environment {
	DCE_ENV_PRODUCTION_DRV = 0,
	/* Emulation on FPGA, in "Maximus" System.
	 * This environment enforces that *only* DC registers accessed.
	 * (access to non-DC registers will hang FPGA) */
	DCE_ENV_FPGA_MAXIMUS,
	/* Emulation on real HW or on FPGA. Used by Diagnostics, enforces
	 * requirements of Diagnostics team. */
	DCE_ENV_DIAG
};

/* Note: use these macro definitions instead of direct comparison! */
#define IS_FPGA_MAXIMUS_DC(dce_environment) \
	(dce_environment == DCE_ENV_FPGA_MAXIMUS)

#define IS_DIAG_DC(dce_environment) \
	(IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))

struct hw_asic_id {
	uint32_t chip_id;
	uint32_t chip_family;
	uint32_t pci_revision_id;
	uint32_t hw_internal_rev;
	uint32_t vram_type;
	uint32_t vram_width;
	uint32_t feature_flags;
	uint32_t fake_paths_num;
	void *atombios_base_address;
};

struct dc_context {
	struct dc *dc;

	void *driver_context; /* e.g. amdgpu_device */

	struct dal_logger *logger;
	void *cgs_device;

	enum dce_environment dce_environment;
	struct hw_asic_id asic_id;

	/* todo: below should probably move to dc.  to facilitate removal
	 * of AS we will store these here
	 */
	enum dce_version dce_version;
	struct dc_bios *dc_bios;
	bool created_bios;
	struct gpio_service *gpio_service;
	struct i2caux *i2caux;
#if defined(CONFIG_DRM_AMD_DC_FBC)
	uint64_t fbc_gpu_addr;
#endif
};


#define MAX_EDID_BUFFER_SIZE 512
#define EDID_BLOCK_SIZE 128
#define MAX_SURFACE_NUM 4
#define NUM_PIXEL_FORMATS 10

#include "dc_ddc_types.h"

enum tiling_mode {
	TILING_MODE_INVALID,
	TILING_MODE_LINEAR,
	TILING_MODE_TILED,
	TILING_MODE_COUNT
};

enum view_3d_format {
	VIEW_3D_FORMAT_NONE = 0,
	VIEW_3D_FORMAT_FRAME_SEQUENTIAL,
	VIEW_3D_FORMAT_SIDE_BY_SIDE,
	VIEW_3D_FORMAT_TOP_AND_BOTTOM,
	VIEW_3D_FORMAT_COUNT,
	VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL
};

enum plane_stereo_format {
	PLANE_STEREO_FORMAT_NONE = 0,
	PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1,
	PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2,
	PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3,
	PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5,
	PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6,
	PLANE_STEREO_FORMAT_CHECKER_BOARD = 7
};

/* TODO: Find way to calculate number of bits
 *  Please increase if pixel_format enum increases
 * num  from  PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32
 */

enum dc_edid_connector_type {
	EDID_CONNECTOR_UNKNOWN = 0,
	EDID_CONNECTOR_ANALOG = 1,
	EDID_CONNECTOR_DIGITAL = 10,
	EDID_CONNECTOR_DVI = 11,
	EDID_CONNECTOR_HDMIA = 12,
	EDID_CONNECTOR_MDDI = 14,
	EDID_CONNECTOR_DISPLAYPORT = 15
};

enum dc_edid_status {
	EDID_OK,
	EDID_BAD_INPUT,
	EDID_NO_RESPONSE,
	EDID_BAD_CHECKSUM,
	EDID_THE_SAME,
};

/* audio capability from EDID*/
struct dc_cea_audio_mode {
	uint8_t format_code; /* ucData[0] [6:3]*/
	uint8_t channel_count; /* ucData[0] [2:0]*/
	uint8_t sample_rate; /* ucData[1]*/
	union {
		uint8_t sample_size; /* for LPCM*/
		/*  for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
		uint8_t max_bit_rate;
		uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
	};
};

struct dc_edid {
	uint32_t length;
	uint8_t raw_edid[MAX_EDID_BUFFER_SIZE];
};

/* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION
 * is used. In this case we assume speaker location are: front left, front
 * right and front center. */
#define DEFAULT_SPEAKER_LOCATION 5

#define DC_MAX_AUDIO_DESC_COUNT 16

#define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20

union display_content_support {
	unsigned int raw;
	struct {
		unsigned int valid_content_type :1;
		unsigned int game_content :1;
		unsigned int cinema_content :1;
		unsigned int photo_content :1;
		unsigned int graphics_content :1;
		unsigned int reserved :27;
	} bits;
};

struct dc_panel_patch {
	unsigned int dppowerup_delay;
};

struct dc_edid_caps {
	/* sink identification */
	uint16_t manufacturer_id;
	uint16_t product_id;
	uint32_t serial_number;
	uint8_t manufacture_week;
	uint8_t manufacture_year;
	uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];

	/* audio caps */
	uint8_t speaker_flags;
	uint32_t audio_mode_count;
	struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT];
	uint32_t audio_latency;
	uint32_t video_latency;

	union display_content_support content_support;

	uint8_t qs_bit;
	uint8_t qy_bit;

	/*HDMI 2.0 caps*/
	bool lte_340mcsc_scramble;

	bool edid_hdmi;
	bool hdr_supported;

	struct dc_panel_patch panel_patch;
};

struct view {
	uint32_t width;
	uint32_t height;
};

struct dc_mode_flags {
	/* note: part of refresh rate flag*/
	uint32_t INTERLACE :1;
	/* native display timing*/
	uint32_t NATIVE :1;
	/* preferred is the recommended mode, one per display */
	uint32_t PREFERRED :1;
	/* true if this mode should use reduced blanking timings
	 *_not_ related to the Reduced Blanking adjustment*/
	uint32_t REDUCED_BLANKING :1;
	/* note: part of refreshrate flag*/
	uint32_t VIDEO_OPTIMIZED_RATE :1;
	/* should be reported to upper layers as mode_flags*/
	uint32_t PACKED_PIXEL_FORMAT :1;
	/*< preferred view*/
	uint32_t PREFERRED_VIEW :1;
	/* this timing should be used only in tiled mode*/
	uint32_t TILED_MODE :1;
	uint32_t DSE_MODE :1;
	/* Refresh rate divider when Miracast sink is using a
	 different rate than the output display device
	 Must be zero for wired displays and non-zero for
	 Miracast displays*/
	uint32_t MIRACAST_REFRESH_DIVIDER;
};


enum dc_timing_source {
	TIMING_SOURCE_UNDEFINED,

	/* explicitly specifed by user, most important*/
	TIMING_SOURCE_USER_FORCED,
	TIMING_SOURCE_USER_OVERRIDE,
	TIMING_SOURCE_CUSTOM,
	TIMING_SOURCE_EXPLICIT,

	/* explicitly specified by the display device, more important*/
	TIMING_SOURCE_EDID_CEA_SVD_3D,
	TIMING_SOURCE_EDID_CEA_SVD_PREFERRED,
	TIMING_SOURCE_EDID_CEA_SVD_420,
	TIMING_SOURCE_EDID_DETAILED,
	TIMING_SOURCE_EDID_ESTABLISHED,
	TIMING_SOURCE_EDID_STANDARD,
	TIMING_SOURCE_EDID_CEA_SVD,
	TIMING_SOURCE_EDID_CVT_3BYTE,
	TIMING_SOURCE_EDID_4BYTE,
	TIMING_SOURCE_VBIOS,
	TIMING_SOURCE_CV,
	TIMING_SOURCE_TV,
	TIMING_SOURCE_HDMI_VIC,

	/* implicitly specified by display device, still safe but less important*/
	TIMING_SOURCE_DEFAULT,

	/* only used for custom base modes */
	TIMING_SOURCE_CUSTOM_BASE,

	/* these timing might not work, least important*/
	TIMING_SOURCE_RANGELIMIT,
	TIMING_SOURCE_OS_FORCED,
	TIMING_SOURCE_IMPLICIT,

	/* only used by default mode list*/
	TIMING_SOURCE_BASICMODE,

	TIMING_SOURCE_COUNT
};


struct stereo_3d_features {
	bool supported			;
	bool allTimings			;
	bool cloneMode			;
	bool scaling			;
	bool singleFrameSWPacked;
};

enum dc_timing_support_method {
	TIMING_SUPPORT_METHOD_UNDEFINED,
	TIMING_SUPPORT_METHOD_EXPLICIT,
	TIMING_SUPPORT_METHOD_IMPLICIT,
	TIMING_SUPPORT_METHOD_NATIVE
};

struct dc_mode_info {
	uint32_t pixel_width;
	uint32_t pixel_height;
	uint32_t field_rate;
	/* Vertical refresh rate for progressive modes.
	* Field rate for interlaced modes.*/

	enum dc_timing_standard timing_standard;
	enum dc_timing_source timing_source;
	struct dc_mode_flags flags;
};

enum dc_power_state {
	DC_POWER_STATE_ON = 1,
	DC_POWER_STATE_STANDBY,
	DC_POWER_STATE_SUSPEND,
	DC_POWER_STATE_OFF
};

/* DC PowerStates */
enum dc_video_power_state {
	DC_VIDEO_POWER_UNSPECIFIED = 0,
	DC_VIDEO_POWER_ON = 1,
	DC_VIDEO_POWER_STANDBY,
	DC_VIDEO_POWER_SUSPEND,
	DC_VIDEO_POWER_OFF,
	DC_VIDEO_POWER_HIBERNATE,
	DC_VIDEO_POWER_SHUTDOWN,
	DC_VIDEO_POWER_ULPS,	/* BACO or Ultra-Light-Power-State */
	DC_VIDEO_POWER_AFTER_RESET,
	DC_VIDEO_POWER_MAXIMUM
};

enum dc_acpi_cm_power_state {
	DC_ACPI_CM_POWER_STATE_D0 = 1,
	DC_ACPI_CM_POWER_STATE_D1 = 2,
	DC_ACPI_CM_POWER_STATE_D2 = 4,
	DC_ACPI_CM_POWER_STATE_D3 = 8
};

enum dc_connection_type {
	dc_connection_none,
	dc_connection_single,
	dc_connection_mst_branch,
	dc_connection_active_dongle
};

struct dc_csc_adjustments {
	struct fixed31_32 contrast;
	struct fixed31_32 saturation;
	struct fixed31_32 brightness;
	struct fixed31_32 hue;
};

enum dpcd_downstream_port_max_bpc {
	DOWN_STREAM_MAX_8BPC = 0,
	DOWN_STREAM_MAX_10BPC,
	DOWN_STREAM_MAX_12BPC,
	DOWN_STREAM_MAX_16BPC
};
struct dc_dongle_caps {
	/* dongle type (DP converter, CV smart dongle) */
	enum display_dongle_type dongle_type;
	bool extendedCapValid;
	/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
	indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
	bool is_dp_hdmi_s3d_converter;
	bool is_dp_hdmi_ycbcr422_pass_through;
	bool is_dp_hdmi_ycbcr420_pass_through;
	bool is_dp_hdmi_ycbcr422_converter;
	bool is_dp_hdmi_ycbcr420_converter;
	uint32_t dp_hdmi_max_bpc;
	uint32_t dp_hdmi_max_pixel_clk;
};
/* Scaling format */
enum scaling_transformation {
	SCALING_TRANSFORMATION_UNINITIALIZED,
	SCALING_TRANSFORMATION_IDENTITY = 0x0001,
	SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002,
	SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004,
	SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008,
	SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010,
	SCALING_TRANSFORMATION_INVALID = 0x80000000,

	/* Flag the first and last */
	SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY,
	SCALING_TRANSFORMATION_END =
		SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
};

enum display_content_type {
	DISPLAY_CONTENT_TYPE_NO_DATA = 0,
	DISPLAY_CONTENT_TYPE_GRAPHICS = 1,
	DISPLAY_CONTENT_TYPE_PHOTO = 2,
	DISPLAY_CONTENT_TYPE_CINEMA = 4,
	DISPLAY_CONTENT_TYPE_GAME = 8
};

/* audio*/

union audio_sample_rates {
	struct sample_rates {
		uint8_t RATE_32:1;
		uint8_t RATE_44_1:1;
		uint8_t RATE_48:1;
		uint8_t RATE_88_2:1;
		uint8_t RATE_96:1;
		uint8_t RATE_176_4:1;
		uint8_t RATE_192:1;
	} rate;

	uint8_t all;
};

struct audio_speaker_flags {
	uint32_t FL_FR:1;
	uint32_t LFE:1;
	uint32_t FC:1;
	uint32_t RL_RR:1;
	uint32_t RC:1;
	uint32_t FLC_FRC:1;
	uint32_t RLC_RRC:1;
	uint32_t SUPPORT_AI:1;
};

struct audio_speaker_info {
	uint32_t ALLSPEAKERS:7;
	uint32_t SUPPORT_AI:1;
};


struct audio_info_flags {

	union {

		struct audio_speaker_flags speaker_flags;
		struct audio_speaker_info   info;

		uint8_t all;
	};
};

enum audio_format_code {
	AUDIO_FORMAT_CODE_FIRST = 1,
	AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST,

	AUDIO_FORMAT_CODE_AC3,
	/*Layers 1 & 2 */
	AUDIO_FORMAT_CODE_MPEG1,
	/*MPEG1 Layer 3 */
	AUDIO_FORMAT_CODE_MP3,
	/*multichannel */
	AUDIO_FORMAT_CODE_MPEG2,
	AUDIO_FORMAT_CODE_AAC,
	AUDIO_FORMAT_CODE_DTS,
	AUDIO_FORMAT_CODE_ATRAC,
	AUDIO_FORMAT_CODE_1BITAUDIO,
	AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS,
	AUDIO_FORMAT_CODE_DTS_HD,
	AUDIO_FORMAT_CODE_MAT_MLP,
	AUDIO_FORMAT_CODE_DST,
	AUDIO_FORMAT_CODE_WMAPRO,
	AUDIO_FORMAT_CODE_LAST,
	AUDIO_FORMAT_CODE_COUNT =
		AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST
};

struct audio_mode {
	 /* ucData[0] [6:3] */
	enum audio_format_code format_code;
	/* ucData[0] [2:0] */
	uint8_t channel_count;
	/* ucData[1] */
	union audio_sample_rates sample_rates;
	union {
		/* for LPCM */
		uint8_t sample_size;
		/* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */
		uint8_t max_bit_rate;
		/* for Audio Formats 9-15 */
		uint8_t vendor_specific;
	};
};

struct audio_info {
	struct audio_info_flags flags;
	uint32_t video_latency;
	uint32_t audio_latency;
	uint32_t display_index;
	uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
	uint32_t manufacture_id;
	uint32_t product_id;
	/* PortID used for ContainerID when defined */
	uint32_t port_id[2];
	uint32_t mode_count;
	/* this field must be last in this struct */
	struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT];
};

struct vrr_params {
	enum vrr_state state;
	uint32_t window_min;
	uint32_t window_max;
	uint32_t inserted_frame_duration_in_us;
	uint32_t frames_to_insert;
	uint32_t frame_counter;
};

struct dc_info_packet {
	bool valid;
	uint8_t hb0;
	uint8_t hb1;
	uint8_t hb2;
	uint8_t hb3;
	uint8_t sb[32];
};

#define DC_PLANE_UPDATE_TIMES_MAX 10

struct dc_plane_flip_time {
	unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX];
	unsigned int index;
	unsigned int prev_update_time_in_us;
};

// Will combine with vrr_params at some point.
struct freesync_context {
	bool supported;
	bool enabled;
	bool active;

	unsigned int min_refresh_in_micro_hz;
	unsigned int nominal_refresh_in_micro_hz;
};

struct psr_config {
	unsigned char psr_version;
	unsigned int psr_rfb_setup_time;
	bool psr_exit_link_training_required;

	bool psr_frame_capture_indication_req;
	unsigned int psr_sdp_transmit_line_num_deadline;
};

union dmcu_psr_level {
	struct {
		unsigned int SKIP_CRC:1;
		unsigned int SKIP_DP_VID_STREAM_DISABLE:1;
		unsigned int SKIP_PHY_POWER_DOWN:1;
		unsigned int SKIP_AUX_ACK_CHECK:1;
		unsigned int SKIP_CRTC_DISABLE:1;
		unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1;
		unsigned int SKIP_SMU_NOTIFICATION:1;
		unsigned int SKIP_AUTO_STATE_ADVANCE:1;
		unsigned int DISABLE_PSR_ENTRY_ABORT:1;
		unsigned int SKIP_SINGLE_OTG_DISABLE:1;
		unsigned int RESERVED:22;
	} bits;
	unsigned int u32all;
};

enum physical_phy_id {
	PHYLD_0,
	PHYLD_1,
	PHYLD_2,
	PHYLD_3,
	PHYLD_4,
	PHYLD_5,
	PHYLD_6,
	PHYLD_7,
	PHYLD_8,
	PHYLD_9,
	PHYLD_COUNT,
	PHYLD_UNKNOWN = (-1L)
};

enum phy_type {
	PHY_TYPE_UNKNOWN  = 1,
	PHY_TYPE_PCIE_PHY = 2,
	PHY_TYPE_UNIPHY = 3,
};

struct psr_context {
	/* ddc line */
	enum channel_id channel;
	/* Transmitter id */
	enum transmitter transmitterId;
	/* Engine Id is used for Dig Be source select */
	enum engine_id engineId;
	/* Controller Id used for Dig Fe source select */
	enum controller_id controllerId;
	/* Pcie or Uniphy */
	enum phy_type phyType;
	/* Physical PHY Id used by SMU interpretation */
	enum physical_phy_id smuPhyId;
	/* Vertical total pixels from crtc timing.
	 * This is used for static screen detection.
	 * ie. If we want to detect half a frame,
	 * we use this to determine the hyst lines.
	 */
	unsigned int crtcTimingVerticalTotal;
	/* PSR supported from panel capabilities and
	 * current display configuration
	 */
	bool psrSupportedDisplayConfig;
	/* Whether fast link training is supported by the panel */
	bool psrExitLinkTrainingRequired;
	/* If RFB setup time is greater than the total VBLANK time,
	 * it is not possible for the sink to capture the video frame
	 * in the same frame the SDP is sent. In this case,
	 * the frame capture indication bit should be set and an extra
	 * static frame should be transmitted to the sink.
	 */
	bool psrFrameCaptureIndicationReq;
	/* Set the last possible line SDP may be transmitted without violating
	 * the RFB setup time or entering the active video frame.
	 */
	unsigned int sdpTransmitLineNumDeadline;
	/* The VSync rate in Hz used to calculate the
	 * step size for smooth brightness feature
	 */
	unsigned int vsyncRateHz;
	unsigned int skipPsrWaitForPllLock;
	unsigned int numberOfControllers;
	/* Unused, for future use. To indicate that first changed frame from
	 * state3 shouldn't result in psr_inactive, but rather to perform
	 * an automatic single frame rfb_update.
	 */
	bool rfb_update_auto_en;
	/* Number of frame before entering static screen */
	unsigned int timehyst_frames;
	/* Partial frames before entering static screen */
	unsigned int hyst_lines;
	/* # of repeated AUX transaction attempts to make before
	 * indicating failure to the driver
	 */
	unsigned int aux_repeats;
	/* Controls hw blocks to power down during PSR active state */
	union dmcu_psr_level psr_level;
	/* Controls additional delay after remote frame capture before
	 * continuing powerd own
	 */
	unsigned int frame_delay;
};

struct colorspace_transform {
	struct fixed31_32 matrix[12];
	bool enable_remap;
};

enum i2c_mot_mode {
	I2C_MOT_UNDEF,
	I2C_MOT_TRUE,
	I2C_MOT_FALSE
};

#endif /* DC_TYPES_H_ */
Commit	Line	Data
4562236b HW	1	/*
	2	* Copyright 2012-15 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25	#ifndef DC_TYPES_H_
	26	#define DC_TYPES_H_
	27
eb0e5154	28	#include "os_types.h"
4562236b HW	29	#include "fixed31_32.h"
	30	#include "irq_types.h"
	31	#include "dc_dp_types.h"
	32	#include "dc_hw_types.h"
	33	#include "dal_types.h"
9f72f51d	34	#include "grph_object_defs.h"
4562236b HW	35
4562236b HW	36	/* forward declarations */
c9614aeb	37	struct dc_plane_state;
0971c40e	38	struct dc_stream_state;
4562236b HW	39	struct dc_link;
	40	struct dc_sink;
	41	struct dal;
	42
	43	/********************************
	44	* Environment definitions
	45	********************************/
	46	enum dce_environment {
	47	DCE_ENV_PRODUCTION_DRV = 0,
	48	/* Emulation on FPGA, in "Maximus" System.
	49	* This environment enforces that only DC registers accessed.
	50	* (access to non-DC registers will hang FPGA) */
	51	DCE_ENV_FPGA_MAXIMUS,
	52	/* Emulation on real HW or on FPGA. Used by Diagnostics, enforces
	53	* requirements of Diagnostics team. */
	54	DCE_ENV_DIAG
	55	};
	56
	57	/* Note: use these macro definitions instead of direct comparison! */
	58	#define IS_FPGA_MAXIMUS_DC(dce_environment) \
	59	(dce_environment == DCE_ENV_FPGA_MAXIMUS)
	60
	61	#define IS_DIAG_DC(dce_environment) \
	62	(IS_FPGA_MAXIMUS_DC(dce_environment) \|\| (dce_environment == DCE_ENV_DIAG))
	63
	64	struct hw_asic_id {
	65	uint32_t chip_id;
	66	uint32_t chip_family;
	67	uint32_t pci_revision_id;
	68	uint32_t hw_internal_rev;
	69	uint32_t vram_type;
	70	uint32_t vram_width;
	71	uint32_t feature_flags;
	72	uint32_t fake_paths_num;
	73	void *atombios_base_address;
	74	};
	75
	76	struct dc_context {
	77	struct dc *dc;
	78
	79	void driver_context; / e.g. amdgpu_device */
	80
	81	struct dal_logger *logger;
	82	void *cgs_device;
	83
	84	enum dce_environment dce_environment;
	85	struct hw_asic_id asic_id;
	86
	87	/* todo: below should probably move to dc. to facilitate removal
	88	* of AS we will store these here
	89	*/
	90	enum dce_version dce_version;
	91	struct dc_bios *dc_bios;
	92	bool created_bios;
	93	struct gpio_service *gpio_service;
	94	struct i2caux *i2caux;
3eab7916	95	#if defined(CONFIG_DRM_AMD_DC_FBC)
690b5e39 RL	96	uint64_t fbc_gpu_addr;
690b5e39 RL	97	#endif
4562236b HW	98	};
	99
	100
	101	#define MAX_EDID_BUFFER_SIZE 512
	102	#define EDID_BLOCK_SIZE 128
ba326a91	103	#define MAX_SURFACE_NUM 4
4562236b HW	104	#define NUM_PIXEL_FORMATS 10
	105
	106	#include "dc_ddc_types.h"
	107
	108	enum tiling_mode {
	109	TILING_MODE_INVALID,
	110	TILING_MODE_LINEAR,
	111	TILING_MODE_TILED,
	112	TILING_MODE_COUNT
	113	};
	114
	115	enum view_3d_format {
	116	VIEW_3D_FORMAT_NONE = 0,
	117	VIEW_3D_FORMAT_FRAME_SEQUENTIAL,
	118	VIEW_3D_FORMAT_SIDE_BY_SIDE,
	119	VIEW_3D_FORMAT_TOP_AND_BOTTOM,
	120	VIEW_3D_FORMAT_COUNT,
	121	VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL
	122	};
	123
	124	enum plane_stereo_format {
	125	PLANE_STEREO_FORMAT_NONE = 0,
	126	PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1,
	127	PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2,
	128	PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3,
	129	PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5,
	130	PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6,
	131	PLANE_STEREO_FORMAT_CHECKER_BOARD = 7
	132	};
	133
	134	/* TODO: Find way to calculate number of bits
	135	* Please increase if pixel_format enum increases
	136	* num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32
	137	*/
	138
	139	enum dc_edid_connector_type {
	140	EDID_CONNECTOR_UNKNOWN = 0,
	141	EDID_CONNECTOR_ANALOG = 1,
	142	EDID_CONNECTOR_DIGITAL = 10,
	143	EDID_CONNECTOR_DVI = 11,
	144	EDID_CONNECTOR_HDMIA = 12,
	145	EDID_CONNECTOR_MDDI = 14,
	146	EDID_CONNECTOR_DISPLAYPORT = 15
	147	};
	148
	149	enum dc_edid_status {
	150	EDID_OK,
	151	EDID_BAD_INPUT,
	152	EDID_NO_RESPONSE,
	153	EDID_BAD_CHECKSUM,
7d58e721	154	EDID_THE_SAME,
4562236b HW	155	};
	156
	157	/* audio capability from EDID*/
	158	struct dc_cea_audio_mode {
	159	uint8_t format_code; /* ucData[0] [6:3]*/
	160	uint8_t channel_count; /* ucData[0] [2:0]*/
	161	uint8_t sample_rate; /* ucData[1]*/
	162	union {
	163	uint8_t sample_size; /* for LPCM*/
	164	/* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
	165	uint8_t max_bit_rate;
	166	uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
	167	};
	168	};
	169
	170	struct dc_edid {
	171	uint32_t length;
	172	uint8_t raw_edid[MAX_EDID_BUFFER_SIZE];
	173	};
	174
	175	/* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION
	176	* is used. In this case we assume speaker location are: front left, front
	177	* right and front center. */
	178	#define DEFAULT_SPEAKER_LOCATION 5
	179
	180	#define DC_MAX_AUDIO_DESC_COUNT 16
	181
	182	#define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20
	183
50e27654 ZF	184	union display_content_support {
	185	unsigned int raw;
	186	struct {
	187	unsigned int valid_content_type :1;
	188	unsigned int game_content :1;
	189	unsigned int cinema_content :1;
	190	unsigned int photo_content :1;
	191	unsigned int graphics_content :1;
	192	unsigned int reserved :27;
	193	} bits;
	194	};
	195
243c46c5	196	struct dc_panel_patch {
b686ee20	197	unsigned int dppowerup_delay;
243c46c5 JB	198	};
243c46c5 JB	199
4562236b HW	200	struct dc_edid_caps {
	201	/* sink identification */
	202	uint16_t manufacturer_id;
	203	uint16_t product_id;
	204	uint32_t serial_number;
	205	uint8_t manufacture_week;
	206	uint8_t manufacture_year;
	207	uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
	208
	209	/* audio caps */
	210	uint8_t speaker_flags;
	211	uint32_t audio_mode_count;
	212	struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT];
	213	uint32_t audio_latency;
	214	uint32_t video_latency;
	215
50e27654 ZF	216	union display_content_support content_support;
	217
	218	uint8_t qs_bit;
	219	uint8_t qy_bit;
	220
4562236b HW	221	/HDMI 2.0 caps/
	222	bool lte_340mcsc_scramble;
	223
	224	bool edid_hdmi;
506ab334	225	bool hdr_supported;
243c46c5 JB	226
243c46c5 JB	227	struct dc_panel_patch panel_patch;
4562236b HW	228	};
	229
	230	struct view {
	231	uint32_t width;
	232	uint32_t height;
	233	};
	234
	235	struct dc_mode_flags {
	236	/* note: part of refresh rate flag*/
	237	uint32_t INTERLACE :1;
	238	/* native display timing*/
	239	uint32_t NATIVE :1;
	240	/* preferred is the recommended mode, one per display */
	241	uint32_t PREFERRED :1;
	242	/* true if this mode should use reduced blanking timings
	243	_not_ related to the Reduced Blanking adjustment/
	244	uint32_t REDUCED_BLANKING :1;
	245	/* note: part of refreshrate flag*/
	246	uint32_t VIDEO_OPTIMIZED_RATE :1;
	247	/* should be reported to upper layers as mode_flags*/
	248	uint32_t PACKED_PIXEL_FORMAT :1;
	249	/< preferred view/
	250	uint32_t PREFERRED_VIEW :1;
	251	/* this timing should be used only in tiled mode*/
	252	uint32_t TILED_MODE :1;
	253	uint32_t DSE_MODE :1;
	254	/* Refresh rate divider when Miracast sink is using a
	255	different rate than the output display device
	256	Must be zero for wired displays and non-zero for
	257	Miracast displays*/
	258	uint32_t MIRACAST_REFRESH_DIVIDER;
	259	};
	260
	261
	262	enum dc_timing_source {
	263	TIMING_SOURCE_UNDEFINED,
	264
	265	/* explicitly specifed by user, most important*/
	266	TIMING_SOURCE_USER_FORCED,
	267	TIMING_SOURCE_USER_OVERRIDE,
	268	TIMING_SOURCE_CUSTOM,
	269	TIMING_SOURCE_EXPLICIT,
	270
	271	/* explicitly specified by the display device, more important*/
	272	TIMING_SOURCE_EDID_CEA_SVD_3D,
	273	TIMING_SOURCE_EDID_CEA_SVD_PREFERRED,
	274	TIMING_SOURCE_EDID_CEA_SVD_420,
	275	TIMING_SOURCE_EDID_DETAILED,
	276	TIMING_SOURCE_EDID_ESTABLISHED,
	277	TIMING_SOURCE_EDID_STANDARD,
	278	TIMING_SOURCE_EDID_CEA_SVD,
	279	TIMING_SOURCE_EDID_CVT_3BYTE,
	280	TIMING_SOURCE_EDID_4BYTE,
	281	TIMING_SOURCE_VBIOS,
	282	TIMING_SOURCE_CV,
	283	TIMING_SOURCE_TV,
	284	TIMING_SOURCE_HDMI_VIC,
	285
	286	/* implicitly specified by display device, still safe but less important*/
	287	TIMING_SOURCE_DEFAULT,
	288
	289	/* only used for custom base modes */
	290	TIMING_SOURCE_CUSTOM_BASE,
	291
292	/* these timing might not work, least important*/
293	TIMING_SOURCE_RANGELIMIT,
294	TIMING_SOURCE_OS_FORCED,
295	TIMING_SOURCE_IMPLICIT,
296
297	/* only used by default mode list*/
298	TIMING_SOURCE_BASICMODE,
299
300	TIMING_SOURCE_COUNT
301	};
302
b6d6103b VP	303
	304	struct stereo_3d_features {
	305	bool supported ;
	306	bool allTimings ;
	307	bool cloneMode ;
	308	bool scaling ;
	309	bool singleFrameSWPacked;
	310	};
	311
4562236b HW	312	enum dc_timing_support_method {
	313	TIMING_SUPPORT_METHOD_UNDEFINED,
	314	TIMING_SUPPORT_METHOD_EXPLICIT,
	315	TIMING_SUPPORT_METHOD_IMPLICIT,
	316	TIMING_SUPPORT_METHOD_NATIVE
	317	};
	318
	319	struct dc_mode_info {
	320	uint32_t pixel_width;
	321	uint32_t pixel_height;
	322	uint32_t field_rate;
	323	/* Vertical refresh rate for progressive modes.
	324	* Field rate for interlaced modes.*/
	325
	326	enum dc_timing_standard timing_standard;
	327	enum dc_timing_source timing_source;
	328	struct dc_mode_flags flags;
	329	};
	330
	331	enum dc_power_state {
	332	DC_POWER_STATE_ON = 1,
	333	DC_POWER_STATE_STANDBY,
	334	DC_POWER_STATE_SUSPEND,
	335	DC_POWER_STATE_OFF
	336	};
	337
	338	/* DC PowerStates */
	339	enum dc_video_power_state {
	340	DC_VIDEO_POWER_UNSPECIFIED = 0,
	341	DC_VIDEO_POWER_ON = 1,
	342	DC_VIDEO_POWER_STANDBY,
	343	DC_VIDEO_POWER_SUSPEND,
	344	DC_VIDEO_POWER_OFF,
	345	DC_VIDEO_POWER_HIBERNATE,
	346	DC_VIDEO_POWER_SHUTDOWN,
	347	DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */
	348	DC_VIDEO_POWER_AFTER_RESET,
	349	DC_VIDEO_POWER_MAXIMUM
	350	};
	351
	352	enum dc_acpi_cm_power_state {
	353	DC_ACPI_CM_POWER_STATE_D0 = 1,
	354	DC_ACPI_CM_POWER_STATE_D1 = 2,
	355	DC_ACPI_CM_POWER_STATE_D2 = 4,
	356	DC_ACPI_CM_POWER_STATE_D3 = 8
	357	};
	358
	359	enum dc_connection_type {
	360	dc_connection_none,
	361	dc_connection_single,
	362	dc_connection_mst_branch,
	363	dc_connection_active_dongle
	364	};
	365
	366	struct dc_csc_adjustments {
	367	struct fixed31_32 contrast;
	368	struct fixed31_32 saturation;
	369	struct fixed31_32 brightness;
	370	struct fixed31_32 hue;
	371	};
	372
03f5c686 CL	373	enum dpcd_downstream_port_max_bpc {
	374	DOWN_STREAM_MAX_8BPC = 0,
	375	DOWN_STREAM_MAX_10BPC,
	376	DOWN_STREAM_MAX_12BPC,
	377	DOWN_STREAM_MAX_16BPC
	378	};
	379	struct dc_dongle_caps {
	380	/* dongle type (DP converter, CV smart dongle) */
	381	enum display_dongle_type dongle_type;
	382	bool extendedCapValid;
	383	/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
	384	indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
	385	bool is_dp_hdmi_s3d_converter;
	386	bool is_dp_hdmi_ycbcr422_pass_through;
	387	bool is_dp_hdmi_ycbcr420_pass_through;
	388	bool is_dp_hdmi_ycbcr422_converter;
	389	bool is_dp_hdmi_ycbcr420_converter;
	390	uint32_t dp_hdmi_max_bpc;
	391	uint32_t dp_hdmi_max_pixel_clk;
	392	};
4562236b HW	393	/* Scaling format */
	394	enum scaling_transformation {
	395	SCALING_TRANSFORMATION_UNINITIALIZED,
	396	SCALING_TRANSFORMATION_IDENTITY = 0x0001,
	397	SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002,
	398	SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004,
	399	SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008,
	400	SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010,
	401	SCALING_TRANSFORMATION_INVALID = 0x80000000,
	402
	403	/* Flag the first and last */
	404	SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY,
	405	SCALING_TRANSFORMATION_END =
	406	SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
	407	};
	408
50e27654 ZF	409	enum display_content_type {
	410	DISPLAY_CONTENT_TYPE_NO_DATA = 0,
	411	DISPLAY_CONTENT_TYPE_GRAPHICS = 1,
	412	DISPLAY_CONTENT_TYPE_PHOTO = 2,
	413	DISPLAY_CONTENT_TYPE_CINEMA = 4,
	414	DISPLAY_CONTENT_TYPE_GAME = 8
	415	};
	416
4562236b HW	417	/* audio*/
	418
	419	union audio_sample_rates {
	420	struct sample_rates {
	421	uint8_t RATE_32:1;
	422	uint8_t RATE_44_1:1;
	423	uint8_t RATE_48:1;
	424	uint8_t RATE_88_2:1;
	425	uint8_t RATE_96:1;
	426	uint8_t RATE_176_4:1;
	427	uint8_t RATE_192:1;
	428	} rate;
	429
	430	uint8_t all;
	431	};
	432
	433	struct audio_speaker_flags {
5667ff5c DA	434	uint32_t FL_FR:1;
	435	uint32_t LFE:1;
	436	uint32_t FC:1;
	437	uint32_t RL_RR:1;
	438	uint32_t RC:1;
	439	uint32_t FLC_FRC:1;
	440	uint32_t RLC_RRC:1;
	441	uint32_t SUPPORT_AI:1;
4562236b HW	442	};
	443
	444	struct audio_speaker_info {
	445	uint32_t ALLSPEAKERS:7;
	446	uint32_t SUPPORT_AI:1;
	447	};
	448
	449
	450	struct audio_info_flags {
	451
	452	union {
	453
	454	struct audio_speaker_flags speaker_flags;
	455	struct audio_speaker_info info;
	456
	457	uint8_t all;
	458	};
	459	};
	460
	461	enum audio_format_code {
	462	AUDIO_FORMAT_CODE_FIRST = 1,
	463	AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST,
	464
	465	AUDIO_FORMAT_CODE_AC3,
	466	/Layers 1 & 2 /
	467	AUDIO_FORMAT_CODE_MPEG1,
	468	/MPEG1 Layer 3 /
	469	AUDIO_FORMAT_CODE_MP3,
	470	/multichannel /
	471	AUDIO_FORMAT_CODE_MPEG2,
	472	AUDIO_FORMAT_CODE_AAC,
	473	AUDIO_FORMAT_CODE_DTS,
	474	AUDIO_FORMAT_CODE_ATRAC,
	475	AUDIO_FORMAT_CODE_1BITAUDIO,
	476	AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS,
	477	AUDIO_FORMAT_CODE_DTS_HD,
	478	AUDIO_FORMAT_CODE_MAT_MLP,
	479	AUDIO_FORMAT_CODE_DST,
	480	AUDIO_FORMAT_CODE_WMAPRO,
	481	AUDIO_FORMAT_CODE_LAST,
	482	AUDIO_FORMAT_CODE_COUNT =
	483	AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST
	484	};
	485
	486	struct audio_mode {
	487	/* ucData[0] [6:3] */
	488	enum audio_format_code format_code;
	489	/* ucData[0] [2:0] */
	490	uint8_t channel_count;
	491	/* ucData[1] */
	492	union audio_sample_rates sample_rates;
	493	union {
	494	/* for LPCM */
	495	uint8_t sample_size;
	496	/* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */
	497	uint8_t max_bit_rate;
	498	/* for Audio Formats 9-15 */
	499	uint8_t vendor_specific;
	500	};
	501	};
	502
	503	struct audio_info {
	504	struct audio_info_flags flags;
	505	uint32_t video_latency;
506	uint32_t audio_latency;
507	uint32_t display_index;
508	uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
509	uint32_t manufacture_id;
510	uint32_t product_id;
511	/* PortID used for ContainerID when defined */
512	uint32_t port_id[2];
513	uint32_t mode_count;
514	/* this field must be last in this struct */
515	struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT];
516	};
517
64ed6a2e AK	518	struct vrr_params {
	519	enum vrr_state state;
	520	uint32_t window_min;
	521	uint32_t window_max;
	522	uint32_t inserted_frame_duration_in_us;
	523	uint32_t frames_to_insert;
	524	uint32_t frame_counter;
	525	};
	526
e09b6473 AK	527	struct dc_info_packet {
	528	bool valid;
	529	uint8_t hb0;
	530	uint8_t hb1;
	531	uint8_t hb2;
	532	uint8_t hb3;
	533	uint8_t sb[32];
	534	};
	535
64ed6a2e AK	536	#define DC_PLANE_UPDATE_TIMES_MAX 10
	537
	538	struct dc_plane_flip_time {
	539	unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX];
	540	unsigned int index;
	541	unsigned int prev_update_time_in_us;
	542	};
	543
	544	// Will combine with vrr_params at some point.
4562236b HW	545	struct freesync_context {
	546	bool supported;
	547	bool enabled;
	548	bool active;
	549
	550	unsigned int min_refresh_in_micro_hz;
	551	unsigned int nominal_refresh_in_micro_hz;
	552	};
	553
94267b3d ST	554	struct psr_config {
	555	unsigned char psr_version;
	556	unsigned int psr_rfb_setup_time;
	557	bool psr_exit_link_training_required;
	558
	559	bool psr_frame_capture_indication_req;
	560	unsigned int psr_sdp_transmit_line_num_deadline;
	561	};
	562
9f72f51d AZ	563	union dmcu_psr_level {
	564	struct {
	565	unsigned int SKIP_CRC:1;
	566	unsigned int SKIP_DP_VID_STREAM_DISABLE:1;
	567	unsigned int SKIP_PHY_POWER_DOWN:1;
	568	unsigned int SKIP_AUX_ACK_CHECK:1;
	569	unsigned int SKIP_CRTC_DISABLE:1;
	570	unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1;
	571	unsigned int SKIP_SMU_NOTIFICATION:1;
	572	unsigned int SKIP_AUTO_STATE_ADVANCE:1;
	573	unsigned int DISABLE_PSR_ENTRY_ABORT:1;
ee356d8f CL	574	unsigned int SKIP_SINGLE_OTG_DISABLE:1;
ee356d8f CL	575	unsigned int RESERVED:22;
9f72f51d AZ	576	} bits;
	577	unsigned int u32all;
	578	};
	579
	580	enum physical_phy_id {
	581	PHYLD_0,
	582	PHYLD_1,
	583	PHYLD_2,
	584	PHYLD_3,
	585	PHYLD_4,
	586	PHYLD_5,
	587	PHYLD_6,
	588	PHYLD_7,
	589	PHYLD_8,
	590	PHYLD_9,
	591	PHYLD_COUNT,
	592	PHYLD_UNKNOWN = (-1L)
	593	};
	594
	595	enum phy_type {
	596	PHY_TYPE_UNKNOWN = 1,
	597	PHY_TYPE_PCIE_PHY = 2,
	598	PHY_TYPE_UNIPHY = 3,
	599	};
	600
	601	struct psr_context {
	602	/* ddc line */
	603	enum channel_id channel;
	604	/* Transmitter id */
	605	enum transmitter transmitterId;
	606	/* Engine Id is used for Dig Be source select */
	607	enum engine_id engineId;
	608	/* Controller Id used for Dig Fe source select */
	609	enum controller_id controllerId;
	610	/* Pcie or Uniphy */
	611	enum phy_type phyType;
	612	/* Physical PHY Id used by SMU interpretation */
	613	enum physical_phy_id smuPhyId;
	614	/* Vertical total pixels from crtc timing.
	615	* This is used for static screen detection.
	616	* ie. If we want to detect half a frame,
	617	* we use this to determine the hyst lines.
	618	*/
	619	unsigned int crtcTimingVerticalTotal;
	620	/* PSR supported from panel capabilities and
	621	* current display configuration
	622	*/
	623	bool psrSupportedDisplayConfig;
	624	/* Whether fast link training is supported by the panel */
	625	bool psrExitLinkTrainingRequired;
	626	/* If RFB setup time is greater than the total VBLANK time,
	627	* it is not possible for the sink to capture the video frame
	628	* in the same frame the SDP is sent. In this case,
	629	* the frame capture indication bit should be set and an extra
	630	* static frame should be transmitted to the sink.
	631	*/
	632	bool psrFrameCaptureIndicationReq;
	633	/* Set the last possible line SDP may be transmitted without violating
	634	* the RFB setup time or entering the active video frame.
	635	*/
	636	unsigned int sdpTransmitLineNumDeadline;
	637	/* The VSync rate in Hz used to calculate the
	638	* step size for smooth brightness feature
	639	*/
640	unsigned int vsyncRateHz;
641	unsigned int skipPsrWaitForPllLock;
642	unsigned int numberOfControllers;
643	/* Unused, for future use. To indicate that first changed frame from
644	* state3 shouldn't result in psr_inactive, but rather to perform
645	* an automatic single frame rfb_update.
646	*/
647	bool rfb_update_auto_en;
648	/* Number of frame before entering static screen */
649	unsigned int timehyst_frames;
650	/* Partial frames before entering static screen */
651	unsigned int hyst_lines;
652	/* # of repeated AUX transaction attempts to make before
653	* indicating failure to the driver
654	*/
655	unsigned int aux_repeats;
656	/* Controls hw blocks to power down during PSR active state */
657	union dmcu_psr_level psr_level;
658	/* Controls additional delay after remote frame capture before
659	* continuing powerd own
660	*/
661	unsigned int frame_delay;
662	};
663
4562236b HW	664	struct colorspace_transform {
	665	struct fixed31_32 matrix[12];
	666	bool enable_remap;
	667	};
	668
7c7f5b15 AG	669	enum i2c_mot_mode {
	670	I2C_MOT_UNDEF,
	671	I2C_MOT_TRUE,
	672	I2C_MOT_FALSE
	673	};
	674
4562236b	675	#endif /* DC_TYPES_H_ */