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4562236b HW |
1 | /* |
2 | * Copyright 2012-15 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | #ifndef DC_TYPES_H_ | |
26 | #define DC_TYPES_H_ | |
27 | ||
28 | #include "fixed32_32.h" | |
29 | #include "fixed31_32.h" | |
30 | #include "irq_types.h" | |
31 | #include "dc_dp_types.h" | |
32 | #include "dc_hw_types.h" | |
33 | #include "dal_types.h" | |
9f72f51d | 34 | #include "grph_object_defs.h" |
4562236b HW |
35 | |
36 | /* forward declarations */ | |
c9614aeb | 37 | struct dc_plane_state; |
4562236b HW |
38 | struct dc_stream; |
39 | struct dc_link; | |
40 | struct dc_sink; | |
41 | struct dal; | |
42 | ||
43 | /******************************** | |
44 | * Environment definitions | |
45 | ********************************/ | |
46 | enum dce_environment { | |
47 | DCE_ENV_PRODUCTION_DRV = 0, | |
48 | /* Emulation on FPGA, in "Maximus" System. | |
49 | * This environment enforces that *only* DC registers accessed. | |
50 | * (access to non-DC registers will hang FPGA) */ | |
51 | DCE_ENV_FPGA_MAXIMUS, | |
52 | /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces | |
53 | * requirements of Diagnostics team. */ | |
54 | DCE_ENV_DIAG | |
55 | }; | |
56 | ||
57 | /* Note: use these macro definitions instead of direct comparison! */ | |
58 | #define IS_FPGA_MAXIMUS_DC(dce_environment) \ | |
59 | (dce_environment == DCE_ENV_FPGA_MAXIMUS) | |
60 | ||
61 | #define IS_DIAG_DC(dce_environment) \ | |
62 | (IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG)) | |
63 | ||
64 | struct hw_asic_id { | |
65 | uint32_t chip_id; | |
66 | uint32_t chip_family; | |
67 | uint32_t pci_revision_id; | |
68 | uint32_t hw_internal_rev; | |
69 | uint32_t vram_type; | |
70 | uint32_t vram_width; | |
71 | uint32_t feature_flags; | |
72 | uint32_t fake_paths_num; | |
73 | void *atombios_base_address; | |
74 | }; | |
75 | ||
76 | struct dc_context { | |
77 | struct dc *dc; | |
78 | ||
79 | void *driver_context; /* e.g. amdgpu_device */ | |
80 | ||
81 | struct dal_logger *logger; | |
82 | void *cgs_device; | |
83 | ||
84 | enum dce_environment dce_environment; | |
85 | struct hw_asic_id asic_id; | |
86 | ||
87 | /* todo: below should probably move to dc. to facilitate removal | |
88 | * of AS we will store these here | |
89 | */ | |
90 | enum dce_version dce_version; | |
91 | struct dc_bios *dc_bios; | |
92 | bool created_bios; | |
93 | struct gpio_service *gpio_service; | |
94 | struct i2caux *i2caux; | |
690b5e39 RL |
95 | #ifdef ENABLE_FBC |
96 | uint64_t fbc_gpu_addr; | |
97 | #endif | |
4562236b HW |
98 | }; |
99 | ||
100 | ||
101 | #define MAX_EDID_BUFFER_SIZE 512 | |
102 | #define EDID_BLOCK_SIZE 128 | |
ba326a91 | 103 | #define MAX_SURFACE_NUM 4 |
4562236b HW |
104 | #define NUM_PIXEL_FORMATS 10 |
105 | ||
106 | #include "dc_ddc_types.h" | |
107 | ||
108 | enum tiling_mode { | |
109 | TILING_MODE_INVALID, | |
110 | TILING_MODE_LINEAR, | |
111 | TILING_MODE_TILED, | |
112 | TILING_MODE_COUNT | |
113 | }; | |
114 | ||
115 | enum view_3d_format { | |
116 | VIEW_3D_FORMAT_NONE = 0, | |
117 | VIEW_3D_FORMAT_FRAME_SEQUENTIAL, | |
118 | VIEW_3D_FORMAT_SIDE_BY_SIDE, | |
119 | VIEW_3D_FORMAT_TOP_AND_BOTTOM, | |
120 | VIEW_3D_FORMAT_COUNT, | |
121 | VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL | |
122 | }; | |
123 | ||
124 | enum plane_stereo_format { | |
125 | PLANE_STEREO_FORMAT_NONE = 0, | |
126 | PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1, | |
127 | PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2, | |
128 | PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3, | |
129 | PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5, | |
130 | PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6, | |
131 | PLANE_STEREO_FORMAT_CHECKER_BOARD = 7 | |
132 | }; | |
133 | ||
134 | /* TODO: Find way to calculate number of bits | |
135 | * Please increase if pixel_format enum increases | |
136 | * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32 | |
137 | */ | |
138 | ||
139 | enum dc_edid_connector_type { | |
140 | EDID_CONNECTOR_UNKNOWN = 0, | |
141 | EDID_CONNECTOR_ANALOG = 1, | |
142 | EDID_CONNECTOR_DIGITAL = 10, | |
143 | EDID_CONNECTOR_DVI = 11, | |
144 | EDID_CONNECTOR_HDMIA = 12, | |
145 | EDID_CONNECTOR_MDDI = 14, | |
146 | EDID_CONNECTOR_DISPLAYPORT = 15 | |
147 | }; | |
148 | ||
149 | enum dc_edid_status { | |
150 | EDID_OK, | |
151 | EDID_BAD_INPUT, | |
152 | EDID_NO_RESPONSE, | |
153 | EDID_BAD_CHECKSUM, | |
154 | }; | |
155 | ||
156 | /* audio capability from EDID*/ | |
157 | struct dc_cea_audio_mode { | |
158 | uint8_t format_code; /* ucData[0] [6:3]*/ | |
159 | uint8_t channel_count; /* ucData[0] [2:0]*/ | |
160 | uint8_t sample_rate; /* ucData[1]*/ | |
161 | union { | |
162 | uint8_t sample_size; /* for LPCM*/ | |
163 | /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/ | |
164 | uint8_t max_bit_rate; | |
165 | uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/ | |
166 | }; | |
167 | }; | |
168 | ||
169 | struct dc_edid { | |
170 | uint32_t length; | |
171 | uint8_t raw_edid[MAX_EDID_BUFFER_SIZE]; | |
172 | }; | |
173 | ||
174 | /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION | |
175 | * is used. In this case we assume speaker location are: front left, front | |
176 | * right and front center. */ | |
177 | #define DEFAULT_SPEAKER_LOCATION 5 | |
178 | ||
179 | #define DC_MAX_AUDIO_DESC_COUNT 16 | |
180 | ||
181 | #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20 | |
182 | ||
50e27654 ZF |
183 | union display_content_support { |
184 | unsigned int raw; | |
185 | struct { | |
186 | unsigned int valid_content_type :1; | |
187 | unsigned int game_content :1; | |
188 | unsigned int cinema_content :1; | |
189 | unsigned int photo_content :1; | |
190 | unsigned int graphics_content :1; | |
191 | unsigned int reserved :27; | |
192 | } bits; | |
193 | }; | |
194 | ||
4562236b HW |
195 | struct dc_edid_caps { |
196 | /* sink identification */ | |
197 | uint16_t manufacturer_id; | |
198 | uint16_t product_id; | |
199 | uint32_t serial_number; | |
200 | uint8_t manufacture_week; | |
201 | uint8_t manufacture_year; | |
202 | uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; | |
203 | ||
204 | /* audio caps */ | |
205 | uint8_t speaker_flags; | |
206 | uint32_t audio_mode_count; | |
207 | struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT]; | |
208 | uint32_t audio_latency; | |
209 | uint32_t video_latency; | |
210 | ||
50e27654 ZF |
211 | union display_content_support content_support; |
212 | ||
213 | uint8_t qs_bit; | |
214 | uint8_t qy_bit; | |
215 | ||
4562236b HW |
216 | /*HDMI 2.0 caps*/ |
217 | bool lte_340mcsc_scramble; | |
218 | ||
219 | bool edid_hdmi; | |
220 | }; | |
221 | ||
222 | struct view { | |
223 | uint32_t width; | |
224 | uint32_t height; | |
225 | }; | |
226 | ||
227 | struct dc_mode_flags { | |
228 | /* note: part of refresh rate flag*/ | |
229 | uint32_t INTERLACE :1; | |
230 | /* native display timing*/ | |
231 | uint32_t NATIVE :1; | |
232 | /* preferred is the recommended mode, one per display */ | |
233 | uint32_t PREFERRED :1; | |
234 | /* true if this mode should use reduced blanking timings | |
235 | *_not_ related to the Reduced Blanking adjustment*/ | |
236 | uint32_t REDUCED_BLANKING :1; | |
237 | /* note: part of refreshrate flag*/ | |
238 | uint32_t VIDEO_OPTIMIZED_RATE :1; | |
239 | /* should be reported to upper layers as mode_flags*/ | |
240 | uint32_t PACKED_PIXEL_FORMAT :1; | |
241 | /*< preferred view*/ | |
242 | uint32_t PREFERRED_VIEW :1; | |
243 | /* this timing should be used only in tiled mode*/ | |
244 | uint32_t TILED_MODE :1; | |
245 | uint32_t DSE_MODE :1; | |
246 | /* Refresh rate divider when Miracast sink is using a | |
247 | different rate than the output display device | |
248 | Must be zero for wired displays and non-zero for | |
249 | Miracast displays*/ | |
250 | uint32_t MIRACAST_REFRESH_DIVIDER; | |
251 | }; | |
252 | ||
253 | ||
254 | enum dc_timing_source { | |
255 | TIMING_SOURCE_UNDEFINED, | |
256 | ||
257 | /* explicitly specifed by user, most important*/ | |
258 | TIMING_SOURCE_USER_FORCED, | |
259 | TIMING_SOURCE_USER_OVERRIDE, | |
260 | TIMING_SOURCE_CUSTOM, | |
261 | TIMING_SOURCE_EXPLICIT, | |
262 | ||
263 | /* explicitly specified by the display device, more important*/ | |
264 | TIMING_SOURCE_EDID_CEA_SVD_3D, | |
265 | TIMING_SOURCE_EDID_CEA_SVD_PREFERRED, | |
266 | TIMING_SOURCE_EDID_CEA_SVD_420, | |
267 | TIMING_SOURCE_EDID_DETAILED, | |
268 | TIMING_SOURCE_EDID_ESTABLISHED, | |
269 | TIMING_SOURCE_EDID_STANDARD, | |
270 | TIMING_SOURCE_EDID_CEA_SVD, | |
271 | TIMING_SOURCE_EDID_CVT_3BYTE, | |
272 | TIMING_SOURCE_EDID_4BYTE, | |
273 | TIMING_SOURCE_VBIOS, | |
274 | TIMING_SOURCE_CV, | |
275 | TIMING_SOURCE_TV, | |
276 | TIMING_SOURCE_HDMI_VIC, | |
277 | ||
278 | /* implicitly specified by display device, still safe but less important*/ | |
279 | TIMING_SOURCE_DEFAULT, | |
280 | ||
281 | /* only used for custom base modes */ | |
282 | TIMING_SOURCE_CUSTOM_BASE, | |
283 | ||
284 | /* these timing might not work, least important*/ | |
285 | TIMING_SOURCE_RANGELIMIT, | |
286 | TIMING_SOURCE_OS_FORCED, | |
287 | TIMING_SOURCE_IMPLICIT, | |
288 | ||
289 | /* only used by default mode list*/ | |
290 | TIMING_SOURCE_BASICMODE, | |
291 | ||
292 | TIMING_SOURCE_COUNT | |
293 | }; | |
294 | ||
b6d6103b VP |
295 | |
296 | struct stereo_3d_features { | |
297 | bool supported ; | |
298 | bool allTimings ; | |
299 | bool cloneMode ; | |
300 | bool scaling ; | |
301 | bool singleFrameSWPacked; | |
302 | }; | |
303 | ||
4562236b HW |
304 | enum dc_timing_support_method { |
305 | TIMING_SUPPORT_METHOD_UNDEFINED, | |
306 | TIMING_SUPPORT_METHOD_EXPLICIT, | |
307 | TIMING_SUPPORT_METHOD_IMPLICIT, | |
308 | TIMING_SUPPORT_METHOD_NATIVE | |
309 | }; | |
310 | ||
311 | struct dc_mode_info { | |
312 | uint32_t pixel_width; | |
313 | uint32_t pixel_height; | |
314 | uint32_t field_rate; | |
315 | /* Vertical refresh rate for progressive modes. | |
316 | * Field rate for interlaced modes.*/ | |
317 | ||
318 | enum dc_timing_standard timing_standard; | |
319 | enum dc_timing_source timing_source; | |
320 | struct dc_mode_flags flags; | |
321 | }; | |
322 | ||
323 | enum dc_power_state { | |
324 | DC_POWER_STATE_ON = 1, | |
325 | DC_POWER_STATE_STANDBY, | |
326 | DC_POWER_STATE_SUSPEND, | |
327 | DC_POWER_STATE_OFF | |
328 | }; | |
329 | ||
330 | /* DC PowerStates */ | |
331 | enum dc_video_power_state { | |
332 | DC_VIDEO_POWER_UNSPECIFIED = 0, | |
333 | DC_VIDEO_POWER_ON = 1, | |
334 | DC_VIDEO_POWER_STANDBY, | |
335 | DC_VIDEO_POWER_SUSPEND, | |
336 | DC_VIDEO_POWER_OFF, | |
337 | DC_VIDEO_POWER_HIBERNATE, | |
338 | DC_VIDEO_POWER_SHUTDOWN, | |
339 | DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */ | |
340 | DC_VIDEO_POWER_AFTER_RESET, | |
341 | DC_VIDEO_POWER_MAXIMUM | |
342 | }; | |
343 | ||
344 | enum dc_acpi_cm_power_state { | |
345 | DC_ACPI_CM_POWER_STATE_D0 = 1, | |
346 | DC_ACPI_CM_POWER_STATE_D1 = 2, | |
347 | DC_ACPI_CM_POWER_STATE_D2 = 4, | |
348 | DC_ACPI_CM_POWER_STATE_D3 = 8 | |
349 | }; | |
350 | ||
351 | enum dc_connection_type { | |
352 | dc_connection_none, | |
353 | dc_connection_single, | |
354 | dc_connection_mst_branch, | |
355 | dc_connection_active_dongle | |
356 | }; | |
357 | ||
358 | struct dc_csc_adjustments { | |
359 | struct fixed31_32 contrast; | |
360 | struct fixed31_32 saturation; | |
361 | struct fixed31_32 brightness; | |
362 | struct fixed31_32 hue; | |
363 | }; | |
364 | ||
365 | enum { | |
366 | MAX_LANES = 2, | |
367 | MAX_COFUNC_PATH = 6, | |
368 | LAYER_INDEX_PRIMARY = -1, | |
369 | }; | |
370 | ||
03f5c686 CL |
371 | enum dpcd_downstream_port_max_bpc { |
372 | DOWN_STREAM_MAX_8BPC = 0, | |
373 | DOWN_STREAM_MAX_10BPC, | |
374 | DOWN_STREAM_MAX_12BPC, | |
375 | DOWN_STREAM_MAX_16BPC | |
376 | }; | |
377 | struct dc_dongle_caps { | |
378 | /* dongle type (DP converter, CV smart dongle) */ | |
379 | enum display_dongle_type dongle_type; | |
380 | bool extendedCapValid; | |
381 | /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, | |
382 | indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ | |
383 | bool is_dp_hdmi_s3d_converter; | |
384 | bool is_dp_hdmi_ycbcr422_pass_through; | |
385 | bool is_dp_hdmi_ycbcr420_pass_through; | |
386 | bool is_dp_hdmi_ycbcr422_converter; | |
387 | bool is_dp_hdmi_ycbcr420_converter; | |
388 | uint32_t dp_hdmi_max_bpc; | |
389 | uint32_t dp_hdmi_max_pixel_clk; | |
390 | }; | |
4562236b HW |
391 | /* Scaling format */ |
392 | enum scaling_transformation { | |
393 | SCALING_TRANSFORMATION_UNINITIALIZED, | |
394 | SCALING_TRANSFORMATION_IDENTITY = 0x0001, | |
395 | SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002, | |
396 | SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004, | |
397 | SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008, | |
398 | SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010, | |
399 | SCALING_TRANSFORMATION_INVALID = 0x80000000, | |
400 | ||
401 | /* Flag the first and last */ | |
402 | SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY, | |
403 | SCALING_TRANSFORMATION_END = | |
404 | SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE | |
405 | }; | |
406 | ||
50e27654 ZF |
407 | enum display_content_type { |
408 | DISPLAY_CONTENT_TYPE_NO_DATA = 0, | |
409 | DISPLAY_CONTENT_TYPE_GRAPHICS = 1, | |
410 | DISPLAY_CONTENT_TYPE_PHOTO = 2, | |
411 | DISPLAY_CONTENT_TYPE_CINEMA = 4, | |
412 | DISPLAY_CONTENT_TYPE_GAME = 8 | |
413 | }; | |
414 | ||
4562236b HW |
415 | /* audio*/ |
416 | ||
417 | union audio_sample_rates { | |
418 | struct sample_rates { | |
419 | uint8_t RATE_32:1; | |
420 | uint8_t RATE_44_1:1; | |
421 | uint8_t RATE_48:1; | |
422 | uint8_t RATE_88_2:1; | |
423 | uint8_t RATE_96:1; | |
424 | uint8_t RATE_176_4:1; | |
425 | uint8_t RATE_192:1; | |
426 | } rate; | |
427 | ||
428 | uint8_t all; | |
429 | }; | |
430 | ||
431 | struct audio_speaker_flags { | |
432 | uint32_t FL_FR:1; | |
433 | uint32_t LFE:1; | |
434 | uint32_t FC:1; | |
435 | uint32_t RL_RR:1; | |
436 | uint32_t RC:1; | |
437 | uint32_t FLC_FRC:1; | |
438 | uint32_t RLC_RRC:1; | |
439 | uint32_t SUPPORT_AI:1; | |
440 | }; | |
441 | ||
442 | struct audio_speaker_info { | |
443 | uint32_t ALLSPEAKERS:7; | |
444 | uint32_t SUPPORT_AI:1; | |
445 | }; | |
446 | ||
447 | ||
448 | struct audio_info_flags { | |
449 | ||
450 | union { | |
451 | ||
452 | struct audio_speaker_flags speaker_flags; | |
453 | struct audio_speaker_info info; | |
454 | ||
455 | uint8_t all; | |
456 | }; | |
457 | }; | |
458 | ||
459 | enum audio_format_code { | |
460 | AUDIO_FORMAT_CODE_FIRST = 1, | |
461 | AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST, | |
462 | ||
463 | AUDIO_FORMAT_CODE_AC3, | |
464 | /*Layers 1 & 2 */ | |
465 | AUDIO_FORMAT_CODE_MPEG1, | |
466 | /*MPEG1 Layer 3 */ | |
467 | AUDIO_FORMAT_CODE_MP3, | |
468 | /*multichannel */ | |
469 | AUDIO_FORMAT_CODE_MPEG2, | |
470 | AUDIO_FORMAT_CODE_AAC, | |
471 | AUDIO_FORMAT_CODE_DTS, | |
472 | AUDIO_FORMAT_CODE_ATRAC, | |
473 | AUDIO_FORMAT_CODE_1BITAUDIO, | |
474 | AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS, | |
475 | AUDIO_FORMAT_CODE_DTS_HD, | |
476 | AUDIO_FORMAT_CODE_MAT_MLP, | |
477 | AUDIO_FORMAT_CODE_DST, | |
478 | AUDIO_FORMAT_CODE_WMAPRO, | |
479 | AUDIO_FORMAT_CODE_LAST, | |
480 | AUDIO_FORMAT_CODE_COUNT = | |
481 | AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST | |
482 | }; | |
483 | ||
484 | struct audio_mode { | |
485 | /* ucData[0] [6:3] */ | |
486 | enum audio_format_code format_code; | |
487 | /* ucData[0] [2:0] */ | |
488 | uint8_t channel_count; | |
489 | /* ucData[1] */ | |
490 | union audio_sample_rates sample_rates; | |
491 | union { | |
492 | /* for LPCM */ | |
493 | uint8_t sample_size; | |
494 | /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */ | |
495 | uint8_t max_bit_rate; | |
496 | /* for Audio Formats 9-15 */ | |
497 | uint8_t vendor_specific; | |
498 | }; | |
499 | }; | |
500 | ||
501 | struct audio_info { | |
502 | struct audio_info_flags flags; | |
503 | uint32_t video_latency; | |
504 | uint32_t audio_latency; | |
505 | uint32_t display_index; | |
506 | uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; | |
507 | uint32_t manufacture_id; | |
508 | uint32_t product_id; | |
509 | /* PortID used for ContainerID when defined */ | |
510 | uint32_t port_id[2]; | |
511 | uint32_t mode_count; | |
512 | /* this field must be last in this struct */ | |
513 | struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT]; | |
514 | }; | |
515 | ||
516 | struct freesync_context { | |
517 | bool supported; | |
518 | bool enabled; | |
519 | bool active; | |
520 | ||
521 | unsigned int min_refresh_in_micro_hz; | |
522 | unsigned int nominal_refresh_in_micro_hz; | |
523 | }; | |
524 | ||
94267b3d ST |
525 | struct psr_config { |
526 | unsigned char psr_version; | |
527 | unsigned int psr_rfb_setup_time; | |
528 | bool psr_exit_link_training_required; | |
529 | ||
530 | bool psr_frame_capture_indication_req; | |
531 | unsigned int psr_sdp_transmit_line_num_deadline; | |
532 | }; | |
533 | ||
9f72f51d AZ |
534 | union dmcu_psr_level { |
535 | struct { | |
536 | unsigned int SKIP_CRC:1; | |
537 | unsigned int SKIP_DP_VID_STREAM_DISABLE:1; | |
538 | unsigned int SKIP_PHY_POWER_DOWN:1; | |
539 | unsigned int SKIP_AUX_ACK_CHECK:1; | |
540 | unsigned int SKIP_CRTC_DISABLE:1; | |
541 | unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1; | |
542 | unsigned int SKIP_SMU_NOTIFICATION:1; | |
543 | unsigned int SKIP_AUTO_STATE_ADVANCE:1; | |
544 | unsigned int DISABLE_PSR_ENTRY_ABORT:1; | |
ee356d8f CL |
545 | unsigned int SKIP_SINGLE_OTG_DISABLE:1; |
546 | unsigned int RESERVED:22; | |
9f72f51d AZ |
547 | } bits; |
548 | unsigned int u32all; | |
549 | }; | |
550 | ||
551 | enum physical_phy_id { | |
552 | PHYLD_0, | |
553 | PHYLD_1, | |
554 | PHYLD_2, | |
555 | PHYLD_3, | |
556 | PHYLD_4, | |
557 | PHYLD_5, | |
558 | PHYLD_6, | |
559 | PHYLD_7, | |
560 | PHYLD_8, | |
561 | PHYLD_9, | |
562 | PHYLD_COUNT, | |
563 | PHYLD_UNKNOWN = (-1L) | |
564 | }; | |
565 | ||
566 | enum phy_type { | |
567 | PHY_TYPE_UNKNOWN = 1, | |
568 | PHY_TYPE_PCIE_PHY = 2, | |
569 | PHY_TYPE_UNIPHY = 3, | |
570 | }; | |
571 | ||
572 | struct psr_context { | |
573 | /* ddc line */ | |
574 | enum channel_id channel; | |
575 | /* Transmitter id */ | |
576 | enum transmitter transmitterId; | |
577 | /* Engine Id is used for Dig Be source select */ | |
578 | enum engine_id engineId; | |
579 | /* Controller Id used for Dig Fe source select */ | |
580 | enum controller_id controllerId; | |
581 | /* Pcie or Uniphy */ | |
582 | enum phy_type phyType; | |
583 | /* Physical PHY Id used by SMU interpretation */ | |
584 | enum physical_phy_id smuPhyId; | |
585 | /* Vertical total pixels from crtc timing. | |
586 | * This is used for static screen detection. | |
587 | * ie. If we want to detect half a frame, | |
588 | * we use this to determine the hyst lines. | |
589 | */ | |
590 | unsigned int crtcTimingVerticalTotal; | |
591 | /* PSR supported from panel capabilities and | |
592 | * current display configuration | |
593 | */ | |
594 | bool psrSupportedDisplayConfig; | |
595 | /* Whether fast link training is supported by the panel */ | |
596 | bool psrExitLinkTrainingRequired; | |
597 | /* If RFB setup time is greater than the total VBLANK time, | |
598 | * it is not possible for the sink to capture the video frame | |
599 | * in the same frame the SDP is sent. In this case, | |
600 | * the frame capture indication bit should be set and an extra | |
601 | * static frame should be transmitted to the sink. | |
602 | */ | |
603 | bool psrFrameCaptureIndicationReq; | |
604 | /* Set the last possible line SDP may be transmitted without violating | |
605 | * the RFB setup time or entering the active video frame. | |
606 | */ | |
607 | unsigned int sdpTransmitLineNumDeadline; | |
608 | /* The VSync rate in Hz used to calculate the | |
609 | * step size for smooth brightness feature | |
610 | */ | |
611 | unsigned int vsyncRateHz; | |
612 | unsigned int skipPsrWaitForPllLock; | |
613 | unsigned int numberOfControllers; | |
614 | /* Unused, for future use. To indicate that first changed frame from | |
615 | * state3 shouldn't result in psr_inactive, but rather to perform | |
616 | * an automatic single frame rfb_update. | |
617 | */ | |
618 | bool rfb_update_auto_en; | |
619 | /* Number of frame before entering static screen */ | |
620 | unsigned int timehyst_frames; | |
621 | /* Partial frames before entering static screen */ | |
622 | unsigned int hyst_lines; | |
623 | /* # of repeated AUX transaction attempts to make before | |
624 | * indicating failure to the driver | |
625 | */ | |
626 | unsigned int aux_repeats; | |
627 | /* Controls hw blocks to power down during PSR active state */ | |
628 | union dmcu_psr_level psr_level; | |
629 | /* Controls additional delay after remote frame capture before | |
630 | * continuing powerd own | |
631 | */ | |
632 | unsigned int frame_delay; | |
633 | }; | |
634 | ||
4562236b HW |
635 | struct colorspace_transform { |
636 | struct fixed31_32 matrix[12]; | |
637 | bool enable_remap; | |
638 | }; | |
639 | ||
640 | struct csc_transform { | |
641 | uint16_t matrix[12]; | |
642 | bool enable_adjustment; | |
643 | }; | |
644 | ||
7c7f5b15 AG |
645 | enum i2c_mot_mode { |
646 | I2C_MOT_UNDEF, | |
647 | I2C_MOT_TRUE, | |
648 | I2C_MOT_FALSE | |
649 | }; | |
650 | ||
4562236b | 651 | #endif /* DC_TYPES_H_ */ |