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drm/amd/display: Fix MST topology debugfs
[linux-block.git] / drivers / gpu / drm / amd / display / dc / dc_types.h
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#ifndef DC_TYPES_H_
26#define DC_TYPES_H_
27
0417df16
BZ		 28/* AND EdidUtility only needs a portion
29 * of this file, including the rest only
30 * causes additional issues.
31 */
eb0e5154 32#include "os_types.h"
4562236b
HW		 33#include "fixed31_32.h"
34#include "irq_types.h"
35#include "dc_dp_types.h"
36#include "dc_hw_types.h"
37#include "dal_types.h"
9f72f51d 38#include "grph_object_defs.h"
4562236b 39
d462fcf5
BL		 40#ifdef CONFIG_DRM_AMD_DC_HDCP
41#include "dm_cp_psp.h"
42#endif
43
4562236b 44/* forward declarations */
c9614aeb 45struct dc_plane_state;
0971c40e 46struct dc_stream_state;
4562236b
HW		 47struct dc_link;
48struct dc_sink;
49struct dal;
3a1627b0 50struct dc_dmub_srv;
4562236b
HW		 51
52/********************************
53 * Environment definitions
54 ********************************/
55enum dce_environment {
56 DCE_ENV_PRODUCTION_DRV = 0,
57 /* Emulation on FPGA, in "Maximus" System.
58 * This environment enforces that *only* DC registers accessed.
59 * (access to non-DC registers will hang FPGA) */
60 DCE_ENV_FPGA_MAXIMUS,
61 /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces
62 * requirements of Diagnostics team. */
68c0fca5
JL		 63 DCE_ENV_DIAG,
64 /*
65 * Guest VM system, DC HW may exist but is not virtualized and
66 * should not be used. SW support for VDI only.
67 */
68 DCE_ENV_VIRTUAL_HW
4562236b
HW		 69};
70
71/* Note: use these macro definitions instead of direct comparison! */
72#define IS_FPGA_MAXIMUS_DC(dce_environment) \
73 (dce_environment == DCE_ENV_FPGA_MAXIMUS)
74
75#define IS_DIAG_DC(dce_environment) \
76 (IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))
77
78struct hw_asic_id {
79 uint32_t chip_id;
80 uint32_t chip_family;
81 uint32_t pci_revision_id;
82 uint32_t hw_internal_rev;
83 uint32_t vram_type;
84 uint32_t vram_width;
85 uint32_t feature_flags;
86 uint32_t fake_paths_num;
87 void *atombios_base_address;
88};
89
0cf5eb76
DF		 90struct dc_perf_trace {
91 unsigned long read_count;
92 unsigned long write_count;
93 unsigned long last_entry_read;
94 unsigned long last_entry_write;
95};
96
4562236b
HW		 97struct dc_context {
98 struct dc *dc;
99
100 void *driver_context; /* e.g. amdgpu_device */
0cf5eb76 101 struct dc_perf_trace *perf_trace;
4562236b
HW		 102 void *cgs_device;
103
104 enum dce_environment dce_environment;
105 struct hw_asic_id asic_id;
106
107 /* todo: below should probably move to dc. to facilitate removal
108 * of AS we will store these here
109 */
110 enum dce_version dce_version;
111 struct dc_bios *dc_bios;
112 bool created_bios;
113 struct gpio_service *gpio_service;
ce3f6e82 114 uint32_t dc_sink_id_count;
04a789be 115 uint32_t dc_stream_id_count;
690b5e39 116 uint64_t fbc_gpu_addr;
3a1627b0 117 struct dc_dmub_srv *dmub_srv;
2200eb9e 118
d462fcf5
BL		 119#ifdef CONFIG_DRM_AMD_DC_HDCP
120 struct cp_psp cp_psp;
121#endif
4562236b
HW		 122};
123
124
123ecf68 125#define DC_MAX_EDID_BUFFER_SIZE 1280
a634913e 126#define DC_EDID_BLOCK_SIZE 128
ba326a91 127#define MAX_SURFACE_NUM 4
4562236b 128#define NUM_PIXEL_FORMATS 10
8e5100a5 129#define MAX_REPEATER_CNT 8
4562236b
HW		 130
131#include "dc_ddc_types.h"
132
133enum tiling_mode {
134 TILING_MODE_INVALID,
135 TILING_MODE_LINEAR,
136 TILING_MODE_TILED,
137 TILING_MODE_COUNT
138};
139
140enum view_3d_format {
141 VIEW_3D_FORMAT_NONE = 0,
142 VIEW_3D_FORMAT_FRAME_SEQUENTIAL,
143 VIEW_3D_FORMAT_SIDE_BY_SIDE,
144 VIEW_3D_FORMAT_TOP_AND_BOTTOM,
145 VIEW_3D_FORMAT_COUNT,
146 VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL
147};
148
149enum plane_stereo_format {
150 PLANE_STEREO_FORMAT_NONE = 0,
151 PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1,
152 PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2,
153 PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3,
154 PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5,
155 PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6,
156 PLANE_STEREO_FORMAT_CHECKER_BOARD = 7
157};
158
159/* TODO: Find way to calculate number of bits
160 * Please increase if pixel_format enum increases
161 * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32
162 */
163
164enum dc_edid_connector_type {
8de94233
RA		 165 DC_EDID_CONNECTOR_UNKNOWN = 0,
166 DC_EDID_CONNECTOR_ANALOG = 1,
167 DC_EDID_CONNECTOR_DIGITAL = 10,
168 DC_EDID_CONNECTOR_DVI = 11,
169 DC_EDID_CONNECTOR_HDMIA = 12,
170 DC_EDID_CONNECTOR_MDDI = 14,
171 DC_EDID_CONNECTOR_DISPLAYPORT = 15
4562236b
HW		 172};
173
174enum dc_edid_status {
175 EDID_OK,
176 EDID_BAD_INPUT,
177 EDID_NO_RESPONSE,
178 EDID_BAD_CHECKSUM,
7d58e721 179 EDID_THE_SAME,
07c8176e 180 EDID_FALL_BACK,
4562236b
HW		 181};
182
48af9b91
AL		 183enum act_return_status {
184 ACT_SUCCESS,
185 ACT_LINK_LOST,
186 ACT_FAILED
187};
188
4562236b
HW		 189/* audio capability from EDID*/
190struct dc_cea_audio_mode {
191 uint8_t format_code; /* ucData[0] [6:3]*/
192 uint8_t channel_count; /* ucData[0] [2:0]*/
193 uint8_t sample_rate; /* ucData[1]*/
194 union {
195 uint8_t sample_size; /* for LPCM*/
196 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
197 uint8_t max_bit_rate;
198 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
199 };
200};
201
202struct dc_edid {
203 uint32_t length;
8de94233 204 uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE];
4562236b
HW		 205};
206
207/* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION
208 * is used. In this case we assume speaker location are: front left, front
209 * right and front center. */
210#define DEFAULT_SPEAKER_LOCATION 5
211
212#define DC_MAX_AUDIO_DESC_COUNT 16
213
214#define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20
215
50e27654
ZF		 216union display_content_support {
217 unsigned int raw;
218 struct {
219 unsigned int valid_content_type :1;
220 unsigned int game_content :1;
221 unsigned int cinema_content :1;
222 unsigned int photo_content :1;
223 unsigned int graphics_content :1;
224 unsigned int reserved :27;
225 } bits;
226};
227
243c46c5 228struct dc_panel_patch {
b686ee20 229 unsigned int dppowerup_delay;
ff587987 230 unsigned int extra_t12_ms;
a4f1d2b8 231 unsigned int extra_delay_backlight_off;
88eac241 232 unsigned int extra_t7_ms;
a760fc1b 233 unsigned int skip_scdc_overwrite;
dc326f61 234 unsigned int delay_ignore_msa;
8151306b 235 unsigned int disable_fec;
6798d042 236 unsigned int extra_t3_ms;
9abdf392 237 unsigned int max_dsc_target_bpp_limit;
74d021b5 238 unsigned int skip_avmute;
243c46c5
JB		 239};
240
4562236b
HW		 241struct dc_edid_caps {
242 /* sink identification */
243 uint16_t manufacturer_id;
244 uint16_t product_id;
245 uint32_t serial_number;
246 uint8_t manufacture_week;
247 uint8_t manufacture_year;
248 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
249
250 /* audio caps */
251 uint8_t speaker_flags;
252 uint32_t audio_mode_count;
253 struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT];
254 uint32_t audio_latency;
255 uint32_t video_latency;
256
50e27654
ZF		 257 union display_content_support content_support;
258
259 uint8_t qs_bit;
260 uint8_t qy_bit;
261
c04bd16e
DZ		 262 uint32_t max_tmds_clk_mhz;
263
4562236b
HW		 264 /*HDMI 2.0 caps*/
265 bool lte_340mcsc_scramble;
266
267 bool edid_hdmi;
506ab334 268 bool hdr_supported;
243c46c5
JB		 269
270 struct dc_panel_patch panel_patch;
4562236b
HW		 271};
272
273struct view {
274 uint32_t width;
275 uint32_t height;
276};
277
278struct dc_mode_flags {
279 /* note: part of refresh rate flag*/
280 uint32_t INTERLACE :1;
281 /* native display timing*/
282 uint32_t NATIVE :1;
283 /* preferred is the recommended mode, one per display */
284 uint32_t PREFERRED :1;
285 /* true if this mode should use reduced blanking timings
286 *_not_ related to the Reduced Blanking adjustment*/
287 uint32_t REDUCED_BLANKING :1;
288 /* note: part of refreshrate flag*/
289 uint32_t VIDEO_OPTIMIZED_RATE :1;
290 /* should be reported to upper layers as mode_flags*/
291 uint32_t PACKED_PIXEL_FORMAT :1;
292 /*< preferred view*/
293 uint32_t PREFERRED_VIEW :1;
294 /* this timing should be used only in tiled mode*/
295 uint32_t TILED_MODE :1;
296 uint32_t DSE_MODE :1;
297 /* Refresh rate divider when Miracast sink is using a
298 different rate than the output display device
299 Must be zero for wired displays and non-zero for
300 Miracast displays*/
301 uint32_t MIRACAST_REFRESH_DIVIDER;
302};
303
304
305enum dc_timing_source {
306 TIMING_SOURCE_UNDEFINED,
307
308 /* explicitly specifed by user, most important*/
309 TIMING_SOURCE_USER_FORCED,
310 TIMING_SOURCE_USER_OVERRIDE,
311 TIMING_SOURCE_CUSTOM,
312 TIMING_SOURCE_EXPLICIT,
313
314 /* explicitly specified by the display device, more important*/
315 TIMING_SOURCE_EDID_CEA_SVD_3D,
316 TIMING_SOURCE_EDID_CEA_SVD_PREFERRED,
317 TIMING_SOURCE_EDID_CEA_SVD_420,
318 TIMING_SOURCE_EDID_DETAILED,
319 TIMING_SOURCE_EDID_ESTABLISHED,
320 TIMING_SOURCE_EDID_STANDARD,
321 TIMING_SOURCE_EDID_CEA_SVD,
322 TIMING_SOURCE_EDID_CVT_3BYTE,
323 TIMING_SOURCE_EDID_4BYTE,
324 TIMING_SOURCE_VBIOS,
325 TIMING_SOURCE_CV,
326 TIMING_SOURCE_TV,
327 TIMING_SOURCE_HDMI_VIC,
328
329 /* implicitly specified by display device, still safe but less important*/
330 TIMING_SOURCE_DEFAULT,
331
332 /* only used for custom base modes */
333 TIMING_SOURCE_CUSTOM_BASE,
334
335 /* these timing might not work, least important*/
336 TIMING_SOURCE_RANGELIMIT,
337 TIMING_SOURCE_OS_FORCED,
338 TIMING_SOURCE_IMPLICIT,
339
340 /* only used by default mode list*/
341 TIMING_SOURCE_BASICMODE,
342
343 TIMING_SOURCE_COUNT
344};
345
b6d6103b
VP		 346
347struct stereo_3d_features {
348 bool supported ;
349 bool allTimings ;
350 bool cloneMode ;
351 bool scaling ;
352 bool singleFrameSWPacked;
353};
354
4562236b
HW		 355enum dc_timing_support_method {
356 TIMING_SUPPORT_METHOD_UNDEFINED,
357 TIMING_SUPPORT_METHOD_EXPLICIT,
358 TIMING_SUPPORT_METHOD_IMPLICIT,
359 TIMING_SUPPORT_METHOD_NATIVE
360};
361
362struct dc_mode_info {
363 uint32_t pixel_width;
364 uint32_t pixel_height;
365 uint32_t field_rate;
366 /* Vertical refresh rate for progressive modes.
367 * Field rate for interlaced modes.*/
368
369 enum dc_timing_standard timing_standard;
370 enum dc_timing_source timing_source;
371 struct dc_mode_flags flags;
372};
373
374enum dc_power_state {
375 DC_POWER_STATE_ON = 1,
376 DC_POWER_STATE_STANDBY,
377 DC_POWER_STATE_SUSPEND,
378 DC_POWER_STATE_OFF
379};
380
381/* DC PowerStates */
382enum dc_video_power_state {
383 DC_VIDEO_POWER_UNSPECIFIED = 0,
384 DC_VIDEO_POWER_ON = 1,
385 DC_VIDEO_POWER_STANDBY,
386 DC_VIDEO_POWER_SUSPEND,
387 DC_VIDEO_POWER_OFF,
388 DC_VIDEO_POWER_HIBERNATE,
389 DC_VIDEO_POWER_SHUTDOWN,
390 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */
391 DC_VIDEO_POWER_AFTER_RESET,
392 DC_VIDEO_POWER_MAXIMUM
393};
394
395enum dc_acpi_cm_power_state {
396 DC_ACPI_CM_POWER_STATE_D0 = 1,
397 DC_ACPI_CM_POWER_STATE_D1 = 2,
398 DC_ACPI_CM_POWER_STATE_D2 = 4,
399 DC_ACPI_CM_POWER_STATE_D3 = 8
400};
401
402enum dc_connection_type {
403 dc_connection_none,
404 dc_connection_single,
405 dc_connection_mst_branch,
406 dc_connection_active_dongle
407};
408
409struct dc_csc_adjustments {
410 struct fixed31_32 contrast;
411 struct fixed31_32 saturation;
412 struct fixed31_32 brightness;
413 struct fixed31_32 hue;
414};
415
03f5c686
CL		 416enum dpcd_downstream_port_max_bpc {
417 DOWN_STREAM_MAX_8BPC = 0,
418 DOWN_STREAM_MAX_10BPC,
419 DOWN_STREAM_MAX_12BPC,
420 DOWN_STREAM_MAX_16BPC
421};
8e5100a5 422
423
424enum link_training_offset {
425 DPRX = 0,
426 LTTPR_PHY_REPEATER1 = 1,
427 LTTPR_PHY_REPEATER2 = 2,
428 LTTPR_PHY_REPEATER3 = 3,
429 LTTPR_PHY_REPEATER4 = 4,
430 LTTPR_PHY_REPEATER5 = 5,
431 LTTPR_PHY_REPEATER6 = 6,
432 LTTPR_PHY_REPEATER7 = 7,
433 LTTPR_PHY_REPEATER8 = 8
434};
435
8e5100a5 436struct dc_lttpr_caps {
61aa7a6f 437 union dpcd_rev revision;
438 uint8_t mode;
8e5100a5 439 uint8_t max_lane_count;
440 uint8_t max_link_rate;
441 uint8_t phy_repeater_cnt;
442 uint8_t max_ext_timeout;
443 uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1];
444};
445
03f5c686
CL		 446struct dc_dongle_caps {
447 /* dongle type (DP converter, CV smart dongle) */
448 enum display_dongle_type dongle_type;
449 bool extendedCapValid;
450 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
451 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
452 bool is_dp_hdmi_s3d_converter;
453 bool is_dp_hdmi_ycbcr422_pass_through;
454 bool is_dp_hdmi_ycbcr420_pass_through;
455 bool is_dp_hdmi_ycbcr422_converter;
456 bool is_dp_hdmi_ycbcr420_converter;
457 uint32_t dp_hdmi_max_bpc;
e5490464 458 uint32_t dp_hdmi_max_pixel_clk_in_khz;
03f5c686 459};
4562236b
HW		 460/* Scaling format */
461enum scaling_transformation {
462 SCALING_TRANSFORMATION_UNINITIALIZED,
463 SCALING_TRANSFORMATION_IDENTITY = 0x0001,
464 SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002,
465 SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004,
466 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008,
467 SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010,
468 SCALING_TRANSFORMATION_INVALID = 0x80000000,
469
470 /* Flag the first and last */
471 SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY,
472 SCALING_TRANSFORMATION_END =
473 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
474};
475
50e27654
ZF		 476enum display_content_type {
477 DISPLAY_CONTENT_TYPE_NO_DATA = 0,
478 DISPLAY_CONTENT_TYPE_GRAPHICS = 1,
479 DISPLAY_CONTENT_TYPE_PHOTO = 2,
480 DISPLAY_CONTENT_TYPE_CINEMA = 4,
481 DISPLAY_CONTENT_TYPE_GAME = 8
482};
483
8993dee0
BL		 484enum cm_gamut_adjust_type {
485 CM_GAMUT_ADJUST_TYPE_BYPASS = 0,
486 CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */
487 CM_GAMUT_ADJUST_TYPE_SW /* use adjustments */
488};
489
490struct cm_grph_csc_adjustment {
491 struct fixed31_32 temperature_matrix[12];
492 enum cm_gamut_adjust_type gamut_adjust_type;
493 enum cm_gamut_coef_format gamut_coef_format;
494};
20f2ffe5 495
345429a6 496/* writeback */
9796b713
TD		 497struct dwb_stereo_params {
498 bool stereo_enabled; /* false: normal mode, true: 3D stereo */
499 enum dwb_stereo_type stereo_type; /* indicates stereo format */
500 bool stereo_polarity; /* indicates left eye or right eye comes first in stereo mode */
501 enum dwb_stereo_eye_select stereo_eye_select; /* indicate which eye should be captured */
502};
503
345429a6
HW		 504struct dc_dwb_cnv_params {
505 unsigned int src_width; /* input active width */
506 unsigned int src_height; /* input active height (half-active height in interlaced mode) */
507 unsigned int crop_width; /* cropped window width at cnv output */
508 bool crop_en; /* window cropping enable in cnv */
509 unsigned int crop_height; /* cropped window height at cnv output */
510 unsigned int crop_x; /* cropped window start x value at cnv output */
511 unsigned int crop_y; /* cropped window start y value at cnv output */
512 enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */
8993dee0
BL		 513 enum dwb_out_format fc_out_format; /* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */
514 enum dwb_out_denorm out_denorm_mode;/* dwb output denormalization mode */
515 unsigned int out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */
516 unsigned int out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */
345429a6
HW		 517};
518
519struct dc_dwb_params {
8993dee0
BL		 520 unsigned int dwbscl_black_color; /* must be in FP1.5.10 */
521 unsigned int hdr_mult; /* must be in FP1.6.12 */
522 struct cm_grph_csc_adjustment csc_params;
523 struct dwb_stereo_params stereo_params;
345429a6
HW		 524 struct dc_dwb_cnv_params cnv_params; /* CNV source size and cropping window parameters */
525 unsigned int dest_width; /* Destination width */
526 unsigned int dest_height; /* Destination height */
527 enum dwb_scaler_mode out_format; /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */
528 enum dwb_output_depth output_depth; /* output pixel depth - 8bpc or 10bpc */
529 enum dwb_capture_rate capture_rate; /* controls the frame capture rate */
530 struct scaling_taps scaler_taps; /* Scaling taps */
531 enum dwb_subsample_position subsample_position;
532 struct dc_transfer_func *out_transfer_func;
533};
345429a6 534
4562236b
HW		 535/* audio*/
536
537union audio_sample_rates {
538 struct sample_rates {
539 uint8_t RATE_32:1;
540 uint8_t RATE_44_1:1;
541 uint8_t RATE_48:1;
542 uint8_t RATE_88_2:1;
543 uint8_t RATE_96:1;
544 uint8_t RATE_176_4:1;
545 uint8_t RATE_192:1;
546 } rate;
547
548 uint8_t all;
549};
550
551struct audio_speaker_flags {
5667ff5c
DA		 552 uint32_t FL_FR:1;
553 uint32_t LFE:1;
554 uint32_t FC:1;
555 uint32_t RL_RR:1;
556 uint32_t RC:1;
557 uint32_t FLC_FRC:1;
558 uint32_t RLC_RRC:1;
559 uint32_t SUPPORT_AI:1;
4562236b
HW		 560};
561
562struct audio_speaker_info {
563 uint32_t ALLSPEAKERS:7;
564 uint32_t SUPPORT_AI:1;
565};
566
567
568struct audio_info_flags {
569
570 union {
571
572 struct audio_speaker_flags speaker_flags;
573 struct audio_speaker_info info;
574
575 uint8_t all;
576 };
577};
578
579enum audio_format_code {
580 AUDIO_FORMAT_CODE_FIRST = 1,
581 AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST,
582
583 AUDIO_FORMAT_CODE_AC3,
584 /*Layers 1 & 2 */
585 AUDIO_FORMAT_CODE_MPEG1,
586 /*MPEG1 Layer 3 */
587 AUDIO_FORMAT_CODE_MP3,
588 /*multichannel */
589 AUDIO_FORMAT_CODE_MPEG2,
590 AUDIO_FORMAT_CODE_AAC,
591 AUDIO_FORMAT_CODE_DTS,
592 AUDIO_FORMAT_CODE_ATRAC,
593 AUDIO_FORMAT_CODE_1BITAUDIO,
594 AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS,
595 AUDIO_FORMAT_CODE_DTS_HD,
596 AUDIO_FORMAT_CODE_MAT_MLP,
597 AUDIO_FORMAT_CODE_DST,
598 AUDIO_FORMAT_CODE_WMAPRO,
599 AUDIO_FORMAT_CODE_LAST,
600 AUDIO_FORMAT_CODE_COUNT =
601 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST
602};
603
604struct audio_mode {
605 /* ucData[0] [6:3] */
606 enum audio_format_code format_code;
607 /* ucData[0] [2:0] */
608 uint8_t channel_count;
609 /* ucData[1] */
610 union audio_sample_rates sample_rates;
611 union {
612 /* for LPCM */
613 uint8_t sample_size;
614 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */
615 uint8_t max_bit_rate;
616 /* for Audio Formats 9-15 */
617 uint8_t vendor_specific;
618 };
619};
620
621struct audio_info {
622 struct audio_info_flags flags;
623 uint32_t video_latency;
624 uint32_t audio_latency;
625 uint32_t display_index;
626 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
627 uint32_t manufacture_id;
628 uint32_t product_id;
629 /* PortID used for ContainerID when defined */
630 uint32_t port_id[2];
631 uint32_t mode_count;
632 /* this field must be last in this struct */
633 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT];
634};
3ab4cc65
CL		 635struct audio_check {
636 unsigned int audio_packet_type;
637 unsigned int max_audiosample_rate;
638 unsigned int acat;
639};
98e6436d
AK		 640enum dc_infoframe_type {
641 DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81,
642 DC_HDMI_INFOFRAME_TYPE_AVI = 0x82,
643 DC_HDMI_INFOFRAME_TYPE_SPD = 0x83,
644 DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84,
97bda032 645 DC_DP_INFOFRAME_TYPE_PPS = 0x10,
64ed6a2e
AK		 646};
647
e09b6473
AK		 648struct dc_info_packet {
649 bool valid;
650 uint8_t hb0;
651 uint8_t hb1;
652 uint8_t hb2;
653 uint8_t hb3;
654 uint8_t sb[32];
655};
656
f82c916c
CL		 657struct dc_info_packet_128 {
658 bool valid;
659 uint8_t hb0;
660 uint8_t hb1;
661 uint8_t hb2;
662 uint8_t hb3;
663 uint8_t sb[128];
664};
a6132cb1 665
64ed6a2e
AK		 666#define DC_PLANE_UPDATE_TIMES_MAX 10
667
668struct dc_plane_flip_time {
669 unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX];
670 unsigned int index;
671 unsigned int prev_update_time_in_us;
672};
673
1d496907
KK		 674enum dc_psr_state {
675 PSR_STATE0 = 0x0,
676 PSR_STATE1,
677 PSR_STATE1a,
678 PSR_STATE2,
679 PSR_STATE2a,
680 PSR_STATE3,
681 PSR_STATE3Init,
682 PSR_STATE4,
683 PSR_STATE4a,
684 PSR_STATE4b,
685 PSR_STATE4c,
686 PSR_STATE4d,
687 PSR_STATE5,
688 PSR_STATE5a,
689 PSR_STATE5b,
690 PSR_STATE5c
691};
692
94267b3d
ST		 693struct psr_config {
694 unsigned char psr_version;
695 unsigned int psr_rfb_setup_time;
696 bool psr_exit_link_training_required;
94267b3d
ST		 697 bool psr_frame_capture_indication_req;
698 unsigned int psr_sdp_transmit_line_num_deadline;
5d87a3fd 699 bool allow_smu_optimizations;
175f0971 700 bool allow_multi_disp_optimizations;
94267b3d
ST		 701};
702
9f72f51d
AZ		 703union dmcu_psr_level {
704 struct {
705 unsigned int SKIP_CRC:1;
706 unsigned int SKIP_DP_VID_STREAM_DISABLE:1;
707 unsigned int SKIP_PHY_POWER_DOWN:1;
708 unsigned int SKIP_AUX_ACK_CHECK:1;
709 unsigned int SKIP_CRTC_DISABLE:1;
710 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1;
711 unsigned int SKIP_SMU_NOTIFICATION:1;
712 unsigned int SKIP_AUTO_STATE_ADVANCE:1;
713 unsigned int DISABLE_PSR_ENTRY_ABORT:1;
ee356d8f
CL		 714 unsigned int SKIP_SINGLE_OTG_DISABLE:1;
715 unsigned int RESERVED:22;
9f72f51d
AZ		 716 } bits;
717 unsigned int u32all;
718};
719
720enum physical_phy_id {
721 PHYLD_0,
722 PHYLD_1,
723 PHYLD_2,
724 PHYLD_3,
725 PHYLD_4,
726 PHYLD_5,
727 PHYLD_6,
728 PHYLD_7,
729 PHYLD_8,
730 PHYLD_9,
731 PHYLD_COUNT,
732 PHYLD_UNKNOWN = (-1L)
733};
734
735enum phy_type {
736 PHY_TYPE_UNKNOWN = 1,
737 PHY_TYPE_PCIE_PHY = 2,
738 PHY_TYPE_UNIPHY = 3,
739};
740
741struct psr_context {
742 /* ddc line */
743 enum channel_id channel;
744 /* Transmitter id */
745 enum transmitter transmitterId;
746 /* Engine Id is used for Dig Be source select */
747 enum engine_id engineId;
748 /* Controller Id used for Dig Fe source select */
749 enum controller_id controllerId;
750 /* Pcie or Uniphy */
751 enum phy_type phyType;
752 /* Physical PHY Id used by SMU interpretation */
753 enum physical_phy_id smuPhyId;
754 /* Vertical total pixels from crtc timing.
755 * This is used for static screen detection.
756 * ie. If we want to detect half a frame,
757 * we use this to determine the hyst lines.
758 */
759 unsigned int crtcTimingVerticalTotal;
760 /* PSR supported from panel capabilities and
761 * current display configuration
762 */
763 bool psrSupportedDisplayConfig;
764 /* Whether fast link training is supported by the panel */
765 bool psrExitLinkTrainingRequired;
766 /* If RFB setup time is greater than the total VBLANK time,
767 * it is not possible for the sink to capture the video frame
768 * in the same frame the SDP is sent. In this case,
769 * the frame capture indication bit should be set and an extra
770 * static frame should be transmitted to the sink.
771 */
772 bool psrFrameCaptureIndicationReq;
773 /* Set the last possible line SDP may be transmitted without violating
774 * the RFB setup time or entering the active video frame.
775 */
776 unsigned int sdpTransmitLineNumDeadline;
777 /* The VSync rate in Hz used to calculate the
778 * step size for smooth brightness feature
779 */
5b5abe95 780 unsigned int vsync_rate_hz;
9f72f51d
AZ		 781 unsigned int skipPsrWaitForPllLock;
782 unsigned int numberOfControllers;
783 /* Unused, for future use. To indicate that first changed frame from
784 * state3 shouldn't result in psr_inactive, but rather to perform
785 * an automatic single frame rfb_update.
786 */
787 bool rfb_update_auto_en;
788 /* Number of frame before entering static screen */
789 unsigned int timehyst_frames;
790 /* Partial frames before entering static screen */
791 unsigned int hyst_lines;
792 /* # of repeated AUX transaction attempts to make before
793 * indicating failure to the driver
794 */
795 unsigned int aux_repeats;
796 /* Controls hw blocks to power down during PSR active state */
797 union dmcu_psr_level psr_level;
798 /* Controls additional delay after remote frame capture before
799 * continuing powerd own
800 */
801 unsigned int frame_delay;
5d87a3fd 802 bool allow_smu_optimizations;
175f0971 803 bool allow_multi_disp_optimizations;
9f72f51d
AZ		 804};
805
4562236b
HW		 806struct colorspace_transform {
807 struct fixed31_32 matrix[12];
808 bool enable_remap;
809};
810
7c7f5b15
AG		 811enum i2c_mot_mode {
812 I2C_MOT_UNDEF,
813 I2C_MOT_TRUE,
814 I2C_MOT_FALSE
815};
816
8ab2180f
EB		 817struct AsicStateEx {
818 unsigned int memoryClock;
819 unsigned int displayClock;
820 unsigned int engineClock;
821 unsigned int maxSupportedDppClock;
822 unsigned int dppClock;
823 unsigned int socClock;
824 unsigned int dcfClockDeepSleep;
825 unsigned int fClock;
826 unsigned int phyClock;
827};
828
925f566c
CL		 829
830enum dc_clock_type {
831 DC_CLOCK_TYPE_DISPCLK = 0,
832 DC_CLOCK_TYPE_DPPCLK = 1,
833};
834
835struct dc_clock_config {
836 uint32_t max_clock_khz;
837 uint32_t min_clock_khz;
838 uint32_t bw_requirequired_clock_khz;
839 uint32_t current_clock_khz;/*current clock in use*/
840};
841
97bda032
HW		 842/* DSC DPCD capabilities */
843union dsc_slice_caps1 {
844 struct {
845 uint8_t NUM_SLICES_1 : 1;
846 uint8_t NUM_SLICES_2 : 1;
847 uint8_t RESERVED : 1;
848 uint8_t NUM_SLICES_4 : 1;
849 uint8_t NUM_SLICES_6 : 1;
850 uint8_t NUM_SLICES_8 : 1;
851 uint8_t NUM_SLICES_10 : 1;
852 uint8_t NUM_SLICES_12 : 1;
853 } bits;
854 uint8_t raw;
855};
856
857union dsc_slice_caps2 {
858 struct {
859 uint8_t NUM_SLICES_16 : 1;
860 uint8_t NUM_SLICES_20 : 1;
861 uint8_t NUM_SLICES_24 : 1;
862 uint8_t RESERVED : 5;
863 } bits;
864 uint8_t raw;
865};
866
867union dsc_color_formats {
868 struct {
869 uint8_t RGB : 1;
870 uint8_t YCBCR_444 : 1;
871 uint8_t YCBCR_SIMPLE_422 : 1;
872 uint8_t YCBCR_NATIVE_422 : 1;
873 uint8_t YCBCR_NATIVE_420 : 1;
874 uint8_t RESERVED : 3;
875 } bits;
876 uint8_t raw;
877};
878
879union dsc_color_depth {
880 struct {
881 uint8_t RESERVED1 : 1;
882 uint8_t COLOR_DEPTH_8_BPC : 1;
883 uint8_t COLOR_DEPTH_10_BPC : 1;
884 uint8_t COLOR_DEPTH_12_BPC : 1;
885 uint8_t RESERVED2 : 3;
886 } bits;
887 uint8_t raw;
888};
889
890struct dsc_dec_dpcd_caps {
891 bool is_dsc_supported;
892 uint8_t dsc_version;
893 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */
894 union dsc_slice_caps1 slice_caps1;
895 union dsc_slice_caps2 slice_caps2;
896 int32_t lb_bit_depth;
897 bool is_block_pred_supported;
898 int32_t edp_max_bits_per_pixel; /* Valid only in eDP */
899 union dsc_color_formats color_formats;
900 union dsc_color_depth color_depth;
901 int32_t throughput_mode_0_mps; /* In MPs */
902 int32_t throughput_mode_1_mps; /* In MPs */
903 int32_t max_slice_width;
904 uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */
f446489a
NC		 905
906 /* Extended DSC caps */
907 uint32_t branch_overall_throughput_0_mps; /* In MPs */
908 uint32_t branch_overall_throughput_1_mps; /* In MPs */
909 uint32_t branch_max_line_width;
97bda032 910};
0417df16 911
6224220d
IK		 912struct dc_golden_table {
913 uint16_t dc_golden_table_ver;
914 uint32_t aux_dphy_rx_control0_val;
915 uint32_t aux_dphy_tx_control_val;
916 uint32_t aux_dphy_rx_control1_val;
917 uint32_t dc_gpio_aux_ctrl_0_val;
918 uint32_t dc_gpio_aux_ctrl_1_val;
919 uint32_t dc_gpio_aux_ctrl_2_val;
920 uint32_t dc_gpio_aux_ctrl_3_val;
921 uint32_t dc_gpio_aux_ctrl_4_val;
922 uint32_t dc_gpio_aux_ctrl_5_val;
923};
924
79037324
BL		 925enum dc_gpu_mem_alloc_type {
926 DC_MEM_ALLOC_TYPE_GART,
927 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
928 DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER,
929 DC_MEM_ALLOC_TYPE_AGP
930};
931
1cfbbdde
AK		 932enum dc_psr_version {
933 DC_PSR_VERSION_1 = 0,
934 DC_PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF,
935};
936
4562236b 937#endif /* DC_TYPES_H_ */
Linux 6.x block layer and io_uring tree(s)